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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +02002 * linux/drivers/ide/ppc/pmac.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +02009 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 * Some code taken from drivers/ide/ide-dma.c:
17 *
18 * Copyright (c) 1995-1998 Mark Lord
19 *
20 * TODO: - Use pre-calculated (kauai) timing tables all the time and
21 * get rid of the "rounded" tables used previously, so we have the
22 * same table format for all controllers and can then just have one
23 * big table
24 *
25 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/types.h>
27#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/ide.h>
31#include <linux/notifier.h>
32#include <linux/reboot.h>
33#include <linux/pci.h>
34#include <linux/adb.h>
35#include <linux/pmu.h>
36#include <linux/scatterlist.h>
37
38#include <asm/prom.h>
39#include <asm/io.h>
40#include <asm/dbdma.h>
41#include <asm/ide.h>
42#include <asm/pci-bridge.h>
43#include <asm/machdep.h>
44#include <asm/pmac_feature.h>
45#include <asm/sections.h>
46#include <asm/irq.h>
47
48#ifndef CONFIG_PPC64
49#include <asm/mediabay.h>
50#endif
51
Andrew Morton9e5755b2007-03-03 17:48:54 +010052#include "../ide-timing.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54#undef IDE_PMAC_DEBUG
55
56#define DMA_WAIT_TIMEOUT 50
57
58typedef struct pmac_ide_hwif {
59 unsigned long regbase;
60 int irq;
61 int kind;
62 int aapl_bus_id;
63 unsigned cable_80 : 1;
64 unsigned mediabay : 1;
65 unsigned broken_dma : 1;
66 unsigned broken_dma_warn : 1;
67 struct device_node* node;
68 struct macio_dev *mdev;
69 u32 timings[4];
70 volatile u32 __iomem * *kauai_fcr;
71#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
72 /* Those fields are duplicating what is in hwif. We currently
73 * can't use the hwif ones because of some assumptions that are
74 * beeing done by the generic code about the kind of dma controller
75 * and format of the dma table. This will have to be fixed though.
76 */
77 volatile struct dbdma_regs __iomem * dma_regs;
78 struct dbdma_cmd* dma_table_cpu;
79#endif
80
81} pmac_ide_hwif_t;
82
Jon Loeligeraacaf9b2005-09-17 10:36:54 -050083static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
Linus Torvalds1da177e2005-04-16 15:20:36 -070084static int pmac_ide_count;
85
86enum {
87 controller_ohare, /* OHare based */
88 controller_heathrow, /* Heathrow/Paddington */
89 controller_kl_ata3, /* KeyLargo ATA-3 */
90 controller_kl_ata4, /* KeyLargo ATA-4 */
91 controller_un_ata6, /* UniNorth2 ATA-6 */
92 controller_k2_ata6, /* K2 ATA-6 */
93 controller_sh_ata6, /* Shasta ATA-6 */
94};
95
96static const char* model_name[] = {
97 "OHare ATA", /* OHare based */
98 "Heathrow ATA", /* Heathrow/Paddington */
99 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
100 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
101 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
102 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
103 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
104};
105
106/*
107 * Extra registers, both 32-bit little-endian
108 */
109#define IDE_TIMING_CONFIG 0x200
110#define IDE_INTERRUPT 0x300
111
112/* Kauai (U2) ATA has different register setup */
113#define IDE_KAUAI_PIO_CONFIG 0x200
114#define IDE_KAUAI_ULTRA_CONFIG 0x210
115#define IDE_KAUAI_POLL_CONFIG 0x220
116
117/*
118 * Timing configuration register definitions
119 */
120
121/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
122#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
123#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
124#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
125#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
126
127/* 133Mhz cell, found in shasta.
128 * See comments about 100 Mhz Uninorth 2...
129 * Note that PIO_MASK and MDMA_MASK seem to overlap
130 */
131#define TR_133_PIOREG_PIO_MASK 0xff000fff
132#define TR_133_PIOREG_MDMA_MASK 0x00fff800
133#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
134#define TR_133_UDMAREG_UDMA_EN 0x00000001
135
136/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
137 * this one yet, it appears as a pci device (106b/0033) on uninorth
138 * internal PCI bus and it's clock is controlled like gem or fw. It
139 * appears to be an evolution of keylargo ATA4 with a timing register
140 * extended to 2 32bits registers and a similar DBDMA channel. Other
141 * registers seem to exist but I can't tell much about them.
142 *
143 * So far, I'm using pre-calculated tables for this extracted from
144 * the values used by the MacOS X driver.
145 *
146 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
147 * register controls the UDMA timings. At least, it seems bit 0
148 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
149 * cycle time in units of 10ns. Bits 8..15 are used by I don't
150 * know their meaning yet
151 */
152#define TR_100_PIOREG_PIO_MASK 0xff000fff
153#define TR_100_PIOREG_MDMA_MASK 0x00fff000
154#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
155#define TR_100_UDMAREG_UDMA_EN 0x00000001
156
157
158/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
159 * 40 connector cable and to 4 on 80 connector one.
160 * Clock unit is 15ns (66Mhz)
161 *
162 * 3 Values can be programmed:
163 * - Write data setup, which appears to match the cycle time. They
164 * also call it DIOW setup.
165 * - Ready to pause time (from spec)
166 * - Address setup. That one is weird. I don't see where exactly
167 * it fits in UDMA cycles, I got it's name from an obscure piece
168 * of commented out code in Darwin. They leave it to 0, we do as
169 * well, despite a comment that would lead to think it has a
170 * min value of 45ns.
171 * Apple also add 60ns to the write data setup (or cycle time ?) on
172 * reads.
173 */
174#define TR_66_UDMA_MASK 0xfff00000
175#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
176#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
177#define TR_66_UDMA_ADDRSETUP_SHIFT 29
178#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
179#define TR_66_UDMA_RDY2PAUS_SHIFT 25
180#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
181#define TR_66_UDMA_WRDATASETUP_SHIFT 21
182#define TR_66_MDMA_MASK 0x000ffc00
183#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
184#define TR_66_MDMA_RECOVERY_SHIFT 15
185#define TR_66_MDMA_ACCESS_MASK 0x00007c00
186#define TR_66_MDMA_ACCESS_SHIFT 10
187#define TR_66_PIO_MASK 0x000003ff
188#define TR_66_PIO_RECOVERY_MASK 0x000003e0
189#define TR_66_PIO_RECOVERY_SHIFT 5
190#define TR_66_PIO_ACCESS_MASK 0x0000001f
191#define TR_66_PIO_ACCESS_SHIFT 0
192
193/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
194 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
195 *
196 * The access time and recovery time can be programmed. Some older
197 * Darwin code base limit OHare to 150ns cycle time. I decided to do
198 * the same here fore safety against broken old hardware ;)
199 * The HalfTick bit, when set, adds half a clock (15ns) to the access
200 * time and removes one from recovery. It's not supported on KeyLargo
201 * implementation afaik. The E bit appears to be set for PIO mode 0 and
202 * is used to reach long timings used in this mode.
203 */
204#define TR_33_MDMA_MASK 0x003ff800
205#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
206#define TR_33_MDMA_RECOVERY_SHIFT 16
207#define TR_33_MDMA_ACCESS_MASK 0x0000f800
208#define TR_33_MDMA_ACCESS_SHIFT 11
209#define TR_33_MDMA_HALFTICK 0x00200000
210#define TR_33_PIO_MASK 0x000007ff
211#define TR_33_PIO_E 0x00000400
212#define TR_33_PIO_RECOVERY_MASK 0x000003e0
213#define TR_33_PIO_RECOVERY_SHIFT 5
214#define TR_33_PIO_ACCESS_MASK 0x0000001f
215#define TR_33_PIO_ACCESS_SHIFT 0
216
217/*
218 * Interrupt register definitions
219 */
220#define IDE_INTR_DMA 0x80000000
221#define IDE_INTR_DEVICE 0x40000000
222
223/*
224 * FCR Register on Kauai. Not sure what bit 0x4 is ...
225 */
226#define KAUAI_FCR_UATA_MAGIC 0x00000004
227#define KAUAI_FCR_UATA_RESET_N 0x00000002
228#define KAUAI_FCR_UATA_ENABLE 0x00000001
229
230#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
231
232/* Rounded Multiword DMA timings
233 *
234 * I gave up finding a generic formula for all controller
235 * types and instead, built tables based on timing values
236 * used by Apple in Darwin's implementation.
237 */
238struct mdma_timings_t {
239 int accessTime;
240 int recoveryTime;
241 int cycleTime;
242};
243
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500244struct mdma_timings_t mdma_timings_33[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245{
246 { 240, 240, 480 },
247 { 180, 180, 360 },
248 { 135, 135, 270 },
249 { 120, 120, 240 },
250 { 105, 105, 210 },
251 { 90, 90, 180 },
252 { 75, 75, 150 },
253 { 75, 45, 120 },
254 { 0, 0, 0 }
255};
256
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500257struct mdma_timings_t mdma_timings_33k[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258{
259 { 240, 240, 480 },
260 { 180, 180, 360 },
261 { 150, 150, 300 },
262 { 120, 120, 240 },
263 { 90, 120, 210 },
264 { 90, 90, 180 },
265 { 90, 60, 150 },
266 { 90, 30, 120 },
267 { 0, 0, 0 }
268};
269
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500270struct mdma_timings_t mdma_timings_66[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271{
272 { 240, 240, 480 },
273 { 180, 180, 360 },
274 { 135, 135, 270 },
275 { 120, 120, 240 },
276 { 105, 105, 210 },
277 { 90, 90, 180 },
278 { 90, 75, 165 },
279 { 75, 45, 120 },
280 { 0, 0, 0 }
281};
282
283/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
284struct {
285 int addrSetup; /* ??? */
286 int rdy2pause;
287 int wrDataSetup;
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500288} kl66_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289{
290 { 0, 180, 120 }, /* Mode 0 */
291 { 0, 150, 90 }, /* 1 */
292 { 0, 120, 60 }, /* 2 */
293 { 0, 90, 45 }, /* 3 */
294 { 0, 90, 30 } /* 4 */
295};
296
297/* UniNorth 2 ATA/100 timings */
298struct kauai_timing {
299 int cycle_time;
300 u32 timing_reg;
301};
302
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500303static struct kauai_timing kauai_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304{
305 { 930 , 0x08000fff },
306 { 600 , 0x08000a92 },
307 { 383 , 0x0800060f },
308 { 360 , 0x08000492 },
309 { 330 , 0x0800048f },
310 { 300 , 0x080003cf },
311 { 270 , 0x080003cc },
312 { 240 , 0x0800038b },
313 { 239 , 0x0800030c },
314 { 180 , 0x05000249 },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200315 { 120 , 0x04000148 },
316 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317};
318
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500319static struct kauai_timing kauai_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320{
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
330 { 0 , 0 },
331};
332
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500333static struct kauai_timing kauai_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334{
335 { 120 , 0x000070c0 },
336 { 90 , 0x00005d80 },
337 { 60 , 0x00004a60 },
338 { 45 , 0x00003a50 },
339 { 30 , 0x00002a30 },
340 { 20 , 0x00002921 },
341 { 0 , 0 },
342};
343
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500344static struct kauai_timing shasta_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345{
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200356 { 120 , 0x0400010a },
357 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358};
359
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500360static struct kauai_timing shasta_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361{
362 { 1260 , 0x00fff000 },
363 { 480 , 0x00820800 },
364 { 360 , 0x00820800 },
365 { 270 , 0x00820800 },
366 { 240 , 0x00820800 },
367 { 210 , 0x00820800 },
368 { 180 , 0x00820800 },
369 { 150 , 0x0028b000 },
370 { 120 , 0x001ca000 },
371 { 0 , 0 },
372};
373
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500374static struct kauai_timing shasta_udma133_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375{
376 { 120 , 0x00035901, },
377 { 90 , 0x000348b1, },
378 { 60 , 0x00033881, },
379 { 45 , 0x00033861, },
380 { 30 , 0x00033841, },
381 { 20 , 0x00033031, },
382 { 15 , 0x00033021, },
383 { 0 , 0 },
384};
385
386
387static inline u32
388kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
389{
390 int i;
391
392 for (i=0; table[i].cycle_time; i++)
393 if (cycle_time > table[i+1].cycle_time)
394 return table[i].timing_reg;
Bartlomiej Zolnierkiewicz90a87ea2007-10-13 17:47:48 +0200395 BUG();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 return 0;
397}
398
399/* allow up to 256 DBDMA commands per xfer */
400#define MAX_DCMDS 256
401
402/*
403 * Wait 1s for disk to answer on IDE bus after a hard reset
404 * of the device (via GPIO/FCR).
405 *
406 * Some devices seem to "pollute" the bus even after dropping
407 * the BSY bit (typically some combo drives slave on the UDMA
408 * bus) after a hard reset. Since we hard reset all drives on
409 * KeyLargo ATA66, we have to keep that delay around. I may end
410 * up not hard resetting anymore on these and keep the delay only
411 * for older interfaces instead (we have to reset when coming
412 * from MacOS...) --BenH.
413 */
414#define IDE_WAKEUP_DELAY (1*HZ)
415
416static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
417static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418static void pmac_ide_selectproc(ide_drive_t *drive);
419static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
420
421#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
422
423/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 * N.B. this can't be an initfunc, because the media-bay task can
425 * call ide_[un]register at any time.
426 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500427void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428pmac_ide_init_hwif_ports(hw_regs_t *hw,
429 unsigned long data_port, unsigned long ctrl_port,
430 int *irq)
431{
432 int i, ix;
433
434 if (data_port == 0)
435 return;
436
437 for (ix = 0; ix < MAX_HWIFS; ++ix)
438 if (data_port == pmac_ide[ix].regbase)
439 break;
440
Bartlomiej Zolnierkiewiczd26805f2008-01-25 22:17:07 +0100441 if (ix >= MAX_HWIFS)
442 return; /* not an IDE PMAC interface */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443
444 for (i = 0; i < 8; ++i)
445 hw->io_ports[i] = data_port + i * 0x10;
446 hw->io_ports[8] = data_port + 0x160;
447
448 if (irq != NULL)
449 *irq = pmac_ide[ix].irq;
Benjamin Herrenschmidt22192cc2006-05-20 14:59:53 -0700450
451 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452}
453
454#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
455
456/*
457 * Apply the timings of the proper unit (master/slave) to the shared
458 * timing register when selecting that unit. This version is for
459 * ASICs with a single timing register
460 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500461static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462pmac_ide_selectproc(ide_drive_t *drive)
463{
464 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
465
466 if (pmif == NULL)
467 return;
468
469 if (drive->select.b.unit & 0x01)
470 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
471 else
472 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
473 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
474}
475
476/*
477 * Apply the timings of the proper unit (master/slave) to the shared
478 * timing register when selecting that unit. This version is for
479 * ASICs with a dual timing register (Kauai)
480 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500481static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482pmac_ide_kauai_selectproc(ide_drive_t *drive)
483{
484 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
485
486 if (pmif == NULL)
487 return;
488
489 if (drive->select.b.unit & 0x01) {
490 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
491 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
492 } else {
493 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
494 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
495 }
496 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
497}
498
499/*
500 * Force an update of controller timing values for a given drive
501 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500502static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503pmac_ide_do_update_timings(ide_drive_t *drive)
504{
505 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
506
507 if (pmif == NULL)
508 return;
509
510 if (pmif->kind == controller_sh_ata6 ||
511 pmif->kind == controller_un_ata6 ||
512 pmif->kind == controller_k2_ata6)
513 pmac_ide_kauai_selectproc(drive);
514 else
515 pmac_ide_selectproc(drive);
516}
517
518static void
519pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
520{
521 u32 tmp;
522
523 writeb(value, (void __iomem *) port);
524 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
525}
526
527/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
529 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500530static void
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200531pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532{
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200533 u32 *timings, t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534 unsigned accessTicks, recTicks;
535 unsigned accessTime, recTime;
536 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200537 unsigned int cycle_time;
538
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539 if (pmif == NULL)
540 return;
541
542 /* which drive is it ? */
543 timings = &pmif->timings[drive->select.b.unit & 0x01];
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200544 t = *timings;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200546 cycle_time = ide_pio_cycle_time(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547
548 switch (pmif->kind) {
549 case controller_sh_ata6: {
550 /* 133Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200551 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200552 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 break;
554 }
555 case controller_un_ata6:
556 case controller_k2_ata6: {
557 /* 100Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200558 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200559 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 break;
561 }
562 case controller_kl_ata4:
563 /* 66Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200564 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 - ide_pio_timings[pio].setup_time;
566 recTime = max(recTime, 150U);
567 accessTime = ide_pio_timings[pio].active_time;
568 accessTime = max(accessTime, 150U);
569 accessTicks = SYSCLK_TICKS_66(accessTime);
570 accessTicks = min(accessTicks, 0x1fU);
571 recTicks = SYSCLK_TICKS_66(recTime);
572 recTicks = min(recTicks, 0x1fU);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200573 t = (t & ~TR_66_PIO_MASK) |
574 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
575 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576 break;
577 default: {
578 /* 33Mhz cell */
579 int ebit = 0;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200580 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581 - ide_pio_timings[pio].setup_time;
582 recTime = max(recTime, 150U);
583 accessTime = ide_pio_timings[pio].active_time;
584 accessTime = max(accessTime, 150U);
585 accessTicks = SYSCLK_TICKS(accessTime);
586 accessTicks = min(accessTicks, 0x1fU);
587 accessTicks = max(accessTicks, 4U);
588 recTicks = SYSCLK_TICKS(recTime);
589 recTicks = min(recTicks, 0x1fU);
590 recTicks = max(recTicks, 5U) - 4;
591 if (recTicks > 9) {
592 recTicks--; /* guess, but it's only for PIO0, so... */
593 ebit = 1;
594 }
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200595 t = (t & ~TR_33_PIO_MASK) |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
597 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
598 if (ebit)
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200599 t |= TR_33_PIO_E;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600 break;
601 }
602 }
603
604#ifdef IDE_PMAC_DEBUG
605 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
606 drive->name, pio, *timings);
607#endif
608
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200609 *timings = t;
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200610 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611}
612
613#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
614
615/*
616 * Calculate KeyLargo ATA/66 UDMA timings
617 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500618static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619set_timings_udma_ata4(u32 *timings, u8 speed)
620{
621 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
622
623 if (speed > XFER_UDMA_4)
624 return 1;
625
626 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
627 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
628 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
629
630 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
631 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
632 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
633 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
634 TR_66_UDMA_EN;
635#ifdef IDE_PMAC_DEBUG
636 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
637 speed & 0xf, *timings);
638#endif
639
640 return 0;
641}
642
643/*
644 * Calculate Kauai ATA/100 UDMA timings
645 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500646static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
648{
649 struct ide_timing *t = ide_timing_find_mode(speed);
650 u32 tr;
651
652 if (speed > XFER_UDMA_5 || t == NULL)
653 return 1;
654 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
656 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
657
658 return 0;
659}
660
661/*
662 * Calculate Shasta ATA/133 UDMA timings
663 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500664static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
666{
667 struct ide_timing *t = ide_timing_find_mode(speed);
668 u32 tr;
669
670 if (speed > XFER_UDMA_6 || t == NULL)
671 return 1;
672 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
674 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
675
676 return 0;
677}
678
679/*
680 * Calculate MDMA timings for all cells
681 */
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200682static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200684 u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685{
686 int cycleTime, accessTime = 0, recTime = 0;
687 unsigned accessTicks, recTicks;
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200688 struct hd_driveid *id = drive->id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689 struct mdma_timings_t* tm = NULL;
690 int i;
691
692 /* Get default cycle time for mode */
693 switch(speed & 0xf) {
694 case 0: cycleTime = 480; break;
695 case 1: cycleTime = 150; break;
696 case 2: cycleTime = 120; break;
697 default:
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200698 BUG();
699 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700 }
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200701
702 /* Check if drive provides explicit DMA cycle time */
703 if ((id->field_valid & 2) && id->eide_dma_time)
704 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
705
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706 /* OHare limits according to some old Apple sources */
707 if ((intf_type == controller_ohare) && (cycleTime < 150))
708 cycleTime = 150;
709 /* Get the proper timing array for this controller */
710 switch(intf_type) {
711 case controller_sh_ata6:
712 case controller_un_ata6:
713 case controller_k2_ata6:
714 break;
715 case controller_kl_ata4:
716 tm = mdma_timings_66;
717 break;
718 case controller_kl_ata3:
719 tm = mdma_timings_33k;
720 break;
721 default:
722 tm = mdma_timings_33;
723 break;
724 }
725 if (tm != NULL) {
726 /* Lookup matching access & recovery times */
727 i = -1;
728 for (;;) {
729 if (tm[i+1].cycleTime < cycleTime)
730 break;
731 i++;
732 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733 cycleTime = tm[i].cycleTime;
734 accessTime = tm[i].accessTime;
735 recTime = tm[i].recoveryTime;
736
737#ifdef IDE_PMAC_DEBUG
738 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
739 drive->name, cycleTime, accessTime, recTime);
740#endif
741 }
742 switch(intf_type) {
743 case controller_sh_ata6: {
744 /* 133Mhz cell */
745 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
747 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
748 }
749 case controller_un_ata6:
750 case controller_k2_ata6: {
751 /* 100Mhz cell */
752 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
754 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
755 }
756 break;
757 case controller_kl_ata4:
758 /* 66Mhz cell */
759 accessTicks = SYSCLK_TICKS_66(accessTime);
760 accessTicks = min(accessTicks, 0x1fU);
761 accessTicks = max(accessTicks, 0x1U);
762 recTicks = SYSCLK_TICKS_66(recTime);
763 recTicks = min(recTicks, 0x1fU);
764 recTicks = max(recTicks, 0x3U);
765 /* Clear out mdma bits and disable udma */
766 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
767 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
768 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
769 break;
770 case controller_kl_ata3:
771 /* 33Mhz cell on KeyLargo */
772 accessTicks = SYSCLK_TICKS(accessTime);
773 accessTicks = max(accessTicks, 1U);
774 accessTicks = min(accessTicks, 0x1fU);
775 accessTime = accessTicks * IDE_SYSCLK_NS;
776 recTicks = SYSCLK_TICKS(recTime);
777 recTicks = max(recTicks, 1U);
778 recTicks = min(recTicks, 0x1fU);
779 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
780 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
781 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
782 break;
783 default: {
784 /* 33Mhz cell on others */
785 int halfTick = 0;
786 int origAccessTime = accessTime;
787 int origRecTime = recTime;
788
789 accessTicks = SYSCLK_TICKS(accessTime);
790 accessTicks = max(accessTicks, 1U);
791 accessTicks = min(accessTicks, 0x1fU);
792 accessTime = accessTicks * IDE_SYSCLK_NS;
793 recTicks = SYSCLK_TICKS(recTime);
794 recTicks = max(recTicks, 2U) - 1;
795 recTicks = min(recTicks, 0x1fU);
796 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
797 if ((accessTicks > 1) &&
798 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
799 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
800 halfTick = 1;
801 accessTicks--;
802 }
803 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
804 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
805 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
806 if (halfTick)
807 *timings |= TR_33_MDMA_HALFTICK;
808 }
809 }
810#ifdef IDE_PMAC_DEBUG
811 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
812 drive->name, speed & 0xf, *timings);
813#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814}
815#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
816
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200817static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818{
819 int unit = (drive->select.b.unit & 0x01);
820 int ret = 0;
821 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200822 u32 *timings, *timings2, tl[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824 timings = &pmif->timings[unit];
825 timings2 = &pmif->timings[unit+2];
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200826
827 /* Copy timings to local image */
828 tl[0] = *timings;
829 tl[1] = *timings2;
830
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +0100832 if (speed >= XFER_UDMA_0) {
833 if (pmif->kind == controller_kl_ata4)
834 ret = set_timings_udma_ata4(&tl[0], speed);
835 else if (pmif->kind == controller_un_ata6
836 || pmif->kind == controller_k2_ata6)
837 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
838 else if (pmif->kind == controller_sh_ata6)
839 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
840 else
841 ret = -1;
842 } else
843 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 if (ret)
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200846 return;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200847
848 /* Apply timings to controller */
849 *timings = tl[0];
850 *timings2 = tl[1];
851
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853}
854
855/*
856 * Blast some well known "safe" values to the timing registers at init or
857 * wakeup from sleep time, before we do real calculation
858 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500859static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860sanitize_timings(pmac_ide_hwif_t *pmif)
861{
862 unsigned int value, value2 = 0;
863
864 switch(pmif->kind) {
865 case controller_sh_ata6:
866 value = 0x0a820c97;
867 value2 = 0x00033031;
868 break;
869 case controller_un_ata6:
870 case controller_k2_ata6:
871 value = 0x08618a92;
872 value2 = 0x00002921;
873 break;
874 case controller_kl_ata4:
875 value = 0x0008438c;
876 break;
877 case controller_kl_ata3:
878 value = 0x00084526;
879 break;
880 case controller_heathrow:
881 case controller_ohare:
882 default:
883 value = 0x00074526;
884 break;
885 }
886 pmif->timings[0] = pmif->timings[1] = value;
887 pmif->timings[2] = pmif->timings[3] = value2;
888}
889
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500890unsigned long
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891pmac_ide_get_base(int index)
892{
893 return pmac_ide[index].regbase;
894}
895
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500896int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897pmac_ide_check_base(unsigned long base)
898{
899 int ix;
900
901 for (ix = 0; ix < MAX_HWIFS; ++ix)
902 if (base == pmac_ide[ix].regbase)
903 return ix;
904 return -1;
905}
906
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500907int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908pmac_ide_get_irq(unsigned long base)
909{
910 int ix;
911
912 for (ix = 0; ix < MAX_HWIFS; ++ix)
913 if (base == pmac_ide[ix].regbase)
914 return pmac_ide[ix].irq;
915 return 0;
916}
917
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500918static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919
920dev_t __init
921pmac_find_ide_boot(char *bootdevice, int n)
922{
923 int i;
924
925 /*
926 * Look through the list of IDE interfaces for this one.
927 */
928 for (i = 0; i < pmac_ide_count; ++i) {
929 char *name;
930 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
931 continue;
932 name = pmac_ide[i].node->full_name;
933 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
934 /* XXX should cope with the 2nd drive as well... */
935 return MKDEV(ide_majors[i], 0);
936 }
937 }
938
939 return 0;
940}
941
942/* Suspend call back, should be called after the child devices
943 * have actually been suspended
944 */
945static int
946pmac_ide_do_suspend(ide_hwif_t *hwif)
947{
948 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
949
950 /* We clear the timings */
951 pmif->timings[0] = 0;
952 pmif->timings[1] = 0;
953
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700954 disable_irq(pmif->irq);
955
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 /* The media bay will handle itself just fine */
957 if (pmif->mediabay)
958 return 0;
959
960 /* Kauai has bus control FCRs directly here */
961 if (pmif->kauai_fcr) {
962 u32 fcr = readl(pmif->kauai_fcr);
963 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
964 writel(fcr, pmif->kauai_fcr);
965 }
966
967 /* Disable the bus on older machines and the cell on kauai */
968 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
969 0);
970
971 return 0;
972}
973
974/* Resume call back, should be called before the child devices
975 * are resumed
976 */
977static int
978pmac_ide_do_resume(ide_hwif_t *hwif)
979{
980 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
981
982 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
983 if (!pmif->mediabay) {
984 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
985 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
986 msleep(10);
987 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988
989 /* Kauai has it different */
990 if (pmif->kauai_fcr) {
991 u32 fcr = readl(pmif->kauai_fcr);
992 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
993 writel(fcr, pmif->kauai_fcr);
994 }
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700995
996 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997 }
998
999 /* Sanitize drive timings */
1000 sanitize_timings(pmif);
1001
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -07001002 enable_irq(pmif->irq);
1003
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 return 0;
1005}
1006
1007/*
1008 * Setup, register & probe an IDE channel driven by this driver, this is
1009 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1010 * that ends up beeing free of any device is not kept around by this driver
1011 * (it is kept in 2.4). This introduce an interface numbering change on some
1012 * rare machines unfortunately, but it's better this way.
1013 */
1014static int
1015pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1016{
1017 struct device_node *np = pmif->node;
Jeremy Kerr018a3d12006-07-12 15:40:29 +10001018 const int *bidp;
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001019 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
Bartlomiej Zolnierkiewicz9239b332007-10-20 00:32:33 +02001020 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021
1022 pmif->cable_80 = 0;
1023 pmif->broken_dma = pmif->broken_dma_warn = 0;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001024 if (of_device_is_compatible(np, "shasta-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025 pmif->kind = controller_sh_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001026 else if (of_device_is_compatible(np, "kauai-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027 pmif->kind = controller_un_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001028 else if (of_device_is_compatible(np, "K2-UATA"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029 pmif->kind = controller_k2_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001030 else if (of_device_is_compatible(np, "keylargo-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031 if (strcmp(np->name, "ata-4") == 0)
1032 pmif->kind = controller_kl_ata4;
1033 else
1034 pmif->kind = controller_kl_ata3;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001035 } else if (of_device_is_compatible(np, "heathrow-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036 pmif->kind = controller_heathrow;
1037 else {
1038 pmif->kind = controller_ohare;
1039 pmif->broken_dma = 1;
1040 }
1041
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10001042 bidp = of_get_property(np, "AAPL,bus-id", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001043 pmif->aapl_bus_id = bidp ? *bidp : 0;
1044
1045 /* Get cable type from device-tree */
1046 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1047 || pmif->kind == controller_k2_ata6
1048 || pmif->kind == controller_sh_ata6) {
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10001049 const char* cable = of_get_property(np, "cable-type", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050 if (cable && !strncmp(cable, "80-", 3))
1051 pmif->cable_80 = 1;
1052 }
1053 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1054 * they have a 80 conductor cable, this seem to be always the case unless
1055 * the user mucked around
1056 */
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001057 if (of_device_is_compatible(np, "K2-UATA") ||
1058 of_device_is_compatible(np, "shasta-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059 pmif->cable_80 = 1;
1060
1061 /* On Kauai-type controllers, we make sure the FCR is correct */
1062 if (pmif->kauai_fcr)
1063 writel(KAUAI_FCR_UATA_MAGIC |
1064 KAUAI_FCR_UATA_RESET_N |
1065 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1066
1067 pmif->mediabay = 0;
1068
1069 /* Make sure we have sane timings */
1070 sanitize_timings(pmif);
1071
1072#ifndef CONFIG_PPC64
1073 /* XXX FIXME: Media bay stuff need re-organizing */
1074 if (np->parent && np->parent->name
1075 && strcasecmp(np->parent->name, "media-bay") == 0) {
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001076#ifdef CONFIG_PMAC_MEDIABAY
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001078#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079 pmif->mediabay = 1;
1080 if (!bidp)
1081 pmif->aapl_bus_id = 1;
1082 } else if (pmif->kind == controller_ohare) {
1083 /* The code below is having trouble on some ohare machines
1084 * (timing related ?). Until I can put my hand on one of these
1085 * units, I keep the old way
1086 */
1087 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1088 } else
1089#endif
1090 {
1091 /* This is necessary to enable IDE when net-booting */
1092 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1093 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1094 msleep(10);
1095 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1096 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1097 }
1098
1099 /* Setup MMIO ops */
1100 default_hwif_mmiops(hwif);
1101 hwif->OUTBSYNC = pmac_outbsync;
1102
1103 /* Tell common code _not_ to mess with resources */
Bartlomiej Zolnierkiewicz2ad1e552007-02-17 02:40:25 +01001104 hwif->mmio = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 hwif->hwif_data = pmif;
Bartlomiej Zolnierkiewicz9239b332007-10-20 00:32:33 +02001106 memset(&hw, 0, sizeof(hw));
1107 pmac_ide_init_hwif_ports(&hw, pmif->regbase, 0, &hwif->irq);
1108 memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109 hwif->chipset = ide_pmac;
1110 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1111 hwif->hold = pmif->mediabay;
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +02001112 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113 hwif->drives[0].unmask = 1;
1114 hwif->drives[1].unmask = 1;
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +02001115 hwif->drives[0].autotune = IDE_TUNE_AUTO;
1116 hwif->drives[1].autotune = IDE_TUNE_AUTO;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001117 hwif->host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
Bartlomiej Zolnierkiewicz03644cd2007-11-13 22:09:15 +01001118 IDE_HFLAG_PIO_NO_DOWNGRADE |
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001119 IDE_HFLAG_POST_SET_MODE;
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001120 hwif->pio_mask = ATA_PIO4;
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +02001121 hwif->set_pio_mode = pmac_ide_set_pio_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122 if (pmif->kind == controller_un_ata6
1123 || pmif->kind == controller_k2_ata6
1124 || pmif->kind == controller_sh_ata6)
1125 hwif->selectproc = pmac_ide_kauai_selectproc;
1126 else
1127 hwif->selectproc = pmac_ide_selectproc;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001128 hwif->set_dma_mode = pmac_ide_set_dma_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1131 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1132 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1133
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001134#ifdef CONFIG_PMAC_MEDIABAY
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1136 hwif->noprobe = 0;
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001137#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001138
1139 hwif->sg_max_nents = MAX_DCMDS;
1140
1141#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1142 /* has a DBDMA controller channel */
1143 if (pmif->dma_regs)
1144 pmac_ide_setup_dma(pmif, hwif);
1145#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1146
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001147 idx[0] = hwif->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001149 ide_device_add(idx);
Bartlomiej Zolnierkiewicz5cbf79c2007-05-10 00:01:11 +02001150
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151 return 0;
1152}
1153
1154/*
1155 * Attach to a macio probed interface
1156 */
1157static int __devinit
Jeff Mahoney5e655772005-07-06 15:44:41 -04001158pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159{
1160 void __iomem *base;
1161 unsigned long regbase;
1162 int irq;
1163 ide_hwif_t *hwif;
1164 pmac_ide_hwif_t *pmif;
1165 int i, rc;
1166
1167 i = 0;
1168 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1169 || pmac_ide[i].node != NULL))
1170 ++i;
1171 if (i >= MAX_HWIFS) {
1172 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1173 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1174 return -ENODEV;
1175 }
1176
1177 pmif = &pmac_ide[i];
1178 hwif = &ide_hwifs[i];
1179
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +11001180 if (macio_resource_count(mdev) == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 printk(KERN_WARNING "ide%d: no address for %s\n",
1182 i, mdev->ofdev.node->full_name);
1183 return -ENXIO;
1184 }
1185
1186 /* Request memory resource for IO ports */
1187 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1188 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1189 return -EBUSY;
1190 }
1191
1192 /* XXX This is bogus. Should be fixed in the registry by checking
1193 * the kind of host interrupt controller, a bit like gatwick
1194 * fixes in irq.c. That works well enough for the single case
1195 * where that happens though...
1196 */
1197 if (macio_irq_count(mdev) == 0) {
1198 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1199 i, mdev->ofdev.node->full_name);
Benjamin Herrenschmidt69917c22006-09-22 12:56:30 +10001200 irq = irq_create_mapping(NULL, 13);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201 } else
1202 irq = macio_irq(mdev, 0);
1203
1204 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1205 regbase = (unsigned long) base;
1206
1207 hwif->pci_dev = mdev->bus->pdev;
1208 hwif->gendev.parent = &mdev->ofdev.dev;
1209
1210 pmif->mdev = mdev;
1211 pmif->node = mdev->ofdev.node;
1212 pmif->regbase = regbase;
1213 pmif->irq = irq;
1214 pmif->kauai_fcr = NULL;
1215#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1216 if (macio_resource_count(mdev) >= 2) {
1217 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1218 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1219 else
1220 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1221 } else
1222 pmif->dma_regs = NULL;
1223#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1224 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1225
1226 rc = pmac_ide_setup_device(pmif, hwif);
1227 if (rc != 0) {
1228 /* The inteface is released to the common IDE layer */
1229 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1230 iounmap(base);
1231 if (pmif->dma_regs)
1232 iounmap(pmif->dma_regs);
1233 memset(pmif, 0, sizeof(*pmif));
1234 macio_release_resource(mdev, 0);
1235 if (pmif->dma_regs)
1236 macio_release_resource(mdev, 1);
1237 }
1238
1239 return rc;
1240}
1241
1242static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001243pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244{
1245 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1246 int rc = 0;
1247
David Brownell8b4b8a22006-08-14 23:11:03 -07001248 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1249 && mesg.event == PM_EVENT_SUSPEND) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250 rc = pmac_ide_do_suspend(hwif);
1251 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001252 mdev->ofdev.dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253 }
1254
1255 return rc;
1256}
1257
1258static int
1259pmac_ide_macio_resume(struct macio_dev *mdev)
1260{
1261 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1262 int rc = 0;
1263
Pavel Machekca078ba2005-09-03 15:56:57 -07001264 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001265 rc = pmac_ide_do_resume(hwif);
1266 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001267 mdev->ofdev.dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268 }
1269
1270 return rc;
1271}
1272
1273/*
1274 * Attach to a PCI probed interface
1275 */
1276static int __devinit
1277pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1278{
1279 ide_hwif_t *hwif;
1280 struct device_node *np;
1281 pmac_ide_hwif_t *pmif;
1282 void __iomem *base;
1283 unsigned long rbase, rlen;
1284 int i, rc;
1285
1286 np = pci_device_to_OF_node(pdev);
1287 if (np == NULL) {
1288 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1289 return -ENODEV;
1290 }
1291 i = 0;
1292 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1293 || pmac_ide[i].node != NULL))
1294 ++i;
1295 if (i >= MAX_HWIFS) {
1296 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1297 printk(KERN_ERR " %s\n", np->full_name);
1298 return -ENODEV;
1299 }
1300
1301 pmif = &pmac_ide[i];
1302 hwif = &ide_hwifs[i];
1303
1304 if (pci_enable_device(pdev)) {
1305 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1306 i, np->full_name);
1307 return -ENXIO;
1308 }
1309 pci_set_master(pdev);
1310
1311 if (pci_request_regions(pdev, "Kauai ATA")) {
1312 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1313 i, np->full_name);
1314 return -ENXIO;
1315 }
1316
1317 hwif->pci_dev = pdev;
1318 hwif->gendev.parent = &pdev->dev;
1319 pmif->mdev = NULL;
1320 pmif->node = np;
1321
1322 rbase = pci_resource_start(pdev, 0);
1323 rlen = pci_resource_len(pdev, 0);
1324
1325 base = ioremap(rbase, rlen);
1326 pmif->regbase = (unsigned long) base + 0x2000;
1327#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1328 pmif->dma_regs = base + 0x1000;
1329#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1330 pmif->kauai_fcr = base;
1331 pmif->irq = pdev->irq;
1332
1333 pci_set_drvdata(pdev, hwif);
1334
1335 rc = pmac_ide_setup_device(pmif, hwif);
1336 if (rc != 0) {
1337 /* The inteface is released to the common IDE layer */
1338 pci_set_drvdata(pdev, NULL);
1339 iounmap(base);
1340 memset(pmif, 0, sizeof(*pmif));
1341 pci_release_regions(pdev);
1342 }
1343
1344 return rc;
1345}
1346
1347static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001348pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349{
1350 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1351 int rc = 0;
1352
David Brownell8b4b8a22006-08-14 23:11:03 -07001353 if (mesg.event != pdev->dev.power.power_state.event
1354 && mesg.event == PM_EVENT_SUSPEND) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355 rc = pmac_ide_do_suspend(hwif);
1356 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001357 pdev->dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358 }
1359
1360 return rc;
1361}
1362
1363static int
1364pmac_ide_pci_resume(struct pci_dev *pdev)
1365{
1366 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1367 int rc = 0;
1368
Pavel Machekca078ba2005-09-03 15:56:57 -07001369 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 rc = pmac_ide_do_resume(hwif);
1371 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001372 pdev->dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373 }
1374
1375 return rc;
1376}
1377
Jeff Mahoney5e655772005-07-06 15:44:41 -04001378static struct of_device_id pmac_ide_macio_match[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001379{
1380 {
1381 .name = "IDE",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382 },
1383 {
1384 .name = "ATA",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385 },
1386 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001387 .type = "ide",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388 },
1389 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390 .type = "ata",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001391 },
1392 {},
1393};
1394
1395static struct macio_driver pmac_ide_macio_driver =
1396{
1397 .name = "ide-pmac",
1398 .match_table = pmac_ide_macio_match,
1399 .probe = pmac_ide_macio_attach,
1400 .suspend = pmac_ide_macio_suspend,
1401 .resume = pmac_ide_macio_resume,
1402};
1403
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001404static const struct pci_device_id pmac_ide_pci_match[] = {
1405 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1406 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1407 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1408 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1409 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
Benjamin Herrenschmidt71e4eda2007-10-06 18:52:27 +10001410 {},
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411};
1412
1413static struct pci_driver pmac_ide_pci_driver = {
1414 .name = "ide-pmac",
1415 .id_table = pmac_ide_pci_match,
1416 .probe = pmac_ide_pci_attach,
1417 .suspend = pmac_ide_pci_suspend,
1418 .resume = pmac_ide_pci_resume,
1419};
1420MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1421
Andrew Morton9e5755b2007-03-03 17:48:54 +01001422int __init pmac_ide_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423{
Andrew Morton9e5755b2007-03-03 17:48:54 +01001424 int error;
1425
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001426 if (!machine_is(powermac))
Andrew Morton9e5755b2007-03-03 17:48:54 +01001427 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001428
1429#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
Andrew Morton9e5755b2007-03-03 17:48:54 +01001430 error = pci_register_driver(&pmac_ide_pci_driver);
1431 if (error)
1432 goto out;
1433 error = macio_register_driver(&pmac_ide_macio_driver);
1434 if (error) {
1435 pci_unregister_driver(&pmac_ide_pci_driver);
1436 goto out;
1437 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438#else
Andrew Morton9e5755b2007-03-03 17:48:54 +01001439 error = macio_register_driver(&pmac_ide_macio_driver);
1440 if (error)
1441 goto out;
1442 error = pci_register_driver(&pmac_ide_pci_driver);
1443 if (error) {
1444 macio_unregister_driver(&pmac_ide_macio_driver);
1445 goto out;
1446 }
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001447#endif
Andrew Morton9e5755b2007-03-03 17:48:54 +01001448out:
1449 return error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450}
1451
1452#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1453
1454/*
1455 * pmac_ide_build_dmatable builds the DBDMA command list
1456 * for a transfer and sets the DBDMA channel to point to it.
1457 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001458static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1460{
1461 struct dbdma_cmd *table;
1462 int i, count = 0;
1463 ide_hwif_t *hwif = HWIF(drive);
1464 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1465 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1466 struct scatterlist *sg;
1467 int wr = (rq_data_dir(rq) == WRITE);
1468
1469 /* DMA table is already aligned */
1470 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1471
1472 /* Make sure DMA controller is stopped (necessary ?) */
1473 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1474 while (readl(&dma->status) & RUN)
1475 udelay(1);
1476
1477 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1478
1479 if (!i)
1480 return 0;
1481
1482 /* Build DBDMA commands list */
1483 sg = hwif->sg_table;
1484 while (i && sg_dma_len(sg)) {
1485 u32 cur_addr;
1486 u32 cur_len;
1487
1488 cur_addr = sg_dma_address(sg);
1489 cur_len = sg_dma_len(sg);
1490
1491 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1492 if (pmif->broken_dma_warn == 0) {
Joe Perchesaca38a52007-11-27 21:35:55 +01001493 printk(KERN_WARNING "%s: DMA on non aligned address, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494 "switching to PIO on Ohare chipset\n", drive->name);
1495 pmif->broken_dma_warn = 1;
1496 }
1497 goto use_pio_instead;
1498 }
1499 while (cur_len) {
1500 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1501
1502 if (count++ >= MAX_DCMDS) {
1503 printk(KERN_WARNING "%s: DMA table too small\n",
1504 drive->name);
1505 goto use_pio_instead;
1506 }
1507 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1508 st_le16(&table->req_count, tc);
1509 st_le32(&table->phy_addr, cur_addr);
1510 table->cmd_dep = 0;
1511 table->xfer_status = 0;
1512 table->res_count = 0;
1513 cur_addr += tc;
1514 cur_len -= tc;
1515 ++table;
1516 }
Jens Axboe55c16a72007-07-25 08:13:56 +02001517 sg = sg_next(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518 i--;
1519 }
1520
1521 /* convert the last command to an input/output last command */
1522 if (count) {
1523 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1524 /* add the stop command to the end of the list */
1525 memset(table, 0, sizeof(struct dbdma_cmd));
1526 st_le16(&table->command, DBDMA_STOP);
1527 mb();
1528 writel(hwif->dmatable_dma, &dma->cmdptr);
1529 return 1;
1530 }
1531
1532 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1533 use_pio_instead:
1534 pci_unmap_sg(hwif->pci_dev,
1535 hwif->sg_table,
1536 hwif->sg_nents,
1537 hwif->sg_dma_direction);
1538 return 0; /* revert to PIO for this request */
1539}
1540
1541/* Teardown mappings after DMA has completed. */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001542static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543pmac_ide_destroy_dmatable (ide_drive_t *drive)
1544{
1545 ide_hwif_t *hwif = drive->hwif;
1546 struct pci_dev *dev = HWIF(drive)->pci_dev;
1547 struct scatterlist *sg = hwif->sg_table;
1548 int nents = hwif->sg_nents;
1549
1550 if (nents) {
1551 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1552 hwif->sg_nents = 0;
1553 }
1554}
1555
1556/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1558 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1559 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001560static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561pmac_ide_dma_setup(ide_drive_t *drive)
1562{
1563 ide_hwif_t *hwif = HWIF(drive);
1564 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1565 struct request *rq = HWGROUP(drive)->rq;
1566 u8 unit = (drive->select.b.unit & 0x01);
1567 u8 ata4;
1568
1569 if (pmif == NULL)
1570 return 1;
1571 ata4 = (pmif->kind == controller_kl_ata4);
1572
1573 if (!pmac_ide_build_dmatable(drive, rq)) {
1574 ide_map_sg(drive, rq);
1575 return 1;
1576 }
1577
1578 /* Apple adds 60ns to wrDataSetup on reads */
1579 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1580 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1581 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1582 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1583 }
1584
1585 drive->waiting_for_dma = 1;
1586
1587 return 0;
1588}
1589
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001590static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1592{
1593 /* issue cmd to drive */
1594 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1595}
1596
1597/*
1598 * Kick the DMA controller into life after the DMA command has been issued
1599 * to the drive.
1600 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001601static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602pmac_ide_dma_start(ide_drive_t *drive)
1603{
1604 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1605 volatile struct dbdma_regs __iomem *dma;
1606
1607 dma = pmif->dma_regs;
1608
1609 writel((RUN << 16) | RUN, &dma->control);
1610 /* Make sure it gets to the controller right now */
1611 (void)readl(&dma->control);
1612}
1613
1614/*
1615 * After a DMA transfer, make sure the controller is stopped
1616 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001617static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001618pmac_ide_dma_end (ide_drive_t *drive)
1619{
1620 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1621 volatile struct dbdma_regs __iomem *dma;
1622 u32 dstat;
1623
1624 if (pmif == NULL)
1625 return 0;
1626 dma = pmif->dma_regs;
1627
1628 drive->waiting_for_dma = 0;
1629 dstat = readl(&dma->status);
1630 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1631 pmac_ide_destroy_dmatable(drive);
1632 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1633 * in theory, but with ATAPI decices doing buffer underruns, that would
1634 * cause us to disable DMA, which isn't what we want
1635 */
1636 return (dstat & (RUN|DEAD)) != RUN;
1637}
1638
1639/*
1640 * Check out that the interrupt we got was for us. We can't always know this
1641 * for sure with those Apple interfaces (well, we could on the recent ones but
1642 * that's not implemented yet), on the other hand, we don't have shared interrupts
1643 * so it's not really a problem
1644 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001645static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646pmac_ide_dma_test_irq (ide_drive_t *drive)
1647{
1648 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1649 volatile struct dbdma_regs __iomem *dma;
1650 unsigned long status, timeout;
1651
1652 if (pmif == NULL)
1653 return 0;
1654 dma = pmif->dma_regs;
1655
1656 /* We have to things to deal with here:
1657 *
1658 * - The dbdma won't stop if the command was started
1659 * but completed with an error without transferring all
1660 * datas. This happens when bad blocks are met during
1661 * a multi-block transfer.
1662 *
1663 * - The dbdma fifo hasn't yet finished flushing to
1664 * to system memory when the disk interrupt occurs.
1665 *
1666 */
1667
1668 /* If ACTIVE is cleared, the STOP command have passed and
1669 * transfer is complete.
1670 */
1671 status = readl(&dma->status);
1672 if (!(status & ACTIVE))
1673 return 1;
1674 if (!drive->waiting_for_dma)
1675 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1676 called while not waiting\n", HWIF(drive)->index);
1677
1678 /* If dbdma didn't execute the STOP command yet, the
1679 * active bit is still set. We consider that we aren't
1680 * sharing interrupts (which is hopefully the case with
1681 * those controllers) and so we just try to flush the
1682 * channel for pending data in the fifo
1683 */
1684 udelay(1);
1685 writel((FLUSH << 16) | FLUSH, &dma->control);
1686 timeout = 0;
1687 for (;;) {
1688 udelay(1);
1689 status = readl(&dma->status);
1690 if ((status & FLUSH) == 0)
1691 break;
1692 if (++timeout > 100) {
1693 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1694 timeout flushing channel\n", HWIF(drive)->index);
1695 break;
1696 }
1697 }
1698 return 1;
1699}
1700
Bartlomiej Zolnierkiewicz7469aaf2007-02-17 02:40:26 +01001701static void pmac_ide_dma_host_off(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001703}
1704
Andrew Morton9e5755b2007-03-03 17:48:54 +01001705static void pmac_ide_dma_host_on(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001706{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001707}
1708
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001709static void
1710pmac_ide_dma_lost_irq (ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001711{
1712 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1713 volatile struct dbdma_regs __iomem *dma;
1714 unsigned long status;
1715
1716 if (pmif == NULL)
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001717 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718 dma = pmif->dma_regs;
1719
1720 status = readl(&dma->status);
1721 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001722}
1723
1724/*
1725 * Allocate the data structures needed for using DMA with an interface
1726 * and fill the proper list of functions pointers
1727 */
1728static void __init
1729pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1730{
1731 /* We won't need pci_dev if we switch to generic consistent
1732 * DMA routines ...
1733 */
1734 if (hwif->pci_dev == NULL)
1735 return;
1736 /*
1737 * Allocate space for the DBDMA commands.
1738 * The +2 is +1 for the stop command and +1 to allow for
1739 * aligning the start address to a multiple of 16 bytes.
1740 */
1741 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
1742 hwif->pci_dev,
1743 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1744 &hwif->dmatable_dma);
1745 if (pmif->dma_table_cpu == NULL) {
1746 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1747 hwif->name);
1748 return;
1749 }
1750
Bartlomiej Zolnierkiewicz7469aaf2007-02-17 02:40:26 +01001751 hwif->dma_off_quietly = &ide_dma_off_quietly;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001752 hwif->ide_dma_on = &__ide_dma_on;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001753 hwif->dma_setup = &pmac_ide_dma_setup;
1754 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
1755 hwif->dma_start = &pmac_ide_dma_start;
1756 hwif->ide_dma_end = &pmac_ide_dma_end;
1757 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
Bartlomiej Zolnierkiewicz7469aaf2007-02-17 02:40:26 +01001758 hwif->dma_host_off = &pmac_ide_dma_host_off;
Bartlomiej Zolnierkiewiczccf35282007-02-17 02:40:26 +01001759 hwif->dma_host_on = &pmac_ide_dma_host_on;
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +02001760 hwif->dma_timeout = &ide_dma_timeout;
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001761 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001762
Linus Torvalds1da177e2005-04-16 15:20:36 -07001763 switch(pmif->kind) {
1764 case controller_sh_ata6:
1765 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
1766 hwif->mwdma_mask = 0x07;
1767 hwif->swdma_mask = 0x00;
1768 break;
1769 case controller_un_ata6:
1770 case controller_k2_ata6:
1771 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
1772 hwif->mwdma_mask = 0x07;
1773 hwif->swdma_mask = 0x00;
1774 break;
1775 case controller_kl_ata4:
1776 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
1777 hwif->mwdma_mask = 0x07;
1778 hwif->swdma_mask = 0x00;
1779 break;
1780 default:
1781 hwif->ultra_mask = 0x00;
1782 hwif->mwdma_mask = 0x07;
1783 hwif->swdma_mask = 0x00;
1784 break;
Bartlomiej Zolnierkiewicz254bb552007-10-13 17:47:50 +02001785 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001786}
1787
1788#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */