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gerrit-public.fairphone.software / kernel / msm / 7dda18a44bf22ff0decb3c370114ccd73224f6bb / . / arch / arm / boot / dts / msm8610.dtsi
blob: 53d0d5d83d53c54b4035ac984f1e8d6020e88223 [file] [log] [blame]
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Olav Haugan54166782013-01-28 16:59:51 -0800[diff] [blame]14/include/ "msm-iommu-v0.dtsi"
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]15/include/ "msm8610-ion.dtsi"
Matt Wagantall1bf56932012-11-29 15:03:29 -0800[diff] [blame]16/include/ "msm-gdsc.dtsi"
Aparna Dasd16555b2013-03-06 15:46:38 -0800[diff] [blame]17/include/ "msm8610-coresight.dtsi"
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]18/include/ "msm8610-pm.dtsi"
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]19
20/ {
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]21 model = "Qualcomm MSM 8610";
22 compatible = "qcom,msm8610";
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]23 interrupt-parent = <&intc>;
24
25 intc: interrupt-controller@f9000000 {
26 compatible = "qcom,msm-qgic2";
27 interrupt-controller;
28 #interrupt-cells = <3>;
29 reg = <0xf9000000 0x1000>,
30 <0xf9002000 0x1000>;
31 };
32
33 msmgpio: gpio@fd510000 {
34 compatible = "qcom,msm-gpio";
35 interrupt-controller;
36 #interrupt-cells = <2>;
37 reg = <0xfd510000 0x4000>;
Syed Rameez Mustafa86cccfc2012-12-10 18:06:08 -0800[diff] [blame]38 gpio-controller;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]39 #gpio-cells = <2>;
Rohit Vaswani341c2032012-11-08 18:49:29 -0800[diff] [blame]40 ngpio = <102>;
Rohit Vaswanid2001522012-12-05 19:23:44 -0800[diff] [blame]41 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -0800[diff] [blame]42 qcom,direct-connect-irqs = <8>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]43 };
44
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]45 aliases {
46 spi0 = &spi_0;
47 };
48
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -0700[diff] [blame]49 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -0800[diff] [blame]50 compatible = "arm,armv7-timer";
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -0700[diff] [blame]51 interrupts = <1 2 0 1 3 0>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]52 clock-frequency = <19200000>;
53 };
54
Arun Menon2a7e3772013-01-17 12:06:59 -0800[diff] [blame]55 qcom,msm-adsp-loader {
56 compatible = "qcom,adsp-loader";
57 qcom,adsp-state = <0>;
58 };
59
Abhimanyu Kapur032b1f42013-01-18 00:10:50 -0800[diff] [blame]60 qcom,msm-imem@fe805000 {
61 compatible = "qcom,msm-imem";
62 reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
63 };
64
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]65 serial@f991f000 {
66 compatible = "qcom,msm-lsuart-v14";
67 reg = <0xf991f000 0x1000>;
68 interrupts = <0 109 0>;
69 status = "disabled";
70 };
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]71
Arun Menon8e25dd42013-01-11 14:11:54 -0800[diff] [blame]72 qcom,vidc@fdc00000 {
73 compatible = "qcom,msm-vidc";
74 hfi = "q6";
75 };
76
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]77 usb@f9a55000 {
78 compatible = "qcom,hsusb-otg";
79 reg = <0xf9a55000 0x400>;
Mayank Rana33d26662013-01-17 10:22:25 +0530[diff] [blame]80 interrupts = <0 134 0>, <0 140 0>;
81 interrupt-names = "core_irq", "async_irq";
Mayank Rana76c6ce22012-11-07 17:07:58 +0530[diff] [blame]82 HSUSB_VDDCX-supply = <&pm8110_s1>;
83 HSUSB_1p8-supply = <&pm8110_l10>;
84 HSUSB_3p3-supply = <&pm8110_l20>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]85
86 qcom,hsusb-otg-phy-type = <2>;
87 qcom,hsusb-otg-mode = <1>;
88 qcom,hsusb-otg-otg-control = <1>;
89 qcom,hsusb-otg-disable-reset;
90 };
91
Mayank Ranacc0c5452013-01-29 16:41:53 +0530[diff] [blame]92 android_usb@fe8050c8 {
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]93 compatible = "qcom,android-usb";
Mayank Ranacc0c5452013-01-29 16:41:53 +0530[diff] [blame]94 reg = <0xfe8050c8 0xc8>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]95 };
96
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]97 sdcc1: qcom,sdcc@f9824000 {
98 cell-index = <1>; /* SDC1 eMMC slot */
99 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800[diff] [blame]100 reg = <0xf9824000 0x800>,
101 <0xf9824800 0x100>,
102 <0xf9804000 0x7000>;
103 reg-names = "core_mem", "dml_mem", "bam_mem";
104 interrupts = <0 123 0>, <0 137 0>;
105 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]106
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]107 vdd-supply = <&pm8110_l17>;
108 qcom,vdd-always-on;
109 qcom,vdd-lpm-sup;
110 qcom,vdd-voltage-level = <2900000 2900000>;
111 qcom,vdd-current-level = <9000 400000>;
112
113 vdd-io-supply = <&pm8110_l6>;
114 qcom,vdd-io-always-on;
115 qcom,vdd-io-lpm-sup;
116 qcom,vdd-io-voltage-level = <1800000 1800000>;
117 qcom,vdd-io-current-level = <9000 60000>;
118
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]119 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
120 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
121 qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
122 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]123
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]124 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]125 qcom,sup-voltages = <2900 2900>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]126 qcom,bus-width = <8>;
127 qcom,nonremovable;
128 qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]129 };
130
131 sdcc2: qcom,sdcc@f98a4000 {
132 cell-index = <2>; /* SDC2 SD card slot */
133 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800[diff] [blame]134 reg = <0xf98a4000 0x800>,
135 <0xf98a4800 0x100>,
136 <0xf9884000 0x7000>;
137 reg-names = "core_mem", "dml_mem", "bam_mem";
138 interrupts = <0 125 0>, <0 220 0>;
139 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]140
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]141 vdd-supply = <&pm8110_l18>;
142 qcom,vdd-voltage-level = <2950000 2950000>;
143 qcom,vdd-current-level = <9000 400000>;
144
145 vdd-io-supply = <&pm8110_l21>;
146 qcom,vdd-io-voltage-level = <1800000 2950000>;
147 qcom,vdd-io-current-level = <9000 50000>;
148
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]149 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
150 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
151 qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
152 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]153
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]154 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
155 qcom,sup-voltages = <2950 2950>;
156 qcom,bus-width = <4>;
157 qcom,xpc;
158 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
159 qcom,current-limit = <800>;
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]160 };
161
Yan He6c7304c2012-11-09 22:07:08 -0800[diff] [blame]162 qcom,sps {
163 compatible = "qcom,msm_sps";
164 qcom,device-type = <3>;
165 };
166
Jeff Hugo6a289a32012-11-29 16:16:47 -0700[diff] [blame]167 qcom,smem@d600000 {
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]168 compatible = "qcom,smem";
Jeff Hugo6a289a32012-11-29 16:16:47 -0700[diff] [blame]169 reg = <0xd600000 0x200000>,
Stepan Moskovchenkod6ee8262013-02-06 11:26:05 -0800[diff] [blame]170 <0xf9011000 0x1000>,
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]171 <0xfc428000 0x4000>;
172 reg-names = "smem", "irq-reg-base", "aux-mem1";
173
174 qcom,smd-modem {
175 compatible = "qcom,smd";
176 qcom,smd-edge = <0>;
177 qcom,smd-irq-offset = <0x8>;
178 qcom,smd-irq-bitmask = <0x1000>;
179 qcom,pil-string = "modem";
180 interrupts = <0 25 1>;
181 };
182
183 qcom,smsm-modem {
184 compatible = "qcom,smsm";
185 qcom,smsm-edge = <0>;
186 qcom,smsm-irq-offset = <0x8>;
187 qcom,smsm-irq-bitmask = <0x2000>;
188 interrupts = <0 26 1>;
189 };
190
191 qcom,smd-adsp {
192 compatible = "qcom,smd";
193 qcom,smd-edge = <1>;
194 qcom,smd-irq-offset = <0x8>;
195 qcom,smd-irq-bitmask = <0x100>;
196 qcom,pil-string = "adsp";
197 interrupts = <0 156 1>;
198 };
199
200 qcom,smsm-adsp {
201 compatible = "qcom,smsm";
202 qcom,smsm-edge = <1>;
203 qcom,smsm-irq-offset = <0x8>;
204 qcom,smsm-irq-bitmask = <0x200>;
205 interrupts = <0 157 1>;
206 };
207
208 qcom,smd-wcnss {
209 compatible = "qcom,smd";
210 qcom,smd-edge = <6>;
211 qcom,smd-irq-offset = <0x8>;
212 qcom,smd-irq-bitmask = <0x20000>;
213 qcom,pil-string = "wcnss";
214 interrupts = <0 142 1>;
215 };
216
217 qcom,smsm-wcnss {
218 compatible = "qcom,smsm";
219 qcom,smsm-edge = <6>;
220 qcom,smsm-irq-offset = <0x8>;
221 qcom,smsm-irq-bitmask = <0x80000>;
222 interrupts = <0 144 1>;
223 };
224
225 qcom,smd-rpm {
226 compatible = "qcom,smd";
227 qcom,smd-edge = <15>;
228 qcom,smd-irq-offset = <0x8>;
229 qcom,smd-irq-bitmask = <0x1>;
230 interrupts = <0 168 1>;
231 qcom,irq-no-suspend;
232 };
David Ng5a3cb232012-12-03 16:42:53 -0800[diff] [blame]233 };
Hanumant Singh4e334c82012-11-14 10:16:39 -0800[diff] [blame]234
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]235 rpm_bus: qcom,rpm-smd {
236 compatible = "qcom,rpm-smd";
237 rpm-channel-name = "rpm_requests";
238 rpm-channel-type = <15>; /* SMD_APPS_RPM */
Priyanka Mathur6e993c92013-03-20 11:17:27 -0700[diff] [blame]239 rpm-standalone;
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]240 };
241
Olav Haugan8340d932013-01-25 12:03:11 -0800[diff] [blame]242 qcom,msm-mem-hole {
243 compatible = "qcom,msm-mem-hole";
244 qcom,memblock-remove = <0x07C00000 0x6000000>; /* Address and Size of Hole */
245 };
246
Hanumant Singh4e334c82012-11-14 10:16:39 -0800[diff] [blame]247 qcom,wdt@f9017000 {
248 compatible = "qcom,msm-watchdog";
249 reg = <0xf9017000 0x1000>;
250 interrupts = <0 3 0>, <0 4 0>;
251 qcom,bark-time = <11000>;
252 qcom,pet-time = <10000>;
Mitchel Humpherys1be23802012-11-16 15:52:32 -0800[diff] [blame]253 qcom,ipi-ping;
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]254 };
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]255
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800[diff] [blame]256 qcom,acpuclk@f9011050 {
257 compatible = "qcom,acpuclk-a7";
258 reg = <0xf9011050 0x8>;
259 reg-names = "rcg_base";
260 a7_cpu-supply = <&pm8110_s2>;
261 a7_mem-supply = <&pm8110_l3>;
262 };
263
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]264 spmi_bus: qcom,spmi@fc4c0000 {
265 cell-index = <0>;
266 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]267 reg-names = "core", "intr", "cnfg";
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]268 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]269 <0Xfc4cb000 0x1000>,
270 <0Xfc4ca000 0x1000>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]271 /* 190,ee0_krait_hlos_spmi_periph_irq */
272 /* 187,channel_0_krait_hlos_trans_done_irq */
273 interrupts = <0 190 0>, <0 187 0>;
274 qcom,not-wakeup;
275 qcom,pmic-arb-ee = <0>;
276 qcom,pmic-arb-channel = <0>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]277 };
278
Gilad Avidovf84f2792013-01-31 13:26:39 -0700[diff] [blame]279 i2c@f9925000 { /* BLSP-1 QUP-3 */
280 cell-index = <0>;
281 compatible = "qcom,i2c-qup";
282 #address-cells = <1>;
283 #size-cells = <0>;
284 reg-names = "qup_phys_addr";
285 reg = <0xf9925000 0x1000>;
286 interrupt-names = "qup_err_intr";
287 interrupts = <0 97 0>;
288 qcom,i2c-bus-freq = <100000>;
289 };
290
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]291
292 spi_0: spi@f9923000 { /* BLSP1 QUP1 */
293 compatible = "qcom,spi-qup-v2";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 reg-names = "spi_physical", "spi_bam_physical";
297 reg = <0xf9923000 0x1000>,
298 <0xf9904000 0xF000>;
299 interrupt-names = "spi_irq", "spi_bam_irq";
300 interrupts = <0 95 0>, <0 238 0>;
301 spi-max-frequency = <19200000>;
302
303 gpios = <&msmgpio 3 0>, /* CLK */
304 <&msmgpio 1 0>, /* MISO */
305 <&msmgpio 0 0>; /* MOSI */
306 cs-gpios = <&msmgpio 2 0>;
307
308 qcom,infinite-mode = <0>;
309 qcom,use-bam;
310 qcom,ver-reg-exists;
311 qcom,bam-consumer-pipe-index = <12>;
312 qcom,bam-producer-pipe-index = <13>;
313 };
314
Vikram Mulukutla1ac32fd2013-01-28 10:03:58 -0800[diff] [blame]315 qcom,pronto@fb21b000 {
316 compatible = "qcom,pil-pronto";
317 reg = <0xfb21b000 0x3000>,
318 <0xfc401700 0x4>,
319 <0xfd485300 0xc>;
320 reg-names = "pmu_base", "clk_base", "halt_base";
321 interrupts = <0 149 1>;
322 vdd_pronto_pll-supply = <&pm8110_l10>;
323
324 qcom,firmware-name = "wcnss";
325 };
326
Fred Oh92b18a02013-01-22 13:29:41 -0800[diff] [blame]327 sound {
328 compatible = "qcom,msm8x10-audio-codec";
329 qcom,model = "msm8x10-snd-card";
330 };
331
332 qcom,msm-pcm {
333 compatible = "qcom,msm-pcm-dsp";
334 };
335
336 qcom,msm-pcm-routing {
337 compatible = "qcom,msm-pcm-routing";
338 };
339
340 qcom,msm-pcm-lpa {
341 compatible = "qcom,msm-pcm-lpa";
342 };
343
344 qcom,msm-compr-dsp {
345 compatible = "qcom,msm-compr-dsp";
346 };
347
348 qcom,msm-voip-dsp {
349 compatible = "qcom,msm-voip-dsp";
350 };
351
352 qcom,msm-pcm-voice {
353 compatible = "qcom,msm-pcm-voice";
354 };
355
356 qcom,msm-stub-codec {
357 compatible = "qcom,msm-stub-codec";
358 };
359
360 qcom,msm-dai-fe {
361 compatible = "qcom,msm-dai-fe";
362 };
363
364 qcom,msm-pcm-afe {
365 compatible = "qcom,msm-pcm-afe";
366 };
367
368 qcom,msm-dai-mi2s {
369 compatible = "qcom,msm-dai-mi2s";
370 qcom,msm-dai-q6-mi2s-prim {
371 compatible = "qcom,msm-dai-q6-mi2s";
372 qcom,msm-dai-q6-mi2s-dev-id = <0>;
373 qcom,msm-mi2s-rx-lines = <1>;
374 qcom,msm-mi2s-tx-lines = <0>;
375 };
376
377 qcom,msm-dai-q6-mi2s-sec {
378 compatible = "qcom,msm-dai-q6-mi2s";
379 qcom,msm-dai-q6-mi2s-dev-id = <1>;
380 qcom,msm-mi2s-rx-lines = <0>;
381 qcom,msm-mi2s-tx-lines = <3>;
382 };
383 };
384
385 qcom,msm-dai-q6 {
386 compatible = "qcom,msm-dai-q6";
387 qcom,msm-dai-q6-bt-sco-rx {
388 compatible = "qcom,msm-dai-q6-dev";
389 qcom,msm-dai-q6-dev-id = <12288>;
390 };
391
392 qcom,msm-dai-q6-bt-sco-tx {
393 compatible = "qcom,msm-dai-q6-dev";
394 qcom,msm-dai-q6-dev-id = <12289>;
395 };
396
397 qcom,msm-dai-q6-int-fm-rx {
398 compatible = "qcom,msm-dai-q6-dev";
399 qcom,msm-dai-q6-dev-id = <12292>;
400 };
401
402 qcom,msm-dai-q6-int-fm-tx {
403 compatible = "qcom,msm-dai-q6-dev";
404 qcom,msm-dai-q6-dev-id = <12293>;
405 };
406
407 qcom,msm-dai-q6-be-afe-pcm-rx {
408 compatible = "qcom,msm-dai-q6-dev";
409 qcom,msm-dai-q6-dev-id = <224>;
410 };
411
412 qcom,msm-dai-q6-be-afe-pcm-tx {
413 compatible = "qcom,msm-dai-q6-dev";
414 qcom,msm-dai-q6-dev-id = <225>;
415 };
416
417 qcom,msm-dai-q6-afe-proxy-rx {
418 compatible = "qcom,msm-dai-q6-dev";
419 qcom,msm-dai-q6-dev-id = <241>;
420 };
421
422 qcom,msm-dai-q6-afe-proxy-tx {
423 compatible = "qcom,msm-dai-q6-dev";
424 qcom,msm-dai-q6-dev-id = <240>;
425 };
426 };
427
428 qcom,msm-pcm-hostless {
429 compatible = "qcom,msm-pcm-hostless";
430 };
431
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]432 qcom,lpass@fe200000 {
433 compatible = "qcom,pil-q6v5-lpass";
434 reg = <0xfe200000 0x00100>,
Matt Wagantall015b50af2013-03-05 18:51:16 -0800[diff] [blame]435 <0xfd485100 0x00010>,
436 <0xfc4016c0 0x00004>;
437 reg-names = "qdsp6_base", "halt_base", "restart_reg";
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]438 interrupts = <0 162 1>;
Matt Wagantall6c515982013-01-29 14:58:43 -0800[diff] [blame]439 vdd_cx-supply = <&pm8110_s1_corner>;
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]440 qcom,firmware-name = "adsp";
441 };
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]442
443 tsens: tsens@fc4a8000 {
444 compatible = "qcom,msm-tsens";
445 reg = <0xfc4a8000 0x2000>,
446 <0xfc4b8000 0x1000>;
447 reg-names = "tsens_physical", "tsens_eeprom_physical";
448 interrupts = <0 184 0>;
449 qcom,sensors = <2>;
450 qcom,slope = <2901 2846>;
451 qcom,calib-mode = "fuse_map2";
452 qcom,calibration-less-mode;
Siddartha Mohanadoss0ca83312013-03-14 11:43:18 -0700[diff] [blame]453 qcom,tsens-local-init;
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]454 };
455
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]456};
David Collinsc6b34832012-10-24 12:57:57 -0700[diff] [blame]457
Matt Wagantall1bf56932012-11-29 15:03:29 -0800[diff] [blame]458&gdsc_vfe {
459 status = "ok";
460};
461
462&gdsc_oxili_cx {
463 status = "ok";
464};
465
Olav Haugan9c255522012-11-16 16:43:17 -0800[diff] [blame]466&lpass_iommu {
467 status = "ok";
468};
469
470&copss_iommu {
471 status = "ok";
472};
473
474&mdpe_iommu {
475 status = "ok";
476};
477
478&mdps_iommu {
479 status = "ok";
480};
481
482&gfx_iommu {
483 status = "ok";
484};
485
486&vfe_iommu {
487 status = "ok";
488};
489
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]490/include/ "msm8610-iommu-domains.dtsi"
Olav Haugan4bc4b692012-12-10 18:29:35 -0800[diff] [blame]491
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]492/include/ "msm-pm8110.dtsi"
Xiaozhe Shi1581a7b2013-02-21 15:17:57 -0800[diff] [blame]493/include/ "msm8610-regulator.dtsi"
Siddartha Mohanadoss0f664a82013-03-11 22:52:01 -0700[diff] [blame]494
495&pm8110_vadc {
496 chan@0 {
497 label = "usb_in";
498 reg = <0>;
499 qcom,decimation = <0>;
500 qcom,pre-div-channel-scaling = <4>;
501 qcom,calibration-type = "absolute";
502 qcom,scale-function = <0>;
503 qcom,hw-settle-time = <0>;
504 qcom,fast-avg-setup = <0>;
505 };
506
507 chan@2 {
508 label = "vchg_sns";
509 reg = <2>;
510 qcom,decimation = <0>;
511 qcom,pre-div-channel-scaling = <3>;
512 qcom,calibration-type = "absolute";
513 qcom,scale-function = <0>;
514 qcom,hw-settle-time = <0>;
515 qcom,fast-avg-setup = <0>;
516 };
517
518 chan@5 {
519 label = "vcoin";
520 reg = <5>;
521 qcom,decimation = <0>;
522 qcom,pre-div-channel-scaling = <1>;
523 qcom,calibration-type = "absolute";
524 qcom,scale-function = <0>;
525 qcom,hw-settle-time = <0>;
526 qcom,fast-avg-setup = <0>;
527 };
528
529 chan@6 {
530 label = "vbat_sns";
531 reg = <6>;
532 qcom,decimation = <0>;
533 qcom,pre-div-channel-scaling = <1>;
534 qcom,calibration-type = "absolute";
535 qcom,scale-function = <0>;
536 qcom,hw-settle-time = <0>;
537 qcom,fast-avg-setup = <0>;
538 };
539
540 chan@7 {
541 label = "vph_pwr";
542 reg = <7>;
543 qcom,decimation = <0>;
544 qcom,pre-div-channel-scaling = <1>;
545 qcom,calibration-type = "absolute";
546 qcom,scale-function = <0>;
547 qcom,hw-settle-time = <0>;
548 qcom,fast-avg-setup = <0>;
549 };
550
551 chan@30 {
552 label = "batt_therm";
553 reg = <0x30>;
554 qcom,decimation = <0>;
555 qcom,pre-div-channel-scaling = <0>;
556 qcom,calibration-type = "ratiometric";
557 qcom,scale-function = <1>;
558 qcom,hw-settle-time = <2>;
559 qcom,fast-avg-setup = <0>;
560 };
561
562 chan@31 {
563 label = "batt_id";
564 reg = <0x31>;
565 qcom,decimation = <0>;
566 qcom,pre-div-channel-scaling = <0>;
567 qcom,calibration-type = "ratiometric";
568 qcom,scale-function = <0>;
569 qcom,hw-settle-time = <2>;
570 qcom,fast-avg-setup = <0>;
571 };
572
573 chan@b2 {
574 label = "xo_therm_pu2";
575 reg = <0xb2>;
576 qcom,decimation = <0>;
577 qcom,pre-div-channel-scaling = <0>;
578 qcom,calibration-type = "ratiometric";
579 qcom,scale-function = <4>;
580 qcom,hw-settle-time = <2>;
581 qcom,fast-avg-setup = <0>;
582 };
583};
584
585