blob: b06419d33dd2a4df989cb8e3da4d9ba58d6822d3 [file] [log] [blame]
Pushkar Joshi70210812012-12-15 19:01:39 -08001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Rohit Vaswani3fc60342012-04-23 18:55:15 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Rohit Vaswani3fc60342012-04-23 18:55:15 -070013/include/ "skeleton.dtsi"
Mitchel Humpherysb3f40d12012-10-05 16:26:58 -070014/include/ "msm9625-ion.dtsi"
Girish Mahadevanfc5f5c32012-10-23 16:27:28 -070015/include/ "msm9625-pm.dtsi"
Pushkar Joshifaf92a72012-10-29 17:45:27 -070016/include/ "msm9625-coresight.dtsi"
Seemanta Dutta519dfd12013-01-22 17:34:36 -080017/include/ "msm9625-smp2p.dtsi"
Rohit Vaswani3fc60342012-04-23 18:55:15 -070018
19/ {
20 model = "Qualcomm MSM 9625";
21 compatible = "qcom,msm9625";
22 interrupt-parent = <&intc>;
23
Gilad Avidov0697ea62013-02-11 16:46:38 -070024 aliases {
25 spi0 = &spi_0;
26 };
27
Rohit Vaswani3fc60342012-04-23 18:55:15 -070028 intc: interrupt-controller@F9000000 {
29 compatible = "qcom,msm-qgic2";
30 interrupt-controller;
31 #interrupt-cells = <3>;
32 reg = <0xF9000000 0x1000>,
33 <0xF9002000 0x1000>;
34 };
35
Abhimanyu Kapur490d20c2012-06-22 17:34:20 -070036 l2: cache-controller@f9040000 {
37 compatible = "arm,pl310-cache";
38 reg = <0xf9040000 0x1000>;
Abhimanyu Kapur490d20c2012-06-22 17:34:20 -070039 cache-unified;
40 cache-level = <2>;
41 };
42
Rohit Vaswani3fc60342012-04-23 18:55:15 -070043 msmgpio: gpio@fd510000 {
44 compatible = "qcom,msm-gpio";
Rohit Vaswanib1cc4932012-07-23 21:30:11 -070045 gpio-controller;
46 #gpio-cells = <2>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070047 interrupt-controller;
48 #interrupt-cells = <2>;
49 reg = <0xfd510000 0x4000>;
Rohit Vaswani341c2032012-11-08 18:49:29 -080050 ngpio = <76>;
Rohit Vaswanid2001522012-12-05 19:23:44 -080051 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -080052 qcom,direct-connect-irqs = <8>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070053 };
54
Abhimanyu Kapur28d0e102013-03-08 19:52:14 -080055 qcom,mpm2-sleep-counter@fc4a3000 {
56 compatible = "qcom,mpm2-sleep-counter";
57 reg = <0xfc4a3000 0x1000>;
58 clock-frequency = <32768>;
59 };
60
Rohit Vaswania5129562012-06-12 20:11:23 -070061 timer: msm-qtimer@f9021000 {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -080062 compatible = "arm,armv7-timer";
Rohit Vaswania5129562012-06-12 20:11:23 -070063 reg = <0xF9021000 0x1000>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070064 interrupts = <0 7 0>;
Rohit Vaswania5129562012-06-12 20:11:23 -070065 irq-is-not-percpu;
Abhimanyu Kapuraf4c4d52012-10-01 14:15:10 -070066 clock-frequency = <19200000>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070067 };
Jin Hong8d328582012-05-01 15:45:29 -070068
Yan He3cb97ba2012-05-13 16:45:24 -070069 qcom,sps@f9980000 {
70 compatible = "qcom,msm_sps";
71 reg = <0xf9984000 0x15000>,
72 <0xf9999000 0xb000>,
Yan He6f9ae712012-09-20 12:55:47 -070073 <0xfe803000 0x4800>;
Yan He3cb97ba2012-05-13 16:45:24 -070074 interrupts = <0 94 0>;
75 qcom,device-type = <2>;
76 };
77
Jin Hong8d328582012-05-01 15:45:29 -070078 serial@f991f000 {
79 compatible = "qcom,msm-lsuart-v14";
80 reg = <0xf991f000 0x1000>;
81 interrupts = <0 109 0>;
82 };
Sahitya Tummala9ba4b282012-06-19 11:41:51 +053083
Jack Phama01e9c12012-09-25 21:37:03 -070084 usb@f9a55000 {
85 compatible = "qcom,hsusb-otg";
86 reg = <0xf9a55000 0x400>;
87 interrupts = <0 134 0 0 140 0>;
88 interrupt-names = "core_irq", "async_irq";
89 HSUSB_VDDCX-supply = <&pm8019_l12>;
90 HSUSB_1p8-supply = <&pm8019_l2>;
91 HSUSB_3p3-supply = <&pm8019_l4>;
David Collins84d39b22012-11-01 14:40:08 -070092 vbus_otg-supply = <&usb_vbus>;
Jack Phama01e9c12012-09-25 21:37:03 -070093
94 qcom,hsusb-otg-phy-type = <2>;
Amit Blay0d353532013-01-22 18:09:51 +020095 qcom,hsusb-otg-mode = <3>;
Jack Phama01e9c12012-09-25 21:37:03 -070096 qcom,hsusb-otg-otg-control = <1>;
97 qcom,hsusb-otg-disable-reset;
Ido Shayevitz9f953c12013-01-13 13:36:30 +020098 qcom,hsusb-otg-lpm-on-dev-suspend;
Ido Shayevitz0f2942d2013-01-13 13:59:48 +020099 qcom,hsusb-otg-clk-always-on-workaround;
Shimrit Malichi3043c0c2013-03-10 11:26:41 +0200100 qcom,hsusb-otg-delay-lpm;
Ido Shayevitz57101762013-01-18 10:06:24 +0200101
102 qcom,msm-bus,name = "usb2";
103 qcom,msm-bus,num-cases = <2>;
104 qcom,msm-bus,active-only = <0>;
105 qcom,msm-bus,num-paths = <1>;
106 qcom,msm-bus,vectors-KBps =
107 <87 512 0 0>,
108 <87 512 40000 640000>;
Jack Phama01e9c12012-09-25 21:37:03 -0700109 };
110
Ofir Cohenb1d52612012-11-14 09:37:38 +0200111 hsic@f9a15000 {
112 compatible = "qcom,hsic-host";
113 reg = <0xf9a15000 0x400>;
Ido Shayevitzfafb1b12013-02-18 18:10:05 +0200114 interrupts = <0 136 0>, <0 148 0>;
115 interrupt-names = "core_irq", "async_irq";
Ofir Cohenb1d52612012-11-14 09:37:38 +0200116 HSIC_VDDCX-supply = <&pm8019_l12>;
117 HSIC_GDSC-supply = <&gdsc_usb_hsic>;
Ido Shayevitz57101762013-01-18 10:06:24 +0200118
119 qcom,msm-bus,name = "hsic";
120 qcom,msm-bus,num-cases = <2>;
121 qcom,msm-bus,active-only = <0>;
122 qcom,msm-bus,num-paths = <1>;
123 qcom,msm-bus,vectors-KBps =
124 <85 512 0 0>,
125 <85 512 40000 640000>;
Shimrit Malichi9e840e32013-03-14 20:45:16 +0200126 qcom,pool-64-bit-align;
127 qcom,enable-hbm;
Ofir Cohenb1d52612012-11-14 09:37:38 +0200128 };
129
Jack Phamd61ff562012-11-21 19:25:53 +0200130 qcom,usbbam@f9a44000 {
131 compatible = "qcom,usb-bam-msm";
Shimrit Malichi9e840e32013-03-14 20:45:16 +0200132 reg = <0xf9a44000 0x11000>,
133 <0xf9a04000 0x11000>;
134 reg-names = "hsusb", "hsic";
135 interrupts = <0 135 0 0 255 0>;
136 interrupt-names = "hsusb", "hsic";
Jack Phamd61ff562012-11-21 19:25:53 +0200137 qcom,usb-bam-num-pipes = <16>;
138 qcom,ignore-core-reset-ack;
repo syncb0ca7512013-01-16 19:37:44 +0200139 qcom,disable-clk-gating;
Jack Phamd61ff562012-11-21 19:25:53 +0200140
141 qcom,pipe0 {
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200142 label = "hsusb-ipa-out-0";
Lena Salman192db732013-03-19 14:43:52 +0200143 qcom,usb-bam-mem-type = <2>;
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200144 qcom,bam-type = <1>;
145 qcom,dir = <0>;
146 qcom,pipe-num = <0>;
147 qcom,peer-bam = <2>;
Jack Phamd61ff562012-11-21 19:25:53 +0200148 qcom,src-bam-physical-address = <0xf9a44000>;
149 qcom,src-bam-pipe-index = <1>;
Lena Salman192db732013-03-19 14:43:52 +0200150 qcom,data-fifo-size = <0x8000>;
151 qcom,descriptor-fifo-size = <0x2000>;
Jack Phamd61ff562012-11-21 19:25:53 +0200152 };
Jack Phamd61ff562012-11-21 19:25:53 +0200153 qcom,pipe1 {
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200154 label = "hsusb-ipa-in-0";
Lena Salman192db732013-03-19 14:43:52 +0200155 qcom,usb-bam-mem-type = <2>;
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200156 qcom,bam-type = <1>;
157 qcom,dir = <1>;
158 qcom,pipe-num = <0>;
159 qcom,peer-bam = <2>;
Jack Phamd61ff562012-11-21 19:25:53 +0200160 qcom,dst-bam-physical-address = <0xf9a44000>;
161 qcom,dst-bam-pipe-index = <0>;
Lena Salman192db732013-03-19 14:43:52 +0200162 qcom,data-fifo-size = <0x8000>;
163 qcom,descriptor-fifo-size = <0x2000>;
Jack Phamd61ff562012-11-21 19:25:53 +0200164 };
Anna Perel6ac1fa92013-01-24 22:08:06 +0200165 qcom,pipe2 {
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200166 label = "hsusb-qdss-in-0";
Anna Perel6ac1fa92013-01-24 22:08:06 +0200167 qcom,usb-bam-mem-type = <0>;
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200168 qcom,bam-type = <1>;
169 qcom,dir = <1>;
170 qcom,pipe-num = <0>;
171 qcom,peer-bam = <1>;
Anna Perel6ac1fa92013-01-24 22:08:06 +0200172 qcom,src-bam-physical-address = <0xfc37c000>;
173 qcom,src-bam-pipe-index = <0>;
174 qcom,dst-bam-physical-address = <0xf9a44000>;
175 qcom,dst-bam-pipe-index = <2>;
176 qcom,data-fifo-offset = <0x4100>;
177 qcom,data-fifo-size = <0x400>;
178 qcom,descriptor-fifo-offset = <0x4000>;
179 qcom,descriptor-fifo-size = <0x400>;
180 };
Shimrit Malichi9e840e32013-03-14 20:45:16 +0200181 qcom,pipe3 {
182 label = "hsic-ipa-in-0";
183 qcom,usb-bam-mem-type = <2>;
184 qcom,bam-type = <2>;
185 qcom,dir = <1>;
186 qcom,pipe-num = <0>;
187 qcom,peer-bam = <2>;
188 qcom,dst-bam-physical-address = <0xf9a04000>;
189 qcom,dst-bam-pipe-index = <3>;
190 qcom,data-fifo-size = <0xD480>;
191 qcom,descriptor-fifo-size = <0x1A80>;
192 };
193 qcom,pipe4 {
194 label = "hsic-ipa-in-1";
195 qcom,bam-type = <2>;
196 qcom,dir = <1>;
197 qcom,pipe-num = <1>;
198 qcom,peer-bam = <2>;
199 qcom,usb-bam-mem-type = <2>;
200 qcom,dst-bam-physical-address = <0xf9a04000>;
201 qcom,dst-bam-pipe-index = <4>;
202 qcom,data-fifo-size = <0xD480>;
203 qcom,descriptor-fifo-size = <0x1A80>;
204 };
205 qcom,pipe5 {
206 label = "hsic-ipa-in-2";
207 qcom,usb-bam-mem-type = <2>;
208 qcom,bam-type = <2>;
209 qcom,dir = <1>;
210 qcom,pipe-num = <2>;
211 qcom,peer-bam = <2>;
212 qcom,dst-bam-physical-address = <0xf9a04000>;
213 qcom,dst-bam-pipe-index = <5>;
214 qcom,data-fifo-size = <0xD480>;
215 qcom,descriptor-fifo-size = <0x1A80>;
216 };
217 qcom,pipe6 {
218 label = "hsic-ipa-in-3";
219 qcom,usb-bam-mem-type = <2>;
220 qcom,bam-type = <2>;
221 qcom,dir = <1>;
222 qcom,pipe-num = <3>;
223 qcom,peer-bam = <2>;
224 qcom,dst-bam-physical-address = <0xf9a04000>;
225 qcom,dst-bam-pipe-index = <6>;
226 qcom,data-fifo-size = <0xD480>;
227 qcom,descriptor-fifo-size = <0x1A80>;
228 };
229 qcom,pipe7 {
230 label = "hsic-ipa-out-0";
231 qcom,usb-bam-mem-type = <2>;
232 qcom,bam-type = <2>;
233 qcom,dir = <0>;
234 qcom,pipe-num = <0>;
235 qcom,peer-bam = <2>;
236 qcom,src-bam-physical-address = <0xf9a04000>;
237 qcom,src-bam-pipe-index = <7>;
238 qcom,data-fifo-size = <0xD480>;
239 qcom,descriptor-fifo-size = <0x1A80>;
240 };
Jack Phamd61ff562012-11-21 19:25:53 +0200241 };
242
Sahitya Tummala9ba4b282012-06-19 11:41:51 +0530243 qcom,nand@f9ac0000 {
244 compatible = "qcom,msm-nand";
245 reg = <0xf9ac0000 0x1000>,
246 <0xf9ac4000 0x8000>;
247 reg-names = "nand_phys",
248 "bam_phys";
249 interrupts = <0 247 0>;
250 interrupt-names = "bam_irq";
251 };
Rohit Vaswani0045df42012-06-29 16:21:48 -0700252
Gilad Avidov0697ea62013-02-11 16:46:38 -0700253 spi_0: spi@f9924000 {
Rohit Vaswani0045df42012-06-29 16:21:48 -0700254 compatible = "qcom,spi-qup-v2";
Gilad Avidov09c78ec2012-10-18 09:34:35 -0600255 reg = <0xf9924000 0x1000>;
256 interrupts = <0 96 0>;
257 spi-max-frequency = <25000000>;
Rohit Vaswani0045df42012-06-29 16:21:48 -0700258 #address-cells = <1>;
259 #size-cells = <0>;
Gilad Avidov09c78ec2012-10-18 09:34:35 -0600260 gpios = <&msmgpio 7 0>, /* CLK */
261 <&msmgpio 5 0>, /* MISO */
262 <&msmgpio 4 0>; /* MOSI */
Rohit Vaswani0045df42012-06-29 16:21:48 -0700263
Gilad Avidov09c78ec2012-10-18 09:34:35 -0600264 cs-gpios = <&msmgpio 6 0>;
Rohit Vaswani0045df42012-06-29 16:21:48 -0700265
266 ethernet-switch@0 {
267 compatible = "simtec,ks8851";
268 reg = <0>;
269 interrupt-parent = <&msmgpio>;
270 interrupts = <75 0>;
Gilad Avidov09c78ec2012-10-18 09:34:35 -0600271 spi-max-frequency = <4800000>;
Rohit Vaswani0045df42012-06-29 16:21:48 -0700272 };
273 };
Hanumant Singh6c4bf062012-09-06 15:51:10 -0700274
275 qcom,wdt@f9017000 {
276 compatible = "qcom,msm-watchdog";
277 reg = <0xf9017000 0x1000>;
278 interrupts = <1 2 0>, <1 1 0>;
279 qcom,bark-time = <11000>;
280 qcom,pet-time = <10000>;
Hanumant Singh6c4bf062012-09-06 15:51:10 -0700281 };
Kenneth Heitkec2642402012-09-18 18:56:47 -0600282
Girish Mahadevanc65a7112012-09-19 11:15:56 -0600283 rpm_bus: qcom,rpm-smd {
284 compatible = "qcom,rpm-smd";
285 rpm-channel-name = "rpm_requests";
286 rpm-channel-type = <15>; /* SMD_APPS_RPM */
287 };
288
Kenneth Heitkec2642402012-09-18 18:56:47 -0600289 spmi_bus: qcom,spmi@fc4c0000 {
290 cell-index = <0>;
291 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700292 reg-names = "core", "intr", "cnfg";
Kenneth Heitkec2642402012-09-18 18:56:47 -0600293 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700294 <0Xfc4cb000 0x1000>,
295 <0Xfc4ca000 0x1000>;
Kenneth Heitkec2642402012-09-18 18:56:47 -0600296 /* 190,ee0_krait_hlos_spmi_periph_irq */
297 /* 187,channel_0_krait_hlos_trans_done_irq */
298 interrupts = <0 190 0 0 187 0>;
299 qcom,pmic-arb-ee = <0>;
300 qcom,pmic-arb-channel = <0>;
Kenneth Heitkec2642402012-09-18 18:56:47 -0600301 };
Kenneth Heitkef92a8c72012-10-10 17:15:05 -0600302
303 i2c@f9925000 {
304 cell-index = <3>;
305 compatible = "qcom,i2c-qup";
306 reg = <0xf9925000 0x1000>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 reg-names = "qup_phys_addr";
310 interrupts = <0 97 0>;
311 interrupt-names = "qup_err_intr";
312 qcom,i2c-bus-freq = <100000>;
313 qcom,i2c-src-freq = <24000000>;
314 };
Oluwafemi Adeyemibbbcc6e2012-09-14 17:24:26 -0700315
316 sdcc2: qcom,sdcc@f98a4000 {
317 cell-index = <2>; /* SDC2 SD card slot */
318 compatible = "qcom,msm-sdcc";
319 reg = <0xf98a4000 0x800>,
320 <0xf98a4800 0x100>,
321 <0xf9884000 0x7000>;
322 reg-names = "core_mem", "dml_mem", "bam_mem";
323
324 vdd-supply = <&ext_2p95v>;
325
326 vdd-io-supply = <&pm8019_l13>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700327 qcom,vdd-io-always-on;
328 qcom,vdd-io-lpm-sup;
329 qcom,vdd-io-voltage-level = <1800000 2950000>;
330 qcom,vdd-io-current-level = <6 22000>;
Oluwafemi Adeyemibbbcc6e2012-09-14 17:24:26 -0700331
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700332 qcom,pad-pull-on = <0x0 0x3 0x3>;
333 qcom,pad-pull-off = <0x0 0x3 0x3>;
334 qcom,pad-drv-on = <0x7 0x4 0x4>;
335 qcom,pad-drv-off = <0x0 0x0 0x0>;
Oluwafemi Adeyemibbbcc6e2012-09-14 17:24:26 -0700336
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700337 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
338 qcom,sup-voltages = <2950 2950>;
339 qcom,bus-width = <4>;
340 qcom,xpc;
341 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
342 qcom,current-limit = <800>;
Oluwafemi Adeyemibbbcc6e2012-09-14 17:24:26 -0700343
344 interrupt-parent = <&sdcc2>;
345 #address-cells = <0>;
346 interrupts = <0 1 2>;
347 #interrupt-cells = <1>;
348 interrupt-map-mask = <0xffffffff>;
349 interrupt-map = <0 &intc 0 125 0
350 1 &intc 0 220 0
351 2 &msmgpio 66 0x3>;
352 interrupt-names = "core_irq", "bam_irq", "status_irq";
353 cd-gpios = <&msmgpio 66 0>;
354 };
Oluwafemi Adeyemi4926a9e2012-09-14 17:39:59 -0700355
356 sdcc3: qcom,sdcc@f9864000 {
357 cell-index = <3>; /* SDC3 SDIO slot */
358 compatible = "qcom,msm-sdcc";
359 reg = <0xf9864000 0x800>,
360 <0xf9864800 0x100>,
361 <0xf9844000 0x7000>;
362 reg-names = "core_mem", "dml_mem", "bam_mem";
363 interrupts = <0 127 0>, <0 223 0>;
364 interrupt-names = "core_irq", "bam_irq";
365
366 gpios = <&msmgpio 25 0>,
367 <&msmgpio 24 0>,
368 <&msmgpio 16 0>,
369 <&msmgpio 17 0>,
370 <&msmgpio 18 0>,
371 <&msmgpio 19 0>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700372 qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
Oluwafemi Adeyemi4926a9e2012-09-14 17:39:59 -0700373
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700374 qcom,clk-rates = <400000 25000000 50000000 100000000>;
375 qcom,sup-voltages = <2950 2950>;
376 qcom,bus-width = <4>;
377 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Oluwafemi Adeyemi4926a9e2012-09-14 17:39:59 -0700378 };
Jeff Hugocdcb8aa2012-10-16 13:41:20 -0600379
Ravi Gummadidalaedae2002013-02-06 12:13:59 -0800380 ipa_hw: qcom,ipa@fd4c0000 {
Talel Atias49196392012-11-20 19:20:14 +0200381 compatible = "qcom,ipa";
382 reg = <0xfd4c0000 0x26000>,
Vladislav Mordohovich4028f802013-03-04 15:16:31 +0200383 <0xfd4c4000 0x14818>,
384 <0xfc834000 0x7000>;
385 reg-names = "ipa-base", "bam-base", "a2-bam-base";
Talel Atias49196392012-11-20 19:20:14 +0200386 interrupts = <0 252 0>,
Vladislav Mordohovich4028f802013-03-04 15:16:31 +0200387 <0 253 0>,
388 <0 29 1>;
389 interrupt-names = "ipa-irq", "bam-irq", "a2-bam-irq";
Talel Atias49196392012-11-20 19:20:14 +0200390
391 qcom,pipe1 {
392 label = "a2-to-ipa";
393 qcom,src-bam-physical-address = <0xfc834000>;
394 qcom,ipa-bam-mem-type = <0>;
395 qcom,src-bam-pipe-index = <1>;
396 qcom,dst-bam-physical-address = <0xfd4c0000>;
397 qcom,dst-bam-pipe-index = <6>;
398 qcom,data-fifo-offset = <0x1000>;
399 qcom,data-fifo-size = <0xd00>;
400 qcom,descriptor-fifo-offset = <0x1d00>;
401 qcom,descriptor-fifo-size = <0x300>;
402 };
403
404 qcom,pipe2 {
405 label = "ipa-to-a2";
406 qcom,src-bam-physical-address = <0xfd4c0000>;
407 qcom,ipa-bam-mem-type = <0>;
408 qcom,src-bam-pipe-index = <7>;
409 qcom,dst-bam-physical-address = <0xfc834000>;
410 qcom,dst-bam-pipe-index = <0>;
411 qcom,data-fifo-offset = <0x00>;
412 qcom,data-fifo-size = <0xd00>;
413 qcom,descriptor-fifo-offset = <0xd00>;
414 qcom,descriptor-fifo-size = <0x300>;
415 };
416 };
417
Tianyi Gouf6ffa872012-10-22 14:22:58 -0700418 qcom,acpuclk@f9010000 {
419 compatible = "qcom,acpuclk-9625";
420 reg = <0xf9010008 0x10>,
421 <0xf9008004 0x4>;
422 reg-names = "rcg_base", "pwr_base";
423 a5_cpu-supply = <&pm8019_l10_corner_ao>;
424 a5_mem-supply = <&pm8019_l12_ao>;
425 };
Tianyi Gou343bd932012-10-29 11:03:03 -0700426
427 gdsc_usb_hsic: qcom,gdsc@fc400404 {
428 compatible = "qcom,gdsc";
429 reg = <0xfc400404 0x4>;
430 regulator-name = "gdsc_usb_hsic";
431 };
Siddartha Mohanadoss650af6b2012-10-25 20:09:11 -0700432
433 tsens@fc4a8000 {
434 compatible = "qcom,msm-tsens";
435 reg = <0xfc4a8000 0x2000>,
436 <0xfc4b8000 0x1000>;
437 reg-names = "tsens_physical", "tsens_eeprom_physical";
438 interrupts = <0 184 0>;
439 qcom,sensors = <5>;
440 qcom,slope = <3200 3200 3200 3200 3200>;
Siddartha Mohanadoss3f8cd142013-02-06 17:24:33 -0800441 qcom,calib-mode = "fuse_map1";
Siddartha Mohanadoss650af6b2012-10-25 20:09:11 -0700442 };
Hariprasad Dhalinarasimhae9ad1da2012-11-14 18:21:56 -0800443
444 qcom,msm-rng@f9bff000 {
445 compatible = "qcom,msm-rng";
446 reg = <0xf9bff000 0x200>;
447 qcom,msm-rng-iface-clk;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700448 };
449
450 wcd9xxx_intc: wcd9xxx-irq {
451 compatible = "qcom,wcd9xxx-irq";
452 interrupt-controller;
453 #interrupt-cells = <1>;
454 interrupt-parent = <&msmgpio>;
455 interrupts = <20 0>;
456 interrupt-names = "cdc-int";
457 };
458
459 i2c@f9925000 {
460 cell-index = <3>;
461 compatible = "qcom,i2c-qup";
462 reg = <0xf9925000 0x1000>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 reg-names = "qup_phys_addr";
466 interrupts = <0 97 0>;
467 interrupt-names = "qup_err_intr";
468 qcom,i2c-bus-freq = <100000>;
469 qcom,i2c-src-freq = <24000000>;
470
471 wcd9xxx_codec@0d{
472 compatible = "qcom,wcd9xxx-i2c";
473 reg = <0x0d>;
474 qcom,cdc-reset-gpio = <&msmgpio 22 0>;
475 interrupt-parent = <&wcd9xxx_intc>;
476 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28>;
477 cdc-vdd-buck-supply = <&pm8019_l11>;
478 qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
479 qcom,cdc-vdd-buck-current = <25000>;
480
481 cdc-vdd-tx-h-supply = <&pm8019_l11>;
482 qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
483 qcom,cdc-vdd-tx-h-current = <25000>;
484
485 cdc-vdd-rx-h-supply = <&pm8019_l11>;
486 qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
487 qcom,cdc-vdd-rx-h-current = <25000>;
488
489 cdc-vddpx-1-supply = <&pm8019_l11>;
490 qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
491 qcom,cdc-vddpx-1-current = <10000>;
492
493 cdc-vdd-a-1p2v-supply = <&pm8019_l9>;
494 qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
495 qcom,cdc-vdd-a-1p2v-current = <10000>;
496
497 cdc-vddcx-1-supply = <&pm8019_l9>;
498 qcom,cdc-vddcx-1-voltage = <1200000 1200000>;
499 qcom,cdc-vddcx-1-current = <10000>;
500
501 cdc-vddcx-2-supply = <&pm8019_l9>;
502 qcom,cdc-vddcx-2-voltage = <1200000 1200000>;
503 qcom,cdc-vddcx-2-current = <10000>;
504
505 qcom,cdc-micbias-ldoh-v = <0x3>;
506 qcom,cdc-micbias-cfilt1-mv = <1800>;
507 qcom,cdc-micbias-cfilt2-mv = <2700>;
508 qcom,cdc-micbias-cfilt3-mv = <1800>;
509 qcom,cdc-micbias1-cfilt-sel = <0x0>;
510 qcom,cdc-micbias2-cfilt-sel = <0x1>;
511 qcom,cdc-micbias3-cfilt-sel = <0x2>;
512 qcom,cdc-micbias4-cfilt-sel = <0x2>;
Venkat Sudhira50a3762012-11-26 12:12:15 -0800513 qcom,cdc-mclk-clk-rate = <12288000>;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700514 };
515
516 wcd9xxx_codec@77{
517 compatible = "qcom,wcd9xxx-i2c";
518 reg = <0x77>;
519 };
520
521 wcd9xxx_codec@66{
522 compatible = "qcom,wcd9xxx-i2c";
523 reg = <0x66>;
524 };
525
526 wcd9xxx_codec@55{
527 compatible = "qcom,wcd9xxx-i2c";
528 reg = <0x55>;
529 };
530 };
531
532 sound {
533 compatible = "qcom,mdm9625-audio-taiko";
534 qcom,model = "mdm9625-taiko-i2s-snd-card";
535
536 qcom,audio-routing =
537 "RX_BIAS", "MCLK",
538 "LDO_H", "MCLK",
539 "Ext Spk Bottom Pos", "LINEOUT1",
540 "Ext Spk Bottom Neg", "LINEOUT3",
541 "Ext Spk Top Pos", "LINEOUT2",
542 "Ext Spk Top Neg", "LINEOUT4",
543 "AMIC1", "MIC BIAS1 External",
544 "MIC BIAS1 External", "Handset Mic",
545 "AMIC2", "MIC BIAS2 External",
546 "MIC BIAS2 External", "Headset Mic",
547 "AMIC3", "MIC BIAS3 Internal1",
548 "MIC BIAS3 Internal1", "ANCRight Headset Mic",
549 "AMIC4", "MIC BIAS1 Internal2",
550 "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
551 "DMIC1", "MIC BIAS1 External",
552 "MIC BIAS1 External", "Digital Mic1",
553 "DMIC2", "MIC BIAS1 External",
554 "MIC BIAS1 External", "Digital Mic2",
555 "DMIC3", "MIC BIAS3 External",
556 "MIC BIAS3 External", "Digital Mic3",
557 "DMIC4", "MIC BIAS3 External",
558 "MIC BIAS3 External", "Digital Mic4",
559 "DMIC5", "MIC BIAS4 External",
560 "MIC BIAS4 External", "Digital Mic5",
561 "DMIC6", "MIC BIAS4 External",
562 "MIC BIAS4 External", "Digital Mic6";
563 qcom,taiko-mclk-clk-freq = <12288000>;
Venkat Sudhir459d6f52012-12-04 12:00:13 -0800564 prim-i2s-gpio-ws = <&msmgpio 12 0>;
565 prim-i2s-gpio-din = <&msmgpio 13 0>;
566 prim-i2s-gpio-dout = <&msmgpio 14 0>;
567 prim-i2s-gpio-sclk = <&msmgpio 15 0>;
568 prim-i2s-gpio-mclk = <&msmgpio 71 0>;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700569 };
570
571 qcom,msm-adsp-loader {
572 compatible = "qcom,adsp-loader";
Venkat Sudhir480db8a2012-11-09 15:31:50 -0800573 qcom,adsp-state = <2>;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700574 };
575
576 qcom,msm-pcm {
577 compatible = "qcom,msm-pcm-dsp";
Venkat Sudhir3f88b092013-02-28 16:28:37 -0800578 qcom,msm-pcm-dsp-id = <0>;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700579 };
580
581 qcom,msm-pcm-routing {
582 compatible = "qcom,msm-pcm-routing";
583 };
584
585 qcom,msm-compr-dsp {
586 compatible = "qcom,msm-compr-dsp";
587 };
588
589 qcom,msm-voip-dsp {
590 compatible = "qcom,msm-voip-dsp";
591 };
592
593 qcom,msm-pcm-voice {
594 compatible = "qcom,msm-pcm-voice";
595 };
596
Venkat Sudhire26f8c42013-01-14 16:53:35 -0800597 qcom,msm-stub-codec {
598 compatible = "qcom,msm-stub-codec";
599 };
600
Venkat Sudhir49965c72012-10-23 14:06:10 -0700601 qcom,msm-dai-fe {
602 compatible = "qcom,msm-dai-fe";
603 };
604
605 qcom,msm-pcm-afe {
606 compatible = "qcom,msm-pcm-afe";
607 };
608
609 qcom,msm-pcm-hostless {
610 compatible = "qcom,msm-pcm-hostless";
611 };
612
Venkat Sudhire26f8c42013-01-14 16:53:35 -0800613 qcom,msm-dai-q6 {
614 compatible = "qcom,msm-dai-q6";
615 qcom,msm-dai-q6-be-afe-pcm-rx {
616 compatible = "qcom,msm-dai-q6-dev";
617 qcom,msm-dai-q6-dev-id = <224>;
618 };
619
620 qcom,msm-dai-q6-be-afe-pcm-tx {
621 compatible = "qcom,msm-dai-q6-dev";
622 qcom,msm-dai-q6-dev-id = <225>;
623 };
624
625 qcom,msm-dai-q6-afe-proxy-rx {
626 compatible = "qcom,msm-dai-q6-dev";
627 qcom,msm-dai-q6-dev-id = <241>;
628 };
629
630 qcom,msm-dai-q6-afe-proxy-tx {
631 compatible = "qcom,msm-dai-q6-dev";
632 qcom,msm-dai-q6-dev-id = <240>;
633 };
634 };
Venkat Sudhire8320292013-01-17 13:45:15 -0800635 qcom,msm-pcm-dtmf {
636 compatible = "qcom,msm-pcm-dtmf";
637 };
638
639 qcom,msm-dai-stub {
640 compatible = "qcom,msm-dai-stub";
641 };
642
643 qcom,msm-stub-codec {
644 compatible = "qcom,msm-stub-codec";
645 };
Venkat Sudhire26f8c42013-01-14 16:53:35 -0800646
Prashanth Reddyf9536572013-02-13 12:17:08 -0800647 qcom,msm-auxpcm {
648 compatible = "qcom,msm-auxpcm-resource";
649 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
650 qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
651 qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
652 qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
653 qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
654 qcom,msm-cpudai-auxpcm-slot = <1>, <1>;
655 qcom,msm-cpudai-auxpcm-data = <0>, <0>;
656 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
657
658 qcom,msm-auxpcm-rx {
659 qcom,msm-auxpcm-dev-id = <4106>;
660 compatible = "qcom,msm-auxpcm-dev";
661 };
662
663 qcom,msm-auxpcm-tx {
664 qcom,msm-auxpcm-dev-id = <4107>;
665 compatible = "qcom,msm-auxpcm-dev";
666 };
667 };
668
Venkat Sudhir49965c72012-10-23 14:06:10 -0700669 qcom,msm-dai-mi2s {
670 compatible = "qcom,msm-dai-mi2s";
671 qcom,msm-dai-q6-mi2s-prim {
672 compatible = "qcom,msm-dai-q6-mi2s";
673 qcom,msm-dai-q6-mi2s-dev-id = <0>;
674 qcom,msm-mi2s-rx-lines = <2>;
675 qcom,msm-mi2s-tx-lines = <1>;
676 };
677 };
678
679 qcom,msm-dai-q6 {
680 compatible = "qcom,msm-dai-q6";
681 };
Vikram Mulukutla7f4ed0d2012-11-05 15:26:51 -0800682
683 qcom,mss {
684 compatible = "qcom,pil-q6v5-mss";
685 interrupts = <0 24 1>;
Seemanta Dutta519dfd12013-01-22 17:34:36 -0800686
687 /* GPIO input from mss */
688 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
689
690 /* GPIO output to mss */
691 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Vikram Mulukutla7f4ed0d2012-11-05 15:26:51 -0800692 };
Jeff Hugo27a6cf02012-11-29 15:46:50 -0700693
694 qcom,smem@fa00000 {
695 compatible = "qcom,smem";
696 reg = <0xfa00000 0x200000>,
Stepan Moskovchenkod6ee8262013-02-06 11:26:05 -0800697 <0xf9011000 0x1000>,
Jeff Hugo27a6cf02012-11-29 15:46:50 -0700698 <0xfc428000 0x4000>;
699 reg-names = "smem", "irq-reg-base", "aux-mem1";
700
701 qcom,smd-modem {
702 compatible = "qcom,smd";
703 qcom,smd-edge = <0>;
704 qcom,smd-irq-offset = <0x8>;
705 qcom,smd-irq-bitmask = <0x1000>;
706 qcom,pil-string = "modem";
707 interrupts = <0 25 1>;
708 };
709
710 qcom,smsm-modem {
711 compatible = "qcom,smsm";
712 qcom,smsm-edge = <0>;
713 qcom,smsm-irq-offset = <0x8>;
714 qcom,smsm-irq-bitmask = <0x2000>;
715 interrupts = <0 26 1>;
716 };
717
718 qcom,smd-adsp {
719 compatible = "qcom,smd";
720 qcom,smd-edge = <1>;
721 qcom,smd-irq-offset = <0x8>;
722 qcom,smd-irq-bitmask = <0x100>;
723 qcom,pil-string = "adsp";
724 interrupts = <0 156 1>;
725 };
726
727 qcom,smsm-adsp {
728 compatible = "qcom,smsm";
729 qcom,smsm-edge = <1>;
730 qcom,smsm-irq-offset = <0x8>;
731 qcom,smsm-irq-bitmask = <0x200>;
732 interrupts = <0 157 1>;
733 };
734
735 qcom,smd-rpm {
736 compatible = "qcom,smd";
737 qcom,smd-edge = <15>;
738 qcom,smd-irq-offset = <0x8>;
739 qcom,smd-irq-bitmask = <0x1>;
740 interrupts = <0 168 1>;
741 qcom,irq-no-suspend;
742 };
743 };
Hariprasad Dhalinarasimhaf4a5b0c2012-11-21 17:49:19 -0800744
745 qcom,qcedev@fd400000 {
746 compatible = "qcom,qcedev";
747 reg = <0xfd400000 0x20000>,
748 <0xfd404000 0x8000>;
749 reg-names = "crypto-base","crypto-bam-base";
750 interrupts = <0 207 0>;
751 qcom,bam-pipe-pair = <1>;
752 };
753
754 qcom,qcrypto@fd440000 {
755 compatible = "qcom,qcrypto";
756 reg = <0xfd400000 0x20000>,
757 <0xfd404000 0x8000>;
758 reg-names = "crypto-base","crypto-bam-base";
759 interrupts = <0 207 0>;
760 qcom,bam-pipe-pair = <2>;
761 };
762
Pushkar Joshi70210812012-12-15 19:01:39 -0800763 jtag_mm: jtagmm@fc332000 {
764 compatible = "qcom,jtag-mm";
765 reg = <0xfc332000 0x1000>,
766 <0xfc330000 0x1000>;
767 reg-names = "etm-base","debug-base";
768 };
Pushkar Joshi30306d32013-01-16 17:00:26 -0800769
770 qcom,msm-rtb {
771 compatible = "qcom,msm-rtb";
772 qcom,memory-reservation-type = "EBI1";
773 qcom,memory-reservation-size = <0x1000>; /* 4K EBI1 buffer */
774 };
Neeti Desai2036e122012-11-30 14:24:13 -0800775
776 qcom,msm-mem-hole {
777 compatible = "qcom,msm-mem-hole";
778 qcom,memblock-remove = <0x1f00000 0x5700000>; /* Address and Size of Hole */
779 };
780
Jeff Hugo96766e22013-03-06 13:52:37 -0700781 sfpb_spinlock: qcom,ipc-spinlock@fd484000 {
782 compatible = "qcom,ipc-spinlock-sfpb";
Jeff Hugo86a55b22013-03-14 14:51:30 -0600783 reg = <0xfd484000 0x400>;
784 qcom,num-locks = <8>;
Jeff Hugo96766e22013-03-06 13:52:37 -0700785 };
786
787 ldrex_spinlock: qcom,ipc-spinlock@fa00000 {
788 compatible = "qcom,ipc-spinlock-ldrex";
789 reg = <0xfa00000 0x200000>;
790 status = "disable";
791 };
792
Ashwin Chaugule50d59892013-03-12 12:58:51 -0400793 cpu-pmu {
794 compatible = "arm,cortex-a5-pmu";
795 qcom,irq-is-percpu;
796 interrupts = <1 7 0x00>;
797 };
798
799 l2-pmu {
800 compatible = "qcom,l2-pmu";
801 interrupts = <0 1 0>;
802 };
803
Rohit Vaswani3fc60342012-04-23 18:55:15 -0700804};
David Collinsa2b73f22012-09-13 17:32:16 -0700805
David Collins722a6512012-09-14 11:09:18 -0700806/include/ "msm-pm8019-rpm-regulator.dtsi"
David Collinsa2b73f22012-09-13 17:32:16 -0700807/include/ "msm-pm8019.dtsi"
David Collins56b41122012-09-24 17:09:23 -0700808/include/ "msm9625-regulator.dtsi"
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700809
810&pm8019_vadc {
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800811 chan@31 {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700812 label = "batt_id_therm";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800813 reg = <0x31>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700814 qcom,decimation = <0>;
815 qcom,pre-div-channel-scaling = <0>;
816 qcom,calibration-type = "ratiometric";
817 qcom,scale-function = <0>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800818 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700819 qcom,fast-avg-setup = <0>;
820 };
821
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800822 chan@33 {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700823 label = "pa_therm1";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800824 reg = <0x33>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700825 qcom,decimation = <0>;
826 qcom,pre-div-channel-scaling = <0>;
827 qcom,calibration-type = "ratiometric";
828 qcom,scale-function = <2>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800829 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700830 qcom,fast-avg-setup = <0>;
831 };
832
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800833 chan@34 {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700834 label = "pa_therm2";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800835 reg = <0x34>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700836 qcom,decimation = <0>;
837 qcom,pre-div-channel-scaling = <0>;
838 qcom,calibration-type = "ratiometric";
839 qcom,scale-function = <2>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800840 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700841 qcom,fast-avg-setup = <0>;
842 };
843
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800844 chan@32 {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700845 label = "xo_therm";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800846 reg = <0x32>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700847 qcom,decimation = <0>;
848 qcom,pre-div-channel-scaling = <0>;
849 qcom,calibration-type = "ratiometric";
850 qcom,scale-function = <4>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800851 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700852 qcom,fast-avg-setup = <0>;
853 };
854
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800855 chan@3c {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700856 label = "xo_therm_amux";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800857 reg = <0x3c>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700858 qcom,decimation = <0>;
859 qcom,pre-div-channel-scaling = <0>;
860 qcom,calibration-type = "ratiometric";
861 qcom,scale-function = <4>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800862 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700863 qcom,fast-avg-setup = <0>;
864 };
865};