Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/ctype.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/spinlock.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/clk.h> |
Vikram Mulukutla | 14ee37d | 2012-08-08 15:18:09 -0700 | [diff] [blame] | 21 | #include <linux/iopoll.h> |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 22 | |
| 23 | #include <mach/clk.h> |
Vikram Mulukutla | b7a1a74 | 2012-05-30 17:24:33 -0700 | [diff] [blame] | 24 | #include <mach/rpm-regulator-smd.h> |
Vikram Mulukutla | 19245e0 | 2012-07-23 15:58:04 -0700 | [diff] [blame] | 25 | #include <mach/socinfo.h> |
Vikram Mulukutla | 77140da | 2012-08-13 21:37:18 -0700 | [diff] [blame] | 26 | #include <mach/rpm-smd.h> |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 27 | |
| 28 | #include "clock-local2.h" |
| 29 | #include "clock-pll.h" |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 30 | #include "clock-rpm.h" |
| 31 | #include "clock-voter.h" |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 32 | #include "clock-mdss-8974.h" |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 33 | |
| 34 | enum { |
| 35 | GCC_BASE, |
| 36 | MMSS_BASE, |
| 37 | LPASS_BASE, |
| 38 | MSS_BASE, |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 39 | APCS_BASE, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 40 | N_BASES, |
| 41 | }; |
| 42 | |
| 43 | static void __iomem *virt_bases[N_BASES]; |
| 44 | |
| 45 | #define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x)) |
| 46 | #define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x)) |
| 47 | #define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x)) |
| 48 | #define MSS_REG_BASE(x) (void __iomem *)(virt_bases[MSS_BASE] + (x)) |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 49 | #define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x)) |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 50 | |
| 51 | #define GPLL0_MODE_REG 0x0000 |
| 52 | #define GPLL0_L_REG 0x0004 |
| 53 | #define GPLL0_M_REG 0x0008 |
| 54 | #define GPLL0_N_REG 0x000C |
| 55 | #define GPLL0_USER_CTL_REG 0x0010 |
| 56 | #define GPLL0_CONFIG_CTL_REG 0x0014 |
| 57 | #define GPLL0_TEST_CTL_REG 0x0018 |
| 58 | #define GPLL0_STATUS_REG 0x001C |
| 59 | |
| 60 | #define GPLL1_MODE_REG 0x0040 |
| 61 | #define GPLL1_L_REG 0x0044 |
| 62 | #define GPLL1_M_REG 0x0048 |
| 63 | #define GPLL1_N_REG 0x004C |
| 64 | #define GPLL1_USER_CTL_REG 0x0050 |
| 65 | #define GPLL1_CONFIG_CTL_REG 0x0054 |
| 66 | #define GPLL1_TEST_CTL_REG 0x0058 |
| 67 | #define GPLL1_STATUS_REG 0x005C |
| 68 | |
| 69 | #define MMPLL0_MODE_REG 0x0000 |
| 70 | #define MMPLL0_L_REG 0x0004 |
| 71 | #define MMPLL0_M_REG 0x0008 |
| 72 | #define MMPLL0_N_REG 0x000C |
| 73 | #define MMPLL0_USER_CTL_REG 0x0010 |
| 74 | #define MMPLL0_CONFIG_CTL_REG 0x0014 |
| 75 | #define MMPLL0_TEST_CTL_REG 0x0018 |
| 76 | #define MMPLL0_STATUS_REG 0x001C |
| 77 | |
| 78 | #define MMPLL1_MODE_REG 0x0040 |
| 79 | #define MMPLL1_L_REG 0x0044 |
| 80 | #define MMPLL1_M_REG 0x0048 |
| 81 | #define MMPLL1_N_REG 0x004C |
| 82 | #define MMPLL1_USER_CTL_REG 0x0050 |
| 83 | #define MMPLL1_CONFIG_CTL_REG 0x0054 |
| 84 | #define MMPLL1_TEST_CTL_REG 0x0058 |
| 85 | #define MMPLL1_STATUS_REG 0x005C |
| 86 | |
| 87 | #define MMPLL3_MODE_REG 0x0080 |
| 88 | #define MMPLL3_L_REG 0x0084 |
| 89 | #define MMPLL3_M_REG 0x0088 |
| 90 | #define MMPLL3_N_REG 0x008C |
| 91 | #define MMPLL3_USER_CTL_REG 0x0090 |
| 92 | #define MMPLL3_CONFIG_CTL_REG 0x0094 |
| 93 | #define MMPLL3_TEST_CTL_REG 0x0098 |
| 94 | #define MMPLL3_STATUS_REG 0x009C |
| 95 | |
| 96 | #define LPAPLL_MODE_REG 0x0000 |
| 97 | #define LPAPLL_L_REG 0x0004 |
| 98 | #define LPAPLL_M_REG 0x0008 |
| 99 | #define LPAPLL_N_REG 0x000C |
| 100 | #define LPAPLL_USER_CTL_REG 0x0010 |
| 101 | #define LPAPLL_CONFIG_CTL_REG 0x0014 |
| 102 | #define LPAPLL_TEST_CTL_REG 0x0018 |
| 103 | #define LPAPLL_STATUS_REG 0x001C |
| 104 | |
| 105 | #define GCC_DEBUG_CLK_CTL_REG 0x1880 |
| 106 | #define CLOCK_FRQ_MEASURE_CTL_REG 0x1884 |
| 107 | #define CLOCK_FRQ_MEASURE_STATUS_REG 0x1888 |
| 108 | #define GCC_XO_DIV4_CBCR_REG 0x10C8 |
Matt Wagantall | 9a9b6f0 | 2012-08-07 23:12:26 -0700 | [diff] [blame] | 109 | #define GCC_PLLTEST_PAD_CFG_REG 0x188C |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 110 | #define APCS_GPLL_ENA_VOTE_REG 0x1480 |
| 111 | #define MMSS_PLL_VOTE_APCS_REG 0x0100 |
| 112 | #define MMSS_DEBUG_CLK_CTL_REG 0x0900 |
| 113 | #define LPASS_DEBUG_CLK_CTL_REG 0x29000 |
| 114 | #define LPASS_LPA_PLL_VOTE_APPS_REG 0x2000 |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 115 | #define MSS_DEBUG_CLK_CTL_REG 0x0078 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 116 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 117 | #define GLB_CLK_DIAG_REG 0x001C |
| 118 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 119 | #define USB30_MASTER_CMD_RCGR 0x03D4 |
| 120 | #define USB30_MOCK_UTMI_CMD_RCGR 0x03E8 |
| 121 | #define USB_HSIC_SYSTEM_CMD_RCGR 0x041C |
| 122 | #define USB_HSIC_CMD_RCGR 0x0440 |
| 123 | #define USB_HSIC_IO_CAL_CMD_RCGR 0x0458 |
| 124 | #define USB_HS_SYSTEM_CMD_RCGR 0x0490 |
Vikram Mulukutla | 3b98a6d | 2012-08-15 20:35:25 -0700 | [diff] [blame] | 125 | #define SYS_NOC_USB3_AXI_CBCR 0x0108 |
| 126 | #define USB30_SLEEP_CBCR 0x03CC |
| 127 | #define USB2A_PHY_SLEEP_CBCR 0x04AC |
| 128 | #define USB2B_PHY_SLEEP_CBCR 0x04B4 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 129 | #define SDCC1_APPS_CMD_RCGR 0x04D0 |
| 130 | #define SDCC2_APPS_CMD_RCGR 0x0510 |
| 131 | #define SDCC3_APPS_CMD_RCGR 0x0550 |
| 132 | #define SDCC4_APPS_CMD_RCGR 0x0590 |
| 133 | #define BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x064C |
| 134 | #define BLSP1_UART1_APPS_CMD_RCGR 0x068C |
| 135 | #define BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x06CC |
| 136 | #define BLSP1_UART2_APPS_CMD_RCGR 0x070C |
| 137 | #define BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x074C |
| 138 | #define BLSP1_UART3_APPS_CMD_RCGR 0x078C |
| 139 | #define BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x07CC |
| 140 | #define BLSP1_UART4_APPS_CMD_RCGR 0x080C |
| 141 | #define BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x084C |
| 142 | #define BLSP1_UART5_APPS_CMD_RCGR 0x088C |
| 143 | #define BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x08CC |
| 144 | #define BLSP1_UART6_APPS_CMD_RCGR 0x090C |
| 145 | #define BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x098C |
| 146 | #define BLSP2_UART1_APPS_CMD_RCGR 0x09CC |
| 147 | #define BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x0A0C |
| 148 | #define BLSP2_UART2_APPS_CMD_RCGR 0x0A4C |
| 149 | #define BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x0A8C |
| 150 | #define BLSP2_UART3_APPS_CMD_RCGR 0x0ACC |
| 151 | #define BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x0B0C |
| 152 | #define BLSP2_UART4_APPS_CMD_RCGR 0x0B4C |
| 153 | #define BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x0B8C |
| 154 | #define BLSP2_UART5_APPS_CMD_RCGR 0x0BCC |
| 155 | #define BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x0C0C |
| 156 | #define BLSP2_UART6_APPS_CMD_RCGR 0x0C4C |
| 157 | #define PDM2_CMD_RCGR 0x0CD0 |
| 158 | #define TSIF_REF_CMD_RCGR 0x0D90 |
| 159 | #define CE1_CMD_RCGR 0x1050 |
| 160 | #define CE2_CMD_RCGR 0x1090 |
| 161 | #define GP1_CMD_RCGR 0x1904 |
| 162 | #define GP2_CMD_RCGR 0x1944 |
| 163 | #define GP3_CMD_RCGR 0x1984 |
| 164 | #define LPAIF_SPKR_CMD_RCGR 0xA000 |
| 165 | #define LPAIF_PRI_CMD_RCGR 0xB000 |
| 166 | #define LPAIF_SEC_CMD_RCGR 0xC000 |
| 167 | #define LPAIF_TER_CMD_RCGR 0xD000 |
| 168 | #define LPAIF_QUAD_CMD_RCGR 0xE000 |
| 169 | #define LPAIF_PCM0_CMD_RCGR 0xF000 |
| 170 | #define LPAIF_PCM1_CMD_RCGR 0x10000 |
| 171 | #define RESAMPLER_CMD_RCGR 0x11000 |
| 172 | #define SLIMBUS_CMD_RCGR 0x12000 |
| 173 | #define LPAIF_PCMOE_CMD_RCGR 0x13000 |
| 174 | #define AHBFABRIC_CMD_RCGR 0x18000 |
| 175 | #define VCODEC0_CMD_RCGR 0x1000 |
| 176 | #define PCLK0_CMD_RCGR 0x2000 |
| 177 | #define PCLK1_CMD_RCGR 0x2020 |
| 178 | #define MDP_CMD_RCGR 0x2040 |
| 179 | #define EXTPCLK_CMD_RCGR 0x2060 |
| 180 | #define VSYNC_CMD_RCGR 0x2080 |
| 181 | #define EDPPIXEL_CMD_RCGR 0x20A0 |
| 182 | #define EDPLINK_CMD_RCGR 0x20C0 |
| 183 | #define EDPAUX_CMD_RCGR 0x20E0 |
| 184 | #define HDMI_CMD_RCGR 0x2100 |
| 185 | #define BYTE0_CMD_RCGR 0x2120 |
| 186 | #define BYTE1_CMD_RCGR 0x2140 |
| 187 | #define ESC0_CMD_RCGR 0x2160 |
| 188 | #define ESC1_CMD_RCGR 0x2180 |
| 189 | #define CSI0PHYTIMER_CMD_RCGR 0x3000 |
| 190 | #define CSI1PHYTIMER_CMD_RCGR 0x3030 |
| 191 | #define CSI2PHYTIMER_CMD_RCGR 0x3060 |
| 192 | #define CSI0_CMD_RCGR 0x3090 |
| 193 | #define CSI1_CMD_RCGR 0x3100 |
| 194 | #define CSI2_CMD_RCGR 0x3160 |
| 195 | #define CSI3_CMD_RCGR 0x31C0 |
| 196 | #define CCI_CMD_RCGR 0x3300 |
| 197 | #define MCLK0_CMD_RCGR 0x3360 |
| 198 | #define MCLK1_CMD_RCGR 0x3390 |
| 199 | #define MCLK2_CMD_RCGR 0x33C0 |
| 200 | #define MCLK3_CMD_RCGR 0x33F0 |
| 201 | #define MMSS_GP0_CMD_RCGR 0x3420 |
| 202 | #define MMSS_GP1_CMD_RCGR 0x3450 |
| 203 | #define JPEG0_CMD_RCGR 0x3500 |
| 204 | #define JPEG1_CMD_RCGR 0x3520 |
| 205 | #define JPEG2_CMD_RCGR 0x3540 |
| 206 | #define VFE0_CMD_RCGR 0x3600 |
| 207 | #define VFE1_CMD_RCGR 0x3620 |
| 208 | #define CPP_CMD_RCGR 0x3640 |
| 209 | #define GFX3D_CMD_RCGR 0x4000 |
| 210 | #define RBCPR_CMD_RCGR 0x4060 |
| 211 | #define AHB_CMD_RCGR 0x5000 |
| 212 | #define AXI_CMD_RCGR 0x5040 |
| 213 | #define OCMEMNOC_CMD_RCGR 0x5090 |
Vikram Mulukutla | 274b2d9 | 2012-07-13 15:53:04 -0700 | [diff] [blame] | 214 | #define OCMEMCX_OCMEMNOC_CBCR 0x4058 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 215 | |
| 216 | #define MMSS_BCR 0x0240 |
| 217 | #define USB_30_BCR 0x03C0 |
| 218 | #define USB3_PHY_BCR 0x03FC |
| 219 | #define USB_HS_HSIC_BCR 0x0400 |
| 220 | #define USB_HS_BCR 0x0480 |
| 221 | #define SDCC1_BCR 0x04C0 |
| 222 | #define SDCC2_BCR 0x0500 |
| 223 | #define SDCC3_BCR 0x0540 |
| 224 | #define SDCC4_BCR 0x0580 |
| 225 | #define BLSP1_BCR 0x05C0 |
| 226 | #define BLSP1_QUP1_BCR 0x0640 |
| 227 | #define BLSP1_UART1_BCR 0x0680 |
| 228 | #define BLSP1_QUP2_BCR 0x06C0 |
| 229 | #define BLSP1_UART2_BCR 0x0700 |
| 230 | #define BLSP1_QUP3_BCR 0x0740 |
| 231 | #define BLSP1_UART3_BCR 0x0780 |
| 232 | #define BLSP1_QUP4_BCR 0x07C0 |
| 233 | #define BLSP1_UART4_BCR 0x0800 |
| 234 | #define BLSP1_QUP5_BCR 0x0840 |
| 235 | #define BLSP1_UART5_BCR 0x0880 |
| 236 | #define BLSP1_QUP6_BCR 0x08C0 |
| 237 | #define BLSP1_UART6_BCR 0x0900 |
| 238 | #define BLSP2_BCR 0x0940 |
| 239 | #define BLSP2_QUP1_BCR 0x0980 |
| 240 | #define BLSP2_UART1_BCR 0x09C0 |
| 241 | #define BLSP2_QUP2_BCR 0x0A00 |
| 242 | #define BLSP2_UART2_BCR 0x0A40 |
| 243 | #define BLSP2_QUP3_BCR 0x0A80 |
| 244 | #define BLSP2_UART3_BCR 0x0AC0 |
| 245 | #define BLSP2_QUP4_BCR 0x0B00 |
| 246 | #define BLSP2_UART4_BCR 0x0B40 |
| 247 | #define BLSP2_QUP5_BCR 0x0B80 |
| 248 | #define BLSP2_UART5_BCR 0x0BC0 |
| 249 | #define BLSP2_QUP6_BCR 0x0C00 |
| 250 | #define BLSP2_UART6_BCR 0x0C40 |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 251 | #define BOOT_ROM_BCR 0x0E00 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 252 | #define PDM_BCR 0x0CC0 |
| 253 | #define PRNG_BCR 0x0D00 |
| 254 | #define BAM_DMA_BCR 0x0D40 |
| 255 | #define TSIF_BCR 0x0D80 |
| 256 | #define CE1_BCR 0x1040 |
| 257 | #define CE2_BCR 0x1080 |
| 258 | #define AUDIO_CORE_BCR 0x4000 |
| 259 | #define VENUS0_BCR 0x1020 |
| 260 | #define MDSS_BCR 0x2300 |
| 261 | #define CAMSS_PHY0_BCR 0x3020 |
| 262 | #define CAMSS_PHY1_BCR 0x3050 |
| 263 | #define CAMSS_PHY2_BCR 0x3080 |
| 264 | #define CAMSS_CSI0_BCR 0x30B0 |
| 265 | #define CAMSS_CSI0PHY_BCR 0x30C0 |
| 266 | #define CAMSS_CSI0RDI_BCR 0x30D0 |
| 267 | #define CAMSS_CSI0PIX_BCR 0x30E0 |
| 268 | #define CAMSS_CSI1_BCR 0x3120 |
| 269 | #define CAMSS_CSI1PHY_BCR 0x3130 |
| 270 | #define CAMSS_CSI1RDI_BCR 0x3140 |
| 271 | #define CAMSS_CSI1PIX_BCR 0x3150 |
| 272 | #define CAMSS_CSI2_BCR 0x3180 |
| 273 | #define CAMSS_CSI2PHY_BCR 0x3190 |
| 274 | #define CAMSS_CSI2RDI_BCR 0x31A0 |
| 275 | #define CAMSS_CSI2PIX_BCR 0x31B0 |
| 276 | #define CAMSS_CSI3_BCR 0x31E0 |
| 277 | #define CAMSS_CSI3PHY_BCR 0x31F0 |
| 278 | #define CAMSS_CSI3RDI_BCR 0x3200 |
| 279 | #define CAMSS_CSI3PIX_BCR 0x3210 |
| 280 | #define CAMSS_ISPIF_BCR 0x3220 |
| 281 | #define CAMSS_CCI_BCR 0x3340 |
| 282 | #define CAMSS_MCLK0_BCR 0x3380 |
| 283 | #define CAMSS_MCLK1_BCR 0x33B0 |
| 284 | #define CAMSS_MCLK2_BCR 0x33E0 |
| 285 | #define CAMSS_MCLK3_BCR 0x3410 |
| 286 | #define CAMSS_GP0_BCR 0x3440 |
| 287 | #define CAMSS_GP1_BCR 0x3470 |
| 288 | #define CAMSS_TOP_BCR 0x3480 |
| 289 | #define CAMSS_MICRO_BCR 0x3490 |
| 290 | #define CAMSS_JPEG_BCR 0x35A0 |
| 291 | #define CAMSS_VFE_BCR 0x36A0 |
| 292 | #define CAMSS_CSI_VFE0_BCR 0x3700 |
| 293 | #define CAMSS_CSI_VFE1_BCR 0x3710 |
| 294 | #define OCMEMNOC_BCR 0x50B0 |
| 295 | #define MMSSNOCAHB_BCR 0x5020 |
| 296 | #define MMSSNOCAXI_BCR 0x5060 |
| 297 | #define OXILI_GFX3D_CBCR 0x4028 |
| 298 | #define OXILICX_AHB_CBCR 0x403C |
| 299 | #define OXILICX_AXI_CBCR 0x4038 |
| 300 | #define OXILI_BCR 0x4020 |
| 301 | #define OXILICX_BCR 0x4030 |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 302 | #define LPASS_Q6SS_BCR 0x6000 |
| 303 | #define MSS_Q6SS_BCR 0x1068 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 304 | |
| 305 | #define OCMEM_SYS_NOC_AXI_CBCR 0x0244 |
| 306 | #define OCMEM_NOC_CFG_AHB_CBCR 0x0248 |
| 307 | #define MMSS_NOC_CFG_AHB_CBCR 0x024C |
| 308 | |
| 309 | #define USB30_MASTER_CBCR 0x03C8 |
| 310 | #define USB30_MOCK_UTMI_CBCR 0x03D0 |
| 311 | #define USB_HSIC_AHB_CBCR 0x0408 |
| 312 | #define USB_HSIC_SYSTEM_CBCR 0x040C |
| 313 | #define USB_HSIC_CBCR 0x0410 |
| 314 | #define USB_HSIC_IO_CAL_CBCR 0x0414 |
| 315 | #define USB_HS_SYSTEM_CBCR 0x0484 |
| 316 | #define USB_HS_AHB_CBCR 0x0488 |
| 317 | #define SDCC1_APPS_CBCR 0x04C4 |
| 318 | #define SDCC1_AHB_CBCR 0x04C8 |
| 319 | #define SDCC2_APPS_CBCR 0x0504 |
| 320 | #define SDCC2_AHB_CBCR 0x0508 |
| 321 | #define SDCC3_APPS_CBCR 0x0544 |
| 322 | #define SDCC3_AHB_CBCR 0x0548 |
| 323 | #define SDCC4_APPS_CBCR 0x0584 |
| 324 | #define SDCC4_AHB_CBCR 0x0588 |
| 325 | #define BLSP1_AHB_CBCR 0x05C4 |
| 326 | #define BLSP1_QUP1_SPI_APPS_CBCR 0x0644 |
| 327 | #define BLSP1_QUP1_I2C_APPS_CBCR 0x0648 |
| 328 | #define BLSP1_UART1_APPS_CBCR 0x0684 |
| 329 | #define BLSP1_UART1_SIM_CBCR 0x0688 |
| 330 | #define BLSP1_QUP2_SPI_APPS_CBCR 0x06C4 |
| 331 | #define BLSP1_QUP2_I2C_APPS_CBCR 0x06C8 |
| 332 | #define BLSP1_UART2_APPS_CBCR 0x0704 |
| 333 | #define BLSP1_UART2_SIM_CBCR 0x0708 |
| 334 | #define BLSP1_QUP3_SPI_APPS_CBCR 0x0744 |
| 335 | #define BLSP1_QUP3_I2C_APPS_CBCR 0x0748 |
| 336 | #define BLSP1_UART3_APPS_CBCR 0x0784 |
| 337 | #define BLSP1_UART3_SIM_CBCR 0x0788 |
| 338 | #define BLSP1_QUP4_SPI_APPS_CBCR 0x07C4 |
| 339 | #define BLSP1_QUP4_I2C_APPS_CBCR 0x07C8 |
| 340 | #define BLSP1_UART4_APPS_CBCR 0x0804 |
| 341 | #define BLSP1_UART4_SIM_CBCR 0x0808 |
| 342 | #define BLSP1_QUP5_SPI_APPS_CBCR 0x0844 |
| 343 | #define BLSP1_QUP5_I2C_APPS_CBCR 0x0848 |
| 344 | #define BLSP1_UART5_APPS_CBCR 0x0884 |
| 345 | #define BLSP1_UART5_SIM_CBCR 0x0888 |
| 346 | #define BLSP1_QUP6_SPI_APPS_CBCR 0x08C4 |
| 347 | #define BLSP1_QUP6_I2C_APPS_CBCR 0x08C8 |
| 348 | #define BLSP1_UART6_APPS_CBCR 0x0904 |
| 349 | #define BLSP1_UART6_SIM_CBCR 0x0908 |
| 350 | #define BLSP2_AHB_CBCR 0x0944 |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 351 | #define BOOT_ROM_AHB_CBCR 0x0E04 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 352 | #define BLSP2_QUP1_SPI_APPS_CBCR 0x0984 |
| 353 | #define BLSP2_QUP1_I2C_APPS_CBCR 0x0988 |
| 354 | #define BLSP2_UART1_APPS_CBCR 0x09C4 |
| 355 | #define BLSP2_UART1_SIM_CBCR 0x09C8 |
| 356 | #define BLSP2_QUP2_SPI_APPS_CBCR 0x0A04 |
| 357 | #define BLSP2_QUP2_I2C_APPS_CBCR 0x0A08 |
| 358 | #define BLSP2_UART2_APPS_CBCR 0x0A44 |
| 359 | #define BLSP2_UART2_SIM_CBCR 0x0A48 |
| 360 | #define BLSP2_QUP3_SPI_APPS_CBCR 0x0A84 |
| 361 | #define BLSP2_QUP3_I2C_APPS_CBCR 0x0A88 |
| 362 | #define BLSP2_UART3_APPS_CBCR 0x0AC4 |
| 363 | #define BLSP2_UART3_SIM_CBCR 0x0AC8 |
| 364 | #define BLSP2_QUP4_SPI_APPS_CBCR 0x0B04 |
| 365 | #define BLSP2_QUP4_I2C_APPS_CBCR 0x0B08 |
| 366 | #define BLSP2_UART4_APPS_CBCR 0x0B44 |
| 367 | #define BLSP2_UART4_SIM_CBCR 0x0B48 |
| 368 | #define BLSP2_QUP5_SPI_APPS_CBCR 0x0B84 |
| 369 | #define BLSP2_QUP5_I2C_APPS_CBCR 0x0B88 |
| 370 | #define BLSP2_UART5_APPS_CBCR 0x0BC4 |
| 371 | #define BLSP2_UART5_SIM_CBCR 0x0BC8 |
| 372 | #define BLSP2_QUP6_SPI_APPS_CBCR 0x0C04 |
| 373 | #define BLSP2_QUP6_I2C_APPS_CBCR 0x0C08 |
| 374 | #define BLSP2_UART6_APPS_CBCR 0x0C44 |
| 375 | #define BLSP2_UART6_SIM_CBCR 0x0C48 |
| 376 | #define PDM_AHB_CBCR 0x0CC4 |
| 377 | #define PDM_XO4_CBCR 0x0CC8 |
| 378 | #define PDM2_CBCR 0x0CCC |
| 379 | #define PRNG_AHB_CBCR 0x0D04 |
| 380 | #define BAM_DMA_AHB_CBCR 0x0D44 |
| 381 | #define TSIF_AHB_CBCR 0x0D84 |
| 382 | #define TSIF_REF_CBCR 0x0D88 |
| 383 | #define MSG_RAM_AHB_CBCR 0x0E44 |
| 384 | #define CE1_CBCR 0x1044 |
| 385 | #define CE1_AXI_CBCR 0x1048 |
| 386 | #define CE1_AHB_CBCR 0x104C |
| 387 | #define CE2_CBCR 0x1084 |
| 388 | #define CE2_AXI_CBCR 0x1088 |
| 389 | #define CE2_AHB_CBCR 0x108C |
| 390 | #define GCC_AHB_CBCR 0x10C0 |
| 391 | #define GP1_CBCR 0x1900 |
| 392 | #define GP2_CBCR 0x1940 |
| 393 | #define GP3_CBCR 0x1980 |
Vikram Mulukutla | 14ee37d | 2012-08-08 15:18:09 -0700 | [diff] [blame] | 394 | #define AUDIO_CORE_GDSCR 0x7000 |
Vikram Mulukutla | 6c0f1a7 | 2012-08-10 01:59:28 -0700 | [diff] [blame] | 395 | #define AUDIO_CORE_IXFABRIC_CBCR 0x1B000 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 396 | #define AUDIO_CORE_LPAIF_CODEC_SPKR_OSR_CBCR 0xA014 |
| 397 | #define AUDIO_CORE_LPAIF_CODEC_SPKR_IBIT_CBCR 0xA018 |
| 398 | #define AUDIO_CORE_LPAIF_CODEC_SPKR_EBIT_CBCR 0xA01C |
| 399 | #define AUDIO_CORE_LPAIF_PRI_OSR_CBCR 0xB014 |
| 400 | #define AUDIO_CORE_LPAIF_PRI_IBIT_CBCR 0xB018 |
| 401 | #define AUDIO_CORE_LPAIF_PRI_EBIT_CBCR 0xB01C |
| 402 | #define AUDIO_CORE_LPAIF_SEC_OSR_CBCR 0xC014 |
| 403 | #define AUDIO_CORE_LPAIF_SEC_IBIT_CBCR 0xC018 |
| 404 | #define AUDIO_CORE_LPAIF_SEC_EBIT_CBCR 0xC01C |
| 405 | #define AUDIO_CORE_LPAIF_TER_OSR_CBCR 0xD014 |
| 406 | #define AUDIO_CORE_LPAIF_TER_IBIT_CBCR 0xD018 |
| 407 | #define AUDIO_CORE_LPAIF_TER_EBIT_CBCR 0xD01C |
| 408 | #define AUDIO_CORE_LPAIF_QUAD_OSR_CBCR 0xE014 |
| 409 | #define AUDIO_CORE_LPAIF_QUAD_IBIT_CBCR 0xE018 |
| 410 | #define AUDIO_CORE_LPAIF_QUAD_EBIT_CBCR 0xE01C |
| 411 | #define AUDIO_CORE_LPAIF_PCM0_IBIT_CBCR 0xF014 |
| 412 | #define AUDIO_CORE_LPAIF_PCM0_EBIT_CBCR 0xF018 |
| 413 | #define AUDIO_CORE_LPAIF_PCM1_IBIT_CBCR 0x10014 |
| 414 | #define AUDIO_CORE_LPAIF_PCM1_EBIT_CBCR 0x10018 |
| 415 | #define AUDIO_CORE_RESAMPLER_CORE_CBCR 0x11014 |
| 416 | #define AUDIO_CORE_RESAMPLER_LFABIF_CBCR 0x11018 |
| 417 | #define AUDIO_CORE_SLIMBUS_CORE_CBCR 0x12014 |
| 418 | #define AUDIO_CORE_SLIMBUS_LFABIF_CBCR 0x12018 |
| 419 | #define AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR 0x13014 |
| 420 | #define VENUS0_VCODEC0_CBCR 0x1028 |
| 421 | #define VENUS0_AHB_CBCR 0x1030 |
| 422 | #define VENUS0_AXI_CBCR 0x1034 |
| 423 | #define VENUS0_OCMEMNOC_CBCR 0x1038 |
| 424 | #define MDSS_AHB_CBCR 0x2308 |
| 425 | #define MDSS_HDMI_AHB_CBCR 0x230C |
| 426 | #define MDSS_AXI_CBCR 0x2310 |
| 427 | #define MDSS_PCLK0_CBCR 0x2314 |
| 428 | #define MDSS_PCLK1_CBCR 0x2318 |
| 429 | #define MDSS_MDP_CBCR 0x231C |
| 430 | #define MDSS_MDP_LUT_CBCR 0x2320 |
| 431 | #define MDSS_EXTPCLK_CBCR 0x2324 |
| 432 | #define MDSS_VSYNC_CBCR 0x2328 |
| 433 | #define MDSS_EDPPIXEL_CBCR 0x232C |
| 434 | #define MDSS_EDPLINK_CBCR 0x2330 |
| 435 | #define MDSS_EDPAUX_CBCR 0x2334 |
| 436 | #define MDSS_HDMI_CBCR 0x2338 |
| 437 | #define MDSS_BYTE0_CBCR 0x233C |
| 438 | #define MDSS_BYTE1_CBCR 0x2340 |
| 439 | #define MDSS_ESC0_CBCR 0x2344 |
| 440 | #define MDSS_ESC1_CBCR 0x2348 |
| 441 | #define CAMSS_PHY0_CSI0PHYTIMER_CBCR 0x3024 |
| 442 | #define CAMSS_PHY1_CSI1PHYTIMER_CBCR 0x3054 |
| 443 | #define CAMSS_PHY2_CSI2PHYTIMER_CBCR 0x3084 |
| 444 | #define CAMSS_CSI0_CBCR 0x30B4 |
| 445 | #define CAMSS_CSI0_AHB_CBCR 0x30BC |
| 446 | #define CAMSS_CSI0PHY_CBCR 0x30C4 |
| 447 | #define CAMSS_CSI0RDI_CBCR 0x30D4 |
| 448 | #define CAMSS_CSI0PIX_CBCR 0x30E4 |
| 449 | #define CAMSS_CSI1_CBCR 0x3124 |
| 450 | #define CAMSS_CSI1_AHB_CBCR 0x3128 |
| 451 | #define CAMSS_CSI1PHY_CBCR 0x3134 |
| 452 | #define CAMSS_CSI1RDI_CBCR 0x3144 |
| 453 | #define CAMSS_CSI1PIX_CBCR 0x3154 |
| 454 | #define CAMSS_CSI2_CBCR 0x3184 |
| 455 | #define CAMSS_CSI2_AHB_CBCR 0x3188 |
| 456 | #define CAMSS_CSI2PHY_CBCR 0x3194 |
| 457 | #define CAMSS_CSI2RDI_CBCR 0x31A4 |
| 458 | #define CAMSS_CSI2PIX_CBCR 0x31B4 |
| 459 | #define CAMSS_CSI3_CBCR 0x31E4 |
| 460 | #define CAMSS_CSI3_AHB_CBCR 0x31E8 |
| 461 | #define CAMSS_CSI3PHY_CBCR 0x31F4 |
| 462 | #define CAMSS_CSI3RDI_CBCR 0x3204 |
| 463 | #define CAMSS_CSI3PIX_CBCR 0x3214 |
| 464 | #define CAMSS_ISPIF_AHB_CBCR 0x3224 |
| 465 | #define CAMSS_CCI_CCI_CBCR 0x3344 |
| 466 | #define CAMSS_CCI_CCI_AHB_CBCR 0x3348 |
| 467 | #define CAMSS_MCLK0_CBCR 0x3384 |
| 468 | #define CAMSS_MCLK1_CBCR 0x33B4 |
| 469 | #define CAMSS_MCLK2_CBCR 0x33E4 |
| 470 | #define CAMSS_MCLK3_CBCR 0x3414 |
| 471 | #define CAMSS_GP0_CBCR 0x3444 |
| 472 | #define CAMSS_GP1_CBCR 0x3474 |
| 473 | #define CAMSS_TOP_AHB_CBCR 0x3484 |
| 474 | #define CAMSS_MICRO_AHB_CBCR 0x3494 |
| 475 | #define CAMSS_JPEG_JPEG0_CBCR 0x35A8 |
| 476 | #define CAMSS_JPEG_JPEG1_CBCR 0x35AC |
| 477 | #define CAMSS_JPEG_JPEG2_CBCR 0x35B0 |
| 478 | #define CAMSS_JPEG_JPEG_AHB_CBCR 0x35B4 |
| 479 | #define CAMSS_JPEG_JPEG_AXI_CBCR 0x35B8 |
| 480 | #define CAMSS_JPEG_JPEG_OCMEMNOC_CBCR 0x35BC |
| 481 | #define CAMSS_VFE_VFE0_CBCR 0x36A8 |
| 482 | #define CAMSS_VFE_VFE1_CBCR 0x36AC |
| 483 | #define CAMSS_VFE_CPP_CBCR 0x36B0 |
| 484 | #define CAMSS_VFE_CPP_AHB_CBCR 0x36B4 |
| 485 | #define CAMSS_VFE_VFE_AHB_CBCR 0x36B8 |
| 486 | #define CAMSS_VFE_VFE_AXI_CBCR 0x36BC |
| 487 | #define CAMSS_VFE_VFE_OCMEMNOC_CBCR 0x36C0 |
| 488 | #define CAMSS_CSI_VFE0_CBCR 0x3704 |
| 489 | #define CAMSS_CSI_VFE1_CBCR 0x3714 |
| 490 | #define MMSS_MMSSNOC_AXI_CBCR 0x506C |
| 491 | #define MMSS_MMSSNOC_AHB_CBCR 0x5024 |
| 492 | #define MMSS_MMSSNOC_BTO_AHB_CBCR 0x5028 |
| 493 | #define MMSS_MISC_AHB_CBCR 0x502C |
| 494 | #define MMSS_S0_AXI_CBCR 0x5064 |
| 495 | #define OCMEMNOC_CBCR 0x50B4 |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 496 | #define LPASS_Q6SS_AHB_LFABIF_CBCR 0x22000 |
| 497 | #define LPASS_Q6SS_XO_CBCR 0x26000 |
Vikram Mulukutla | 3454e9e | 2012-08-11 20:18:42 -0700 | [diff] [blame] | 498 | #define LPASS_Q6_AXI_CBCR 0x11C0 |
Vikram Mulukutla | b5b311e | 2012-08-09 14:58:48 -0700 | [diff] [blame] | 499 | #define Q6SS_AHBM_CBCR 0x22004 |
Vikram Mulukutla | 97ac334 | 2012-08-21 12:55:13 -0700 | [diff] [blame^] | 500 | #define AUDIO_WRAPPER_BR_CBCR 0x24000 |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 501 | #define MSS_XO_Q6_CBCR 0x108C |
| 502 | #define MSS_BUS_Q6_CBCR 0x10A4 |
| 503 | #define MSS_CFG_AHB_CBCR 0x0280 |
Vikram Mulukutla | 31926eb | 2012-08-12 19:58:08 -0700 | [diff] [blame] | 504 | #define MSS_Q6_BIMC_AXI_CBCR 0x0284 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 505 | |
| 506 | #define APCS_CLOCK_BRANCH_ENA_VOTE 0x1484 |
| 507 | #define APCS_CLOCK_SLEEP_ENA_VOTE 0x1488 |
| 508 | |
| 509 | /* Mux source select values */ |
| 510 | #define cxo_source_val 0 |
| 511 | #define gpll0_source_val 1 |
| 512 | #define gpll1_source_val 2 |
| 513 | #define gnd_source_val 5 |
| 514 | #define mmpll0_mm_source_val 1 |
| 515 | #define mmpll1_mm_source_val 2 |
| 516 | #define mmpll3_mm_source_val 3 |
| 517 | #define gpll0_mm_source_val 5 |
| 518 | #define cxo_mm_source_val 0 |
| 519 | #define mm_gnd_source_val 6 |
| 520 | #define gpll1_hsic_source_val 4 |
| 521 | #define cxo_lpass_source_val 0 |
| 522 | #define lpapll0_lpass_source_val 1 |
| 523 | #define gpll0_lpass_source_val 5 |
| 524 | #define edppll_270_mm_source_val 4 |
| 525 | #define edppll_350_mm_source_val 4 |
| 526 | #define dsipll_750_mm_source_val 1 |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 527 | #define dsipll0_byte_mm_source_val 1 |
| 528 | #define dsipll0_pixel_mm_source_val 1 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 529 | #define hdmipll_297_mm_source_val 3 |
| 530 | |
| 531 | #define F(f, s, div, m, n) \ |
| 532 | { \ |
| 533 | .freq_hz = (f), \ |
| 534 | .src_clk = &s##_clk_src.c, \ |
| 535 | .m_val = (m), \ |
Vikram Mulukutla | 60bfbb0 | 2012-08-08 00:49:20 -0700 | [diff] [blame] | 536 | .n_val = ~((n)-(m)) * !!(n), \ |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 537 | .d_val = ~(n),\ |
| 538 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 539 | | BVAL(10, 8, s##_source_val), \ |
| 540 | } |
| 541 | |
| 542 | #define F_MM(f, s, div, m, n) \ |
| 543 | { \ |
| 544 | .freq_hz = (f), \ |
| 545 | .src_clk = &s##_clk_src.c, \ |
| 546 | .m_val = (m), \ |
Vikram Mulukutla | 60bfbb0 | 2012-08-08 00:49:20 -0700 | [diff] [blame] | 547 | .n_val = ~((n)-(m)) * !!(n), \ |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 548 | .d_val = ~(n),\ |
| 549 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 550 | | BVAL(10, 8, s##_mm_source_val), \ |
| 551 | } |
| 552 | |
| 553 | #define F_MDSS(f, s, div, m, n) \ |
| 554 | { \ |
| 555 | .freq_hz = (f), \ |
| 556 | .m_val = (m), \ |
Vikram Mulukutla | 60bfbb0 | 2012-08-08 00:49:20 -0700 | [diff] [blame] | 557 | .n_val = ~((n)-(m)) * !!(n), \ |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 558 | .d_val = ~(n),\ |
| 559 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 560 | | BVAL(10, 8, s##_mm_source_val), \ |
| 561 | } |
| 562 | |
| 563 | #define F_HSIC(f, s, div, m, n) \ |
| 564 | { \ |
| 565 | .freq_hz = (f), \ |
| 566 | .src_clk = &s##_clk_src.c, \ |
| 567 | .m_val = (m), \ |
Vikram Mulukutla | 60bfbb0 | 2012-08-08 00:49:20 -0700 | [diff] [blame] | 568 | .n_val = ~((n)-(m)) * !!(n), \ |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 569 | .d_val = ~(n),\ |
| 570 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 571 | | BVAL(10, 8, s##_hsic_source_val), \ |
| 572 | } |
| 573 | |
| 574 | #define F_LPASS(f, s, div, m, n) \ |
| 575 | { \ |
| 576 | .freq_hz = (f), \ |
| 577 | .src_clk = &s##_clk_src.c, \ |
| 578 | .m_val = (m), \ |
Vikram Mulukutla | 60bfbb0 | 2012-08-08 00:49:20 -0700 | [diff] [blame] | 579 | .n_val = ~((n)-(m)) * !!(n), \ |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 580 | .d_val = ~(n),\ |
| 581 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 582 | | BVAL(10, 8, s##_lpass_source_val), \ |
| 583 | } |
| 584 | |
| 585 | #define VDD_DIG_FMAX_MAP1(l1, f1) \ |
| 586 | .vdd_class = &vdd_dig, \ |
| 587 | .fmax[VDD_DIG_##l1] = (f1) |
| 588 | #define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ |
| 589 | .vdd_class = &vdd_dig, \ |
| 590 | .fmax[VDD_DIG_##l1] = (f1), \ |
| 591 | .fmax[VDD_DIG_##l2] = (f2) |
| 592 | #define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ |
| 593 | .vdd_class = &vdd_dig, \ |
| 594 | .fmax[VDD_DIG_##l1] = (f1), \ |
| 595 | .fmax[VDD_DIG_##l2] = (f2), \ |
| 596 | .fmax[VDD_DIG_##l3] = (f3) |
| 597 | |
| 598 | enum vdd_dig_levels { |
| 599 | VDD_DIG_NONE, |
| 600 | VDD_DIG_LOW, |
| 601 | VDD_DIG_NOMINAL, |
| 602 | VDD_DIG_HIGH |
| 603 | }; |
| 604 | |
Vikram Mulukutla | b7a1a74 | 2012-05-30 17:24:33 -0700 | [diff] [blame] | 605 | static const int vdd_corner[] = { |
| 606 | [VDD_DIG_NONE] = RPM_REGULATOR_CORNER_NONE, |
| 607 | [VDD_DIG_LOW] = RPM_REGULATOR_CORNER_SVS_SOC, |
| 608 | [VDD_DIG_NOMINAL] = RPM_REGULATOR_CORNER_NORMAL, |
| 609 | [VDD_DIG_HIGH] = RPM_REGULATOR_CORNER_SUPER_TURBO, |
| 610 | }; |
| 611 | |
| 612 | static struct rpm_regulator *vdd_dig_reg; |
| 613 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 614 | static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level) |
| 615 | { |
Vikram Mulukutla | b7a1a74 | 2012-05-30 17:24:33 -0700 | [diff] [blame] | 616 | return rpm_regulator_set_voltage(vdd_dig_reg, vdd_corner[level], |
| 617 | RPM_REGULATOR_CORNER_SUPER_TURBO); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig); |
| 621 | |
Vikram Mulukutla | 80b7ab5 | 2012-07-26 19:03:15 -0700 | [diff] [blame] | 622 | #define RPM_MISC_CLK_TYPE 0x306b6c63 |
| 623 | #define RPM_BUS_CLK_TYPE 0x316b6c63 |
| 624 | #define RPM_MEM_CLK_TYPE 0x326b6c63 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 625 | |
Vikram Mulukutla | 77140da | 2012-08-13 21:37:18 -0700 | [diff] [blame] | 626 | #define RPM_SMD_KEY_ENABLE 0x62616E45 |
| 627 | |
| 628 | #define CXO_ID 0x0 |
| 629 | #define QDSS_ID 0x1 |
| 630 | #define RPM_SCALING_ENABLE_ID 0x2 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 631 | |
Vikram Mulukutla | 6ddff4e | 2012-06-22 15:11:28 -0700 | [diff] [blame] | 632 | #define PNOC_ID 0x0 |
| 633 | #define SNOC_ID 0x1 |
| 634 | #define CNOC_ID 0x2 |
Vikram Mulukutla | c77922f | 2012-08-13 21:44:45 -0700 | [diff] [blame] | 635 | #define MMSSNOC_AHB_ID 0x3 |
Matt Wagantall | c4388bf | 2012-05-14 23:03:00 -0700 | [diff] [blame] | 636 | |
Vikram Mulukutla | 6ddff4e | 2012-06-22 15:11:28 -0700 | [diff] [blame] | 637 | #define BIMC_ID 0x0 |
Vikram Mulukutla | 1e6127d | 2012-08-21 21:05:24 -0700 | [diff] [blame] | 638 | #define OXILI_ID 0x1 |
| 639 | #define OCMEM_ID 0x2 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 640 | |
Vikram Mulukutla | 80b7ab5 | 2012-07-26 19:03:15 -0700 | [diff] [blame] | 641 | enum { |
| 642 | D0_ID = 1, |
| 643 | D1_ID, |
| 644 | A0_ID, |
| 645 | A1_ID, |
| 646 | A2_ID, |
| 647 | }; |
| 648 | |
Vikram Mulukutla | 6ddff4e | 2012-06-22 15:11:28 -0700 | [diff] [blame] | 649 | DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL); |
| 650 | DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL); |
| 651 | DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL); |
Vikram Mulukutla | 09e2081 | 2012-07-12 11:32:42 -0700 | [diff] [blame] | 652 | DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE, |
| 653 | MMSSNOC_AHB_ID, NULL); |
Vikram Mulukutla | 6ddff4e | 2012-06-22 15:11:28 -0700 | [diff] [blame] | 654 | |
| 655 | DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL); |
| 656 | DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID, |
| 657 | NULL); |
Vikram Mulukutla | 1e6127d | 2012-08-21 21:05:24 -0700 | [diff] [blame] | 658 | DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID, |
| 659 | NULL); |
Vikram Mulukutla | 6ddff4e | 2012-06-22 15:11:28 -0700 | [diff] [blame] | 660 | |
| 661 | DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_a_clk_src, |
| 662 | RPM_MISC_CLK_TYPE, CXO_ID, 19200000); |
Vikram Mulukutla | 0f63e00 | 2012-06-28 14:29:44 -0700 | [diff] [blame] | 663 | DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 664 | |
Vikram Mulukutla | 80b7ab5 | 2012-07-26 19:03:15 -0700 | [diff] [blame] | 665 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID); |
| 666 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID); |
| 667 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID); |
| 668 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID); |
| 669 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID); |
| 670 | |
| 671 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID); |
| 672 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID); |
| 673 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID); |
| 674 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID); |
| 675 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID); |
| 676 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 677 | static struct pll_vote_clk gpll0_clk_src = { |
| 678 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 679 | .status_reg = (void __iomem *)GPLL0_STATUS_REG, |
| 680 | .status_mask = BIT(17), |
| 681 | .parent = &cxo_clk_src.c, |
| 682 | .base = &virt_bases[GCC_BASE], |
| 683 | .c = { |
| 684 | .rate = 600000000, |
| 685 | .dbg_name = "gpll0_clk_src", |
| 686 | .ops = &clk_ops_pll_vote, |
| 687 | .warned = true, |
| 688 | CLK_INIT(gpll0_clk_src.c), |
| 689 | }, |
| 690 | }; |
| 691 | |
| 692 | static struct pll_vote_clk gpll1_clk_src = { |
| 693 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG, |
| 694 | .en_mask = BIT(1), |
| 695 | .status_reg = (void __iomem *)GPLL1_STATUS_REG, |
| 696 | .status_mask = BIT(17), |
| 697 | .parent = &cxo_clk_src.c, |
| 698 | .base = &virt_bases[GCC_BASE], |
| 699 | .c = { |
| 700 | .rate = 480000000, |
| 701 | .dbg_name = "gpll1_clk_src", |
| 702 | .ops = &clk_ops_pll_vote, |
| 703 | .warned = true, |
| 704 | CLK_INIT(gpll1_clk_src.c), |
| 705 | }, |
| 706 | }; |
| 707 | |
| 708 | static struct pll_vote_clk lpapll0_clk_src = { |
| 709 | .en_reg = (void __iomem *)LPASS_LPA_PLL_VOTE_APPS_REG, |
| 710 | .en_mask = BIT(0), |
| 711 | .status_reg = (void __iomem *)LPAPLL_STATUS_REG, |
| 712 | .status_mask = BIT(17), |
| 713 | .parent = &cxo_clk_src.c, |
| 714 | .base = &virt_bases[LPASS_BASE], |
| 715 | .c = { |
| 716 | .rate = 491520000, |
| 717 | .dbg_name = "lpapll0_clk_src", |
| 718 | .ops = &clk_ops_pll_vote, |
| 719 | .warned = true, |
| 720 | CLK_INIT(lpapll0_clk_src.c), |
| 721 | }, |
| 722 | }; |
| 723 | |
| 724 | static struct pll_vote_clk mmpll0_clk_src = { |
| 725 | .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS_REG, |
| 726 | .en_mask = BIT(0), |
| 727 | .status_reg = (void __iomem *)MMPLL0_STATUS_REG, |
| 728 | .status_mask = BIT(17), |
| 729 | .parent = &cxo_clk_src.c, |
| 730 | .base = &virt_bases[MMSS_BASE], |
| 731 | .c = { |
| 732 | .dbg_name = "mmpll0_clk_src", |
| 733 | .rate = 800000000, |
| 734 | .ops = &clk_ops_pll_vote, |
| 735 | .warned = true, |
| 736 | CLK_INIT(mmpll0_clk_src.c), |
| 737 | }, |
| 738 | }; |
| 739 | |
| 740 | static struct pll_vote_clk mmpll1_clk_src = { |
| 741 | .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS_REG, |
| 742 | .en_mask = BIT(1), |
| 743 | .status_reg = (void __iomem *)MMPLL1_STATUS_REG, |
| 744 | .status_mask = BIT(17), |
| 745 | .parent = &cxo_clk_src.c, |
| 746 | .base = &virt_bases[MMSS_BASE], |
| 747 | .c = { |
| 748 | .dbg_name = "mmpll1_clk_src", |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 749 | .rate = 846000000, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 750 | .ops = &clk_ops_pll_vote, |
| 751 | .warned = true, |
| 752 | CLK_INIT(mmpll1_clk_src.c), |
| 753 | }, |
| 754 | }; |
| 755 | |
| 756 | static struct pll_clk mmpll3_clk_src = { |
| 757 | .mode_reg = (void __iomem *)MMPLL3_MODE_REG, |
| 758 | .status_reg = (void __iomem *)MMPLL3_STATUS_REG, |
| 759 | .parent = &cxo_clk_src.c, |
| 760 | .base = &virt_bases[MMSS_BASE], |
| 761 | .c = { |
| 762 | .dbg_name = "mmpll3_clk_src", |
| 763 | .rate = 1000000000, |
| 764 | .ops = &clk_ops_local_pll, |
Vikram Mulukutla | 08aae61 | 2012-07-24 12:34:44 -0700 | [diff] [blame] | 765 | .warned = true, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 766 | CLK_INIT(mmpll3_clk_src.c), |
| 767 | }, |
| 768 | }; |
| 769 | |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 770 | static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX); |
| 771 | static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX); |
| 772 | static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX); |
| 773 | static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX); |
| 774 | static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX); |
| 775 | static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX); |
| 776 | |
| 777 | static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX); |
| 778 | static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX); |
| 779 | static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX); |
Vikram Mulukutla | 1e6127d | 2012-08-21 21:05:24 -0700 | [diff] [blame] | 780 | static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX); |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 781 | static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX); |
| 782 | static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX); |
Naveen Ramaraj | 65396b9 | 2012-08-15 17:05:07 -0700 | [diff] [blame] | 783 | static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX); |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 784 | |
Sujit Reddy Thumma | 5024749 | 2012-06-18 09:39:36 +0530 | [diff] [blame] | 785 | static DEFINE_CLK_VOTER(pnoc_sdcc1_clk, &pnoc_clk.c, 0); |
| 786 | static DEFINE_CLK_VOTER(pnoc_sdcc2_clk, &pnoc_clk.c, 0); |
| 787 | static DEFINE_CLK_VOTER(pnoc_sdcc3_clk, &pnoc_clk.c, 0); |
| 788 | static DEFINE_CLK_VOTER(pnoc_sdcc4_clk, &pnoc_clk.c, 0); |
| 789 | |
Vikram Mulukutla | b0ad9f3 | 2012-07-03 12:57:24 -0700 | [diff] [blame] | 790 | static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, 0); |
| 791 | static DEFINE_CLK_VOTER(pnoc_qseecom_clk, &pnoc_clk.c, 0); |
| 792 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 793 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = { |
| 794 | F(125000000, gpll0, 1, 5, 24), |
| 795 | F_END |
| 796 | }; |
| 797 | |
| 798 | static struct rcg_clk usb30_master_clk_src = { |
| 799 | .cmd_rcgr_reg = USB30_MASTER_CMD_RCGR, |
| 800 | .set_rate = set_rate_mnd, |
| 801 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 802 | .current_freq = &rcg_dummy_freq, |
| 803 | .base = &virt_bases[GCC_BASE], |
| 804 | .c = { |
| 805 | .dbg_name = "usb30_master_clk_src", |
| 806 | .ops = &clk_ops_rcg_mnd, |
| 807 | VDD_DIG_FMAX_MAP1(NOMINAL, 125000000), |
| 808 | CLK_INIT(usb30_master_clk_src.c), |
| 809 | }, |
| 810 | }; |
| 811 | |
| 812 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = { |
| 813 | F( 960000, cxo, 10, 1, 2), |
| 814 | F( 4800000, cxo, 4, 0, 0), |
| 815 | F( 9600000, cxo, 2, 0, 0), |
| 816 | F(15000000, gpll0, 10, 1, 4), |
| 817 | F(19200000, cxo, 1, 0, 0), |
| 818 | F(25000000, gpll0, 12, 1, 2), |
| 819 | F(50000000, gpll0, 12, 0, 0), |
| 820 | F_END |
| 821 | }; |
| 822 | |
| 823 | static struct rcg_clk blsp1_qup1_spi_apps_clk_src = { |
| 824 | .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR, |
| 825 | .set_rate = set_rate_mnd, |
| 826 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 827 | .current_freq = &rcg_dummy_freq, |
| 828 | .base = &virt_bases[GCC_BASE], |
| 829 | .c = { |
| 830 | .dbg_name = "blsp1_qup1_spi_apps_clk_src", |
| 831 | .ops = &clk_ops_rcg_mnd, |
| 832 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 833 | CLK_INIT(blsp1_qup1_spi_apps_clk_src.c), |
| 834 | }, |
| 835 | }; |
| 836 | |
| 837 | static struct rcg_clk blsp1_qup2_spi_apps_clk_src = { |
| 838 | .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR, |
| 839 | .set_rate = set_rate_mnd, |
| 840 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 841 | .current_freq = &rcg_dummy_freq, |
| 842 | .base = &virt_bases[GCC_BASE], |
| 843 | .c = { |
| 844 | .dbg_name = "blsp1_qup2_spi_apps_clk_src", |
| 845 | .ops = &clk_ops_rcg_mnd, |
| 846 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 847 | CLK_INIT(blsp1_qup2_spi_apps_clk_src.c), |
| 848 | }, |
| 849 | }; |
| 850 | |
| 851 | static struct rcg_clk blsp1_qup3_spi_apps_clk_src = { |
| 852 | .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR, |
| 853 | .set_rate = set_rate_mnd, |
| 854 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 855 | .current_freq = &rcg_dummy_freq, |
| 856 | .base = &virt_bases[GCC_BASE], |
| 857 | .c = { |
| 858 | .dbg_name = "blsp1_qup3_spi_apps_clk_src", |
| 859 | .ops = &clk_ops_rcg_mnd, |
| 860 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 861 | CLK_INIT(blsp1_qup3_spi_apps_clk_src.c), |
| 862 | }, |
| 863 | }; |
| 864 | |
| 865 | static struct rcg_clk blsp1_qup4_spi_apps_clk_src = { |
| 866 | .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR, |
| 867 | .set_rate = set_rate_mnd, |
| 868 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 869 | .current_freq = &rcg_dummy_freq, |
| 870 | .base = &virt_bases[GCC_BASE], |
| 871 | .c = { |
| 872 | .dbg_name = "blsp1_qup4_spi_apps_clk_src", |
| 873 | .ops = &clk_ops_rcg_mnd, |
| 874 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 875 | CLK_INIT(blsp1_qup4_spi_apps_clk_src.c), |
| 876 | }, |
| 877 | }; |
| 878 | |
| 879 | static struct rcg_clk blsp1_qup5_spi_apps_clk_src = { |
| 880 | .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR, |
| 881 | .set_rate = set_rate_mnd, |
| 882 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 883 | .current_freq = &rcg_dummy_freq, |
| 884 | .base = &virt_bases[GCC_BASE], |
| 885 | .c = { |
| 886 | .dbg_name = "blsp1_qup5_spi_apps_clk_src", |
| 887 | .ops = &clk_ops_rcg_mnd, |
| 888 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 889 | CLK_INIT(blsp1_qup5_spi_apps_clk_src.c), |
| 890 | }, |
| 891 | }; |
| 892 | |
| 893 | static struct rcg_clk blsp1_qup6_spi_apps_clk_src = { |
| 894 | .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR, |
| 895 | .set_rate = set_rate_mnd, |
| 896 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 897 | .current_freq = &rcg_dummy_freq, |
| 898 | .base = &virt_bases[GCC_BASE], |
| 899 | .c = { |
| 900 | .dbg_name = "blsp1_qup6_spi_apps_clk_src", |
| 901 | .ops = &clk_ops_rcg_mnd, |
| 902 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 903 | CLK_INIT(blsp1_qup6_spi_apps_clk_src.c), |
| 904 | }, |
| 905 | }; |
| 906 | |
| 907 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = { |
| 908 | F( 3686400, gpll0, 1, 96, 15625), |
| 909 | F( 7372800, gpll0, 1, 192, 15625), |
| 910 | F(14745600, gpll0, 1, 384, 15625), |
| 911 | F(16000000, gpll0, 5, 2, 15), |
| 912 | F(19200000, cxo, 1, 0, 0), |
| 913 | F(24000000, gpll0, 5, 1, 5), |
| 914 | F(32000000, gpll0, 1, 4, 75), |
| 915 | F(40000000, gpll0, 15, 0, 0), |
| 916 | F(46400000, gpll0, 1, 29, 375), |
| 917 | F(48000000, gpll0, 12.5, 0, 0), |
| 918 | F(51200000, gpll0, 1, 32, 375), |
| 919 | F(56000000, gpll0, 1, 7, 75), |
| 920 | F(58982400, gpll0, 1, 1536, 15625), |
| 921 | F(60000000, gpll0, 10, 0, 0), |
| 922 | F_END |
| 923 | }; |
| 924 | |
| 925 | static struct rcg_clk blsp1_uart1_apps_clk_src = { |
| 926 | .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR, |
| 927 | .set_rate = set_rate_mnd, |
| 928 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 929 | .current_freq = &rcg_dummy_freq, |
| 930 | .base = &virt_bases[GCC_BASE], |
| 931 | .c = { |
| 932 | .dbg_name = "blsp1_uart1_apps_clk_src", |
| 933 | .ops = &clk_ops_rcg_mnd, |
| 934 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 935 | CLK_INIT(blsp1_uart1_apps_clk_src.c), |
| 936 | }, |
| 937 | }; |
| 938 | |
| 939 | static struct rcg_clk blsp1_uart2_apps_clk_src = { |
| 940 | .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR, |
| 941 | .set_rate = set_rate_mnd, |
| 942 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 943 | .current_freq = &rcg_dummy_freq, |
| 944 | .base = &virt_bases[GCC_BASE], |
| 945 | .c = { |
| 946 | .dbg_name = "blsp1_uart2_apps_clk_src", |
| 947 | .ops = &clk_ops_rcg_mnd, |
| 948 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 949 | CLK_INIT(blsp1_uart2_apps_clk_src.c), |
| 950 | }, |
| 951 | }; |
| 952 | |
| 953 | static struct rcg_clk blsp1_uart3_apps_clk_src = { |
| 954 | .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR, |
| 955 | .set_rate = set_rate_mnd, |
| 956 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 957 | .current_freq = &rcg_dummy_freq, |
| 958 | .base = &virt_bases[GCC_BASE], |
| 959 | .c = { |
| 960 | .dbg_name = "blsp1_uart3_apps_clk_src", |
| 961 | .ops = &clk_ops_rcg_mnd, |
| 962 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 963 | CLK_INIT(blsp1_uart3_apps_clk_src.c), |
| 964 | }, |
| 965 | }; |
| 966 | |
| 967 | static struct rcg_clk blsp1_uart4_apps_clk_src = { |
| 968 | .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR, |
| 969 | .set_rate = set_rate_mnd, |
| 970 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 971 | .current_freq = &rcg_dummy_freq, |
| 972 | .base = &virt_bases[GCC_BASE], |
| 973 | .c = { |
| 974 | .dbg_name = "blsp1_uart4_apps_clk_src", |
| 975 | .ops = &clk_ops_rcg_mnd, |
| 976 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 977 | CLK_INIT(blsp1_uart4_apps_clk_src.c), |
| 978 | }, |
| 979 | }; |
| 980 | |
| 981 | static struct rcg_clk blsp1_uart5_apps_clk_src = { |
| 982 | .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR, |
| 983 | .set_rate = set_rate_mnd, |
| 984 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 985 | .current_freq = &rcg_dummy_freq, |
| 986 | .base = &virt_bases[GCC_BASE], |
| 987 | .c = { |
| 988 | .dbg_name = "blsp1_uart5_apps_clk_src", |
| 989 | .ops = &clk_ops_rcg_mnd, |
| 990 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 991 | CLK_INIT(blsp1_uart5_apps_clk_src.c), |
| 992 | }, |
| 993 | }; |
| 994 | |
| 995 | static struct rcg_clk blsp1_uart6_apps_clk_src = { |
| 996 | .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR, |
| 997 | .set_rate = set_rate_mnd, |
| 998 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 999 | .current_freq = &rcg_dummy_freq, |
| 1000 | .base = &virt_bases[GCC_BASE], |
| 1001 | .c = { |
| 1002 | .dbg_name = "blsp1_uart6_apps_clk_src", |
| 1003 | .ops = &clk_ops_rcg_mnd, |
| 1004 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 1005 | CLK_INIT(blsp1_uart6_apps_clk_src.c), |
| 1006 | }, |
| 1007 | }; |
| 1008 | |
| 1009 | static struct rcg_clk blsp2_qup1_spi_apps_clk_src = { |
| 1010 | .cmd_rcgr_reg = BLSP2_QUP1_SPI_APPS_CMD_RCGR, |
| 1011 | .set_rate = set_rate_mnd, |
| 1012 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 1013 | .current_freq = &rcg_dummy_freq, |
| 1014 | .base = &virt_bases[GCC_BASE], |
| 1015 | .c = { |
| 1016 | .dbg_name = "blsp2_qup1_spi_apps_clk_src", |
| 1017 | .ops = &clk_ops_rcg_mnd, |
| 1018 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 1019 | CLK_INIT(blsp2_qup1_spi_apps_clk_src.c), |
| 1020 | }, |
| 1021 | }; |
| 1022 | |
| 1023 | static struct rcg_clk blsp2_qup2_spi_apps_clk_src = { |
| 1024 | .cmd_rcgr_reg = BLSP2_QUP2_SPI_APPS_CMD_RCGR, |
| 1025 | .set_rate = set_rate_mnd, |
| 1026 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 1027 | .current_freq = &rcg_dummy_freq, |
| 1028 | .base = &virt_bases[GCC_BASE], |
| 1029 | .c = { |
| 1030 | .dbg_name = "blsp2_qup2_spi_apps_clk_src", |
| 1031 | .ops = &clk_ops_rcg_mnd, |
| 1032 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 1033 | CLK_INIT(blsp2_qup2_spi_apps_clk_src.c), |
| 1034 | }, |
| 1035 | }; |
| 1036 | |
| 1037 | static struct rcg_clk blsp2_qup3_spi_apps_clk_src = { |
| 1038 | .cmd_rcgr_reg = BLSP2_QUP3_SPI_APPS_CMD_RCGR, |
| 1039 | .set_rate = set_rate_mnd, |
| 1040 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 1041 | .current_freq = &rcg_dummy_freq, |
| 1042 | .base = &virt_bases[GCC_BASE], |
| 1043 | .c = { |
| 1044 | .dbg_name = "blsp2_qup3_spi_apps_clk_src", |
| 1045 | .ops = &clk_ops_rcg_mnd, |
| 1046 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 1047 | CLK_INIT(blsp2_qup3_spi_apps_clk_src.c), |
| 1048 | }, |
| 1049 | }; |
| 1050 | |
| 1051 | static struct rcg_clk blsp2_qup4_spi_apps_clk_src = { |
| 1052 | .cmd_rcgr_reg = BLSP2_QUP4_SPI_APPS_CMD_RCGR, |
| 1053 | .set_rate = set_rate_mnd, |
| 1054 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 1055 | .current_freq = &rcg_dummy_freq, |
| 1056 | .base = &virt_bases[GCC_BASE], |
| 1057 | .c = { |
| 1058 | .dbg_name = "blsp2_qup4_spi_apps_clk_src", |
| 1059 | .ops = &clk_ops_rcg_mnd, |
| 1060 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 1061 | CLK_INIT(blsp2_qup4_spi_apps_clk_src.c), |
| 1062 | }, |
| 1063 | }; |
| 1064 | |
| 1065 | static struct rcg_clk blsp2_qup5_spi_apps_clk_src = { |
| 1066 | .cmd_rcgr_reg = BLSP2_QUP5_SPI_APPS_CMD_RCGR, |
| 1067 | .set_rate = set_rate_mnd, |
| 1068 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 1069 | .current_freq = &rcg_dummy_freq, |
| 1070 | .base = &virt_bases[GCC_BASE], |
| 1071 | .c = { |
| 1072 | .dbg_name = "blsp2_qup5_spi_apps_clk_src", |
| 1073 | .ops = &clk_ops_rcg_mnd, |
| 1074 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 1075 | CLK_INIT(blsp2_qup5_spi_apps_clk_src.c), |
| 1076 | }, |
| 1077 | }; |
| 1078 | |
| 1079 | static struct rcg_clk blsp2_qup6_spi_apps_clk_src = { |
| 1080 | .cmd_rcgr_reg = BLSP2_QUP6_SPI_APPS_CMD_RCGR, |
| 1081 | .set_rate = set_rate_mnd, |
| 1082 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
| 1083 | .current_freq = &rcg_dummy_freq, |
| 1084 | .base = &virt_bases[GCC_BASE], |
| 1085 | .c = { |
| 1086 | .dbg_name = "blsp2_qup6_spi_apps_clk_src", |
| 1087 | .ops = &clk_ops_rcg_mnd, |
| 1088 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 1089 | CLK_INIT(blsp2_qup6_spi_apps_clk_src.c), |
| 1090 | }, |
| 1091 | }; |
| 1092 | |
| 1093 | static struct rcg_clk blsp2_uart1_apps_clk_src = { |
| 1094 | .cmd_rcgr_reg = BLSP2_UART1_APPS_CMD_RCGR, |
| 1095 | .set_rate = set_rate_mnd, |
| 1096 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 1097 | .current_freq = &rcg_dummy_freq, |
| 1098 | .base = &virt_bases[GCC_BASE], |
| 1099 | .c = { |
| 1100 | .dbg_name = "blsp2_uart1_apps_clk_src", |
| 1101 | .ops = &clk_ops_rcg_mnd, |
| 1102 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 1103 | CLK_INIT(blsp2_uart1_apps_clk_src.c), |
| 1104 | }, |
| 1105 | }; |
| 1106 | |
| 1107 | static struct rcg_clk blsp2_uart2_apps_clk_src = { |
| 1108 | .cmd_rcgr_reg = BLSP2_UART2_APPS_CMD_RCGR, |
| 1109 | .set_rate = set_rate_mnd, |
| 1110 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 1111 | .current_freq = &rcg_dummy_freq, |
| 1112 | .base = &virt_bases[GCC_BASE], |
| 1113 | .c = { |
| 1114 | .dbg_name = "blsp2_uart2_apps_clk_src", |
| 1115 | .ops = &clk_ops_rcg_mnd, |
| 1116 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 1117 | CLK_INIT(blsp2_uart2_apps_clk_src.c), |
| 1118 | }, |
| 1119 | }; |
| 1120 | |
| 1121 | static struct rcg_clk blsp2_uart3_apps_clk_src = { |
| 1122 | .cmd_rcgr_reg = BLSP2_UART3_APPS_CMD_RCGR, |
| 1123 | .set_rate = set_rate_mnd, |
| 1124 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 1125 | .current_freq = &rcg_dummy_freq, |
| 1126 | .base = &virt_bases[GCC_BASE], |
| 1127 | .c = { |
| 1128 | .dbg_name = "blsp2_uart3_apps_clk_src", |
| 1129 | .ops = &clk_ops_rcg_mnd, |
| 1130 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 1131 | CLK_INIT(blsp2_uart3_apps_clk_src.c), |
| 1132 | }, |
| 1133 | }; |
| 1134 | |
| 1135 | static struct rcg_clk blsp2_uart4_apps_clk_src = { |
| 1136 | .cmd_rcgr_reg = BLSP2_UART4_APPS_CMD_RCGR, |
| 1137 | .set_rate = set_rate_mnd, |
| 1138 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 1139 | .current_freq = &rcg_dummy_freq, |
| 1140 | .base = &virt_bases[GCC_BASE], |
| 1141 | .c = { |
| 1142 | .dbg_name = "blsp2_uart4_apps_clk_src", |
| 1143 | .ops = &clk_ops_rcg_mnd, |
| 1144 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 1145 | CLK_INIT(blsp2_uart4_apps_clk_src.c), |
| 1146 | }, |
| 1147 | }; |
| 1148 | |
| 1149 | static struct rcg_clk blsp2_uart5_apps_clk_src = { |
| 1150 | .cmd_rcgr_reg = BLSP2_UART5_APPS_CMD_RCGR, |
| 1151 | .set_rate = set_rate_mnd, |
| 1152 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 1153 | .current_freq = &rcg_dummy_freq, |
| 1154 | .base = &virt_bases[GCC_BASE], |
| 1155 | .c = { |
| 1156 | .dbg_name = "blsp2_uart5_apps_clk_src", |
| 1157 | .ops = &clk_ops_rcg_mnd, |
| 1158 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 1159 | CLK_INIT(blsp2_uart5_apps_clk_src.c), |
| 1160 | }, |
| 1161 | }; |
| 1162 | |
| 1163 | static struct rcg_clk blsp2_uart6_apps_clk_src = { |
| 1164 | .cmd_rcgr_reg = BLSP2_UART6_APPS_CMD_RCGR, |
| 1165 | .set_rate = set_rate_mnd, |
| 1166 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 1167 | .current_freq = &rcg_dummy_freq, |
| 1168 | .base = &virt_bases[GCC_BASE], |
| 1169 | .c = { |
| 1170 | .dbg_name = "blsp2_uart6_apps_clk_src", |
| 1171 | .ops = &clk_ops_rcg_mnd, |
| 1172 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 1173 | CLK_INIT(blsp2_uart6_apps_clk_src.c), |
| 1174 | }, |
| 1175 | }; |
| 1176 | |
| 1177 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 1178 | F( 50000000, gpll0, 12, 0, 0), |
| 1179 | F(100000000, gpll0, 6, 0, 0), |
| 1180 | F_END |
| 1181 | }; |
| 1182 | |
| 1183 | static struct rcg_clk ce1_clk_src = { |
| 1184 | .cmd_rcgr_reg = CE1_CMD_RCGR, |
| 1185 | .set_rate = set_rate_hid, |
| 1186 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 1187 | .current_freq = &rcg_dummy_freq, |
| 1188 | .base = &virt_bases[GCC_BASE], |
| 1189 | .c = { |
| 1190 | .dbg_name = "ce1_clk_src", |
| 1191 | .ops = &clk_ops_rcg, |
| 1192 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 1193 | CLK_INIT(ce1_clk_src.c), |
| 1194 | }, |
| 1195 | }; |
| 1196 | |
| 1197 | static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = { |
| 1198 | F( 50000000, gpll0, 12, 0, 0), |
| 1199 | F(100000000, gpll0, 6, 0, 0), |
| 1200 | F_END |
| 1201 | }; |
| 1202 | |
| 1203 | static struct rcg_clk ce2_clk_src = { |
| 1204 | .cmd_rcgr_reg = CE2_CMD_RCGR, |
| 1205 | .set_rate = set_rate_hid, |
| 1206 | .freq_tbl = ftbl_gcc_ce2_clk, |
| 1207 | .current_freq = &rcg_dummy_freq, |
| 1208 | .base = &virt_bases[GCC_BASE], |
| 1209 | .c = { |
| 1210 | .dbg_name = "ce2_clk_src", |
| 1211 | .ops = &clk_ops_rcg, |
| 1212 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 1213 | CLK_INIT(ce2_clk_src.c), |
| 1214 | }, |
| 1215 | }; |
| 1216 | |
| 1217 | static struct clk_freq_tbl ftbl_gcc_gp_clk[] = { |
| 1218 | F(19200000, cxo, 1, 0, 0), |
| 1219 | F_END |
| 1220 | }; |
| 1221 | |
| 1222 | static struct rcg_clk gp1_clk_src = { |
| 1223 | .cmd_rcgr_reg = GP1_CMD_RCGR, |
| 1224 | .set_rate = set_rate_mnd, |
| 1225 | .freq_tbl = ftbl_gcc_gp_clk, |
| 1226 | .current_freq = &rcg_dummy_freq, |
| 1227 | .base = &virt_bases[GCC_BASE], |
| 1228 | .c = { |
| 1229 | .dbg_name = "gp1_clk_src", |
| 1230 | .ops = &clk_ops_rcg_mnd, |
| 1231 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1232 | CLK_INIT(gp1_clk_src.c), |
| 1233 | }, |
| 1234 | }; |
| 1235 | |
| 1236 | static struct rcg_clk gp2_clk_src = { |
| 1237 | .cmd_rcgr_reg = GP2_CMD_RCGR, |
| 1238 | .set_rate = set_rate_mnd, |
| 1239 | .freq_tbl = ftbl_gcc_gp_clk, |
| 1240 | .current_freq = &rcg_dummy_freq, |
| 1241 | .base = &virt_bases[GCC_BASE], |
| 1242 | .c = { |
| 1243 | .dbg_name = "gp2_clk_src", |
| 1244 | .ops = &clk_ops_rcg_mnd, |
| 1245 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1246 | CLK_INIT(gp2_clk_src.c), |
| 1247 | }, |
| 1248 | }; |
| 1249 | |
| 1250 | static struct rcg_clk gp3_clk_src = { |
| 1251 | .cmd_rcgr_reg = GP3_CMD_RCGR, |
| 1252 | .set_rate = set_rate_mnd, |
| 1253 | .freq_tbl = ftbl_gcc_gp_clk, |
| 1254 | .current_freq = &rcg_dummy_freq, |
| 1255 | .base = &virt_bases[GCC_BASE], |
| 1256 | .c = { |
| 1257 | .dbg_name = "gp3_clk_src", |
| 1258 | .ops = &clk_ops_rcg_mnd, |
| 1259 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1260 | CLK_INIT(gp3_clk_src.c), |
| 1261 | }, |
| 1262 | }; |
| 1263 | |
| 1264 | static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = { |
| 1265 | F(60000000, gpll0, 10, 0, 0), |
| 1266 | F_END |
| 1267 | }; |
| 1268 | |
| 1269 | static struct rcg_clk pdm2_clk_src = { |
| 1270 | .cmd_rcgr_reg = PDM2_CMD_RCGR, |
| 1271 | .set_rate = set_rate_hid, |
| 1272 | .freq_tbl = ftbl_gcc_pdm2_clk, |
| 1273 | .current_freq = &rcg_dummy_freq, |
| 1274 | .base = &virt_bases[GCC_BASE], |
| 1275 | .c = { |
| 1276 | .dbg_name = "pdm2_clk_src", |
| 1277 | .ops = &clk_ops_rcg, |
| 1278 | VDD_DIG_FMAX_MAP1(LOW, 60000000), |
| 1279 | CLK_INIT(pdm2_clk_src.c), |
| 1280 | }, |
| 1281 | }; |
| 1282 | |
| 1283 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = { |
| 1284 | F( 144000, cxo, 16, 3, 25), |
| 1285 | F( 400000, cxo, 12, 1, 4), |
| 1286 | F( 20000000, gpll0, 15, 1, 2), |
| 1287 | F( 25000000, gpll0, 12, 1, 2), |
| 1288 | F( 50000000, gpll0, 12, 0, 0), |
| 1289 | F(100000000, gpll0, 6, 0, 0), |
| 1290 | F(200000000, gpll0, 3, 0, 0), |
| 1291 | F_END |
| 1292 | }; |
| 1293 | |
| 1294 | static struct clk_freq_tbl ftbl_gcc_sdcc3_4_apps_clk[] = { |
| 1295 | F( 144000, cxo, 16, 3, 25), |
| 1296 | F( 400000, cxo, 12, 1, 4), |
| 1297 | F( 20000000, gpll0, 15, 1, 2), |
| 1298 | F( 25000000, gpll0, 12, 1, 2), |
| 1299 | F( 50000000, gpll0, 12, 0, 0), |
| 1300 | F(100000000, gpll0, 6, 0, 0), |
| 1301 | F_END |
| 1302 | }; |
| 1303 | |
Vikram Mulukutla | 19245e0 | 2012-07-23 15:58:04 -0700 | [diff] [blame] | 1304 | static struct clk_freq_tbl ftbl_gcc_sdcc_apps_rumi_clk[] = { |
| 1305 | F( 400000, cxo, 12, 1, 4), |
| 1306 | F( 19200000, cxo, 1, 0, 0), |
| 1307 | F_END |
| 1308 | }; |
| 1309 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1310 | static struct rcg_clk sdcc1_apps_clk_src = { |
| 1311 | .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR, |
| 1312 | .set_rate = set_rate_mnd, |
| 1313 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 1314 | .current_freq = &rcg_dummy_freq, |
| 1315 | .base = &virt_bases[GCC_BASE], |
| 1316 | .c = { |
| 1317 | .dbg_name = "sdcc1_apps_clk_src", |
| 1318 | .ops = &clk_ops_rcg_mnd, |
| 1319 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1320 | CLK_INIT(sdcc1_apps_clk_src.c), |
| 1321 | }, |
| 1322 | }; |
| 1323 | |
| 1324 | static struct rcg_clk sdcc2_apps_clk_src = { |
| 1325 | .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR, |
| 1326 | .set_rate = set_rate_mnd, |
| 1327 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 1328 | .current_freq = &rcg_dummy_freq, |
| 1329 | .base = &virt_bases[GCC_BASE], |
| 1330 | .c = { |
| 1331 | .dbg_name = "sdcc2_apps_clk_src", |
| 1332 | .ops = &clk_ops_rcg_mnd, |
| 1333 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1334 | CLK_INIT(sdcc2_apps_clk_src.c), |
| 1335 | }, |
| 1336 | }; |
| 1337 | |
| 1338 | static struct rcg_clk sdcc3_apps_clk_src = { |
| 1339 | .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR, |
| 1340 | .set_rate = set_rate_mnd, |
| 1341 | .freq_tbl = ftbl_gcc_sdcc3_4_apps_clk, |
| 1342 | .current_freq = &rcg_dummy_freq, |
| 1343 | .base = &virt_bases[GCC_BASE], |
| 1344 | .c = { |
| 1345 | .dbg_name = "sdcc3_apps_clk_src", |
| 1346 | .ops = &clk_ops_rcg_mnd, |
| 1347 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 1348 | CLK_INIT(sdcc3_apps_clk_src.c), |
| 1349 | }, |
| 1350 | }; |
| 1351 | |
| 1352 | static struct rcg_clk sdcc4_apps_clk_src = { |
| 1353 | .cmd_rcgr_reg = SDCC4_APPS_CMD_RCGR, |
| 1354 | .set_rate = set_rate_mnd, |
| 1355 | .freq_tbl = ftbl_gcc_sdcc3_4_apps_clk, |
| 1356 | .current_freq = &rcg_dummy_freq, |
| 1357 | .base = &virt_bases[GCC_BASE], |
| 1358 | .c = { |
| 1359 | .dbg_name = "sdcc4_apps_clk_src", |
| 1360 | .ops = &clk_ops_rcg_mnd, |
| 1361 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 1362 | CLK_INIT(sdcc4_apps_clk_src.c), |
| 1363 | }, |
| 1364 | }; |
| 1365 | |
| 1366 | static struct clk_freq_tbl ftbl_gcc_tsif_ref_clk[] = { |
| 1367 | F(105000, cxo, 2, 1, 91), |
| 1368 | F_END |
| 1369 | }; |
| 1370 | |
| 1371 | static struct rcg_clk tsif_ref_clk_src = { |
| 1372 | .cmd_rcgr_reg = TSIF_REF_CMD_RCGR, |
| 1373 | .set_rate = set_rate_mnd, |
| 1374 | .freq_tbl = ftbl_gcc_tsif_ref_clk, |
| 1375 | .current_freq = &rcg_dummy_freq, |
| 1376 | .base = &virt_bases[GCC_BASE], |
| 1377 | .c = { |
| 1378 | .dbg_name = "tsif_ref_clk_src", |
| 1379 | .ops = &clk_ops_rcg_mnd, |
| 1380 | VDD_DIG_FMAX_MAP1(LOW, 105500), |
| 1381 | CLK_INIT(tsif_ref_clk_src.c), |
| 1382 | }, |
| 1383 | }; |
| 1384 | |
| 1385 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { |
| 1386 | F(60000000, gpll0, 10, 0, 0), |
| 1387 | F_END |
| 1388 | }; |
| 1389 | |
| 1390 | static struct rcg_clk usb30_mock_utmi_clk_src = { |
| 1391 | .cmd_rcgr_reg = USB30_MOCK_UTMI_CMD_RCGR, |
| 1392 | .set_rate = set_rate_hid, |
| 1393 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, |
| 1394 | .current_freq = &rcg_dummy_freq, |
| 1395 | .base = &virt_bases[GCC_BASE], |
| 1396 | .c = { |
| 1397 | .dbg_name = "usb30_mock_utmi_clk_src", |
| 1398 | .ops = &clk_ops_rcg, |
| 1399 | VDD_DIG_FMAX_MAP1(NOMINAL, 60000000), |
| 1400 | CLK_INIT(usb30_mock_utmi_clk_src.c), |
| 1401 | }, |
| 1402 | }; |
| 1403 | |
| 1404 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = { |
| 1405 | F(75000000, gpll0, 8, 0, 0), |
| 1406 | F_END |
| 1407 | }; |
| 1408 | |
| 1409 | static struct rcg_clk usb_hs_system_clk_src = { |
| 1410 | .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR, |
| 1411 | .set_rate = set_rate_hid, |
| 1412 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 1413 | .current_freq = &rcg_dummy_freq, |
| 1414 | .base = &virt_bases[GCC_BASE], |
| 1415 | .c = { |
| 1416 | .dbg_name = "usb_hs_system_clk_src", |
| 1417 | .ops = &clk_ops_rcg, |
| 1418 | VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000), |
| 1419 | CLK_INIT(usb_hs_system_clk_src.c), |
| 1420 | }, |
| 1421 | }; |
| 1422 | |
| 1423 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = { |
| 1424 | F_HSIC(480000000, gpll1, 1, 0, 0), |
| 1425 | F_END |
| 1426 | }; |
| 1427 | |
| 1428 | static struct rcg_clk usb_hsic_clk_src = { |
| 1429 | .cmd_rcgr_reg = USB_HSIC_CMD_RCGR, |
| 1430 | .set_rate = set_rate_hid, |
| 1431 | .freq_tbl = ftbl_gcc_usb_hsic_clk, |
| 1432 | .current_freq = &rcg_dummy_freq, |
| 1433 | .base = &virt_bases[GCC_BASE], |
| 1434 | .c = { |
| 1435 | .dbg_name = "usb_hsic_clk_src", |
| 1436 | .ops = &clk_ops_rcg, |
| 1437 | VDD_DIG_FMAX_MAP1(LOW, 480000000), |
| 1438 | CLK_INIT(usb_hsic_clk_src.c), |
| 1439 | }, |
| 1440 | }; |
| 1441 | |
| 1442 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { |
| 1443 | F(9600000, cxo, 2, 0, 0), |
| 1444 | F_END |
| 1445 | }; |
| 1446 | |
| 1447 | static struct rcg_clk usb_hsic_io_cal_clk_src = { |
| 1448 | .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR, |
| 1449 | .set_rate = set_rate_hid, |
| 1450 | .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, |
| 1451 | .current_freq = &rcg_dummy_freq, |
| 1452 | .base = &virt_bases[GCC_BASE], |
| 1453 | .c = { |
| 1454 | .dbg_name = "usb_hsic_io_cal_clk_src", |
| 1455 | .ops = &clk_ops_rcg, |
| 1456 | VDD_DIG_FMAX_MAP1(LOW, 9600000), |
| 1457 | CLK_INIT(usb_hsic_io_cal_clk_src.c), |
| 1458 | }, |
| 1459 | }; |
| 1460 | |
| 1461 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { |
| 1462 | F(75000000, gpll0, 8, 0, 0), |
| 1463 | F_END |
| 1464 | }; |
| 1465 | |
| 1466 | static struct rcg_clk usb_hsic_system_clk_src = { |
| 1467 | .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR, |
| 1468 | .set_rate = set_rate_hid, |
| 1469 | .freq_tbl = ftbl_gcc_usb_hsic_system_clk, |
| 1470 | .current_freq = &rcg_dummy_freq, |
| 1471 | .base = &virt_bases[GCC_BASE], |
| 1472 | .c = { |
| 1473 | .dbg_name = "usb_hsic_system_clk_src", |
| 1474 | .ops = &clk_ops_rcg, |
| 1475 | VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000), |
| 1476 | CLK_INIT(usb_hsic_system_clk_src.c), |
| 1477 | }, |
| 1478 | }; |
| 1479 | |
| 1480 | static struct local_vote_clk gcc_bam_dma_ahb_clk = { |
| 1481 | .cbcr_reg = BAM_DMA_AHB_CBCR, |
| 1482 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1483 | .en_mask = BIT(12), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1484 | .base = &virt_bases[GCC_BASE], |
| 1485 | .c = { |
| 1486 | .dbg_name = "gcc_bam_dma_ahb_clk", |
| 1487 | .ops = &clk_ops_vote, |
| 1488 | CLK_INIT(gcc_bam_dma_ahb_clk.c), |
| 1489 | }, |
| 1490 | }; |
| 1491 | |
| 1492 | static struct local_vote_clk gcc_blsp1_ahb_clk = { |
| 1493 | .cbcr_reg = BLSP1_AHB_CBCR, |
| 1494 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1495 | .en_mask = BIT(17), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1496 | .base = &virt_bases[GCC_BASE], |
| 1497 | .c = { |
| 1498 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 1499 | .ops = &clk_ops_vote, |
| 1500 | CLK_INIT(gcc_blsp1_ahb_clk.c), |
| 1501 | }, |
| 1502 | }; |
| 1503 | |
| 1504 | static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = { |
| 1505 | .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR, |
| 1506 | .parent = &cxo_clk_src.c, |
| 1507 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1508 | .base = &virt_bases[GCC_BASE], |
| 1509 | .c = { |
| 1510 | .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk", |
| 1511 | .ops = &clk_ops_branch, |
| 1512 | CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c), |
| 1513 | }, |
| 1514 | }; |
| 1515 | |
| 1516 | static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = { |
| 1517 | .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR, |
| 1518 | .parent = &blsp1_qup1_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1519 | .base = &virt_bases[GCC_BASE], |
| 1520 | .c = { |
| 1521 | .dbg_name = "gcc_blsp1_qup1_spi_apps_clk", |
| 1522 | .ops = &clk_ops_branch, |
| 1523 | CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c), |
| 1524 | }, |
| 1525 | }; |
| 1526 | |
| 1527 | static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = { |
| 1528 | .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR, |
| 1529 | .parent = &cxo_clk_src.c, |
| 1530 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1531 | .base = &virt_bases[GCC_BASE], |
| 1532 | .c = { |
| 1533 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 1534 | .ops = &clk_ops_branch, |
| 1535 | CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c), |
| 1536 | }, |
| 1537 | }; |
| 1538 | |
| 1539 | static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = { |
| 1540 | .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR, |
| 1541 | .parent = &blsp1_qup2_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1542 | .base = &virt_bases[GCC_BASE], |
| 1543 | .c = { |
| 1544 | .dbg_name = "gcc_blsp1_qup2_spi_apps_clk", |
| 1545 | .ops = &clk_ops_branch, |
| 1546 | CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c), |
| 1547 | }, |
| 1548 | }; |
| 1549 | |
| 1550 | static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = { |
| 1551 | .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR, |
| 1552 | .parent = &cxo_clk_src.c, |
| 1553 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1554 | .base = &virt_bases[GCC_BASE], |
| 1555 | .c = { |
| 1556 | .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk", |
| 1557 | .ops = &clk_ops_branch, |
| 1558 | CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c), |
| 1559 | }, |
| 1560 | }; |
| 1561 | |
| 1562 | static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = { |
| 1563 | .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR, |
| 1564 | .parent = &blsp1_qup3_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1565 | .base = &virt_bases[GCC_BASE], |
| 1566 | .c = { |
| 1567 | .dbg_name = "gcc_blsp1_qup3_spi_apps_clk", |
| 1568 | .ops = &clk_ops_branch, |
| 1569 | CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c), |
| 1570 | }, |
| 1571 | }; |
| 1572 | |
| 1573 | static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = { |
| 1574 | .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR, |
| 1575 | .parent = &cxo_clk_src.c, |
| 1576 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1577 | .base = &virt_bases[GCC_BASE], |
| 1578 | .c = { |
| 1579 | .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk", |
| 1580 | .ops = &clk_ops_branch, |
| 1581 | CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c), |
| 1582 | }, |
| 1583 | }; |
| 1584 | |
| 1585 | static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = { |
| 1586 | .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR, |
| 1587 | .parent = &blsp1_qup4_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1588 | .base = &virt_bases[GCC_BASE], |
| 1589 | .c = { |
| 1590 | .dbg_name = "gcc_blsp1_qup4_spi_apps_clk", |
| 1591 | .ops = &clk_ops_branch, |
| 1592 | CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c), |
| 1593 | }, |
| 1594 | }; |
| 1595 | |
| 1596 | static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = { |
| 1597 | .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR, |
| 1598 | .parent = &cxo_clk_src.c, |
| 1599 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1600 | .base = &virt_bases[GCC_BASE], |
| 1601 | .c = { |
| 1602 | .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk", |
| 1603 | .ops = &clk_ops_branch, |
| 1604 | CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c), |
| 1605 | }, |
| 1606 | }; |
| 1607 | |
| 1608 | static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = { |
| 1609 | .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR, |
| 1610 | .parent = &blsp1_qup5_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1611 | .base = &virt_bases[GCC_BASE], |
| 1612 | .c = { |
| 1613 | .dbg_name = "gcc_blsp1_qup5_spi_apps_clk", |
| 1614 | .ops = &clk_ops_branch, |
| 1615 | CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c), |
| 1616 | }, |
| 1617 | }; |
| 1618 | |
| 1619 | static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = { |
| 1620 | .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR, |
| 1621 | .parent = &cxo_clk_src.c, |
| 1622 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1623 | .base = &virt_bases[GCC_BASE], |
| 1624 | .c = { |
| 1625 | .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk", |
| 1626 | .ops = &clk_ops_branch, |
| 1627 | CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c), |
| 1628 | }, |
| 1629 | }; |
| 1630 | |
| 1631 | static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = { |
| 1632 | .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR, |
| 1633 | .parent = &blsp1_qup6_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1634 | .base = &virt_bases[GCC_BASE], |
| 1635 | .c = { |
| 1636 | .dbg_name = "gcc_blsp1_qup6_spi_apps_clk", |
| 1637 | .ops = &clk_ops_branch, |
| 1638 | CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c), |
| 1639 | }, |
| 1640 | }; |
| 1641 | |
| 1642 | static struct branch_clk gcc_blsp1_uart1_apps_clk = { |
| 1643 | .cbcr_reg = BLSP1_UART1_APPS_CBCR, |
| 1644 | .parent = &blsp1_uart1_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1645 | .base = &virt_bases[GCC_BASE], |
| 1646 | .c = { |
| 1647 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
| 1648 | .ops = &clk_ops_branch, |
| 1649 | CLK_INIT(gcc_blsp1_uart1_apps_clk.c), |
| 1650 | }, |
| 1651 | }; |
| 1652 | |
| 1653 | static struct branch_clk gcc_blsp1_uart2_apps_clk = { |
| 1654 | .cbcr_reg = BLSP1_UART2_APPS_CBCR, |
| 1655 | .parent = &blsp1_uart2_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1656 | .base = &virt_bases[GCC_BASE], |
| 1657 | .c = { |
| 1658 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 1659 | .ops = &clk_ops_branch, |
| 1660 | CLK_INIT(gcc_blsp1_uart2_apps_clk.c), |
| 1661 | }, |
| 1662 | }; |
| 1663 | |
| 1664 | static struct branch_clk gcc_blsp1_uart3_apps_clk = { |
| 1665 | .cbcr_reg = BLSP1_UART3_APPS_CBCR, |
| 1666 | .parent = &blsp1_uart3_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1667 | .base = &virt_bases[GCC_BASE], |
| 1668 | .c = { |
| 1669 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
| 1670 | .ops = &clk_ops_branch, |
| 1671 | CLK_INIT(gcc_blsp1_uart3_apps_clk.c), |
| 1672 | }, |
| 1673 | }; |
| 1674 | |
| 1675 | static struct branch_clk gcc_blsp1_uart4_apps_clk = { |
| 1676 | .cbcr_reg = BLSP1_UART4_APPS_CBCR, |
| 1677 | .parent = &blsp1_uart4_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1678 | .base = &virt_bases[GCC_BASE], |
| 1679 | .c = { |
| 1680 | .dbg_name = "gcc_blsp1_uart4_apps_clk", |
| 1681 | .ops = &clk_ops_branch, |
| 1682 | CLK_INIT(gcc_blsp1_uart4_apps_clk.c), |
| 1683 | }, |
| 1684 | }; |
| 1685 | |
| 1686 | static struct branch_clk gcc_blsp1_uart5_apps_clk = { |
| 1687 | .cbcr_reg = BLSP1_UART5_APPS_CBCR, |
| 1688 | .parent = &blsp1_uart5_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1689 | .base = &virt_bases[GCC_BASE], |
| 1690 | .c = { |
| 1691 | .dbg_name = "gcc_blsp1_uart5_apps_clk", |
| 1692 | .ops = &clk_ops_branch, |
| 1693 | CLK_INIT(gcc_blsp1_uart5_apps_clk.c), |
| 1694 | }, |
| 1695 | }; |
| 1696 | |
| 1697 | static struct branch_clk gcc_blsp1_uart6_apps_clk = { |
| 1698 | .cbcr_reg = BLSP1_UART6_APPS_CBCR, |
| 1699 | .parent = &blsp1_uart6_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1700 | .base = &virt_bases[GCC_BASE], |
| 1701 | .c = { |
| 1702 | .dbg_name = "gcc_blsp1_uart6_apps_clk", |
| 1703 | .ops = &clk_ops_branch, |
| 1704 | CLK_INIT(gcc_blsp1_uart6_apps_clk.c), |
| 1705 | }, |
| 1706 | }; |
| 1707 | |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 1708 | static struct local_vote_clk gcc_boot_rom_ahb_clk = { |
| 1709 | .cbcr_reg = BOOT_ROM_AHB_CBCR, |
| 1710 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1711 | .en_mask = BIT(10), |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 1712 | .base = &virt_bases[GCC_BASE], |
| 1713 | .c = { |
| 1714 | .dbg_name = "gcc_boot_rom_ahb_clk", |
| 1715 | .ops = &clk_ops_vote, |
| 1716 | CLK_INIT(gcc_boot_rom_ahb_clk.c), |
| 1717 | }, |
| 1718 | }; |
| 1719 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1720 | static struct local_vote_clk gcc_blsp2_ahb_clk = { |
| 1721 | .cbcr_reg = BLSP2_AHB_CBCR, |
| 1722 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1723 | .en_mask = BIT(15), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1724 | .base = &virt_bases[GCC_BASE], |
| 1725 | .c = { |
| 1726 | .dbg_name = "gcc_blsp2_ahb_clk", |
| 1727 | .ops = &clk_ops_vote, |
| 1728 | CLK_INIT(gcc_blsp2_ahb_clk.c), |
| 1729 | }, |
| 1730 | }; |
| 1731 | |
| 1732 | static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = { |
| 1733 | .cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR, |
| 1734 | .parent = &cxo_clk_src.c, |
| 1735 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1736 | .base = &virt_bases[GCC_BASE], |
| 1737 | .c = { |
| 1738 | .dbg_name = "gcc_blsp2_qup1_i2c_apps_clk", |
| 1739 | .ops = &clk_ops_branch, |
| 1740 | CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c), |
| 1741 | }, |
| 1742 | }; |
| 1743 | |
| 1744 | static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = { |
| 1745 | .cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR, |
| 1746 | .parent = &blsp2_qup1_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1747 | .base = &virt_bases[GCC_BASE], |
| 1748 | .c = { |
| 1749 | .dbg_name = "gcc_blsp2_qup1_spi_apps_clk", |
| 1750 | .ops = &clk_ops_branch, |
| 1751 | CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c), |
| 1752 | }, |
| 1753 | }; |
| 1754 | |
| 1755 | static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = { |
| 1756 | .cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR, |
| 1757 | .parent = &cxo_clk_src.c, |
| 1758 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1759 | .base = &virt_bases[GCC_BASE], |
| 1760 | .c = { |
| 1761 | .dbg_name = "gcc_blsp2_qup2_i2c_apps_clk", |
| 1762 | .ops = &clk_ops_branch, |
| 1763 | CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c), |
| 1764 | }, |
| 1765 | }; |
| 1766 | |
| 1767 | static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = { |
| 1768 | .cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR, |
| 1769 | .parent = &blsp2_qup2_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1770 | .base = &virt_bases[GCC_BASE], |
| 1771 | .c = { |
| 1772 | .dbg_name = "gcc_blsp2_qup2_spi_apps_clk", |
| 1773 | .ops = &clk_ops_branch, |
| 1774 | CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c), |
| 1775 | }, |
| 1776 | }; |
| 1777 | |
| 1778 | static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = { |
| 1779 | .cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR, |
| 1780 | .parent = &cxo_clk_src.c, |
| 1781 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1782 | .base = &virt_bases[GCC_BASE], |
| 1783 | .c = { |
| 1784 | .dbg_name = "gcc_blsp2_qup3_i2c_apps_clk", |
| 1785 | .ops = &clk_ops_branch, |
| 1786 | CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c), |
| 1787 | }, |
| 1788 | }; |
| 1789 | |
| 1790 | static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = { |
| 1791 | .cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR, |
| 1792 | .parent = &blsp2_qup3_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1793 | .base = &virt_bases[GCC_BASE], |
| 1794 | .c = { |
| 1795 | .dbg_name = "gcc_blsp2_qup3_spi_apps_clk", |
| 1796 | .ops = &clk_ops_branch, |
| 1797 | CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c), |
| 1798 | }, |
| 1799 | }; |
| 1800 | |
| 1801 | static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = { |
| 1802 | .cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR, |
| 1803 | .parent = &cxo_clk_src.c, |
| 1804 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1805 | .base = &virt_bases[GCC_BASE], |
| 1806 | .c = { |
| 1807 | .dbg_name = "gcc_blsp2_qup4_i2c_apps_clk", |
| 1808 | .ops = &clk_ops_branch, |
| 1809 | CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c), |
| 1810 | }, |
| 1811 | }; |
| 1812 | |
| 1813 | static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = { |
| 1814 | .cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR, |
| 1815 | .parent = &blsp2_qup4_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1816 | .base = &virt_bases[GCC_BASE], |
| 1817 | .c = { |
| 1818 | .dbg_name = "gcc_blsp2_qup4_spi_apps_clk", |
| 1819 | .ops = &clk_ops_branch, |
| 1820 | CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c), |
| 1821 | }, |
| 1822 | }; |
| 1823 | |
| 1824 | static struct branch_clk gcc_blsp2_qup5_i2c_apps_clk = { |
| 1825 | .cbcr_reg = BLSP2_QUP5_I2C_APPS_CBCR, |
| 1826 | .parent = &cxo_clk_src.c, |
| 1827 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1828 | .base = &virt_bases[GCC_BASE], |
| 1829 | .c = { |
| 1830 | .dbg_name = "gcc_blsp2_qup5_i2c_apps_clk", |
| 1831 | .ops = &clk_ops_branch, |
| 1832 | CLK_INIT(gcc_blsp2_qup5_i2c_apps_clk.c), |
| 1833 | }, |
| 1834 | }; |
| 1835 | |
| 1836 | static struct branch_clk gcc_blsp2_qup5_spi_apps_clk = { |
| 1837 | .cbcr_reg = BLSP2_QUP5_SPI_APPS_CBCR, |
| 1838 | .parent = &blsp2_qup5_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1839 | .base = &virt_bases[GCC_BASE], |
| 1840 | .c = { |
| 1841 | .dbg_name = "gcc_blsp2_qup5_spi_apps_clk", |
| 1842 | .ops = &clk_ops_branch, |
| 1843 | CLK_INIT(gcc_blsp2_qup5_spi_apps_clk.c), |
| 1844 | }, |
| 1845 | }; |
| 1846 | |
| 1847 | static struct branch_clk gcc_blsp2_qup6_i2c_apps_clk = { |
| 1848 | .cbcr_reg = BLSP2_QUP6_I2C_APPS_CBCR, |
| 1849 | .parent = &cxo_clk_src.c, |
| 1850 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1851 | .base = &virt_bases[GCC_BASE], |
| 1852 | .c = { |
| 1853 | .dbg_name = "gcc_blsp2_qup6_i2c_apps_clk", |
| 1854 | .ops = &clk_ops_branch, |
| 1855 | CLK_INIT(gcc_blsp2_qup6_i2c_apps_clk.c), |
| 1856 | }, |
| 1857 | }; |
| 1858 | |
| 1859 | static struct branch_clk gcc_blsp2_qup6_spi_apps_clk = { |
| 1860 | .cbcr_reg = BLSP2_QUP6_SPI_APPS_CBCR, |
| 1861 | .parent = &blsp2_qup6_spi_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1862 | .base = &virt_bases[GCC_BASE], |
| 1863 | .c = { |
| 1864 | .dbg_name = "gcc_blsp2_qup6_spi_apps_clk", |
| 1865 | .ops = &clk_ops_branch, |
| 1866 | CLK_INIT(gcc_blsp2_qup6_spi_apps_clk.c), |
| 1867 | }, |
| 1868 | }; |
| 1869 | |
| 1870 | static struct branch_clk gcc_blsp2_uart1_apps_clk = { |
| 1871 | .cbcr_reg = BLSP2_UART1_APPS_CBCR, |
| 1872 | .parent = &blsp2_uart1_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1873 | .base = &virt_bases[GCC_BASE], |
| 1874 | .c = { |
| 1875 | .dbg_name = "gcc_blsp2_uart1_apps_clk", |
| 1876 | .ops = &clk_ops_branch, |
| 1877 | CLK_INIT(gcc_blsp2_uart1_apps_clk.c), |
| 1878 | }, |
| 1879 | }; |
| 1880 | |
| 1881 | static struct branch_clk gcc_blsp2_uart2_apps_clk = { |
| 1882 | .cbcr_reg = BLSP2_UART2_APPS_CBCR, |
| 1883 | .parent = &blsp2_uart2_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1884 | .base = &virt_bases[GCC_BASE], |
| 1885 | .c = { |
| 1886 | .dbg_name = "gcc_blsp2_uart2_apps_clk", |
| 1887 | .ops = &clk_ops_branch, |
| 1888 | CLK_INIT(gcc_blsp2_uart2_apps_clk.c), |
| 1889 | }, |
| 1890 | }; |
| 1891 | |
| 1892 | static struct branch_clk gcc_blsp2_uart3_apps_clk = { |
| 1893 | .cbcr_reg = BLSP2_UART3_APPS_CBCR, |
| 1894 | .parent = &blsp2_uart3_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1895 | .base = &virt_bases[GCC_BASE], |
| 1896 | .c = { |
| 1897 | .dbg_name = "gcc_blsp2_uart3_apps_clk", |
| 1898 | .ops = &clk_ops_branch, |
| 1899 | CLK_INIT(gcc_blsp2_uart3_apps_clk.c), |
| 1900 | }, |
| 1901 | }; |
| 1902 | |
| 1903 | static struct branch_clk gcc_blsp2_uart4_apps_clk = { |
| 1904 | .cbcr_reg = BLSP2_UART4_APPS_CBCR, |
| 1905 | .parent = &blsp2_uart4_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1906 | .base = &virt_bases[GCC_BASE], |
| 1907 | .c = { |
| 1908 | .dbg_name = "gcc_blsp2_uart4_apps_clk", |
| 1909 | .ops = &clk_ops_branch, |
| 1910 | CLK_INIT(gcc_blsp2_uart4_apps_clk.c), |
| 1911 | }, |
| 1912 | }; |
| 1913 | |
| 1914 | static struct branch_clk gcc_blsp2_uart5_apps_clk = { |
| 1915 | .cbcr_reg = BLSP2_UART5_APPS_CBCR, |
| 1916 | .parent = &blsp2_uart5_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1917 | .base = &virt_bases[GCC_BASE], |
| 1918 | .c = { |
| 1919 | .dbg_name = "gcc_blsp2_uart5_apps_clk", |
| 1920 | .ops = &clk_ops_branch, |
| 1921 | CLK_INIT(gcc_blsp2_uart5_apps_clk.c), |
| 1922 | }, |
| 1923 | }; |
| 1924 | |
| 1925 | static struct branch_clk gcc_blsp2_uart6_apps_clk = { |
| 1926 | .cbcr_reg = BLSP2_UART6_APPS_CBCR, |
| 1927 | .parent = &blsp2_uart6_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1928 | .base = &virt_bases[GCC_BASE], |
| 1929 | .c = { |
| 1930 | .dbg_name = "gcc_blsp2_uart6_apps_clk", |
| 1931 | .ops = &clk_ops_branch, |
| 1932 | CLK_INIT(gcc_blsp2_uart6_apps_clk.c), |
| 1933 | }, |
| 1934 | }; |
| 1935 | |
| 1936 | static struct local_vote_clk gcc_ce1_clk = { |
| 1937 | .cbcr_reg = CE1_CBCR, |
| 1938 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1939 | .en_mask = BIT(5), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1940 | .base = &virt_bases[GCC_BASE], |
| 1941 | .c = { |
| 1942 | .dbg_name = "gcc_ce1_clk", |
| 1943 | .ops = &clk_ops_vote, |
| 1944 | CLK_INIT(gcc_ce1_clk.c), |
| 1945 | }, |
| 1946 | }; |
| 1947 | |
| 1948 | static struct local_vote_clk gcc_ce1_ahb_clk = { |
| 1949 | .cbcr_reg = CE1_AHB_CBCR, |
| 1950 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1951 | .en_mask = BIT(3), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1952 | .base = &virt_bases[GCC_BASE], |
| 1953 | .c = { |
| 1954 | .dbg_name = "gcc_ce1_ahb_clk", |
| 1955 | .ops = &clk_ops_vote, |
| 1956 | CLK_INIT(gcc_ce1_ahb_clk.c), |
| 1957 | }, |
| 1958 | }; |
| 1959 | |
| 1960 | static struct local_vote_clk gcc_ce1_axi_clk = { |
| 1961 | .cbcr_reg = CE1_AXI_CBCR, |
| 1962 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1963 | .en_mask = BIT(4), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1964 | .base = &virt_bases[GCC_BASE], |
| 1965 | .c = { |
| 1966 | .dbg_name = "gcc_ce1_axi_clk", |
| 1967 | .ops = &clk_ops_vote, |
| 1968 | CLK_INIT(gcc_ce1_axi_clk.c), |
| 1969 | }, |
| 1970 | }; |
| 1971 | |
| 1972 | static struct local_vote_clk gcc_ce2_clk = { |
| 1973 | .cbcr_reg = CE2_CBCR, |
| 1974 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1975 | .en_mask = BIT(2), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1976 | .base = &virt_bases[GCC_BASE], |
| 1977 | .c = { |
| 1978 | .dbg_name = "gcc_ce2_clk", |
| 1979 | .ops = &clk_ops_vote, |
| 1980 | CLK_INIT(gcc_ce2_clk.c), |
| 1981 | }, |
| 1982 | }; |
| 1983 | |
| 1984 | static struct local_vote_clk gcc_ce2_ahb_clk = { |
| 1985 | .cbcr_reg = CE2_AHB_CBCR, |
| 1986 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1987 | .en_mask = BIT(0), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 1988 | .base = &virt_bases[GCC_BASE], |
| 1989 | .c = { |
| 1990 | .dbg_name = "gcc_ce1_ahb_clk", |
| 1991 | .ops = &clk_ops_vote, |
| 1992 | CLK_INIT(gcc_ce1_ahb_clk.c), |
| 1993 | }, |
| 1994 | }; |
| 1995 | |
| 1996 | static struct local_vote_clk gcc_ce2_axi_clk = { |
| 1997 | .cbcr_reg = CE2_AXI_CBCR, |
| 1998 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1999 | .en_mask = BIT(1), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2000 | .base = &virt_bases[GCC_BASE], |
| 2001 | .c = { |
| 2002 | .dbg_name = "gcc_ce1_axi_clk", |
| 2003 | .ops = &clk_ops_vote, |
| 2004 | CLK_INIT(gcc_ce2_axi_clk.c), |
| 2005 | }, |
| 2006 | }; |
| 2007 | |
| 2008 | static struct branch_clk gcc_gp1_clk = { |
| 2009 | .cbcr_reg = GP1_CBCR, |
| 2010 | .parent = &gp1_clk_src.c, |
| 2011 | .base = &virt_bases[GCC_BASE], |
| 2012 | .c = { |
| 2013 | .dbg_name = "gcc_gp1_clk", |
| 2014 | .ops = &clk_ops_branch, |
| 2015 | CLK_INIT(gcc_gp1_clk.c), |
| 2016 | }, |
| 2017 | }; |
| 2018 | |
| 2019 | static struct branch_clk gcc_gp2_clk = { |
| 2020 | .cbcr_reg = GP2_CBCR, |
| 2021 | .parent = &gp2_clk_src.c, |
| 2022 | .base = &virt_bases[GCC_BASE], |
| 2023 | .c = { |
| 2024 | .dbg_name = "gcc_gp2_clk", |
| 2025 | .ops = &clk_ops_branch, |
| 2026 | CLK_INIT(gcc_gp2_clk.c), |
| 2027 | }, |
| 2028 | }; |
| 2029 | |
| 2030 | static struct branch_clk gcc_gp3_clk = { |
| 2031 | .cbcr_reg = GP3_CBCR, |
| 2032 | .parent = &gp3_clk_src.c, |
| 2033 | .base = &virt_bases[GCC_BASE], |
| 2034 | .c = { |
| 2035 | .dbg_name = "gcc_gp3_clk", |
| 2036 | .ops = &clk_ops_branch, |
| 2037 | CLK_INIT(gcc_gp3_clk.c), |
| 2038 | }, |
| 2039 | }; |
| 2040 | |
| 2041 | static struct branch_clk gcc_pdm2_clk = { |
| 2042 | .cbcr_reg = PDM2_CBCR, |
| 2043 | .parent = &pdm2_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2044 | .base = &virt_bases[GCC_BASE], |
| 2045 | .c = { |
| 2046 | .dbg_name = "gcc_pdm2_clk", |
| 2047 | .ops = &clk_ops_branch, |
| 2048 | CLK_INIT(gcc_pdm2_clk.c), |
| 2049 | }, |
| 2050 | }; |
| 2051 | |
| 2052 | static struct branch_clk gcc_pdm_ahb_clk = { |
| 2053 | .cbcr_reg = PDM_AHB_CBCR, |
| 2054 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2055 | .base = &virt_bases[GCC_BASE], |
| 2056 | .c = { |
| 2057 | .dbg_name = "gcc_pdm_ahb_clk", |
| 2058 | .ops = &clk_ops_branch, |
| 2059 | CLK_INIT(gcc_pdm_ahb_clk.c), |
| 2060 | }, |
| 2061 | }; |
| 2062 | |
| 2063 | static struct local_vote_clk gcc_prng_ahb_clk = { |
| 2064 | .cbcr_reg = PRNG_AHB_CBCR, |
| 2065 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 2066 | .en_mask = BIT(13), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2067 | .base = &virt_bases[GCC_BASE], |
| 2068 | .c = { |
| 2069 | .dbg_name = "gcc_prng_ahb_clk", |
| 2070 | .ops = &clk_ops_vote, |
| 2071 | CLK_INIT(gcc_prng_ahb_clk.c), |
| 2072 | }, |
| 2073 | }; |
| 2074 | |
| 2075 | static struct branch_clk gcc_sdcc1_ahb_clk = { |
| 2076 | .cbcr_reg = SDCC1_AHB_CBCR, |
| 2077 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2078 | .base = &virt_bases[GCC_BASE], |
| 2079 | .c = { |
| 2080 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 2081 | .ops = &clk_ops_branch, |
| 2082 | CLK_INIT(gcc_sdcc1_ahb_clk.c), |
| 2083 | }, |
| 2084 | }; |
| 2085 | |
| 2086 | static struct branch_clk gcc_sdcc1_apps_clk = { |
| 2087 | .cbcr_reg = SDCC1_APPS_CBCR, |
| 2088 | .parent = &sdcc1_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2089 | .base = &virt_bases[GCC_BASE], |
| 2090 | .c = { |
| 2091 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 2092 | .ops = &clk_ops_branch, |
| 2093 | CLK_INIT(gcc_sdcc1_apps_clk.c), |
| 2094 | }, |
| 2095 | }; |
| 2096 | |
| 2097 | static struct branch_clk gcc_sdcc2_ahb_clk = { |
| 2098 | .cbcr_reg = SDCC2_AHB_CBCR, |
| 2099 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2100 | .base = &virt_bases[GCC_BASE], |
| 2101 | .c = { |
| 2102 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 2103 | .ops = &clk_ops_branch, |
| 2104 | CLK_INIT(gcc_sdcc2_ahb_clk.c), |
| 2105 | }, |
| 2106 | }; |
| 2107 | |
| 2108 | static struct branch_clk gcc_sdcc2_apps_clk = { |
| 2109 | .cbcr_reg = SDCC2_APPS_CBCR, |
| 2110 | .parent = &sdcc2_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2111 | .base = &virt_bases[GCC_BASE], |
| 2112 | .c = { |
| 2113 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 2114 | .ops = &clk_ops_branch, |
| 2115 | CLK_INIT(gcc_sdcc2_apps_clk.c), |
| 2116 | }, |
| 2117 | }; |
| 2118 | |
| 2119 | static struct branch_clk gcc_sdcc3_ahb_clk = { |
| 2120 | .cbcr_reg = SDCC3_AHB_CBCR, |
| 2121 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2122 | .base = &virt_bases[GCC_BASE], |
| 2123 | .c = { |
| 2124 | .dbg_name = "gcc_sdcc3_ahb_clk", |
| 2125 | .ops = &clk_ops_branch, |
| 2126 | CLK_INIT(gcc_sdcc3_ahb_clk.c), |
| 2127 | }, |
| 2128 | }; |
| 2129 | |
| 2130 | static struct branch_clk gcc_sdcc3_apps_clk = { |
| 2131 | .cbcr_reg = SDCC3_APPS_CBCR, |
| 2132 | .parent = &sdcc3_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2133 | .base = &virt_bases[GCC_BASE], |
| 2134 | .c = { |
| 2135 | .dbg_name = "gcc_sdcc3_apps_clk", |
| 2136 | .ops = &clk_ops_branch, |
| 2137 | CLK_INIT(gcc_sdcc3_apps_clk.c), |
| 2138 | }, |
| 2139 | }; |
| 2140 | |
| 2141 | static struct branch_clk gcc_sdcc4_ahb_clk = { |
| 2142 | .cbcr_reg = SDCC4_AHB_CBCR, |
| 2143 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2144 | .base = &virt_bases[GCC_BASE], |
| 2145 | .c = { |
| 2146 | .dbg_name = "gcc_sdcc4_ahb_clk", |
| 2147 | .ops = &clk_ops_branch, |
| 2148 | CLK_INIT(gcc_sdcc4_ahb_clk.c), |
| 2149 | }, |
| 2150 | }; |
| 2151 | |
| 2152 | static struct branch_clk gcc_sdcc4_apps_clk = { |
| 2153 | .cbcr_reg = SDCC4_APPS_CBCR, |
| 2154 | .parent = &sdcc4_apps_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2155 | .base = &virt_bases[GCC_BASE], |
| 2156 | .c = { |
| 2157 | .dbg_name = "gcc_sdcc4_apps_clk", |
| 2158 | .ops = &clk_ops_branch, |
| 2159 | CLK_INIT(gcc_sdcc4_apps_clk.c), |
| 2160 | }, |
| 2161 | }; |
| 2162 | |
| 2163 | static struct branch_clk gcc_tsif_ahb_clk = { |
| 2164 | .cbcr_reg = TSIF_AHB_CBCR, |
| 2165 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2166 | .base = &virt_bases[GCC_BASE], |
| 2167 | .c = { |
| 2168 | .dbg_name = "gcc_tsif_ahb_clk", |
| 2169 | .ops = &clk_ops_branch, |
| 2170 | CLK_INIT(gcc_tsif_ahb_clk.c), |
| 2171 | }, |
| 2172 | }; |
| 2173 | |
| 2174 | static struct branch_clk gcc_tsif_ref_clk = { |
| 2175 | .cbcr_reg = TSIF_REF_CBCR, |
| 2176 | .parent = &tsif_ref_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2177 | .base = &virt_bases[GCC_BASE], |
| 2178 | .c = { |
| 2179 | .dbg_name = "gcc_tsif_ref_clk", |
| 2180 | .ops = &clk_ops_branch, |
| 2181 | CLK_INIT(gcc_tsif_ref_clk.c), |
| 2182 | }, |
| 2183 | }; |
| 2184 | |
| 2185 | static struct branch_clk gcc_usb30_master_clk = { |
| 2186 | .cbcr_reg = USB30_MASTER_CBCR, |
Vikram Mulukutla | 777c3ce | 2012-07-03 20:02:55 -0700 | [diff] [blame] | 2187 | .bcr_reg = USB_30_BCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2188 | .parent = &usb30_master_clk_src.c, |
| 2189 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2190 | .base = &virt_bases[GCC_BASE], |
| 2191 | .c = { |
| 2192 | .dbg_name = "gcc_usb30_master_clk", |
| 2193 | .ops = &clk_ops_branch, |
| 2194 | CLK_INIT(gcc_usb30_master_clk.c), |
| 2195 | }, |
| 2196 | }; |
| 2197 | |
| 2198 | static struct branch_clk gcc_usb30_mock_utmi_clk = { |
| 2199 | .cbcr_reg = USB30_MOCK_UTMI_CBCR, |
| 2200 | .parent = &usb30_mock_utmi_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2201 | .base = &virt_bases[GCC_BASE], |
| 2202 | .c = { |
| 2203 | .dbg_name = "gcc_usb30_mock_utmi_clk", |
| 2204 | .ops = &clk_ops_branch, |
| 2205 | CLK_INIT(gcc_usb30_mock_utmi_clk.c), |
| 2206 | }, |
| 2207 | }; |
| 2208 | |
Vikram Mulukutla | 3b98a6d | 2012-08-15 20:35:25 -0700 | [diff] [blame] | 2209 | struct branch_clk gcc_sys_noc_usb3_axi_clk = { |
| 2210 | .cbcr_reg = SYS_NOC_USB3_AXI_CBCR, |
| 2211 | .parent = &usb30_master_clk_src.c, |
| 2212 | .has_sibling = 1, |
| 2213 | .base = &virt_bases[GCC_BASE], |
| 2214 | .c = { |
| 2215 | .dbg_name = "gcc_sys_noc_usb3_axi_clk", |
| 2216 | .ops = &clk_ops_branch, |
| 2217 | CLK_INIT(gcc_sys_noc_usb3_axi_clk.c), |
| 2218 | }, |
| 2219 | }; |
| 2220 | |
| 2221 | struct branch_clk gcc_usb30_sleep_clk = { |
| 2222 | .cbcr_reg = USB30_SLEEP_CBCR, |
| 2223 | .has_sibling = 1, |
| 2224 | .base = &virt_bases[GCC_BASE], |
| 2225 | .c = { |
| 2226 | .dbg_name = "gcc_usb30_sleep_clk", |
| 2227 | .ops = &clk_ops_branch, |
| 2228 | CLK_INIT(gcc_usb30_sleep_clk.c), |
| 2229 | }, |
| 2230 | }; |
| 2231 | |
| 2232 | struct branch_clk gcc_usb2a_phy_sleep_clk = { |
| 2233 | .cbcr_reg = USB2A_PHY_SLEEP_CBCR, |
| 2234 | .has_sibling = 1, |
| 2235 | .base = &virt_bases[GCC_BASE], |
| 2236 | .c = { |
| 2237 | .dbg_name = "gcc_usb2a_phy_sleep_clk", |
| 2238 | .ops = &clk_ops_branch, |
| 2239 | CLK_INIT(gcc_usb2a_phy_sleep_clk.c), |
| 2240 | }, |
| 2241 | }; |
| 2242 | |
| 2243 | struct branch_clk gcc_usb2b_phy_sleep_clk = { |
| 2244 | .cbcr_reg = USB2B_PHY_SLEEP_CBCR, |
| 2245 | .has_sibling = 1, |
| 2246 | .base = &virt_bases[GCC_BASE], |
| 2247 | .c = { |
| 2248 | .dbg_name = "gcc_usb2b_phy_sleep_clk", |
| 2249 | .ops = &clk_ops_branch, |
| 2250 | CLK_INIT(gcc_usb2b_phy_sleep_clk.c), |
| 2251 | }, |
| 2252 | }; |
| 2253 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2254 | static struct branch_clk gcc_usb_hs_ahb_clk = { |
| 2255 | .cbcr_reg = USB_HS_AHB_CBCR, |
| 2256 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2257 | .base = &virt_bases[GCC_BASE], |
| 2258 | .c = { |
| 2259 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 2260 | .ops = &clk_ops_branch, |
| 2261 | CLK_INIT(gcc_usb_hs_ahb_clk.c), |
| 2262 | }, |
| 2263 | }; |
| 2264 | |
| 2265 | static struct branch_clk gcc_usb_hs_system_clk = { |
| 2266 | .cbcr_reg = USB_HS_SYSTEM_CBCR, |
Vikram Mulukutla | 777c3ce | 2012-07-03 20:02:55 -0700 | [diff] [blame] | 2267 | .bcr_reg = USB_HS_BCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2268 | .parent = &usb_hs_system_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2269 | .base = &virt_bases[GCC_BASE], |
| 2270 | .c = { |
| 2271 | .dbg_name = "gcc_usb_hs_system_clk", |
| 2272 | .ops = &clk_ops_branch, |
| 2273 | CLK_INIT(gcc_usb_hs_system_clk.c), |
| 2274 | }, |
| 2275 | }; |
| 2276 | |
| 2277 | static struct branch_clk gcc_usb_hsic_ahb_clk = { |
| 2278 | .cbcr_reg = USB_HSIC_AHB_CBCR, |
| 2279 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2280 | .base = &virt_bases[GCC_BASE], |
| 2281 | .c = { |
| 2282 | .dbg_name = "gcc_usb_hsic_ahb_clk", |
| 2283 | .ops = &clk_ops_branch, |
| 2284 | CLK_INIT(gcc_usb_hsic_ahb_clk.c), |
| 2285 | }, |
| 2286 | }; |
| 2287 | |
| 2288 | static struct branch_clk gcc_usb_hsic_clk = { |
| 2289 | .cbcr_reg = USB_HSIC_CBCR, |
Vikram Mulukutla | 777c3ce | 2012-07-03 20:02:55 -0700 | [diff] [blame] | 2290 | .bcr_reg = USB_HS_HSIC_BCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2291 | .parent = &usb_hsic_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2292 | .base = &virt_bases[GCC_BASE], |
| 2293 | .c = { |
| 2294 | .dbg_name = "gcc_usb_hsic_clk", |
| 2295 | .ops = &clk_ops_branch, |
| 2296 | CLK_INIT(gcc_usb_hsic_clk.c), |
| 2297 | }, |
| 2298 | }; |
| 2299 | |
| 2300 | static struct branch_clk gcc_usb_hsic_io_cal_clk = { |
| 2301 | .cbcr_reg = USB_HSIC_IO_CAL_CBCR, |
| 2302 | .parent = &usb_hsic_io_cal_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2303 | .base = &virt_bases[GCC_BASE], |
| 2304 | .c = { |
| 2305 | .dbg_name = "gcc_usb_hsic_io_cal_clk", |
| 2306 | .ops = &clk_ops_branch, |
| 2307 | CLK_INIT(gcc_usb_hsic_io_cal_clk.c), |
| 2308 | }, |
| 2309 | }; |
| 2310 | |
| 2311 | static struct branch_clk gcc_usb_hsic_system_clk = { |
| 2312 | .cbcr_reg = USB_HSIC_SYSTEM_CBCR, |
| 2313 | .parent = &usb_hsic_system_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2314 | .base = &virt_bases[GCC_BASE], |
| 2315 | .c = { |
| 2316 | .dbg_name = "gcc_usb_hsic_system_clk", |
| 2317 | .ops = &clk_ops_branch, |
| 2318 | CLK_INIT(gcc_usb_hsic_system_clk.c), |
| 2319 | }, |
| 2320 | }; |
| 2321 | |
Vikram Mulukutla | 274b2d9 | 2012-07-13 15:53:04 -0700 | [diff] [blame] | 2322 | struct branch_clk gcc_mmss_noc_cfg_ahb_clk = { |
| 2323 | .cbcr_reg = MMSS_NOC_CFG_AHB_CBCR, |
| 2324 | .has_sibling = 1, |
| 2325 | .base = &virt_bases[GCC_BASE], |
| 2326 | .c = { |
| 2327 | .dbg_name = "gcc_mmss_noc_cfg_ahb_clk", |
| 2328 | .ops = &clk_ops_branch, |
| 2329 | CLK_INIT(gcc_mmss_noc_cfg_ahb_clk.c), |
| 2330 | }, |
| 2331 | }; |
| 2332 | |
| 2333 | struct branch_clk gcc_ocmem_noc_cfg_ahb_clk = { |
| 2334 | .cbcr_reg = OCMEM_NOC_CFG_AHB_CBCR, |
| 2335 | .has_sibling = 1, |
| 2336 | .base = &virt_bases[GCC_BASE], |
| 2337 | .c = { |
| 2338 | .dbg_name = "gcc_ocmem_noc_cfg_ahb_clk", |
| 2339 | .ops = &clk_ops_branch, |
| 2340 | CLK_INIT(gcc_ocmem_noc_cfg_ahb_clk.c), |
| 2341 | }, |
| 2342 | }; |
| 2343 | |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 2344 | static struct branch_clk gcc_mss_cfg_ahb_clk = { |
| 2345 | .cbcr_reg = MSS_CFG_AHB_CBCR, |
| 2346 | .has_sibling = 1, |
| 2347 | .base = &virt_bases[GCC_BASE], |
| 2348 | .c = { |
| 2349 | .dbg_name = "gcc_mss_cfg_ahb_clk", |
| 2350 | .ops = &clk_ops_branch, |
| 2351 | CLK_INIT(gcc_mss_cfg_ahb_clk.c), |
| 2352 | }, |
| 2353 | }; |
| 2354 | |
Vikram Mulukutla | 31926eb | 2012-08-12 19:58:08 -0700 | [diff] [blame] | 2355 | static struct branch_clk gcc_mss_q6_bimc_axi_clk = { |
| 2356 | .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR, |
| 2357 | .has_sibling = 1, |
| 2358 | .base = &virt_bases[GCC_BASE], |
| 2359 | .c = { |
| 2360 | .dbg_name = "gcc_mss_q6_bimc_axi_clk", |
| 2361 | .ops = &clk_ops_branch, |
| 2362 | CLK_INIT(gcc_mss_q6_bimc_axi_clk.c), |
| 2363 | }, |
| 2364 | }; |
| 2365 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2366 | static struct clk_freq_tbl ftbl_mmss_axi_clk[] = { |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 2367 | F_MM( 19200000, cxo, 1, 0, 0), |
| 2368 | F_MM(150000000, gpll0, 4, 0, 0), |
| 2369 | F_MM(282000000, mmpll1, 3, 0, 0), |
Vikram Mulukutla | 2007865 | 2012-07-31 11:22:40 -0700 | [diff] [blame] | 2370 | F_MM(320000000, mmpll0, 2.5, 0, 0), |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 2371 | F_MM(400000000, mmpll0, 2, 0, 0), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2372 | F_END |
| 2373 | }; |
| 2374 | |
| 2375 | static struct rcg_clk axi_clk_src = { |
| 2376 | .cmd_rcgr_reg = 0x5040, |
| 2377 | .set_rate = set_rate_hid, |
| 2378 | .freq_tbl = ftbl_mmss_axi_clk, |
| 2379 | .current_freq = &rcg_dummy_freq, |
| 2380 | .base = &virt_bases[MMSS_BASE], |
| 2381 | .c = { |
| 2382 | .dbg_name = "axi_clk_src", |
| 2383 | .ops = &clk_ops_rcg, |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 2384 | VDD_DIG_FMAX_MAP3(LOW, 150000000, NOMINAL, 282000000, |
| 2385 | HIGH, 320000000), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2386 | CLK_INIT(axi_clk_src.c), |
| 2387 | }, |
| 2388 | }; |
| 2389 | |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 2390 | static struct clk_freq_tbl ftbl_ocmemnoc_clk[] = { |
| 2391 | F_MM( 19200000, cxo, 1, 0, 0), |
| 2392 | F_MM(150000000, gpll0, 4, 0, 0), |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 2393 | F_MM(282000000, mmpll1, 3, 0, 0), |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 2394 | F_MM(400000000, mmpll0, 2, 0, 0), |
| 2395 | F_END |
| 2396 | }; |
| 2397 | |
| 2398 | struct rcg_clk ocmemnoc_clk_src = { |
| 2399 | .cmd_rcgr_reg = OCMEMNOC_CMD_RCGR, |
| 2400 | .set_rate = set_rate_hid, |
| 2401 | .freq_tbl = ftbl_ocmemnoc_clk, |
| 2402 | .current_freq = &rcg_dummy_freq, |
| 2403 | .base = &virt_bases[MMSS_BASE], |
| 2404 | .c = { |
| 2405 | .dbg_name = "ocmemnoc_clk_src", |
| 2406 | .ops = &clk_ops_rcg, |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 2407 | VDD_DIG_FMAX_MAP3(LOW, 150000000, NOMINAL, 282000000, |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 2408 | HIGH, 400000000), |
| 2409 | CLK_INIT(ocmemnoc_clk_src.c), |
| 2410 | }, |
| 2411 | }; |
| 2412 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2413 | static struct clk_freq_tbl ftbl_camss_csi0_3_clk[] = { |
| 2414 | F_MM(100000000, gpll0, 6, 0, 0), |
| 2415 | F_MM(200000000, mmpll0, 4, 0, 0), |
| 2416 | F_END |
| 2417 | }; |
| 2418 | |
| 2419 | static struct rcg_clk csi0_clk_src = { |
| 2420 | .cmd_rcgr_reg = CSI0_CMD_RCGR, |
| 2421 | .set_rate = set_rate_hid, |
| 2422 | .freq_tbl = ftbl_camss_csi0_3_clk, |
| 2423 | .current_freq = &rcg_dummy_freq, |
| 2424 | .base = &virt_bases[MMSS_BASE], |
| 2425 | .c = { |
| 2426 | .dbg_name = "csi0_clk_src", |
| 2427 | .ops = &clk_ops_rcg, |
| 2428 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2429 | CLK_INIT(csi0_clk_src.c), |
| 2430 | }, |
| 2431 | }; |
| 2432 | |
| 2433 | static struct rcg_clk csi1_clk_src = { |
| 2434 | .cmd_rcgr_reg = CSI1_CMD_RCGR, |
| 2435 | .set_rate = set_rate_hid, |
| 2436 | .freq_tbl = ftbl_camss_csi0_3_clk, |
| 2437 | .current_freq = &rcg_dummy_freq, |
| 2438 | .base = &virt_bases[MMSS_BASE], |
| 2439 | .c = { |
| 2440 | .dbg_name = "csi1_clk_src", |
| 2441 | .ops = &clk_ops_rcg, |
| 2442 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2443 | CLK_INIT(csi1_clk_src.c), |
| 2444 | }, |
| 2445 | }; |
| 2446 | |
| 2447 | static struct rcg_clk csi2_clk_src = { |
| 2448 | .cmd_rcgr_reg = CSI2_CMD_RCGR, |
| 2449 | .set_rate = set_rate_hid, |
| 2450 | .freq_tbl = ftbl_camss_csi0_3_clk, |
| 2451 | .current_freq = &rcg_dummy_freq, |
| 2452 | .base = &virt_bases[MMSS_BASE], |
| 2453 | .c = { |
| 2454 | .dbg_name = "csi2_clk_src", |
| 2455 | .ops = &clk_ops_rcg, |
| 2456 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2457 | CLK_INIT(csi2_clk_src.c), |
| 2458 | }, |
| 2459 | }; |
| 2460 | |
| 2461 | static struct rcg_clk csi3_clk_src = { |
| 2462 | .cmd_rcgr_reg = CSI3_CMD_RCGR, |
| 2463 | .set_rate = set_rate_hid, |
| 2464 | .freq_tbl = ftbl_camss_csi0_3_clk, |
| 2465 | .current_freq = &rcg_dummy_freq, |
| 2466 | .base = &virt_bases[MMSS_BASE], |
| 2467 | .c = { |
| 2468 | .dbg_name = "csi3_clk_src", |
| 2469 | .ops = &clk_ops_rcg, |
| 2470 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2471 | CLK_INIT(csi3_clk_src.c), |
| 2472 | }, |
| 2473 | }; |
| 2474 | |
| 2475 | static struct clk_freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { |
| 2476 | F_MM( 37500000, gpll0, 16, 0, 0), |
| 2477 | F_MM( 50000000, gpll0, 12, 0, 0), |
| 2478 | F_MM( 60000000, gpll0, 10, 0, 0), |
| 2479 | F_MM( 80000000, gpll0, 7.5, 0, 0), |
| 2480 | F_MM(100000000, gpll0, 6, 0, 0), |
| 2481 | F_MM(109090000, gpll0, 5.5, 0, 0), |
| 2482 | F_MM(150000000, gpll0, 4, 0, 0), |
| 2483 | F_MM(200000000, gpll0, 3, 0, 0), |
| 2484 | F_MM(228570000, mmpll0, 3.5, 0, 0), |
| 2485 | F_MM(266670000, mmpll0, 3, 0, 0), |
| 2486 | F_MM(320000000, mmpll0, 2.5, 0, 0), |
| 2487 | F_END |
| 2488 | }; |
| 2489 | |
| 2490 | static struct rcg_clk vfe0_clk_src = { |
| 2491 | .cmd_rcgr_reg = VFE0_CMD_RCGR, |
| 2492 | .set_rate = set_rate_hid, |
| 2493 | .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, |
| 2494 | .current_freq = &rcg_dummy_freq, |
| 2495 | .base = &virt_bases[MMSS_BASE], |
| 2496 | .c = { |
| 2497 | .dbg_name = "vfe0_clk_src", |
| 2498 | .ops = &clk_ops_rcg, |
| 2499 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, |
| 2500 | HIGH, 320000000), |
| 2501 | CLK_INIT(vfe0_clk_src.c), |
| 2502 | }, |
| 2503 | }; |
| 2504 | |
| 2505 | static struct rcg_clk vfe1_clk_src = { |
| 2506 | .cmd_rcgr_reg = VFE1_CMD_RCGR, |
| 2507 | .set_rate = set_rate_hid, |
| 2508 | .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, |
| 2509 | .current_freq = &rcg_dummy_freq, |
| 2510 | .base = &virt_bases[MMSS_BASE], |
| 2511 | .c = { |
| 2512 | .dbg_name = "vfe1_clk_src", |
| 2513 | .ops = &clk_ops_rcg, |
| 2514 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, |
| 2515 | HIGH, 320000000), |
| 2516 | CLK_INIT(vfe1_clk_src.c), |
| 2517 | }, |
| 2518 | }; |
| 2519 | |
| 2520 | static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = { |
| 2521 | F_MM( 37500000, gpll0, 16, 0, 0), |
| 2522 | F_MM( 60000000, gpll0, 10, 0, 0), |
| 2523 | F_MM( 75000000, gpll0, 8, 0, 0), |
| 2524 | F_MM( 85710000, gpll0, 7, 0, 0), |
| 2525 | F_MM(100000000, gpll0, 6, 0, 0), |
| 2526 | F_MM(133330000, mmpll0, 6, 0, 0), |
| 2527 | F_MM(160000000, mmpll0, 5, 0, 0), |
| 2528 | F_MM(200000000, mmpll0, 4, 0, 0), |
| 2529 | F_MM(266670000, mmpll0, 3, 0, 0), |
| 2530 | F_MM(320000000, mmpll0, 2.5, 0, 0), |
| 2531 | F_END |
| 2532 | }; |
| 2533 | |
| 2534 | static struct rcg_clk mdp_clk_src = { |
| 2535 | .cmd_rcgr_reg = MDP_CMD_RCGR, |
| 2536 | .set_rate = set_rate_hid, |
| 2537 | .freq_tbl = ftbl_mdss_mdp_clk, |
| 2538 | .current_freq = &rcg_dummy_freq, |
| 2539 | .base = &virt_bases[MMSS_BASE], |
| 2540 | .c = { |
| 2541 | .dbg_name = "mdp_clk_src", |
| 2542 | .ops = &clk_ops_rcg, |
| 2543 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, |
| 2544 | HIGH, 320000000), |
| 2545 | CLK_INIT(mdp_clk_src.c), |
| 2546 | }, |
| 2547 | }; |
| 2548 | |
| 2549 | static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = { |
| 2550 | F_MM(19200000, cxo, 1, 0, 0), |
| 2551 | F_END |
| 2552 | }; |
| 2553 | |
| 2554 | static struct rcg_clk cci_clk_src = { |
| 2555 | .cmd_rcgr_reg = CCI_CMD_RCGR, |
| 2556 | .set_rate = set_rate_hid, |
| 2557 | .freq_tbl = ftbl_camss_cci_cci_clk, |
| 2558 | .current_freq = &rcg_dummy_freq, |
| 2559 | .base = &virt_bases[MMSS_BASE], |
| 2560 | .c = { |
| 2561 | .dbg_name = "cci_clk_src", |
| 2562 | .ops = &clk_ops_rcg, |
| 2563 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 2564 | CLK_INIT(cci_clk_src.c), |
| 2565 | }, |
| 2566 | }; |
| 2567 | |
| 2568 | static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = { |
| 2569 | F_MM( 10000, cxo, 16, 1, 120), |
| 2570 | F_MM( 20000, cxo, 16, 1, 50), |
| 2571 | F_MM( 6000000, gpll0, 10, 1, 10), |
| 2572 | F_MM(12000000, gpll0, 10, 1, 5), |
| 2573 | F_MM(13000000, gpll0, 10, 13, 60), |
| 2574 | F_MM(24000000, gpll0, 5, 1, 5), |
| 2575 | F_END |
| 2576 | }; |
| 2577 | |
| 2578 | static struct rcg_clk mmss_gp0_clk_src = { |
| 2579 | .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR, |
| 2580 | .set_rate = set_rate_mnd, |
| 2581 | .freq_tbl = ftbl_camss_gp0_1_clk, |
| 2582 | .current_freq = &rcg_dummy_freq, |
| 2583 | .base = &virt_bases[MMSS_BASE], |
| 2584 | .c = { |
| 2585 | .dbg_name = "mmss_gp0_clk_src", |
| 2586 | .ops = &clk_ops_rcg_mnd, |
| 2587 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2588 | CLK_INIT(mmss_gp0_clk_src.c), |
| 2589 | }, |
| 2590 | }; |
| 2591 | |
| 2592 | static struct rcg_clk mmss_gp1_clk_src = { |
| 2593 | .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR, |
| 2594 | .set_rate = set_rate_mnd, |
| 2595 | .freq_tbl = ftbl_camss_gp0_1_clk, |
| 2596 | .current_freq = &rcg_dummy_freq, |
| 2597 | .base = &virt_bases[MMSS_BASE], |
| 2598 | .c = { |
| 2599 | .dbg_name = "mmss_gp1_clk_src", |
| 2600 | .ops = &clk_ops_rcg_mnd, |
| 2601 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2602 | CLK_INIT(mmss_gp1_clk_src.c), |
| 2603 | }, |
| 2604 | }; |
| 2605 | |
| 2606 | static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { |
| 2607 | F_MM( 75000000, gpll0, 8, 0, 0), |
| 2608 | F_MM(150000000, gpll0, 4, 0, 0), |
| 2609 | F_MM(200000000, gpll0, 3, 0, 0), |
| 2610 | F_MM(228570000, mmpll0, 3.5, 0, 0), |
| 2611 | F_MM(266670000, mmpll0, 3, 0, 0), |
| 2612 | F_MM(320000000, mmpll0, 2.5, 0, 0), |
| 2613 | F_END |
| 2614 | }; |
| 2615 | |
| 2616 | static struct rcg_clk jpeg0_clk_src = { |
| 2617 | .cmd_rcgr_reg = JPEG0_CMD_RCGR, |
| 2618 | .set_rate = set_rate_hid, |
| 2619 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, |
| 2620 | .current_freq = &rcg_dummy_freq, |
| 2621 | .base = &virt_bases[MMSS_BASE], |
| 2622 | .c = { |
| 2623 | .dbg_name = "jpeg0_clk_src", |
| 2624 | .ops = &clk_ops_rcg, |
| 2625 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, |
| 2626 | HIGH, 320000000), |
| 2627 | CLK_INIT(jpeg0_clk_src.c), |
| 2628 | }, |
| 2629 | }; |
| 2630 | |
| 2631 | static struct rcg_clk jpeg1_clk_src = { |
| 2632 | .cmd_rcgr_reg = JPEG1_CMD_RCGR, |
| 2633 | .set_rate = set_rate_hid, |
| 2634 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, |
| 2635 | .current_freq = &rcg_dummy_freq, |
| 2636 | .base = &virt_bases[MMSS_BASE], |
| 2637 | .c = { |
| 2638 | .dbg_name = "jpeg1_clk_src", |
| 2639 | .ops = &clk_ops_rcg, |
| 2640 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, |
| 2641 | HIGH, 320000000), |
| 2642 | CLK_INIT(jpeg1_clk_src.c), |
| 2643 | }, |
| 2644 | }; |
| 2645 | |
| 2646 | static struct rcg_clk jpeg2_clk_src = { |
| 2647 | .cmd_rcgr_reg = JPEG2_CMD_RCGR, |
| 2648 | .set_rate = set_rate_hid, |
| 2649 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, |
| 2650 | .current_freq = &rcg_dummy_freq, |
| 2651 | .base = &virt_bases[MMSS_BASE], |
| 2652 | .c = { |
| 2653 | .dbg_name = "jpeg2_clk_src", |
| 2654 | .ops = &clk_ops_rcg, |
| 2655 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, |
| 2656 | HIGH, 320000000), |
| 2657 | CLK_INIT(jpeg2_clk_src.c), |
| 2658 | }, |
| 2659 | }; |
| 2660 | |
| 2661 | static struct clk_freq_tbl ftbl_camss_mclk0_3_clk[] = { |
Vikram Mulukutla | 7dc7502 | 2012-08-23 16:50:56 -0700 | [diff] [blame] | 2662 | F_MM(19200000, cxo, 1, 0, 0), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2663 | F_MM(66670000, gpll0, 9, 0, 0), |
| 2664 | F_END |
| 2665 | }; |
| 2666 | |
| 2667 | static struct rcg_clk mclk0_clk_src = { |
| 2668 | .cmd_rcgr_reg = MCLK0_CMD_RCGR, |
| 2669 | .set_rate = set_rate_hid, |
| 2670 | .freq_tbl = ftbl_camss_mclk0_3_clk, |
| 2671 | .current_freq = &rcg_dummy_freq, |
| 2672 | .base = &virt_bases[MMSS_BASE], |
| 2673 | .c = { |
| 2674 | .dbg_name = "mclk0_clk_src", |
| 2675 | .ops = &clk_ops_rcg, |
| 2676 | VDD_DIG_FMAX_MAP1(LOW, 66670000), |
| 2677 | CLK_INIT(mclk0_clk_src.c), |
| 2678 | }, |
| 2679 | }; |
| 2680 | |
| 2681 | static struct rcg_clk mclk1_clk_src = { |
| 2682 | .cmd_rcgr_reg = MCLK1_CMD_RCGR, |
| 2683 | .set_rate = set_rate_hid, |
| 2684 | .freq_tbl = ftbl_camss_mclk0_3_clk, |
| 2685 | .current_freq = &rcg_dummy_freq, |
| 2686 | .base = &virt_bases[MMSS_BASE], |
| 2687 | .c = { |
| 2688 | .dbg_name = "mclk1_clk_src", |
| 2689 | .ops = &clk_ops_rcg, |
| 2690 | VDD_DIG_FMAX_MAP1(LOW, 66670000), |
| 2691 | CLK_INIT(mclk1_clk_src.c), |
| 2692 | }, |
| 2693 | }; |
| 2694 | |
| 2695 | static struct rcg_clk mclk2_clk_src = { |
| 2696 | .cmd_rcgr_reg = MCLK2_CMD_RCGR, |
| 2697 | .set_rate = set_rate_hid, |
| 2698 | .freq_tbl = ftbl_camss_mclk0_3_clk, |
| 2699 | .current_freq = &rcg_dummy_freq, |
| 2700 | .base = &virt_bases[MMSS_BASE], |
| 2701 | .c = { |
| 2702 | .dbg_name = "mclk2_clk_src", |
| 2703 | .ops = &clk_ops_rcg, |
| 2704 | VDD_DIG_FMAX_MAP1(LOW, 66670000), |
| 2705 | CLK_INIT(mclk2_clk_src.c), |
| 2706 | }, |
| 2707 | }; |
| 2708 | |
| 2709 | static struct rcg_clk mclk3_clk_src = { |
| 2710 | .cmd_rcgr_reg = MCLK3_CMD_RCGR, |
| 2711 | .set_rate = set_rate_hid, |
| 2712 | .freq_tbl = ftbl_camss_mclk0_3_clk, |
| 2713 | .current_freq = &rcg_dummy_freq, |
| 2714 | .base = &virt_bases[MMSS_BASE], |
| 2715 | .c = { |
| 2716 | .dbg_name = "mclk3_clk_src", |
| 2717 | .ops = &clk_ops_rcg, |
| 2718 | VDD_DIG_FMAX_MAP1(LOW, 66670000), |
| 2719 | CLK_INIT(mclk3_clk_src.c), |
| 2720 | }, |
| 2721 | }; |
| 2722 | |
| 2723 | static struct clk_freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { |
| 2724 | F_MM(100000000, gpll0, 6, 0, 0), |
| 2725 | F_MM(200000000, mmpll0, 4, 0, 0), |
| 2726 | F_END |
| 2727 | }; |
| 2728 | |
| 2729 | static struct rcg_clk csi0phytimer_clk_src = { |
| 2730 | .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR, |
| 2731 | .set_rate = set_rate_hid, |
| 2732 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, |
| 2733 | .current_freq = &rcg_dummy_freq, |
| 2734 | .base = &virt_bases[MMSS_BASE], |
| 2735 | .c = { |
| 2736 | .dbg_name = "csi0phytimer_clk_src", |
| 2737 | .ops = &clk_ops_rcg, |
| 2738 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2739 | CLK_INIT(csi0phytimer_clk_src.c), |
| 2740 | }, |
| 2741 | }; |
| 2742 | |
| 2743 | static struct rcg_clk csi1phytimer_clk_src = { |
| 2744 | .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR, |
| 2745 | .set_rate = set_rate_hid, |
| 2746 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, |
| 2747 | .current_freq = &rcg_dummy_freq, |
| 2748 | .base = &virt_bases[MMSS_BASE], |
| 2749 | .c = { |
| 2750 | .dbg_name = "csi1phytimer_clk_src", |
| 2751 | .ops = &clk_ops_rcg, |
| 2752 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2753 | CLK_INIT(csi1phytimer_clk_src.c), |
| 2754 | }, |
| 2755 | }; |
| 2756 | |
| 2757 | static struct rcg_clk csi2phytimer_clk_src = { |
| 2758 | .cmd_rcgr_reg = CSI2PHYTIMER_CMD_RCGR, |
| 2759 | .set_rate = set_rate_hid, |
| 2760 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, |
| 2761 | .current_freq = &rcg_dummy_freq, |
| 2762 | .base = &virt_bases[MMSS_BASE], |
| 2763 | .c = { |
| 2764 | .dbg_name = "csi2phytimer_clk_src", |
| 2765 | .ops = &clk_ops_rcg, |
| 2766 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2767 | CLK_INIT(csi2phytimer_clk_src.c), |
| 2768 | }, |
| 2769 | }; |
| 2770 | |
| 2771 | static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = { |
| 2772 | F_MM(150000000, gpll0, 4, 0, 0), |
| 2773 | F_MM(266670000, mmpll0, 3, 0, 0), |
| 2774 | F_MM(320000000, mmpll0, 2.5, 0, 0), |
| 2775 | F_END |
| 2776 | }; |
| 2777 | |
| 2778 | static struct rcg_clk cpp_clk_src = { |
| 2779 | .cmd_rcgr_reg = CPP_CMD_RCGR, |
| 2780 | .set_rate = set_rate_hid, |
| 2781 | .freq_tbl = ftbl_camss_vfe_cpp_clk, |
| 2782 | .current_freq = &rcg_dummy_freq, |
| 2783 | .base = &virt_bases[MMSS_BASE], |
| 2784 | .c = { |
| 2785 | .dbg_name = "cpp_clk_src", |
| 2786 | .ops = &clk_ops_rcg, |
| 2787 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, |
| 2788 | HIGH, 320000000), |
| 2789 | CLK_INIT(cpp_clk_src.c), |
| 2790 | }, |
| 2791 | }; |
| 2792 | |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 2793 | static struct clk *dsi_pll_clk_get_parent(struct clk *c) |
| 2794 | { |
| 2795 | return &cxo_clk_src.c; |
| 2796 | } |
| 2797 | |
| 2798 | static struct clk dsipll0_byte_clk_src = { |
| 2799 | .dbg_name = "dsipll0_byte_clk_src", |
| 2800 | .ops = &clk_ops_dsi_byte_pll, |
| 2801 | CLK_INIT(dsipll0_byte_clk_src), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2802 | }; |
| 2803 | |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 2804 | static struct clk dsipll0_pixel_clk_src = { |
| 2805 | .dbg_name = "dsipll0_pixel_clk_src", |
| 2806 | .ops = &clk_ops_dsi_pixel_pll, |
| 2807 | CLK_INIT(dsipll0_pixel_clk_src), |
| 2808 | }; |
| 2809 | |
| 2810 | static struct clk_freq_tbl byte_freq = { |
| 2811 | .src_clk = &dsipll0_byte_clk_src, |
| 2812 | .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val), |
| 2813 | }; |
| 2814 | static struct clk_freq_tbl pixel_freq = { |
| 2815 | .src_clk = &dsipll0_byte_clk_src, |
| 2816 | .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val), |
| 2817 | }; |
| 2818 | static struct clk_ops clk_ops_byte; |
| 2819 | static struct clk_ops clk_ops_pixel; |
| 2820 | |
| 2821 | #define CFG_RCGR_DIV_MASK BM(4, 0) |
| 2822 | |
| 2823 | static int set_rate_byte(struct clk *clk, unsigned long rate) |
| 2824 | { |
| 2825 | struct rcg_clk *rcg = to_rcg_clk(clk); |
| 2826 | struct clk *pll = &dsipll0_byte_clk_src; |
| 2827 | unsigned long source_rate, div; |
| 2828 | int rc; |
| 2829 | |
| 2830 | if (rate == 0) |
| 2831 | return -EINVAL; |
| 2832 | |
| 2833 | rc = clk_set_rate(pll, rate); |
| 2834 | if (rc) |
| 2835 | return rc; |
| 2836 | |
| 2837 | source_rate = clk_round_rate(pll, rate); |
| 2838 | if ((2 * source_rate) % rate) |
| 2839 | return -EINVAL; |
| 2840 | |
| 2841 | div = ((2 * source_rate)/rate) - 1; |
| 2842 | if (div > CFG_RCGR_DIV_MASK) |
| 2843 | return -EINVAL; |
| 2844 | |
| 2845 | byte_freq.div_src_val &= ~CFG_RCGR_DIV_MASK; |
| 2846 | byte_freq.div_src_val |= BVAL(4, 0, div); |
| 2847 | set_rate_mnd(rcg, &byte_freq); |
| 2848 | |
| 2849 | return 0; |
| 2850 | } |
| 2851 | |
| 2852 | static int set_rate_pixel(struct clk *clk, unsigned long rate) |
| 2853 | { |
| 2854 | struct rcg_clk *rcg = to_rcg_clk(clk); |
| 2855 | struct clk *pll = &dsipll0_pixel_clk_src; |
| 2856 | unsigned long source_rate, div; |
| 2857 | int rc; |
| 2858 | |
| 2859 | if (rate == 0) |
| 2860 | return -EINVAL; |
| 2861 | |
| 2862 | rc = clk_set_rate(pll, rate); |
| 2863 | if (rc) |
| 2864 | return rc; |
| 2865 | |
| 2866 | source_rate = clk_round_rate(pll, rate); |
| 2867 | if ((2 * source_rate) % rate) |
| 2868 | return -EINVAL; |
| 2869 | |
| 2870 | div = ((2 * source_rate)/rate) - 1; |
| 2871 | if (div > CFG_RCGR_DIV_MASK) |
| 2872 | return -EINVAL; |
| 2873 | |
| 2874 | pixel_freq.div_src_val &= ~CFG_RCGR_DIV_MASK; |
| 2875 | pixel_freq.div_src_val |= BVAL(4, 0, div); |
| 2876 | set_rate_hid(rcg, &pixel_freq); |
| 2877 | |
| 2878 | return 0; |
| 2879 | } |
| 2880 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2881 | static struct rcg_clk byte0_clk_src = { |
| 2882 | .cmd_rcgr_reg = BYTE0_CMD_RCGR, |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 2883 | .current_freq = &byte_freq, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2884 | .base = &virt_bases[MMSS_BASE], |
| 2885 | .c = { |
| 2886 | .dbg_name = "byte0_clk_src", |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 2887 | .ops = &clk_ops_byte, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2888 | VDD_DIG_FMAX_MAP3(LOW, 93800000, NOMINAL, 187500000, |
| 2889 | HIGH, 188000000), |
| 2890 | CLK_INIT(byte0_clk_src.c), |
| 2891 | }, |
| 2892 | }; |
| 2893 | |
| 2894 | static struct rcg_clk byte1_clk_src = { |
| 2895 | .cmd_rcgr_reg = BYTE1_CMD_RCGR, |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 2896 | .current_freq = &byte_freq, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2897 | .base = &virt_bases[MMSS_BASE], |
| 2898 | .c = { |
| 2899 | .dbg_name = "byte1_clk_src", |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 2900 | .ops = &clk_ops_byte, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 2901 | VDD_DIG_FMAX_MAP3(LOW, 93800000, NOMINAL, 187500000, |
| 2902 | HIGH, 188000000), |
| 2903 | CLK_INIT(byte1_clk_src.c), |
| 2904 | }, |
| 2905 | }; |
| 2906 | |
| 2907 | static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = { |
| 2908 | F_MM(19200000, cxo, 1, 0, 0), |
| 2909 | F_END |
| 2910 | }; |
| 2911 | |
| 2912 | static struct rcg_clk edpaux_clk_src = { |
| 2913 | .cmd_rcgr_reg = EDPAUX_CMD_RCGR, |
| 2914 | .set_rate = set_rate_hid, |
| 2915 | .freq_tbl = ftbl_mdss_edpaux_clk, |
| 2916 | .current_freq = &rcg_dummy_freq, |
| 2917 | .base = &virt_bases[MMSS_BASE], |
| 2918 | .c = { |
| 2919 | .dbg_name = "edpaux_clk_src", |
| 2920 | .ops = &clk_ops_rcg, |
| 2921 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 2922 | CLK_INIT(edpaux_clk_src.c), |
| 2923 | }, |
| 2924 | }; |
| 2925 | |
| 2926 | static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = { |
| 2927 | F_MDSS(135000000, edppll_270, 2, 0, 0), |
| 2928 | F_MDSS(270000000, edppll_270, 11, 0, 0), |
| 2929 | F_END |
| 2930 | }; |
| 2931 | |
| 2932 | static struct rcg_clk edplink_clk_src = { |
| 2933 | .cmd_rcgr_reg = EDPLINK_CMD_RCGR, |
| 2934 | .set_rate = set_rate_hid, |
| 2935 | .freq_tbl = ftbl_mdss_edplink_clk, |
| 2936 | .current_freq = &rcg_dummy_freq, |
| 2937 | .base = &virt_bases[MMSS_BASE], |
| 2938 | .c = { |
| 2939 | .dbg_name = "edplink_clk_src", |
| 2940 | .ops = &clk_ops_rcg, |
| 2941 | VDD_DIG_FMAX_MAP2(LOW, 135000000, NOMINAL, 270000000), |
| 2942 | CLK_INIT(edplink_clk_src.c), |
| 2943 | }, |
| 2944 | }; |
| 2945 | |
| 2946 | static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = { |
| 2947 | F_MDSS(175000000, edppll_350, 2, 0, 0), |
| 2948 | F_MDSS(350000000, edppll_350, 11, 0, 0), |
| 2949 | F_END |
| 2950 | }; |
| 2951 | |
| 2952 | static struct rcg_clk edppixel_clk_src = { |
| 2953 | .cmd_rcgr_reg = EDPPIXEL_CMD_RCGR, |
| 2954 | .set_rate = set_rate_mnd, |
| 2955 | .freq_tbl = ftbl_mdss_edppixel_clk, |
| 2956 | .current_freq = &rcg_dummy_freq, |
| 2957 | .base = &virt_bases[MMSS_BASE], |
| 2958 | .c = { |
| 2959 | .dbg_name = "edppixel_clk_src", |
| 2960 | .ops = &clk_ops_rcg_mnd, |
| 2961 | VDD_DIG_FMAX_MAP2(LOW, 175000000, NOMINAL, 350000000), |
| 2962 | CLK_INIT(edppixel_clk_src.c), |
| 2963 | }, |
| 2964 | }; |
| 2965 | |
| 2966 | static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = { |
| 2967 | F_MM(19200000, cxo, 1, 0, 0), |
| 2968 | F_END |
| 2969 | }; |
| 2970 | |
| 2971 | static struct rcg_clk esc0_clk_src = { |
| 2972 | .cmd_rcgr_reg = ESC0_CMD_RCGR, |
| 2973 | .set_rate = set_rate_hid, |
| 2974 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 2975 | .current_freq = &rcg_dummy_freq, |
| 2976 | .base = &virt_bases[MMSS_BASE], |
| 2977 | .c = { |
| 2978 | .dbg_name = "esc0_clk_src", |
| 2979 | .ops = &clk_ops_rcg, |
| 2980 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 2981 | CLK_INIT(esc0_clk_src.c), |
| 2982 | }, |
| 2983 | }; |
| 2984 | |
| 2985 | static struct rcg_clk esc1_clk_src = { |
| 2986 | .cmd_rcgr_reg = ESC1_CMD_RCGR, |
| 2987 | .set_rate = set_rate_hid, |
| 2988 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 2989 | .current_freq = &rcg_dummy_freq, |
| 2990 | .base = &virt_bases[MMSS_BASE], |
| 2991 | .c = { |
| 2992 | .dbg_name = "esc1_clk_src", |
| 2993 | .ops = &clk_ops_rcg, |
| 2994 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 2995 | CLK_INIT(esc1_clk_src.c), |
| 2996 | }, |
| 2997 | }; |
| 2998 | |
| 2999 | static struct clk_freq_tbl ftbl_mdss_extpclk_clk[] = { |
| 3000 | F_MDSS(148500000, hdmipll_297, 2, 0, 0), |
| 3001 | F_END |
| 3002 | }; |
| 3003 | |
| 3004 | static struct rcg_clk extpclk_clk_src = { |
| 3005 | .cmd_rcgr_reg = EXTPCLK_CMD_RCGR, |
| 3006 | .set_rate = set_rate_hid, |
| 3007 | .freq_tbl = ftbl_mdss_extpclk_clk, |
| 3008 | .current_freq = &rcg_dummy_freq, |
| 3009 | .base = &virt_bases[MMSS_BASE], |
| 3010 | .c = { |
| 3011 | .dbg_name = "extpclk_clk_src", |
| 3012 | .ops = &clk_ops_rcg, |
| 3013 | VDD_DIG_FMAX_MAP2(LOW, 148500000, NOMINAL, 297000000), |
| 3014 | CLK_INIT(extpclk_clk_src.c), |
| 3015 | }, |
| 3016 | }; |
| 3017 | |
| 3018 | static struct clk_freq_tbl ftbl_mdss_hdmi_clk[] = { |
| 3019 | F_MDSS(19200000, cxo, 1, 0, 0), |
| 3020 | F_END |
| 3021 | }; |
| 3022 | |
| 3023 | static struct rcg_clk hdmi_clk_src = { |
| 3024 | .cmd_rcgr_reg = HDMI_CMD_RCGR, |
| 3025 | .set_rate = set_rate_hid, |
| 3026 | .freq_tbl = ftbl_mdss_hdmi_clk, |
| 3027 | .current_freq = &rcg_dummy_freq, |
| 3028 | .base = &virt_bases[MMSS_BASE], |
| 3029 | .c = { |
| 3030 | .dbg_name = "hdmi_clk_src", |
| 3031 | .ops = &clk_ops_rcg, |
| 3032 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 3033 | CLK_INIT(hdmi_clk_src.c), |
| 3034 | }, |
| 3035 | }; |
| 3036 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3037 | |
| 3038 | static struct rcg_clk pclk0_clk_src = { |
| 3039 | .cmd_rcgr_reg = PCLK0_CMD_RCGR, |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 3040 | .current_freq = &pixel_freq, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3041 | .base = &virt_bases[MMSS_BASE], |
| 3042 | .c = { |
| 3043 | .dbg_name = "pclk0_clk_src", |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 3044 | .ops = &clk_ops_pixel, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3045 | VDD_DIG_FMAX_MAP2(LOW, 125000000, NOMINAL, 250000000), |
| 3046 | CLK_INIT(pclk0_clk_src.c), |
| 3047 | }, |
| 3048 | }; |
| 3049 | |
| 3050 | static struct rcg_clk pclk1_clk_src = { |
| 3051 | .cmd_rcgr_reg = PCLK1_CMD_RCGR, |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 3052 | .current_freq = &pixel_freq, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3053 | .base = &virt_bases[MMSS_BASE], |
| 3054 | .c = { |
| 3055 | .dbg_name = "pclk1_clk_src", |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 3056 | .ops = &clk_ops_pixel, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3057 | VDD_DIG_FMAX_MAP2(LOW, 125000000, NOMINAL, 250000000), |
| 3058 | CLK_INIT(pclk1_clk_src.c), |
| 3059 | }, |
| 3060 | }; |
| 3061 | |
| 3062 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 3063 | F_MDSS(19200000, cxo, 1, 0, 0), |
| 3064 | F_END |
| 3065 | }; |
| 3066 | |
| 3067 | static struct rcg_clk vsync_clk_src = { |
| 3068 | .cmd_rcgr_reg = VSYNC_CMD_RCGR, |
| 3069 | .set_rate = set_rate_hid, |
| 3070 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 3071 | .current_freq = &rcg_dummy_freq, |
| 3072 | .base = &virt_bases[MMSS_BASE], |
| 3073 | .c = { |
| 3074 | .dbg_name = "vsync_clk_src", |
| 3075 | .ops = &clk_ops_rcg, |
| 3076 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 3077 | CLK_INIT(vsync_clk_src.c), |
| 3078 | }, |
| 3079 | }; |
| 3080 | |
| 3081 | static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = { |
| 3082 | F_MM( 50000000, gpll0, 12, 0, 0), |
| 3083 | F_MM(100000000, gpll0, 6, 0, 0), |
| 3084 | F_MM(133330000, mmpll0, 6, 0, 0), |
| 3085 | F_MM(200000000, mmpll0, 4, 0, 0), |
| 3086 | F_MM(266670000, mmpll0, 3, 0, 0), |
| 3087 | F_MM(410000000, mmpll3, 2, 0, 0), |
| 3088 | F_END |
| 3089 | }; |
| 3090 | |
| 3091 | static struct rcg_clk vcodec0_clk_src = { |
| 3092 | .cmd_rcgr_reg = VCODEC0_CMD_RCGR, |
| 3093 | .set_rate = set_rate_mnd, |
| 3094 | .freq_tbl = ftbl_venus0_vcodec0_clk, |
| 3095 | .current_freq = &rcg_dummy_freq, |
| 3096 | .base = &virt_bases[MMSS_BASE], |
| 3097 | .c = { |
| 3098 | .dbg_name = "vcodec0_clk_src", |
| 3099 | .ops = &clk_ops_rcg_mnd, |
| 3100 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, |
| 3101 | HIGH, 410000000), |
| 3102 | CLK_INIT(vcodec0_clk_src.c), |
| 3103 | }, |
| 3104 | }; |
| 3105 | |
| 3106 | static struct branch_clk camss_cci_cci_ahb_clk = { |
| 3107 | .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3108 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3109 | .base = &virt_bases[MMSS_BASE], |
| 3110 | .c = { |
| 3111 | .dbg_name = "camss_cci_cci_ahb_clk", |
| 3112 | .ops = &clk_ops_branch, |
| 3113 | CLK_INIT(camss_cci_cci_ahb_clk.c), |
| 3114 | }, |
| 3115 | }; |
| 3116 | |
| 3117 | static struct branch_clk camss_cci_cci_clk = { |
| 3118 | .cbcr_reg = CAMSS_CCI_CCI_CBCR, |
| 3119 | .parent = &cci_clk_src.c, |
| 3120 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3121 | .base = &virt_bases[MMSS_BASE], |
| 3122 | .c = { |
| 3123 | .dbg_name = "camss_cci_cci_clk", |
| 3124 | .ops = &clk_ops_branch, |
| 3125 | CLK_INIT(camss_cci_cci_clk.c), |
| 3126 | }, |
| 3127 | }; |
| 3128 | |
| 3129 | static struct branch_clk camss_csi0_ahb_clk = { |
| 3130 | .cbcr_reg = CAMSS_CSI0_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3131 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3132 | .base = &virt_bases[MMSS_BASE], |
| 3133 | .c = { |
| 3134 | .dbg_name = "camss_csi0_ahb_clk", |
| 3135 | .ops = &clk_ops_branch, |
| 3136 | CLK_INIT(camss_csi0_ahb_clk.c), |
| 3137 | }, |
| 3138 | }; |
| 3139 | |
| 3140 | static struct branch_clk camss_csi0_clk = { |
| 3141 | .cbcr_reg = CAMSS_CSI0_CBCR, |
| 3142 | .parent = &csi0_clk_src.c, |
| 3143 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3144 | .base = &virt_bases[MMSS_BASE], |
| 3145 | .c = { |
| 3146 | .dbg_name = "camss_csi0_clk", |
| 3147 | .ops = &clk_ops_branch, |
| 3148 | CLK_INIT(camss_csi0_clk.c), |
| 3149 | }, |
| 3150 | }; |
| 3151 | |
| 3152 | static struct branch_clk camss_csi0phy_clk = { |
| 3153 | .cbcr_reg = CAMSS_CSI0PHY_CBCR, |
| 3154 | .parent = &csi0_clk_src.c, |
| 3155 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3156 | .base = &virt_bases[MMSS_BASE], |
| 3157 | .c = { |
| 3158 | .dbg_name = "camss_csi0phy_clk", |
| 3159 | .ops = &clk_ops_branch, |
| 3160 | CLK_INIT(camss_csi0phy_clk.c), |
| 3161 | }, |
| 3162 | }; |
| 3163 | |
| 3164 | static struct branch_clk camss_csi0pix_clk = { |
| 3165 | .cbcr_reg = CAMSS_CSI0PIX_CBCR, |
| 3166 | .parent = &csi0_clk_src.c, |
| 3167 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3168 | .base = &virt_bases[MMSS_BASE], |
| 3169 | .c = { |
| 3170 | .dbg_name = "camss_csi0pix_clk", |
| 3171 | .ops = &clk_ops_branch, |
| 3172 | CLK_INIT(camss_csi0pix_clk.c), |
| 3173 | }, |
| 3174 | }; |
| 3175 | |
| 3176 | static struct branch_clk camss_csi0rdi_clk = { |
| 3177 | .cbcr_reg = CAMSS_CSI0RDI_CBCR, |
| 3178 | .parent = &csi0_clk_src.c, |
| 3179 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3180 | .base = &virt_bases[MMSS_BASE], |
| 3181 | .c = { |
| 3182 | .dbg_name = "camss_csi0rdi_clk", |
| 3183 | .ops = &clk_ops_branch, |
| 3184 | CLK_INIT(camss_csi0rdi_clk.c), |
| 3185 | }, |
| 3186 | }; |
| 3187 | |
| 3188 | static struct branch_clk camss_csi1_ahb_clk = { |
| 3189 | .cbcr_reg = CAMSS_CSI1_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3190 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3191 | .base = &virt_bases[MMSS_BASE], |
| 3192 | .c = { |
| 3193 | .dbg_name = "camss_csi1_ahb_clk", |
| 3194 | .ops = &clk_ops_branch, |
| 3195 | CLK_INIT(camss_csi1_ahb_clk.c), |
| 3196 | }, |
| 3197 | }; |
| 3198 | |
| 3199 | static struct branch_clk camss_csi1_clk = { |
| 3200 | .cbcr_reg = CAMSS_CSI1_CBCR, |
| 3201 | .parent = &csi1_clk_src.c, |
| 3202 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3203 | .base = &virt_bases[MMSS_BASE], |
| 3204 | .c = { |
| 3205 | .dbg_name = "camss_csi1_clk", |
| 3206 | .ops = &clk_ops_branch, |
| 3207 | CLK_INIT(camss_csi1_clk.c), |
| 3208 | }, |
| 3209 | }; |
| 3210 | |
| 3211 | static struct branch_clk camss_csi1phy_clk = { |
| 3212 | .cbcr_reg = CAMSS_CSI1PHY_CBCR, |
| 3213 | .parent = &csi1_clk_src.c, |
| 3214 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3215 | .base = &virt_bases[MMSS_BASE], |
| 3216 | .c = { |
| 3217 | .dbg_name = "camss_csi1phy_clk", |
| 3218 | .ops = &clk_ops_branch, |
| 3219 | CLK_INIT(camss_csi1phy_clk.c), |
| 3220 | }, |
| 3221 | }; |
| 3222 | |
| 3223 | static struct branch_clk camss_csi1pix_clk = { |
| 3224 | .cbcr_reg = CAMSS_CSI1PIX_CBCR, |
| 3225 | .parent = &csi1_clk_src.c, |
| 3226 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3227 | .base = &virt_bases[MMSS_BASE], |
| 3228 | .c = { |
| 3229 | .dbg_name = "camss_csi1pix_clk", |
| 3230 | .ops = &clk_ops_branch, |
| 3231 | CLK_INIT(camss_csi1pix_clk.c), |
| 3232 | }, |
| 3233 | }; |
| 3234 | |
| 3235 | static struct branch_clk camss_csi1rdi_clk = { |
| 3236 | .cbcr_reg = CAMSS_CSI1RDI_CBCR, |
| 3237 | .parent = &csi1_clk_src.c, |
| 3238 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3239 | .base = &virt_bases[MMSS_BASE], |
| 3240 | .c = { |
| 3241 | .dbg_name = "camss_csi1rdi_clk", |
| 3242 | .ops = &clk_ops_branch, |
| 3243 | CLK_INIT(camss_csi1rdi_clk.c), |
| 3244 | }, |
| 3245 | }; |
| 3246 | |
| 3247 | static struct branch_clk camss_csi2_ahb_clk = { |
| 3248 | .cbcr_reg = CAMSS_CSI2_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3249 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3250 | .base = &virt_bases[MMSS_BASE], |
| 3251 | .c = { |
| 3252 | .dbg_name = "camss_csi2_ahb_clk", |
| 3253 | .ops = &clk_ops_branch, |
| 3254 | CLK_INIT(camss_csi2_ahb_clk.c), |
| 3255 | }, |
| 3256 | }; |
| 3257 | |
| 3258 | static struct branch_clk camss_csi2_clk = { |
| 3259 | .cbcr_reg = CAMSS_CSI2_CBCR, |
| 3260 | .parent = &csi2_clk_src.c, |
| 3261 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3262 | .base = &virt_bases[MMSS_BASE], |
| 3263 | .c = { |
| 3264 | .dbg_name = "camss_csi2_clk", |
| 3265 | .ops = &clk_ops_branch, |
| 3266 | CLK_INIT(camss_csi2_clk.c), |
| 3267 | }, |
| 3268 | }; |
| 3269 | |
| 3270 | static struct branch_clk camss_csi2phy_clk = { |
| 3271 | .cbcr_reg = CAMSS_CSI2PHY_CBCR, |
| 3272 | .parent = &csi2_clk_src.c, |
| 3273 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3274 | .base = &virt_bases[MMSS_BASE], |
| 3275 | .c = { |
| 3276 | .dbg_name = "camss_csi2phy_clk", |
| 3277 | .ops = &clk_ops_branch, |
| 3278 | CLK_INIT(camss_csi2phy_clk.c), |
| 3279 | }, |
| 3280 | }; |
| 3281 | |
| 3282 | static struct branch_clk camss_csi2pix_clk = { |
| 3283 | .cbcr_reg = CAMSS_CSI2PIX_CBCR, |
| 3284 | .parent = &csi2_clk_src.c, |
| 3285 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3286 | .base = &virt_bases[MMSS_BASE], |
| 3287 | .c = { |
| 3288 | .dbg_name = "camss_csi2pix_clk", |
| 3289 | .ops = &clk_ops_branch, |
| 3290 | CLK_INIT(camss_csi2pix_clk.c), |
| 3291 | }, |
| 3292 | }; |
| 3293 | |
| 3294 | static struct branch_clk camss_csi2rdi_clk = { |
| 3295 | .cbcr_reg = CAMSS_CSI2RDI_CBCR, |
| 3296 | .parent = &csi2_clk_src.c, |
| 3297 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3298 | .base = &virt_bases[MMSS_BASE], |
| 3299 | .c = { |
| 3300 | .dbg_name = "camss_csi2rdi_clk", |
| 3301 | .ops = &clk_ops_branch, |
| 3302 | CLK_INIT(camss_csi2rdi_clk.c), |
| 3303 | }, |
| 3304 | }; |
| 3305 | |
| 3306 | static struct branch_clk camss_csi3_ahb_clk = { |
| 3307 | .cbcr_reg = CAMSS_CSI3_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3308 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3309 | .base = &virt_bases[MMSS_BASE], |
| 3310 | .c = { |
| 3311 | .dbg_name = "camss_csi3_ahb_clk", |
| 3312 | .ops = &clk_ops_branch, |
| 3313 | CLK_INIT(camss_csi3_ahb_clk.c), |
| 3314 | }, |
| 3315 | }; |
| 3316 | |
| 3317 | static struct branch_clk camss_csi3_clk = { |
| 3318 | .cbcr_reg = CAMSS_CSI3_CBCR, |
| 3319 | .parent = &csi3_clk_src.c, |
| 3320 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3321 | .base = &virt_bases[MMSS_BASE], |
| 3322 | .c = { |
| 3323 | .dbg_name = "camss_csi3_clk", |
| 3324 | .ops = &clk_ops_branch, |
| 3325 | CLK_INIT(camss_csi3_clk.c), |
| 3326 | }, |
| 3327 | }; |
| 3328 | |
| 3329 | static struct branch_clk camss_csi3phy_clk = { |
| 3330 | .cbcr_reg = CAMSS_CSI3PHY_CBCR, |
| 3331 | .parent = &csi3_clk_src.c, |
| 3332 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3333 | .base = &virt_bases[MMSS_BASE], |
| 3334 | .c = { |
| 3335 | .dbg_name = "camss_csi3phy_clk", |
| 3336 | .ops = &clk_ops_branch, |
| 3337 | CLK_INIT(camss_csi3phy_clk.c), |
| 3338 | }, |
| 3339 | }; |
| 3340 | |
| 3341 | static struct branch_clk camss_csi3pix_clk = { |
| 3342 | .cbcr_reg = CAMSS_CSI3PIX_CBCR, |
| 3343 | .parent = &csi3_clk_src.c, |
| 3344 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3345 | .base = &virt_bases[MMSS_BASE], |
| 3346 | .c = { |
| 3347 | .dbg_name = "camss_csi3pix_clk", |
| 3348 | .ops = &clk_ops_branch, |
| 3349 | CLK_INIT(camss_csi3pix_clk.c), |
| 3350 | }, |
| 3351 | }; |
| 3352 | |
| 3353 | static struct branch_clk camss_csi3rdi_clk = { |
| 3354 | .cbcr_reg = CAMSS_CSI3RDI_CBCR, |
| 3355 | .parent = &csi3_clk_src.c, |
| 3356 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3357 | .base = &virt_bases[MMSS_BASE], |
| 3358 | .c = { |
| 3359 | .dbg_name = "camss_csi3rdi_clk", |
| 3360 | .ops = &clk_ops_branch, |
| 3361 | CLK_INIT(camss_csi3rdi_clk.c), |
| 3362 | }, |
| 3363 | }; |
| 3364 | |
| 3365 | static struct branch_clk camss_csi_vfe0_clk = { |
| 3366 | .cbcr_reg = CAMSS_CSI_VFE0_CBCR, |
| 3367 | .parent = &vfe0_clk_src.c, |
| 3368 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3369 | .base = &virt_bases[MMSS_BASE], |
| 3370 | .c = { |
| 3371 | .dbg_name = "camss_csi_vfe0_clk", |
| 3372 | .ops = &clk_ops_branch, |
| 3373 | CLK_INIT(camss_csi_vfe0_clk.c), |
| 3374 | }, |
| 3375 | }; |
| 3376 | |
| 3377 | static struct branch_clk camss_csi_vfe1_clk = { |
| 3378 | .cbcr_reg = CAMSS_CSI_VFE1_CBCR, |
| 3379 | .parent = &vfe1_clk_src.c, |
| 3380 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3381 | .base = &virt_bases[MMSS_BASE], |
| 3382 | .c = { |
| 3383 | .dbg_name = "camss_csi_vfe1_clk", |
| 3384 | .ops = &clk_ops_branch, |
| 3385 | CLK_INIT(camss_csi_vfe1_clk.c), |
| 3386 | }, |
| 3387 | }; |
| 3388 | |
| 3389 | static struct branch_clk camss_gp0_clk = { |
| 3390 | .cbcr_reg = CAMSS_GP0_CBCR, |
| 3391 | .parent = &mmss_gp0_clk_src.c, |
| 3392 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3393 | .base = &virt_bases[MMSS_BASE], |
| 3394 | .c = { |
| 3395 | .dbg_name = "camss_gp0_clk", |
| 3396 | .ops = &clk_ops_branch, |
| 3397 | CLK_INIT(camss_gp0_clk.c), |
| 3398 | }, |
| 3399 | }; |
| 3400 | |
| 3401 | static struct branch_clk camss_gp1_clk = { |
| 3402 | .cbcr_reg = CAMSS_GP1_CBCR, |
| 3403 | .parent = &mmss_gp1_clk_src.c, |
| 3404 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3405 | .base = &virt_bases[MMSS_BASE], |
| 3406 | .c = { |
| 3407 | .dbg_name = "camss_gp1_clk", |
| 3408 | .ops = &clk_ops_branch, |
| 3409 | CLK_INIT(camss_gp1_clk.c), |
| 3410 | }, |
| 3411 | }; |
| 3412 | |
| 3413 | static struct branch_clk camss_ispif_ahb_clk = { |
| 3414 | .cbcr_reg = CAMSS_ISPIF_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3415 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3416 | .base = &virt_bases[MMSS_BASE], |
| 3417 | .c = { |
| 3418 | .dbg_name = "camss_ispif_ahb_clk", |
| 3419 | .ops = &clk_ops_branch, |
| 3420 | CLK_INIT(camss_ispif_ahb_clk.c), |
| 3421 | }, |
| 3422 | }; |
| 3423 | |
| 3424 | static struct branch_clk camss_jpeg_jpeg0_clk = { |
| 3425 | .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR, |
| 3426 | .parent = &jpeg0_clk_src.c, |
| 3427 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3428 | .base = &virt_bases[MMSS_BASE], |
| 3429 | .c = { |
| 3430 | .dbg_name = "camss_jpeg_jpeg0_clk", |
| 3431 | .ops = &clk_ops_branch, |
| 3432 | CLK_INIT(camss_jpeg_jpeg0_clk.c), |
| 3433 | }, |
| 3434 | }; |
| 3435 | |
| 3436 | static struct branch_clk camss_jpeg_jpeg1_clk = { |
| 3437 | .cbcr_reg = CAMSS_JPEG_JPEG1_CBCR, |
| 3438 | .parent = &jpeg1_clk_src.c, |
| 3439 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3440 | .base = &virt_bases[MMSS_BASE], |
| 3441 | .c = { |
| 3442 | .dbg_name = "camss_jpeg_jpeg1_clk", |
| 3443 | .ops = &clk_ops_branch, |
| 3444 | CLK_INIT(camss_jpeg_jpeg1_clk.c), |
| 3445 | }, |
| 3446 | }; |
| 3447 | |
| 3448 | static struct branch_clk camss_jpeg_jpeg2_clk = { |
| 3449 | .cbcr_reg = CAMSS_JPEG_JPEG2_CBCR, |
| 3450 | .parent = &jpeg2_clk_src.c, |
| 3451 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3452 | .base = &virt_bases[MMSS_BASE], |
| 3453 | .c = { |
| 3454 | .dbg_name = "camss_jpeg_jpeg2_clk", |
| 3455 | .ops = &clk_ops_branch, |
| 3456 | CLK_INIT(camss_jpeg_jpeg2_clk.c), |
| 3457 | }, |
| 3458 | }; |
| 3459 | |
| 3460 | static struct branch_clk camss_jpeg_jpeg_ahb_clk = { |
| 3461 | .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3462 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3463 | .base = &virt_bases[MMSS_BASE], |
| 3464 | .c = { |
| 3465 | .dbg_name = "camss_jpeg_jpeg_ahb_clk", |
| 3466 | .ops = &clk_ops_branch, |
| 3467 | CLK_INIT(camss_jpeg_jpeg_ahb_clk.c), |
| 3468 | }, |
| 3469 | }; |
| 3470 | |
| 3471 | static struct branch_clk camss_jpeg_jpeg_axi_clk = { |
| 3472 | .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR, |
| 3473 | .parent = &axi_clk_src.c, |
| 3474 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3475 | .base = &virt_bases[MMSS_BASE], |
| 3476 | .c = { |
| 3477 | .dbg_name = "camss_jpeg_jpeg_axi_clk", |
| 3478 | .ops = &clk_ops_branch, |
| 3479 | CLK_INIT(camss_jpeg_jpeg_axi_clk.c), |
| 3480 | }, |
| 3481 | }; |
| 3482 | |
| 3483 | static struct branch_clk camss_jpeg_jpeg_ocmemnoc_clk = { |
| 3484 | .cbcr_reg = CAMSS_JPEG_JPEG_OCMEMNOC_CBCR, |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 3485 | .parent = &ocmemnoc_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3486 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3487 | .base = &virt_bases[MMSS_BASE], |
| 3488 | .c = { |
| 3489 | .dbg_name = "camss_jpeg_jpeg_ocmemnoc_clk", |
| 3490 | .ops = &clk_ops_branch, |
| 3491 | CLK_INIT(camss_jpeg_jpeg_ocmemnoc_clk.c), |
| 3492 | }, |
| 3493 | }; |
| 3494 | |
| 3495 | static struct branch_clk camss_mclk0_clk = { |
| 3496 | .cbcr_reg = CAMSS_MCLK0_CBCR, |
| 3497 | .parent = &mclk0_clk_src.c, |
| 3498 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3499 | .base = &virt_bases[MMSS_BASE], |
| 3500 | .c = { |
| 3501 | .dbg_name = "camss_mclk0_clk", |
| 3502 | .ops = &clk_ops_branch, |
| 3503 | CLK_INIT(camss_mclk0_clk.c), |
| 3504 | }, |
| 3505 | }; |
| 3506 | |
| 3507 | static struct branch_clk camss_mclk1_clk = { |
| 3508 | .cbcr_reg = CAMSS_MCLK1_CBCR, |
| 3509 | .parent = &mclk1_clk_src.c, |
| 3510 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3511 | .base = &virt_bases[MMSS_BASE], |
| 3512 | .c = { |
| 3513 | .dbg_name = "camss_mclk1_clk", |
| 3514 | .ops = &clk_ops_branch, |
| 3515 | CLK_INIT(camss_mclk1_clk.c), |
| 3516 | }, |
| 3517 | }; |
| 3518 | |
| 3519 | static struct branch_clk camss_mclk2_clk = { |
| 3520 | .cbcr_reg = CAMSS_MCLK2_CBCR, |
| 3521 | .parent = &mclk2_clk_src.c, |
| 3522 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3523 | .base = &virt_bases[MMSS_BASE], |
| 3524 | .c = { |
| 3525 | .dbg_name = "camss_mclk2_clk", |
| 3526 | .ops = &clk_ops_branch, |
| 3527 | CLK_INIT(camss_mclk2_clk.c), |
| 3528 | }, |
| 3529 | }; |
| 3530 | |
| 3531 | static struct branch_clk camss_mclk3_clk = { |
| 3532 | .cbcr_reg = CAMSS_MCLK3_CBCR, |
| 3533 | .parent = &mclk3_clk_src.c, |
| 3534 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3535 | .base = &virt_bases[MMSS_BASE], |
| 3536 | .c = { |
| 3537 | .dbg_name = "camss_mclk3_clk", |
| 3538 | .ops = &clk_ops_branch, |
| 3539 | CLK_INIT(camss_mclk3_clk.c), |
| 3540 | }, |
| 3541 | }; |
| 3542 | |
| 3543 | static struct branch_clk camss_micro_ahb_clk = { |
| 3544 | .cbcr_reg = CAMSS_MICRO_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3545 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3546 | .base = &virt_bases[MMSS_BASE], |
| 3547 | .c = { |
| 3548 | .dbg_name = "camss_micro_ahb_clk", |
| 3549 | .ops = &clk_ops_branch, |
| 3550 | CLK_INIT(camss_micro_ahb_clk.c), |
| 3551 | }, |
| 3552 | }; |
| 3553 | |
| 3554 | static struct branch_clk camss_phy0_csi0phytimer_clk = { |
| 3555 | .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR, |
| 3556 | .parent = &csi0phytimer_clk_src.c, |
| 3557 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3558 | .base = &virt_bases[MMSS_BASE], |
| 3559 | .c = { |
| 3560 | .dbg_name = "camss_phy0_csi0phytimer_clk", |
| 3561 | .ops = &clk_ops_branch, |
| 3562 | CLK_INIT(camss_phy0_csi0phytimer_clk.c), |
| 3563 | }, |
| 3564 | }; |
| 3565 | |
| 3566 | static struct branch_clk camss_phy1_csi1phytimer_clk = { |
| 3567 | .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR, |
| 3568 | .parent = &csi1phytimer_clk_src.c, |
| 3569 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3570 | .base = &virt_bases[MMSS_BASE], |
| 3571 | .c = { |
| 3572 | .dbg_name = "camss_phy1_csi1phytimer_clk", |
| 3573 | .ops = &clk_ops_branch, |
| 3574 | CLK_INIT(camss_phy1_csi1phytimer_clk.c), |
| 3575 | }, |
| 3576 | }; |
| 3577 | |
| 3578 | static struct branch_clk camss_phy2_csi2phytimer_clk = { |
| 3579 | .cbcr_reg = CAMSS_PHY2_CSI2PHYTIMER_CBCR, |
| 3580 | .parent = &csi2phytimer_clk_src.c, |
| 3581 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3582 | .base = &virt_bases[MMSS_BASE], |
| 3583 | .c = { |
| 3584 | .dbg_name = "camss_phy2_csi2phytimer_clk", |
| 3585 | .ops = &clk_ops_branch, |
| 3586 | CLK_INIT(camss_phy2_csi2phytimer_clk.c), |
| 3587 | }, |
| 3588 | }; |
| 3589 | |
| 3590 | static struct branch_clk camss_top_ahb_clk = { |
| 3591 | .cbcr_reg = CAMSS_TOP_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3592 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3593 | .base = &virt_bases[MMSS_BASE], |
| 3594 | .c = { |
| 3595 | .dbg_name = "camss_top_ahb_clk", |
| 3596 | .ops = &clk_ops_branch, |
| 3597 | CLK_INIT(camss_top_ahb_clk.c), |
| 3598 | }, |
| 3599 | }; |
| 3600 | |
| 3601 | static struct branch_clk camss_vfe_cpp_ahb_clk = { |
| 3602 | .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3603 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3604 | .base = &virt_bases[MMSS_BASE], |
| 3605 | .c = { |
| 3606 | .dbg_name = "camss_vfe_cpp_ahb_clk", |
| 3607 | .ops = &clk_ops_branch, |
| 3608 | CLK_INIT(camss_vfe_cpp_ahb_clk.c), |
| 3609 | }, |
| 3610 | }; |
| 3611 | |
| 3612 | static struct branch_clk camss_vfe_cpp_clk = { |
| 3613 | .cbcr_reg = CAMSS_VFE_CPP_CBCR, |
| 3614 | .parent = &cpp_clk_src.c, |
| 3615 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3616 | .base = &virt_bases[MMSS_BASE], |
| 3617 | .c = { |
| 3618 | .dbg_name = "camss_vfe_cpp_clk", |
| 3619 | .ops = &clk_ops_branch, |
| 3620 | CLK_INIT(camss_vfe_cpp_clk.c), |
| 3621 | }, |
| 3622 | }; |
| 3623 | |
| 3624 | static struct branch_clk camss_vfe_vfe0_clk = { |
| 3625 | .cbcr_reg = CAMSS_VFE_VFE0_CBCR, |
| 3626 | .parent = &vfe0_clk_src.c, |
| 3627 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3628 | .base = &virt_bases[MMSS_BASE], |
| 3629 | .c = { |
| 3630 | .dbg_name = "camss_vfe_vfe0_clk", |
| 3631 | .ops = &clk_ops_branch, |
| 3632 | CLK_INIT(camss_vfe_vfe0_clk.c), |
| 3633 | }, |
| 3634 | }; |
| 3635 | |
| 3636 | static struct branch_clk camss_vfe_vfe1_clk = { |
| 3637 | .cbcr_reg = CAMSS_VFE_VFE1_CBCR, |
| 3638 | .parent = &vfe1_clk_src.c, |
| 3639 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3640 | .base = &virt_bases[MMSS_BASE], |
| 3641 | .c = { |
| 3642 | .dbg_name = "camss_vfe_vfe1_clk", |
| 3643 | .ops = &clk_ops_branch, |
| 3644 | CLK_INIT(camss_vfe_vfe1_clk.c), |
| 3645 | }, |
| 3646 | }; |
| 3647 | |
| 3648 | static struct branch_clk camss_vfe_vfe_ahb_clk = { |
| 3649 | .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3650 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3651 | .base = &virt_bases[MMSS_BASE], |
| 3652 | .c = { |
| 3653 | .dbg_name = "camss_vfe_vfe_ahb_clk", |
| 3654 | .ops = &clk_ops_branch, |
| 3655 | CLK_INIT(camss_vfe_vfe_ahb_clk.c), |
| 3656 | }, |
| 3657 | }; |
| 3658 | |
| 3659 | static struct branch_clk camss_vfe_vfe_axi_clk = { |
| 3660 | .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR, |
| 3661 | .parent = &axi_clk_src.c, |
| 3662 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3663 | .base = &virt_bases[MMSS_BASE], |
| 3664 | .c = { |
| 3665 | .dbg_name = "camss_vfe_vfe_axi_clk", |
| 3666 | .ops = &clk_ops_branch, |
| 3667 | CLK_INIT(camss_vfe_vfe_axi_clk.c), |
| 3668 | }, |
| 3669 | }; |
| 3670 | |
| 3671 | static struct branch_clk camss_vfe_vfe_ocmemnoc_clk = { |
| 3672 | .cbcr_reg = CAMSS_VFE_VFE_OCMEMNOC_CBCR, |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 3673 | .parent = &ocmemnoc_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3674 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3675 | .base = &virt_bases[MMSS_BASE], |
| 3676 | .c = { |
| 3677 | .dbg_name = "camss_vfe_vfe_ocmemnoc_clk", |
| 3678 | .ops = &clk_ops_branch, |
| 3679 | CLK_INIT(camss_vfe_vfe_ocmemnoc_clk.c), |
| 3680 | }, |
| 3681 | }; |
| 3682 | |
| 3683 | static struct branch_clk mdss_ahb_clk = { |
| 3684 | .cbcr_reg = MDSS_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3685 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3686 | .base = &virt_bases[MMSS_BASE], |
| 3687 | .c = { |
| 3688 | .dbg_name = "mdss_ahb_clk", |
| 3689 | .ops = &clk_ops_branch, |
| 3690 | CLK_INIT(mdss_ahb_clk.c), |
| 3691 | }, |
| 3692 | }; |
| 3693 | |
| 3694 | static struct branch_clk mdss_axi_clk = { |
| 3695 | .cbcr_reg = MDSS_AXI_CBCR, |
| 3696 | .parent = &axi_clk_src.c, |
| 3697 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3698 | .base = &virt_bases[MMSS_BASE], |
| 3699 | .c = { |
| 3700 | .dbg_name = "mdss_axi_clk", |
| 3701 | .ops = &clk_ops_branch, |
| 3702 | CLK_INIT(mdss_axi_clk.c), |
| 3703 | }, |
| 3704 | }; |
| 3705 | |
| 3706 | static struct branch_clk mdss_byte0_clk = { |
| 3707 | .cbcr_reg = MDSS_BYTE0_CBCR, |
| 3708 | .parent = &byte0_clk_src.c, |
| 3709 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3710 | .base = &virt_bases[MMSS_BASE], |
| 3711 | .c = { |
| 3712 | .dbg_name = "mdss_byte0_clk", |
| 3713 | .ops = &clk_ops_branch, |
| 3714 | CLK_INIT(mdss_byte0_clk.c), |
| 3715 | }, |
| 3716 | }; |
| 3717 | |
| 3718 | static struct branch_clk mdss_byte1_clk = { |
| 3719 | .cbcr_reg = MDSS_BYTE1_CBCR, |
| 3720 | .parent = &byte1_clk_src.c, |
| 3721 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3722 | .base = &virt_bases[MMSS_BASE], |
| 3723 | .c = { |
| 3724 | .dbg_name = "mdss_byte1_clk", |
| 3725 | .ops = &clk_ops_branch, |
| 3726 | CLK_INIT(mdss_byte1_clk.c), |
| 3727 | }, |
| 3728 | }; |
| 3729 | |
| 3730 | static struct branch_clk mdss_edpaux_clk = { |
| 3731 | .cbcr_reg = MDSS_EDPAUX_CBCR, |
| 3732 | .parent = &edpaux_clk_src.c, |
| 3733 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3734 | .base = &virt_bases[MMSS_BASE], |
| 3735 | .c = { |
| 3736 | .dbg_name = "mdss_edpaux_clk", |
| 3737 | .ops = &clk_ops_branch, |
| 3738 | CLK_INIT(mdss_edpaux_clk.c), |
| 3739 | }, |
| 3740 | }; |
| 3741 | |
| 3742 | static struct branch_clk mdss_edplink_clk = { |
| 3743 | .cbcr_reg = MDSS_EDPLINK_CBCR, |
| 3744 | .parent = &edplink_clk_src.c, |
| 3745 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3746 | .base = &virt_bases[MMSS_BASE], |
| 3747 | .c = { |
| 3748 | .dbg_name = "mdss_edplink_clk", |
| 3749 | .ops = &clk_ops_branch, |
| 3750 | CLK_INIT(mdss_edplink_clk.c), |
| 3751 | }, |
| 3752 | }; |
| 3753 | |
| 3754 | static struct branch_clk mdss_edppixel_clk = { |
| 3755 | .cbcr_reg = MDSS_EDPPIXEL_CBCR, |
| 3756 | .parent = &edppixel_clk_src.c, |
| 3757 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3758 | .base = &virt_bases[MMSS_BASE], |
| 3759 | .c = { |
| 3760 | .dbg_name = "mdss_edppixel_clk", |
| 3761 | .ops = &clk_ops_branch, |
| 3762 | CLK_INIT(mdss_edppixel_clk.c), |
| 3763 | }, |
| 3764 | }; |
| 3765 | |
| 3766 | static struct branch_clk mdss_esc0_clk = { |
| 3767 | .cbcr_reg = MDSS_ESC0_CBCR, |
| 3768 | .parent = &esc0_clk_src.c, |
| 3769 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3770 | .base = &virt_bases[MMSS_BASE], |
| 3771 | .c = { |
| 3772 | .dbg_name = "mdss_esc0_clk", |
| 3773 | .ops = &clk_ops_branch, |
| 3774 | CLK_INIT(mdss_esc0_clk.c), |
| 3775 | }, |
| 3776 | }; |
| 3777 | |
| 3778 | static struct branch_clk mdss_esc1_clk = { |
| 3779 | .cbcr_reg = MDSS_ESC1_CBCR, |
| 3780 | .parent = &esc1_clk_src.c, |
| 3781 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3782 | .base = &virt_bases[MMSS_BASE], |
| 3783 | .c = { |
| 3784 | .dbg_name = "mdss_esc1_clk", |
| 3785 | .ops = &clk_ops_branch, |
| 3786 | CLK_INIT(mdss_esc1_clk.c), |
| 3787 | }, |
| 3788 | }; |
| 3789 | |
| 3790 | static struct branch_clk mdss_extpclk_clk = { |
| 3791 | .cbcr_reg = MDSS_EXTPCLK_CBCR, |
| 3792 | .parent = &extpclk_clk_src.c, |
| 3793 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3794 | .base = &virt_bases[MMSS_BASE], |
| 3795 | .c = { |
| 3796 | .dbg_name = "mdss_extpclk_clk", |
| 3797 | .ops = &clk_ops_branch, |
| 3798 | CLK_INIT(mdss_extpclk_clk.c), |
| 3799 | }, |
| 3800 | }; |
| 3801 | |
| 3802 | static struct branch_clk mdss_hdmi_ahb_clk = { |
| 3803 | .cbcr_reg = MDSS_HDMI_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3804 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3805 | .base = &virt_bases[MMSS_BASE], |
| 3806 | .c = { |
| 3807 | .dbg_name = "mdss_hdmi_ahb_clk", |
| 3808 | .ops = &clk_ops_branch, |
| 3809 | CLK_INIT(mdss_hdmi_ahb_clk.c), |
| 3810 | }, |
| 3811 | }; |
| 3812 | |
| 3813 | static struct branch_clk mdss_hdmi_clk = { |
| 3814 | .cbcr_reg = MDSS_HDMI_CBCR, |
| 3815 | .parent = &hdmi_clk_src.c, |
| 3816 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3817 | .base = &virt_bases[MMSS_BASE], |
| 3818 | .c = { |
| 3819 | .dbg_name = "mdss_hdmi_clk", |
| 3820 | .ops = &clk_ops_branch, |
| 3821 | CLK_INIT(mdss_hdmi_clk.c), |
| 3822 | }, |
| 3823 | }; |
| 3824 | |
| 3825 | static struct branch_clk mdss_mdp_clk = { |
| 3826 | .cbcr_reg = MDSS_MDP_CBCR, |
| 3827 | .parent = &mdp_clk_src.c, |
| 3828 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3829 | .base = &virt_bases[MMSS_BASE], |
| 3830 | .c = { |
| 3831 | .dbg_name = "mdss_mdp_clk", |
| 3832 | .ops = &clk_ops_branch, |
| 3833 | CLK_INIT(mdss_mdp_clk.c), |
| 3834 | }, |
| 3835 | }; |
| 3836 | |
| 3837 | static struct branch_clk mdss_mdp_lut_clk = { |
| 3838 | .cbcr_reg = MDSS_MDP_LUT_CBCR, |
| 3839 | .parent = &mdp_clk_src.c, |
| 3840 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3841 | .base = &virt_bases[MMSS_BASE], |
| 3842 | .c = { |
| 3843 | .dbg_name = "mdss_mdp_lut_clk", |
| 3844 | .ops = &clk_ops_branch, |
| 3845 | CLK_INIT(mdss_mdp_lut_clk.c), |
| 3846 | }, |
| 3847 | }; |
| 3848 | |
| 3849 | static struct branch_clk mdss_pclk0_clk = { |
| 3850 | .cbcr_reg = MDSS_PCLK0_CBCR, |
| 3851 | .parent = &pclk0_clk_src.c, |
| 3852 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3853 | .base = &virt_bases[MMSS_BASE], |
| 3854 | .c = { |
| 3855 | .dbg_name = "mdss_pclk0_clk", |
| 3856 | .ops = &clk_ops_branch, |
| 3857 | CLK_INIT(mdss_pclk0_clk.c), |
| 3858 | }, |
| 3859 | }; |
| 3860 | |
| 3861 | static struct branch_clk mdss_pclk1_clk = { |
| 3862 | .cbcr_reg = MDSS_PCLK1_CBCR, |
| 3863 | .parent = &pclk1_clk_src.c, |
| 3864 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3865 | .base = &virt_bases[MMSS_BASE], |
| 3866 | .c = { |
| 3867 | .dbg_name = "mdss_pclk1_clk", |
| 3868 | .ops = &clk_ops_branch, |
| 3869 | CLK_INIT(mdss_pclk1_clk.c), |
| 3870 | }, |
| 3871 | }; |
| 3872 | |
| 3873 | static struct branch_clk mdss_vsync_clk = { |
| 3874 | .cbcr_reg = MDSS_VSYNC_CBCR, |
| 3875 | .parent = &vsync_clk_src.c, |
| 3876 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3877 | .base = &virt_bases[MMSS_BASE], |
| 3878 | .c = { |
| 3879 | .dbg_name = "mdss_vsync_clk", |
| 3880 | .ops = &clk_ops_branch, |
| 3881 | CLK_INIT(mdss_vsync_clk.c), |
| 3882 | }, |
| 3883 | }; |
| 3884 | |
| 3885 | static struct branch_clk mmss_misc_ahb_clk = { |
| 3886 | .cbcr_reg = MMSS_MISC_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3887 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3888 | .base = &virt_bases[MMSS_BASE], |
| 3889 | .c = { |
| 3890 | .dbg_name = "mmss_misc_ahb_clk", |
| 3891 | .ops = &clk_ops_branch, |
| 3892 | CLK_INIT(mmss_misc_ahb_clk.c), |
| 3893 | }, |
| 3894 | }; |
| 3895 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3896 | static struct branch_clk mmss_mmssnoc_bto_ahb_clk = { |
| 3897 | .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3898 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3899 | .base = &virt_bases[MMSS_BASE], |
| 3900 | .c = { |
| 3901 | .dbg_name = "mmss_mmssnoc_bto_ahb_clk", |
| 3902 | .ops = &clk_ops_branch, |
| 3903 | CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c), |
| 3904 | }, |
| 3905 | }; |
| 3906 | |
| 3907 | static struct branch_clk mmss_mmssnoc_axi_clk = { |
| 3908 | .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR, |
| 3909 | .parent = &axi_clk_src.c, |
Vikram Mulukutla | c15dac0 | 2012-08-09 13:31:08 -0700 | [diff] [blame] | 3910 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3911 | .base = &virt_bases[MMSS_BASE], |
| 3912 | .c = { |
| 3913 | .dbg_name = "mmss_mmssnoc_axi_clk", |
| 3914 | .ops = &clk_ops_branch, |
| 3915 | CLK_INIT(mmss_mmssnoc_axi_clk.c), |
| 3916 | }, |
| 3917 | }; |
| 3918 | |
| 3919 | static struct branch_clk mmss_s0_axi_clk = { |
| 3920 | .cbcr_reg = MMSS_S0_AXI_CBCR, |
| 3921 | .parent = &axi_clk_src.c, |
Vikram Mulukutla | c15dac0 | 2012-08-09 13:31:08 -0700 | [diff] [blame] | 3922 | /* The bus driver needs set_rate to go through to the parent */ |
| 3923 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3924 | .base = &virt_bases[MMSS_BASE], |
| 3925 | .c = { |
| 3926 | .dbg_name = "mmss_s0_axi_clk", |
| 3927 | .ops = &clk_ops_branch, |
| 3928 | CLK_INIT(mmss_s0_axi_clk.c), |
Vikram Mulukutla | c15dac0 | 2012-08-09 13:31:08 -0700 | [diff] [blame] | 3929 | .depends = &mmss_mmssnoc_axi_clk.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3930 | }, |
| 3931 | }; |
| 3932 | |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 3933 | struct branch_clk ocmemnoc_clk = { |
| 3934 | .cbcr_reg = OCMEMNOC_CBCR, |
| 3935 | .parent = &ocmemnoc_clk_src.c, |
| 3936 | .has_sibling = 0, |
| 3937 | .bcr_reg = 0x50b0, |
| 3938 | .base = &virt_bases[MMSS_BASE], |
| 3939 | .c = { |
| 3940 | .dbg_name = "ocmemnoc_clk", |
| 3941 | .ops = &clk_ops_branch, |
| 3942 | CLK_INIT(ocmemnoc_clk.c), |
| 3943 | }, |
| 3944 | }; |
| 3945 | |
Vikram Mulukutla | 274b2d9 | 2012-07-13 15:53:04 -0700 | [diff] [blame] | 3946 | struct branch_clk ocmemcx_ocmemnoc_clk = { |
| 3947 | .cbcr_reg = OCMEMCX_OCMEMNOC_CBCR, |
| 3948 | .parent = &ocmemnoc_clk_src.c, |
| 3949 | .has_sibling = 1, |
| 3950 | .base = &virt_bases[MMSS_BASE], |
| 3951 | .c = { |
| 3952 | .dbg_name = "ocmemcx_ocmemnoc_clk", |
| 3953 | .ops = &clk_ops_branch, |
| 3954 | CLK_INIT(ocmemcx_ocmemnoc_clk.c), |
| 3955 | }, |
| 3956 | }; |
| 3957 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3958 | static struct branch_clk venus0_ahb_clk = { |
| 3959 | .cbcr_reg = VENUS0_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3960 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3961 | .base = &virt_bases[MMSS_BASE], |
| 3962 | .c = { |
| 3963 | .dbg_name = "venus0_ahb_clk", |
| 3964 | .ops = &clk_ops_branch, |
| 3965 | CLK_INIT(venus0_ahb_clk.c), |
| 3966 | }, |
| 3967 | }; |
| 3968 | |
| 3969 | static struct branch_clk venus0_axi_clk = { |
| 3970 | .cbcr_reg = VENUS0_AXI_CBCR, |
| 3971 | .parent = &axi_clk_src.c, |
| 3972 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3973 | .base = &virt_bases[MMSS_BASE], |
| 3974 | .c = { |
| 3975 | .dbg_name = "venus0_axi_clk", |
| 3976 | .ops = &clk_ops_branch, |
| 3977 | CLK_INIT(venus0_axi_clk.c), |
| 3978 | }, |
| 3979 | }; |
| 3980 | |
| 3981 | static struct branch_clk venus0_ocmemnoc_clk = { |
| 3982 | .cbcr_reg = VENUS0_OCMEMNOC_CBCR, |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 3983 | .parent = &ocmemnoc_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3984 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3985 | .base = &virt_bases[MMSS_BASE], |
| 3986 | .c = { |
| 3987 | .dbg_name = "venus0_ocmemnoc_clk", |
| 3988 | .ops = &clk_ops_branch, |
| 3989 | CLK_INIT(venus0_ocmemnoc_clk.c), |
| 3990 | }, |
| 3991 | }; |
| 3992 | |
| 3993 | static struct branch_clk venus0_vcodec0_clk = { |
| 3994 | .cbcr_reg = VENUS0_VCODEC0_CBCR, |
| 3995 | .parent = &vcodec0_clk_src.c, |
| 3996 | .has_sibling = 0, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 3997 | .base = &virt_bases[MMSS_BASE], |
| 3998 | .c = { |
| 3999 | .dbg_name = "venus0_vcodec0_clk", |
| 4000 | .ops = &clk_ops_branch, |
| 4001 | CLK_INIT(venus0_vcodec0_clk.c), |
| 4002 | }, |
| 4003 | }; |
| 4004 | |
Vikram Mulukutla | e3b0306 | 2012-05-16 12:07:08 -0700 | [diff] [blame] | 4005 | static struct branch_clk oxilicx_axi_clk = { |
| 4006 | .cbcr_reg = OXILICX_AXI_CBCR, |
| 4007 | .parent = &axi_clk_src.c, |
| 4008 | .has_sibling = 1, |
| 4009 | .base = &virt_bases[MMSS_BASE], |
| 4010 | .c = { |
| 4011 | .dbg_name = "oxilicx_axi_clk", |
| 4012 | .ops = &clk_ops_branch, |
| 4013 | CLK_INIT(oxilicx_axi_clk.c), |
| 4014 | }, |
| 4015 | }; |
| 4016 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4017 | static struct branch_clk oxili_gfx3d_clk = { |
| 4018 | .cbcr_reg = OXILI_GFX3D_CBCR, |
Vikram Mulukutla | 1e6127d | 2012-08-21 21:05:24 -0700 | [diff] [blame] | 4019 | .parent = &oxili_gfx3d_clk_src.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4020 | .base = &virt_bases[MMSS_BASE], |
| 4021 | .c = { |
| 4022 | .dbg_name = "oxili_gfx3d_clk", |
| 4023 | .ops = &clk_ops_branch, |
| 4024 | CLK_INIT(oxili_gfx3d_clk.c), |
Vikram Mulukutla | e3b0306 | 2012-05-16 12:07:08 -0700 | [diff] [blame] | 4025 | .depends = &oxilicx_axi_clk.c, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4026 | }, |
| 4027 | }; |
| 4028 | |
| 4029 | static struct branch_clk oxilicx_ahb_clk = { |
| 4030 | .cbcr_reg = OXILICX_AHB_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4031 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4032 | .base = &virt_bases[MMSS_BASE], |
| 4033 | .c = { |
| 4034 | .dbg_name = "oxilicx_ahb_clk", |
| 4035 | .ops = &clk_ops_branch, |
| 4036 | CLK_INIT(oxilicx_ahb_clk.c), |
| 4037 | }, |
| 4038 | }; |
| 4039 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4040 | static struct clk_freq_tbl ftbl_audio_core_slimbus_core_clock[] = { |
Vikram Mulukutla | 94d531c | 2012-08-11 18:50:27 -0700 | [diff] [blame] | 4041 | F_LPASS(24576000, lpapll0, 4, 1, 5), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4042 | F_END |
| 4043 | }; |
| 4044 | |
| 4045 | static struct rcg_clk audio_core_slimbus_core_clk_src = { |
| 4046 | .cmd_rcgr_reg = SLIMBUS_CMD_RCGR, |
| 4047 | .set_rate = set_rate_mnd, |
| 4048 | .freq_tbl = ftbl_audio_core_slimbus_core_clock, |
| 4049 | .current_freq = &rcg_dummy_freq, |
| 4050 | .base = &virt_bases[LPASS_BASE], |
| 4051 | .c = { |
| 4052 | .dbg_name = "audio_core_slimbus_core_clk_src", |
| 4053 | .ops = &clk_ops_rcg_mnd, |
| 4054 | VDD_DIG_FMAX_MAP2(LOW, 70000000, NOMINAL, 140000000), |
| 4055 | CLK_INIT(audio_core_slimbus_core_clk_src.c), |
| 4056 | }, |
| 4057 | }; |
| 4058 | |
| 4059 | static struct branch_clk audio_core_slimbus_core_clk = { |
| 4060 | .cbcr_reg = AUDIO_CORE_SLIMBUS_CORE_CBCR, |
| 4061 | .parent = &audio_core_slimbus_core_clk_src.c, |
| 4062 | .base = &virt_bases[LPASS_BASE], |
| 4063 | .c = { |
| 4064 | .dbg_name = "audio_core_slimbus_core_clk", |
| 4065 | .ops = &clk_ops_branch, |
| 4066 | CLK_INIT(audio_core_slimbus_core_clk.c), |
| 4067 | }, |
| 4068 | }; |
| 4069 | |
| 4070 | static struct branch_clk audio_core_slimbus_lfabif_clk = { |
| 4071 | .cbcr_reg = AUDIO_CORE_SLIMBUS_LFABIF_CBCR, |
| 4072 | .has_sibling = 1, |
| 4073 | .base = &virt_bases[LPASS_BASE], |
| 4074 | .c = { |
| 4075 | .dbg_name = "audio_core_slimbus_lfabif_clk", |
| 4076 | .ops = &clk_ops_branch, |
| 4077 | CLK_INIT(audio_core_slimbus_lfabif_clk.c), |
| 4078 | }, |
| 4079 | }; |
| 4080 | |
| 4081 | static struct clk_freq_tbl ftbl_audio_core_lpaif_clock[] = { |
| 4082 | F_LPASS( 512000, lpapll0, 16, 1, 60), |
| 4083 | F_LPASS( 768000, lpapll0, 16, 1, 40), |
| 4084 | F_LPASS( 1024000, lpapll0, 16, 1, 30), |
Vikram Mulukutla | 27da8de | 2012-08-09 19:28:51 -0700 | [diff] [blame] | 4085 | F_LPASS( 1536000, lpapll0, 16, 1, 20), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4086 | F_LPASS( 2048000, lpapll0, 16, 1, 15), |
| 4087 | F_LPASS( 3072000, lpapll0, 16, 1, 10), |
| 4088 | F_LPASS( 4096000, lpapll0, 15, 1, 8), |
| 4089 | F_LPASS( 6144000, lpapll0, 10, 1, 8), |
| 4090 | F_LPASS( 8192000, lpapll0, 15, 1, 4), |
| 4091 | F_LPASS(12288000, lpapll0, 10, 1, 4), |
| 4092 | F_END |
| 4093 | }; |
| 4094 | |
| 4095 | static struct rcg_clk audio_core_lpaif_codec_spkr_clk_src = { |
| 4096 | .cmd_rcgr_reg = LPAIF_SPKR_CMD_RCGR, |
| 4097 | .set_rate = set_rate_mnd, |
| 4098 | .freq_tbl = ftbl_audio_core_lpaif_clock, |
| 4099 | .current_freq = &rcg_dummy_freq, |
| 4100 | .base = &virt_bases[LPASS_BASE], |
| 4101 | .c = { |
| 4102 | .dbg_name = "audio_core_lpaif_codec_spkr_clk_src", |
| 4103 | .ops = &clk_ops_rcg_mnd, |
| 4104 | VDD_DIG_FMAX_MAP2(LOW, 12000000, NOMINAL, 25000000), |
| 4105 | CLK_INIT(audio_core_lpaif_codec_spkr_clk_src.c), |
| 4106 | }, |
| 4107 | }; |
| 4108 | |
| 4109 | static struct rcg_clk audio_core_lpaif_pri_clk_src = { |
| 4110 | .cmd_rcgr_reg = LPAIF_PRI_CMD_RCGR, |
| 4111 | .set_rate = set_rate_mnd, |
| 4112 | .freq_tbl = ftbl_audio_core_lpaif_clock, |
| 4113 | .current_freq = &rcg_dummy_freq, |
| 4114 | .base = &virt_bases[LPASS_BASE], |
| 4115 | .c = { |
| 4116 | .dbg_name = "audio_core_lpaif_pri_clk_src", |
| 4117 | .ops = &clk_ops_rcg_mnd, |
| 4118 | VDD_DIG_FMAX_MAP2(LOW, 12000000, NOMINAL, 25000000), |
| 4119 | CLK_INIT(audio_core_lpaif_pri_clk_src.c), |
| 4120 | }, |
| 4121 | }; |
| 4122 | |
| 4123 | static struct rcg_clk audio_core_lpaif_sec_clk_src = { |
| 4124 | .cmd_rcgr_reg = LPAIF_SEC_CMD_RCGR, |
| 4125 | .set_rate = set_rate_mnd, |
| 4126 | .freq_tbl = ftbl_audio_core_lpaif_clock, |
| 4127 | .current_freq = &rcg_dummy_freq, |
| 4128 | .base = &virt_bases[LPASS_BASE], |
| 4129 | .c = { |
| 4130 | .dbg_name = "audio_core_lpaif_sec_clk_src", |
| 4131 | .ops = &clk_ops_rcg_mnd, |
| 4132 | VDD_DIG_FMAX_MAP2(LOW, 12000000, NOMINAL, 25000000), |
| 4133 | CLK_INIT(audio_core_lpaif_sec_clk_src.c), |
| 4134 | }, |
| 4135 | }; |
| 4136 | |
| 4137 | static struct rcg_clk audio_core_lpaif_ter_clk_src = { |
| 4138 | .cmd_rcgr_reg = LPAIF_TER_CMD_RCGR, |
| 4139 | .set_rate = set_rate_mnd, |
| 4140 | .freq_tbl = ftbl_audio_core_lpaif_clock, |
| 4141 | .current_freq = &rcg_dummy_freq, |
| 4142 | .base = &virt_bases[LPASS_BASE], |
| 4143 | .c = { |
| 4144 | .dbg_name = "audio_core_lpaif_ter_clk_src", |
| 4145 | .ops = &clk_ops_rcg_mnd, |
| 4146 | VDD_DIG_FMAX_MAP2(LOW, 12000000, NOMINAL, 25000000), |
| 4147 | CLK_INIT(audio_core_lpaif_ter_clk_src.c), |
| 4148 | }, |
| 4149 | }; |
| 4150 | |
| 4151 | static struct rcg_clk audio_core_lpaif_quad_clk_src = { |
| 4152 | .cmd_rcgr_reg = LPAIF_QUAD_CMD_RCGR, |
| 4153 | .set_rate = set_rate_mnd, |
| 4154 | .freq_tbl = ftbl_audio_core_lpaif_clock, |
| 4155 | .current_freq = &rcg_dummy_freq, |
| 4156 | .base = &virt_bases[LPASS_BASE], |
| 4157 | .c = { |
| 4158 | .dbg_name = "audio_core_lpaif_quad_clk_src", |
| 4159 | .ops = &clk_ops_rcg_mnd, |
| 4160 | VDD_DIG_FMAX_MAP2(LOW, 12000000, NOMINAL, 25000000), |
| 4161 | CLK_INIT(audio_core_lpaif_quad_clk_src.c), |
| 4162 | }, |
| 4163 | }; |
| 4164 | |
| 4165 | static struct rcg_clk audio_core_lpaif_pcm0_clk_src = { |
| 4166 | .cmd_rcgr_reg = LPAIF_PCM0_CMD_RCGR, |
| 4167 | .set_rate = set_rate_mnd, |
| 4168 | .freq_tbl = ftbl_audio_core_lpaif_clock, |
| 4169 | .current_freq = &rcg_dummy_freq, |
| 4170 | .base = &virt_bases[LPASS_BASE], |
| 4171 | .c = { |
| 4172 | .dbg_name = "audio_core_lpaif_pcm0_clk_src", |
| 4173 | .ops = &clk_ops_rcg_mnd, |
| 4174 | VDD_DIG_FMAX_MAP2(LOW, 12000000, NOMINAL, 25000000), |
| 4175 | CLK_INIT(audio_core_lpaif_pcm0_clk_src.c), |
| 4176 | }, |
| 4177 | }; |
| 4178 | |
| 4179 | static struct rcg_clk audio_core_lpaif_pcm1_clk_src = { |
| 4180 | .cmd_rcgr_reg = LPAIF_PCM1_CMD_RCGR, |
| 4181 | .set_rate = set_rate_mnd, |
| 4182 | .freq_tbl = ftbl_audio_core_lpaif_clock, |
| 4183 | .current_freq = &rcg_dummy_freq, |
| 4184 | .base = &virt_bases[LPASS_BASE], |
| 4185 | .c = { |
| 4186 | .dbg_name = "audio_core_lpaif_pcm1_clk_src", |
| 4187 | .ops = &clk_ops_rcg_mnd, |
| 4188 | VDD_DIG_FMAX_MAP2(LOW, 12000000, NOMINAL, 25000000), |
| 4189 | CLK_INIT(audio_core_lpaif_pcm1_clk_src.c), |
| 4190 | }, |
| 4191 | }; |
| 4192 | |
Vikram Mulukutla | 1d25218 | 2012-07-13 10:51:44 -0700 | [diff] [blame] | 4193 | struct rcg_clk audio_core_lpaif_pcmoe_clk_src = { |
| 4194 | .cmd_rcgr_reg = LPAIF_PCMOE_CMD_RCGR, |
| 4195 | .set_rate = set_rate_mnd, |
| 4196 | .freq_tbl = ftbl_audio_core_lpaif_clock, |
| 4197 | .current_freq = &rcg_dummy_freq, |
| 4198 | .base = &virt_bases[LPASS_BASE], |
| 4199 | .c = { |
| 4200 | .dbg_name = "audio_core_lpaif_pcmoe_clk_src", |
| 4201 | .ops = &clk_ops_rcg_mnd, |
| 4202 | VDD_DIG_FMAX_MAP1(LOW, 12290000), |
| 4203 | CLK_INIT(audio_core_lpaif_pcmoe_clk_src.c), |
| 4204 | }, |
| 4205 | }; |
| 4206 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4207 | static struct branch_clk audio_core_lpaif_codec_spkr_osr_clk = { |
| 4208 | .cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_OSR_CBCR, |
| 4209 | .parent = &audio_core_lpaif_codec_spkr_clk_src.c, |
| 4210 | .has_sibling = 1, |
| 4211 | .base = &virt_bases[LPASS_BASE], |
| 4212 | .c = { |
Vikram Mulukutla | fed770b | 2012-07-13 15:10:52 -0700 | [diff] [blame] | 4213 | .dbg_name = "audio_core_lpaif_codec_spkr_osr_clk", |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4214 | .ops = &clk_ops_branch, |
Vikram Mulukutla | fed770b | 2012-07-13 15:10:52 -0700 | [diff] [blame] | 4215 | CLK_INIT(audio_core_lpaif_codec_spkr_osr_clk.c), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4216 | }, |
| 4217 | }; |
| 4218 | |
| 4219 | static struct branch_clk audio_core_lpaif_codec_spkr_ebit_clk = { |
| 4220 | .cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_EBIT_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4221 | .has_sibling = 1, |
| 4222 | .base = &virt_bases[LPASS_BASE], |
| 4223 | .c = { |
Vikram Mulukutla | fed770b | 2012-07-13 15:10:52 -0700 | [diff] [blame] | 4224 | .dbg_name = "audio_core_lpaif_codec_spkr_ebit_clk", |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4225 | .ops = &clk_ops_branch, |
Vikram Mulukutla | fed770b | 2012-07-13 15:10:52 -0700 | [diff] [blame] | 4226 | CLK_INIT(audio_core_lpaif_codec_spkr_ebit_clk.c), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4227 | }, |
| 4228 | }; |
| 4229 | |
| 4230 | static struct branch_clk audio_core_lpaif_codec_spkr_ibit_clk = { |
| 4231 | .cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_IBIT_CBCR, |
| 4232 | .parent = &audio_core_lpaif_codec_spkr_clk_src.c, |
| 4233 | .has_sibling = 1, |
Vikram Mulukutla | 94ee5bb | 2012-05-16 13:57:28 -0700 | [diff] [blame] | 4234 | .max_div = 15, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4235 | .base = &virt_bases[LPASS_BASE], |
| 4236 | .c = { |
Vikram Mulukutla | fed770b | 2012-07-13 15:10:52 -0700 | [diff] [blame] | 4237 | .dbg_name = "audio_core_lpaif_codec_spkr_ibit_clk", |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4238 | .ops = &clk_ops_branch, |
Vikram Mulukutla | fed770b | 2012-07-13 15:10:52 -0700 | [diff] [blame] | 4239 | CLK_INIT(audio_core_lpaif_codec_spkr_ibit_clk.c), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4240 | }, |
| 4241 | }; |
| 4242 | |
| 4243 | static struct branch_clk audio_core_lpaif_pri_osr_clk = { |
| 4244 | .cbcr_reg = AUDIO_CORE_LPAIF_PRI_OSR_CBCR, |
| 4245 | .parent = &audio_core_lpaif_pri_clk_src.c, |
| 4246 | .has_sibling = 1, |
| 4247 | .base = &virt_bases[LPASS_BASE], |
| 4248 | .c = { |
| 4249 | .dbg_name = "audio_core_lpaif_pri_osr_clk", |
| 4250 | .ops = &clk_ops_branch, |
| 4251 | CLK_INIT(audio_core_lpaif_pri_osr_clk.c), |
| 4252 | }, |
| 4253 | }; |
| 4254 | |
| 4255 | static struct branch_clk audio_core_lpaif_pri_ebit_clk = { |
| 4256 | .cbcr_reg = AUDIO_CORE_LPAIF_PRI_EBIT_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4257 | .has_sibling = 1, |
| 4258 | .base = &virt_bases[LPASS_BASE], |
| 4259 | .c = { |
| 4260 | .dbg_name = "audio_core_lpaif_pri_ebit_clk", |
| 4261 | .ops = &clk_ops_branch, |
| 4262 | CLK_INIT(audio_core_lpaif_pri_ebit_clk.c), |
| 4263 | }, |
| 4264 | }; |
| 4265 | |
| 4266 | static struct branch_clk audio_core_lpaif_pri_ibit_clk = { |
| 4267 | .cbcr_reg = AUDIO_CORE_LPAIF_PRI_IBIT_CBCR, |
| 4268 | .parent = &audio_core_lpaif_pri_clk_src.c, |
| 4269 | .has_sibling = 1, |
Vikram Mulukutla | 94ee5bb | 2012-05-16 13:57:28 -0700 | [diff] [blame] | 4270 | .max_div = 15, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4271 | .base = &virt_bases[LPASS_BASE], |
| 4272 | .c = { |
| 4273 | .dbg_name = "audio_core_lpaif_pri_ibit_clk", |
| 4274 | .ops = &clk_ops_branch, |
| 4275 | CLK_INIT(audio_core_lpaif_pri_ibit_clk.c), |
| 4276 | }, |
| 4277 | }; |
| 4278 | |
| 4279 | static struct branch_clk audio_core_lpaif_sec_osr_clk = { |
| 4280 | .cbcr_reg = AUDIO_CORE_LPAIF_SEC_OSR_CBCR, |
| 4281 | .parent = &audio_core_lpaif_sec_clk_src.c, |
| 4282 | .has_sibling = 1, |
| 4283 | .base = &virt_bases[LPASS_BASE], |
| 4284 | .c = { |
| 4285 | .dbg_name = "audio_core_lpaif_sec_osr_clk", |
| 4286 | .ops = &clk_ops_branch, |
| 4287 | CLK_INIT(audio_core_lpaif_sec_osr_clk.c), |
| 4288 | }, |
| 4289 | }; |
| 4290 | |
| 4291 | static struct branch_clk audio_core_lpaif_sec_ebit_clk = { |
| 4292 | .cbcr_reg = AUDIO_CORE_LPAIF_SEC_EBIT_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4293 | .has_sibling = 1, |
| 4294 | .base = &virt_bases[LPASS_BASE], |
| 4295 | .c = { |
| 4296 | .dbg_name = "audio_core_lpaif_sec_ebit_clk", |
| 4297 | .ops = &clk_ops_branch, |
| 4298 | CLK_INIT(audio_core_lpaif_sec_ebit_clk.c), |
| 4299 | }, |
| 4300 | }; |
| 4301 | |
| 4302 | static struct branch_clk audio_core_lpaif_sec_ibit_clk = { |
| 4303 | .cbcr_reg = AUDIO_CORE_LPAIF_SEC_IBIT_CBCR, |
| 4304 | .parent = &audio_core_lpaif_sec_clk_src.c, |
| 4305 | .has_sibling = 1, |
Vikram Mulukutla | 94ee5bb | 2012-05-16 13:57:28 -0700 | [diff] [blame] | 4306 | .max_div = 15, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4307 | .base = &virt_bases[LPASS_BASE], |
| 4308 | .c = { |
| 4309 | .dbg_name = "audio_core_lpaif_sec_ibit_clk", |
| 4310 | .ops = &clk_ops_branch, |
| 4311 | CLK_INIT(audio_core_lpaif_sec_ibit_clk.c), |
| 4312 | }, |
| 4313 | }; |
| 4314 | |
| 4315 | static struct branch_clk audio_core_lpaif_ter_osr_clk = { |
| 4316 | .cbcr_reg = AUDIO_CORE_LPAIF_TER_OSR_CBCR, |
| 4317 | .parent = &audio_core_lpaif_ter_clk_src.c, |
| 4318 | .has_sibling = 1, |
| 4319 | .base = &virt_bases[LPASS_BASE], |
| 4320 | .c = { |
| 4321 | .dbg_name = "audio_core_lpaif_ter_osr_clk", |
| 4322 | .ops = &clk_ops_branch, |
| 4323 | CLK_INIT(audio_core_lpaif_ter_osr_clk.c), |
| 4324 | }, |
| 4325 | }; |
| 4326 | |
| 4327 | static struct branch_clk audio_core_lpaif_ter_ebit_clk = { |
| 4328 | .cbcr_reg = AUDIO_CORE_LPAIF_TER_EBIT_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4329 | .has_sibling = 1, |
| 4330 | .base = &virt_bases[LPASS_BASE], |
| 4331 | .c = { |
| 4332 | .dbg_name = "audio_core_lpaif_ter_ebit_clk", |
| 4333 | .ops = &clk_ops_branch, |
| 4334 | CLK_INIT(audio_core_lpaif_ter_ebit_clk.c), |
| 4335 | }, |
| 4336 | }; |
| 4337 | |
| 4338 | static struct branch_clk audio_core_lpaif_ter_ibit_clk = { |
| 4339 | .cbcr_reg = AUDIO_CORE_LPAIF_TER_IBIT_CBCR, |
| 4340 | .parent = &audio_core_lpaif_ter_clk_src.c, |
| 4341 | .has_sibling = 1, |
Vikram Mulukutla | 94ee5bb | 2012-05-16 13:57:28 -0700 | [diff] [blame] | 4342 | .max_div = 15, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4343 | .base = &virt_bases[LPASS_BASE], |
| 4344 | .c = { |
| 4345 | .dbg_name = "audio_core_lpaif_ter_ibit_clk", |
| 4346 | .ops = &clk_ops_branch, |
| 4347 | CLK_INIT(audio_core_lpaif_ter_ibit_clk.c), |
| 4348 | }, |
| 4349 | }; |
| 4350 | |
| 4351 | static struct branch_clk audio_core_lpaif_quad_osr_clk = { |
| 4352 | .cbcr_reg = AUDIO_CORE_LPAIF_QUAD_OSR_CBCR, |
| 4353 | .parent = &audio_core_lpaif_quad_clk_src.c, |
| 4354 | .has_sibling = 1, |
| 4355 | .base = &virt_bases[LPASS_BASE], |
| 4356 | .c = { |
| 4357 | .dbg_name = "audio_core_lpaif_quad_osr_clk", |
| 4358 | .ops = &clk_ops_branch, |
| 4359 | CLK_INIT(audio_core_lpaif_quad_osr_clk.c), |
| 4360 | }, |
| 4361 | }; |
| 4362 | |
| 4363 | static struct branch_clk audio_core_lpaif_quad_ebit_clk = { |
| 4364 | .cbcr_reg = AUDIO_CORE_LPAIF_QUAD_EBIT_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4365 | .has_sibling = 1, |
| 4366 | .base = &virt_bases[LPASS_BASE], |
| 4367 | .c = { |
| 4368 | .dbg_name = "audio_core_lpaif_quad_ebit_clk", |
| 4369 | .ops = &clk_ops_branch, |
| 4370 | CLK_INIT(audio_core_lpaif_quad_ebit_clk.c), |
| 4371 | }, |
| 4372 | }; |
| 4373 | |
| 4374 | static struct branch_clk audio_core_lpaif_quad_ibit_clk = { |
| 4375 | .cbcr_reg = AUDIO_CORE_LPAIF_QUAD_IBIT_CBCR, |
| 4376 | .parent = &audio_core_lpaif_quad_clk_src.c, |
| 4377 | .has_sibling = 1, |
Vikram Mulukutla | 94ee5bb | 2012-05-16 13:57:28 -0700 | [diff] [blame] | 4378 | .max_div = 15, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4379 | .base = &virt_bases[LPASS_BASE], |
| 4380 | .c = { |
| 4381 | .dbg_name = "audio_core_lpaif_quad_ibit_clk", |
| 4382 | .ops = &clk_ops_branch, |
| 4383 | CLK_INIT(audio_core_lpaif_quad_ibit_clk.c), |
| 4384 | }, |
| 4385 | }; |
| 4386 | |
| 4387 | static struct branch_clk audio_core_lpaif_pcm0_ebit_clk = { |
| 4388 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM0_EBIT_CBCR, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4389 | .has_sibling = 1, |
| 4390 | .base = &virt_bases[LPASS_BASE], |
| 4391 | .c = { |
| 4392 | .dbg_name = "audio_core_lpaif_pcm0_ebit_clk", |
| 4393 | .ops = &clk_ops_branch, |
| 4394 | CLK_INIT(audio_core_lpaif_pcm0_ebit_clk.c), |
| 4395 | }, |
| 4396 | }; |
| 4397 | |
| 4398 | static struct branch_clk audio_core_lpaif_pcm0_ibit_clk = { |
| 4399 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM0_IBIT_CBCR, |
| 4400 | .parent = &audio_core_lpaif_pcm0_clk_src.c, |
| 4401 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4402 | .base = &virt_bases[LPASS_BASE], |
| 4403 | .c = { |
| 4404 | .dbg_name = "audio_core_lpaif_pcm0_ibit_clk", |
| 4405 | .ops = &clk_ops_branch, |
| 4406 | CLK_INIT(audio_core_lpaif_pcm0_ibit_clk.c), |
| 4407 | }, |
| 4408 | }; |
| 4409 | |
| 4410 | static struct branch_clk audio_core_lpaif_pcm1_ebit_clk = { |
| 4411 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM1_EBIT_CBCR, |
| 4412 | .parent = &audio_core_lpaif_pcm1_clk_src.c, |
| 4413 | .has_sibling = 1, |
| 4414 | .base = &virt_bases[LPASS_BASE], |
| 4415 | .c = { |
| 4416 | .dbg_name = "audio_core_lpaif_pcm1_ebit_clk", |
| 4417 | .ops = &clk_ops_branch, |
| 4418 | CLK_INIT(audio_core_lpaif_pcm1_ebit_clk.c), |
| 4419 | }, |
| 4420 | }; |
| 4421 | |
| 4422 | static struct branch_clk audio_core_lpaif_pcm1_ibit_clk = { |
| 4423 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM1_IBIT_CBCR, |
| 4424 | .parent = &audio_core_lpaif_pcm1_clk_src.c, |
| 4425 | .has_sibling = 1, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4426 | .base = &virt_bases[LPASS_BASE], |
| 4427 | .c = { |
| 4428 | .dbg_name = "audio_core_lpaif_pcm1_ibit_clk", |
| 4429 | .ops = &clk_ops_branch, |
| 4430 | CLK_INIT(audio_core_lpaif_pcm1_ibit_clk.c), |
| 4431 | }, |
| 4432 | }; |
| 4433 | |
Vikram Mulukutla | 1d25218 | 2012-07-13 10:51:44 -0700 | [diff] [blame] | 4434 | struct branch_clk audio_core_lpaif_pcmoe_clk = { |
| 4435 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR, |
| 4436 | .parent = &audio_core_lpaif_pcmoe_clk_src.c, |
| 4437 | .base = &virt_bases[LPASS_BASE], |
| 4438 | .c = { |
| 4439 | .dbg_name = "audio_core_lpaif_pcmoe_clk", |
| 4440 | .ops = &clk_ops_branch, |
| 4441 | CLK_INIT(audio_core_lpaif_pcmoe_clk.c), |
| 4442 | }, |
| 4443 | }; |
| 4444 | |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 4445 | static struct branch_clk q6ss_ahb_lfabif_clk = { |
| 4446 | .cbcr_reg = LPASS_Q6SS_AHB_LFABIF_CBCR, |
| 4447 | .has_sibling = 1, |
| 4448 | .base = &virt_bases[LPASS_BASE], |
| 4449 | .c = { |
| 4450 | .dbg_name = "q6ss_ahb_lfabif_clk", |
| 4451 | .ops = &clk_ops_branch, |
| 4452 | CLK_INIT(q6ss_ahb_lfabif_clk.c), |
| 4453 | }, |
| 4454 | }; |
| 4455 | |
Vikram Mulukutla | 6c0f1a7 | 2012-08-10 01:59:28 -0700 | [diff] [blame] | 4456 | static struct branch_clk audio_core_ixfabric_clk = { |
| 4457 | .cbcr_reg = AUDIO_CORE_IXFABRIC_CBCR, |
| 4458 | .has_sibling = 1, |
| 4459 | .base = &virt_bases[LPASS_BASE], |
| 4460 | .c = { |
| 4461 | .dbg_name = "audio_core_ixfabric_clk", |
| 4462 | .ops = &clk_ops_branch, |
| 4463 | CLK_INIT(audio_core_ixfabric_clk.c), |
| 4464 | }, |
| 4465 | }; |
| 4466 | |
Vikram Mulukutla | 3454e9e | 2012-08-11 20:18:42 -0700 | [diff] [blame] | 4467 | static struct branch_clk gcc_lpass_q6_axi_clk = { |
| 4468 | .cbcr_reg = LPASS_Q6_AXI_CBCR, |
| 4469 | .has_sibling = 1, |
| 4470 | .base = &virt_bases[GCC_BASE], |
| 4471 | .c = { |
| 4472 | .dbg_name = "gcc_lpass_q6_axi_clk", |
| 4473 | .ops = &clk_ops_branch, |
| 4474 | CLK_INIT(gcc_lpass_q6_axi_clk.c), |
| 4475 | }, |
| 4476 | }; |
| 4477 | |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 4478 | static struct branch_clk q6ss_xo_clk = { |
| 4479 | .cbcr_reg = LPASS_Q6SS_XO_CBCR, |
| 4480 | .bcr_reg = LPASS_Q6SS_BCR, |
| 4481 | .has_sibling = 1, |
| 4482 | .base = &virt_bases[LPASS_BASE], |
| 4483 | .c = { |
| 4484 | .dbg_name = "q6ss_xo_clk", |
| 4485 | .ops = &clk_ops_branch, |
| 4486 | CLK_INIT(q6ss_xo_clk.c), |
| 4487 | }, |
| 4488 | }; |
| 4489 | |
Vikram Mulukutla | b5b311e | 2012-08-09 14:58:48 -0700 | [diff] [blame] | 4490 | static struct branch_clk q6ss_ahbm_clk = { |
| 4491 | .cbcr_reg = Q6SS_AHBM_CBCR, |
| 4492 | .has_sibling = 1, |
| 4493 | .base = &virt_bases[LPASS_BASE], |
| 4494 | .c = { |
| 4495 | .dbg_name = "q6ss_ahbm_clk", |
| 4496 | .ops = &clk_ops_branch, |
| 4497 | CLK_INIT(q6ss_ahbm_clk.c), |
| 4498 | }, |
| 4499 | }; |
| 4500 | |
Vikram Mulukutla | 97ac334 | 2012-08-21 12:55:13 -0700 | [diff] [blame^] | 4501 | static struct branch_clk audio_wrapper_br_clk = { |
| 4502 | .cbcr_reg = AUDIO_WRAPPER_BR_CBCR, |
| 4503 | .has_sibling = 1, |
| 4504 | .base = &virt_bases[LPASS_BASE], |
| 4505 | .c = { |
| 4506 | .dbg_name = "audio_wrapper_br_clk", |
| 4507 | .ops = &clk_ops_branch, |
| 4508 | CLK_INIT(audio_wrapper_br_clk.c), |
| 4509 | }, |
| 4510 | }; |
| 4511 | |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 4512 | static struct branch_clk mss_xo_q6_clk = { |
| 4513 | .cbcr_reg = MSS_XO_Q6_CBCR, |
| 4514 | .bcr_reg = MSS_Q6SS_BCR, |
| 4515 | .has_sibling = 1, |
| 4516 | .base = &virt_bases[MSS_BASE], |
| 4517 | .c = { |
| 4518 | .dbg_name = "mss_xo_q6_clk", |
| 4519 | .ops = &clk_ops_branch, |
| 4520 | CLK_INIT(mss_xo_q6_clk.c), |
| 4521 | .depends = &gcc_mss_cfg_ahb_clk.c, |
| 4522 | }, |
| 4523 | }; |
| 4524 | |
| 4525 | static struct branch_clk mss_bus_q6_clk = { |
| 4526 | .cbcr_reg = MSS_BUS_Q6_CBCR, |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 4527 | .has_sibling = 1, |
| 4528 | .base = &virt_bases[MSS_BASE], |
| 4529 | .c = { |
| 4530 | .dbg_name = "mss_bus_q6_clk", |
| 4531 | .ops = &clk_ops_branch, |
| 4532 | CLK_INIT(mss_bus_q6_clk.c), |
| 4533 | .depends = &gcc_mss_cfg_ahb_clk.c, |
| 4534 | }, |
| 4535 | }; |
| 4536 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 4537 | static DEFINE_CLK_MEASURE(l2_m_clk); |
| 4538 | static DEFINE_CLK_MEASURE(krait0_m_clk); |
| 4539 | static DEFINE_CLK_MEASURE(krait1_m_clk); |
| 4540 | static DEFINE_CLK_MEASURE(krait2_m_clk); |
| 4541 | static DEFINE_CLK_MEASURE(krait3_m_clk); |
| 4542 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4543 | #ifdef CONFIG_DEBUG_FS |
| 4544 | |
| 4545 | struct measure_mux_entry { |
| 4546 | struct clk *c; |
| 4547 | int base; |
| 4548 | u32 debug_mux; |
| 4549 | }; |
| 4550 | |
| 4551 | struct measure_mux_entry measure_mux[] = { |
Vikram Mulukutla | 9cd8f0f | 2012-07-27 14:15:24 -0700 | [diff] [blame] | 4552 | {&gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0}, |
| 4553 | {&gcc_blsp2_qup1_i2c_apps_clk.c, GCC_BASE, 0x00ab}, |
| 4554 | {&gcc_blsp2_qup3_spi_apps_clk.c, GCC_BASE, 0x00b3}, |
| 4555 | {&gcc_blsp2_uart5_apps_clk.c, GCC_BASE, 0x00be}, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4556 | {&gcc_usb30_master_clk.c, GCC_BASE, 0x0050}, |
Vikram Mulukutla | 9cd8f0f | 2012-07-27 14:15:24 -0700 | [diff] [blame] | 4557 | {&gcc_blsp2_qup3_i2c_apps_clk.c, GCC_BASE, 0x00b4}, |
| 4558 | {&gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059}, |
| 4559 | {&gcc_blsp2_uart3_apps_clk.c, GCC_BASE, 0x00b5}, |
| 4560 | {&gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b}, |
| 4561 | {&gcc_ce2_axi_clk.c, GCC_BASE, 0x0141}, |
| 4562 | {&gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079}, |
| 4563 | {&gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d}, |
| 4564 | {&gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a}, |
| 4565 | {&gcc_blsp2_uart4_apps_clk.c, GCC_BASE, 0x00ba}, |
| 4566 | {&gcc_ce2_clk.c, GCC_BASE, 0x0140}, |
| 4567 | {&gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091}, |
| 4568 | {&gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069}, |
| 4569 | {&gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030}, |
| 4570 | {&gcc_tsif_ahb_clk.c, GCC_BASE, 0x00e8}, |
| 4571 | {&gcc_sdcc4_ahb_clk.c, GCC_BASE, 0x0081}, |
| 4572 | {&gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098}, |
| 4573 | {&gcc_blsp2_qup4_spi_apps_clk.c, GCC_BASE, 0x00b8}, |
| 4574 | {&gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093}, |
| 4575 | {&gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2}, |
| 4576 | {&gcc_blsp2_qup6_i2c_apps_clk.c, GCC_BASE, 0x00c2}, |
| 4577 | {&gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0}, |
| 4578 | {&gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078}, |
| 4579 | {&gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060}, |
| 4580 | {&gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088}, |
| 4581 | {&gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068}, |
| 4582 | {&gcc_blsp2_qup5_i2c_apps_clk.c, GCC_BASE, 0x00bd}, |
| 4583 | {&gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a}, |
| 4584 | {&gcc_blsp2_qup2_spi_apps_clk.c, GCC_BASE, 0x00ae}, |
| 4585 | {&gcc_blsp2_qup6_spi_apps_clk.c, GCC_BASE, 0x00c1}, |
| 4586 | {&gcc_blsp2_uart2_apps_clk.c, GCC_BASE, 0x00b1}, |
| 4587 | {&gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e}, |
| 4588 | {&gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058}, |
| 4589 | {&gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095}, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4590 | {&gcc_usb30_mock_utmi_clk.c, GCC_BASE, 0x0052}, |
Vikram Mulukutla | 9cd8f0f | 2012-07-27 14:15:24 -0700 | [diff] [blame] | 4591 | {&gcc_ce1_axi_clk.c, GCC_BASE, 0x0139}, |
| 4592 | {&gcc_sdcc4_apps_clk.c, GCC_BASE, 0x0080}, |
| 4593 | {&gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c}, |
| 4594 | {&gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061}, |
| 4595 | {&gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1}, |
| 4596 | {&gcc_blsp2_qup2_i2c_apps_clk.c, GCC_BASE, 0x00b0}, |
| 4597 | {&gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8}, |
| 4598 | {&gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094}, |
| 4599 | {&gcc_usb_hsic_clk.c, GCC_BASE, 0x005a}, |
| 4600 | {&gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3}, |
| 4601 | {&gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070}, |
| 4602 | {&gcc_tsif_ref_clk.c, GCC_BASE, 0x00e9}, |
| 4603 | {&gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c}, |
| 4604 | {&gcc_blsp2_qup5_spi_apps_clk.c, GCC_BASE, 0x00bc}, |
| 4605 | {&gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099}, |
| 4606 | {&gcc_mmss_noc_cfg_ahb_clk.c, GCC_BASE, 0x002a}, |
| 4607 | {&gcc_blsp2_ahb_clk.c, GCC_BASE, 0x00a8}, |
| 4608 | {&gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8}, |
| 4609 | {&gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a}, |
| 4610 | {&gcc_pdm2_clk.c, GCC_BASE, 0x00d2}, |
| 4611 | {&gcc_blsp2_qup4_i2c_apps_clk.c, GCC_BASE, 0x00b9}, |
| 4612 | {&gcc_ce2_ahb_clk.c, GCC_BASE, 0x0142}, |
| 4613 | {&gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e}, |
| 4614 | {&gcc_blsp2_qup1_spi_apps_clk.c, GCC_BASE, 0x00aa}, |
| 4615 | {&gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090}, |
| 4616 | {&gcc_blsp2_uart1_apps_clk.c, GCC_BASE, 0x00ac}, |
| 4617 | {&gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b}, |
| 4618 | {&gcc_blsp2_uart6_apps_clk.c, GCC_BASE, 0x00c3}, |
| 4619 | {&gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071}, |
Vikram Mulukutla | 3b98a6d | 2012-08-15 20:35:25 -0700 | [diff] [blame] | 4620 | {&gcc_usb30_sleep_clk.c, GCC_BASE, 0x0051}, |
| 4621 | {&gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063}, |
| 4622 | {&gcc_usb2b_phy_sleep_clk.c, GCC_BASE, 0x0064}, |
| 4623 | {&gcc_sys_noc_usb3_axi_clk.c, GCC_BASE, 0x0001}, |
Vikram Mulukutla | 9cd8f0f | 2012-07-27 14:15:24 -0700 | [diff] [blame] | 4624 | {&gcc_ocmem_noc_cfg_ahb_clk.c, GCC_BASE, 0x0029}, |
| 4625 | {&gcc_ce1_clk.c, GCC_BASE, 0x0138}, |
Vikram Mulukutla | 3454e9e | 2012-08-11 20:18:42 -0700 | [diff] [blame] | 4626 | {&gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160}, |
Vikram Mulukutla | 31926eb | 2012-08-12 19:58:08 -0700 | [diff] [blame] | 4627 | {&gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031}, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4628 | {&mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004}, |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 4629 | {&ocmemnoc_clk.c, MMSS_BASE, 0x0007}, |
Vikram Mulukutla | 274b2d9 | 2012-07-13 15:53:04 -0700 | [diff] [blame] | 4630 | {&ocmemcx_ocmemnoc_clk.c, MMSS_BASE, 0x0009}, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4631 | {&camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e}, |
| 4632 | {&camss_cci_cci_clk.c, MMSS_BASE, 0x002d}, |
| 4633 | {&camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042}, |
| 4634 | {&camss_csi0_clk.c, MMSS_BASE, 0x0041}, |
| 4635 | {&camss_csi0phy_clk.c, MMSS_BASE, 0x0043}, |
| 4636 | {&camss_csi0pix_clk.c, MMSS_BASE, 0x0045}, |
| 4637 | {&camss_csi0rdi_clk.c, MMSS_BASE, 0x0044}, |
| 4638 | {&camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047}, |
| 4639 | {&camss_csi1_clk.c, MMSS_BASE, 0x0046}, |
| 4640 | {&camss_csi1phy_clk.c, MMSS_BASE, 0x0048}, |
| 4641 | {&camss_csi1pix_clk.c, MMSS_BASE, 0x004a}, |
| 4642 | {&camss_csi1rdi_clk.c, MMSS_BASE, 0x0049}, |
| 4643 | {&camss_csi2_ahb_clk.c, MMSS_BASE, 0x004c}, |
| 4644 | {&camss_csi2_clk.c, MMSS_BASE, 0x004b}, |
| 4645 | {&camss_csi2phy_clk.c, MMSS_BASE, 0x004d}, |
| 4646 | {&camss_csi2pix_clk.c, MMSS_BASE, 0x004f}, |
| 4647 | {&camss_csi2rdi_clk.c, MMSS_BASE, 0x004e}, |
| 4648 | {&camss_csi3_ahb_clk.c, MMSS_BASE, 0x0051}, |
| 4649 | {&camss_csi3_clk.c, MMSS_BASE, 0x0050}, |
| 4650 | {&camss_csi3phy_clk.c, MMSS_BASE, 0x0052}, |
| 4651 | {&camss_csi3pix_clk.c, MMSS_BASE, 0x0054}, |
| 4652 | {&camss_csi3rdi_clk.c, MMSS_BASE, 0x0053}, |
| 4653 | {&camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f}, |
| 4654 | {&camss_csi_vfe1_clk.c, MMSS_BASE, 0x0040}, |
| 4655 | {&camss_gp0_clk.c, MMSS_BASE, 0x0027}, |
| 4656 | {&camss_gp1_clk.c, MMSS_BASE, 0x0028}, |
| 4657 | {&camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055}, |
| 4658 | {&camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032}, |
| 4659 | {&camss_jpeg_jpeg1_clk.c, MMSS_BASE, 0x0033}, |
| 4660 | {&camss_jpeg_jpeg2_clk.c, MMSS_BASE, 0x0034}, |
| 4661 | {&camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035}, |
| 4662 | {&camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036}, |
| 4663 | {&camss_jpeg_jpeg_ocmemnoc_clk.c, MMSS_BASE, 0x0037}, |
| 4664 | {&camss_mclk0_clk.c, MMSS_BASE, 0x0029}, |
| 4665 | {&camss_mclk1_clk.c, MMSS_BASE, 0x002a}, |
| 4666 | {&camss_mclk2_clk.c, MMSS_BASE, 0x002b}, |
| 4667 | {&camss_mclk3_clk.c, MMSS_BASE, 0x002c}, |
| 4668 | {&camss_micro_ahb_clk.c, MMSS_BASE, 0x0026}, |
| 4669 | {&camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f}, |
| 4670 | {&camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030}, |
| 4671 | {&camss_phy2_csi2phytimer_clk.c, MMSS_BASE, 0x0031}, |
| 4672 | {&camss_top_ahb_clk.c, MMSS_BASE, 0x0025}, |
| 4673 | {&camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b}, |
| 4674 | {&camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a}, |
| 4675 | {&camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038}, |
| 4676 | {&camss_vfe_vfe1_clk.c, MMSS_BASE, 0x0039}, |
| 4677 | {&camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c}, |
| 4678 | {&camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d}, |
| 4679 | {&camss_vfe_vfe_ocmemnoc_clk.c, MMSS_BASE, 0x003e}, |
Vikram Mulukutla | df04d53 | 2012-08-10 21:01:00 -0700 | [diff] [blame] | 4680 | {&oxilicx_axi_clk.c, MMSS_BASE, 0x000b}, |
| 4681 | {&oxilicx_ahb_clk.c, MMSS_BASE, 0x000c}, |
| 4682 | {&ocmemcx_ocmemnoc_clk.c, MMSS_BASE, 0x0009}, |
| 4683 | {&oxili_gfx3d_clk.c, MMSS_BASE, 0x000d}, |
| 4684 | {&venus0_axi_clk.c, MMSS_BASE, 0x000f}, |
| 4685 | {&venus0_ocmemnoc_clk.c, MMSS_BASE, 0x0010}, |
| 4686 | {&venus0_ahb_clk.c, MMSS_BASE, 0x0011}, |
| 4687 | {&venus0_vcodec0_clk.c, MMSS_BASE, 0x000e}, |
| 4688 | {&mmss_s0_axi_clk.c, MMSS_BASE, 0x0005}, |
| 4689 | {&mmssnoc_ahb_clk.c, MMSS_BASE, 0x0001}, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4690 | {&mdss_ahb_clk.c, MMSS_BASE, 0x0022}, |
| 4691 | {&mdss_hdmi_clk.c, MMSS_BASE, 0x001d}, |
| 4692 | {&mdss_mdp_clk.c, MMSS_BASE, 0x0014}, |
| 4693 | {&mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015}, |
| 4694 | {&mdss_axi_clk.c, MMSS_BASE, 0x0024}, |
| 4695 | {&mdss_vsync_clk.c, MMSS_BASE, 0x001c}, |
| 4696 | {&mdss_esc0_clk.c, MMSS_BASE, 0x0020}, |
| 4697 | {&mdss_esc1_clk.c, MMSS_BASE, 0x0021}, |
| 4698 | {&mdss_edpaux_clk.c, MMSS_BASE, 0x001b}, |
| 4699 | {&mdss_byte0_clk.c, MMSS_BASE, 0x001e}, |
| 4700 | {&mdss_byte1_clk.c, MMSS_BASE, 0x001f}, |
| 4701 | {&mdss_edplink_clk.c, MMSS_BASE, 0x001a}, |
| 4702 | {&mdss_edppixel_clk.c, MMSS_BASE, 0x0019}, |
| 4703 | {&mdss_extpclk_clk.c, MMSS_BASE, 0x0018}, |
| 4704 | {&mdss_hdmi_ahb_clk.c, MMSS_BASE, 0x0023}, |
| 4705 | {&mdss_pclk0_clk.c, MMSS_BASE, 0x0016}, |
| 4706 | {&mdss_pclk1_clk.c, MMSS_BASE, 0x0017}, |
| 4707 | {&audio_core_lpaif_pri_clk_src.c, LPASS_BASE, 0x0017}, |
| 4708 | {&audio_core_lpaif_sec_clk_src.c, LPASS_BASE, 0x0016}, |
| 4709 | {&audio_core_lpaif_ter_clk_src.c, LPASS_BASE, 0x0015}, |
| 4710 | {&audio_core_lpaif_quad_clk_src.c, LPASS_BASE, 0x0014}, |
| 4711 | {&audio_core_lpaif_pcm0_clk_src.c, LPASS_BASE, 0x0013}, |
| 4712 | {&audio_core_lpaif_pcm1_clk_src.c, LPASS_BASE, 0x0012}, |
Vikram Mulukutla | 1d25218 | 2012-07-13 10:51:44 -0700 | [diff] [blame] | 4713 | {&audio_core_lpaif_pcmoe_clk_src.c, LPASS_BASE, 0x000f}, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4714 | {&audio_core_slimbus_core_clk.c, LPASS_BASE, 0x003d}, |
| 4715 | {&audio_core_slimbus_lfabif_clk.c, LPASS_BASE, 0x003e}, |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 4716 | {&q6ss_xo_clk.c, LPASS_BASE, 0x002b}, |
| 4717 | {&q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e}, |
Vikram Mulukutla | b5b311e | 2012-08-09 14:58:48 -0700 | [diff] [blame] | 4718 | {&q6ss_ahbm_clk.c, LPASS_BASE, 0x001d}, |
Vikram Mulukutla | 6c0f1a7 | 2012-08-10 01:59:28 -0700 | [diff] [blame] | 4719 | {&audio_core_ixfabric_clk.c, LPASS_BASE, 0x0059}, |
Vikram Mulukutla | 97ac334 | 2012-08-21 12:55:13 -0700 | [diff] [blame^] | 4720 | {&audio_wrapper_br_clk.c, LPASS_BASE, 0x0022}, |
Vikram Mulukutla | ae7cfdb | 2012-08-10 15:30:21 -0700 | [diff] [blame] | 4721 | {&mss_bus_q6_clk.c, MSS_BASE, 0x003b}, |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 4722 | {&mss_xo_q6_clk.c, MSS_BASE, 0x0007}, |
| 4723 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 4724 | {&l2_m_clk, APCS_BASE, 0x0081}, |
| 4725 | {&krait0_m_clk, APCS_BASE, 0x0080}, |
| 4726 | {&krait1_m_clk, APCS_BASE, 0x0088}, |
| 4727 | {&krait2_m_clk, APCS_BASE, 0x0090}, |
| 4728 | {&krait3_m_clk, APCS_BASE, 0x0098}, |
| 4729 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4730 | {&dummy_clk, N_BASES, 0x0000}, |
| 4731 | }; |
| 4732 | |
| 4733 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
| 4734 | { |
| 4735 | struct measure_clk *clk = to_measure_clk(c); |
| 4736 | unsigned long flags; |
| 4737 | u32 regval, clk_sel, i; |
| 4738 | |
| 4739 | if (!parent) |
| 4740 | return -EINVAL; |
| 4741 | |
| 4742 | for (i = 0; i < (ARRAY_SIZE(measure_mux) - 1); i++) |
| 4743 | if (measure_mux[i].c == parent) |
| 4744 | break; |
| 4745 | |
| 4746 | if (measure_mux[i].c == &dummy_clk) |
| 4747 | return -EINVAL; |
| 4748 | |
| 4749 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 4750 | /* |
| 4751 | * Program the test vector, measurement period (sample_ticks) |
| 4752 | * and scaling multiplier. |
| 4753 | */ |
| 4754 | clk->sample_ticks = 0x10000; |
| 4755 | clk->multiplier = 1; |
| 4756 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4757 | switch (measure_mux[i].base) { |
| 4758 | |
| 4759 | case GCC_BASE: |
Vikram Mulukutla | ae7cfdb | 2012-08-10 15:30:21 -0700 | [diff] [blame] | 4760 | writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL_REG)); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4761 | clk_sel = measure_mux[i].debug_mux; |
| 4762 | break; |
| 4763 | |
| 4764 | case MMSS_BASE: |
Vikram Mulukutla | ae7cfdb | 2012-08-10 15:30:21 -0700 | [diff] [blame] | 4765 | writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL_REG)); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4766 | clk_sel = 0x02C; |
| 4767 | regval = BVAL(11, 0, measure_mux[i].debug_mux); |
| 4768 | writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL_REG)); |
| 4769 | |
| 4770 | /* Activate debug clock output */ |
| 4771 | regval |= BIT(16); |
| 4772 | writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL_REG)); |
| 4773 | break; |
| 4774 | |
| 4775 | case LPASS_BASE: |
Vikram Mulukutla | ae7cfdb | 2012-08-10 15:30:21 -0700 | [diff] [blame] | 4776 | writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL_REG)); |
Vikram Mulukutla | 9353701 | 2012-08-08 14:44:33 -0700 | [diff] [blame] | 4777 | clk_sel = 0x161; |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4778 | regval = BVAL(11, 0, measure_mux[i].debug_mux); |
| 4779 | writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL_REG)); |
| 4780 | |
| 4781 | /* Activate debug clock output */ |
Vikram Mulukutla | 9353701 | 2012-08-08 14:44:33 -0700 | [diff] [blame] | 4782 | regval |= BIT(20); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4783 | writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL_REG)); |
| 4784 | break; |
| 4785 | |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 4786 | case MSS_BASE: |
Vikram Mulukutla | ae7cfdb | 2012-08-10 15:30:21 -0700 | [diff] [blame] | 4787 | writel_relaxed(0, MSS_REG_BASE(MSS_DEBUG_CLK_CTL_REG)); |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 4788 | clk_sel = 0x32; |
| 4789 | regval = BVAL(5, 0, measure_mux[i].debug_mux); |
| 4790 | writel_relaxed(regval, MSS_REG_BASE(MSS_DEBUG_CLK_CTL_REG)); |
| 4791 | break; |
| 4792 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 4793 | case APCS_BASE: |
| 4794 | clk->multiplier = 4; |
| 4795 | clk_sel = 0x16A; |
| 4796 | regval = measure_mux[i].debug_mux; |
| 4797 | writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG_REG)); |
| 4798 | break; |
| 4799 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4800 | default: |
| 4801 | return -EINVAL; |
| 4802 | } |
| 4803 | |
| 4804 | /* Set debug mux clock index */ |
| 4805 | regval = BVAL(8, 0, clk_sel); |
| 4806 | writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL_REG)); |
| 4807 | |
| 4808 | /* Activate debug clock output */ |
| 4809 | regval |= BIT(16); |
| 4810 | writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL_REG)); |
| 4811 | |
| 4812 | /* Make sure test vector is set before starting measurements. */ |
| 4813 | mb(); |
| 4814 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 4815 | |
| 4816 | return 0; |
| 4817 | } |
| 4818 | |
| 4819 | /* Sample clock for 'ticks' reference clock ticks. */ |
| 4820 | static u32 run_measurement(unsigned ticks) |
| 4821 | { |
| 4822 | /* Stop counters and set the XO4 counter start value. */ |
| 4823 | writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL_REG)); |
| 4824 | |
| 4825 | /* Wait for timer to become ready. */ |
| 4826 | while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS_REG)) & |
| 4827 | BIT(25)) != 0) |
| 4828 | cpu_relax(); |
| 4829 | |
| 4830 | /* Run measurement and wait for completion. */ |
| 4831 | writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL_REG)); |
| 4832 | while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS_REG)) & |
| 4833 | BIT(25)) == 0) |
| 4834 | cpu_relax(); |
| 4835 | |
| 4836 | /* Return measured ticks. */ |
| 4837 | return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS_REG)) & |
| 4838 | BM(24, 0); |
| 4839 | } |
| 4840 | |
| 4841 | /* |
| 4842 | * Perform a hardware rate measurement for a given clock. |
| 4843 | * FOR DEBUG USE ONLY: Measurements take ~15 ms! |
| 4844 | */ |
| 4845 | static unsigned long measure_clk_get_rate(struct clk *c) |
| 4846 | { |
| 4847 | unsigned long flags; |
| 4848 | u32 gcc_xo4_reg_backup; |
| 4849 | u64 raw_count_short, raw_count_full; |
| 4850 | struct measure_clk *clk = to_measure_clk(c); |
| 4851 | unsigned ret; |
| 4852 | |
| 4853 | ret = clk_prepare_enable(&cxo_clk_src.c); |
| 4854 | if (ret) { |
| 4855 | pr_warning("CXO clock failed to enable. Can't measure\n"); |
| 4856 | return 0; |
| 4857 | } |
| 4858 | |
| 4859 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 4860 | |
| 4861 | /* Enable CXO/4 and RINGOSC branch. */ |
| 4862 | gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR_REG)); |
| 4863 | writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR_REG)); |
| 4864 | |
| 4865 | /* |
| 4866 | * The ring oscillator counter will not reset if the measured clock |
| 4867 | * is not running. To detect this, run a short measurement before |
| 4868 | * the full measurement. If the raw results of the two are the same |
| 4869 | * then the clock must be off. |
| 4870 | */ |
| 4871 | |
| 4872 | /* Run a short measurement. (~1 ms) */ |
| 4873 | raw_count_short = run_measurement(0x1000); |
| 4874 | /* Run a full measurement. (~14 ms) */ |
| 4875 | raw_count_full = run_measurement(clk->sample_ticks); |
| 4876 | |
| 4877 | writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR_REG)); |
| 4878 | |
| 4879 | /* Return 0 if the clock is off. */ |
| 4880 | if (raw_count_full == raw_count_short) { |
| 4881 | ret = 0; |
| 4882 | } else { |
| 4883 | /* Compute rate in Hz. */ |
| 4884 | raw_count_full = ((raw_count_full * 10) + 15) * 4800000; |
| 4885 | do_div(raw_count_full, ((clk->sample_ticks * 10) + 35)); |
| 4886 | ret = (raw_count_full * clk->multiplier); |
| 4887 | } |
| 4888 | |
Matt Wagantall | 9a9b6f0 | 2012-08-07 23:12:26 -0700 | [diff] [blame] | 4889 | writel_relaxed(0x51A00, GCC_REG_BASE(GCC_PLLTEST_PAD_CFG_REG)); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4890 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 4891 | |
| 4892 | clk_disable_unprepare(&cxo_clk_src.c); |
| 4893 | |
| 4894 | return ret; |
| 4895 | } |
| 4896 | #else /* !CONFIG_DEBUG_FS */ |
| 4897 | static int measure_clk_set_parent(struct clk *clk, struct clk *parent) |
| 4898 | { |
| 4899 | return -EINVAL; |
| 4900 | } |
| 4901 | |
| 4902 | static unsigned long measure_clk_get_rate(struct clk *clk) |
| 4903 | { |
| 4904 | return 0; |
| 4905 | } |
| 4906 | #endif /* CONFIG_DEBUG_FS */ |
| 4907 | |
Matt Wagantall | ae05322 | 2012-05-14 19:42:07 -0700 | [diff] [blame] | 4908 | static struct clk_ops clk_ops_measure = { |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4909 | .set_parent = measure_clk_set_parent, |
| 4910 | .get_rate = measure_clk_get_rate, |
| 4911 | }; |
| 4912 | |
| 4913 | static struct measure_clk measure_clk = { |
| 4914 | .c = { |
| 4915 | .dbg_name = "measure_clk", |
Matt Wagantall | ae05322 | 2012-05-14 19:42:07 -0700 | [diff] [blame] | 4916 | .ops = &clk_ops_measure, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4917 | CLK_INIT(measure_clk.c), |
| 4918 | }, |
| 4919 | .multiplier = 1, |
| 4920 | }; |
| 4921 | |
Vikram Mulukutla | 19245e0 | 2012-07-23 15:58:04 -0700 | [diff] [blame] | 4922 | |
| 4923 | static struct clk_lookup msm_clocks_8974_rumi[] = { |
| 4924 | CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"), |
| 4925 | CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"), |
| 4926 | CLK_LOOKUP("bus_clk", pnoc_sdcc1_clk.c, "msm_sdcc.1"), |
| 4927 | CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"), |
| 4928 | CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"), |
| 4929 | CLK_LOOKUP("bus_clk", pnoc_sdcc2_clk.c, "msm_sdcc.2"), |
| 4930 | CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"), |
| 4931 | CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"), |
| 4932 | CLK_LOOKUP("bus_clk", pnoc_sdcc3_clk.c, "msm_sdcc.3"), |
| 4933 | CLK_LOOKUP("iface_clk", gcc_sdcc4_ahb_clk.c, "msm_sdcc.4"), |
| 4934 | CLK_LOOKUP("core_clk", gcc_sdcc4_apps_clk.c, "msm_sdcc.4"), |
| 4935 | CLK_LOOKUP("bus_clk", pnoc_sdcc4_clk.c, "msm_sdcc.4"), |
| 4936 | CLK_DUMMY("xo", XO_CLK, NULL, OFF), |
| 4937 | CLK_DUMMY("xo", XO_CLK, "pil_pronto", OFF), |
Stepan Moskovchenko | f97dede7 | 2012-08-08 17:40:44 -0700 | [diff] [blame] | 4938 | CLK_DUMMY("core_clk", BLSP2_UART_CLK, "f991f000.serial", OFF), |
| 4939 | CLK_DUMMY("iface_clk", BLSP2_UART_CLK, "f991f000.serial", OFF), |
Vikram Mulukutla | 19245e0 | 2012-07-23 15:58:04 -0700 | [diff] [blame] | 4940 | CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF), |
| 4941 | CLK_DUMMY("iface_clk", SDC1_P_CLK, NULL, OFF), |
| 4942 | CLK_DUMMY("core_clk", SDC3_CLK, NULL, OFF), |
| 4943 | CLK_DUMMY("iface_clk", SDC3_P_CLK, NULL, OFF), |
| 4944 | CLK_DUMMY("phy_clk", NULL, "msm_otg", OFF), |
| 4945 | CLK_DUMMY("core_clk", NULL, "msm_otg", OFF), |
| 4946 | CLK_DUMMY("iface_clk", NULL, "msm_otg", OFF), |
| 4947 | CLK_DUMMY("xo", NULL, "msm_otg", OFF), |
| 4948 | CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0), |
| 4949 | CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0), |
| 4950 | CLK_DUMMY("mem_clk", NULL, NULL, 0), |
| 4951 | CLK_DUMMY("core_clk", SPI_CLK, "spi_qsd.1", OFF), |
| 4952 | CLK_DUMMY("iface_clk", SPI_P_CLK, "spi_qsd.1", OFF), |
| 4953 | CLK_DUMMY("core_clk", NULL, "f9966000.i2c", 0), |
| 4954 | CLK_DUMMY("iface_clk", NULL, "f9966000.i2c", 0), |
| 4955 | CLK_DUMMY("core_clk", NULL, "fe12f000.slim", OFF), |
| 4956 | CLK_DUMMY("core_clk", "mdp.0", NULL, 0), |
| 4957 | CLK_DUMMY("core_clk_src", "mdp.0", NULL, 0), |
| 4958 | CLK_DUMMY("lut_clk", "mdp.0", NULL, 0), |
| 4959 | CLK_DUMMY("vsync_clk", "mdp.0", NULL, 0), |
| 4960 | CLK_DUMMY("iface_clk", "mdp.0", NULL, 0), |
| 4961 | CLK_DUMMY("bus_clk", "mdp.0", NULL, 0), |
| 4962 | }; |
| 4963 | |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 4964 | static struct clk_lookup msm_clocks_8974[] = { |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4965 | CLK_LOOKUP("xo", cxo_clk_src.c, "msm_otg"), |
| 4966 | CLK_LOOKUP("xo", cxo_clk_src.c, "pil-q6v5-lpass"), |
Matt Wagantall | 4e2599e | 2012-03-21 22:31:35 -0700 | [diff] [blame] | 4967 | CLK_LOOKUP("xo", cxo_clk_src.c, "pil-q6v5-mss"), |
Matt Wagantall | e6e00d5 | 2012-03-08 17:39:07 -0800 | [diff] [blame] | 4968 | CLK_LOOKUP("xo", cxo_clk_src.c, "pil-mba"), |
Tianyi Gou | 4307d6c | 2012-05-31 18:36:07 -0700 | [diff] [blame] | 4969 | CLK_LOOKUP("xo", cxo_clk_src.c, "pil_pronto"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4970 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
| 4971 | |
| 4972 | CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"), |
Stepan Moskovchenko | f97dede7 | 2012-08-08 17:40:44 -0700 | [diff] [blame] | 4973 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"), |
Amy Maloche | bc7e967 | 2012-08-15 10:30:40 -0700 | [diff] [blame] | 4974 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9924000.i2c"), |
Stepan Moskovchenko | 5269b60 | 2012-08-08 17:57:09 -0700 | [diff] [blame] | 4975 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991e000.serial"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4976 | CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""), |
Vikram Mulukutla | 82da88d | 2012-05-04 11:24:03 -0700 | [diff] [blame] | 4977 | CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, ""), |
Amy Maloche | bc7e967 | 2012-08-15 10:30:40 -0700 | [diff] [blame] | 4978 | CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, "f9924000.i2c"), |
| 4979 | CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4980 | CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, ""), |
| 4981 | CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""), |
| 4982 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""), |
| 4983 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""), |
| 4984 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""), |
| 4985 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""), |
| 4986 | CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""), |
| 4987 | CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""), |
| 4988 | CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""), |
Stepan Moskovchenko | 5269b60 | 2012-08-08 17:57:09 -0700 | [diff] [blame] | 4989 | CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f991e000.serial"), |
Stepan Moskovchenko | f97dede7 | 2012-08-08 17:40:44 -0700 | [diff] [blame] | 4990 | CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 4991 | CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""), |
| 4992 | CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""), |
| 4993 | CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""), |
| 4994 | |
| 4995 | CLK_LOOKUP("iface_clk", gcc_blsp2_ahb_clk.c, "f9966000.i2c"), |
| 4996 | CLK_LOOKUP("iface_clk", gcc_blsp2_ahb_clk.c, "f995e000.serial"), |
| 4997 | CLK_LOOKUP("core_clk", gcc_blsp2_qup1_i2c_apps_clk.c, ""), |
| 4998 | CLK_LOOKUP("core_clk", gcc_blsp2_qup1_spi_apps_clk.c, ""), |
| 4999 | CLK_LOOKUP("core_clk", gcc_blsp2_qup2_i2c_apps_clk.c, ""), |
| 5000 | CLK_LOOKUP("core_clk", gcc_blsp2_qup2_spi_apps_clk.c, ""), |
Vikram Mulukutla | 82da88d | 2012-05-04 11:24:03 -0700 | [diff] [blame] | 5001 | CLK_LOOKUP("core_clk", gcc_blsp2_qup3_i2c_apps_clk.c, ""), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5002 | CLK_LOOKUP("core_clk", gcc_blsp2_qup3_spi_apps_clk.c, ""), |
Vikram Mulukutla | 82da88d | 2012-05-04 11:24:03 -0700 | [diff] [blame] | 5003 | CLK_LOOKUP("core_clk", gcc_blsp2_qup4_i2c_apps_clk.c, "f9966000.i2c"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5004 | CLK_LOOKUP("core_clk", gcc_blsp2_qup4_spi_apps_clk.c, ""), |
| 5005 | CLK_LOOKUP("core_clk", gcc_blsp2_qup5_i2c_apps_clk.c, ""), |
| 5006 | CLK_LOOKUP("core_clk", gcc_blsp2_qup5_spi_apps_clk.c, ""), |
| 5007 | CLK_LOOKUP("core_clk", gcc_blsp2_qup6_i2c_apps_clk.c, ""), |
| 5008 | CLK_LOOKUP("core_clk", gcc_blsp2_qup6_spi_apps_clk.c, ""), |
Vikram Mulukutla | 82da88d | 2012-05-04 11:24:03 -0700 | [diff] [blame] | 5009 | CLK_LOOKUP("core_clk", gcc_blsp2_uart1_apps_clk.c, ""), |
| 5010 | CLK_LOOKUP("core_clk", gcc_blsp2_uart2_apps_clk.c, "f995e000.serial"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5011 | CLK_LOOKUP("core_clk", gcc_blsp2_uart3_apps_clk.c, ""), |
| 5012 | CLK_LOOKUP("core_clk", gcc_blsp2_uart4_apps_clk.c, ""), |
| 5013 | CLK_LOOKUP("core_clk", gcc_blsp2_uart5_apps_clk.c, ""), |
| 5014 | CLK_LOOKUP("core_clk", gcc_blsp2_uart6_apps_clk.c, ""), |
| 5015 | |
| 5016 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, ""), |
| 5017 | CLK_LOOKUP("core_clk", gcc_ce2_clk.c, ""), |
| 5018 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, ""), |
| 5019 | CLK_LOOKUP("iface_clk", gcc_ce2_ahb_clk.c, ""), |
| 5020 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, ""), |
| 5021 | CLK_LOOKUP("bus_clk", gcc_ce2_axi_clk.c, ""), |
| 5022 | |
Mona Hossain | b43e94b | 2012-05-07 08:52:06 -0700 | [diff] [blame] | 5023 | CLK_LOOKUP("core_clk", gcc_ce2_clk.c, "qcedev.0"), |
| 5024 | CLK_LOOKUP("iface_clk", gcc_ce2_ahb_clk.c, "qcedev.0"), |
| 5025 | CLK_LOOKUP("bus_clk", gcc_ce2_axi_clk.c, "qcedev.0"), |
| 5026 | CLK_LOOKUP("core_clk_src", ce2_clk_src.c, "qcedev.0"), |
| 5027 | |
| 5028 | CLK_LOOKUP("core_clk", gcc_ce2_clk.c, "qcrypto.0"), |
| 5029 | CLK_LOOKUP("iface_clk", gcc_ce2_ahb_clk.c, "qcrypto.0"), |
| 5030 | CLK_LOOKUP("bus_clk", gcc_ce2_axi_clk.c, "qcrypto.0"), |
| 5031 | CLK_LOOKUP("core_clk_src", ce2_clk_src.c, "qcrypto.0"), |
| 5032 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5033 | CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""), |
| 5034 | CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""), |
| 5035 | CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""), |
| 5036 | |
| 5037 | CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""), |
| 5038 | CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""), |
| 5039 | CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""), |
| 5040 | |
| 5041 | CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"), |
| 5042 | CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"), |
Sujit Reddy Thumma | 5024749 | 2012-06-18 09:39:36 +0530 | [diff] [blame] | 5043 | CLK_LOOKUP("bus_clk", pnoc_sdcc1_clk.c, "msm_sdcc.1"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5044 | CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"), |
| 5045 | CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"), |
Sujit Reddy Thumma | 5024749 | 2012-06-18 09:39:36 +0530 | [diff] [blame] | 5046 | CLK_LOOKUP("bus_clk", pnoc_sdcc2_clk.c, "msm_sdcc.2"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5047 | CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"), |
| 5048 | CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"), |
Sujit Reddy Thumma | 5024749 | 2012-06-18 09:39:36 +0530 | [diff] [blame] | 5049 | CLK_LOOKUP("bus_clk", pnoc_sdcc3_clk.c, "msm_sdcc.3"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5050 | CLK_LOOKUP("iface_clk", gcc_sdcc4_ahb_clk.c, "msm_sdcc.4"), |
| 5051 | CLK_LOOKUP("core_clk", gcc_sdcc4_apps_clk.c, "msm_sdcc.4"), |
Sujit Reddy Thumma | 5024749 | 2012-06-18 09:39:36 +0530 | [diff] [blame] | 5052 | CLK_LOOKUP("bus_clk", pnoc_sdcc4_clk.c, "msm_sdcc.4"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5053 | |
| 5054 | CLK_LOOKUP("iface_clk", gcc_tsif_ahb_clk.c, ""), |
| 5055 | CLK_LOOKUP("ref_clk", gcc_tsif_ref_clk.c, ""), |
| 5056 | |
Manu Gautam | 1fd82ac | 2012-08-22 10:27:36 -0700 | [diff] [blame] | 5057 | CLK_LOOKUP("mem_clk", gcc_usb30_master_clk.c, "usb_bam"), |
| 5058 | CLK_LOOKUP("mem_iface_clk", gcc_sys_noc_usb3_axi_clk.c, "usb_bam"), |
Manu Gautam | 51be971 | 2012-06-06 14:54:52 +0530 | [diff] [blame] | 5059 | CLK_LOOKUP("core_clk", gcc_usb30_master_clk.c, "msm_dwc3"), |
| 5060 | CLK_LOOKUP("utmi_clk", gcc_usb30_mock_utmi_clk.c, "msm_dwc3"), |
Vikram Mulukutla | 3b98a6d | 2012-08-15 20:35:25 -0700 | [diff] [blame] | 5061 | CLK_LOOKUP("iface_clk", gcc_sys_noc_usb3_axi_clk.c, "msm_dwc3"), |
| 5062 | CLK_LOOKUP("sleep_clk", gcc_usb30_sleep_clk.c, "msm_dwc3"), |
| 5063 | CLK_LOOKUP("sleep_a_clk", gcc_usb2a_phy_sleep_clk.c, "msm_dwc3"), |
| 5064 | CLK_LOOKUP("sleep_b_clk", gcc_usb2b_phy_sleep_clk.c, "msm_dwc3"), |
Manu Gautam | 51be971 | 2012-06-06 14:54:52 +0530 | [diff] [blame] | 5065 | CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_otg"), |
| 5066 | CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_otg"), |
| 5067 | CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"), |
| 5068 | CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"), |
| 5069 | CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"), |
| 5070 | CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5071 | |
| 5072 | /* Multimedia clocks */ |
| 5073 | CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5074 | CLK_LOOKUP("bus_clk", mmss_mmssnoc_axi_clk.c, ""), |
| 5075 | CLK_LOOKUP("core_clk", mdss_edpaux_clk.c, ""), |
| 5076 | CLK_LOOKUP("core_clk", mdss_edppixel_clk.c, ""), |
Chandan Uddaraju | 19203fa | 2012-07-31 00:28:02 -0700 | [diff] [blame] | 5077 | CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"), |
| 5078 | CLK_LOOKUP("byte_clk", mdss_byte1_clk.c, ""), |
| 5079 | CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5080 | CLK_LOOKUP("core_clk", mdss_esc1_clk.c, ""), |
Chandan Uddaraju | 09adf32 | 2012-08-16 02:55:23 -0700 | [diff] [blame] | 5081 | CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"), |
| 5082 | CLK_LOOKUP("pixel_clk", mdss_pclk1_clk.c, ""), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5083 | CLK_LOOKUP("iface_clk", mdss_hdmi_ahb_clk.c, ""), |
| 5084 | CLK_LOOKUP("core_clk", mdss_hdmi_clk.c, ""), |
Adrian Salido-Moreno | 5ef3ac0 | 2012-05-14 18:40:47 -0700 | [diff] [blame] | 5085 | CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "mdp.0"), |
| 5086 | CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "mdp.0"), |
| 5087 | CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "mdp.0"), |
| 5088 | CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "mdp.0"), |
Kevin Chan | b4b5f86 | 2012-08-23 14:34:33 -0700 | [diff] [blame] | 5089 | |
| 5090 | /* MM sensor clocks */ |
| 5091 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6e.qcom,s5k3l1yx"), |
| 5092 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6c.qcom,ov2720"), |
| 5093 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6e.qcom,s5k3l1yx"), |
| 5094 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6c.qcom,ov2720"), |
| 5095 | CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, ""), |
| 5096 | CLK_LOOKUP("cam_clk", camss_mclk2_clk.c, ""), |
| 5097 | CLK_LOOKUP("cam_clk", camss_mclk3_clk.c, ""), |
| 5098 | CLK_LOOKUP("cam_gp0_src_clk", mmss_gp0_clk_src.c, ""), |
| 5099 | CLK_LOOKUP("cam_gp1_src_clk", mmss_gp1_clk_src.c, ""), |
| 5100 | CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""), |
| 5101 | CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""), |
| 5102 | /* CCI clocks */ |
| 5103 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 5104 | "fda0c000.qcom,cci"), |
| 5105 | CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c, "fda0c000.qcom,cci"), |
| 5106 | CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"), |
| 5107 | CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"), |
| 5108 | /* CSIPHY clocks */ |
| 5109 | CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c, |
| 5110 | "fda0ac00.qcom,csiphy"), |
| 5111 | CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c, |
| 5112 | "fda0ac00.qcom,csiphy"), |
| 5113 | CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c, |
| 5114 | "fda0ac00.qcom,csiphy"), |
| 5115 | CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c, |
| 5116 | "fda0b000.qcom,csiphy"), |
| 5117 | CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c, |
| 5118 | "fda0b000.qcom,csiphy"), |
| 5119 | CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c, |
| 5120 | "fda0b000.qcom,csiphy"), |
| 5121 | CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c, |
| 5122 | "fda0b400.qcom,csiphy"), |
| 5123 | CLK_LOOKUP("csiphy_timer_src_clk", csi2phytimer_clk_src.c, |
| 5124 | "fda0b400.qcom,csiphy"), |
| 5125 | CLK_LOOKUP("csiphy_timer_clk", camss_phy2_csi2phytimer_clk.c, |
| 5126 | "fda0b400.qcom,csiphy"), |
| 5127 | /* CSID clocks */ |
| 5128 | CLK_LOOKUP("csi_ahb_clk", camss_csi0_ahb_clk.c, "fda08000.qcom,csid"), |
| 5129 | CLK_LOOKUP("csi_src_clk", csi0_clk_src.c, "fda08000.qcom,csid"), |
| 5130 | CLK_LOOKUP("csi_phy_clk", camss_csi0phy_clk.c, "fda08000.qcom,csid"), |
| 5131 | CLK_LOOKUP("csi_clk", camss_csi0_clk.c, "fda08000.qcom,csid"), |
Kevin Chan | bdcf7ef | 2012-08-24 08:33:33 -0700 | [diff] [blame] | 5132 | CLK_LOOKUP("csi_pix_clk", camss_csi0pix_clk.c, "fda08000.qcom,csid"), |
| 5133 | CLK_LOOKUP("csi_rdi_clk", camss_csi0rdi_clk.c, "fda08000.qcom,csid"), |
Kevin Chan | b4b5f86 | 2012-08-23 14:34:33 -0700 | [diff] [blame] | 5134 | CLK_LOOKUP("csi_ahb_clk", camss_csi1_ahb_clk.c, "fda08400.qcom,csid"), |
| 5135 | CLK_LOOKUP("csi_src_clk", csi1_clk_src.c, "fda08400.qcom,csid"), |
| 5136 | CLK_LOOKUP("csi_phy_clk", camss_csi1phy_clk.c, "fda08400.qcom,csid"), |
| 5137 | CLK_LOOKUP("csi_clk", camss_csi1_clk.c, "fda08400.qcom,csid"), |
Kevin Chan | bdcf7ef | 2012-08-24 08:33:33 -0700 | [diff] [blame] | 5138 | CLK_LOOKUP("csi_pix_clk", camss_csi1pix_clk.c, "fda08400.qcom,csid"), |
| 5139 | CLK_LOOKUP("csi_rdi_clk", camss_csi1rdi_clk.c, "fda08400.qcom,csid"), |
Kevin Chan | b4b5f86 | 2012-08-23 14:34:33 -0700 | [diff] [blame] | 5140 | CLK_LOOKUP("csi_ahb_clk", camss_csi2_ahb_clk.c, "fda08800.qcom,csid"), |
| 5141 | CLK_LOOKUP("csi_src_clk", csi2_clk_src.c, "fda08800.qcom,csid"), |
| 5142 | CLK_LOOKUP("csi_phy_clk", camss_csi2phy_clk.c, "fda08800.qcom,csid"), |
| 5143 | CLK_LOOKUP("csi_clk", camss_csi2_clk.c, "fda08800.qcom,csid"), |
Kevin Chan | bdcf7ef | 2012-08-24 08:33:33 -0700 | [diff] [blame] | 5144 | CLK_LOOKUP("csi_pix_clk", camss_csi2pix_clk.c, "fda08800.qcom,csid"), |
| 5145 | CLK_LOOKUP("csi_rdi_clk", camss_csi2rdi_clk.c, "fda08800.qcom,csid"), |
Kevin Chan | b4b5f86 | 2012-08-23 14:34:33 -0700 | [diff] [blame] | 5146 | CLK_LOOKUP("csi_ahb_clk", camss_csi3_ahb_clk.c, "fda08c00.qcom,csid"), |
| 5147 | CLK_LOOKUP("csi_src_clk", csi3_clk_src.c, "fda08c00.qcom,csid"), |
| 5148 | CLK_LOOKUP("csi_phy_clk", camss_csi3phy_clk.c, "fda08c00.qcom,csid"), |
| 5149 | CLK_LOOKUP("csi_clk", camss_csi3_clk.c, "fda08c00.qcom,csid"), |
Kevin Chan | bdcf7ef | 2012-08-24 08:33:33 -0700 | [diff] [blame] | 5150 | CLK_LOOKUP("csi_pix_clk", camss_csi3pix_clk.c, "fda08c00.qcom,csid"), |
| 5151 | CLK_LOOKUP("csi_rdi_clk", camss_csi3rdi_clk.c, "fda08c00.qcom,csid"), |
Kevin Chan | b4b5f86 | 2012-08-23 14:34:33 -0700 | [diff] [blame] | 5152 | /*VFE clocks*/ |
| 5153 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 5154 | "fda10000.qcom,vfe"), |
| 5155 | CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"), |
| 5156 | CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c, |
| 5157 | "fda10000.qcom,vfe"), |
| 5158 | CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c, |
| 5159 | "fda10000.qcom,vfe"), |
| 5160 | CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"), |
| 5161 | CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"), |
| 5162 | CLK_LOOKUP("alt_bus_clk", camss_vfe_vfe_ocmemnoc_clk.c, |
| 5163 | "fda10000.qcom,vfe"), |
| 5164 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 5165 | "fda14000.qcom,vfe"), |
| 5166 | CLK_LOOKUP("vfe_clk_src", vfe1_clk_src.c, "fda14000.qcom,vfe"), |
| 5167 | CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe1_clk.c, |
| 5168 | "fda14000.qcom,vfe"), |
| 5169 | CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe1_clk.c, |
| 5170 | "fda14000.qcom,vfe"), |
| 5171 | CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda14000.qcom,vfe"), |
| 5172 | CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda14000.qcom,vfe"), |
| 5173 | CLK_LOOKUP("alt_bus_clk", camss_vfe_vfe_ocmemnoc_clk.c, |
| 5174 | "fda14000.qcom,vfe"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5175 | CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, ""), |
| 5176 | CLK_LOOKUP("core_clk", camss_jpeg_jpeg1_clk.c, ""), |
| 5177 | CLK_LOOKUP("core_clk", camss_jpeg_jpeg2_clk.c, ""), |
Sathish Ambley | d1b89ed | 2012-02-07 21:47:47 -0800 | [diff] [blame] | 5178 | CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c, |
| 5179 | "fda64000.qcom,iommu"), |
| 5180 | CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c, |
| 5181 | "fda64000.qcom,iommu"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5182 | CLK_LOOKUP("bus_clk", camss_jpeg_jpeg_axi_clk.c, ""), |
| 5183 | CLK_LOOKUP("bus_clk", camss_jpeg_jpeg_ocmemnoc_clk.c, ""), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5184 | CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5185 | CLK_LOOKUP("iface_clk", camss_top_ahb_clk.c, ""), |
Stepan Moskovchenko | 372cfb4 | 2012-07-10 20:19:11 -0700 | [diff] [blame] | 5186 | CLK_LOOKUP("iface_clk", camss_vfe_cpp_ahb_clk.c, "fda44000.qcom,iommu"), |
| 5187 | CLK_LOOKUP("core_clk", camss_vfe_cpp_clk.c, "fda44000.qcom,iommu"), |
Adrian Salido-Moreno | 5ef3ac0 | 2012-05-14 18:40:47 -0700 | [diff] [blame] | 5188 | CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "mdp.0"), |
Chandan Uddaraju | 09adf32 | 2012-08-16 02:55:23 -0700 | [diff] [blame] | 5189 | CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "mdss_dsi_clk_ctrl"), |
Sathish Ambley | d1b89ed | 2012-02-07 21:47:47 -0800 | [diff] [blame] | 5190 | CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"), |
| 5191 | CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"), |
Adrian Salido-Moreno | 5ef3ac0 | 2012-05-14 18:40:47 -0700 | [diff] [blame] | 5192 | CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "mdp.0"), |
Vikram Mulukutla | e3b0306 | 2012-05-16 12:07:08 -0700 | [diff] [blame] | 5193 | CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"), |
| 5194 | CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"), |
Vikram Mulukutla | 274b2d9 | 2012-07-13 15:53:04 -0700 | [diff] [blame] | 5195 | CLK_LOOKUP("mem_iface_clk", ocmemcx_ocmemnoc_clk.c, |
| 5196 | "fdb00000.qcom,kgsl-3d0"), |
Vikram Mulukutla | e3b0306 | 2012-05-16 12:07:08 -0700 | [diff] [blame] | 5197 | CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"), |
| 5198 | CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"), |
Stepan Moskovchenko | b26b8ca | 2012-07-24 19:42:44 -0700 | [diff] [blame] | 5199 | CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"), |
Naveen Ramaraj | bea2d5d | 2012-08-15 17:26:43 -0700 | [diff] [blame] | 5200 | CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"), |
| 5201 | CLK_LOOKUP("iface_clk", ocmemcx_ocmemnoc_clk.c, "fdd00000.qcom,ocmem"), |
Sathish Ambley | d1b89ed | 2012-02-07 21:47:47 -0800 | [diff] [blame] | 5202 | CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"), |
Stepan Moskovchenko | b26b8ca | 2012-07-24 19:42:44 -0700 | [diff] [blame] | 5203 | CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c, "fdc84000.qcom,iommu"), |
Sathish Ambley | d1b89ed | 2012-02-07 21:47:47 -0800 | [diff] [blame] | 5204 | CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"), |
| 5205 | CLK_LOOKUP("bus_clk", venus0_axi_clk.c, ""), |
Tianyi Gou | 828798d | 2012-05-02 21:12:38 -0700 | [diff] [blame] | 5206 | CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"), |
| 5207 | CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"), |
| 5208 | CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"), |
| 5209 | CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"), |
| 5210 | CLK_LOOKUP("mem_clk", venus0_ocmemnoc_clk.c, "fdce0000.qcom,venus"), |
Vinay Kalia | 40680aa | 2012-07-23 12:45:39 -0700 | [diff] [blame] | 5211 | CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"), |
| 5212 | CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"), |
| 5213 | CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"), |
| 5214 | CLK_LOOKUP("mem_clk", venus0_ocmemnoc_clk.c, "fdc00000.qcom,vidc"), |
Tianyi Gou | 828798d | 2012-05-02 21:12:38 -0700 | [diff] [blame] | 5215 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5216 | |
| 5217 | /* LPASS clocks */ |
Vikram Mulukutla | 6c0f1a7 | 2012-08-10 01:59:28 -0700 | [diff] [blame] | 5218 | CLK_LOOKUP("bus_clk", audio_core_ixfabric_clk.c, ""), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5219 | CLK_LOOKUP("core_clk", audio_core_slimbus_core_clk.c, "fe12f000.slim"), |
| 5220 | CLK_LOOKUP("iface_clk", audio_core_slimbus_lfabif_clk.c, |
| 5221 | "fe12f000.slim"), |
| 5222 | CLK_LOOKUP("core_clk", audio_core_lpaif_codec_spkr_clk_src.c, ""), |
| 5223 | CLK_LOOKUP("osr_clk", audio_core_lpaif_codec_spkr_osr_clk.c, ""), |
| 5224 | CLK_LOOKUP("ebit_clk", audio_core_lpaif_codec_spkr_ebit_clk.c, ""), |
| 5225 | CLK_LOOKUP("ibit_clk", audio_core_lpaif_codec_spkr_ibit_clk.c, ""), |
| 5226 | CLK_LOOKUP("core_clk", audio_core_lpaif_pri_clk_src.c, ""), |
| 5227 | CLK_LOOKUP("osr_clk", audio_core_lpaif_pri_osr_clk.c, ""), |
| 5228 | CLK_LOOKUP("ebit_clk", audio_core_lpaif_pri_ebit_clk.c, ""), |
| 5229 | CLK_LOOKUP("ibit_clk", audio_core_lpaif_pri_ibit_clk.c, ""), |
| 5230 | CLK_LOOKUP("core_clk", audio_core_lpaif_sec_clk_src.c, ""), |
| 5231 | CLK_LOOKUP("osr_clk", audio_core_lpaif_sec_osr_clk.c, ""), |
| 5232 | CLK_LOOKUP("ebit_clk", audio_core_lpaif_sec_ebit_clk.c, ""), |
| 5233 | CLK_LOOKUP("ibit_clk", audio_core_lpaif_sec_ibit_clk.c, ""), |
| 5234 | CLK_LOOKUP("core_clk", audio_core_lpaif_ter_clk_src.c, ""), |
| 5235 | CLK_LOOKUP("osr_clk", audio_core_lpaif_ter_osr_clk.c, ""), |
| 5236 | CLK_LOOKUP("ebit_clk", audio_core_lpaif_ter_ebit_clk.c, ""), |
| 5237 | CLK_LOOKUP("ibit_clk", audio_core_lpaif_ter_ibit_clk.c, ""), |
| 5238 | CLK_LOOKUP("core_clk", audio_core_lpaif_quad_clk_src.c, ""), |
| 5239 | CLK_LOOKUP("osr_clk", audio_core_lpaif_quad_osr_clk.c, ""), |
| 5240 | CLK_LOOKUP("ebit_clk", audio_core_lpaif_quad_ebit_clk.c, ""), |
| 5241 | CLK_LOOKUP("ibit_clk", audio_core_lpaif_quad_ibit_clk.c, ""), |
Phani Kumar Uppalapati | 978f18d | 2012-08-08 15:49:39 -0700 | [diff] [blame] | 5242 | CLK_LOOKUP("pcm_clk", audio_core_lpaif_pcm0_clk_src.c, |
Phani Kumar Uppalapati | 7474f3d | 2012-07-19 18:54:53 -0700 | [diff] [blame] | 5243 | "msm-dai-q6.4106"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5244 | CLK_LOOKUP("ebit_clk", audio_core_lpaif_pcm0_ebit_clk.c, ""), |
Phani Kumar Uppalapati | 7474f3d | 2012-07-19 18:54:53 -0700 | [diff] [blame] | 5245 | CLK_LOOKUP("ibit_clk", audio_core_lpaif_pcm0_ibit_clk.c, |
| 5246 | "msm-dai-q6.4106"), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5247 | CLK_LOOKUP("ibit_clk", audio_core_lpaif_pcm0_ibit_clk.c, ""), |
| 5248 | CLK_LOOKUP("core_clk", audio_core_lpaif_pcm1_clk_src.c, ""), |
| 5249 | CLK_LOOKUP("ebit_clk", audio_core_lpaif_pcm1_ebit_clk.c, ""), |
| 5250 | CLK_LOOKUP("ibit_clk", audio_core_lpaif_pcm1_ibit_clk.c, ""), |
Phani Kumar Uppalapati | 7474f3d | 2012-07-19 18:54:53 -0700 | [diff] [blame] | 5251 | CLK_LOOKUP("core_oe_src_clk", audio_core_lpaif_pcmoe_clk_src.c, |
| 5252 | "msm-dai-q6.4106"), |
| 5253 | CLK_LOOKUP("core_oe_clk", audio_core_lpaif_pcmoe_clk.c, |
| 5254 | "msm-dai-q6.4106"), |
Vikram Mulukutla | 97ac334 | 2012-08-21 12:55:13 -0700 | [diff] [blame^] | 5255 | CLK_LOOKUP("br_clk", audio_wrapper_br_clk.c, "fdd00000.qcom,ocmem"), |
Matt Wagantall | b2c78be | 2012-08-11 18:55:45 -0700 | [diff] [blame] | 5256 | CLK_LOOKUP("core_clk", mss_xo_q6_clk.c, "pil-q6v5-mss"), |
Matt Wagantall | 8c2246d | 2012-08-12 17:08:04 -0700 | [diff] [blame] | 5257 | CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "pil-q6v5-mss"), |
Matt Wagantall | b2c78be | 2012-08-11 18:55:45 -0700 | [diff] [blame] | 5258 | CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "pil-q6v5-mss"), |
Matt Wagantall | 8c2246d | 2012-08-12 17:08:04 -0700 | [diff] [blame] | 5259 | CLK_LOOKUP("reg_clk", mss_bus_q6_clk.c, "pil-q6v5-mss"), |
Matt Wagantall | b2c78be | 2012-08-11 18:55:45 -0700 | [diff] [blame] | 5260 | CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "pil-q6v5-mss"), |
Vikram Mulukutla | 31926eb | 2012-08-12 19:58:08 -0700 | [diff] [blame] | 5261 | |
Matt Wagantall | b2c78be | 2012-08-11 18:55:45 -0700 | [diff] [blame] | 5262 | CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "pil-q6v5-lpass"), |
| 5263 | CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "pil-q6v5-lpass"), |
| 5264 | CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "pil-q6v5-lpass"), |
| 5265 | CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "pil-q6v5-lpass"), |
Hariprasad Dhalinarasimha | de991f0 | 2012-05-31 13:15:51 -0700 | [diff] [blame] | 5266 | CLK_LOOKUP("core_clk", gcc_prng_ahb_clk.c, "msm_rng"), |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 5267 | |
Vikram Mulukutla | b0ad9f3 | 2012-07-03 12:57:24 -0700 | [diff] [blame] | 5268 | CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"), |
| 5269 | CLK_LOOKUP("bus_clk", pnoc_qseecom_clk.c, "qseecom"), |
Vikram Mulukutla | d08a152 | 2012-05-24 15:24:01 -0700 | [diff] [blame] | 5270 | |
| 5271 | CLK_LOOKUP("bus_clk", snoc_clk.c, ""), |
| 5272 | CLK_LOOKUP("bus_clk", pnoc_clk.c, ""), |
| 5273 | CLK_LOOKUP("bus_clk", cnoc_clk.c, ""), |
| 5274 | CLK_LOOKUP("mem_clk", bimc_clk.c, ""), |
| 5275 | CLK_LOOKUP("mem_clk", ocmemgx_clk.c, ""), |
| 5276 | CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""), |
| 5277 | CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""), |
| 5278 | CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""), |
| 5279 | CLK_LOOKUP("mem_clk", bimc_a_clk.c, ""), |
| 5280 | CLK_LOOKUP("mem_clk", ocmemgx_a_clk.c, ""), |
| 5281 | |
| 5282 | CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"), |
| 5283 | CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"), |
| 5284 | CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"), |
| 5285 | CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"), |
| 5286 | CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"), |
| 5287 | CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"), |
| 5288 | CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"), |
| 5289 | CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"), |
| 5290 | CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""), |
| 5291 | CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"), |
| 5292 | CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"), |
| 5293 | CLK_LOOKUP("bus_clk", ocmemnoc_clk.c, "msm_ocmem_noc"), |
| 5294 | CLK_LOOKUP("bus_a_clk", ocmemnoc_clk.c, "msm_ocmem_noc"), |
Vikram Mulukutla | c15dac0 | 2012-08-09 13:31:08 -0700 | [diff] [blame] | 5295 | CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"), |
| 5296 | CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"), |
Vikram Mulukutla | 274b2d9 | 2012-07-13 15:53:04 -0700 | [diff] [blame] | 5297 | CLK_LOOKUP("iface_clk", gcc_mmss_noc_cfg_ahb_clk.c, ""), |
| 5298 | CLK_LOOKUP("iface_clk", gcc_ocmem_noc_cfg_ahb_clk.c, ""), |
Vikram Mulukutla | 0f63e00 | 2012-06-28 14:29:44 -0700 | [diff] [blame] | 5299 | |
| 5300 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tmc-etr"), |
| 5301 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tpiu"), |
| 5302 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-replicator"), |
| 5303 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tmc-etf"), |
| 5304 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-merg"), |
| 5305 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-in0"), |
| 5306 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-in1"), |
| 5307 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-kpss"), |
| 5308 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-mmss"), |
| 5309 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-stm"), |
| 5310 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm0"), |
| 5311 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm1"), |
| 5312 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm2"), |
| 5313 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm3"), |
| 5314 | |
| 5315 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tmc-etr"), |
| 5316 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tpiu"), |
| 5317 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-replicator"), |
| 5318 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tmc-etf"), |
| 5319 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-merg"), |
| 5320 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-in0"), |
| 5321 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-in1"), |
| 5322 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-kpss"), |
| 5323 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-mmss"), |
| 5324 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-stm"), |
| 5325 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm0"), |
| 5326 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm1"), |
| 5327 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm2"), |
| 5328 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm3"), |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 5329 | |
| 5330 | CLK_LOOKUP("l2_m_clk", l2_m_clk, ""), |
| 5331 | CLK_LOOKUP("krait0_m_clk", krait0_m_clk, ""), |
| 5332 | CLK_LOOKUP("krait1_m_clk", krait1_m_clk, ""), |
| 5333 | CLK_LOOKUP("krait2_m_clk", krait2_m_clk, ""), |
| 5334 | CLK_LOOKUP("krait3_m_clk", krait3_m_clk, ""), |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5335 | }; |
| 5336 | |
| 5337 | static struct pll_config_regs gpll0_regs __initdata = { |
| 5338 | .l_reg = (void __iomem *)GPLL0_L_REG, |
| 5339 | .m_reg = (void __iomem *)GPLL0_M_REG, |
| 5340 | .n_reg = (void __iomem *)GPLL0_N_REG, |
| 5341 | .config_reg = (void __iomem *)GPLL0_USER_CTL_REG, |
| 5342 | .mode_reg = (void __iomem *)GPLL0_MODE_REG, |
| 5343 | .base = &virt_bases[GCC_BASE], |
| 5344 | }; |
| 5345 | |
| 5346 | /* GPLL0 at 600 MHz, main output enabled. */ |
| 5347 | static struct pll_config gpll0_config __initdata = { |
| 5348 | .l = 0x1f, |
| 5349 | .m = 0x1, |
| 5350 | .n = 0x4, |
| 5351 | .vco_val = 0x0, |
| 5352 | .vco_mask = BM(21, 20), |
| 5353 | .pre_div_val = 0x0, |
| 5354 | .pre_div_mask = BM(14, 12), |
| 5355 | .post_div_val = 0x0, |
| 5356 | .post_div_mask = BM(9, 8), |
| 5357 | .mn_ena_val = BIT(24), |
| 5358 | .mn_ena_mask = BIT(24), |
| 5359 | .main_output_val = BIT(0), |
| 5360 | .main_output_mask = BIT(0), |
| 5361 | }; |
| 5362 | |
| 5363 | static struct pll_config_regs gpll1_regs __initdata = { |
| 5364 | .l_reg = (void __iomem *)GPLL1_L_REG, |
| 5365 | .m_reg = (void __iomem *)GPLL1_M_REG, |
| 5366 | .n_reg = (void __iomem *)GPLL1_N_REG, |
| 5367 | .config_reg = (void __iomem *)GPLL1_USER_CTL_REG, |
| 5368 | .mode_reg = (void __iomem *)GPLL1_MODE_REG, |
| 5369 | .base = &virt_bases[GCC_BASE], |
| 5370 | }; |
| 5371 | |
| 5372 | /* GPLL1 at 480 MHz, main output enabled. */ |
| 5373 | static struct pll_config gpll1_config __initdata = { |
| 5374 | .l = 0x19, |
| 5375 | .m = 0x0, |
| 5376 | .n = 0x1, |
| 5377 | .vco_val = 0x0, |
| 5378 | .vco_mask = BM(21, 20), |
| 5379 | .pre_div_val = 0x0, |
| 5380 | .pre_div_mask = BM(14, 12), |
| 5381 | .post_div_val = 0x0, |
| 5382 | .post_div_mask = BM(9, 8), |
| 5383 | .main_output_val = BIT(0), |
| 5384 | .main_output_mask = BIT(0), |
| 5385 | }; |
| 5386 | |
| 5387 | static struct pll_config_regs mmpll0_regs __initdata = { |
| 5388 | .l_reg = (void __iomem *)MMPLL0_L_REG, |
| 5389 | .m_reg = (void __iomem *)MMPLL0_M_REG, |
| 5390 | .n_reg = (void __iomem *)MMPLL0_N_REG, |
| 5391 | .config_reg = (void __iomem *)MMPLL0_USER_CTL_REG, |
| 5392 | .mode_reg = (void __iomem *)MMPLL0_MODE_REG, |
| 5393 | .base = &virt_bases[MMSS_BASE], |
| 5394 | }; |
| 5395 | |
| 5396 | /* MMPLL0 at 800 MHz, main output enabled. */ |
| 5397 | static struct pll_config mmpll0_config __initdata = { |
| 5398 | .l = 0x29, |
| 5399 | .m = 0x2, |
| 5400 | .n = 0x3, |
| 5401 | .vco_val = 0x0, |
| 5402 | .vco_mask = BM(21, 20), |
| 5403 | .pre_div_val = 0x0, |
| 5404 | .pre_div_mask = BM(14, 12), |
| 5405 | .post_div_val = 0x0, |
| 5406 | .post_div_mask = BM(9, 8), |
| 5407 | .mn_ena_val = BIT(24), |
| 5408 | .mn_ena_mask = BIT(24), |
| 5409 | .main_output_val = BIT(0), |
| 5410 | .main_output_mask = BIT(0), |
| 5411 | }; |
| 5412 | |
| 5413 | static struct pll_config_regs mmpll1_regs __initdata = { |
| 5414 | .l_reg = (void __iomem *)MMPLL1_L_REG, |
| 5415 | .m_reg = (void __iomem *)MMPLL1_M_REG, |
| 5416 | .n_reg = (void __iomem *)MMPLL1_N_REG, |
| 5417 | .config_reg = (void __iomem *)MMPLL1_USER_CTL_REG, |
| 5418 | .mode_reg = (void __iomem *)MMPLL1_MODE_REG, |
| 5419 | .base = &virt_bases[MMSS_BASE], |
| 5420 | }; |
| 5421 | |
| 5422 | /* MMPLL1 at 1000 MHz, main output enabled. */ |
| 5423 | static struct pll_config mmpll1_config __initdata = { |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 5424 | .l = 0x2C, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5425 | .m = 0x1, |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 5426 | .n = 0x10, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5427 | .vco_val = 0x0, |
| 5428 | .vco_mask = BM(21, 20), |
| 5429 | .pre_div_val = 0x0, |
| 5430 | .pre_div_mask = BM(14, 12), |
| 5431 | .post_div_val = 0x0, |
| 5432 | .post_div_mask = BM(9, 8), |
| 5433 | .mn_ena_val = BIT(24), |
| 5434 | .mn_ena_mask = BIT(24), |
| 5435 | .main_output_val = BIT(0), |
| 5436 | .main_output_mask = BIT(0), |
| 5437 | }; |
| 5438 | |
| 5439 | static struct pll_config_regs mmpll3_regs __initdata = { |
| 5440 | .l_reg = (void __iomem *)MMPLL3_L_REG, |
| 5441 | .m_reg = (void __iomem *)MMPLL3_M_REG, |
| 5442 | .n_reg = (void __iomem *)MMPLL3_N_REG, |
| 5443 | .config_reg = (void __iomem *)MMPLL3_USER_CTL_REG, |
| 5444 | .mode_reg = (void __iomem *)MMPLL3_MODE_REG, |
| 5445 | .base = &virt_bases[MMSS_BASE], |
| 5446 | }; |
| 5447 | |
| 5448 | /* MMPLL3 at 820 MHz, main output enabled. */ |
| 5449 | static struct pll_config mmpll3_config __initdata = { |
| 5450 | .l = 0x2A, |
| 5451 | .m = 0x11, |
| 5452 | .n = 0x18, |
| 5453 | .vco_val = 0x0, |
| 5454 | .vco_mask = BM(21, 20), |
| 5455 | .pre_div_val = 0x0, |
| 5456 | .pre_div_mask = BM(14, 12), |
| 5457 | .post_div_val = 0x0, |
| 5458 | .post_div_mask = BM(9, 8), |
| 5459 | .mn_ena_val = BIT(24), |
| 5460 | .mn_ena_mask = BIT(24), |
| 5461 | .main_output_val = BIT(0), |
| 5462 | .main_output_mask = BIT(0), |
| 5463 | }; |
| 5464 | |
| 5465 | static struct pll_config_regs lpapll0_regs __initdata = { |
| 5466 | .l_reg = (void __iomem *)LPAPLL_L_REG, |
| 5467 | .m_reg = (void __iomem *)LPAPLL_M_REG, |
| 5468 | .n_reg = (void __iomem *)LPAPLL_N_REG, |
| 5469 | .config_reg = (void __iomem *)LPAPLL_USER_CTL_REG, |
| 5470 | .mode_reg = (void __iomem *)LPAPLL_MODE_REG, |
| 5471 | .base = &virt_bases[LPASS_BASE], |
| 5472 | }; |
| 5473 | |
| 5474 | /* LPAPLL0 at 491.52 MHz, main output enabled. */ |
| 5475 | static struct pll_config lpapll0_config __initdata = { |
| 5476 | .l = 0x33, |
| 5477 | .m = 0x1, |
| 5478 | .n = 0x5, |
| 5479 | .vco_val = 0x0, |
| 5480 | .vco_mask = BM(21, 20), |
| 5481 | .pre_div_val = BVAL(14, 12, 0x1), |
| 5482 | .pre_div_mask = BM(14, 12), |
| 5483 | .post_div_val = 0x0, |
| 5484 | .post_div_mask = BM(9, 8), |
| 5485 | .mn_ena_val = BIT(24), |
| 5486 | .mn_ena_mask = BIT(24), |
| 5487 | .main_output_val = BIT(0), |
| 5488 | .main_output_mask = BIT(0), |
| 5489 | }; |
| 5490 | |
Matt Wagantall | 8c55d7e | 2012-07-17 19:46:32 -0700 | [diff] [blame] | 5491 | #define PLL_AUX_OUTPUT_BIT 1 |
Matt Wagantall | e750237 | 2012-08-08 00:10:10 -0700 | [diff] [blame] | 5492 | #define PLL_AUX2_OUTPUT_BIT 2 |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5493 | |
Vikram Mulukutla | 14ee37d | 2012-08-08 15:18:09 -0700 | [diff] [blame] | 5494 | #define PWR_ON_MASK BIT(31) |
| 5495 | #define EN_REST_WAIT_MASK (0xF << 20) |
| 5496 | #define EN_FEW_WAIT_MASK (0xF << 16) |
| 5497 | #define CLK_DIS_WAIT_MASK (0xF << 12) |
| 5498 | #define SW_OVERRIDE_MASK BIT(2) |
| 5499 | #define HW_CONTROL_MASK BIT(1) |
| 5500 | #define SW_COLLAPSE_MASK BIT(0) |
| 5501 | |
| 5502 | /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ |
| 5503 | #define EN_REST_WAIT_VAL (0x2 << 20) |
| 5504 | #define EN_FEW_WAIT_VAL (0x2 << 16) |
| 5505 | #define CLK_DIS_WAIT_VAL (0x2 << 12) |
| 5506 | #define GDSC_TIMEOUT_US 50000 |
| 5507 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5508 | static void __init reg_init(void) |
| 5509 | { |
Vikram Mulukutla | 14ee37d | 2012-08-08 15:18:09 -0700 | [diff] [blame] | 5510 | u32 regval, status; |
| 5511 | int ret; |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5512 | |
| 5513 | if (!(readl_relaxed(GCC_REG_BASE(GPLL0_STATUS_REG)) |
| 5514 | & gpll0_clk_src.status_mask)) |
| 5515 | configure_pll(&gpll0_config, &gpll0_regs, 1); |
| 5516 | |
| 5517 | if (!(readl_relaxed(GCC_REG_BASE(GPLL1_STATUS_REG)) |
| 5518 | & gpll1_clk_src.status_mask)) |
| 5519 | configure_pll(&gpll1_config, &gpll1_regs, 1); |
| 5520 | |
| 5521 | configure_pll(&mmpll0_config, &mmpll0_regs, 1); |
| 5522 | configure_pll(&mmpll1_config, &mmpll1_regs, 1); |
| 5523 | configure_pll(&mmpll3_config, &mmpll3_regs, 0); |
| 5524 | configure_pll(&lpapll0_config, &lpapll0_regs, 1); |
| 5525 | |
Matt Wagantall | e750237 | 2012-08-08 00:10:10 -0700 | [diff] [blame] | 5526 | /* Enable GPLL0's aux outputs. */ |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5527 | regval = readl_relaxed(GCC_REG_BASE(GPLL0_USER_CTL_REG)); |
Matt Wagantall | e750237 | 2012-08-08 00:10:10 -0700 | [diff] [blame] | 5528 | regval |= BIT(PLL_AUX_OUTPUT_BIT) | BIT(PLL_AUX2_OUTPUT_BIT); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5529 | writel_relaxed(regval, GCC_REG_BASE(GPLL0_USER_CTL_REG)); |
| 5530 | |
| 5531 | /* Vote for GPLL0 to turn on. Needed by acpuclock. */ |
| 5532 | regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE_REG)); |
| 5533 | regval |= BIT(0); |
| 5534 | writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE_REG)); |
| 5535 | |
| 5536 | /* |
| 5537 | * TODO: Confirm that no clocks need to be voted on in this sleep vote |
| 5538 | * register. |
| 5539 | */ |
| 5540 | writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE)); |
Vikram Mulukutla | 14ee37d | 2012-08-08 15:18:09 -0700 | [diff] [blame] | 5541 | |
| 5542 | /* |
| 5543 | * TODO: The following sequence enables the LPASS audio core GDSC. |
| 5544 | * Remove when this becomes unnecessary. |
| 5545 | */ |
| 5546 | |
| 5547 | /* |
| 5548 | * Disable HW trigger: collapse/restore occur based on registers writes. |
| 5549 | * Disable SW override: Use hardware state-machine for sequencing. |
| 5550 | */ |
| 5551 | regval = readl_relaxed(LPASS_REG_BASE(AUDIO_CORE_GDSCR)); |
| 5552 | regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK); |
| 5553 | |
| 5554 | /* Configure wait time between states. */ |
| 5555 | regval &= ~(EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK); |
| 5556 | regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; |
| 5557 | writel_relaxed(regval, LPASS_REG_BASE(AUDIO_CORE_GDSCR)); |
| 5558 | |
| 5559 | regval = readl_relaxed(LPASS_REG_BASE(AUDIO_CORE_GDSCR)); |
| 5560 | regval &= ~BIT(0); |
| 5561 | writel_relaxed(regval, LPASS_REG_BASE(AUDIO_CORE_GDSCR)); |
| 5562 | |
| 5563 | ret = readl_poll_timeout(LPASS_REG_BASE(AUDIO_CORE_GDSCR), status, |
| 5564 | status & PWR_ON_MASK, 50, GDSC_TIMEOUT_US); |
| 5565 | WARN(ret, "LPASS Audio Core GDSC did not power on.\n"); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5566 | } |
| 5567 | |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 5568 | static void __init mdss_clock_setup(void) |
| 5569 | { |
| 5570 | clk_ops_byte = clk_ops_rcg_mnd; |
| 5571 | clk_ops_byte.set_rate = set_rate_byte; |
| 5572 | clk_ops_dsi_byte_pll.get_parent = dsi_pll_clk_get_parent; |
| 5573 | |
| 5574 | clk_ops_pixel = clk_ops_rcg; |
| 5575 | clk_ops_pixel.set_rate = set_rate_pixel; |
| 5576 | clk_ops_dsi_pixel_pll.get_parent = dsi_pll_clk_get_parent; |
| 5577 | |
| 5578 | mdss_clk_ctrl_init(); |
| 5579 | } |
| 5580 | |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 5581 | static void __init msm8974_clock_post_init(void) |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5582 | { |
Vikram Mulukutla | d16a8f1 | 2012-07-20 13:33:45 -0700 | [diff] [blame] | 5583 | clk_set_rate(&axi_clk_src.c, 282000000); |
| 5584 | clk_set_rate(&ocmemnoc_clk_src.c, 282000000); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5585 | |
Vikram Mulukutla | f8634bb | 2012-06-28 16:21:21 -0700 | [diff] [blame] | 5586 | /* |
Vikram Mulukutla | 09e2081 | 2012-07-12 11:32:42 -0700 | [diff] [blame] | 5587 | * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB |
| 5588 | * source. Sleep set vote is 0. |
| 5589 | */ |
| 5590 | clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000); |
| 5591 | clk_prepare_enable(&mmssnoc_ahb_a_clk.c); |
| 5592 | |
| 5593 | /* |
Vikram Mulukutla | f8634bb | 2012-06-28 16:21:21 -0700 | [diff] [blame] | 5594 | * Hold an active set vote for CXO; this is because CXO is expected |
| 5595 | * to remain on whenever CPUs aren't power collapsed. |
| 5596 | */ |
| 5597 | clk_prepare_enable(&cxo_a_clk_src.c); |
| 5598 | |
Vikram Mulukutla | 6c0f1a7 | 2012-08-10 01:59:28 -0700 | [diff] [blame] | 5599 | /* TODO: Temporarily enable a clock to allow access to LPASS core |
| 5600 | * registers. |
| 5601 | */ |
| 5602 | clk_prepare_enable(&audio_core_ixfabric_clk.c); |
| 5603 | |
Vikram Mulukutla | 274b2d9 | 2012-07-13 15:53:04 -0700 | [diff] [blame] | 5604 | /* |
| 5605 | * TODO: Temporarily enable NOC configuration AHB clocks. Remove when |
| 5606 | * the bus driver is ready. |
| 5607 | */ |
| 5608 | clk_prepare_enable(&gcc_mmss_noc_cfg_ahb_clk.c); |
| 5609 | clk_prepare_enable(&gcc_ocmem_noc_cfg_ahb_clk.c); |
| 5610 | |
Vikram Mulukutla | fe0f5a5 | 2012-08-16 16:51:08 -0700 | [diff] [blame] | 5611 | mdss_clock_setup(); |
| 5612 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5613 | /* Set rates for single-rate clocks. */ |
| 5614 | clk_set_rate(&usb30_master_clk_src.c, |
| 5615 | usb30_master_clk_src.freq_tbl[0].freq_hz); |
| 5616 | clk_set_rate(&tsif_ref_clk_src.c, |
| 5617 | tsif_ref_clk_src.freq_tbl[0].freq_hz); |
| 5618 | clk_set_rate(&usb_hs_system_clk_src.c, |
| 5619 | usb_hs_system_clk_src.freq_tbl[0].freq_hz); |
| 5620 | clk_set_rate(&usb_hsic_clk_src.c, |
| 5621 | usb_hsic_clk_src.freq_tbl[0].freq_hz); |
| 5622 | clk_set_rate(&usb_hsic_io_cal_clk_src.c, |
| 5623 | usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz); |
| 5624 | clk_set_rate(&usb_hsic_system_clk_src.c, |
| 5625 | usb_hsic_system_clk_src.freq_tbl[0].freq_hz); |
| 5626 | clk_set_rate(&usb30_mock_utmi_clk_src.c, |
| 5627 | usb30_mock_utmi_clk_src.freq_tbl[0].freq_hz); |
| 5628 | clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz); |
| 5629 | clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz); |
| 5630 | clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz); |
| 5631 | clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz); |
| 5632 | clk_set_rate(&mclk2_clk_src.c, mclk2_clk_src.freq_tbl[0].freq_hz); |
| 5633 | clk_set_rate(&edpaux_clk_src.c, edpaux_clk_src.freq_tbl[0].freq_hz); |
| 5634 | clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz); |
| 5635 | clk_set_rate(&esc1_clk_src.c, esc1_clk_src.freq_tbl[0].freq_hz); |
| 5636 | clk_set_rate(&hdmi_clk_src.c, hdmi_clk_src.freq_tbl[0].freq_hz); |
| 5637 | clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz); |
| 5638 | clk_set_rate(&audio_core_slimbus_core_clk_src.c, |
| 5639 | audio_core_slimbus_core_clk_src.freq_tbl[0].freq_hz); |
| 5640 | } |
| 5641 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 5642 | #define GCC_CC_PHYS 0xFC400000 |
| 5643 | #define GCC_CC_SIZE SZ_16K |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5644 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 5645 | #define MMSS_CC_PHYS 0xFD8C0000 |
| 5646 | #define MMSS_CC_SIZE SZ_256K |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5647 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 5648 | #define LPASS_CC_PHYS 0xFE000000 |
| 5649 | #define LPASS_CC_SIZE SZ_256K |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5650 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 5651 | #define MSS_CC_PHYS 0xFC980000 |
| 5652 | #define MSS_CC_SIZE SZ_16K |
| 5653 | |
| 5654 | #define APCS_GCC_CC_PHYS 0xF9011000 |
| 5655 | #define APCS_GCC_CC_SIZE SZ_4K |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 5656 | |
Vikram Mulukutla | 77140da | 2012-08-13 21:37:18 -0700 | [diff] [blame] | 5657 | static void __init enable_rpm_scaling(void) |
| 5658 | { |
| 5659 | int rc, value = 0x1; |
| 5660 | struct msm_rpm_kvp kvp = { |
| 5661 | .key = RPM_SMD_KEY_ENABLE, |
| 5662 | .data = (void *)&value, |
| 5663 | .length = sizeof(value), |
| 5664 | }; |
| 5665 | |
| 5666 | rc = msm_rpm_send_message_noirq(MSM_RPM_CTX_SLEEP_SET, |
| 5667 | RPM_MISC_CLK_TYPE, RPM_SCALING_ENABLE_ID, &kvp, 1); |
| 5668 | WARN(rc < 0, "RPM clock scaling (sleep set) did not enable!\n"); |
| 5669 | |
| 5670 | rc = msm_rpm_send_message_noirq(MSM_RPM_CTX_ACTIVE_SET, |
| 5671 | RPM_MISC_CLK_TYPE, RPM_SCALING_ENABLE_ID, &kvp, 1); |
| 5672 | WARN(rc < 0, "RPM clock scaling (active set) did not enable!\n"); |
| 5673 | } |
| 5674 | |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 5675 | static void __init msm8974_clock_pre_init(void) |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5676 | { |
| 5677 | virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE); |
| 5678 | if (!virt_bases[GCC_BASE]) |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 5679 | panic("clock-8974: Unable to ioremap GCC memory!"); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5680 | |
| 5681 | virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE); |
| 5682 | if (!virt_bases[MMSS_BASE]) |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 5683 | panic("clock-8974: Unable to ioremap MMSS_CC memory!"); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5684 | |
| 5685 | virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE); |
| 5686 | if (!virt_bases[LPASS_BASE]) |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 5687 | panic("clock-8974: Unable to ioremap LPASS_CC memory!"); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5688 | |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 5689 | virt_bases[MSS_BASE] = ioremap(MSS_CC_PHYS, MSS_CC_SIZE); |
| 5690 | if (!virt_bases[MSS_BASE]) |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 5691 | panic("clock-8974: Unable to ioremap MSS_CC memory!"); |
Vikram Mulukutla | a967db4 | 2012-05-10 16:20:40 -0700 | [diff] [blame] | 5692 | |
Matt Wagantall | edf2fad | 2012-08-06 16:11:46 -0700 | [diff] [blame] | 5693 | virt_bases[APCS_BASE] = ioremap(APCS_GCC_CC_PHYS, APCS_GCC_CC_SIZE); |
| 5694 | if (!virt_bases[APCS_BASE]) |
| 5695 | panic("clock-8974: Unable to ioremap APCS_GCC_CC memory!"); |
| 5696 | |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 5697 | clk_ops_local_pll.enable = msm8974_pll_clk_enable; |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5698 | |
Vikram Mulukutla | b7a1a74 | 2012-05-30 17:24:33 -0700 | [diff] [blame] | 5699 | vdd_dig_reg = rpm_regulator_get(NULL, "vdd_dig"); |
| 5700 | if (IS_ERR(vdd_dig_reg)) |
Vikram Mulukutla | 19245e0 | 2012-07-23 15:58:04 -0700 | [diff] [blame] | 5701 | panic("clock-8974: Unable to get the vdd_dig regulator!"); |
Vikram Mulukutla | b7a1a74 | 2012-05-30 17:24:33 -0700 | [diff] [blame] | 5702 | |
| 5703 | /* |
| 5704 | * TODO: Set a voltage and enable vdd_dig, leaving the voltage high |
| 5705 | * until late_init. This may not be necessary with clock handoff; |
| 5706 | * Investigate this code on a real non-simulator target to determine |
| 5707 | * its necessity. |
| 5708 | */ |
| 5709 | vote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
| 5710 | rpm_regulator_enable(vdd_dig_reg); |
| 5711 | |
Vikram Mulukutla | 77140da | 2012-08-13 21:37:18 -0700 | [diff] [blame] | 5712 | enable_rpm_scaling(); |
| 5713 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5714 | reg_init(); |
| 5715 | } |
| 5716 | |
Vikram Mulukutla | b7a1a74 | 2012-05-30 17:24:33 -0700 | [diff] [blame] | 5717 | static int __init msm8974_clock_late_init(void) |
| 5718 | { |
| 5719 | return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
| 5720 | } |
| 5721 | |
Vikram Mulukutla | 19245e0 | 2012-07-23 15:58:04 -0700 | [diff] [blame] | 5722 | static void __init msm8974_rumi_clock_pre_init(void) |
| 5723 | { |
| 5724 | virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE); |
| 5725 | if (!virt_bases[GCC_BASE]) |
| 5726 | panic("clock-8974: Unable to ioremap GCC memory!"); |
| 5727 | |
| 5728 | /* SDCC clocks are partially emulated in the RUMI */ |
| 5729 | sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc_apps_rumi_clk; |
| 5730 | sdcc2_apps_clk_src.freq_tbl = ftbl_gcc_sdcc_apps_rumi_clk; |
| 5731 | sdcc3_apps_clk_src.freq_tbl = ftbl_gcc_sdcc_apps_rumi_clk; |
| 5732 | sdcc4_apps_clk_src.freq_tbl = ftbl_gcc_sdcc_apps_rumi_clk; |
| 5733 | |
| 5734 | vdd_dig_reg = rpm_regulator_get(NULL, "vdd_dig"); |
| 5735 | if (IS_ERR(vdd_dig_reg)) |
| 5736 | panic("clock-8974: Unable to get the vdd_dig regulator!"); |
| 5737 | |
| 5738 | /* |
| 5739 | * TODO: Set a voltage and enable vdd_dig, leaving the voltage high |
| 5740 | * until late_init. This may not be necessary with clock handoff; |
| 5741 | * Investigate this code on a real non-simulator target to determine |
| 5742 | * its necessity. |
| 5743 | */ |
| 5744 | vote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
| 5745 | rpm_regulator_enable(vdd_dig_reg); |
| 5746 | } |
| 5747 | |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 5748 | struct clock_init_data msm8974_clock_init_data __initdata = { |
| 5749 | .table = msm_clocks_8974, |
| 5750 | .size = ARRAY_SIZE(msm_clocks_8974), |
| 5751 | .pre_init = msm8974_clock_pre_init, |
| 5752 | .post_init = msm8974_clock_post_init, |
Vikram Mulukutla | b7a1a74 | 2012-05-30 17:24:33 -0700 | [diff] [blame] | 5753 | .late_init = msm8974_clock_late_init, |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 5754 | }; |
Vikram Mulukutla | 19245e0 | 2012-07-23 15:58:04 -0700 | [diff] [blame] | 5755 | |
| 5756 | struct clock_init_data msm8974_rumi_clock_init_data __initdata = { |
| 5757 | .table = msm_clocks_8974_rumi, |
| 5758 | .size = ARRAY_SIZE(msm_clocks_8974_rumi), |
| 5759 | .pre_init = msm8974_rumi_clock_pre_init, |
| 5760 | }; |