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gerrit-public.fairphone.software / kernel / msm / a54911245b63a00c3c2595ccac1e3c909f3c999f / . / arch / arm / boot / dts / msm8610.dtsi
blob: a11fa601c3357af50264bd2a8c6426ec07129e64 [file] [log] [blame]
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Olav Haugan54166782013-01-28 16:59:51 -0800[diff] [blame]14/include/ "msm-iommu-v0.dtsi"
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]15/include/ "msm8610-ion.dtsi"
Lokesh Batra8d55eec2013-02-26 11:31:21 -0800[diff] [blame]16/include/ "msm8610-gpu.dtsi"
Matt Wagantall1bf56932012-11-29 15:03:29 -0800[diff] [blame]17/include/ "msm-gdsc.dtsi"
Aparna Dasd16555b2013-03-06 15:46:38 -0800[diff] [blame]18/include/ "msm8610-coresight.dtsi"
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]19/include/ "msm8610-pm.dtsi"
Jeff Hugo53dcf0f2013-03-20 12:37:50 -0600[diff] [blame]20/include/ "msm8610-smp2p.dtsi"
Gagan Macbced3872013-02-04 19:18:04 -0700[diff] [blame]21/include/ "msm8610-bus.dtsi"
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]22
23/ {
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]24 model = "Qualcomm MSM 8610";
25 compatible = "qcom,msm8610";
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]26 interrupt-parent = <&intc>;
27
28 intc: interrupt-controller@f9000000 {
29 compatible = "qcom,msm-qgic2";
30 interrupt-controller;
31 #interrupt-cells = <3>;
32 reg = <0xf9000000 0x1000>,
33 <0xf9002000 0x1000>;
34 };
35
36 msmgpio: gpio@fd510000 {
37 compatible = "qcom,msm-gpio";
38 interrupt-controller;
39 #interrupt-cells = <2>;
40 reg = <0xfd510000 0x4000>;
Syed Rameez Mustafa86cccfc2012-12-10 18:06:08 -0800[diff] [blame]41 gpio-controller;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]42 #gpio-cells = <2>;
Rohit Vaswani341c2032012-11-08 18:49:29 -0800[diff] [blame]43 ngpio = <102>;
Rohit Vaswanid2001522012-12-05 19:23:44 -0800[diff] [blame]44 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -0800[diff] [blame]45 qcom,direct-connect-irqs = <8>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]46 };
47
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]48 aliases {
49 spi0 = &spi_0;
50 };
51
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -0700[diff] [blame]52 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -0800[diff] [blame]53 compatible = "arm,armv7-timer";
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -0700[diff] [blame]54 interrupts = <1 2 0 1 3 0>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]55 clock-frequency = <19200000>;
56 };
57
Arun Menon2a7e3772013-01-17 12:06:59 -0800[diff] [blame]58 qcom,msm-adsp-loader {
59 compatible = "qcom,adsp-loader";
60 qcom,adsp-state = <0>;
61 };
62
Abhimanyu Kapur032b1f42013-01-18 00:10:50 -0800[diff] [blame]63 qcom,msm-imem@fe805000 {
64 compatible = "qcom,msm-imem";
65 reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
66 };
67
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]68 serial@f991f000 {
69 compatible = "qcom,msm-lsuart-v14";
70 reg = <0xf991f000 0x1000>;
71 interrupts = <0 109 0>;
72 status = "disabled";
73 };
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]74
Arun Menon8e25dd42013-01-11 14:11:54 -0800[diff] [blame]75 qcom,vidc@fdc00000 {
76 compatible = "qcom,msm-vidc";
Sachin Shah4e1c8fe2013-03-20 15:10:05 -0700[diff] [blame]77 qcom,vidc-ns-map = <0x40000000 0x40000000>;
78 qcom,iommu-groups = <&q6_domain_ns>;
79 qcom,iommu-group-buffer-types = <0xfff>;
80 qcom,buffer-type-tz-usage-map = <0x1 0x1>,
81 <0x1fe 0x2>;
82 qcom,hfi = "q6";
Deva Ramasubramanian74b1dda2013-03-27 13:16:17 -0700[diff] [blame]83 qcom,max-hw-load = <97200>; /* FWVGA @ 30 * 2 */
Arun Menon8e25dd42013-01-11 14:11:54 -0800[diff] [blame]84 };
85
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]86 usb@f9a55000 {
87 compatible = "qcom,hsusb-otg";
88 reg = <0xf9a55000 0x400>;
Mayank Rana33d26662013-01-17 10:22:25 +0530[diff] [blame]89 interrupts = <0 134 0>, <0 140 0>;
90 interrupt-names = "core_irq", "async_irq";
Mayank Rana76c6ce22012-11-07 17:07:58 +0530[diff] [blame]91 HSUSB_VDDCX-supply = <&pm8110_s1>;
92 HSUSB_1p8-supply = <&pm8110_l10>;
93 HSUSB_3p3-supply = <&pm8110_l20>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]94
95 qcom,hsusb-otg-phy-type = <2>;
96 qcom,hsusb-otg-mode = <1>;
Mayank Rana29bb9f22013-04-04 18:25:12 +0530[diff] [blame]97 qcom,hsusb-otg-otg-control = <2>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]98 qcom,hsusb-otg-disable-reset;
Mayank Ranaa5491122013-04-04 18:32:25 +0530[diff] [blame^]99 qcom,dp-manual-pullup;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]100 };
101
Mayank Ranacc0c5452013-01-29 16:41:53 +0530[diff] [blame]102 android_usb@fe8050c8 {
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]103 compatible = "qcom,android-usb";
Mayank Ranacc0c5452013-01-29 16:41:53 +0530[diff] [blame]104 reg = <0xfe8050c8 0xc8>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]105 };
106
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]107 sdcc1: qcom,sdcc@f9824000 {
108 cell-index = <1>; /* SDC1 eMMC slot */
109 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800[diff] [blame]110 reg = <0xf9824000 0x800>,
111 <0xf9824800 0x100>,
112 <0xf9804000 0x7000>;
113 reg-names = "core_mem", "dml_mem", "bam_mem";
114 interrupts = <0 123 0>, <0 137 0>;
115 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]116
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]117 vdd-supply = <&pm8110_l17>;
118 qcom,vdd-always-on;
119 qcom,vdd-lpm-sup;
120 qcom,vdd-voltage-level = <2900000 2900000>;
121 qcom,vdd-current-level = <9000 400000>;
122
123 vdd-io-supply = <&pm8110_l6>;
124 qcom,vdd-io-always-on;
125 qcom,vdd-io-lpm-sup;
126 qcom,vdd-io-voltage-level = <1800000 1800000>;
127 qcom,vdd-io-current-level = <9000 60000>;
128
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]129 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
130 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
131 qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
132 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]133
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]134 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]135 qcom,sup-voltages = <2900 2900>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]136 qcom,bus-width = <8>;
137 qcom,nonremovable;
138 qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]139 };
140
141 sdcc2: qcom,sdcc@f98a4000 {
142 cell-index = <2>; /* SDC2 SD card slot */
143 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800[diff] [blame]144 reg = <0xf98a4000 0x800>,
145 <0xf98a4800 0x100>,
146 <0xf9884000 0x7000>;
147 reg-names = "core_mem", "dml_mem", "bam_mem";
148 interrupts = <0 125 0>, <0 220 0>;
149 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]150
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]151 vdd-supply = <&pm8110_l18>;
152 qcom,vdd-voltage-level = <2950000 2950000>;
153 qcom,vdd-current-level = <9000 400000>;
154
155 vdd-io-supply = <&pm8110_l21>;
156 qcom,vdd-io-voltage-level = <1800000 2950000>;
157 qcom,vdd-io-current-level = <9000 50000>;
158
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]159 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
160 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
161 qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
162 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]163
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]164 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
165 qcom,sup-voltages = <2950 2950>;
166 qcom,bus-width = <4>;
167 qcom,xpc;
168 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
169 qcom,current-limit = <800>;
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]170 };
171
Yan He6c7304c2012-11-09 22:07:08 -0800[diff] [blame]172 qcom,sps {
173 compatible = "qcom,msm_sps";
174 qcom,device-type = <3>;
175 };
176
Jeff Hugo6a289a32012-11-29 16:16:47 -0700[diff] [blame]177 qcom,smem@d600000 {
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]178 compatible = "qcom,smem";
Jeff Hugo6a289a32012-11-29 16:16:47 -0700[diff] [blame]179 reg = <0xd600000 0x200000>,
Stepan Moskovchenkod6ee8262013-02-06 11:26:05 -0800[diff] [blame]180 <0xf9011000 0x1000>,
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]181 <0xfc428000 0x4000>;
182 reg-names = "smem", "irq-reg-base", "aux-mem1";
183
184 qcom,smd-modem {
185 compatible = "qcom,smd";
186 qcom,smd-edge = <0>;
187 qcom,smd-irq-offset = <0x8>;
188 qcom,smd-irq-bitmask = <0x1000>;
189 qcom,pil-string = "modem";
190 interrupts = <0 25 1>;
191 };
192
193 qcom,smsm-modem {
194 compatible = "qcom,smsm";
195 qcom,smsm-edge = <0>;
196 qcom,smsm-irq-offset = <0x8>;
197 qcom,smsm-irq-bitmask = <0x2000>;
198 interrupts = <0 26 1>;
199 };
200
201 qcom,smd-adsp {
202 compatible = "qcom,smd";
203 qcom,smd-edge = <1>;
204 qcom,smd-irq-offset = <0x8>;
205 qcom,smd-irq-bitmask = <0x100>;
206 qcom,pil-string = "adsp";
207 interrupts = <0 156 1>;
208 };
209
210 qcom,smsm-adsp {
211 compatible = "qcom,smsm";
212 qcom,smsm-edge = <1>;
213 qcom,smsm-irq-offset = <0x8>;
214 qcom,smsm-irq-bitmask = <0x200>;
215 interrupts = <0 157 1>;
216 };
217
218 qcom,smd-wcnss {
219 compatible = "qcom,smd";
220 qcom,smd-edge = <6>;
221 qcom,smd-irq-offset = <0x8>;
222 qcom,smd-irq-bitmask = <0x20000>;
223 qcom,pil-string = "wcnss";
224 interrupts = <0 142 1>;
225 };
226
227 qcom,smsm-wcnss {
228 compatible = "qcom,smsm";
229 qcom,smsm-edge = <6>;
230 qcom,smsm-irq-offset = <0x8>;
231 qcom,smsm-irq-bitmask = <0x80000>;
232 interrupts = <0 144 1>;
233 };
234
235 qcom,smd-rpm {
236 compatible = "qcom,smd";
237 qcom,smd-edge = <15>;
238 qcom,smd-irq-offset = <0x8>;
239 qcom,smd-irq-bitmask = <0x1>;
240 interrupts = <0 168 1>;
241 qcom,irq-no-suspend;
242 };
David Ng5a3cb232012-12-03 16:42:53 -0800[diff] [blame]243 };
Hanumant Singh4e334c82012-11-14 10:16:39 -0800[diff] [blame]244
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]245 rpm_bus: qcom,rpm-smd {
246 compatible = "qcom,rpm-smd";
247 rpm-channel-name = "rpm_requests";
248 rpm-channel-type = <15>; /* SMD_APPS_RPM */
Priyanka Mathur6e993c92013-03-20 11:17:27 -0700[diff] [blame]249 rpm-standalone;
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]250 };
251
Olav Haugan8340d932013-01-25 12:03:11 -0800[diff] [blame]252 qcom,msm-mem-hole {
253 compatible = "qcom,msm-mem-hole";
Olav Hauganfcc860e2013-04-06 10:56:06 -0700[diff] [blame]254 qcom,memblock-remove = <0x07B00000 0x6400000>; /* Address and Size of Hole */
Olav Haugan8340d932013-01-25 12:03:11 -0800[diff] [blame]255 };
256
Hanumant Singh4e334c82012-11-14 10:16:39 -0800[diff] [blame]257 qcom,wdt@f9017000 {
258 compatible = "qcom,msm-watchdog";
259 reg = <0xf9017000 0x1000>;
260 interrupts = <0 3 0>, <0 4 0>;
261 qcom,bark-time = <11000>;
262 qcom,pet-time = <10000>;
Mitchel Humpherys1be23802012-11-16 15:52:32 -0800[diff] [blame]263 qcom,ipi-ping;
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]264 };
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]265
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800[diff] [blame]266 qcom,acpuclk@f9011050 {
267 compatible = "qcom,acpuclk-a7";
268 reg = <0xf9011050 0x8>;
269 reg-names = "rcg_base";
Patrick Dalyf9451d22013-03-20 14:20:12 -0700[diff] [blame]270 a7_cpu-supply = <&apc_vreg_corner>;
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800[diff] [blame]271 a7_mem-supply = <&pm8110_l3>;
272 };
273
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]274 spmi_bus: qcom,spmi@fc4c0000 {
275 cell-index = <0>;
276 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]277 reg-names = "core", "intr", "cnfg";
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]278 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]279 <0Xfc4cb000 0x1000>,
280 <0Xfc4ca000 0x1000>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]281 /* 190,ee0_krait_hlos_spmi_periph_irq */
282 /* 187,channel_0_krait_hlos_trans_done_irq */
283 interrupts = <0 190 0>, <0 187 0>;
284 qcom,not-wakeup;
285 qcom,pmic-arb-ee = <0>;
286 qcom,pmic-arb-channel = <0>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]287 };
288
Gilad Avidovf84f2792013-01-31 13:26:39 -0700[diff] [blame]289 i2c@f9925000 { /* BLSP-1 QUP-3 */
290 cell-index = <0>;
291 compatible = "qcom,i2c-qup";
292 #address-cells = <1>;
293 #size-cells = <0>;
294 reg-names = "qup_phys_addr";
295 reg = <0xf9925000 0x1000>;
296 interrupt-names = "qup_err_intr";
297 interrupts = <0 97 0>;
298 qcom,i2c-bus-freq = <100000>;
299 };
300
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]301
302 spi_0: spi@f9923000 { /* BLSP1 QUP1 */
303 compatible = "qcom,spi-qup-v2";
304 #address-cells = <1>;
305 #size-cells = <0>;
306 reg-names = "spi_physical", "spi_bam_physical";
307 reg = <0xf9923000 0x1000>,
308 <0xf9904000 0xF000>;
309 interrupt-names = "spi_irq", "spi_bam_irq";
310 interrupts = <0 95 0>, <0 238 0>;
311 spi-max-frequency = <19200000>;
312
313 gpios = <&msmgpio 3 0>, /* CLK */
314 <&msmgpio 1 0>, /* MISO */
315 <&msmgpio 0 0>; /* MOSI */
316 cs-gpios = <&msmgpio 2 0>;
317
318 qcom,infinite-mode = <0>;
319 qcom,use-bam;
320 qcom,ver-reg-exists;
321 qcom,bam-consumer-pipe-index = <12>;
322 qcom,bam-producer-pipe-index = <13>;
323 };
324
Vikram Mulukutla1ac32fd2013-01-28 10:03:58 -0800[diff] [blame]325 qcom,pronto@fb21b000 {
326 compatible = "qcom,pil-pronto";
327 reg = <0xfb21b000 0x3000>,
328 <0xfc401700 0x4>,
329 <0xfd485300 0xc>;
330 reg-names = "pmu_base", "clk_base", "halt_base";
331 interrupts = <0 149 1>;
332 vdd_pronto_pll-supply = <&pm8110_l10>;
333
334 qcom,firmware-name = "wcnss";
335 };
336
Fred Oh92b18a02013-01-22 13:29:41 -0800[diff] [blame]337 sound {
338 compatible = "qcom,msm8x10-audio-codec";
339 qcom,model = "msm8x10-snd-card";
340 };
341
342 qcom,msm-pcm {
343 compatible = "qcom,msm-pcm-dsp";
344 };
345
346 qcom,msm-pcm-routing {
347 compatible = "qcom,msm-pcm-routing";
348 };
349
350 qcom,msm-pcm-lpa {
351 compatible = "qcom,msm-pcm-lpa";
352 };
353
354 qcom,msm-compr-dsp {
355 compatible = "qcom,msm-compr-dsp";
356 };
357
358 qcom,msm-voip-dsp {
359 compatible = "qcom,msm-voip-dsp";
360 };
361
362 qcom,msm-pcm-voice {
363 compatible = "qcom,msm-pcm-voice";
364 };
365
366 qcom,msm-stub-codec {
367 compatible = "qcom,msm-stub-codec";
368 };
369
370 qcom,msm-dai-fe {
371 compatible = "qcom,msm-dai-fe";
372 };
373
374 qcom,msm-pcm-afe {
375 compatible = "qcom,msm-pcm-afe";
376 };
377
378 qcom,msm-dai-mi2s {
379 compatible = "qcom,msm-dai-mi2s";
380 qcom,msm-dai-q6-mi2s-prim {
381 compatible = "qcom,msm-dai-q6-mi2s";
382 qcom,msm-dai-q6-mi2s-dev-id = <0>;
383 qcom,msm-mi2s-rx-lines = <1>;
384 qcom,msm-mi2s-tx-lines = <0>;
385 };
386
387 qcom,msm-dai-q6-mi2s-sec {
388 compatible = "qcom,msm-dai-q6-mi2s";
389 qcom,msm-dai-q6-mi2s-dev-id = <1>;
390 qcom,msm-mi2s-rx-lines = <0>;
391 qcom,msm-mi2s-tx-lines = <3>;
392 };
393 };
394
395 qcom,msm-dai-q6 {
396 compatible = "qcom,msm-dai-q6";
397 qcom,msm-dai-q6-bt-sco-rx {
398 compatible = "qcom,msm-dai-q6-dev";
399 qcom,msm-dai-q6-dev-id = <12288>;
400 };
401
402 qcom,msm-dai-q6-bt-sco-tx {
403 compatible = "qcom,msm-dai-q6-dev";
404 qcom,msm-dai-q6-dev-id = <12289>;
405 };
406
407 qcom,msm-dai-q6-int-fm-rx {
408 compatible = "qcom,msm-dai-q6-dev";
409 qcom,msm-dai-q6-dev-id = <12292>;
410 };
411
412 qcom,msm-dai-q6-int-fm-tx {
413 compatible = "qcom,msm-dai-q6-dev";
414 qcom,msm-dai-q6-dev-id = <12293>;
415 };
416
417 qcom,msm-dai-q6-be-afe-pcm-rx {
418 compatible = "qcom,msm-dai-q6-dev";
419 qcom,msm-dai-q6-dev-id = <224>;
420 };
421
422 qcom,msm-dai-q6-be-afe-pcm-tx {
423 compatible = "qcom,msm-dai-q6-dev";
424 qcom,msm-dai-q6-dev-id = <225>;
425 };
426
427 qcom,msm-dai-q6-afe-proxy-rx {
428 compatible = "qcom,msm-dai-q6-dev";
429 qcom,msm-dai-q6-dev-id = <241>;
430 };
431
432 qcom,msm-dai-q6-afe-proxy-tx {
433 compatible = "qcom,msm-dai-q6-dev";
434 qcom,msm-dai-q6-dev-id = <240>;
435 };
436 };
437
438 qcom,msm-pcm-hostless {
439 compatible = "qcom,msm-pcm-hostless";
440 };
441
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]442 qcom,mss@fc880000 {
443 compatible = "qcom,pil-q6v5-mss";
444 reg = <0xfc880000 0x100>,
445 <0xfd485000 0x400>,
446 <0xfc820000 0x020>,
447 <0xfc401680 0x004>,
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]448 <0xfd485194 0x4>;
449 reg-names = "qdsp6_base", "halt_base", "rmb_base",
Matt Wagantall724b2bb2013-03-18 14:54:06 -0700[diff] [blame]450 "restart_reg", "cxrail_bhs_reg";
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]451
452 interrupts = <0 24 1>;
453 vdd_mss-supply = <&pm8110_s1>;
454 vdd_cx-supply = <&pm8110_s1_corner>;
455 vdd_mx-supply = <&pm8110_l3>;
456 vdd_pll-supply = <&pm8110_l10>;
457 qcom,vdd_pll = <1800000>;
458 qcom,is-loadable;
459 qcom,firmware-name = "mba";
460 qcom,pil-self-auth;
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700[diff] [blame]461
Seemanta Duttaa0f253e2013-01-16 18:54:40 -0800[diff] [blame]462 /* GPIO inputs from mss */
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700[diff] [blame]463 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
Seemanta Duttaa0f253e2013-01-16 18:54:40 -0800[diff] [blame]464 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
Vikram Mulukutla7268d9f2013-04-01 16:57:57 -0700[diff] [blame]465
466 /* GPIO output to mss */
467 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]468 };
469
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]470 qcom,lpass@fe200000 {
471 compatible = "qcom,pil-q6v5-lpass";
472 reg = <0xfe200000 0x00100>,
Matt Wagantall015b50af2013-03-05 18:51:16 -0800[diff] [blame]473 <0xfd485100 0x00010>,
474 <0xfc4016c0 0x00004>;
475 reg-names = "qdsp6_base", "halt_base", "restart_reg";
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]476 interrupts = <0 162 1>;
Matt Wagantall6c515982013-01-29 14:58:43 -0800[diff] [blame]477 vdd_cx-supply = <&pm8110_s1_corner>;
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]478 qcom,firmware-name = "adsp";
479 };
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]480
481 tsens: tsens@fc4a8000 {
482 compatible = "qcom,msm-tsens";
483 reg = <0xfc4a8000 0x2000>,
484 <0xfc4b8000 0x1000>;
485 reg-names = "tsens_physical", "tsens_eeprom_physical";
486 interrupts = <0 184 0>;
487 qcom,sensors = <2>;
488 qcom,slope = <2901 2846>;
Siddartha Mohanadossb2f48982013-03-28 13:51:38 -0700[diff] [blame]489 qcom,calib-mode = "fuse_map3";
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]490 qcom,calibration-less-mode;
Siddartha Mohanadoss0ca83312013-03-14 11:43:18 -0700[diff] [blame]491 qcom,tsens-local-init;
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]492 };
493
Jennifer Liuf588d3a2013-04-05 10:11:48 -0700[diff] [blame]494 qcom,msm-thermal {
495 compatible = "qcom,msm-thermal";
496 qcom,sensor-id = <0>;
497 qcom,poll-ms = <250>;
498 qcom,limit-temp = <60>;
499 qcom,temp-hysteresis = <10>;
500 qcom,freq-step = <2>;
501 };
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]502};
David Collinsc6b34832012-10-24 12:57:57 -0700[diff] [blame]503
Matt Wagantall1bf56932012-11-29 15:03:29 -0800[diff] [blame]504&gdsc_vfe {
505 status = "ok";
506};
507
508&gdsc_oxili_cx {
509 status = "ok";
510};
511
Olav Haugan9c255522012-11-16 16:43:17 -0800[diff] [blame]512&lpass_iommu {
513 status = "ok";
514};
515
516&copss_iommu {
517 status = "ok";
518};
519
520&mdpe_iommu {
521 status = "ok";
522};
523
524&mdps_iommu {
525 status = "ok";
526};
527
528&gfx_iommu {
529 status = "ok";
530};
531
532&vfe_iommu {
533 status = "ok";
534};
535
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]536/include/ "msm8610-iommu-domains.dtsi"
Olav Haugan4bc4b692012-12-10 18:29:35 -0800[diff] [blame]537
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]538/include/ "msm-pm8110.dtsi"
Xiaozhe Shi1581a7b2013-02-21 15:17:57 -0800[diff] [blame]539/include/ "msm8610-regulator.dtsi"
Siddartha Mohanadoss0f664a82013-03-11 22:52:01 -0700[diff] [blame]540
541&pm8110_vadc {
542 chan@0 {
543 label = "usb_in";
544 reg = <0>;
545 qcom,decimation = <0>;
546 qcom,pre-div-channel-scaling = <4>;
547 qcom,calibration-type = "absolute";
548 qcom,scale-function = <0>;
549 qcom,hw-settle-time = <0>;
550 qcom,fast-avg-setup = <0>;
551 };
552
553 chan@2 {
554 label = "vchg_sns";
555 reg = <2>;
556 qcom,decimation = <0>;
557 qcom,pre-div-channel-scaling = <3>;
558 qcom,calibration-type = "absolute";
559 qcom,scale-function = <0>;
560 qcom,hw-settle-time = <0>;
561 qcom,fast-avg-setup = <0>;
562 };
563
564 chan@5 {
565 label = "vcoin";
566 reg = <5>;
567 qcom,decimation = <0>;
568 qcom,pre-div-channel-scaling = <1>;
569 qcom,calibration-type = "absolute";
570 qcom,scale-function = <0>;
571 qcom,hw-settle-time = <0>;
572 qcom,fast-avg-setup = <0>;
573 };
574
575 chan@6 {
576 label = "vbat_sns";
577 reg = <6>;
578 qcom,decimation = <0>;
579 qcom,pre-div-channel-scaling = <1>;
580 qcom,calibration-type = "absolute";
581 qcom,scale-function = <0>;
582 qcom,hw-settle-time = <0>;
583 qcom,fast-avg-setup = <0>;
584 };
585
586 chan@7 {
587 label = "vph_pwr";
588 reg = <7>;
589 qcom,decimation = <0>;
590 qcom,pre-div-channel-scaling = <1>;
591 qcom,calibration-type = "absolute";
592 qcom,scale-function = <0>;
593 qcom,hw-settle-time = <0>;
594 qcom,fast-avg-setup = <0>;
595 };
596
597 chan@30 {
598 label = "batt_therm";
599 reg = <0x30>;
600 qcom,decimation = <0>;
601 qcom,pre-div-channel-scaling = <0>;
602 qcom,calibration-type = "ratiometric";
603 qcom,scale-function = <1>;
604 qcom,hw-settle-time = <2>;
605 qcom,fast-avg-setup = <0>;
606 };
607
608 chan@31 {
609 label = "batt_id";
610 reg = <0x31>;
611 qcom,decimation = <0>;
612 qcom,pre-div-channel-scaling = <0>;
613 qcom,calibration-type = "ratiometric";
614 qcom,scale-function = <0>;
615 qcom,hw-settle-time = <2>;
616 qcom,fast-avg-setup = <0>;
617 };
618
619 chan@b2 {
620 label = "xo_therm_pu2";
621 reg = <0xb2>;
622 qcom,decimation = <0>;
623 qcom,pre-div-channel-scaling = <0>;
624 qcom,calibration-type = "ratiometric";
625 qcom,scale-function = <4>;
626 qcom,hw-settle-time = <2>;
627 qcom,fast-avg-setup = <0>;
628 };
629};
630
631