blob: 01ed1cfd3eb6d159af7b560c8a7419e4305ba67c [file] [log] [blame]
Dan Williams5cbafa62009-08-26 13:01:44 -07001/*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2009 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 */
22
23/*
24 * This driver supports an Intel I/OAT DMA engine (versions >= 2), which
25 * does asynchronous data movement and checksumming operations.
26 */
27
28#include <linux/init.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/workqueue.h>
36#include <linux/i7300_idle.h>
37#include "dma.h"
38#include "dma_v2.h"
39#include "registers.h"
40#include "hw.h"
41
Dan Williamsbf40a682009-09-08 17:42:55 -070042int ioat_ring_alloc_order = 8;
Dan Williams5cbafa62009-08-26 13:01:44 -070043module_param(ioat_ring_alloc_order, int, 0644);
44MODULE_PARM_DESC(ioat_ring_alloc_order,
Dan Williams376ec372009-09-16 15:16:50 -070045 "ioat2+: allocate 2^n descriptors per channel"
46 " (default: 8 max: 16)");
Dan Williamsa3092182009-09-08 12:02:01 -070047static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
48module_param(ioat_ring_max_alloc_order, int, 0644);
49MODULE_PARM_DESC(ioat_ring_max_alloc_order,
Dan Williams376ec372009-09-16 15:16:50 -070050 "ioat2+: upper limit for ring size (default: 16)");
Dan Williams5cbafa62009-08-26 13:01:44 -070051
Dan Williamsb094ad32009-09-08 17:42:57 -070052void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
Dan Williams5cbafa62009-08-26 13:01:44 -070053{
Dan Williams281befa2010-03-03 11:47:43 -070054 struct ioat_chan_common *chan = &ioat->base;
Dan Williams5cbafa62009-08-26 13:01:44 -070055
Dan Williams376ec372009-09-16 15:16:50 -070056 ioat->dmacount += ioat2_ring_pending(ioat);
Dan Williams5cbafa62009-08-26 13:01:44 -070057 ioat->issued = ioat->head;
58 /* make descriptor updates globally visible before notifying channel */
59 wmb();
Dan Williams281befa2010-03-03 11:47:43 -070060 writew(ioat->dmacount, chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
61 dev_dbg(to_dev(chan),
Dan Williams6df91832009-09-08 12:00:55 -070062 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
63 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
Dan Williams5cbafa62009-08-26 13:01:44 -070064}
65
Dan Williams281befa2010-03-03 11:47:43 -070066void ioat2_issue_pending(struct dma_chan *c)
Dan Williams5cbafa62009-08-26 13:01:44 -070067{
Dan Williams281befa2010-03-03 11:47:43 -070068 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
Dan Williams5cbafa62009-08-26 13:01:44 -070069
Dan Williams281befa2010-03-03 11:47:43 -070070 if (ioat2_ring_pending(ioat)) {
71 spin_lock_bh(&ioat->ring_lock);
Dan Williams5cbafa62009-08-26 13:01:44 -070072 __ioat2_issue_pending(ioat);
Dan Williams281befa2010-03-03 11:47:43 -070073 spin_unlock_bh(&ioat->ring_lock);
74 }
Dan Williams5cbafa62009-08-26 13:01:44 -070075}
76
77/**
78 * ioat2_update_pending - log pending descriptors
79 * @ioat: ioat2+ channel
80 *
Dan Williams281befa2010-03-03 11:47:43 -070081 * Check if the number of unsubmitted descriptors has exceeded the
82 * watermark. Called with ring_lock held
Dan Williams5cbafa62009-08-26 13:01:44 -070083 */
84static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
85{
Dan Williams281befa2010-03-03 11:47:43 -070086 if (ioat2_ring_pending(ioat) > ioat_pending_level)
Dan Williams5cbafa62009-08-26 13:01:44 -070087 __ioat2_issue_pending(ioat);
Dan Williams5cbafa62009-08-26 13:01:44 -070088}
89
90static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
91{
Dan Williams5cbafa62009-08-26 13:01:44 -070092 struct ioat_ring_ent *desc;
93 struct ioat_dma_descriptor *hw;
94 int idx;
95
96 if (ioat2_ring_space(ioat) < 1) {
97 dev_err(to_dev(&ioat->base),
98 "Unable to start null desc - ring full\n");
99 return;
100 }
101
Dan Williams6df91832009-09-08 12:00:55 -0700102 dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
103 __func__, ioat->head, ioat->tail, ioat->issued);
Dan Williams5cbafa62009-08-26 13:01:44 -0700104 idx = ioat2_desc_alloc(ioat, 1);
105 desc = ioat2_get_ring_ent(ioat, idx);
106
107 hw = desc->hw;
108 hw->ctl = 0;
109 hw->ctl_f.null = 1;
110 hw->ctl_f.int_en = 1;
111 hw->ctl_f.compl_write = 1;
112 /* set size to non-zero value (channel returns error when size is 0) */
113 hw->size = NULL_DESC_BUFFER_SIZE;
114 hw->src_addr = 0;
115 hw->dst_addr = 0;
116 async_tx_ack(&desc->txd);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700117 ioat2_set_chainaddr(ioat, desc->txd.phys);
Dan Williams6df91832009-09-08 12:00:55 -0700118 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700119 __ioat2_issue_pending(ioat);
120}
121
122static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
123{
124 spin_lock_bh(&ioat->ring_lock);
125 __ioat2_start_null_desc(ioat);
126 spin_unlock_bh(&ioat->ring_lock);
127}
128
Dan Williams09c8a5b2009-09-08 12:01:49 -0700129static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
Dan Williams5cbafa62009-08-26 13:01:44 -0700130{
131 struct ioat_chan_common *chan = &ioat->base;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700132 struct dma_async_tx_descriptor *tx;
Dan Williams5cbafa62009-08-26 13:01:44 -0700133 struct ioat_ring_ent *desc;
134 bool seen_current = false;
135 u16 active;
136 int i;
Dan Williams5cbafa62009-08-26 13:01:44 -0700137
Dan Williams6df91832009-09-08 12:00:55 -0700138 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
139 __func__, ioat->head, ioat->tail, ioat->issued);
140
Dan Williams5cbafa62009-08-26 13:01:44 -0700141 active = ioat2_ring_active(ioat);
142 for (i = 0; i < active && !seen_current; i++) {
143 prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
144 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
145 tx = &desc->txd;
Dan Williams6df91832009-09-08 12:00:55 -0700146 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700147 if (tx->cookie) {
148 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
149 chan->completed_cookie = tx->cookie;
150 tx->cookie = 0;
151 if (tx->callback) {
152 tx->callback(tx->callback_param);
153 tx->callback = NULL;
154 }
155 }
156
157 if (tx->phys == phys_complete)
158 seen_current = true;
159 }
160 ioat->tail += i;
Dan Williamsaa75db02010-03-03 21:21:10 -0700161 BUG_ON(active && !seen_current); /* no active descs have written a completion? */
Dan Williams5cbafa62009-08-26 13:01:44 -0700162
163 chan->last_completion = phys_complete;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700164 if (ioat->head == ioat->tail) {
165 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
166 __func__);
167 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
Dan Williamsa3092182009-09-08 12:02:01 -0700168 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700169 }
170}
Dan Williams5cbafa62009-08-26 13:01:44 -0700171
Dan Williams09c8a5b2009-09-08 12:01:49 -0700172/**
173 * ioat2_cleanup - clean finished descriptors (advance tail pointer)
174 * @chan: ioat channel to be cleaned up
175 */
176static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
177{
178 struct ioat_chan_common *chan = &ioat->base;
179 unsigned long phys_complete;
180
181 prefetch(chan->completion);
182
183 if (!spin_trylock_bh(&chan->cleanup_lock))
184 return;
185
186 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
187 spin_unlock_bh(&chan->cleanup_lock);
188 return;
189 }
190
191 if (!spin_trylock_bh(&ioat->ring_lock)) {
192 spin_unlock_bh(&chan->cleanup_lock);
193 return;
194 }
195
196 __cleanup(ioat, phys_complete);
197
198 spin_unlock_bh(&ioat->ring_lock);
Dan Williams5cbafa62009-08-26 13:01:44 -0700199 spin_unlock_bh(&chan->cleanup_lock);
200}
201
Dan Williamse3232712009-09-08 17:43:02 -0700202void ioat2_cleanup_tasklet(unsigned long data)
Dan Williams5cbafa62009-08-26 13:01:44 -0700203{
204 struct ioat2_dma_chan *ioat = (void *) data;
205
206 ioat2_cleanup(ioat);
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700207 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
Dan Williams5cbafa62009-08-26 13:01:44 -0700208}
209
Dan Williamsbf40a682009-09-08 17:42:55 -0700210void __ioat2_restart_chan(struct ioat2_dma_chan *ioat)
Dan Williams09c8a5b2009-09-08 12:01:49 -0700211{
212 struct ioat_chan_common *chan = &ioat->base;
213
214 /* set the tail to be re-issued */
215 ioat->issued = ioat->tail;
216 ioat->dmacount = 0;
217 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
218 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
219
220 dev_dbg(to_dev(chan),
221 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
222 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
223
224 if (ioat2_ring_pending(ioat)) {
225 struct ioat_ring_ent *desc;
226
227 desc = ioat2_get_ring_ent(ioat, ioat->tail);
228 ioat2_set_chainaddr(ioat, desc->txd.phys);
229 __ioat2_issue_pending(ioat);
230 } else
231 __ioat2_start_null_desc(ioat);
232}
233
Dan Williamsa6d52d72009-12-19 15:36:02 -0700234int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo)
Dan Williams09c8a5b2009-09-08 12:01:49 -0700235{
Dan Williamsa6d52d72009-12-19 15:36:02 -0700236 unsigned long end = jiffies + tmo;
237 int err = 0;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700238 u32 status;
239
240 status = ioat_chansts(chan);
241 if (is_ioat_active(status) || is_ioat_idle(status))
242 ioat_suspend(chan);
243 while (is_ioat_active(status) || is_ioat_idle(status)) {
Dan Williamsa6d52d72009-12-19 15:36:02 -0700244 if (end && time_after(jiffies, end)) {
245 err = -ETIMEDOUT;
246 break;
247 }
Dan Williams09c8a5b2009-09-08 12:01:49 -0700248 status = ioat_chansts(chan);
249 cpu_relax();
250 }
251
Dan Williamsa6d52d72009-12-19 15:36:02 -0700252 return err;
253}
254
255int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo)
256{
257 unsigned long end = jiffies + tmo;
258 int err = 0;
259
260 ioat_reset(chan);
261 while (ioat_reset_pending(chan)) {
262 if (end && time_after(jiffies, end)) {
263 err = -ETIMEDOUT;
264 break;
265 }
266 cpu_relax();
267 }
268
269 return err;
270}
271
272static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
273{
274 struct ioat_chan_common *chan = &ioat->base;
275 unsigned long phys_complete;
276
277 ioat2_quiesce(chan, 0);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700278 if (ioat_cleanup_preamble(chan, &phys_complete))
279 __cleanup(ioat, phys_complete);
280
Dan Williamsbf40a682009-09-08 17:42:55 -0700281 __ioat2_restart_chan(ioat);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700282}
283
Dan Williamse3232712009-09-08 17:43:02 -0700284void ioat2_timer_event(unsigned long data)
Dan Williams09c8a5b2009-09-08 12:01:49 -0700285{
286 struct ioat2_dma_chan *ioat = (void *) data;
287 struct ioat_chan_common *chan = &ioat->base;
288
289 spin_lock_bh(&chan->cleanup_lock);
290 if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
291 unsigned long phys_complete;
292 u64 status;
293
294 spin_lock_bh(&ioat->ring_lock);
295 status = ioat_chansts(chan);
296
297 /* when halted due to errors check for channel
298 * programming errors before advancing the completion state
299 */
300 if (is_ioat_halted(status)) {
301 u32 chanerr;
302
303 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
Dan Williamsb57014d2009-11-19 17:10:07 -0700304 dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
305 __func__, chanerr);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700306 BUG_ON(is_ioat_bug(chanerr));
307 }
308
309 /* if we haven't made progress and we have already
310 * acknowledged a pending completion once, then be more
311 * forceful with a restart
312 */
313 if (ioat_cleanup_preamble(chan, &phys_complete))
314 __cleanup(ioat, phys_complete);
315 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
316 ioat2_restart_channel(ioat);
317 else {
318 set_bit(IOAT_COMPLETION_ACK, &chan->state);
319 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
320 }
321 spin_unlock_bh(&ioat->ring_lock);
Dan Williamsa3092182009-09-08 12:02:01 -0700322 } else {
323 u16 active;
324
325 /* if the ring is idle, empty, and oversized try to step
326 * down the size
327 */
328 spin_lock_bh(&ioat->ring_lock);
329 active = ioat2_ring_active(ioat);
330 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
331 reshape_ring(ioat, ioat->alloc_order-1);
332 spin_unlock_bh(&ioat->ring_lock);
333
334 /* keep shrinking until we get back to our minimum
335 * default size
336 */
337 if (ioat->alloc_order > ioat_get_alloc_order())
338 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700339 }
340 spin_unlock_bh(&chan->cleanup_lock);
341}
342
Dan Williamsa6d52d72009-12-19 15:36:02 -0700343static int ioat2_reset_hw(struct ioat_chan_common *chan)
344{
345 /* throw away whatever the channel was doing and get it initialized */
346 u32 chanerr;
347
348 ioat2_quiesce(chan, msecs_to_jiffies(100));
349
350 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
351 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
352
353 return ioat2_reset_sync(chan, msecs_to_jiffies(200));
354}
355
Dan Williams5cbafa62009-08-26 13:01:44 -0700356/**
357 * ioat2_enumerate_channels - find and initialize the device's channels
358 * @device: the device to be enumerated
359 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700360int ioat2_enumerate_channels(struct ioatdma_device *device)
Dan Williams5cbafa62009-08-26 13:01:44 -0700361{
362 struct ioat2_dma_chan *ioat;
363 struct device *dev = &device->pdev->dev;
364 struct dma_device *dma = &device->common;
365 u8 xfercap_log;
366 int i;
367
368 INIT_LIST_HEAD(&dma->channels);
369 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
Dan Williamsbb320782009-09-08 12:01:14 -0700370 dma->chancnt &= 0x1f; /* bits [4:0] valid */
371 if (dma->chancnt > ARRAY_SIZE(device->idx)) {
372 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
373 dma->chancnt, ARRAY_SIZE(device->idx));
374 dma->chancnt = ARRAY_SIZE(device->idx);
375 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700376 xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
Dan Williamsbb320782009-09-08 12:01:14 -0700377 xfercap_log &= 0x1f; /* bits [4:0] valid */
Dan Williams5cbafa62009-08-26 13:01:44 -0700378 if (xfercap_log == 0)
379 return 0;
Dan Williams6df91832009-09-08 12:00:55 -0700380 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
Dan Williams5cbafa62009-08-26 13:01:44 -0700381
382 /* FIXME which i/oat version is i7300? */
383#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
384 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
385 dma->chancnt--;
386#endif
387 for (i = 0; i < dma->chancnt; i++) {
388 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
389 if (!ioat)
390 break;
391
392 ioat_init_channel(device, &ioat->base, i,
Dan Williamsbf40a682009-09-08 17:42:55 -0700393 device->timer_fn,
394 device->cleanup_tasklet,
Dan Williams5cbafa62009-08-26 13:01:44 -0700395 (unsigned long) ioat);
396 ioat->xfercap_log = xfercap_log;
397 spin_lock_init(&ioat->ring_lock);
Dan Williamsa6d52d72009-12-19 15:36:02 -0700398 if (device->reset_hw(&ioat->base)) {
399 i = 0;
400 break;
401 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700402 }
403 dma->chancnt = i;
404 return i;
405}
406
407static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
408{
409 struct dma_chan *c = tx->chan;
410 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700411 struct ioat_chan_common *chan = &ioat->base;
Dan Williams5cbafa62009-08-26 13:01:44 -0700412 dma_cookie_t cookie = c->cookie;
413
414 cookie++;
415 if (cookie < 0)
416 cookie = 1;
417 tx->cookie = cookie;
418 c->cookie = cookie;
Dan Williams6df91832009-09-08 12:00:55 -0700419 dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
420
Dan Williams09c8a5b2009-09-08 12:01:49 -0700421 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
422 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
Dan Williams5cbafa62009-08-26 13:01:44 -0700423 ioat2_update_pending(ioat);
424 spin_unlock_bh(&ioat->ring_lock);
425
426 return cookie;
427}
428
Dan Williamsa3092182009-09-08 12:02:01 -0700429static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
Dan Williams5cbafa62009-08-26 13:01:44 -0700430{
431 struct ioat_dma_descriptor *hw;
432 struct ioat_ring_ent *desc;
433 struct ioatdma_device *dma;
434 dma_addr_t phys;
435
436 dma = to_ioatdma_device(chan->device);
Dan Williamsa3092182009-09-08 12:02:01 -0700437 hw = pci_pool_alloc(dma->dma_pool, flags, &phys);
Dan Williams5cbafa62009-08-26 13:01:44 -0700438 if (!hw)
439 return NULL;
440 memset(hw, 0, sizeof(*hw));
441
Dan Williams162b96e2009-09-08 17:53:04 -0700442 desc = kmem_cache_alloc(ioat2_cache, flags);
Dan Williams5cbafa62009-08-26 13:01:44 -0700443 if (!desc) {
444 pci_pool_free(dma->dma_pool, hw, phys);
445 return NULL;
446 }
Dan Williams162b96e2009-09-08 17:53:04 -0700447 memset(desc, 0, sizeof(*desc));
Dan Williams5cbafa62009-08-26 13:01:44 -0700448
449 dma_async_tx_descriptor_init(&desc->txd, chan);
450 desc->txd.tx_submit = ioat2_tx_submit_unlock;
451 desc->hw = hw;
452 desc->txd.phys = phys;
453 return desc;
454}
455
456static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
457{
458 struct ioatdma_device *dma;
459
460 dma = to_ioatdma_device(chan->device);
461 pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
Dan Williams162b96e2009-09-08 17:53:04 -0700462 kmem_cache_free(ioat2_cache, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700463}
464
Dan Williamsa3092182009-09-08 12:02:01 -0700465static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
466{
467 struct ioat_ring_ent **ring;
468 int descs = 1 << order;
469 int i;
470
471 if (order > ioat_get_max_alloc_order())
472 return NULL;
473
474 /* allocate the array to hold the software ring */
475 ring = kcalloc(descs, sizeof(*ring), flags);
476 if (!ring)
477 return NULL;
478 for (i = 0; i < descs; i++) {
479 ring[i] = ioat2_alloc_ring_ent(c, flags);
480 if (!ring[i]) {
481 while (i--)
482 ioat2_free_ring_ent(ring[i], c);
483 kfree(ring);
484 return NULL;
485 }
486 set_desc_id(ring[i], i);
487 }
488
489 /* link descs */
490 for (i = 0; i < descs-1; i++) {
491 struct ioat_ring_ent *next = ring[i+1];
492 struct ioat_dma_descriptor *hw = ring[i]->hw;
493
494 hw->next = next->txd.phys;
495 }
496 ring[i]->hw->next = ring[0]->txd.phys;
497
498 return ring;
499}
500
Dan Williams5cbafa62009-08-26 13:01:44 -0700501/* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
502 * @chan: channel to be initialized
503 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700504int ioat2_alloc_chan_resources(struct dma_chan *c)
Dan Williams5cbafa62009-08-26 13:01:44 -0700505{
506 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
507 struct ioat_chan_common *chan = &ioat->base;
508 struct ioat_ring_ent **ring;
Dan Williamsa3092182009-09-08 12:02:01 -0700509 int order;
Dan Williams5cbafa62009-08-26 13:01:44 -0700510
511 /* have we already been set up? */
512 if (ioat->ring)
513 return 1 << ioat->alloc_order;
514
515 /* Setup register to interrupt and write completion status on error */
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700516 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
Dan Williams5cbafa62009-08-26 13:01:44 -0700517
Dan Williams5cbafa62009-08-26 13:01:44 -0700518 /* allocate a completion writeback area */
519 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700520 chan->completion = pci_pool_alloc(chan->device->completion_pool,
521 GFP_KERNEL, &chan->completion_dma);
522 if (!chan->completion)
Dan Williams5cbafa62009-08-26 13:01:44 -0700523 return -ENOMEM;
524
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700525 memset(chan->completion, 0, sizeof(*chan->completion));
526 writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
Dan Williams5cbafa62009-08-26 13:01:44 -0700527 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700528 writel(((u64) chan->completion_dma) >> 32,
Dan Williams5cbafa62009-08-26 13:01:44 -0700529 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
530
Dan Williamsa3092182009-09-08 12:02:01 -0700531 order = ioat_get_alloc_order();
532 ring = ioat2_alloc_ring(c, order, GFP_KERNEL);
Dan Williams5cbafa62009-08-26 13:01:44 -0700533 if (!ring)
534 return -ENOMEM;
Dan Williams5cbafa62009-08-26 13:01:44 -0700535
536 spin_lock_bh(&ioat->ring_lock);
537 ioat->ring = ring;
538 ioat->head = 0;
539 ioat->issued = 0;
540 ioat->tail = 0;
Dan Williamsa3092182009-09-08 12:02:01 -0700541 ioat->alloc_order = order;
Dan Williams5cbafa62009-08-26 13:01:44 -0700542 spin_unlock_bh(&ioat->ring_lock);
543
544 tasklet_enable(&chan->cleanup_task);
545 ioat2_start_null_desc(ioat);
546
Dan Williamsa3092182009-09-08 12:02:01 -0700547 return 1 << ioat->alloc_order;
548}
549
Dan Williamsbf40a682009-09-08 17:42:55 -0700550bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
Dan Williamsa3092182009-09-08 12:02:01 -0700551{
552 /* reshape differs from normal ring allocation in that we want
553 * to allocate a new software ring while only
554 * extending/truncating the hardware ring
555 */
556 struct ioat_chan_common *chan = &ioat->base;
557 struct dma_chan *c = &chan->common;
558 const u16 curr_size = ioat2_ring_mask(ioat) + 1;
559 const u16 active = ioat2_ring_active(ioat);
560 const u16 new_size = 1 << order;
561 struct ioat_ring_ent **ring;
562 u16 i;
563
564 if (order > ioat_get_max_alloc_order())
565 return false;
566
567 /* double check that we have at least 1 free descriptor */
568 if (active == curr_size)
569 return false;
570
571 /* when shrinking, verify that we can hold the current active
572 * set in the new ring
573 */
574 if (active >= new_size)
575 return false;
576
577 /* allocate the array to hold the software ring */
578 ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
579 if (!ring)
580 return false;
581
582 /* allocate/trim descriptors as needed */
583 if (new_size > curr_size) {
584 /* copy current descriptors to the new ring */
585 for (i = 0; i < curr_size; i++) {
586 u16 curr_idx = (ioat->tail+i) & (curr_size-1);
587 u16 new_idx = (ioat->tail+i) & (new_size-1);
588
589 ring[new_idx] = ioat->ring[curr_idx];
590 set_desc_id(ring[new_idx], new_idx);
591 }
592
593 /* add new descriptors to the ring */
594 for (i = curr_size; i < new_size; i++) {
595 u16 new_idx = (ioat->tail+i) & (new_size-1);
596
597 ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT);
598 if (!ring[new_idx]) {
599 while (i--) {
600 u16 new_idx = (ioat->tail+i) & (new_size-1);
601
602 ioat2_free_ring_ent(ring[new_idx], c);
603 }
604 kfree(ring);
605 return false;
606 }
607 set_desc_id(ring[new_idx], new_idx);
608 }
609
610 /* hw link new descriptors */
611 for (i = curr_size-1; i < new_size; i++) {
612 u16 new_idx = (ioat->tail+i) & (new_size-1);
613 struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)];
614 struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
615
616 hw->next = next->txd.phys;
617 }
618 } else {
619 struct ioat_dma_descriptor *hw;
620 struct ioat_ring_ent *next;
621
622 /* copy current descriptors to the new ring, dropping the
623 * removed descriptors
624 */
625 for (i = 0; i < new_size; i++) {
626 u16 curr_idx = (ioat->tail+i) & (curr_size-1);
627 u16 new_idx = (ioat->tail+i) & (new_size-1);
628
629 ring[new_idx] = ioat->ring[curr_idx];
630 set_desc_id(ring[new_idx], new_idx);
631 }
632
633 /* free deleted descriptors */
634 for (i = new_size; i < curr_size; i++) {
635 struct ioat_ring_ent *ent;
636
637 ent = ioat2_get_ring_ent(ioat, ioat->tail+i);
638 ioat2_free_ring_ent(ent, c);
639 }
640
641 /* fix up hardware ring */
642 hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw;
643 next = ring[(ioat->tail+new_size) & (new_size-1)];
644 hw->next = next->txd.phys;
645 }
646
647 dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
648 __func__, new_size);
649
650 kfree(ioat->ring);
651 ioat->ring = ring;
652 ioat->alloc_order = order;
653
654 return true;
Dan Williams5cbafa62009-08-26 13:01:44 -0700655}
656
657/**
658 * ioat2_alloc_and_lock - common descriptor alloc boilerplate for ioat2,3 ops
659 * @idx: gets starting descriptor index on successful allocation
660 * @ioat: ioat2,3 channel (ring) to operate on
661 * @num_descs: allocation length
662 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700663int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs)
Dan Williams5cbafa62009-08-26 13:01:44 -0700664{
665 struct ioat_chan_common *chan = &ioat->base;
666
667 spin_lock_bh(&ioat->ring_lock);
Dan Williamsa3092182009-09-08 12:02:01 -0700668 /* never allow the last descriptor to be consumed, we need at
669 * least one free at all times to allow for on-the-fly ring
670 * resizing.
671 */
672 while (unlikely(ioat2_ring_space(ioat) <= num_descs)) {
673 if (reshape_ring(ioat, ioat->alloc_order + 1) &&
674 ioat2_ring_space(ioat) > num_descs)
675 break;
676
Dan Williams5cbafa62009-08-26 13:01:44 -0700677 if (printk_ratelimit())
678 dev_dbg(to_dev(chan),
679 "%s: ring full! num_descs: %d (%x:%x:%x)\n",
680 __func__, num_descs, ioat->head, ioat->tail,
681 ioat->issued);
682 spin_unlock_bh(&ioat->ring_lock);
683
Dan Williams09c8a5b2009-09-08 12:01:49 -0700684 /* progress reclaim in the allocation failure case we
685 * may be called under bh_disabled so we need to trigger
686 * the timer event directly
687 */
688 spin_lock_bh(&chan->cleanup_lock);
689 if (jiffies > chan->timer.expires &&
690 timer_pending(&chan->timer)) {
Dan Williamsbf40a682009-09-08 17:42:55 -0700691 struct ioatdma_device *device = chan->device;
692
Dan Williams09c8a5b2009-09-08 12:01:49 -0700693 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
694 spin_unlock_bh(&chan->cleanup_lock);
Dan Williamsbf40a682009-09-08 17:42:55 -0700695 device->timer_fn((unsigned long) ioat);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700696 } else
697 spin_unlock_bh(&chan->cleanup_lock);
Dan Williams5cbafa62009-08-26 13:01:44 -0700698 return -ENOMEM;
699 }
700
701 dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
702 __func__, num_descs, ioat->head, ioat->tail, ioat->issued);
703
704 *idx = ioat2_desc_alloc(ioat, num_descs);
705 return 0; /* with ioat->ring_lock held */
706}
707
Dan Williamsbf40a682009-09-08 17:42:55 -0700708struct dma_async_tx_descriptor *
Dan Williams5cbafa62009-08-26 13:01:44 -0700709ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
710 dma_addr_t dma_src, size_t len, unsigned long flags)
711{
712 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
713 struct ioat_dma_descriptor *hw;
714 struct ioat_ring_ent *desc;
715 dma_addr_t dst = dma_dest;
716 dma_addr_t src = dma_src;
717 size_t total_len = len;
718 int num_descs;
719 u16 idx;
720 int i;
721
722 num_descs = ioat2_xferlen_to_descs(ioat, len);
723 if (likely(num_descs) &&
724 ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
725 /* pass */;
726 else
727 return NULL;
Andrew Mortonf477f5b2009-09-21 09:17:58 -0700728 i = 0;
729 do {
Dan Williams5cbafa62009-08-26 13:01:44 -0700730 size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
731
732 desc = ioat2_get_ring_ent(ioat, idx + i);
733 hw = desc->hw;
734
735 hw->size = copy;
736 hw->ctl = 0;
737 hw->src_addr = src;
738 hw->dst_addr = dst;
739
740 len -= copy;
741 dst += copy;
742 src += copy;
Dan Williams6df91832009-09-08 12:00:55 -0700743 dump_desc_dbg(ioat, desc);
Andrew Mortonf477f5b2009-09-21 09:17:58 -0700744 } while (++i < num_descs);
Dan Williams5cbafa62009-08-26 13:01:44 -0700745
746 desc->txd.flags = flags;
747 desc->len = total_len;
748 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
Dan Williams128f2d52009-09-08 17:42:53 -0700749 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
Dan Williams5cbafa62009-08-26 13:01:44 -0700750 hw->ctl_f.compl_write = 1;
Dan Williams6df91832009-09-08 12:00:55 -0700751 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700752 /* we leave the channel locked to ensure in order submission */
753
754 return &desc->txd;
755}
756
757/**
758 * ioat2_free_chan_resources - release all the descriptors
759 * @chan: the channel to be cleaned
760 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700761void ioat2_free_chan_resources(struct dma_chan *c)
Dan Williams5cbafa62009-08-26 13:01:44 -0700762{
763 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
764 struct ioat_chan_common *chan = &ioat->base;
Dan Williamsbf40a682009-09-08 17:42:55 -0700765 struct ioatdma_device *device = chan->device;
Dan Williams5cbafa62009-08-26 13:01:44 -0700766 struct ioat_ring_ent *desc;
767 const u16 total_descs = 1 << ioat->alloc_order;
768 int descs;
769 int i;
770
771 /* Before freeing channel resources first check
772 * if they have been previously allocated for this channel.
773 */
774 if (!ioat->ring)
775 return;
776
777 tasklet_disable(&chan->cleanup_task);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700778 del_timer_sync(&chan->timer);
Dan Williamsbf40a682009-09-08 17:42:55 -0700779 device->cleanup_tasklet((unsigned long) ioat);
Dan Williamsa6d52d72009-12-19 15:36:02 -0700780 device->reset_hw(chan);
Dan Williams5cbafa62009-08-26 13:01:44 -0700781
782 spin_lock_bh(&ioat->ring_lock);
783 descs = ioat2_ring_space(ioat);
Dan Williams6df91832009-09-08 12:00:55 -0700784 dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
Dan Williams5cbafa62009-08-26 13:01:44 -0700785 for (i = 0; i < descs; i++) {
786 desc = ioat2_get_ring_ent(ioat, ioat->head + i);
787 ioat2_free_ring_ent(desc, c);
788 }
789
790 if (descs < total_descs)
791 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
792 total_descs - descs);
793
794 for (i = 0; i < total_descs - descs; i++) {
795 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
Dan Williams6df91832009-09-08 12:00:55 -0700796 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700797 ioat2_free_ring_ent(desc, c);
798 }
799
800 kfree(ioat->ring);
801 ioat->ring = NULL;
802 ioat->alloc_order = 0;
Dan Williamsbf40a682009-09-08 17:42:55 -0700803 pci_pool_free(device->completion_pool, chan->completion,
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700804 chan->completion_dma);
Dan Williams5cbafa62009-08-26 13:01:44 -0700805 spin_unlock_bh(&ioat->ring_lock);
806
807 chan->last_completion = 0;
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700808 chan->completion_dma = 0;
Dan Williams5cbafa62009-08-26 13:01:44 -0700809 ioat->dmacount = 0;
Dan Williams5cbafa62009-08-26 13:01:44 -0700810}
811
Dan Williamsbf40a682009-09-08 17:42:55 -0700812enum dma_status
Dan Williams5cbafa62009-08-26 13:01:44 -0700813ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie,
814 dma_cookie_t *done, dma_cookie_t *used)
815{
816 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
Dan Williamsbf40a682009-09-08 17:42:55 -0700817 struct ioatdma_device *device = ioat->base.device;
Dan Williams5cbafa62009-08-26 13:01:44 -0700818
819 if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
820 return DMA_SUCCESS;
821
Dan Williamsbf40a682009-09-08 17:42:55 -0700822 device->cleanup_tasklet((unsigned long) ioat);
Dan Williams5cbafa62009-08-26 13:01:44 -0700823
824 return ioat_is_complete(c, cookie, done, used);
825}
826
Dan Williams5669e312009-09-08 17:42:56 -0700827static ssize_t ring_size_show(struct dma_chan *c, char *page)
828{
829 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
830
831 return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1);
832}
833static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
834
835static ssize_t ring_active_show(struct dma_chan *c, char *page)
836{
837 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
838
839 /* ...taken outside the lock, no need to be precise */
840 return sprintf(page, "%d\n", ioat2_ring_active(ioat));
841}
842static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
843
844static struct attribute *ioat2_attrs[] = {
845 &ring_size_attr.attr,
846 &ring_active_attr.attr,
847 &ioat_cap_attr.attr,
848 &ioat_version_attr.attr,
849 NULL,
850};
851
852struct kobj_type ioat2_ktype = {
853 .sysfs_ops = &ioat_sysfs_ops,
854 .default_attrs = ioat2_attrs,
855};
856
Dan Williams345d8522009-09-08 12:01:30 -0700857int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca)
Dan Williams5cbafa62009-08-26 13:01:44 -0700858{
859 struct pci_dev *pdev = device->pdev;
860 struct dma_device *dma;
861 struct dma_chan *c;
862 struct ioat_chan_common *chan;
863 int err;
864
865 device->enumerate_channels = ioat2_enumerate_channels;
Dan Williamsa6d52d72009-12-19 15:36:02 -0700866 device->reset_hw = ioat2_reset_hw;
Dan Williamsbf40a682009-09-08 17:42:55 -0700867 device->cleanup_tasklet = ioat2_cleanup_tasklet;
868 device->timer_fn = ioat2_timer_event;
Dan Williams9de6fc72009-09-08 17:42:58 -0700869 device->self_test = ioat_dma_self_test;
Dan Williams5cbafa62009-08-26 13:01:44 -0700870 dma = &device->common;
871 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
872 dma->device_issue_pending = ioat2_issue_pending;
873 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
874 dma->device_free_chan_resources = ioat2_free_chan_resources;
875 dma->device_is_tx_complete = ioat2_is_complete;
876
877 err = ioat_probe(device);
878 if (err)
879 return err;
880 ioat_set_tcp_copy_break(2048);
881
882 list_for_each_entry(c, &dma->channels, device_node) {
883 chan = to_chan_common(c);
884 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
885 chan->reg_base + IOAT_DCACTRL_OFFSET);
886 }
887
888 err = ioat_register(device);
889 if (err)
890 return err;
Dan Williams5669e312009-09-08 17:42:56 -0700891
892 ioat_kobject_add(device, &ioat2_ktype);
893
Dan Williams5cbafa62009-08-26 13:01:44 -0700894 if (dca)
895 device->dca = ioat2_dca_init(pdev, device->reg_base);
896
Dan Williams5cbafa62009-08-26 13:01:44 -0700897 return err;
898}