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gerrit-public.fairphone.software / kernel / msm / ac533457045f583acceff7927cafd49ff374c8ce / . / arch / arm / mach-msm / acpuclock-8974.c
blob: 84100196f4de18077c8d130a7743a0340b25776d [file] [log] [blame]
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1/*
Matt Wagantall2dd3f972013-01-08 12:03:43 -0800[diff] [blame]2 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
Steve Mucklef132c6c2012-06-06 18:30:57 -0700[diff] [blame]14#include <linux/module.h>
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]15#include <linux/platform_device.h>
16#include <linux/of.h>
Matt Wagantalld591bf22012-06-29 11:20:53 -0700[diff] [blame]17#include <mach/rpm-regulator-smd.h>
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]18#include <mach/msm_bus_board.h>
19#include <mach/msm_bus.h>
20#include <mach/socinfo.h>
21
22#include "acpuclock.h"
23#include "acpuclock-krait.h"
24
25/* Corner type vreg VDD values */
Matt Wagantallf06e3572012-07-27 12:45:24 -0700[diff] [blame]26#define LVL_NONE RPM_REGULATOR_CORNER_NONE
Matt Wagantalld591bf22012-06-29 11:20:53 -0700[diff] [blame]27#define LVL_LOW RPM_REGULATOR_CORNER_SVS_SOC
28#define LVL_NOM RPM_REGULATOR_CORNER_NORMAL
29#define LVL_HIGH RPM_REGULATOR_CORNER_SUPER_TURBO
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]30
Matt Wagantall1f3762d2012-06-08 19:08:48 -0700[diff] [blame]31static struct hfpll_data hfpll_data __initdata = {
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]32 .mode_offset = 0x00,
33 .l_offset = 0x04,
34 .m_offset = 0x08,
35 .n_offset = 0x0C,
Matt Wagantalla77b7f32012-07-18 16:32:01 -0700[diff] [blame]36 .has_user_reg = true,
37 .user_offset = 0x10,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]38 .config_offset = 0x14,
Matt Wagantalla77b7f32012-07-18 16:32:01 -0700[diff] [blame]39 .user_val = 0x8,
Matt Wagantall0f6e7b22012-09-26 23:36:18 -0700[diff] [blame]40 .user_vco_mask = BIT(20),
Matt Wagantalla77b7f32012-07-18 16:32:01 -0700[diff] [blame]41 .config_val = 0x04D0405D,
Matt Wagantall3c51b5d2013-04-06 12:34:20 -0700[diff] [blame]42 .has_lock_status = true,
43 .status_offset = 0x1C,
Matt Wagantalla77b7f32012-07-18 16:32:01 -0700[diff] [blame]44 .low_vco_l_max = 65,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]45 .low_vdd_l_max = 52,
Matt Wagantall87465f52012-07-23 22:03:06 -0700[diff] [blame]46 .nom_vdd_l_max = 104,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]47 .vdd[HFPLL_VDD_NONE] = LVL_NONE,
48 .vdd[HFPLL_VDD_LOW] = LVL_LOW,
49 .vdd[HFPLL_VDD_NOM] = LVL_NOM,
Matt Wagantall87465f52012-07-23 22:03:06 -0700[diff] [blame]50 .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]51};
52
Matt Wagantall1f3762d2012-06-08 19:08:48 -0700[diff] [blame]53static struct scalable scalable[] __initdata = {
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]54 [CPU0] = {
55 .hfpll_phys_base = 0xF908A000,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]56 .l2cpmr_iaddr = 0x4501,
Matt Wagantall6cd5d752012-09-27 19:56:57 -0700[diff] [blame]57 .sec_clk_sel = 2,
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]58 .vreg[VREG_CORE] = { "krait0", 1100000 },
Matt Wagantall75473eb2012-05-31 15:23:22 -0700[diff] [blame]59 .vreg[VREG_MEM] = { "krait0_mem", 1050000 },
Matt Wagantalld591bf22012-06-29 11:20:53 -0700[diff] [blame]60 .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH },
David Collinsaba4b9b2012-11-28 17:18:24 -0800[diff] [blame]61 .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]62 },
63 [CPU1] = {
64 .hfpll_phys_base = 0xF909A000,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]65 .l2cpmr_iaddr = 0x5501,
Matt Wagantall6cd5d752012-09-27 19:56:57 -0700[diff] [blame]66 .sec_clk_sel = 2,
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]67 .vreg[VREG_CORE] = { "krait1", 1100000 },
Matt Wagantall75473eb2012-05-31 15:23:22 -0700[diff] [blame]68 .vreg[VREG_MEM] = { "krait1_mem", 1050000 },
Matt Wagantalld591bf22012-06-29 11:20:53 -0700[diff] [blame]69 .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH },
David Collinsaba4b9b2012-11-28 17:18:24 -0800[diff] [blame]70 .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]71 },
72 [CPU2] = {
73 .hfpll_phys_base = 0xF90AA000,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]74 .l2cpmr_iaddr = 0x6501,
Matt Wagantall6cd5d752012-09-27 19:56:57 -0700[diff] [blame]75 .sec_clk_sel = 2,
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]76 .vreg[VREG_CORE] = { "krait2", 1100000 },
Matt Wagantall75473eb2012-05-31 15:23:22 -0700[diff] [blame]77 .vreg[VREG_MEM] = { "krait2_mem", 1050000 },
Matt Wagantalld591bf22012-06-29 11:20:53 -0700[diff] [blame]78 .vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH },
David Collinsaba4b9b2012-11-28 17:18:24 -0800[diff] [blame]79 .vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]80 },
81 [CPU3] = {
82 .hfpll_phys_base = 0xF90BA000,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]83 .l2cpmr_iaddr = 0x7501,
Matt Wagantall6cd5d752012-09-27 19:56:57 -0700[diff] [blame]84 .sec_clk_sel = 2,
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]85 .vreg[VREG_CORE] = { "krait3", 1100000 },
Matt Wagantall75473eb2012-05-31 15:23:22 -0700[diff] [blame]86 .vreg[VREG_MEM] = { "krait3_mem", 1050000 },
Matt Wagantalld591bf22012-06-29 11:20:53 -0700[diff] [blame]87 .vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH },
David Collinsaba4b9b2012-11-28 17:18:24 -0800[diff] [blame]88 .vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]89 },
90 [L2] = {
91 .hfpll_phys_base = 0xF9016000,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]92 .l2cpmr_iaddr = 0x0500,
Matt Wagantall6cd5d752012-09-27 19:56:57 -0700[diff] [blame]93 .sec_clk_sel = 2,
David Collinsaba4b9b2012-11-28 17:18:24 -0800[diff] [blame]94 .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]95 },
96};
97
Matt Wagantall63ac3882013-03-07 16:51:14 -0800[diff] [blame]98static struct msm_bus_paths bw_level_tbl_v1[] __initdata = {
Matt Wagantall545cd3e2012-12-07 13:07:16 -0800[diff] [blame]99 [0] = BW_MBPS(600), /* At least 75 MHz on bus. */
100 [1] = BW_MBPS(800), /* At least 100 MHz on bus. */
101 [2] = BW_MBPS(1200), /* At least 150 MHz on bus. */
102 [3] = BW_MBPS(1600), /* At least 200 MHz on bus. */
103 [4] = BW_MBPS(2224), /* At least 278 MHz on bus. */
104 [5] = BW_MBPS(3200), /* At least 400 MHz on bus. */
105 [6] = BW_MBPS(4448), /* At least 556 MHz on bus. */
106 [7] = BW_MBPS(6400), /* At least 800 MHz on bus. */
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]107};
108
Matt Wagantall29b7b472013-03-07 17:09:58 -0800[diff] [blame]109static struct l2_level l2_freq_tbl_v1[] __initdata = {
Matt Wagantall2dd3f972013-01-08 12:03:43 -0800[diff] [blame]110 [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
111 [1] = { { 345600, HFPLL, 2, 36 }, LVL_NOM, 950000, 1 },
112 [2] = { { 422400, HFPLL, 2, 44 }, LVL_NOM, 950000, 1 },
113 [3] = { { 499200, HFPLL, 2, 52 }, LVL_NOM, 950000, 2 },
Matt Wagantalld20d0942013-01-30 14:09:53 -0800[diff] [blame]114 [4] = { { 576000, HFPLL, 1, 30 }, LVL_NOM, 950000, 3 },
Matt Wagantall2dd3f972013-01-08 12:03:43 -0800[diff] [blame]115 [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 3 },
116 [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 3 },
Matt Wagantalld20d0942013-01-30 14:09:53 -0800[diff] [blame]117 [7] = { { 806400, HFPLL, 1, 42 }, LVL_HIGH, 1050000, 4 },
Matt Wagantall545cd3e2012-12-07 13:07:16 -0800[diff] [blame]118 [8] = { { 883200, HFPLL, 1, 46 }, LVL_HIGH, 1050000, 4 },
119 [9] = { { 960000, HFPLL, 1, 50 }, LVL_HIGH, 1050000, 4 },
Matt Wagantalld20d0942013-01-30 14:09:53 -0800[diff] [blame]120 [10] = { { 1036800, HFPLL, 1, 54 }, LVL_HIGH, 1050000, 5 },
Matt Wagantall545cd3e2012-12-07 13:07:16 -0800[diff] [blame]121 [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 5 },
Matt Wagantalld20d0942013-01-30 14:09:53 -0800[diff] [blame]122 [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 6 },
Matt Wagantall545cd3e2012-12-07 13:07:16 -0800[diff] [blame]123 [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 6 },
Matt Wagantalld20d0942013-01-30 14:09:53 -0800[diff] [blame]124 [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 7 },
Matt Wagantall545cd3e2012-12-07 13:07:16 -0800[diff] [blame]125 [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 7 },
126 [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 7 },
Stephen Boyd791bca92012-09-11 21:08:13 -0700[diff] [blame]127 { }
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]128};
129
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]130static struct acpu_level acpu_freq_tbl_v1_pvs0[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]131 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 825000, 73 },
132 { 0, { 345600, HFPLL, 2, 36 }, L2(3), 825000, 85 },
133 { 1, { 422400, HFPLL, 2, 44 }, L2(3), 825000, 104 },
134 { 0, { 499200, HFPLL, 2, 52 }, L2(6), 825000, 124 },
135 { 1, { 576000, HFPLL, 1, 30 }, L2(6), 825000, 144 },
136 { 1, { 652800, HFPLL, 1, 34 }, L2(7), 825000, 165 },
137 { 1, { 729600, HFPLL, 1, 38 }, L2(7), 825000, 186 },
138 { 0, { 806400, HFPLL, 1, 42 }, L2(10), 835000, 208 },
139 { 1, { 883200, HFPLL, 1, 46 }, L2(10), 845000, 229 },
140 { 0, { 960000, HFPLL, 1, 50 }, L2(10), 860000, 252 },
141 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 880000, 275 },
142 { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 905000, 298 },
143 { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 920000, 321 },
144 { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 940000, 346 },
145 { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 960000, 371 },
146 { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 980000, 397 },
147 { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 995000, 423 },
148 { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 1015000, 450 },
149 { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 1030000, 477 },
150 { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1050000, 506 },
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]151 { 0, { 0 } }
152};
153
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]154static struct acpu_level acpu_freq_tbl_v1_pvs1[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]155 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 825000, 73 },
156 { 0, { 345600, HFPLL, 2, 36 }, L2(3), 825000, 85 },
157 { 1, { 422400, HFPLL, 2, 44 }, L2(3), 825000, 104 },
158 { 0, { 499200, HFPLL, 2, 52 }, L2(6), 825000, 124 },
159 { 1, { 576000, HFPLL, 1, 30 }, L2(6), 825000, 144 },
160 { 1, { 652800, HFPLL, 1, 34 }, L2(7), 825000, 165 },
161 { 1, { 729600, HFPLL, 1, 38 }, L2(7), 825000, 186 },
162 { 0, { 806400, HFPLL, 1, 42 }, L2(10), 835000, 208 },
163 { 1, { 883200, HFPLL, 1, 46 }, L2(10), 845000, 229 },
164 { 0, { 960000, HFPLL, 1, 50 }, L2(10), 860000, 252 },
165 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 880000, 275 },
166 { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 905000, 298 },
167 { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 920000, 321 },
168 { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 940000, 346 },
169 { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 960000, 371 },
170 { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 980000, 397 },
171 { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 995000, 423 },
172 { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 1015000, 450 },
173 { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 1030000, 477 },
174 { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1050000, 506 },
Matt Wagantall7b14d282013-01-15 14:49:34 -0800[diff] [blame]175 { 0, { 0 } }
176};
177
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]178static struct acpu_level acpu_freq_tbl_v1_pvs2[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]179 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 825000, 73 },
180 { 0, { 345600, HFPLL, 2, 36 }, L2(3), 825000, 85 },
181 { 1, { 422400, HFPLL, 2, 44 }, L2(3), 825000, 104 },
182 { 0, { 499200, HFPLL, 2, 52 }, L2(6), 825000, 124 },
183 { 1, { 576000, HFPLL, 1, 30 }, L2(6), 825000, 144 },
184 { 1, { 652800, HFPLL, 1, 34 }, L2(7), 825000, 165 },
185 { 1, { 729600, HFPLL, 1, 38 }, L2(7), 825000, 186 },
186 { 0, { 806400, HFPLL, 1, 42 }, L2(10), 825000, 208 },
187 { 1, { 883200, HFPLL, 1, 46 }, L2(10), 825000, 229 },
188 { 0, { 960000, HFPLL, 1, 50 }, L2(10), 835000, 252 },
189 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 855000, 275 },
190 { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 875000, 298 },
191 { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 895000, 321 },
192 { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 915000, 346 },
193 { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 930000, 371 },
194 { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 945000, 397 },
195 { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 960000, 423 },
196 { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 975000, 450 },
197 { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 990000, 477 },
198 { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1000000, 506 },
Matt Wagantall7b14d282013-01-15 14:49:34 -0800[diff] [blame]199 { 0, { 0 } }
200};
201
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]202static struct acpu_level acpu_freq_tbl_v1_pvs3[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]203 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 825000, 73 },
204 { 0, { 345600, HFPLL, 2, 36 }, L2(3), 825000, 85 },
205 { 1, { 422400, HFPLL, 2, 44 }, L2(3), 825000, 104 },
206 { 0, { 499200, HFPLL, 2, 52 }, L2(6), 825000, 124 },
207 { 1, { 576000, HFPLL, 1, 30 }, L2(6), 825000, 144 },
208 { 1, { 652800, HFPLL, 1, 34 }, L2(7), 825000, 165 },
209 { 1, { 729600, HFPLL, 1, 38 }, L2(7), 825000, 186 },
210 { 0, { 806400, HFPLL, 1, 42 }, L2(10), 825000, 208 },
211 { 1, { 883200, HFPLL, 1, 46 }, L2(10), 825000, 229 },
212 { 0, { 960000, HFPLL, 1, 50 }, L2(10), 835000, 252 },
213 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 855000, 275 },
214 { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 875000, 298 },
215 { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 895000, 321 },
216 { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 915000, 346 },
217 { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 930000, 371 },
218 { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 945000, 397 },
219 { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 960000, 423 },
220 { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 975000, 450 },
221 { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 990000, 477 },
222 { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1000000, 506 },
Matt Wagantall7b14d282013-01-15 14:49:34 -0800[diff] [blame]223 { 0, { 0 } }
224};
225
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]226static struct acpu_level acpu_freq_tbl_v1_pvs4[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]227 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 825000, 73 },
228 { 0, { 345600, HFPLL, 2, 36 }, L2(3), 825000, 85 },
229 { 1, { 422400, HFPLL, 2, 44 }, L2(3), 825000, 104 },
230 { 0, { 499200, HFPLL, 2, 52 }, L2(6), 825000, 124 },
231 { 1, { 576000, HFPLL, 1, 30 }, L2(6), 825000, 144 },
232 { 1, { 652800, HFPLL, 1, 34 }, L2(7), 825000, 165 },
233 { 1, { 729600, HFPLL, 1, 38 }, L2(7), 825000, 186 },
234 { 0, { 806400, HFPLL, 1, 42 }, L2(10), 825000, 208 },
235 { 1, { 883200, HFPLL, 1, 46 }, L2(10), 825000, 229 },
236 { 0, { 960000, HFPLL, 1, 50 }, L2(10), 825000, 252 },
237 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 825000, 275 },
238 { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 835000, 298 },
239 { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 855000, 321 },
240 { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 870000, 346 },
241 { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 885000, 371 },
242 { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 900000, 397 },
243 { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 423 },
244 { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 925000, 450 },
245 { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 940000, 477 },
246 { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 950000, 506 },
Matt Wagantall7b14d282013-01-15 14:49:34 -0800[diff] [blame]247 { 0, { 0 } }
248};
249
Matt Wagantall63ac3882013-03-07 16:51:14 -0800[diff] [blame]250static struct msm_bus_paths bw_level_tbl_v2[] __initdata = {
251 [0] = BW_MBPS(600), /* At least 75 MHz on bus. */
252 [1] = BW_MBPS(800), /* At least 100 MHz on bus. */
253 [2] = BW_MBPS(1200), /* At least 150 MHz on bus. */
254 [3] = BW_MBPS(1600), /* At least 200 MHz on bus. */
255 [4] = BW_MBPS(2456), /* At least 307 MHz on bus. */
256 [5] = BW_MBPS(3680), /* At least 460 MHz on bus. */
257 [6] = BW_MBPS(4912), /* At least 614 MHz on bus. */
258 [7] = BW_MBPS(6400), /* At least 800 MHz on bus. */
259 [8] = BW_MBPS(7448), /* At least 931 MHz on bus. */
260};
261
Matt Wagantall29b7b472013-03-07 17:09:58 -0800[diff] [blame]262static struct l2_level l2_freq_tbl_v2[] __initdata = {
263 [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
Matt Wagantall6f2dcea2013-03-22 14:57:44 -0700[diff] [blame]264 [1] = { { 345600, HFPLL, 2, 36 }, LVL_LOW, 950000, 1 },
Matt Wagantall17df6732013-04-03 19:26:32 -0700[diff] [blame]265 [2] = { { 422400, HFPLL, 2, 44 }, LVL_LOW, 950000, 2 },
266 [3] = { { 499200, HFPLL, 2, 52 }, LVL_LOW, 950000, 3 },
267 [4] = { { 576000, HFPLL, 1, 30 }, LVL_LOW, 950000, 4 },
268 [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 4 },
269 [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 4 },
Matt Wagantall6f2dcea2013-03-22 14:57:44 -0700[diff] [blame]270 [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 4 },
Matt Wagantall17df6732013-04-03 19:26:32 -0700[diff] [blame]271 [8] = { { 883200, HFPLL, 1, 46 }, LVL_NOM, 950000, 5 },
272 [9] = { { 960000, HFPLL, 1, 50 }, LVL_NOM, 950000, 5 },
Dilip Gudlur5610b882013-06-20 16:05:21 -0700[diff] [blame]273 [10] = { { 1036800, HFPLL, 1, 54 }, LVL_NOM, 950000, 5 },
Matt Wagantall17df6732013-04-03 19:26:32 -0700[diff] [blame]274 [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 6 },
Matt Wagantall29b7b472013-03-07 17:09:58 -0800[diff] [blame]275 [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 6 },
Matt Wagantall17df6732013-04-03 19:26:32 -0700[diff] [blame]276 [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 7 },
Matt Wagantall29b7b472013-03-07 17:09:58 -0800[diff] [blame]277 [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 7 },
278 [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 7 },
279 [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 7 },
Matt Wagantall17df6732013-04-03 19:26:32 -0700[diff] [blame]280 [17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 7 },
281 [18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 7 },
Matt Wagantall63ac3882013-03-07 16:51:14 -0800[diff] [blame]282 [19] = { { 1728000, HFPLL, 1, 90 }, LVL_HIGH, 1050000, 8 },
Matt Wagantall29b7b472013-03-07 17:09:58 -0800[diff] [blame]283 { }
284};
285
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]286static struct acpu_level acpu_freq_tbl_2g_pvs0[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]287 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 815000, 73 },
288 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 825000, 85 },
289 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 835000, 104 },
290 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 845000, 124 },
291 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 855000, 144 },
292 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 865000, 165 },
293 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 875000, 186 },
294 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 890000, 208 },
295 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 900000, 229 },
296 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 915000, 252 },
297 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 925000, 275 },
298 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 940000, 298 },
299 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 950000, 321 },
300 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 965000, 346 },
301 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 980000, 371 },
302 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 995000, 397 },
303 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1010000, 423 },
304 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 1025000, 450 },
305 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 1040000, 477 },
306 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1055000, 506 },
307 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1070000, 536 },
308 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1085000, 567 },
309 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1100000, 598 },
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]310 { 0, { 0 } }
311};
312
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]313static struct acpu_level acpu_freq_tbl_2g_pvs1[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]314 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 73 },
315 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 810000, 85 },
316 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 820000, 104 },
317 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 830000, 124 },
318 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 840000, 144 },
319 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 850000, 165 },
320 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 860000, 186 },
321 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 875000, 208 },
322 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 885000, 229 },
323 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 895000, 252 },
324 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 910000, 275 },
325 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 920000, 298 },
326 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 930000, 321 },
327 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 945000, 346 },
328 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 960000, 371 },
329 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 975000, 397 },
330 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 990000, 423 },
331 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 1005000, 450 },
332 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 1020000, 477 },
333 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1030000, 506 },
334 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1045000, 536 },
335 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1060000, 567 },
336 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1075000, 598 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]337 { 0, { 0 } }
338};
339
340static struct acpu_level acpu_freq_tbl_2g_pvs2[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]341 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 785000, 73 },
342 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 795000, 85 },
343 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 805000, 104 },
344 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 815000, 124 },
345 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 825000, 144 },
346 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 835000, 165 },
347 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 845000, 186 },
348 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 855000, 208 },
349 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 865000, 229 },
350 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 875000, 252 },
351 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 890000, 275 },
352 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 900000, 298 },
353 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 910000, 321 },
354 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 925000, 346 },
355 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 940000, 371 },
356 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 955000, 397 },
357 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 970000, 423 },
358 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 980000, 450 },
359 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 995000, 477 },
360 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1005000, 506 },
361 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1020000, 536 },
362 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1035000, 567 },
363 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1050000, 598 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]364 { 0, { 0 } }
365};
366
367static struct acpu_level acpu_freq_tbl_2g_pvs3[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]368 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 73 },
369 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 780000, 85 },
370 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 790000, 104 },
371 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 124 },
372 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 144 },
373 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 165 },
374 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 186 },
375 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 208 },
376 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 229 },
377 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 252 },
378 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 875000, 275 },
379 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 885000, 298 },
380 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 895000, 321 },
381 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 346 },
382 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 925000, 371 },
383 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 935000, 397 },
384 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 950000, 423 },
385 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 960000, 450 },
386 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 970000, 477 },
387 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 985000, 506 },
388 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 995000, 536 },
389 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1010000, 567 },
390 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1025000, 598 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]391 { 0, { 0 } }
392};
393
394static struct acpu_level acpu_freq_tbl_2g_pvs4[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]395 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 73 },
396 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 85 },
397 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 780000, 104 },
398 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 790000, 124 },
399 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 144 },
400 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 165 },
401 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 186 },
402 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 208 },
403 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 229 },
404 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 252 },
405 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 275 },
406 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 298 },
407 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 321 },
408 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 895000, 346 },
409 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 371 },
410 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 920000, 397 },
411 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 423 },
412 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 450 },
413 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 950000, 477 },
414 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 960000, 506 },
415 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 975000, 536 },
416 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 985000, 567 },
417 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1000000, 598 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]418 { 0, { 0 } }
419};
420
421static struct acpu_level acpu_freq_tbl_2g_pvs5[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]422 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 73 },
423 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 760000, 85 },
424 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 770000, 104 },
425 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 780000, 124 },
426 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 790000, 144 },
427 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 165 },
428 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 186 },
429 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 208 },
430 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 229 },
431 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 252 },
432 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 275 },
433 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 860000, 298 },
434 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 870000, 321 },
435 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 880000, 346 },
436 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 371 },
437 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 900000, 397 },
438 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 423 },
439 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 450 },
440 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 930000, 477 },
441 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 940000, 506 },
442 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 955000, 536 },
443 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 965000, 567 },
444 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 975000, 598 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]445 { 0, { 0 } }
446};
447
448static struct acpu_level acpu_freq_tbl_2g_pvs6[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]449 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 73 },
450 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 85 },
451 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 760000, 104 },
452 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 770000, 124 },
453 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 780000, 144 },
454 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 790000, 165 },
455 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 186 },
456 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 208 },
457 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 229 },
458 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 252 },
459 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 275 },
460 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 298 },
461 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 321 },
462 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 346 },
463 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 875000, 371 },
464 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 397 },
465 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 423 },
466 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 905000, 450 },
467 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 477 },
468 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 920000, 506 },
469 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 536 },
470 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 567 },
471 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 598 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]472 { 0, { 0 } }
473};
474
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]475static struct acpu_level acpu_freq_tbl_2p2g_pvs0[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]476 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 72 },
477 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 83 },
478 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 805000, 102 },
479 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 815000, 121 },
480 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 825000, 141 },
481 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 835000, 161 },
482 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 845000, 181 },
483 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 855000, 202 },
484 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 865000, 223 },
485 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 875000, 245 },
486 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 890000, 267 },
487 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 900000, 289 },
488 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 915000, 313 },
489 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 925000, 336 },
490 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 940000, 360 },
491 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 950000, 383 },
492 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 965000, 409 },
493 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 980000, 435 },
494 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 995000, 461 },
495 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1010000, 488 },
496 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1025000, 516 },
497 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1040000, 543 },
498 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1055000, 573 },
499 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1070000, 604 },
500 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1085000, 636 },
501 { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1100000, 656 },
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]502 { 0, { 0 } }
503};
504
505static struct acpu_level acpu_freq_tbl_2p2g_pvs1[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]506 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 72 },
507 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 83 },
508 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 102 },
509 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 121 },
510 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 141 },
511 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 161 },
512 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 181 },
513 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 202 },
514 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 223 },
515 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 245 },
516 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 875000, 267 },
517 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 885000, 289 },
518 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 895000, 313 },
519 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 336 },
520 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 920000, 360 },
521 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 930000, 383 },
522 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 945000, 409 },
523 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 960000, 435 },
524 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 975000, 461 },
525 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 990000, 488 },
526 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1005000, 516 },
527 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1020000, 543 },
528 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1030000, 573 },
529 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1045000, 604 },
530 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1060000, 636 },
531 { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1075000, 656 },
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]532 { 0, { 0 } }
533};
534
535static struct acpu_level acpu_freq_tbl_2p2g_pvs2[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]536 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
537 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
538 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 102 },
539 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 785000, 121 },
540 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 795000, 141 },
541 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 805000, 161 },
542 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 815000, 181 },
543 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 825000, 202 },
544 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 835000, 223 },
545 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 845000, 245 },
546 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 855000, 267 },
547 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 865000, 289 },
548 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 875000, 313 },
549 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 336 },
550 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 360 },
551 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 910000, 383 },
552 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 925000, 409 },
553 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 435 },
554 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 461 },
555 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 488 },
556 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 980000, 516 },
557 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 995000, 543 },
558 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1005000, 573 },
559 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1020000, 604 },
560 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1035000, 636 },
561 { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1050000, 656 },
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]562 { 0, { 0 } }
563};
564
565static struct acpu_level acpu_freq_tbl_2p2g_pvs3[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]566 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
567 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
568 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 102 },
569 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 121 },
570 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 780000, 141 },
571 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 790000, 161 },
572 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 181 },
573 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 202 },
574 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 223 },
575 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 245 },
576 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 267 },
577 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 289 },
578 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 313 },
579 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 875000, 336 },
580 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 360 },
581 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 383 },
582 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 409 },
583 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 925000, 435 },
584 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 461 },
585 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 488 },
586 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 960000, 516 },
587 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 970000, 543 },
588 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 985000, 573 },
589 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 995000, 604 },
590 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1010000, 636 },
591 { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1025000, 656 },
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]592 { 0, { 0 } }
593};
594
595static struct acpu_level acpu_freq_tbl_2p2g_pvs4[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]596 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
597 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
598 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 102 },
599 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 121 },
600 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 141 },
601 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 780000, 161 },
602 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 790000, 181 },
603 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202 },
604 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 223 },
605 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 245 },
606 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 267 },
607 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 289 },
608 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 313 },
609 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 336 },
610 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 870000, 360 },
611 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 880000, 383 },
612 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 409 },
613 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 910000, 435 },
614 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 920000, 461 },
615 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 488 },
616 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 940000, 516 },
617 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 950000, 543 },
618 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 573 },
619 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 975000, 604 },
620 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 985000, 636 },
621 { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1000000, 656 },
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]622 { 0, { 0 } }
623};
624
625static struct acpu_level acpu_freq_tbl_2p2g_pvs5[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]626 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
627 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
628 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 102 },
629 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 121 },
630 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 760000, 141 },
631 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 770000, 161 },
632 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 181 },
633 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 202 },
634 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 223 },
635 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 245 },
636 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 267 },
637 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 289 },
638 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 313 },
639 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 336 },
640 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 360 },
641 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 870000, 383 },
642 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 409 },
643 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 890000, 435 },
644 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 461 },
645 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 488 },
646 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 920000, 516 },
647 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 543 },
648 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 940000, 573 },
649 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 955000, 604 },
650 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 965000, 636 },
651 { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 975000, 656 },
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]652 { 0, { 0 } }
653};
654
655static struct acpu_level acpu_freq_tbl_2p2g_pvs6[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]656 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
657 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
658 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 102 },
659 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 121 },
660 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 141 },
661 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 760000, 161 },
662 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 770000, 181 },
663 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 202 },
664 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 223 },
665 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 245 },
666 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 267 },
667 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 289 },
668 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 313 },
669 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 336 },
670 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 360 },
671 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 383 },
672 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 409 },
673 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 875000, 435 },
674 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 461 },
675 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 488 },
676 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 516 },
677 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 543 },
678 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 920000, 573 },
679 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 930000, 604 },
680 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 636 },
681 { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 950000, 656 },
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]682 { 0, { 0 } }
683};
684
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]685static struct acpu_level acpu_freq_tbl_2p3g_pvs0[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]686 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 72 },
687 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 83 },
688 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 101 },
689 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 805000, 120 },
690 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 815000, 139 },
691 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 825000, 159 },
692 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 835000, 180 },
693 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 845000, 200 },
694 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 855000, 221 },
695 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 865000, 242 },
696 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 875000, 264 },
697 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 890000, 287 },
698 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 900000, 308 },
699 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 915000, 333 },
700 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 925000, 356 },
701 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 940000, 380 },
702 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 950000, 404 },
703 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 965000, 430 },
704 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 980000, 456 },
705 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 995000, 482 },
706 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1010000, 510 },
707 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1025000, 538 },
708 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1040000, 565 },
709 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1055000, 596 },
710 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1070000, 627 },
711 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1085000, 659 },
712 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1100000, 691 },
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]713 { 0, { 0 } }
714};
715
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]716static struct acpu_level acpu_freq_tbl_2p3g_pvs1[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]717 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 72 },
718 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 83 },
719 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 101 },
720 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 120 },
721 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 139 },
722 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 159 },
723 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 180 },
724 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 200 },
725 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 221 },
726 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 242 },
727 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 264 },
728 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 875000, 287 },
729 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 885000, 308 },
730 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 895000, 333 },
731 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 356 },
732 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 920000, 380 },
733 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 404 },
734 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 945000, 430 },
735 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 960000, 456 },
736 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 975000, 482 },
737 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 990000, 510 },
738 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1005000, 538 },
739 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1020000, 565 },
740 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 596 },
741 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 627 },
742 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 659 },
743 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 691 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]744 { 0, { 0 } }
745};
746
747static struct acpu_level acpu_freq_tbl_2p3g_pvs2[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]748 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
749 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
750 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
751 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
752 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 785000, 139 },
753 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 795000, 159 },
754 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 805000, 180 },
755 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 815000, 200 },
756 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 825000, 221 },
757 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 835000, 242 },
758 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 845000, 264 },
759 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 855000, 287 },
760 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 865000, 308 },
761 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 875000, 333 },
762 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 356 },
763 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 900000, 380 },
764 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 404 },
765 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 925000, 430 },
766 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 940000, 456 },
767 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 955000, 482 },
768 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 970000, 510 },
769 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 538 },
770 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 565 },
771 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 596 },
772 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627 },
773 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659 },
774 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]775 { 0, { 0 } }
776};
777
778static struct acpu_level acpu_freq_tbl_2p3g_pvs3[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]779 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
780 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
781 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
782 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
783 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139 },
784 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 780000, 159 },
785 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 790000, 180 },
786 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 200 },
787 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 221 },
788 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 242 },
789 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 264 },
790 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 287 },
791 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 308 },
792 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 333 },
793 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 875000, 356 },
794 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 380 },
795 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 404 },
796 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 910000, 430 },
797 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 925000, 456 },
798 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 935000, 482 },
799 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 950000, 510 },
800 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 960000, 538 },
801 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 565 },
802 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 985000, 596 },
803 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 627 },
804 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 659 },
805 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 691 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]806 { 0, { 0 } }
807};
808
809static struct acpu_level acpu_freq_tbl_2p3g_pvs4[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]810 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
811 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
812 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
813 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
814 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139 },
815 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 159 },
816 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 180 },
817 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 200 },
818 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 221 },
819 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 242 },
820 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 264 },
821 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 287 },
822 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 308 },
823 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 333 },
824 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 356 },
825 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 870000, 380 },
826 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 404 },
827 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 895000, 430 },
828 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 910000, 456 },
829 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 920000, 482 },
830 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 510 },
831 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 538 },
832 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 565 },
833 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 596 },
834 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 627 },
835 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659 },
836 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]837 { 0, { 0 } }
838};
839
840static struct acpu_level acpu_freq_tbl_2p3g_pvs5[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]841 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
842 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
843 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
844 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
845 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
846 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 760000, 159 },
847 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 770000, 180 },
848 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 200 },
849 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 221 },
850 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 242 },
851 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 264 },
852 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 287 },
853 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 308 },
854 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 333 },
855 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 356 },
856 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 380 },
857 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 404 },
858 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 880000, 430 },
859 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 890000, 456 },
860 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 482 },
861 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 910000, 510 },
862 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 920000, 538 },
863 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 565 },
864 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 596 },
865 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 627 },
866 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 659 },
867 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]868 { 0, { 0 } }
869};
870
871static struct acpu_level acpu_freq_tbl_2p3g_pvs6[] __initdata = {
Patrick Cain92f4fa12013-04-22 16:23:19 -0700[diff] [blame]872 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
873 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
874 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
875 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
876 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
877 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 159 },
878 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 760000, 180 },
879 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 770000, 200 },
880 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 780000, 221 },
881 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 790000, 242 },
882 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 264 },
883 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 810000, 287 },
884 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 820000, 308 },
885 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 830000, 333 },
886 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 840000, 356 },
887 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 850000, 380 },
888 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 404 },
889 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 430 },
890 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 875000, 456 },
891 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 885000, 482 },
892 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 510 },
893 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 905000, 538 },
894 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 915000, 565 },
895 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 596 },
896 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627 },
897 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659 },
898 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691 },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]899 { 0, { 0 } }
900};
901
Junjie Wuac533452013-08-27 17:56:06 -0700[diff] [blame^]902static struct acpu_level acpu_ftbl_pro_2p3g_pvs0[] __initdata = {
903 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
904 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
905 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
906 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 780000, 120 },
907 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 790000, 139 },
908 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 159 },
909 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 180 },
910 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 200 },
911 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 221 },
912 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 242 },
913 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 264 },
914 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 865000, 287 },
915 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 875000, 308 },
916 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 333 },
917 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 356 },
918 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 915000, 380 },
919 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 925000, 404 },
920 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 430 },
921 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 456 },
922 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 482 },
923 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 985000, 510 },
924 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1000000, 538 },
925 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1015000, 565 },
926 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 596 },
927 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 627 },
928 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 659 },
929 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 691 },
Junjie Wu56fe0542013-06-17 11:34:26 -0700[diff] [blame]930 { 0, { 0 } }
931};
932
Junjie Wuac533452013-08-27 17:56:06 -0700[diff] [blame^]933static struct acpu_level acpu_ftbl_pro_2p3g_pvs1[] __initdata = {
934 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72},
935 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83},
936 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101},
937 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120},
938 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139},
939 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 785000, 159},
940 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 795000, 180},
941 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 200},
942 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 221},
943 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 242},
944 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 264},
945 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 287},
946 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 308},
947 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 333},
948 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 356},
949 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 380},
950 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 905000, 404},
951 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 430},
952 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 456},
953 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 482},
954 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 510},
955 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 538},
956 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 565},
957 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 596},
958 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627},
959 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659},
960 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691},
961 { 0, { 0 } }
962};
963
964static struct acpu_level acpu_ftbl_pro_2p3g_pvs2[] __initdata = {
965 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
966 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
967 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
968 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
969 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 760000, 139 },
970 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 770000, 159 },
971 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 180 },
972 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 200 },
973 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 221 },
974 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 242 },
975 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 264 },
976 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 287 },
977 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 308 },
978 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 333 },
979 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 865000, 356 },
980 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 875000, 380 },
981 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 885000, 404 },
982 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 900000, 430 },
983 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 456 },
984 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 482 },
985 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 945000, 510 },
986 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 955000, 538 },
987 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 565 },
988 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 596 },
989 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 627 },
990 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 659 },
991 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 691 },
992 { 0, { 0 } }
993};
994
995static struct acpu_level acpu_ftbl_pro_2p3g_pvs3[] __initdata = {
996 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72},
997 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83},
998 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101},
999 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120},
1000 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139},
1001 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 755000, 159},
1002 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 765000, 180},
1003 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 200},
1004 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 785000, 221},
1005 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 795000, 242},
1006 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 264},
1007 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 287},
1008 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 308},
1009 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 333},
1010 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 356},
1011 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 380},
1012 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 404},
1013 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 430},
1014 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 456},
1015 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 482},
1016 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 510},
1017 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 538},
1018 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 565},
1019 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 596},
1020 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 627},
1021 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659},
1022 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691},
1023 { 0, { 0 } }
1024};
1025
1026static struct acpu_level acpu_ftbl_pro_2p3g_pvs4[] __initdata = {
1027 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72},
1028 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83},
1029 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101},
1030 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120},
1031 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139},
1032 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 159},
1033 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 755000, 180},
1034 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 765000, 200},
1035 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 221},
1036 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 785000, 242},
1037 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 795000, 264},
1038 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 287},
1039 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 308},
1040 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 333},
1041 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 356},
1042 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 380},
1043 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 404},
1044 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 430},
1045 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 456},
1046 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 482},
1047 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 510},
1048 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 538},
1049 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 565},
1050 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 596},
1051 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 627},
1052 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 659},
1053 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691},
1054 { 0, { 0 } }
1055};
1056
1057static struct acpu_level acpu_ftbl_pro_2p3g_pvs5[] __initdata = {
1058 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72},
1059 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83},
1060 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101},
1061 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120},
1062 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139},
1063 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 735000, 159},
1064 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 745000, 180},
1065 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 755000, 200},
1066 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 765000, 221},
1067 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 242},
1068 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 264},
1069 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 287},
1070 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 308},
1071 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 333},
1072 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 356},
1073 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 380},
1074 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 404},
1075 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 430},
1076 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 456},
1077 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 482},
1078 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 510},
1079 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 538},
1080 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 565},
1081 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 915000, 596},
1082 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627},
1083 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659},
1084 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691},
1085 { 0, { 0 } }
1086};
1087
1088static struct acpu_level acpu_ftbl_pro_2p3g_pvs6[] __initdata = {
1089 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72},
1090 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83},
1091 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101},
1092 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120},
1093 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139},
1094 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 159},
1095 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 735000, 180},
1096 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 745000, 200},
1097 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 755000, 221},
1098 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 765000, 242},
1099 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 264},
1100 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 785000, 287},
1101 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 795000, 308},
1102 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 805000, 333},
1103 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 815000, 356},
1104 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 380},
1105 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 835000, 404},
1106 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 430},
1107 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 456},
1108 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 482},
1109 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 870000, 510},
1110 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 538},
1111 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 890000, 565},
1112 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 596},
1113 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 627},
1114 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 659},
1115 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 925000, 691},
1116 { 0, { 0 } }
1117};
1118
1119static struct acpu_level acpu_ftbl_pro_2p5g_pvs0[] __initdata = {
1120 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76},
1121 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87},
1122 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106},
1123 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125},
1124 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145},
1125 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164},
1126 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183},
1127 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202},
1128 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222},
1129 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241},
1130 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 261},
1131 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 282},
1132 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 305},
1133 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 327},
1134 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 845000, 350},
1135 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 373},
1136 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 398},
1137 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 424},
1138 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 449},
1139 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 476},
1140 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 503},
1141 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 530},
1142 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 559},
1143 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 590},
1144 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 621},
1145 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 654},
1146 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 686},
1147 { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 723},
1148 { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1080000, 761},
1149 { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1100000, 800},
1150 { 0, { 0 } }
1151};
1152
1153static struct acpu_level acpu_ftbl_pro_2p5g_pvs1[] __initdata = {
1154 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76},
1155 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87},
1156 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106},
1157 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125},
1158 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145},
1159 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164},
1160 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183},
1161 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202},
1162 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222},
1163 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241},
1164 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 261},
1165 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 282},
1166 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 305},
1167 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 327},
1168 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 350},
1169 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 373},
1170 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 398},
1171 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 424},
1172 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 449},
1173 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 476},
1174 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 503},
1175 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 530},
1176 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 559},
1177 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 590},
1178 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 621},
1179 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 654},
1180 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 686},
1181 { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1035000, 723},
1182 { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 761},
1183 { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1075000, 800},
1184 { 0, { 0 } }
1185};
1186
1187static struct acpu_level acpu_ftbl_pro_2p5g_pvs2[] __initdata = {
1188 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76},
1189 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87},
1190 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106},
1191 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125},
1192 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145},
1193 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164},
1194 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183},
1195 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202},
1196 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222},
1197 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241},
1198 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 261},
1199 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 282},
1200 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 305},
1201 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 327},
1202 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 350},
1203 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 373},
1204 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 398},
1205 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 424},
1206 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 449},
1207 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 476},
1208 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 503},
1209 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 530},
1210 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 559},
1211 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 590},
1212 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 621},
1213 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 654},
1214 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 686},
1215 { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 723},
1216 { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1030000, 761},
1217 { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1050000, 800},
1218 { 0, { 0 } }
1219};
1220
1221static struct acpu_level acpu_ftbl_pro_2p5g_pvs3[] __initdata = {
1222 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76},
1223 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87},
1224 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106},
1225 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125},
1226 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145},
1227 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164},
1228 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183},
1229 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202},
1230 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222},
1231 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241},
1232 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 261},
1233 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 282},
1234 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 305},
1235 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 327},
1236 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 350},
1237 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 373},
1238 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 398},
1239 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 424},
1240 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 449},
1241 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 476},
1242 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 503},
1243 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 530},
1244 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 559},
1245 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 590},
1246 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 621},
1247 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 654},
1248 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 686},
1249 { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 985000, 723},
1250 { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 761},
1251 { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1025000, 800},
1252 { 0, { 0 } }
1253};
1254
1255static struct acpu_level acpu_ftbl_pro_2p5g_pvs4[] __initdata = {
1256 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76},
1257 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87},
1258 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106},
1259 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125},
1260 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145},
1261 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164},
1262 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183},
1263 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202},
1264 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222},
1265 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241},
1266 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 261},
1267 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 282},
1268 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 305},
1269 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 327},
1270 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 350},
1271 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 373},
1272 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 398},
1273 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 424},
1274 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 840000, 449},
1275 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 476},
1276 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 503},
1277 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 530},
1278 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 559},
1279 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 590},
1280 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 621},
1281 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 654},
1282 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 686},
1283 { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 723},
1284 { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 761},
1285 { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1000000, 800},
1286 { 0, { 0 } }
1287};
1288
1289static struct acpu_level acpu_ftbl_pro_2p5g_pvs5[] __initdata = {
1290 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76},
1291 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87},
1292 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106},
1293 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125},
1294 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145},
1295 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164},
1296 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183},
1297 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202},
1298 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222},
1299 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241},
1300 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 261},
1301 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 282},
1302 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 305},
1303 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 327},
1304 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 350},
1305 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 373},
1306 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 398},
1307 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 424},
1308 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 830000, 449},
1309 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 476},
1310 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 850000, 503},
1311 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 530},
1312 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 870000, 559},
1313 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 885000, 590},
1314 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 900000, 621},
1315 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 654},
1316 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 930000, 686},
1317 { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 945000, 723},
1318 { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 960000, 761},
1319 { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 975000, 800},
1320 { 0, { 0 } }
1321};
1322
1323static struct acpu_level acpu_ftbl_pro_2p5g_pvs6[] __initdata = {
1324 { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 76},
1325 { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 87},
1326 { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 106},
1327 { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 125},
1328 { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 145},
1329 { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 164},
1330 { 1, { 729600, HFPLL, 1, 38 }, L2(4), 725000, 183},
1331 { 0, { 806400, HFPLL, 1, 42 }, L2(4), 725000, 202},
1332 { 1, { 883200, HFPLL, 1, 46 }, L2(4), 725000, 222},
1333 { 1, { 960000, HFPLL, 1, 50 }, L2(9), 725000, 241},
1334 { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 735000, 261},
1335 { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 745000, 282},
1336 { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 755000, 305},
1337 { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 765000, 327},
1338 { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 775000, 350},
1339 { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 785000, 373},
1340 { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 795000, 398},
1341 { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 805000, 424},
1342 { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 449},
1343 { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 825000, 476},
1344 { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 835000, 503},
1345 { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 845000, 530},
1346 { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 855000, 559},
1347 { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 865000, 590},
1348 { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 875000, 621},
1349 { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 890000, 654},
1350 { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 905000, 686},
1351 { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 920000, 723},
1352 { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 935000, 761},
1353 { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 950000, 800},
1354 { 0, { 0 } }
1355};
Junjie Wu56fe0542013-06-17 11:34:26 -0700[diff] [blame]1356
Matt Wagantall75135922013-02-19 21:07:38 -0800[diff] [blame]1357static struct pvs_table pvs_v1[NUM_SPEED_BINS][NUM_PVS] __initdata = {
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]1358 /* 8974v1 1.7GHz Parts */
1359 [0][0] = { acpu_freq_tbl_v1_pvs0, sizeof(acpu_freq_tbl_v1_pvs0) },
1360 [0][1] = { acpu_freq_tbl_v1_pvs1, sizeof(acpu_freq_tbl_v1_pvs1) },
1361 [0][2] = { acpu_freq_tbl_v1_pvs2, sizeof(acpu_freq_tbl_v1_pvs2) },
1362 [0][3] = { acpu_freq_tbl_v1_pvs3, sizeof(acpu_freq_tbl_v1_pvs3) },
1363 [0][4] = { acpu_freq_tbl_v1_pvs4, sizeof(acpu_freq_tbl_v1_pvs4) },
Matt Wagantall75135922013-02-19 21:07:38 -0800[diff] [blame]1364};
1365
1366static struct pvs_table pvs_v2[NUM_SPEED_BINS][NUM_PVS] __initdata = {
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]1367 /* 8974v2 2.0GHz Parts */
1368 [0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]1369 [0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
1370 [0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
1371 [0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
1372 [0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
1373 [0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
1374 [0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
1375 [0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
Matt Wagantallc8c0c3b2013-02-25 20:19:17 -0800[diff] [blame]1376
1377 /* 8974v2 2.3GHz Parts */
1378 [1][0] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
Matt Wagantalld33ed482013-03-12 16:54:59 -0700[diff] [blame]1379 [1][1] = { acpu_freq_tbl_2p3g_pvs1, sizeof(acpu_freq_tbl_2p3g_pvs1) },
1380 [1][2] = { acpu_freq_tbl_2p3g_pvs2, sizeof(acpu_freq_tbl_2p3g_pvs2) },
1381 [1][3] = { acpu_freq_tbl_2p3g_pvs3, sizeof(acpu_freq_tbl_2p3g_pvs3) },
1382 [1][4] = { acpu_freq_tbl_2p3g_pvs4, sizeof(acpu_freq_tbl_2p3g_pvs4) },
1383 [1][5] = { acpu_freq_tbl_2p3g_pvs5, sizeof(acpu_freq_tbl_2p3g_pvs5) },
1384 [1][6] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
1385 [1][7] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]1386
Junjie Wu56fe0542013-06-17 11:34:26 -0700[diff] [blame]1387 /* 8974v2 2.2GHz Parts */
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]1388 [2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
1389 [2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
1390 [2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
1391 [2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
1392 [2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
1393 [2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
1394 [2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
1395 [2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
Junjie Wu8ab0ee22013-06-25 11:38:12 -0700[diff] [blame]1396};
Matt Wagantallf169c7c2013-04-01 20:48:28 -0700[diff] [blame]1397
Junjie Wu8ab0ee22013-06-25 11:38:12 -0700[diff] [blame]1398static struct pvs_table pvs_pro[NUM_SPEED_BINS][NUM_PVS] __initdata = {
Junjie Wuac533452013-08-27 17:56:06 -0700[diff] [blame^]1399 /* 2.0 GHz is not used on 8974Pro */
1400 [0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
1401 [0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
1402 [0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
1403 [0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
1404 [0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
1405 [0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
1406 [0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
1407 [0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
Junjie Wu56fe0542013-06-17 11:34:26 -0700[diff] [blame]1408
Junjie Wuac533452013-08-27 17:56:06 -0700[diff] [blame^]1409 /* 8974Pro AB 2.3GHz */
1410 [1][0] = { acpu_ftbl_pro_2p3g_pvs0, sizeof(acpu_ftbl_pro_2p3g_pvs0) },
1411 [1][1] = { acpu_ftbl_pro_2p3g_pvs1, sizeof(acpu_ftbl_pro_2p3g_pvs1) },
1412 [1][2] = { acpu_ftbl_pro_2p3g_pvs2, sizeof(acpu_ftbl_pro_2p3g_pvs2) },
1413 [1][3] = { acpu_ftbl_pro_2p3g_pvs3, sizeof(acpu_ftbl_pro_2p3g_pvs3) },
1414 [1][4] = { acpu_ftbl_pro_2p3g_pvs4, sizeof(acpu_ftbl_pro_2p3g_pvs4) },
1415 [1][5] = { acpu_ftbl_pro_2p3g_pvs5, sizeof(acpu_ftbl_pro_2p3g_pvs5) },
1416 [1][6] = { acpu_ftbl_pro_2p3g_pvs6, sizeof(acpu_ftbl_pro_2p3g_pvs6) },
1417 [1][7] = { acpu_ftbl_pro_2p3g_pvs6, sizeof(acpu_ftbl_pro_2p3g_pvs6) },
Junjie Wu8ab0ee22013-06-25 11:38:12 -0700[diff] [blame]1418
Junjie Wuac533452013-08-27 17:56:06 -0700[diff] [blame^]1419 /* 2.2GHz is not used on 8974Pro */
1420 [2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
1421 [2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
1422 [2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
1423 [2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
1424 [2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
1425 [2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
1426 [2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
1427 [2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
Junjie Wu8ab0ee22013-06-25 11:38:12 -0700[diff] [blame]1428
Junjie Wuac533452013-08-27 17:56:06 -0700[diff] [blame^]1429 /* 8974Pro AC 2.5GHz */
1430 [3][0] = { acpu_ftbl_pro_2p5g_pvs0, sizeof(acpu_ftbl_pro_2p5g_pvs0) },
1431 [3][1] = { acpu_ftbl_pro_2p5g_pvs1, sizeof(acpu_ftbl_pro_2p5g_pvs1) },
1432 [3][2] = { acpu_ftbl_pro_2p5g_pvs2, sizeof(acpu_ftbl_pro_2p5g_pvs2) },
1433 [3][3] = { acpu_ftbl_pro_2p5g_pvs3, sizeof(acpu_ftbl_pro_2p5g_pvs3) },
1434 [3][4] = { acpu_ftbl_pro_2p5g_pvs4, sizeof(acpu_ftbl_pro_2p5g_pvs4) },
1435 [3][5] = { acpu_ftbl_pro_2p5g_pvs5, sizeof(acpu_ftbl_pro_2p5g_pvs5) },
1436 [3][6] = { acpu_ftbl_pro_2p5g_pvs6, sizeof(acpu_ftbl_pro_2p5g_pvs6) },
1437 [3][7] = { acpu_ftbl_pro_2p5g_pvs6, sizeof(acpu_ftbl_pro_2p5g_pvs6) },
Matt Wagantall1f3762d2012-06-08 19:08:48 -0700[diff] [blame]1438};
1439
Matt Wagantall63ac3882013-03-07 16:51:14 -0800[diff] [blame]1440static struct msm_bus_scale_pdata bus_scale_data __initdata = {
1441 .usecase = bw_level_tbl_v2,
1442 .num_usecases = ARRAY_SIZE(bw_level_tbl_v2),
1443 .active_only = 1,
1444 .name = "acpuclk-8974",
1445};
1446
Matt Wagantall1f3762d2012-06-08 19:08:48 -0700[diff] [blame]1447static struct acpuclk_krait_params acpuclk_8974_params __initdata = {
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1448 .scalable = scalable,
Matt Wagantall1f3762d2012-06-08 19:08:48 -0700[diff] [blame]1449 .scalable_size = sizeof(scalable),
1450 .hfpll_data = &hfpll_data,
Matt Wagantall75135922013-02-19 21:07:38 -0800[diff] [blame]1451 .pvs_tables = pvs_v2,
Matt Wagantall29b7b472013-03-07 17:09:58 -0800[diff] [blame]1452 .l2_freq_tbl = l2_freq_tbl_v2,
1453 .l2_freq_tbl_size = sizeof(l2_freq_tbl_v2),
Matt Wagantall1f3762d2012-06-08 19:08:48 -0700[diff] [blame]1454 .bus_scale = &bus_scale_data,
Matt Wagantallee2b4372012-09-17 17:51:06 -0700[diff] [blame]1455 .pte_efuse_phys = 0xFC4B80B0,
Matt Wagantallf9a4d322013-01-14 18:01:24 -0800[diff] [blame]1456 .get_bin_info = get_krait_bin_format_b,
Matt Wagantallb7c231b2012-07-24 18:40:17 -0700[diff] [blame]1457 .stby_khz = 300000,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1458};
1459
Junjie Wu8ab0ee22013-06-25 11:38:12 -0700[diff] [blame]1460static void __init apply_pro_bringup_workaround(void)
1461{
1462 acpuclk_8974_params.pvs_tables = pvs_pro;
1463}
1464
Matt Wagantall75135922013-02-19 21:07:38 -0800[diff] [blame]1465static void __init apply_v1_l2_workaround(void)
Matt Wagantall2dd3f972013-01-08 12:03:43 -0800[diff] [blame]1466{
1467 static struct l2_level resticted_l2_tbl[] __initdata = {
1468 [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 1050000, 0 },
1469 [1] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 7 },
1470 { }
1471 };
1472 struct acpu_level *l;
1473 int s, p;
1474
1475 for (s = 0; s < NUM_SPEED_BINS; s++)
1476 for (p = 0; p < NUM_PVS; p++)
Matt Wagantall75135922013-02-19 21:07:38 -0800[diff] [blame]1477 for (l = pvs_v1[s][p].table; l && l->speed.khz; l++)
Matt Wagantall2dd3f972013-01-08 12:03:43 -0800[diff] [blame]1478 l->l2_level = l->l2_level > 5 ? 1 : 0;
1479
1480 acpuclk_8974_params.l2_freq_tbl = resticted_l2_tbl;
1481 acpuclk_8974_params.l2_freq_tbl_size = sizeof(resticted_l2_tbl);
1482}
1483
Junjie Wu8ab0ee22013-06-25 11:38:12 -0700[diff] [blame]1484#define cpu_is_msm8974pro() (cpu_is_msm8974pro_aa() || cpu_is_msm8974pro_ab() \
1485 || cpu_is_msm8974pro_ac())
1486
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1487static int __init acpuclk_8974_probe(struct platform_device *pdev)
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1488{
Junjie Wu8ab0ee22013-06-25 11:38:12 -0700[diff] [blame]1489 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1
1490 && cpu_is_msm8974()) {
Matt Wagantall75135922013-02-19 21:07:38 -0800[diff] [blame]1491 acpuclk_8974_params.pvs_tables = pvs_v1;
Matt Wagantall29b7b472013-03-07 17:09:58 -0800[diff] [blame]1492 acpuclk_8974_params.l2_freq_tbl = l2_freq_tbl_v1;
Matt Wagantall63ac3882013-03-07 16:51:14 -0800[diff] [blame]1493 bus_scale_data.usecase = bw_level_tbl_v1;
1494 bus_scale_data.num_usecases = ARRAY_SIZE(bw_level_tbl_v1);
Matt Wagantall29b7b472013-03-07 17:09:58 -0800[diff] [blame]1495 acpuclk_8974_params.l2_freq_tbl_size = sizeof(l2_freq_tbl_v1);
1496
1497 /*
1498 * 8974 hardware revisions older than v1.2 may experience L2
1499 * parity errors when running at some performance points between
1500 * 300MHz and 1497.6MHz (non-inclusive), or when vdd_mx is less
1501 * than 1.05V. Restrict L2 operation to safe performance points
1502 * on these devices.
1503 */
Matt Wagantall75135922013-02-19 21:07:38 -0800[diff] [blame]1504 if (SOCINFO_VERSION_MINOR(socinfo_get_version()) < 2)
1505 apply_v1_l2_workaround();
1506 }
Matt Wagantall2dd3f972013-01-08 12:03:43 -0800[diff] [blame]1507
Junjie Wu8ab0ee22013-06-25 11:38:12 -0700[diff] [blame]1508 if (cpu_is_msm8974pro())
1509 apply_pro_bringup_workaround();
1510
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1511 return acpuclk_krait_init(&pdev->dev, &acpuclk_8974_params);
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1512}
1513
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1514static struct of_device_id acpuclk_8974_match_table[] = {
1515 { .compatible = "qcom,acpuclk-8974" },
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1516 {}
1517};
1518
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1519static struct platform_driver acpuclk_8974_driver = {
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1520 .driver = {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1521 .name = "acpuclk-8974",
1522 .of_match_table = acpuclk_8974_match_table,
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1523 .owner = THIS_MODULE,
1524 },
1525};
1526
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1527static int __init acpuclk_8974_init(void)
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1528{
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1529 return platform_driver_probe(&acpuclk_8974_driver,
1530 acpuclk_8974_probe);
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1531}
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1532device_initcall(acpuclk_8974_init);