Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 2 | * ata_piix.c - Intel PATA/SATA controllers |
| 3 | * |
| 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
| 7 | * |
| 8 | * |
| 9 | * Copyright 2003-2005 Red Hat Inc |
| 10 | * Copyright 2003-2005 Jeff Garzik |
| 11 | * |
| 12 | * |
| 13 | * Copyright header from piix.c: |
| 14 | * |
| 15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
| 16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
| 17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> |
| 18 | * |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2, or (at your option) |
| 23 | * any later version. |
| 24 | * |
| 25 | * This program is distributed in the hope that it will be useful, |
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 28 | * GNU General Public License for more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License |
| 31 | * along with this program; see the file COPYING. If not, write to |
| 32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 33 | * |
| 34 | * |
| 35 | * libata documentation is available via 'make {ps|pdf}docs', |
| 36 | * as Documentation/DocBook/libata.* |
| 37 | * |
| 38 | * Hardware documentation available at http://developer.intel.com/ |
| 39 | * |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 40 | * Documentation |
| 41 | * Publically available from Intel web site. Errata documentation |
| 42 | * is also publically available. As an aide to anyone hacking on this |
| 43 | * driver the list of errata that are relevant is below.going back to |
| 44 | * PIIX4. Older device documentation is now a bit tricky to find. |
| 45 | * |
| 46 | * The chipsets all follow very much the same design. The orginal Triton |
| 47 | * series chipsets do _not_ support independant device timings, but this |
| 48 | * is fixed in Triton II. With the odd mobile exception the chips then |
| 49 | * change little except in gaining more modes until SATA arrives. This |
| 50 | * driver supports only the chips with independant timing (that is those |
| 51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix |
| 52 | * for the early chip drivers. |
| 53 | * |
| 54 | * Errata of note: |
| 55 | * |
| 56 | * Unfixable |
| 57 | * PIIX4 errata #9 - Only on ultra obscure hw |
| 58 | * ICH3 errata #13 - Not observed to affect real hw |
| 59 | * by Intel |
| 60 | * |
| 61 | * Things we must deal with |
| 62 | * PIIX4 errata #10 - BM IDE hang with non UDMA |
| 63 | * (must stop/start dma to recover) |
| 64 | * 440MX errata #15 - As PIIX4 errata #10 |
| 65 | * PIIX4 errata #15 - Must not read control registers |
| 66 | * during a PIO transfer |
| 67 | * 440MX errata #13 - As PIIX4 errata #15 |
| 68 | * ICH2 errata #21 - DMA mode 0 doesn't work right |
| 69 | * ICH0/1 errata #55 - As ICH2 errata #21 |
| 70 | * ICH2 spec c #9 - Extra operations needed to handle |
| 71 | * drive hotswap [NOT YET SUPPORTED] |
| 72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary |
| 73 | * and must be dword aligned |
| 74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 |
| 75 | * |
| 76 | * Should have been BIOS fixed: |
| 77 | * 450NX: errata #19 - DMA hangs on old 450NX |
| 78 | * 450NX: errata #20 - DMA hangs on old 450NX |
| 79 | * 450NX: errata #25 - Corruption with DMA on old 450NX |
| 80 | * ICH3 errata #15 - IDE deadlock under high load |
| 81 | * (BIOS must set dev 31 fn 0 bit 23) |
| 82 | * ICH3 errata #18 - Don't use native mode |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | */ |
| 84 | |
| 85 | #include <linux/kernel.h> |
| 86 | #include <linux/module.h> |
| 87 | #include <linux/pci.h> |
| 88 | #include <linux/init.h> |
| 89 | #include <linux/blkdev.h> |
| 90 | #include <linux/delay.h> |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 91 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | #include <scsi/scsi_host.h> |
| 93 | #include <linux/libata.h> |
| 94 | |
| 95 | #define DRV_NAME "ata_piix" |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 96 | #define DRV_VERSION "2.00ac7" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | |
| 98 | enum { |
| 99 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ |
| 100 | ICH5_PMR = 0x90, /* port mapping register */ |
| 101 | ICH5_PCS = 0x92, /* port control and status */ |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 102 | PIIX_SCC = 0x0A, /* sub-class code register */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
Tejun Heo | 219e621 | 2006-03-05 14:28:51 +0900 | [diff] [blame] | 104 | PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */ |
Tejun Heo | d435804 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 105 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 106 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
| 107 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 109 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
| 110 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, |
| 111 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | /* combined mode. if set, PATA is channel 0. |
| 113 | * if clear, PATA is channel 1. |
| 114 | */ |
Hannes Reinecke | 6a690df | 2005-06-28 17:30:38 -0700 | [diff] [blame] | 115 | PIIX_PORT_ENABLED = (1 << 0), |
| 116 | PIIX_PORT_PRESENT = (1 << 4), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | |
| 118 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
| 119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), |
| 120 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 121 | /* controller IDs */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 122 | piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */ |
| 123 | ich_pata_33 = 1, /* ICH up to UDMA 33 only */ |
| 124 | ich_pata_66 = 2, /* ICH up to 66 Mhz */ |
| 125 | ich_pata_100 = 3, /* ICH up to UDMA 100 */ |
| 126 | ich_pata_133 = 4, /* ICH up to UDMA 133 */ |
| 127 | ich5_sata = 5, |
| 128 | esb_sata = 6, |
| 129 | ich6_sata = 7, |
| 130 | ich6_sata_ahci = 8, |
| 131 | ich6m_sata_ahci = 9, |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 132 | ich8_sata_ahci = 10, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 133 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 134 | /* constants for mapping table */ |
| 135 | P0 = 0, /* port 0 */ |
| 136 | P1 = 1, /* port 1 */ |
| 137 | P2 = 2, /* port 2 */ |
| 138 | P3 = 3, /* port 3 */ |
| 139 | IDE = -1, /* IDE */ |
| 140 | NA = -2, /* not avaliable */ |
| 141 | RV = -3, /* reserved */ |
| 142 | |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 143 | PIIX_AHCI_DEVICE = 6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | }; |
| 145 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 146 | struct piix_map_db { |
| 147 | const u32 mask; |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 148 | const u16 port_enable; |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 149 | const int present_shift; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 150 | const int map[][4]; |
| 151 | }; |
| 152 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 153 | struct piix_host_priv { |
| 154 | const int *map; |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 155 | const struct piix_map_db *map_db; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 156 | }; |
| 157 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | static int piix_init_one (struct pci_dev *pdev, |
| 159 | const struct pci_device_id *ent); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 160 | static void piix_host_stop(struct ata_host *host); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 161 | static void piix_pata_error_handler(struct ata_port *ap); |
| 162 | static void ich_pata_error_handler(struct ata_port *ap); |
| 163 | static void piix_sata_error_handler(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
| 165 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 166 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | |
| 168 | static unsigned int in_module_init = 1; |
| 169 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 170 | static const struct pci_device_id piix_pci_tbl[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | #ifdef ATA_ENABLE_PATA |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 172 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
| 173 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ |
| 174 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 175 | { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 176 | { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 177 | /* Intel PIIX4 */ |
| 178 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 179 | /* Intel PIIX4 */ |
| 180 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 181 | /* Intel PIIX */ |
| 182 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 183 | /* Intel ICH (i810, i815, i840) UDMA 66*/ |
| 184 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, |
| 185 | /* Intel ICH0 : UDMA 33*/ |
| 186 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, |
| 187 | /* Intel ICH2M */ |
| 188 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 189 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ |
| 190 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 191 | /* Intel ICH3M */ |
| 192 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 193 | /* Intel ICH3 (E7500/1) UDMA 100 */ |
| 194 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 195 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ |
| 196 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 197 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 198 | /* Intel ICH5 */ |
| 199 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, |
| 200 | /* C-ICH (i810E2) */ |
| 201 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 202 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 203 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 204 | /* ICH6 (and 6) (i915) UDMA 100 */ |
| 205 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 206 | /* ICH7/7-R (i945, i975) UDMA 100*/ |
| 207 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, |
| 208 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 209 | #endif |
| 210 | |
| 211 | /* NOTE: The following PCI ids must be kept in sync with the |
| 212 | * list in drivers/pci/quirks.c. |
| 213 | */ |
| 214 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 215 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 217 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 219 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
| 220 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, |
| 221 | /* 6300ESB pretending RAID */ |
| 222 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, |
| 223 | /* 82801FB/FW (ICH6/ICH6W) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 225 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 226 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 227 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
| 228 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
| 229 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 230 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 231 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 232 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 233 | /* Enterprise Southbridge 2 (where's the datasheet?) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 234 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 235 | /* SATA Controller 1 IDE (ICH8, no datasheet yet) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 236 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 237 | /* SATA Controller 2 IDE (ICH8, ditto) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 238 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 239 | /* Mobile SATA Controller IDE (ICH8M, ditto) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 240 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | |
| 242 | { } /* terminate list */ |
| 243 | }; |
| 244 | |
| 245 | static struct pci_driver piix_pci_driver = { |
| 246 | .name = DRV_NAME, |
| 247 | .id_table = piix_pci_tbl, |
| 248 | .probe = piix_init_one, |
| 249 | .remove = ata_pci_remove_one, |
Jens Axboe | 9b84754 | 2006-01-06 09:28:07 +0100 | [diff] [blame] | 250 | .suspend = ata_pci_device_suspend, |
| 251 | .resume = ata_pci_device_resume, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | }; |
| 253 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 254 | static struct scsi_host_template piix_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 255 | .module = THIS_MODULE, |
| 256 | .name = DRV_NAME, |
| 257 | .ioctl = ata_scsi_ioctl, |
| 258 | .queuecommand = ata_scsi_queuecmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | .can_queue = ATA_DEF_QUEUE, |
| 260 | .this_id = ATA_SHT_THIS_ID, |
| 261 | .sg_tablesize = LIBATA_MAX_PRD, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 263 | .emulated = ATA_SHT_EMULATED, |
| 264 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 265 | .proc_name = DRV_NAME, |
| 266 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 267 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 268 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | .bios_param = ata_std_bios_param, |
Jens Axboe | 9b84754 | 2006-01-06 09:28:07 +0100 | [diff] [blame] | 270 | .resume = ata_scsi_device_resume, |
| 271 | .suspend = ata_scsi_device_suspend, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | }; |
| 273 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 274 | static const struct ata_port_operations piix_pata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 275 | .port_disable = ata_port_disable, |
| 276 | .set_piomode = piix_set_piomode, |
| 277 | .set_dmamode = piix_set_dmamode, |
Albert Lee | 89bad58 | 2006-05-26 13:49:18 +0800 | [diff] [blame] | 278 | .mode_filter = ata_pci_default_filter, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | |
| 280 | .tf_load = ata_tf_load, |
| 281 | .tf_read = ata_tf_read, |
| 282 | .check_status = ata_check_status, |
| 283 | .exec_command = ata_exec_command, |
| 284 | .dev_select = ata_std_dev_select, |
| 285 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | .bmdma_setup = ata_bmdma_setup, |
| 287 | .bmdma_start = ata_bmdma_start, |
| 288 | .bmdma_stop = ata_bmdma_stop, |
| 289 | .bmdma_status = ata_bmdma_status, |
| 290 | .qc_prep = ata_qc_prep, |
| 291 | .qc_issue = ata_qc_issue_prot, |
Albert Lee | 89bad58 | 2006-05-26 13:49:18 +0800 | [diff] [blame] | 292 | .data_xfer = ata_pio_data_xfer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 294 | .freeze = ata_bmdma_freeze, |
| 295 | .thaw = ata_bmdma_thaw, |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 296 | .error_handler = piix_pata_error_handler, |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 297 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 298 | |
| 299 | .irq_handler = ata_interrupt, |
| 300 | .irq_clear = ata_bmdma_irq_clear, |
| 301 | |
| 302 | .port_start = ata_port_start, |
| 303 | .port_stop = ata_port_stop, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 304 | .host_stop = piix_host_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | }; |
| 306 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 307 | static const struct ata_port_operations ich_pata_ops = { |
| 308 | .port_disable = ata_port_disable, |
| 309 | .set_piomode = piix_set_piomode, |
| 310 | .set_dmamode = ich_set_dmamode, |
| 311 | .mode_filter = ata_pci_default_filter, |
| 312 | |
| 313 | .tf_load = ata_tf_load, |
| 314 | .tf_read = ata_tf_read, |
| 315 | .check_status = ata_check_status, |
| 316 | .exec_command = ata_exec_command, |
| 317 | .dev_select = ata_std_dev_select, |
| 318 | |
| 319 | .bmdma_setup = ata_bmdma_setup, |
| 320 | .bmdma_start = ata_bmdma_start, |
| 321 | .bmdma_stop = ata_bmdma_stop, |
| 322 | .bmdma_status = ata_bmdma_status, |
| 323 | .qc_prep = ata_qc_prep, |
| 324 | .qc_issue = ata_qc_issue_prot, |
| 325 | .data_xfer = ata_pio_data_xfer, |
| 326 | |
| 327 | .freeze = ata_bmdma_freeze, |
| 328 | .thaw = ata_bmdma_thaw, |
| 329 | .error_handler = ich_pata_error_handler, |
| 330 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
| 331 | |
| 332 | .irq_handler = ata_interrupt, |
| 333 | .irq_clear = ata_bmdma_irq_clear, |
| 334 | |
| 335 | .port_start = ata_port_start, |
| 336 | .port_stop = ata_port_stop, |
| 337 | .host_stop = ata_host_stop, |
| 338 | }; |
| 339 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 340 | static const struct ata_port_operations piix_sata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 341 | .port_disable = ata_port_disable, |
| 342 | |
| 343 | .tf_load = ata_tf_load, |
| 344 | .tf_read = ata_tf_read, |
| 345 | .check_status = ata_check_status, |
| 346 | .exec_command = ata_exec_command, |
| 347 | .dev_select = ata_std_dev_select, |
| 348 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | .bmdma_setup = ata_bmdma_setup, |
| 350 | .bmdma_start = ata_bmdma_start, |
| 351 | .bmdma_stop = ata_bmdma_stop, |
| 352 | .bmdma_status = ata_bmdma_status, |
| 353 | .qc_prep = ata_qc_prep, |
| 354 | .qc_issue = ata_qc_issue_prot, |
Albert Lee | 89bad58 | 2006-05-26 13:49:18 +0800 | [diff] [blame] | 355 | .data_xfer = ata_pio_data_xfer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 357 | .freeze = ata_bmdma_freeze, |
| 358 | .thaw = ata_bmdma_thaw, |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 359 | .error_handler = piix_sata_error_handler, |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 360 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | |
| 362 | .irq_handler = ata_interrupt, |
| 363 | .irq_clear = ata_bmdma_irq_clear, |
| 364 | |
| 365 | .port_start = ata_port_start, |
| 366 | .port_stop = ata_port_stop, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 367 | .host_stop = piix_host_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 368 | }; |
| 369 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 370 | static const struct piix_map_db ich5_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 371 | .mask = 0x7, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 372 | .port_enable = 0x3, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 373 | .present_shift = 4, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 374 | .map = { |
| 375 | /* PM PS SM SS MAP */ |
| 376 | { P0, NA, P1, NA }, /* 000b */ |
| 377 | { P1, NA, P0, NA }, /* 001b */ |
| 378 | { RV, RV, RV, RV }, |
| 379 | { RV, RV, RV, RV }, |
| 380 | { P0, P1, IDE, IDE }, /* 100b */ |
| 381 | { P1, P0, IDE, IDE }, /* 101b */ |
| 382 | { IDE, IDE, P0, P1 }, /* 110b */ |
| 383 | { IDE, IDE, P1, P0 }, /* 111b */ |
| 384 | }, |
| 385 | }; |
| 386 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 387 | static const struct piix_map_db ich6_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 388 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 389 | .port_enable = 0xf, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 390 | .present_shift = 4, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 391 | .map = { |
| 392 | /* PM PS SM SS MAP */ |
Tejun Heo | 79ea24e | 2006-03-31 20:01:50 +0900 | [diff] [blame] | 393 | { P0, P2, P1, P3 }, /* 00b */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 394 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 395 | { P0, P2, IDE, IDE }, /* 10b */ |
| 396 | { RV, RV, RV, RV }, |
| 397 | }, |
| 398 | }; |
| 399 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 400 | static const struct piix_map_db ich6m_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 401 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 402 | .port_enable = 0x5, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 403 | .present_shift = 4, |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 404 | |
| 405 | /* Map 01b isn't specified in the doc but some notebooks use |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 406 | * it anyway. MAP 01b have been spotted on both ICH6M and |
| 407 | * ICH7M. |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 408 | */ |
| 409 | .map = { |
| 410 | /* PM PS SM SS MAP */ |
| 411 | { P0, P2, RV, RV }, /* 00b */ |
| 412 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 413 | { P0, P2, IDE, IDE }, /* 10b */ |
| 414 | { RV, RV, RV, RV }, |
| 415 | }, |
| 416 | }; |
| 417 | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 418 | static const struct piix_map_db ich8_map_db = { |
| 419 | .mask = 0x3, |
| 420 | .port_enable = 0x3, |
| 421 | .present_shift = 8, |
| 422 | .map = { |
| 423 | /* PM PS SM SS MAP */ |
Kristen Carlson Accardi | 158f30c8 | 2006-10-19 13:27:39 -0700 | [diff] [blame] | 424 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 425 | { RV, RV, RV, RV }, |
Kristen Carlson Accardi | 158f30c8 | 2006-10-19 13:27:39 -0700 | [diff] [blame] | 426 | { IDE, IDE, NA, NA }, /* 10b (IDE mode) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 427 | { RV, RV, RV, RV }, |
| 428 | }, |
| 429 | }; |
| 430 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 431 | static const struct piix_map_db *piix_map_db_table[] = { |
| 432 | [ich5_sata] = &ich5_map_db, |
| 433 | [esb_sata] = &ich5_map_db, |
| 434 | [ich6_sata] = &ich6_map_db, |
| 435 | [ich6_sata_ahci] = &ich6_map_db, |
| 436 | [ich6m_sata_ahci] = &ich6m_map_db, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 437 | [ich8_sata_ahci] = &ich8_map_db, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 438 | }; |
| 439 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | static struct ata_port_info piix_port_info[] = { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 441 | /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 442 | { |
| 443 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 444 | .flags = PIIX_PATA_FLAGS, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 445 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 446 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 447 | .udma_mask = ATA_UDMA_MASK_40C, |
| 448 | .port_ops = &piix_pata_ops, |
| 449 | }, |
| 450 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 451 | /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 452 | { |
| 453 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 454 | .flags = PIIX_PATA_FLAGS, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 455 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 456 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ |
| 457 | .udma_mask = ATA_UDMA2, /* UDMA33 */ |
| 458 | .port_ops = &ich_pata_ops, |
| 459 | }, |
| 460 | /* ich_pata_66: 2 ICH controllers up to 66MHz */ |
| 461 | { |
| 462 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 463 | .flags = PIIX_PATA_FLAGS, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 464 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 465 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ |
| 466 | .udma_mask = ATA_UDMA4, |
| 467 | .port_ops = &ich_pata_ops, |
| 468 | }, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 469 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 470 | /* ich_pata_100: 3 */ |
| 471 | { |
| 472 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 473 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | .pio_mask = 0x1f, /* pio0-4 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 476 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
| 477 | .port_ops = &ich_pata_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 478 | }, |
| 479 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 480 | /* ich_pata_133: 4 ICH with full UDMA6 */ |
| 481 | { |
| 482 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 483 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 484 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 485 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ |
| 486 | .udma_mask = ATA_UDMA6, /* UDMA133 */ |
| 487 | .port_ops = &ich_pata_ops, |
| 488 | }, |
| 489 | |
| 490 | /* ich5_sata: 5 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | { |
| 492 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 493 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_IGNORE_PCS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | .pio_mask = 0x1f, /* pio0-4 */ |
| 495 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 496 | .udma_mask = 0x7f, /* udma0-6 */ |
| 497 | .port_ops = &piix_sata_ops, |
| 498 | }, |
| 499 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 500 | /* i6300esb_sata: 6 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 501 | { |
| 502 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 503 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_IGNORE_PCS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 504 | .pio_mask = 0x1f, /* pio0-4 */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 505 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 506 | .udma_mask = 0x7f, /* udma0-6 */ |
| 507 | .port_ops = &piix_sata_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | }, |
| 509 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 510 | /* ich6_sata: 7 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | { |
| 512 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 513 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | .pio_mask = 0x1f, /* pio0-4 */ |
| 515 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 516 | .udma_mask = 0x7f, /* udma0-6 */ |
| 517 | .port_ops = &piix_sata_ops, |
| 518 | }, |
| 519 | |
Jeff Garzik | dd1dc80 | 2006-09-11 08:54:55 -0400 | [diff] [blame] | 520 | /* ich6_sata_ahci: 8 */ |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 521 | { |
| 522 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 523 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 524 | PIIX_FLAG_AHCI, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 525 | .pio_mask = 0x1f, /* pio0-4 */ |
| 526 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 527 | .udma_mask = 0x7f, /* udma0-6 */ |
| 528 | .port_ops = &piix_sata_ops, |
| 529 | }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 530 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 531 | /* ich6m_sata_ahci: 9 */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 532 | { |
| 533 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 534 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 535 | PIIX_FLAG_AHCI, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 536 | .pio_mask = 0x1f, /* pio0-4 */ |
| 537 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 538 | .udma_mask = 0x7f, /* udma0-6 */ |
| 539 | .port_ops = &piix_sata_ops, |
| 540 | }, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 541 | |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 542 | /* ich8_sata_ahci: 10 */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 543 | { |
| 544 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame^] | 545 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 546 | PIIX_FLAG_AHCI, |
| 547 | .pio_mask = 0x1f, /* pio0-4 */ |
| 548 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 549 | .udma_mask = 0x7f, /* udma0-6 */ |
| 550 | .port_ops = &piix_sata_ops, |
| 551 | }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 552 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | }; |
| 554 | |
| 555 | static struct pci_bits piix_enable_bits[] = { |
| 556 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ |
| 557 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ |
| 558 | }; |
| 559 | |
| 560 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); |
| 561 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); |
| 562 | MODULE_LICENSE("GPL"); |
| 563 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); |
| 564 | MODULE_VERSION(DRV_VERSION); |
| 565 | |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 566 | static int force_pcs = 0; |
| 567 | module_param(force_pcs, int, 0444); |
| 568 | MODULE_PARM_DESC(force_pcs, "force honoring or ignoring PCS to work around " |
| 569 | "device mis-detection (0=default, 1=ignore PCS, 2=honor PCS)"); |
| 570 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 571 | struct ich_laptop { |
| 572 | u16 device; |
| 573 | u16 subvendor; |
| 574 | u16 subdevice; |
| 575 | }; |
| 576 | |
| 577 | /* |
| 578 | * List of laptops that use short cables rather than 80 wire |
| 579 | */ |
| 580 | |
| 581 | static const struct ich_laptop ich_laptop[] = { |
| 582 | /* devid, subvendor, subdev */ |
| 583 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ |
| 584 | /* end marker */ |
| 585 | { 0, } |
| 586 | }; |
| 587 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 588 | /** |
| 589 | * piix_pata_cbl_detect - Probe host controller cable detect info |
| 590 | * @ap: Port for which cable detect info is desired |
| 591 | * |
| 592 | * Read 80c cable indicator from ATA PCI device's PCI config |
| 593 | * register. This register is normally set by firmware (BIOS). |
| 594 | * |
| 595 | * LOCKING: |
| 596 | * None (inherited from caller). |
| 597 | */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 598 | |
| 599 | static void ich_pata_cbl_detect(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 600 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 601 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 602 | const struct ich_laptop *lap = &ich_laptop[0]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 603 | u8 tmp, mask; |
| 604 | |
| 605 | /* no 80c support in host controller? */ |
| 606 | if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0) |
| 607 | goto cbl40; |
| 608 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 609 | /* Check for specials - Acer Aspire 5602WLMi */ |
| 610 | while (lap->device) { |
| 611 | if (lap->device == pdev->device && |
| 612 | lap->subvendor == pdev->subsystem_vendor && |
| 613 | lap->subdevice == pdev->subsystem_device) { |
| 614 | ap->cbl = ATA_CBL_PATA40_SHORT; |
| 615 | return; |
| 616 | } |
| 617 | lap++; |
| 618 | } |
| 619 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | /* check BIOS cable detect results */ |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 621 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
| 623 | if ((tmp & mask) == 0) |
| 624 | goto cbl40; |
| 625 | |
| 626 | ap->cbl = ATA_CBL_PATA80; |
| 627 | return; |
| 628 | |
| 629 | cbl40: |
| 630 | ap->cbl = ATA_CBL_PATA40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | } |
| 632 | |
| 633 | /** |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 634 | * piix_pata_prereset - prereset for PATA host controller |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 635 | * @ap: Target port |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 636 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | * |
| 638 | * LOCKING: |
| 639 | * None (inherited from caller). |
| 640 | */ |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 641 | static int piix_pata_prereset(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 643 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 645 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
| 646 | return -ENOENT; |
| 647 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 648 | ap->cbl = ATA_CBL_PATA40; |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 649 | return ata_std_prereset(ap); |
| 650 | } |
| 651 | |
| 652 | static void piix_pata_error_handler(struct ata_port *ap) |
| 653 | { |
| 654 | ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, |
| 655 | ata_std_postreset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 656 | } |
| 657 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 658 | |
| 659 | /** |
| 660 | * ich_pata_prereset - prereset for PATA host controller |
| 661 | * @ap: Target port |
| 662 | * |
| 663 | * |
| 664 | * LOCKING: |
| 665 | * None (inherited from caller). |
| 666 | */ |
| 667 | static int ich_pata_prereset(struct ata_port *ap) |
| 668 | { |
| 669 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 670 | |
| 671 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) { |
| 672 | ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n"); |
| 673 | ap->eh_context.i.action &= ~ATA_EH_RESET_MASK; |
| 674 | return 0; |
| 675 | } |
| 676 | |
| 677 | ich_pata_cbl_detect(ap); |
| 678 | |
| 679 | return ata_std_prereset(ap); |
| 680 | } |
| 681 | |
| 682 | static void ich_pata_error_handler(struct ata_port *ap) |
| 683 | { |
| 684 | ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL, |
| 685 | ata_std_postreset); |
| 686 | } |
| 687 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 688 | /** |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 689 | * piix_sata_present_mask - determine present mask for SATA host controller |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 690 | * @ap: Target port |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 691 | * |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 692 | * Reads SATA PCI device's PCI config register Port Configuration |
| 693 | * and Status (PCS) to determine port and device availability. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 694 | * |
| 695 | * LOCKING: |
| 696 | * None (inherited from caller). |
| 697 | * |
| 698 | * RETURNS: |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 699 | * determined present_mask |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | */ |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 701 | static unsigned int piix_sata_present_mask(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 703 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 704 | struct piix_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 705 | const unsigned int *map = hpriv->map; |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 706 | int base = 2 * ap->port_no; |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 707 | unsigned int present_mask = 0; |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 708 | int port, i; |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 709 | u16 pcs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 710 | |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 711 | pci_read_config_word(pdev, ICH5_PCS, &pcs); |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 712 | DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 714 | for (i = 0; i < 2; i++) { |
| 715 | port = map[base + i]; |
| 716 | if (port < 0) |
| 717 | continue; |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 718 | if ((ap->flags & PIIX_FLAG_IGNORE_PCS) || |
| 719 | (pcs & 1 << (hpriv->map_db->present_shift + port))) |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 720 | present_mask |= 1 << i; |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 721 | } |
| 722 | |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 723 | DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n", |
| 724 | ap->id, pcs, present_mask); |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 725 | |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 726 | return present_mask; |
| 727 | } |
| 728 | |
| 729 | /** |
| 730 | * piix_sata_softreset - reset SATA host port via ATA SRST |
| 731 | * @ap: port to reset |
| 732 | * @classes: resulting classes of attached devices |
| 733 | * |
| 734 | * Reset SATA host port via ATA SRST. On controllers with |
| 735 | * reliable PCS present bits, the bits are used to determine |
| 736 | * device presence. |
| 737 | * |
| 738 | * LOCKING: |
| 739 | * Kernel thread context (may sleep) |
| 740 | * |
| 741 | * RETURNS: |
| 742 | * 0 on success, -errno otherwise. |
| 743 | */ |
| 744 | static int piix_sata_softreset(struct ata_port *ap, unsigned int *classes) |
| 745 | { |
| 746 | unsigned int present_mask; |
| 747 | int i, rc; |
| 748 | |
| 749 | present_mask = piix_sata_present_mask(ap); |
| 750 | |
| 751 | rc = ata_std_softreset(ap, classes); |
| 752 | if (rc) |
| 753 | return rc; |
| 754 | |
| 755 | for (i = 0; i < ATA_MAX_DEVICES; i++) { |
| 756 | if (!(present_mask & (1 << i))) |
| 757 | classes[i] = ATA_DEV_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | } |
| 759 | |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 760 | return 0; |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 761 | } |
| 762 | |
| 763 | static void piix_sata_error_handler(struct ata_port *ap) |
| 764 | { |
Tejun Heo | f1a58ec | 2006-08-20 17:56:38 +0900 | [diff] [blame] | 765 | ata_bmdma_drive_eh(ap, ata_std_prereset, piix_sata_softreset, NULL, |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 766 | ata_std_postreset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | } |
| 768 | |
| 769 | /** |
| 770 | * piix_set_piomode - Initialize host controller PATA PIO timings |
| 771 | * @ap: Port whose timings we are configuring |
| 772 | * @adev: um |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | * |
| 774 | * Set PIO mode for device, in host controller PCI config space. |
| 775 | * |
| 776 | * LOCKING: |
| 777 | * None (inherited from caller). |
| 778 | */ |
| 779 | |
| 780 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) |
| 781 | { |
| 782 | unsigned int pio = adev->pio_mode - XFER_PIO_0; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 783 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | unsigned int is_slave = (adev->devno != 0); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 785 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 786 | unsigned int slave_port = 0x44; |
| 787 | u16 master_data; |
| 788 | u8 slave_data; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 789 | u8 udma_enable; |
| 790 | int control = 0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 791 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 792 | /* |
| 793 | * See Intel Document 298600-004 for the timing programing rules |
| 794 | * for ICH controllers. |
| 795 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 796 | |
| 797 | static const /* ISP RTC */ |
| 798 | u8 timings[][2] = { { 0, 0 }, |
| 799 | { 0, 0 }, |
| 800 | { 1, 0 }, |
| 801 | { 2, 1 }, |
| 802 | { 2, 3 }, }; |
| 803 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 804 | if (pio >= 2) |
| 805 | control |= 1; /* TIME1 enable */ |
| 806 | if (ata_pio_need_iordy(adev)) |
| 807 | control |= 2; /* IE enable */ |
| 808 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 809 | /* Intel specifies that the PPE functionality is for disk only */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 810 | if (adev->class == ATA_DEV_ATA) |
| 811 | control |= 4; /* PPE enable */ |
| 812 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | pci_read_config_word(dev, master_port, &master_data); |
| 814 | if (is_slave) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 815 | /* Enable SITRE (seperate slave timing register) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | master_data |= 0x4000; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 817 | /* enable PPE1, IE1 and TIME1 as needed */ |
| 818 | master_data |= (control << 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 819 | pci_read_config_byte(dev, slave_port, &slave_data); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 820 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 821 | /* Load the timing nibble for this slave */ |
| 822 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | } else { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 824 | /* Master keeps the bits in a different format */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 825 | master_data &= 0xccf8; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 826 | /* Enable PPE, IE and TIME as appropriate */ |
| 827 | master_data |= control; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 828 | master_data |= |
| 829 | (timings[pio][0] << 12) | |
| 830 | (timings[pio][1] << 8); |
| 831 | } |
| 832 | pci_write_config_word(dev, master_port, master_data); |
| 833 | if (is_slave) |
| 834 | pci_write_config_byte(dev, slave_port, slave_data); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 835 | |
| 836 | /* Ensure the UDMA bit is off - it will be turned back on if |
| 837 | UDMA is selected */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 838 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 839 | if (ap->udma_mask) { |
| 840 | pci_read_config_byte(dev, 0x48, &udma_enable); |
| 841 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); |
| 842 | pci_write_config_byte(dev, 0x48, udma_enable); |
| 843 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 844 | } |
| 845 | |
| 846 | /** |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 847 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 848 | * @ap: Port whose timings we are configuring |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 849 | * @adev: Drive in question |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 850 | * @udma: udma mode, 0 - 6 |
Henne | c32a8fd | 2006-09-25 22:00:46 +0200 | [diff] [blame] | 851 | * @isich: set if the chip is an ICH device |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 852 | * |
| 853 | * Set UDMA mode for device, in host controller PCI config space. |
| 854 | * |
| 855 | * LOCKING: |
| 856 | * None (inherited from caller). |
| 857 | */ |
| 858 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 859 | static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 860 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 861 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 862 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
| 863 | u16 master_data; |
| 864 | u8 speed = adev->dma_mode; |
| 865 | int devid = adev->devno + 2 * ap->port_no; |
| 866 | u8 udma_enable; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 867 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 868 | static const /* ISP RTC */ |
| 869 | u8 timings[][2] = { { 0, 0 }, |
| 870 | { 0, 0 }, |
| 871 | { 1, 0 }, |
| 872 | { 2, 1 }, |
| 873 | { 2, 3 }, }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 874 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 875 | pci_read_config_word(dev, master_port, &master_data); |
| 876 | pci_read_config_byte(dev, 0x48, &udma_enable); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 877 | |
| 878 | if (speed >= XFER_UDMA_0) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 879 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
| 880 | u16 udma_timing; |
| 881 | u16 ideconf; |
| 882 | int u_clock, u_speed; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 883 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 884 | /* |
| 885 | * UDMA is handled by a combination of clock switching and |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 886 | * selection of dividers |
| 887 | * |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 888 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 889 | * except UDMA0 which is 00 |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 890 | */ |
| 891 | u_speed = min(2 - (udma & 1), udma); |
| 892 | if (udma == 5) |
| 893 | u_clock = 0x1000; /* 100Mhz */ |
| 894 | else if (udma > 2) |
| 895 | u_clock = 1; /* 66Mhz */ |
| 896 | else |
| 897 | u_clock = 0; /* 33Mhz */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 898 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 899 | udma_enable |= (1 << devid); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 900 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 901 | /* Load the CT/RP selection */ |
| 902 | pci_read_config_word(dev, 0x4A, &udma_timing); |
| 903 | udma_timing &= ~(3 << (4 * devid)); |
| 904 | udma_timing |= u_speed << (4 * devid); |
| 905 | pci_write_config_word(dev, 0x4A, udma_timing); |
| 906 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 907 | if (isich) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 908 | /* Select a 33/66/100Mhz clock */ |
| 909 | pci_read_config_word(dev, 0x54, &ideconf); |
| 910 | ideconf &= ~(0x1001 << devid); |
| 911 | ideconf |= u_clock << devid; |
| 912 | /* For ICH or later we should set bit 10 for better |
| 913 | performance (WR_PingPong_En) */ |
| 914 | pci_write_config_word(dev, 0x54, ideconf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 915 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 916 | } else { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 917 | /* |
| 918 | * MWDMA is driven by the PIO timings. We must also enable |
| 919 | * IORDY unconditionally along with TIME1. PPE has already |
| 920 | * been set when the PIO timing was set. |
| 921 | */ |
| 922 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; |
| 923 | unsigned int control; |
| 924 | u8 slave_data; |
| 925 | const unsigned int needed_pio[3] = { |
| 926 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 |
| 927 | }; |
| 928 | int pio = needed_pio[mwdma] - XFER_PIO_0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 929 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 930 | control = 3; /* IORDY|TIME1 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 931 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 932 | /* If the drive MWDMA is faster than it can do PIO then |
| 933 | we must force PIO into PIO0 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 934 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 935 | if (adev->pio_mode < needed_pio[mwdma]) |
| 936 | /* Enable DMA timing only */ |
| 937 | control |= 8; /* PIO cycles in PIO0 */ |
| 938 | |
| 939 | if (adev->devno) { /* Slave */ |
| 940 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ |
| 941 | master_data |= control << 4; |
| 942 | pci_read_config_byte(dev, 0x44, &slave_data); |
| 943 | slave_data &= (0x0F + 0xE1 * ap->port_no); |
| 944 | /* Load the matching timing */ |
| 945 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); |
| 946 | pci_write_config_byte(dev, 0x44, slave_data); |
| 947 | } else { /* Master */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 948 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 949 | and master timing bits */ |
| 950 | master_data |= control; |
| 951 | master_data |= |
| 952 | (timings[pio][0] << 12) | |
| 953 | (timings[pio][1] << 8); |
| 954 | } |
| 955 | udma_enable &= ~(1 << devid); |
| 956 | pci_write_config_word(dev, master_port, master_data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | } |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 958 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
| 959 | if (ap->udma_mask) |
| 960 | pci_write_config_byte(dev, 0x48, udma_enable); |
| 961 | } |
| 962 | |
| 963 | /** |
| 964 | * piix_set_dmamode - Initialize host controller PATA DMA timings |
| 965 | * @ap: Port whose timings we are configuring |
| 966 | * @adev: um |
| 967 | * |
| 968 | * Set MW/UDMA mode for device, in host controller PCI config space. |
| 969 | * |
| 970 | * LOCKING: |
| 971 | * None (inherited from caller). |
| 972 | */ |
| 973 | |
| 974 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 975 | { |
| 976 | do_pata_set_dmamode(ap, adev, 0); |
| 977 | } |
| 978 | |
| 979 | /** |
| 980 | * ich_set_dmamode - Initialize host controller PATA DMA timings |
| 981 | * @ap: Port whose timings we are configuring |
| 982 | * @adev: um |
| 983 | * |
| 984 | * Set MW/UDMA mode for device, in host controller PCI config space. |
| 985 | * |
| 986 | * LOCKING: |
| 987 | * None (inherited from caller). |
| 988 | */ |
| 989 | |
| 990 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 991 | { |
| 992 | do_pata_set_dmamode(ap, adev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 993 | } |
| 994 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 995 | #define AHCI_PCI_BAR 5 |
| 996 | #define AHCI_GLOBAL_CTL 0x04 |
| 997 | #define AHCI_ENABLE (1 << 31) |
| 998 | static int piix_disable_ahci(struct pci_dev *pdev) |
| 999 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1000 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1001 | u32 tmp; |
| 1002 | int rc = 0; |
| 1003 | |
| 1004 | /* BUG: pci_enable_device has not yet been called. This |
| 1005 | * works because this device is usually set up by BIOS. |
| 1006 | */ |
| 1007 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1008 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
| 1009 | !pci_resource_len(pdev, AHCI_PCI_BAR)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1010 | return 0; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1011 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1012 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1013 | if (!mmio) |
| 1014 | return -ENOMEM; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1015 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1016 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 1017 | if (tmp & AHCI_ENABLE) { |
| 1018 | tmp &= ~AHCI_ENABLE; |
| 1019 | writel(tmp, mmio + AHCI_GLOBAL_CTL); |
| 1020 | |
| 1021 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 1022 | if (tmp & AHCI_ENABLE) |
| 1023 | rc = -EIO; |
| 1024 | } |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1025 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1026 | pci_iounmap(pdev, mmio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1027 | return rc; |
| 1028 | } |
| 1029 | |
| 1030 | /** |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1031 | * piix_check_450nx_errata - Check for problem 450NX setup |
Randy Dunlap | c893a3a | 2006-01-28 13:15:32 -0500 | [diff] [blame] | 1032 | * @ata_dev: the PCI device to check |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1033 | * |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1034 | * Check for the present of 450NX errata #19 and errata #25. If |
| 1035 | * they are found return an error code so we can turn off DMA |
| 1036 | */ |
| 1037 | |
| 1038 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) |
| 1039 | { |
| 1040 | struct pci_dev *pdev = NULL; |
| 1041 | u16 cfg; |
| 1042 | u8 rev; |
| 1043 | int no_piix_dma = 0; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1044 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1045 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) |
| 1046 | { |
| 1047 | /* Look for 450NX PXB. Check for problem configurations |
| 1048 | A PCI quirk checks bit 6 already */ |
| 1049 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
| 1050 | pci_read_config_word(pdev, 0x41, &cfg); |
| 1051 | /* Only on the original revision: IDE DMA can hang */ |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 1052 | if (rev == 0x00) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1053 | no_piix_dma = 1; |
| 1054 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 1055 | else if (cfg & (1<<14) && rev < 5) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1056 | no_piix_dma = 2; |
| 1057 | } |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 1058 | if (no_piix_dma) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1059 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 1060 | if (no_piix_dma == 2) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1061 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
| 1062 | return no_piix_dma; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1063 | } |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1064 | |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1065 | static void __devinit piix_init_pcs(struct pci_dev *pdev, |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 1066 | struct ata_port_info *pinfo, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1067 | const struct piix_map_db *map_db) |
| 1068 | { |
| 1069 | u16 pcs, new_pcs; |
| 1070 | |
| 1071 | pci_read_config_word(pdev, ICH5_PCS, &pcs); |
| 1072 | |
| 1073 | new_pcs = pcs | map_db->port_enable; |
| 1074 | |
| 1075 | if (new_pcs != pcs) { |
| 1076 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); |
| 1077 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); |
| 1078 | msleep(150); |
| 1079 | } |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 1080 | |
| 1081 | if (force_pcs == 1) { |
| 1082 | dev_printk(KERN_INFO, &pdev->dev, |
| 1083 | "force ignoring PCS (0x%x)\n", new_pcs); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1084 | pinfo[0].flags |= PIIX_FLAG_IGNORE_PCS; |
| 1085 | pinfo[1].flags |= PIIX_FLAG_IGNORE_PCS; |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 1086 | } else if (force_pcs == 2) { |
| 1087 | dev_printk(KERN_INFO, &pdev->dev, |
| 1088 | "force honoring PCS (0x%x)\n", new_pcs); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1089 | pinfo[0].flags &= ~PIIX_FLAG_IGNORE_PCS; |
| 1090 | pinfo[1].flags &= ~PIIX_FLAG_IGNORE_PCS; |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 1091 | } |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1092 | } |
| 1093 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1094 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1095 | struct ata_port_info *pinfo, |
| 1096 | const struct piix_map_db *map_db) |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1097 | { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1098 | struct piix_host_priv *hpriv = pinfo[0].private_data; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1099 | const unsigned int *map; |
| 1100 | int i, invalid_map = 0; |
| 1101 | u8 map_value; |
| 1102 | |
| 1103 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); |
| 1104 | |
| 1105 | map = map_db->map[map_value & map_db->mask]; |
| 1106 | |
| 1107 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); |
| 1108 | for (i = 0; i < 4; i++) { |
| 1109 | switch (map[i]) { |
| 1110 | case RV: |
| 1111 | invalid_map = 1; |
| 1112 | printk(" XX"); |
| 1113 | break; |
| 1114 | |
| 1115 | case NA: |
| 1116 | printk(" --"); |
| 1117 | break; |
| 1118 | |
| 1119 | case IDE: |
| 1120 | WARN_ON((i & 1) || map[i + 1] != IDE); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 1121 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
Tejun Heo | f814b75 | 2006-08-05 03:59:13 +0900 | [diff] [blame] | 1122 | pinfo[i / 2].private_data = hpriv; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1123 | i++; |
| 1124 | printk(" IDE IDE"); |
| 1125 | break; |
| 1126 | |
| 1127 | default: |
| 1128 | printk(" P%d", map[i]); |
| 1129 | if (i & 1) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1130 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1131 | break; |
| 1132 | } |
| 1133 | } |
| 1134 | printk(" ]\n"); |
| 1135 | |
| 1136 | if (invalid_map) |
| 1137 | dev_printk(KERN_ERR, &pdev->dev, |
| 1138 | "invalid MAP value %u\n", map_value); |
| 1139 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1140 | hpriv->map = map; |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 1141 | hpriv->map_db = map_db; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1142 | } |
| 1143 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1144 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1145 | * piix_init_one - Register PIIX ATA PCI device with kernel services |
| 1146 | * @pdev: PCI device to register |
| 1147 | * @ent: Entry in piix_pci_tbl matching with @pdev |
| 1148 | * |
| 1149 | * Called from kernel PCI layer. We probe for combined mode (sigh), |
| 1150 | * and then hand over control to libata, for it to do the rest. |
| 1151 | * |
| 1152 | * LOCKING: |
| 1153 | * Inherited from PCI layer (may sleep). |
| 1154 | * |
| 1155 | * RETURNS: |
| 1156 | * Zero on success, or -ERRNO value. |
| 1157 | */ |
| 1158 | |
| 1159 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1160 | { |
| 1161 | static int printed_version; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1162 | struct ata_port_info port_info[2]; |
| 1163 | struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] }; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1164 | struct piix_host_priv *hpriv; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1165 | unsigned long port_flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | |
| 1167 | if (!printed_version++) |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 1168 | dev_printk(KERN_DEBUG, &pdev->dev, |
| 1169 | "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1170 | |
| 1171 | /* no hotplugging support (FIXME) */ |
| 1172 | if (!in_module_init) |
| 1173 | return -ENODEV; |
| 1174 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1175 | hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); |
| 1176 | if (!hpriv) |
| 1177 | return -ENOMEM; |
| 1178 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1179 | port_info[0] = piix_port_info[ent->driver_data]; |
| 1180 | port_info[1] = piix_port_info[ent->driver_data]; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1181 | port_info[0].private_data = hpriv; |
| 1182 | port_info[1].private_data = hpriv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1183 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1184 | port_flags = port_info[0].flags; |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 1185 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1186 | if (port_flags & PIIX_FLAG_AHCI) { |
Jeff Garzik | 8a60a07 | 2005-07-31 13:13:24 -0400 | [diff] [blame] | 1187 | u8 tmp; |
| 1188 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); |
| 1189 | if (tmp == PIIX_AHCI_DEVICE) { |
| 1190 | int rc = piix_disable_ahci(pdev); |
| 1191 | if (rc) |
| 1192 | return rc; |
| 1193 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1194 | } |
| 1195 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1196 | /* Initialize SATA map */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1197 | if (port_flags & ATA_FLAG_SATA) { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1198 | piix_init_sata_map(pdev, port_info, |
| 1199 | piix_map_db_table[ent->driver_data]); |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 1200 | piix_init_pcs(pdev, port_info, |
| 1201 | piix_map_db_table[ent->driver_data]); |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1202 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1203 | |
| 1204 | /* On ICH5, some BIOSen disable the interrupt using the |
| 1205 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. |
| 1206 | * On ICH6, this bit has the same effect, but only when |
| 1207 | * MSI is disabled (and it is disabled, as we don't use |
| 1208 | * message-signalled interrupts currently). |
| 1209 | */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1210 | if (port_flags & PIIX_FLAG_CHECKINTR) |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1211 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1212 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1213 | if (piix_check_450nx_errata(pdev)) { |
| 1214 | /* This writes into the master table but it does not |
| 1215 | really matter for this errata as we will apply it to |
| 1216 | all the PIIX devices on the board */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1217 | port_info[0].mwdma_mask = 0; |
| 1218 | port_info[0].udma_mask = 0; |
| 1219 | port_info[1].mwdma_mask = 0; |
| 1220 | port_info[1].udma_mask = 0; |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1221 | } |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1222 | return ata_pci_init_one(pdev, ppinfo, 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1223 | } |
| 1224 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1225 | static void piix_host_stop(struct ata_host *host) |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1226 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1227 | struct piix_host_priv *hpriv = host->private_data; |
Jeff Garzik | 24dd01b | 2006-08-14 14:22:54 -0400 | [diff] [blame] | 1228 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1229 | ata_host_stop(host); |
Jeff Garzik | 24dd01b | 2006-08-14 14:22:54 -0400 | [diff] [blame] | 1230 | |
| 1231 | kfree(hpriv); |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1232 | } |
| 1233 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1234 | static int __init piix_init(void) |
| 1235 | { |
| 1236 | int rc; |
| 1237 | |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 1238 | DPRINTK("pci_register_driver\n"); |
| 1239 | rc = pci_register_driver(&piix_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1240 | if (rc) |
| 1241 | return rc; |
| 1242 | |
| 1243 | in_module_init = 0; |
| 1244 | |
| 1245 | DPRINTK("done\n"); |
| 1246 | return 0; |
| 1247 | } |
| 1248 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1249 | static void __exit piix_exit(void) |
| 1250 | { |
| 1251 | pci_unregister_driver(&piix_pci_driver); |
| 1252 | } |
| 1253 | |
| 1254 | module_init(piix_init); |
| 1255 | module_exit(piix_exit); |