blob: 2bd0dcd1487a4da9d83cb1b881c13f569ebfd847 [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
29#include <mach/msm_xo.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070030#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "clock-local.h"
33#include "clock-rpm.h"
34#include "clock-voter.h"
35#include "clock-dss-8960.h"
36#include "devices.h"
37
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
Stephen Boyda52d7e32011-11-10 11:59:00 -080044#define ADM0_PBUS_CLK_CTL_REG REG(0x2208)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070045#define CE1_HCLK_CTL_REG REG(0x2720)
46#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou05e01102012-02-08 22:15:49 -080047#define PRNG_CLK_NS_REG REG(0x2E80)
Tianyi Gou41515e22011-09-01 19:37:43 -070048#define CE3_HCLK_CTL_REG REG(0x36C4)
49#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
50#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou41515e22011-09-01 19:37:43 -070052#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070053#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
54#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
55#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
56#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070057/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070058#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
59#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070060#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070061#define CLK_TEST_REG REG(0x2FA0)
Matt Wagantall7625a4c2011-11-01 16:17:53 -070062#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
63#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070064#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
65#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
66#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
67#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
68#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
69#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070070#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070071/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070072#define BB_PLL_ENA_SC0_REG REG(0x34C0)
Tianyi Gou59608a72012-01-31 22:19:30 -080073#define BB_PLL_ENA_RPM_REG REG(0x34A0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070074#define BB_PLL0_STATUS_REG REG(0x30D8)
75#define BB_PLL5_STATUS_REG REG(0x30F8)
76#define BB_PLL6_STATUS_REG REG(0x3118)
77#define BB_PLL7_STATUS_REG REG(0x3138)
78#define BB_PLL8_L_VAL_REG REG(0x3144)
79#define BB_PLL8_M_VAL_REG REG(0x3148)
80#define BB_PLL8_MODE_REG REG(0x3140)
81#define BB_PLL8_N_VAL_REG REG(0x314C)
82#define BB_PLL8_STATUS_REG REG(0x3158)
83#define BB_PLL8_CONFIG_REG REG(0x3154)
84#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070085#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
86#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070087#define BB_PLL14_MODE_REG REG(0x31C0)
88#define BB_PLL14_L_VAL_REG REG(0x31C4)
89#define BB_PLL14_M_VAL_REG REG(0x31C8)
90#define BB_PLL14_N_VAL_REG REG(0x31CC)
91#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
92#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070093#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070094#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
95#define PMEM_ACLK_CTL_REG REG(0x25A0)
96#define RINGOSC_NS_REG REG(0x2DC0)
97#define RINGOSC_STATUS_REG REG(0x2DCC)
98#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
Stephen Boyda52d7e32011-11-10 11:59:00 -080099#define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700100#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
101#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
102#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
103#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
104#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
105#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
106#define TSIF_HCLK_CTL_REG REG(0x2700)
107#define TSIF_REF_CLK_MD_REG REG(0x270C)
108#define TSIF_REF_CLK_NS_REG REG(0x2710)
109#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700110#define SATA_CLK_SRC_NS_REG REG(0x2C08)
111#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
112#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
113#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
114#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700115#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
116#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
117#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
118#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
119#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
120#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700121#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700122#define USB_HS1_RESET_REG REG(0x2910)
123#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
124#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700125#define USB_HS3_HCLK_CTL_REG REG(0x3700)
126#define USB_HS3_HCLK_FS_REG REG(0x3704)
127#define USB_HS3_RESET_REG REG(0x3710)
128#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
129#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
130#define USB_HS4_HCLK_CTL_REG REG(0x3720)
131#define USB_HS4_HCLK_FS_REG REG(0x3724)
132#define USB_HS4_RESET_REG REG(0x3730)
133#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
134#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700135#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
136#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
137#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
138#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
139#define USB_HSIC_RESET_REG REG(0x2934)
140#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
141#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
142#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700143#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700144#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
145#define PCIE_HCLK_CTL_REG REG(0x22CC)
146#define GPLL1_MODE_REG REG(0x3160)
147#define GPLL1_L_VAL_REG REG(0x3164)
148#define GPLL1_M_VAL_REG REG(0x3168)
149#define GPLL1_N_VAL_REG REG(0x316C)
150#define GPLL1_CONFIG_REG REG(0x3174)
151#define GPLL1_STATUS_REG REG(0x3178)
152#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700153
154/* Multimedia clock registers. */
155#define AHB_EN_REG REG_MM(0x0008)
156#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700157#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700158#define AHB_NS_REG REG_MM(0x0004)
159#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700160#define CAMCLK0_NS_REG REG_MM(0x0148)
161#define CAMCLK0_CC_REG REG_MM(0x0140)
162#define CAMCLK0_MD_REG REG_MM(0x0144)
163#define CAMCLK1_NS_REG REG_MM(0x015C)
164#define CAMCLK1_CC_REG REG_MM(0x0154)
165#define CAMCLK1_MD_REG REG_MM(0x0158)
166#define CAMCLK2_NS_REG REG_MM(0x0228)
167#define CAMCLK2_CC_REG REG_MM(0x0220)
168#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700169#define CSI0_NS_REG REG_MM(0x0048)
170#define CSI0_CC_REG REG_MM(0x0040)
171#define CSI0_MD_REG REG_MM(0x0044)
172#define CSI1_NS_REG REG_MM(0x0010)
173#define CSI1_CC_REG REG_MM(0x0024)
174#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700175#define CSI2_NS_REG REG_MM(0x0234)
176#define CSI2_CC_REG REG_MM(0x022C)
177#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700178#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
179#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
180#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
181#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
182#define DSI1_BYTE_CC_REG REG_MM(0x0090)
183#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
184#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
185#define DSI1_ESC_NS_REG REG_MM(0x011C)
186#define DSI1_ESC_CC_REG REG_MM(0x00CC)
187#define DSI2_ESC_NS_REG REG_MM(0x0150)
188#define DSI2_ESC_CC_REG REG_MM(0x013C)
189#define DSI_PIXEL_CC_REG REG_MM(0x0130)
190#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
191#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
192#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
193#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
194#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
195#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
196#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
197#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
198#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
199#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700200#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700201#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
202#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
203#define GFX2D0_CC_REG REG_MM(0x0060)
204#define GFX2D0_MD0_REG REG_MM(0x0064)
205#define GFX2D0_MD1_REG REG_MM(0x0068)
206#define GFX2D0_NS_REG REG_MM(0x0070)
207#define GFX2D1_CC_REG REG_MM(0x0074)
208#define GFX2D1_MD0_REG REG_MM(0x0078)
209#define GFX2D1_MD1_REG REG_MM(0x006C)
210#define GFX2D1_NS_REG REG_MM(0x007C)
211#define GFX3D_CC_REG REG_MM(0x0080)
212#define GFX3D_MD0_REG REG_MM(0x0084)
213#define GFX3D_MD1_REG REG_MM(0x0088)
214#define GFX3D_NS_REG REG_MM(0x008C)
215#define IJPEG_CC_REG REG_MM(0x0098)
216#define IJPEG_MD_REG REG_MM(0x009C)
217#define IJPEG_NS_REG REG_MM(0x00A0)
218#define JPEGD_CC_REG REG_MM(0x00A4)
219#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700220#define VCAP_CC_REG REG_MM(0x0178)
221#define VCAP_NS_REG REG_MM(0x021C)
222#define VCAP_MD0_REG REG_MM(0x01EC)
223#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700224#define MAXI_EN_REG REG_MM(0x0018)
225#define MAXI_EN2_REG REG_MM(0x0020)
226#define MAXI_EN3_REG REG_MM(0x002C)
227#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700228#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700229#define MDP_CC_REG REG_MM(0x00C0)
230#define MDP_LUT_CC_REG REG_MM(0x016C)
231#define MDP_MD0_REG REG_MM(0x00C4)
232#define MDP_MD1_REG REG_MM(0x00C8)
233#define MDP_NS_REG REG_MM(0x00D0)
234#define MISC_CC_REG REG_MM(0x0058)
235#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700236#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700237#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700238#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
239#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
240#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
241#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
242#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
243#define MM_PLL1_STATUS_REG REG_MM(0x0334)
244#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700245#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
246#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
247#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
248#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
249#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
250#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700251#define ROT_CC_REG REG_MM(0x00E0)
252#define ROT_NS_REG REG_MM(0x00E8)
253#define SAXI_EN_REG REG_MM(0x0030)
254#define SW_RESET_AHB_REG REG_MM(0x020C)
255#define SW_RESET_AHB2_REG REG_MM(0x0200)
256#define SW_RESET_ALL_REG REG_MM(0x0204)
257#define SW_RESET_AXI_REG REG_MM(0x0208)
258#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700259#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700260#define TV_CC_REG REG_MM(0x00EC)
261#define TV_CC2_REG REG_MM(0x0124)
262#define TV_MD_REG REG_MM(0x00F0)
263#define TV_NS_REG REG_MM(0x00F4)
264#define VCODEC_CC_REG REG_MM(0x00F8)
265#define VCODEC_MD0_REG REG_MM(0x00FC)
266#define VCODEC_MD1_REG REG_MM(0x0128)
267#define VCODEC_NS_REG REG_MM(0x0100)
268#define VFE_CC_REG REG_MM(0x0104)
269#define VFE_MD_REG REG_MM(0x0108)
270#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700271#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700272#define VPE_CC_REG REG_MM(0x0110)
273#define VPE_NS_REG REG_MM(0x0118)
274
275/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700276#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700277#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
278#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
279#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
280#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
281#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
282#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
283#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
284#define LCC_MI2S_MD_REG REG_LPA(0x004C)
285#define LCC_MI2S_NS_REG REG_LPA(0x0048)
286#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
287#define LCC_PCM_MD_REG REG_LPA(0x0058)
288#define LCC_PCM_NS_REG REG_LPA(0x0054)
289#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700290#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
291#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
292#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
293#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
294#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700295#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700296#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
297#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
298#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
299#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
300#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
301#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
302#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
303#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
304#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
305#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700306#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700307
Matt Wagantall8b38f942011-08-02 18:23:18 -0700308#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
309
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700310/* MUX source input identifiers. */
311#define pxo_to_bb_mux 0
Matt Wagantall7625a4c2011-11-01 16:17:53 -0700312#define cxo_to_bb_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700313#define pll0_to_bb_mux 2
314#define pll8_to_bb_mux 3
315#define pll6_to_bb_mux 4
316#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700317#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700318#define pxo_to_mm_mux 0
319#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700320#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
321#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700322#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700323#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700324#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700325#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700326#define hdmi_pll_to_mm_mux 3
327#define cxo_to_xo_mux 0
328#define pxo_to_xo_mux 1
329#define gnd_to_xo_mux 3
330#define pxo_to_lpa_mux 0
331#define cxo_to_lpa_mux 1
332#define pll4_to_lpa_mux 2
333#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700334#define pxo_to_pcie_mux 0
335#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700336
337/* Test Vector Macros */
338#define TEST_TYPE_PER_LS 1
339#define TEST_TYPE_PER_HS 2
340#define TEST_TYPE_MM_LS 3
341#define TEST_TYPE_MM_HS 4
342#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700343#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700344#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700345#define TEST_TYPE_SHIFT 24
346#define TEST_CLK_SEL_MASK BM(23, 0)
347#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
348#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
349#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
350#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
351#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
352#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700353#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700354#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700355
356#define MN_MODE_DUAL_EDGE 0x2
357
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700358struct pll_rate {
359 const uint32_t l_val;
360 const uint32_t m_val;
361 const uint32_t n_val;
362 const uint32_t vco;
363 const uint32_t post_div;
364 const uint32_t i_bits;
365};
366#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
367
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800368static int rpm_vreg_id_vdd_dig;
Tianyi Goue1faaf22012-01-24 16:07:19 -0800369static int rpm_vreg_id_vdd_sr2_pll;
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800370
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700371enum vdd_dig_levels {
372 VDD_DIG_NONE,
373 VDD_DIG_LOW,
374 VDD_DIG_NOMINAL,
375 VDD_DIG_HIGH
376};
377
378static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
379{
380 static const int vdd_uv[] = {
381 [VDD_DIG_NONE] = 0,
382 [VDD_DIG_LOW] = 945000,
383 [VDD_DIG_NOMINAL] = 1050000,
384 [VDD_DIG_HIGH] = 1150000
385 };
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800386 return rpm_vreg_set_voltage(rpm_vreg_id_vdd_dig, RPM_VREG_VOTER3,
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700387 vdd_uv[level], 1150000, 1);
388}
389
390static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
391
392#define VDD_DIG_FMAX_MAP1(l1, f1) \
393 .vdd_class = &vdd_dig, \
394 .fmax[VDD_DIG_##l1] = (f1)
395#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
396 .vdd_class = &vdd_dig, \
397 .fmax[VDD_DIG_##l1] = (f1), \
398 .fmax[VDD_DIG_##l2] = (f2)
399#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
400 .vdd_class = &vdd_dig, \
401 .fmax[VDD_DIG_##l1] = (f1), \
402 .fmax[VDD_DIG_##l2] = (f2), \
403 .fmax[VDD_DIG_##l3] = (f3)
404
Tianyi Goue1faaf22012-01-24 16:07:19 -0800405enum vdd_sr2_pll_levels {
406 VDD_SR2_PLL_OFF,
407 VDD_SR2_PLL_ON
Matt Wagantallc57577d2011-10-06 17:06:53 -0700408};
409
Tianyi Goue1faaf22012-01-24 16:07:19 -0800410static int set_vdd_sr2_pll(struct clk_vdd_class *vdd_class, int level)
Matt Wagantallc57577d2011-10-06 17:06:53 -0700411{
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800412 int rc = 0;
413 if (cpu_is_msm8960()) {
Tianyi Goue1faaf22012-01-24 16:07:19 -0800414 if (level == VDD_SR2_PLL_OFF) {
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800415 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
416 RPM_VREG_VOTER3, 0, 0, 1);
417 if (rc)
418 return rc;
419 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
420 RPM_VREG_VOTER3, 0, 0, 1);
421 if (rc)
422 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
423 RPM_VREG_VOTER3, 1800000, 1800000, 1);
424 } else {
425 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
426 RPM_VREG_VOTER3, 2200000, 2200000, 1);
427 if (rc)
428 return rc;
429 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
430 RPM_VREG_VOTER3, 1800000, 1800000, 1);
431 if (rc)
432 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
433 RPM_VREG_VOTER3, 0, 0, 1);
434 }
Tianyi Goue1faaf22012-01-24 16:07:19 -0800435 } else {
436 if (level == VDD_SR2_PLL_OFF) {
437 rc = rpm_vreg_set_voltage(rpm_vreg_id_vdd_sr2_pll,
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800438 RPM_VREG_VOTER3, 0, 0, 1);
439 if (rc)
440 return rc;
441 } else {
Tianyi Goue1faaf22012-01-24 16:07:19 -0800442 rc = rpm_vreg_set_voltage(rpm_vreg_id_vdd_sr2_pll,
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800443 RPM_VREG_VOTER3, 1800000, 1800000, 1);
444 if (rc)
445 return rc;
446 }
Matt Wagantallc57577d2011-10-06 17:06:53 -0700447 }
448
449 return rc;
450}
451
Tianyi Goue1faaf22012-01-24 16:07:19 -0800452static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll);
Matt Wagantallc57577d2011-10-06 17:06:53 -0700453
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700454/*
455 * Clock Descriptions
456 */
457
458static struct msm_xo_voter *xo_pxo, *xo_cxo;
459
460static int pxo_clk_enable(struct clk *clk)
461{
462 return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON);
463}
464
465static void pxo_clk_disable(struct clk *clk)
466{
Tianyi Gou41515e22011-09-01 19:37:43 -0700467 msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700468}
469
470static struct clk_ops clk_ops_pxo = {
471 .enable = pxo_clk_enable,
472 .disable = pxo_clk_disable,
473 .get_rate = fixed_clk_get_rate,
474 .is_local = local_clk_is_local,
475};
476
477static struct fixed_clk pxo_clk = {
478 .rate = 27000000,
479 .c = {
480 .dbg_name = "pxo_clk",
481 .ops = &clk_ops_pxo,
482 CLK_INIT(pxo_clk.c),
483 },
484};
485
486static int cxo_clk_enable(struct clk *clk)
487{
488 return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON);
489}
490
491static void cxo_clk_disable(struct clk *clk)
492{
493 msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF);
494}
495
496static struct clk_ops clk_ops_cxo = {
497 .enable = cxo_clk_enable,
498 .disable = cxo_clk_disable,
499 .get_rate = fixed_clk_get_rate,
500 .is_local = local_clk_is_local,
501};
502
503static struct fixed_clk cxo_clk = {
504 .rate = 19200000,
505 .c = {
506 .dbg_name = "cxo_clk",
507 .ops = &clk_ops_cxo,
508 CLK_INIT(cxo_clk.c),
509 },
510};
511
512static struct pll_clk pll2_clk = {
513 .rate = 800000000,
514 .mode_reg = MM_PLL1_MODE_REG,
515 .parent = &pxo_clk.c,
516 .c = {
517 .dbg_name = "pll2_clk",
518 .ops = &clk_ops_pll,
519 CLK_INIT(pll2_clk.c),
520 },
521};
522
Stephen Boyd94625ef2011-07-12 17:06:01 -0700523static struct pll_clk pll3_clk = {
524 .rate = 1200000000,
525 .mode_reg = BB_MMCC_PLL2_MODE_REG,
526 .parent = &pxo_clk.c,
527 .c = {
528 .dbg_name = "pll3_clk",
529 .ops = &clk_ops_pll,
Tianyi Goue1faaf22012-01-24 16:07:19 -0800530 .vdd_class = &vdd_sr2_pll,
531 .fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700532 CLK_INIT(pll3_clk.c),
533 },
534};
535
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700536static struct pll_vote_clk pll4_clk = {
537 .rate = 393216000,
538 .en_reg = BB_PLL_ENA_SC0_REG,
539 .en_mask = BIT(4),
540 .status_reg = LCC_PLL0_STATUS_REG,
541 .parent = &pxo_clk.c,
542 .c = {
543 .dbg_name = "pll4_clk",
544 .ops = &clk_ops_pll_vote,
545 CLK_INIT(pll4_clk.c),
546 },
547};
548
549static struct pll_vote_clk pll8_clk = {
550 .rate = 384000000,
551 .en_reg = BB_PLL_ENA_SC0_REG,
552 .en_mask = BIT(8),
553 .status_reg = BB_PLL8_STATUS_REG,
554 .parent = &pxo_clk.c,
555 .c = {
556 .dbg_name = "pll8_clk",
557 .ops = &clk_ops_pll_vote,
558 CLK_INIT(pll8_clk.c),
559 },
560};
561
Stephen Boyd94625ef2011-07-12 17:06:01 -0700562static struct pll_vote_clk pll14_clk = {
563 .rate = 480000000,
564 .en_reg = BB_PLL_ENA_SC0_REG,
565 .en_mask = BIT(14),
566 .status_reg = BB_PLL14_STATUS_REG,
567 .parent = &pxo_clk.c,
568 .c = {
569 .dbg_name = "pll14_clk",
570 .ops = &clk_ops_pll_vote,
571 CLK_INIT(pll14_clk.c),
572 },
573};
574
Tianyi Gou41515e22011-09-01 19:37:43 -0700575static struct pll_clk pll15_clk = {
576 .rate = 975000000,
577 .mode_reg = MM_PLL3_MODE_REG,
578 .parent = &pxo_clk.c,
579 .c = {
580 .dbg_name = "pll15_clk",
581 .ops = &clk_ops_pll,
582 CLK_INIT(pll15_clk.c),
583 },
584};
585
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700586static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700587 .enable = rcg_clk_enable,
588 .disable = rcg_clk_disable,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800589 .enable_hwcg = rcg_clk_enable_hwcg,
590 .disable_hwcg = rcg_clk_disable_hwcg,
591 .in_hwcg_mode = rcg_clk_in_hwcg_mode,
Matt Wagantall41af0772011-09-17 12:21:39 -0700592 .auto_off = rcg_clk_disable,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700593 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700594 .set_rate = rcg_clk_set_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700595 .get_rate = rcg_clk_get_rate,
596 .list_rate = rcg_clk_list_rate,
597 .is_enabled = rcg_clk_is_enabled,
598 .round_rate = rcg_clk_round_rate,
Stephen Boyd7bf28142011-12-07 00:30:52 -0800599 .reset = rcg_clk_reset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700600 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700601 .get_parent = rcg_clk_get_parent,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800602 .set_flags = rcg_clk_set_flags,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700603};
604
605static struct clk_ops clk_ops_branch = {
606 .enable = branch_clk_enable,
607 .disable = branch_clk_disable,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800608 .enable_hwcg = branch_clk_enable_hwcg,
609 .disable_hwcg = branch_clk_disable_hwcg,
610 .in_hwcg_mode = branch_clk_in_hwcg_mode,
Matt Wagantall41af0772011-09-17 12:21:39 -0700611 .auto_off = branch_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700612 .is_enabled = branch_clk_is_enabled,
613 .reset = branch_clk_reset,
614 .is_local = local_clk_is_local,
615 .get_parent = branch_clk_get_parent,
616 .set_parent = branch_clk_set_parent,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800617 .handoff = branch_clk_handoff,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800618 .set_flags = branch_clk_set_flags,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700619};
620
621static struct clk_ops clk_ops_reset = {
622 .reset = branch_clk_reset,
623 .is_local = local_clk_is_local,
624};
625
626/* AXI Interfaces */
627static struct branch_clk gmem_axi_clk = {
628 .b = {
629 .ctl_reg = MAXI_EN_REG,
630 .en_mask = BIT(24),
631 .halt_reg = DBG_BUS_VEC_E_REG,
632 .halt_bit = 6,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800633 .retain_reg = MAXI_EN2_REG,
634 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700635 },
636 .c = {
637 .dbg_name = "gmem_axi_clk",
638 .ops = &clk_ops_branch,
639 CLK_INIT(gmem_axi_clk.c),
640 },
641};
642
643static struct branch_clk ijpeg_axi_clk = {
644 .b = {
645 .ctl_reg = MAXI_EN_REG,
646 .en_mask = BIT(21),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800647 .hwcg_reg = MAXI_EN_REG,
648 .hwcg_mask = BIT(11),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700649 .reset_reg = SW_RESET_AXI_REG,
650 .reset_mask = BIT(14),
651 .halt_reg = DBG_BUS_VEC_E_REG,
652 .halt_bit = 4,
653 },
654 .c = {
655 .dbg_name = "ijpeg_axi_clk",
656 .ops = &clk_ops_branch,
657 CLK_INIT(ijpeg_axi_clk.c),
658 },
659};
660
661static struct branch_clk imem_axi_clk = {
662 .b = {
663 .ctl_reg = MAXI_EN_REG,
664 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800665 .hwcg_reg = MAXI_EN_REG,
666 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700667 .reset_reg = SW_RESET_CORE_REG,
668 .reset_mask = BIT(10),
669 .halt_reg = DBG_BUS_VEC_E_REG,
670 .halt_bit = 7,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800671 .retain_reg = MAXI_EN2_REG,
672 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700673 },
674 .c = {
675 .dbg_name = "imem_axi_clk",
676 .ops = &clk_ops_branch,
677 CLK_INIT(imem_axi_clk.c),
678 },
679};
680
681static struct branch_clk jpegd_axi_clk = {
682 .b = {
683 .ctl_reg = MAXI_EN_REG,
684 .en_mask = BIT(25),
685 .halt_reg = DBG_BUS_VEC_E_REG,
686 .halt_bit = 5,
687 },
688 .c = {
689 .dbg_name = "jpegd_axi_clk",
690 .ops = &clk_ops_branch,
691 CLK_INIT(jpegd_axi_clk.c),
692 },
693};
694
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700695static struct branch_clk vcodec_axi_b_clk = {
696 .b = {
697 .ctl_reg = MAXI_EN4_REG,
698 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800699 .hwcg_reg = MAXI_EN4_REG,
700 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700701 .halt_reg = DBG_BUS_VEC_I_REG,
702 .halt_bit = 25,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800703 .retain_reg = MAXI_EN4_REG,
704 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700705 },
706 .c = {
707 .dbg_name = "vcodec_axi_b_clk",
708 .ops = &clk_ops_branch,
709 CLK_INIT(vcodec_axi_b_clk.c),
710 },
711};
712
Matt Wagantall91f42702011-07-14 12:01:15 -0700713static struct branch_clk vcodec_axi_a_clk = {
714 .b = {
715 .ctl_reg = MAXI_EN4_REG,
716 .en_mask = BIT(25),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800717 .hwcg_reg = MAXI_EN4_REG,
718 .hwcg_mask = BIT(24),
Matt Wagantall91f42702011-07-14 12:01:15 -0700719 .halt_reg = DBG_BUS_VEC_I_REG,
720 .halt_bit = 26,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800721 .retain_reg = MAXI_EN4_REG,
722 .retain_mask = BIT(10),
Matt Wagantall91f42702011-07-14 12:01:15 -0700723 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700724 .c = {
725 .dbg_name = "vcodec_axi_a_clk",
726 .ops = &clk_ops_branch,
727 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700728 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700729 },
730};
731
732static struct branch_clk vcodec_axi_clk = {
733 .b = {
734 .ctl_reg = MAXI_EN_REG,
735 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800736 .hwcg_reg = MAXI_EN_REG,
737 .hwcg_mask = BIT(13),
Matt Wagantall91f42702011-07-14 12:01:15 -0700738 .reset_reg = SW_RESET_AXI_REG,
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -0800739 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700740 .halt_reg = DBG_BUS_VEC_E_REG,
741 .halt_bit = 3,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800742 .retain_reg = MAXI_EN2_REG,
743 .retain_mask = BIT(28),
Matt Wagantall91f42702011-07-14 12:01:15 -0700744 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700745 .c = {
746 .dbg_name = "vcodec_axi_clk",
747 .ops = &clk_ops_branch,
748 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700749 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700750 },
751};
752
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700753static struct branch_clk vfe_axi_clk = {
754 .b = {
755 .ctl_reg = MAXI_EN_REG,
756 .en_mask = BIT(18),
757 .reset_reg = SW_RESET_AXI_REG,
758 .reset_mask = BIT(9),
759 .halt_reg = DBG_BUS_VEC_E_REG,
760 .halt_bit = 0,
761 },
762 .c = {
763 .dbg_name = "vfe_axi_clk",
764 .ops = &clk_ops_branch,
765 CLK_INIT(vfe_axi_clk.c),
766 },
767};
768
769static struct branch_clk mdp_axi_clk = {
770 .b = {
771 .ctl_reg = MAXI_EN_REG,
772 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800773 .hwcg_reg = MAXI_EN_REG,
774 .hwcg_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700775 .reset_reg = SW_RESET_AXI_REG,
776 .reset_mask = BIT(13),
777 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700778 .halt_bit = 8,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800779 .retain_reg = MAXI_EN_REG,
780 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700781 },
782 .c = {
783 .dbg_name = "mdp_axi_clk",
784 .ops = &clk_ops_branch,
785 CLK_INIT(mdp_axi_clk.c),
786 },
787};
788
789static struct branch_clk rot_axi_clk = {
790 .b = {
791 .ctl_reg = MAXI_EN2_REG,
792 .en_mask = BIT(24),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800793 .hwcg_reg = MAXI_EN2_REG,
794 .hwcg_mask = BIT(25),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700795 .reset_reg = SW_RESET_AXI_REG,
796 .reset_mask = BIT(6),
797 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700798 .halt_bit = 2,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800799 .retain_reg = MAXI_EN3_REG,
800 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700801 },
802 .c = {
803 .dbg_name = "rot_axi_clk",
804 .ops = &clk_ops_branch,
805 CLK_INIT(rot_axi_clk.c),
806 },
807};
808
809static struct branch_clk vpe_axi_clk = {
810 .b = {
811 .ctl_reg = MAXI_EN2_REG,
812 .en_mask = BIT(26),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800813 .hwcg_reg = MAXI_EN2_REG,
814 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700815 .reset_reg = SW_RESET_AXI_REG,
816 .reset_mask = BIT(15),
817 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700818 .halt_bit = 1,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800819 .retain_reg = MAXI_EN3_REG,
820 .retain_mask = BIT(21),
821
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700822 },
823 .c = {
824 .dbg_name = "vpe_axi_clk",
825 .ops = &clk_ops_branch,
826 CLK_INIT(vpe_axi_clk.c),
827 },
828};
829
Tianyi Gou41515e22011-09-01 19:37:43 -0700830static struct branch_clk vcap_axi_clk = {
831 .b = {
832 .ctl_reg = MAXI_EN5_REG,
833 .en_mask = BIT(12),
834 .reset_reg = SW_RESET_AXI_REG,
835 .reset_mask = BIT(16),
836 .halt_reg = DBG_BUS_VEC_J_REG,
837 .halt_bit = 20,
838 },
839 .c = {
840 .dbg_name = "vcap_axi_clk",
841 .ops = &clk_ops_branch,
842 CLK_INIT(vcap_axi_clk.c),
843 },
844};
845
Tianyi Gou621f8742011-09-01 21:45:01 -0700846/* For 8064, gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
847static struct branch_clk gfx3d_axi_clk = {
848 .b = {
849 .ctl_reg = MAXI_EN5_REG,
850 .en_mask = BIT(25),
851 .reset_reg = SW_RESET_AXI_REG,
852 .reset_mask = BIT(17),
853 .halt_reg = DBG_BUS_VEC_J_REG,
854 .halt_bit = 30,
855 },
856 .c = {
857 .dbg_name = "gfx3d_axi_clk",
858 .ops = &clk_ops_branch,
859 CLK_INIT(gfx3d_axi_clk.c),
860 },
861};
862
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700863/* AHB Interfaces */
864static struct branch_clk amp_p_clk = {
865 .b = {
866 .ctl_reg = AHB_EN_REG,
867 .en_mask = BIT(24),
868 .halt_reg = DBG_BUS_VEC_F_REG,
869 .halt_bit = 18,
870 },
871 .c = {
872 .dbg_name = "amp_p_clk",
873 .ops = &clk_ops_branch,
874 CLK_INIT(amp_p_clk.c),
875 },
876};
877
Matt Wagantallc23eee92011-08-16 23:06:52 -0700878static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700879 .b = {
880 .ctl_reg = AHB_EN_REG,
881 .en_mask = BIT(7),
882 .reset_reg = SW_RESET_AHB_REG,
883 .reset_mask = BIT(17),
884 .halt_reg = DBG_BUS_VEC_F_REG,
885 .halt_bit = 16,
886 },
887 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700888 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700889 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700890 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700891 },
892};
893
894static struct branch_clk dsi1_m_p_clk = {
895 .b = {
896 .ctl_reg = AHB_EN_REG,
897 .en_mask = BIT(9),
898 .reset_reg = SW_RESET_AHB_REG,
899 .reset_mask = BIT(6),
900 .halt_reg = DBG_BUS_VEC_F_REG,
901 .halt_bit = 19,
902 },
903 .c = {
904 .dbg_name = "dsi1_m_p_clk",
905 .ops = &clk_ops_branch,
906 CLK_INIT(dsi1_m_p_clk.c),
907 },
908};
909
910static struct branch_clk dsi1_s_p_clk = {
911 .b = {
912 .ctl_reg = AHB_EN_REG,
913 .en_mask = BIT(18),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800914 .hwcg_reg = AHB_EN2_REG,
915 .hwcg_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700916 .reset_reg = SW_RESET_AHB_REG,
917 .reset_mask = BIT(5),
918 .halt_reg = DBG_BUS_VEC_F_REG,
919 .halt_bit = 21,
920 },
921 .c = {
922 .dbg_name = "dsi1_s_p_clk",
923 .ops = &clk_ops_branch,
924 CLK_INIT(dsi1_s_p_clk.c),
925 },
926};
927
928static struct branch_clk dsi2_m_p_clk = {
929 .b = {
930 .ctl_reg = AHB_EN_REG,
931 .en_mask = BIT(17),
932 .reset_reg = SW_RESET_AHB2_REG,
933 .reset_mask = BIT(1),
934 .halt_reg = DBG_BUS_VEC_E_REG,
935 .halt_bit = 18,
936 },
937 .c = {
938 .dbg_name = "dsi2_m_p_clk",
939 .ops = &clk_ops_branch,
940 CLK_INIT(dsi2_m_p_clk.c),
941 },
942};
943
944static struct branch_clk dsi2_s_p_clk = {
945 .b = {
946 .ctl_reg = AHB_EN_REG,
947 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800948 .hwcg_reg = AHB_EN2_REG,
949 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700950 .reset_reg = SW_RESET_AHB2_REG,
951 .reset_mask = BIT(0),
952 .halt_reg = DBG_BUS_VEC_F_REG,
953 .halt_bit = 20,
954 },
955 .c = {
956 .dbg_name = "dsi2_s_p_clk",
957 .ops = &clk_ops_branch,
958 CLK_INIT(dsi2_s_p_clk.c),
959 },
960};
961
962static struct branch_clk gfx2d0_p_clk = {
963 .b = {
964 .ctl_reg = AHB_EN_REG,
965 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800966 .hwcg_reg = AHB_EN2_REG,
967 .hwcg_mask = BIT(28),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700968 .reset_reg = SW_RESET_AHB_REG,
969 .reset_mask = BIT(12),
970 .halt_reg = DBG_BUS_VEC_F_REG,
971 .halt_bit = 2,
972 },
973 .c = {
974 .dbg_name = "gfx2d0_p_clk",
975 .ops = &clk_ops_branch,
976 CLK_INIT(gfx2d0_p_clk.c),
977 },
978};
979
980static struct branch_clk gfx2d1_p_clk = {
981 .b = {
982 .ctl_reg = AHB_EN_REG,
983 .en_mask = BIT(2),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800984 .hwcg_reg = AHB_EN2_REG,
985 .hwcg_mask = BIT(29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700986 .reset_reg = SW_RESET_AHB_REG,
987 .reset_mask = BIT(11),
988 .halt_reg = DBG_BUS_VEC_F_REG,
989 .halt_bit = 3,
990 },
991 .c = {
992 .dbg_name = "gfx2d1_p_clk",
993 .ops = &clk_ops_branch,
994 CLK_INIT(gfx2d1_p_clk.c),
995 },
996};
997
998static struct branch_clk gfx3d_p_clk = {
999 .b = {
1000 .ctl_reg = AHB_EN_REG,
1001 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001002 .hwcg_reg = AHB_EN2_REG,
1003 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001004 .reset_reg = SW_RESET_AHB_REG,
1005 .reset_mask = BIT(10),
1006 .halt_reg = DBG_BUS_VEC_F_REG,
1007 .halt_bit = 4,
1008 },
1009 .c = {
1010 .dbg_name = "gfx3d_p_clk",
1011 .ops = &clk_ops_branch,
1012 CLK_INIT(gfx3d_p_clk.c),
1013 },
1014};
1015
1016static struct branch_clk hdmi_m_p_clk = {
1017 .b = {
1018 .ctl_reg = AHB_EN_REG,
1019 .en_mask = BIT(14),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001020 .hwcg_reg = AHB_EN2_REG,
1021 .hwcg_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001022 .reset_reg = SW_RESET_AHB_REG,
1023 .reset_mask = BIT(9),
1024 .halt_reg = DBG_BUS_VEC_F_REG,
1025 .halt_bit = 5,
1026 },
1027 .c = {
1028 .dbg_name = "hdmi_m_p_clk",
1029 .ops = &clk_ops_branch,
1030 CLK_INIT(hdmi_m_p_clk.c),
1031 },
1032};
1033
1034static struct branch_clk hdmi_s_p_clk = {
1035 .b = {
1036 .ctl_reg = AHB_EN_REG,
1037 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001038 .hwcg_reg = AHB_EN2_REG,
1039 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001040 .reset_reg = SW_RESET_AHB_REG,
1041 .reset_mask = BIT(9),
1042 .halt_reg = DBG_BUS_VEC_F_REG,
1043 .halt_bit = 6,
1044 },
1045 .c = {
1046 .dbg_name = "hdmi_s_p_clk",
1047 .ops = &clk_ops_branch,
1048 CLK_INIT(hdmi_s_p_clk.c),
1049 },
1050};
1051
1052static struct branch_clk ijpeg_p_clk = {
1053 .b = {
1054 .ctl_reg = AHB_EN_REG,
1055 .en_mask = BIT(5),
1056 .reset_reg = SW_RESET_AHB_REG,
1057 .reset_mask = BIT(7),
1058 .halt_reg = DBG_BUS_VEC_F_REG,
1059 .halt_bit = 9,
1060 },
1061 .c = {
1062 .dbg_name = "ijpeg_p_clk",
1063 .ops = &clk_ops_branch,
1064 CLK_INIT(ijpeg_p_clk.c),
1065 },
1066};
1067
1068static struct branch_clk imem_p_clk = {
1069 .b = {
1070 .ctl_reg = AHB_EN_REG,
1071 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001072 .hwcg_reg = AHB_EN2_REG,
1073 .hwcg_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001074 .reset_reg = SW_RESET_AHB_REG,
1075 .reset_mask = BIT(8),
1076 .halt_reg = DBG_BUS_VEC_F_REG,
1077 .halt_bit = 10,
1078 },
1079 .c = {
1080 .dbg_name = "imem_p_clk",
1081 .ops = &clk_ops_branch,
1082 CLK_INIT(imem_p_clk.c),
1083 },
1084};
1085
1086static struct branch_clk jpegd_p_clk = {
1087 .b = {
1088 .ctl_reg = AHB_EN_REG,
1089 .en_mask = BIT(21),
1090 .reset_reg = SW_RESET_AHB_REG,
1091 .reset_mask = BIT(4),
1092 .halt_reg = DBG_BUS_VEC_F_REG,
1093 .halt_bit = 7,
1094 },
1095 .c = {
1096 .dbg_name = "jpegd_p_clk",
1097 .ops = &clk_ops_branch,
1098 CLK_INIT(jpegd_p_clk.c),
1099 },
1100};
1101
1102static struct branch_clk mdp_p_clk = {
1103 .b = {
1104 .ctl_reg = AHB_EN_REG,
1105 .en_mask = BIT(10),
1106 .reset_reg = SW_RESET_AHB_REG,
1107 .reset_mask = BIT(3),
1108 .halt_reg = DBG_BUS_VEC_F_REG,
1109 .halt_bit = 11,
1110 },
1111 .c = {
1112 .dbg_name = "mdp_p_clk",
1113 .ops = &clk_ops_branch,
1114 CLK_INIT(mdp_p_clk.c),
1115 },
1116};
1117
1118static struct branch_clk rot_p_clk = {
1119 .b = {
1120 .ctl_reg = AHB_EN_REG,
1121 .en_mask = BIT(12),
1122 .reset_reg = SW_RESET_AHB_REG,
1123 .reset_mask = BIT(2),
1124 .halt_reg = DBG_BUS_VEC_F_REG,
1125 .halt_bit = 13,
1126 },
1127 .c = {
1128 .dbg_name = "rot_p_clk",
1129 .ops = &clk_ops_branch,
1130 CLK_INIT(rot_p_clk.c),
1131 },
1132};
1133
1134static struct branch_clk smmu_p_clk = {
1135 .b = {
1136 .ctl_reg = AHB_EN_REG,
1137 .en_mask = BIT(15),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001138 .hwcg_reg = AHB_EN_REG,
1139 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001140 .halt_reg = DBG_BUS_VEC_F_REG,
1141 .halt_bit = 22,
1142 },
1143 .c = {
1144 .dbg_name = "smmu_p_clk",
1145 .ops = &clk_ops_branch,
1146 CLK_INIT(smmu_p_clk.c),
1147 },
1148};
1149
1150static struct branch_clk tv_enc_p_clk = {
1151 .b = {
1152 .ctl_reg = AHB_EN_REG,
1153 .en_mask = BIT(25),
1154 .reset_reg = SW_RESET_AHB_REG,
1155 .reset_mask = BIT(15),
1156 .halt_reg = DBG_BUS_VEC_F_REG,
1157 .halt_bit = 23,
1158 },
1159 .c = {
1160 .dbg_name = "tv_enc_p_clk",
1161 .ops = &clk_ops_branch,
1162 CLK_INIT(tv_enc_p_clk.c),
1163 },
1164};
1165
1166static struct branch_clk vcodec_p_clk = {
1167 .b = {
1168 .ctl_reg = AHB_EN_REG,
1169 .en_mask = BIT(11),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001170 .hwcg_reg = AHB_EN2_REG,
1171 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001172 .reset_reg = SW_RESET_AHB_REG,
1173 .reset_mask = BIT(1),
1174 .halt_reg = DBG_BUS_VEC_F_REG,
1175 .halt_bit = 12,
1176 },
1177 .c = {
1178 .dbg_name = "vcodec_p_clk",
1179 .ops = &clk_ops_branch,
1180 CLK_INIT(vcodec_p_clk.c),
1181 },
1182};
1183
1184static struct branch_clk vfe_p_clk = {
1185 .b = {
1186 .ctl_reg = AHB_EN_REG,
1187 .en_mask = BIT(13),
1188 .reset_reg = SW_RESET_AHB_REG,
1189 .reset_mask = BIT(0),
1190 .halt_reg = DBG_BUS_VEC_F_REG,
1191 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08001192 .retain_reg = AHB_EN2_REG,
1193 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001194 },
1195 .c = {
1196 .dbg_name = "vfe_p_clk",
1197 .ops = &clk_ops_branch,
1198 CLK_INIT(vfe_p_clk.c),
1199 },
1200};
1201
1202static struct branch_clk vpe_p_clk = {
1203 .b = {
1204 .ctl_reg = AHB_EN_REG,
1205 .en_mask = BIT(16),
1206 .reset_reg = SW_RESET_AHB_REG,
1207 .reset_mask = BIT(14),
1208 .halt_reg = DBG_BUS_VEC_F_REG,
1209 .halt_bit = 15,
1210 },
1211 .c = {
1212 .dbg_name = "vpe_p_clk",
1213 .ops = &clk_ops_branch,
1214 CLK_INIT(vpe_p_clk.c),
1215 },
1216};
1217
Tianyi Gou41515e22011-09-01 19:37:43 -07001218static struct branch_clk vcap_p_clk = {
1219 .b = {
1220 .ctl_reg = AHB_EN3_REG,
1221 .en_mask = BIT(1),
1222 .reset_reg = SW_RESET_AHB2_REG,
1223 .reset_mask = BIT(2),
1224 .halt_reg = DBG_BUS_VEC_J_REG,
1225 .halt_bit = 23,
1226 },
1227 .c = {
1228 .dbg_name = "vcap_p_clk",
1229 .ops = &clk_ops_branch,
1230 CLK_INIT(vcap_p_clk.c),
1231 },
1232};
1233
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001234/*
1235 * Peripheral Clocks
1236 */
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001237#define CLK_GP(i, n, h_r, h_b) \
1238 struct rcg_clk i##_clk = { \
1239 .b = { \
1240 .ctl_reg = GPn_NS_REG(n), \
1241 .en_mask = BIT(9), \
1242 .halt_reg = h_r, \
1243 .halt_bit = h_b, \
1244 }, \
1245 .ns_reg = GPn_NS_REG(n), \
1246 .md_reg = GPn_MD_REG(n), \
1247 .root_en_mask = BIT(11), \
1248 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1249 .set_rate = set_rate_mnd, \
1250 .freq_tbl = clk_tbl_gp, \
1251 .current_freq = &rcg_dummy_freq, \
1252 .c = { \
1253 .dbg_name = #i "_clk", \
1254 .ops = &clk_ops_rcg_8960, \
1255 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
1256 CLK_INIT(i##_clk.c), \
1257 }, \
1258 }
1259#define F_GP(f, s, d, m, n) \
1260 { \
1261 .freq_hz = f, \
1262 .src_clk = &s##_clk.c, \
1263 .md_val = MD8(16, m, 0, n), \
1264 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1265 .mnd_en_mask = BIT(8) * !!(n), \
1266 }
1267static struct clk_freq_tbl clk_tbl_gp[] = {
1268 F_GP( 0, gnd, 1, 0, 0),
1269 F_GP( 9600000, cxo, 2, 0, 0),
1270 F_GP( 13500000, pxo, 2, 0, 0),
1271 F_GP( 19200000, cxo, 1, 0, 0),
1272 F_GP( 27000000, pxo, 1, 0, 0),
1273 F_GP( 64000000, pll8, 2, 1, 3),
1274 F_GP( 76800000, pll8, 1, 1, 5),
1275 F_GP( 96000000, pll8, 4, 0, 0),
1276 F_GP(128000000, pll8, 3, 0, 0),
1277 F_GP(192000000, pll8, 2, 0, 0),
1278 F_GP(384000000, pll8, 1, 0, 0),
1279 F_END
1280};
1281
1282static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
1283static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
1284static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
1285
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001286#define CLK_GSBI_UART(i, n, h_r, h_b) \
1287 struct rcg_clk i##_clk = { \
1288 .b = { \
1289 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1290 .en_mask = BIT(9), \
1291 .reset_reg = GSBIn_RESET_REG(n), \
1292 .reset_mask = BIT(0), \
1293 .halt_reg = h_r, \
1294 .halt_bit = h_b, \
1295 }, \
1296 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1297 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1298 .root_en_mask = BIT(11), \
1299 .ns_mask = (BM(31, 16) | BM(6, 0)), \
1300 .set_rate = set_rate_mnd, \
1301 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001302 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001303 .c = { \
1304 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001305 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001306 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001307 CLK_INIT(i##_clk.c), \
1308 }, \
1309 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001310#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001311 { \
1312 .freq_hz = f, \
1313 .src_clk = &s##_clk.c, \
1314 .md_val = MD16(m, n), \
1315 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1316 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001317 }
1318static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001319 F_GSBI_UART( 0, gnd, 1, 0, 0),
Matt Wagantall9a561f72012-01-19 16:13:12 -08001320 F_GSBI_UART( 1843200, pll8, 2, 6, 625),
1321 F_GSBI_UART( 3686400, pll8, 2, 12, 625),
1322 F_GSBI_UART( 7372800, pll8, 2, 24, 625),
1323 F_GSBI_UART(14745600, pll8, 2, 48, 625),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001324 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1325 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1326 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1327 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1328 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1329 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1330 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1331 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1332 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1333 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001334 F_END
1335};
1336
1337static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1338static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1339static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1340static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1341static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1342static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1343static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1344static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1345static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1346static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1347static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1348static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1349
1350#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1351 struct rcg_clk i##_clk = { \
1352 .b = { \
1353 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1354 .en_mask = BIT(9), \
1355 .reset_reg = GSBIn_RESET_REG(n), \
1356 .reset_mask = BIT(0), \
1357 .halt_reg = h_r, \
1358 .halt_bit = h_b, \
1359 }, \
1360 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1361 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1362 .root_en_mask = BIT(11), \
1363 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1364 .set_rate = set_rate_mnd, \
1365 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001366 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001367 .c = { \
1368 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001369 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001370 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001371 CLK_INIT(i##_clk.c), \
1372 }, \
1373 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001374#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001375 { \
1376 .freq_hz = f, \
1377 .src_clk = &s##_clk.c, \
1378 .md_val = MD8(16, m, 0, n), \
1379 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1380 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001381 }
1382static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001383 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1384 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1385 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1386 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1387 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1388 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1389 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1390 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1391 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1392 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001393 F_END
1394};
1395
1396static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1397static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1398static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1399static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1400static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1401static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1402static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1403static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1404static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1405static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1406static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1407static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1408
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001409#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001410 { \
1411 .freq_hz = f, \
1412 .src_clk = &s##_clk.c, \
1413 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001414 }
1415static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001416 F_PDM( 0, gnd, 1),
1417 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001418 F_END
1419};
1420
1421static struct rcg_clk pdm_clk = {
1422 .b = {
1423 .ctl_reg = PDM_CLK_NS_REG,
1424 .en_mask = BIT(9),
1425 .reset_reg = PDM_CLK_NS_REG,
1426 .reset_mask = BIT(12),
1427 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1428 .halt_bit = 3,
1429 },
1430 .ns_reg = PDM_CLK_NS_REG,
1431 .root_en_mask = BIT(11),
1432 .ns_mask = BM(1, 0),
1433 .set_rate = set_rate_nop,
1434 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001435 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001436 .c = {
1437 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001438 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001439 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001440 CLK_INIT(pdm_clk.c),
1441 },
1442};
1443
1444static struct branch_clk pmem_clk = {
1445 .b = {
1446 .ctl_reg = PMEM_ACLK_CTL_REG,
1447 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001448 .hwcg_reg = PMEM_ACLK_CTL_REG,
1449 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001450 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1451 .halt_bit = 20,
1452 },
1453 .c = {
1454 .dbg_name = "pmem_clk",
1455 .ops = &clk_ops_branch,
1456 CLK_INIT(pmem_clk.c),
1457 },
1458};
1459
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001460#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001461 { \
1462 .freq_hz = f, \
1463 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001464 }
1465static struct clk_freq_tbl clk_tbl_prng[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001466 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001467 F_END
1468};
1469
1470static struct rcg_clk prng_clk = {
1471 .b = {
1472 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1473 .en_mask = BIT(10),
1474 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1475 .halt_check = HALT_VOTED,
1476 .halt_bit = 10,
1477 },
1478 .set_rate = set_rate_nop,
1479 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001480 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001481 .c = {
1482 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001483 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001484 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001485 CLK_INIT(prng_clk.c),
1486 },
1487};
1488
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001489#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001490 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001491 .b = { \
1492 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1493 .en_mask = BIT(9), \
1494 .reset_reg = SDCn_RESET_REG(n), \
1495 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001496 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001497 .halt_bit = h_b, \
1498 }, \
1499 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1500 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1501 .root_en_mask = BIT(11), \
1502 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1503 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001504 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001505 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001506 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001507 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001508 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001509 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001510 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001511 }, \
1512 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001513#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001514 { \
1515 .freq_hz = f, \
1516 .src_clk = &s##_clk.c, \
1517 .md_val = MD8(16, m, 0, n), \
1518 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1519 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001520 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001521static struct clk_freq_tbl clk_tbl_sdc[] = {
1522 F_SDC( 0, gnd, 1, 0, 0),
1523 F_SDC( 144000, pxo, 3, 2, 125),
1524 F_SDC( 400000, pll8, 4, 1, 240),
1525 F_SDC( 16000000, pll8, 4, 1, 6),
1526 F_SDC( 17070000, pll8, 1, 2, 45),
1527 F_SDC( 20210000, pll8, 1, 1, 19),
1528 F_SDC( 24000000, pll8, 4, 1, 4),
1529 F_SDC( 48000000, pll8, 4, 1, 2),
1530 F_SDC( 64000000, pll8, 3, 1, 2),
1531 F_SDC( 96000000, pll8, 4, 0, 0),
Subhash Jadavanibd238ba2011-11-24 15:12:39 +05301532 F_SDC(192000000, pll8, 2, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001533 F_END
1534};
1535
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001536static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1537static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1538static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1539static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1540static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001541
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001542#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001543 { \
1544 .freq_hz = f, \
1545 .src_clk = &s##_clk.c, \
1546 .md_val = MD16(m, n), \
1547 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1548 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001549 }
1550static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001551 F_TSIF_REF( 0, gnd, 1, 0, 0),
1552 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001553 F_END
1554};
1555
1556static struct rcg_clk tsif_ref_clk = {
1557 .b = {
1558 .ctl_reg = TSIF_REF_CLK_NS_REG,
1559 .en_mask = BIT(9),
1560 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1561 .halt_bit = 5,
1562 },
1563 .ns_reg = TSIF_REF_CLK_NS_REG,
1564 .md_reg = TSIF_REF_CLK_MD_REG,
1565 .root_en_mask = BIT(11),
1566 .ns_mask = (BM(31, 16) | BM(6, 0)),
1567 .set_rate = set_rate_mnd,
1568 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001569 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001570 .c = {
1571 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001572 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001573 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001574 CLK_INIT(tsif_ref_clk.c),
1575 },
1576};
1577
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001578#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001579 { \
1580 .freq_hz = f, \
1581 .src_clk = &s##_clk.c, \
1582 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001583 }
1584static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001585 F_TSSC( 0, gnd),
1586 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001587 F_END
1588};
1589
1590static struct rcg_clk tssc_clk = {
1591 .b = {
1592 .ctl_reg = TSSC_CLK_CTL_REG,
1593 .en_mask = BIT(4),
1594 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1595 .halt_bit = 4,
1596 },
1597 .ns_reg = TSSC_CLK_CTL_REG,
1598 .ns_mask = BM(1, 0),
1599 .set_rate = set_rate_nop,
1600 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001601 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001602 .c = {
1603 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001604 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001605 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001606 CLK_INIT(tssc_clk.c),
1607 },
1608};
1609
Tianyi Gou41515e22011-09-01 19:37:43 -07001610#define CLK_USB_HS(name, n, h_b) \
1611 static struct rcg_clk name = { \
1612 .b = { \
1613 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1614 .en_mask = BIT(9), \
1615 .reset_reg = USB_HS##n##_RESET_REG, \
1616 .reset_mask = BIT(0), \
1617 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1618 .halt_bit = h_b, \
1619 }, \
1620 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1621 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1622 .root_en_mask = BIT(11), \
1623 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1624 .set_rate = set_rate_mnd, \
1625 .freq_tbl = clk_tbl_usb, \
1626 .current_freq = &rcg_dummy_freq, \
1627 .c = { \
1628 .dbg_name = #name, \
1629 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001630 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001631 CLK_INIT(name.c), \
1632 }, \
1633}
1634
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001635#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001636 { \
1637 .freq_hz = f, \
1638 .src_clk = &s##_clk.c, \
1639 .md_val = MD8(16, m, 0, n), \
1640 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1641 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001642 }
1643static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001644 F_USB( 0, gnd, 1, 0, 0),
1645 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001646 F_END
1647};
1648
Tianyi Gou41515e22011-09-01 19:37:43 -07001649CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1650CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1651CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001652
Stephen Boyd94625ef2011-07-12 17:06:01 -07001653static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001654 F_USB( 0, gnd, 1, 0, 0),
1655 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001656 F_END
1657};
1658
1659static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1660 .b = {
1661 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1662 .en_mask = BIT(9),
1663 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1664 .halt_bit = 26,
1665 },
1666 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1667 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1668 .root_en_mask = BIT(11),
1669 .ns_mask = (BM(23, 16) | BM(6, 0)),
1670 .set_rate = set_rate_mnd,
1671 .freq_tbl = clk_tbl_usb_hsic,
1672 .current_freq = &rcg_dummy_freq,
1673 .c = {
1674 .dbg_name = "usb_hsic_xcvr_fs_clk",
1675 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001676 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001677 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1678 },
1679};
1680
1681static struct branch_clk usb_hsic_system_clk = {
1682 .b = {
1683 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1684 .en_mask = BIT(4),
1685 .reset_reg = USB_HSIC_RESET_REG,
1686 .reset_mask = BIT(0),
1687 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1688 .halt_bit = 24,
1689 },
1690 .parent = &usb_hsic_xcvr_fs_clk.c,
1691 .c = {
1692 .dbg_name = "usb_hsic_system_clk",
1693 .ops = &clk_ops_branch,
1694 CLK_INIT(usb_hsic_system_clk.c),
1695 },
1696};
1697
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001698#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001699 { \
1700 .freq_hz = f, \
1701 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001702 }
1703static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001704 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001705 F_END
1706};
1707
1708static struct rcg_clk usb_hsic_hsic_src_clk = {
1709 .b = {
1710 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1711 .halt_check = NOCHECK,
1712 },
1713 .root_en_mask = BIT(0),
1714 .set_rate = set_rate_nop,
1715 .freq_tbl = clk_tbl_usb2_hsic,
1716 .current_freq = &rcg_dummy_freq,
1717 .c = {
1718 .dbg_name = "usb_hsic_hsic_src_clk",
1719 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001720 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001721 CLK_INIT(usb_hsic_hsic_src_clk.c),
1722 },
1723};
1724
1725static struct branch_clk usb_hsic_hsic_clk = {
1726 .b = {
1727 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1728 .en_mask = BIT(0),
1729 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1730 .halt_bit = 19,
1731 },
1732 .parent = &usb_hsic_hsic_src_clk.c,
1733 .c = {
1734 .dbg_name = "usb_hsic_hsic_clk",
1735 .ops = &clk_ops_branch,
1736 CLK_INIT(usb_hsic_hsic_clk.c),
1737 },
1738};
1739
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001740#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001741 { \
1742 .freq_hz = f, \
1743 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001744 }
1745static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001746 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001747 F_END
1748};
1749
1750static struct rcg_clk usb_hsic_hsio_cal_clk = {
1751 .b = {
1752 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1753 .en_mask = BIT(0),
1754 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1755 .halt_bit = 23,
1756 },
1757 .set_rate = set_rate_nop,
1758 .freq_tbl = clk_tbl_usb_hsio_cal,
1759 .current_freq = &rcg_dummy_freq,
1760 .c = {
1761 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyda0e82ec2011-09-19 12:18:45 -07001762 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001763 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001764 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1765 },
1766};
1767
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001768static struct branch_clk usb_phy0_clk = {
1769 .b = {
1770 .reset_reg = USB_PHY0_RESET_REG,
1771 .reset_mask = BIT(0),
1772 },
1773 .c = {
1774 .dbg_name = "usb_phy0_clk",
1775 .ops = &clk_ops_reset,
1776 CLK_INIT(usb_phy0_clk.c),
1777 },
1778};
1779
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001780#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001781 struct rcg_clk i##_clk = { \
1782 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1783 .b = { \
1784 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1785 .halt_check = NOCHECK, \
1786 }, \
1787 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1788 .root_en_mask = BIT(11), \
1789 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1790 .set_rate = set_rate_mnd, \
1791 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001792 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001793 .c = { \
1794 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001795 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001796 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001797 CLK_INIT(i##_clk.c), \
1798 }, \
1799 }
1800
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001801static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001802static struct branch_clk usb_fs1_xcvr_clk = {
1803 .b = {
1804 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1805 .en_mask = BIT(9),
1806 .reset_reg = USB_FSn_RESET_REG(1),
1807 .reset_mask = BIT(1),
1808 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1809 .halt_bit = 15,
1810 },
1811 .parent = &usb_fs1_src_clk.c,
1812 .c = {
1813 .dbg_name = "usb_fs1_xcvr_clk",
1814 .ops = &clk_ops_branch,
1815 CLK_INIT(usb_fs1_xcvr_clk.c),
1816 },
1817};
1818
1819static struct branch_clk usb_fs1_sys_clk = {
1820 .b = {
1821 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1822 .en_mask = BIT(4),
1823 .reset_reg = USB_FSn_RESET_REG(1),
1824 .reset_mask = BIT(0),
1825 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1826 .halt_bit = 16,
1827 },
1828 .parent = &usb_fs1_src_clk.c,
1829 .c = {
1830 .dbg_name = "usb_fs1_sys_clk",
1831 .ops = &clk_ops_branch,
1832 CLK_INIT(usb_fs1_sys_clk.c),
1833 },
1834};
1835
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001836static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001837static struct branch_clk usb_fs2_xcvr_clk = {
1838 .b = {
1839 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1840 .en_mask = BIT(9),
1841 .reset_reg = USB_FSn_RESET_REG(2),
1842 .reset_mask = BIT(1),
1843 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1844 .halt_bit = 12,
1845 },
1846 .parent = &usb_fs2_src_clk.c,
1847 .c = {
1848 .dbg_name = "usb_fs2_xcvr_clk",
1849 .ops = &clk_ops_branch,
1850 CLK_INIT(usb_fs2_xcvr_clk.c),
1851 },
1852};
1853
1854static struct branch_clk usb_fs2_sys_clk = {
1855 .b = {
1856 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1857 .en_mask = BIT(4),
1858 .reset_reg = USB_FSn_RESET_REG(2),
1859 .reset_mask = BIT(0),
1860 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1861 .halt_bit = 13,
1862 },
1863 .parent = &usb_fs2_src_clk.c,
1864 .c = {
1865 .dbg_name = "usb_fs2_sys_clk",
1866 .ops = &clk_ops_branch,
1867 CLK_INIT(usb_fs2_sys_clk.c),
1868 },
1869};
1870
1871/* Fast Peripheral Bus Clocks */
1872static struct branch_clk ce1_core_clk = {
1873 .b = {
1874 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1875 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001876 .hwcg_reg = CE1_CORE_CLK_CTL_REG,
1877 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001878 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1879 .halt_bit = 27,
1880 },
1881 .c = {
1882 .dbg_name = "ce1_core_clk",
1883 .ops = &clk_ops_branch,
1884 CLK_INIT(ce1_core_clk.c),
1885 },
1886};
Tianyi Gou41515e22011-09-01 19:37:43 -07001887
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001888static struct branch_clk ce1_p_clk = {
1889 .b = {
1890 .ctl_reg = CE1_HCLK_CTL_REG,
1891 .en_mask = BIT(4),
1892 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1893 .halt_bit = 1,
1894 },
1895 .c = {
1896 .dbg_name = "ce1_p_clk",
1897 .ops = &clk_ops_branch,
1898 CLK_INIT(ce1_p_clk.c),
1899 },
1900};
1901
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001902#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07001903 { \
1904 .freq_hz = f, \
1905 .src_clk = &s##_clk.c, \
1906 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001907 }
1908
1909static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001910 F_CE3( 0, gnd, 1),
1911 F_CE3( 48000000, pll8, 8),
1912 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07001913 F_END
1914};
1915
1916static struct rcg_clk ce3_src_clk = {
1917 .b = {
1918 .ctl_reg = CE3_CLK_SRC_NS_REG,
1919 .halt_check = NOCHECK,
1920 },
1921 .ns_reg = CE3_CLK_SRC_NS_REG,
1922 .root_en_mask = BIT(7),
1923 .ns_mask = BM(6, 0),
1924 .set_rate = set_rate_nop,
1925 .freq_tbl = clk_tbl_ce3,
1926 .current_freq = &rcg_dummy_freq,
1927 .c = {
1928 .dbg_name = "ce3_src_clk",
1929 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001930 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07001931 CLK_INIT(ce3_src_clk.c),
1932 },
1933};
1934
1935static struct branch_clk ce3_core_clk = {
1936 .b = {
1937 .ctl_reg = CE3_CORE_CLK_CTL_REG,
1938 .en_mask = BIT(4),
1939 .reset_reg = CE3_CORE_CLK_CTL_REG,
1940 .reset_mask = BIT(7),
1941 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1942 .halt_bit = 5,
1943 },
1944 .parent = &ce3_src_clk.c,
1945 .c = {
1946 .dbg_name = "ce3_core_clk",
1947 .ops = &clk_ops_branch,
1948 CLK_INIT(ce3_core_clk.c),
1949 }
1950};
1951
1952static struct branch_clk ce3_p_clk = {
1953 .b = {
1954 .ctl_reg = CE3_HCLK_CTL_REG,
1955 .en_mask = BIT(4),
1956 .reset_reg = CE3_HCLK_CTL_REG,
1957 .reset_mask = BIT(7),
1958 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1959 .halt_bit = 16,
1960 },
1961 .parent = &ce3_src_clk.c,
1962 .c = {
1963 .dbg_name = "ce3_p_clk",
1964 .ops = &clk_ops_branch,
1965 CLK_INIT(ce3_p_clk.c),
1966 }
1967};
1968
1969static struct branch_clk sata_phy_ref_clk = {
1970 .b = {
1971 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
1972 .en_mask = BIT(4),
1973 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1974 .halt_bit = 24,
1975 },
1976 .parent = &pxo_clk.c,
1977 .c = {
1978 .dbg_name = "sata_phy_ref_clk",
1979 .ops = &clk_ops_branch,
1980 CLK_INIT(sata_phy_ref_clk.c),
1981 },
1982};
1983
1984static struct branch_clk pcie_p_clk = {
1985 .b = {
1986 .ctl_reg = PCIE_HCLK_CTL_REG,
1987 .en_mask = BIT(4),
1988 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1989 .halt_bit = 8,
1990 },
1991 .c = {
1992 .dbg_name = "pcie_p_clk",
1993 .ops = &clk_ops_branch,
1994 CLK_INIT(pcie_p_clk.c),
1995 },
1996};
1997
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001998static struct branch_clk dma_bam_p_clk = {
1999 .b = {
2000 .ctl_reg = DMA_BAM_HCLK_CTL,
2001 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002002 .hwcg_reg = DMA_BAM_HCLK_CTL,
2003 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002004 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2005 .halt_bit = 12,
2006 },
2007 .c = {
2008 .dbg_name = "dma_bam_p_clk",
2009 .ops = &clk_ops_branch,
2010 CLK_INIT(dma_bam_p_clk.c),
2011 },
2012};
2013
2014static struct branch_clk gsbi1_p_clk = {
2015 .b = {
2016 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
2017 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002018 .hwcg_reg = GSBIn_HCLK_CTL_REG(1),
2019 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002020 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2021 .halt_bit = 11,
2022 },
2023 .c = {
2024 .dbg_name = "gsbi1_p_clk",
2025 .ops = &clk_ops_branch,
2026 CLK_INIT(gsbi1_p_clk.c),
2027 },
2028};
2029
2030static struct branch_clk gsbi2_p_clk = {
2031 .b = {
2032 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2033 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002034 .hwcg_reg = GSBIn_HCLK_CTL_REG(2),
2035 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002036 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2037 .halt_bit = 7,
2038 },
2039 .c = {
2040 .dbg_name = "gsbi2_p_clk",
2041 .ops = &clk_ops_branch,
2042 CLK_INIT(gsbi2_p_clk.c),
2043 },
2044};
2045
2046static struct branch_clk gsbi3_p_clk = {
2047 .b = {
2048 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2049 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002050 .hwcg_reg = GSBIn_HCLK_CTL_REG(3),
2051 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002052 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2053 .halt_bit = 3,
2054 },
2055 .c = {
2056 .dbg_name = "gsbi3_p_clk",
2057 .ops = &clk_ops_branch,
2058 CLK_INIT(gsbi3_p_clk.c),
2059 },
2060};
2061
2062static struct branch_clk gsbi4_p_clk = {
2063 .b = {
2064 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2065 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002066 .hwcg_reg = GSBIn_HCLK_CTL_REG(4),
2067 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002068 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2069 .halt_bit = 27,
2070 },
2071 .c = {
2072 .dbg_name = "gsbi4_p_clk",
2073 .ops = &clk_ops_branch,
2074 CLK_INIT(gsbi4_p_clk.c),
2075 },
2076};
2077
2078static struct branch_clk gsbi5_p_clk = {
2079 .b = {
2080 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2081 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002082 .hwcg_reg = GSBIn_HCLK_CTL_REG(5),
2083 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002084 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2085 .halt_bit = 23,
2086 },
2087 .c = {
2088 .dbg_name = "gsbi5_p_clk",
2089 .ops = &clk_ops_branch,
2090 CLK_INIT(gsbi5_p_clk.c),
2091 },
2092};
2093
2094static struct branch_clk gsbi6_p_clk = {
2095 .b = {
2096 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2097 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002098 .hwcg_reg = GSBIn_HCLK_CTL_REG(6),
2099 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002100 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2101 .halt_bit = 19,
2102 },
2103 .c = {
2104 .dbg_name = "gsbi6_p_clk",
2105 .ops = &clk_ops_branch,
2106 CLK_INIT(gsbi6_p_clk.c),
2107 },
2108};
2109
2110static struct branch_clk gsbi7_p_clk = {
2111 .b = {
2112 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2113 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002114 .hwcg_reg = GSBIn_HCLK_CTL_REG(7),
2115 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002116 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2117 .halt_bit = 15,
2118 },
2119 .c = {
2120 .dbg_name = "gsbi7_p_clk",
2121 .ops = &clk_ops_branch,
2122 CLK_INIT(gsbi7_p_clk.c),
2123 },
2124};
2125
2126static struct branch_clk gsbi8_p_clk = {
2127 .b = {
2128 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2129 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002130 .hwcg_reg = GSBIn_HCLK_CTL_REG(8),
2131 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002132 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2133 .halt_bit = 11,
2134 },
2135 .c = {
2136 .dbg_name = "gsbi8_p_clk",
2137 .ops = &clk_ops_branch,
2138 CLK_INIT(gsbi8_p_clk.c),
2139 },
2140};
2141
2142static struct branch_clk gsbi9_p_clk = {
2143 .b = {
2144 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2145 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002146 .hwcg_reg = GSBIn_HCLK_CTL_REG(9),
2147 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002148 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2149 .halt_bit = 7,
2150 },
2151 .c = {
2152 .dbg_name = "gsbi9_p_clk",
2153 .ops = &clk_ops_branch,
2154 CLK_INIT(gsbi9_p_clk.c),
2155 },
2156};
2157
2158static struct branch_clk gsbi10_p_clk = {
2159 .b = {
2160 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2161 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002162 .hwcg_reg = GSBIn_HCLK_CTL_REG(10),
2163 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002164 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2165 .halt_bit = 3,
2166 },
2167 .c = {
2168 .dbg_name = "gsbi10_p_clk",
2169 .ops = &clk_ops_branch,
2170 CLK_INIT(gsbi10_p_clk.c),
2171 },
2172};
2173
2174static struct branch_clk gsbi11_p_clk = {
2175 .b = {
2176 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2177 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002178 .hwcg_reg = GSBIn_HCLK_CTL_REG(11),
2179 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002180 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2181 .halt_bit = 18,
2182 },
2183 .c = {
2184 .dbg_name = "gsbi11_p_clk",
2185 .ops = &clk_ops_branch,
2186 CLK_INIT(gsbi11_p_clk.c),
2187 },
2188};
2189
2190static struct branch_clk gsbi12_p_clk = {
2191 .b = {
2192 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2193 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002194 .hwcg_reg = GSBIn_HCLK_CTL_REG(12),
2195 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002196 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2197 .halt_bit = 14,
2198 },
2199 .c = {
2200 .dbg_name = "gsbi12_p_clk",
2201 .ops = &clk_ops_branch,
2202 CLK_INIT(gsbi12_p_clk.c),
2203 },
2204};
2205
Tianyi Gou41515e22011-09-01 19:37:43 -07002206static struct branch_clk sata_phy_cfg_clk = {
2207 .b = {
2208 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2209 .en_mask = BIT(4),
2210 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2211 .halt_bit = 12,
2212 },
2213 .c = {
2214 .dbg_name = "sata_phy_cfg_clk",
2215 .ops = &clk_ops_branch,
2216 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002217 },
2218};
2219
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002220static struct branch_clk tsif_p_clk = {
2221 .b = {
2222 .ctl_reg = TSIF_HCLK_CTL_REG,
2223 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002224 .hwcg_reg = TSIF_HCLK_CTL_REG,
2225 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002226 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2227 .halt_bit = 7,
2228 },
2229 .c = {
2230 .dbg_name = "tsif_p_clk",
2231 .ops = &clk_ops_branch,
2232 CLK_INIT(tsif_p_clk.c),
2233 },
2234};
2235
2236static struct branch_clk usb_fs1_p_clk = {
2237 .b = {
2238 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2239 .en_mask = BIT(4),
2240 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2241 .halt_bit = 17,
2242 },
2243 .c = {
2244 .dbg_name = "usb_fs1_p_clk",
2245 .ops = &clk_ops_branch,
2246 CLK_INIT(usb_fs1_p_clk.c),
2247 },
2248};
2249
2250static struct branch_clk usb_fs2_p_clk = {
2251 .b = {
2252 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2253 .en_mask = BIT(4),
2254 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2255 .halt_bit = 14,
2256 },
2257 .c = {
2258 .dbg_name = "usb_fs2_p_clk",
2259 .ops = &clk_ops_branch,
2260 CLK_INIT(usb_fs2_p_clk.c),
2261 },
2262};
2263
2264static struct branch_clk usb_hs1_p_clk = {
2265 .b = {
2266 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2267 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002268 .hwcg_reg = USB_HS1_HCLK_CTL_REG,
2269 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002270 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2271 .halt_bit = 1,
2272 },
2273 .c = {
2274 .dbg_name = "usb_hs1_p_clk",
2275 .ops = &clk_ops_branch,
2276 CLK_INIT(usb_hs1_p_clk.c),
2277 },
2278};
2279
Tianyi Gou41515e22011-09-01 19:37:43 -07002280static struct branch_clk usb_hs3_p_clk = {
2281 .b = {
2282 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2283 .en_mask = BIT(4),
2284 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2285 .halt_bit = 31,
2286 },
2287 .c = {
2288 .dbg_name = "usb_hs3_p_clk",
2289 .ops = &clk_ops_branch,
2290 CLK_INIT(usb_hs3_p_clk.c),
2291 },
2292};
2293
2294static struct branch_clk usb_hs4_p_clk = {
2295 .b = {
2296 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2297 .en_mask = BIT(4),
2298 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2299 .halt_bit = 7,
2300 },
2301 .c = {
2302 .dbg_name = "usb_hs4_p_clk",
2303 .ops = &clk_ops_branch,
2304 CLK_INIT(usb_hs4_p_clk.c),
2305 },
2306};
2307
Stephen Boyd94625ef2011-07-12 17:06:01 -07002308static struct branch_clk usb_hsic_p_clk = {
2309 .b = {
2310 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2311 .en_mask = BIT(4),
2312 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2313 .halt_bit = 28,
2314 },
2315 .c = {
2316 .dbg_name = "usb_hsic_p_clk",
2317 .ops = &clk_ops_branch,
2318 CLK_INIT(usb_hsic_p_clk.c),
2319 },
2320};
2321
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002322static struct branch_clk sdc1_p_clk = {
2323 .b = {
2324 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2325 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002326 .hwcg_reg = SDCn_HCLK_CTL_REG(1),
2327 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002328 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2329 .halt_bit = 11,
2330 },
2331 .c = {
2332 .dbg_name = "sdc1_p_clk",
2333 .ops = &clk_ops_branch,
2334 CLK_INIT(sdc1_p_clk.c),
2335 },
2336};
2337
2338static struct branch_clk sdc2_p_clk = {
2339 .b = {
2340 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2341 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002342 .hwcg_reg = SDCn_HCLK_CTL_REG(2),
2343 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002344 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2345 .halt_bit = 10,
2346 },
2347 .c = {
2348 .dbg_name = "sdc2_p_clk",
2349 .ops = &clk_ops_branch,
2350 CLK_INIT(sdc2_p_clk.c),
2351 },
2352};
2353
2354static struct branch_clk sdc3_p_clk = {
2355 .b = {
2356 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2357 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002358 .hwcg_reg = SDCn_HCLK_CTL_REG(3),
2359 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002360 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2361 .halt_bit = 9,
2362 },
2363 .c = {
2364 .dbg_name = "sdc3_p_clk",
2365 .ops = &clk_ops_branch,
2366 CLK_INIT(sdc3_p_clk.c),
2367 },
2368};
2369
2370static struct branch_clk sdc4_p_clk = {
2371 .b = {
2372 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2373 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002374 .hwcg_reg = SDCn_HCLK_CTL_REG(4),
2375 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002376 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2377 .halt_bit = 8,
2378 },
2379 .c = {
2380 .dbg_name = "sdc4_p_clk",
2381 .ops = &clk_ops_branch,
2382 CLK_INIT(sdc4_p_clk.c),
2383 },
2384};
2385
2386static struct branch_clk sdc5_p_clk = {
2387 .b = {
2388 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2389 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002390 .hwcg_reg = SDCn_HCLK_CTL_REG(5),
2391 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002392 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2393 .halt_bit = 7,
2394 },
2395 .c = {
2396 .dbg_name = "sdc5_p_clk",
2397 .ops = &clk_ops_branch,
2398 CLK_INIT(sdc5_p_clk.c),
2399 },
2400};
2401
2402/* HW-Voteable Clocks */
2403static struct branch_clk adm0_clk = {
2404 .b = {
2405 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2406 .en_mask = BIT(2),
2407 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2408 .halt_check = HALT_VOTED,
2409 .halt_bit = 14,
2410 },
2411 .c = {
2412 .dbg_name = "adm0_clk",
2413 .ops = &clk_ops_branch,
2414 CLK_INIT(adm0_clk.c),
2415 },
2416};
2417
2418static struct branch_clk adm0_p_clk = {
2419 .b = {
2420 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2421 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002422 .hwcg_reg = ADM0_PBUS_CLK_CTL_REG,
2423 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002424 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2425 .halt_check = HALT_VOTED,
2426 .halt_bit = 13,
2427 },
2428 .c = {
2429 .dbg_name = "adm0_p_clk",
2430 .ops = &clk_ops_branch,
2431 CLK_INIT(adm0_p_clk.c),
2432 },
2433};
2434
2435static struct branch_clk pmic_arb0_p_clk = {
2436 .b = {
2437 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2438 .en_mask = BIT(8),
2439 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2440 .halt_check = HALT_VOTED,
2441 .halt_bit = 22,
2442 },
2443 .c = {
2444 .dbg_name = "pmic_arb0_p_clk",
2445 .ops = &clk_ops_branch,
2446 CLK_INIT(pmic_arb0_p_clk.c),
2447 },
2448};
2449
2450static struct branch_clk pmic_arb1_p_clk = {
2451 .b = {
2452 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2453 .en_mask = BIT(9),
2454 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2455 .halt_check = HALT_VOTED,
2456 .halt_bit = 21,
2457 },
2458 .c = {
2459 .dbg_name = "pmic_arb1_p_clk",
2460 .ops = &clk_ops_branch,
2461 CLK_INIT(pmic_arb1_p_clk.c),
2462 },
2463};
2464
2465static struct branch_clk pmic_ssbi2_clk = {
2466 .b = {
2467 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2468 .en_mask = BIT(7),
2469 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2470 .halt_check = HALT_VOTED,
2471 .halt_bit = 23,
2472 },
2473 .c = {
2474 .dbg_name = "pmic_ssbi2_clk",
2475 .ops = &clk_ops_branch,
2476 CLK_INIT(pmic_ssbi2_clk.c),
2477 },
2478};
2479
2480static struct branch_clk rpm_msg_ram_p_clk = {
2481 .b = {
2482 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2483 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002484 .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG,
2485 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002486 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2487 .halt_check = HALT_VOTED,
2488 .halt_bit = 12,
2489 },
2490 .c = {
2491 .dbg_name = "rpm_msg_ram_p_clk",
2492 .ops = &clk_ops_branch,
2493 CLK_INIT(rpm_msg_ram_p_clk.c),
2494 },
2495};
2496
2497/*
2498 * Multimedia Clocks
2499 */
2500
2501static struct branch_clk amp_clk = {
2502 .b = {
2503 .reset_reg = SW_RESET_CORE_REG,
2504 .reset_mask = BIT(20),
2505 },
2506 .c = {
2507 .dbg_name = "amp_clk",
2508 .ops = &clk_ops_reset,
2509 CLK_INIT(amp_clk.c),
2510 },
2511};
2512
Stephen Boyd94625ef2011-07-12 17:06:01 -07002513#define CLK_CAM(name, n, hb) \
2514 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002515 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002516 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002517 .en_mask = BIT(0), \
2518 .halt_reg = DBG_BUS_VEC_I_REG, \
2519 .halt_bit = hb, \
2520 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002521 .ns_reg = CAMCLK##n##_NS_REG, \
2522 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002523 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002524 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002525 .ctl_mask = BM(7, 6), \
2526 .set_rate = set_rate_mnd_8, \
2527 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002528 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002529 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002530 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002531 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002532 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002533 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002534 }, \
2535 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002536#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002537 { \
2538 .freq_hz = f, \
2539 .src_clk = &s##_clk.c, \
2540 .md_val = MD8(8, m, 0, n), \
2541 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2542 .ctl_val = CC(6, n), \
2543 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002544 }
2545static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002546 F_CAM( 0, gnd, 1, 0, 0),
2547 F_CAM( 6000000, pll8, 4, 1, 16),
2548 F_CAM( 8000000, pll8, 4, 1, 12),
2549 F_CAM( 12000000, pll8, 4, 1, 8),
2550 F_CAM( 16000000, pll8, 4, 1, 6),
2551 F_CAM( 19200000, pll8, 4, 1, 5),
2552 F_CAM( 24000000, pll8, 4, 1, 4),
2553 F_CAM( 32000000, pll8, 4, 1, 3),
2554 F_CAM( 48000000, pll8, 4, 1, 2),
2555 F_CAM( 64000000, pll8, 3, 1, 2),
2556 F_CAM( 96000000, pll8, 4, 0, 0),
2557 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002558 F_END
2559};
2560
Stephen Boyd94625ef2011-07-12 17:06:01 -07002561static CLK_CAM(cam0_clk, 0, 15);
2562static CLK_CAM(cam1_clk, 1, 16);
2563static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002564
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002565#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002566 { \
2567 .freq_hz = f, \
2568 .src_clk = &s##_clk.c, \
2569 .md_val = MD8(8, m, 0, n), \
2570 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2571 .ctl_val = CC(6, n), \
2572 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002573 }
2574static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002575 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002576 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002577 F_CSI( 85330000, pll8, 1, 2, 9),
2578 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002579 F_END
2580};
2581
2582static struct rcg_clk csi0_src_clk = {
2583 .ns_reg = CSI0_NS_REG,
2584 .b = {
2585 .ctl_reg = CSI0_CC_REG,
2586 .halt_check = NOCHECK,
2587 },
2588 .md_reg = CSI0_MD_REG,
2589 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002590 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002591 .ctl_mask = BM(7, 6),
2592 .set_rate = set_rate_mnd,
2593 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002594 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002595 .c = {
2596 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002597 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002598 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002599 CLK_INIT(csi0_src_clk.c),
2600 },
2601};
2602
2603static struct branch_clk csi0_clk = {
2604 .b = {
2605 .ctl_reg = CSI0_CC_REG,
2606 .en_mask = BIT(0),
2607 .reset_reg = SW_RESET_CORE_REG,
2608 .reset_mask = BIT(8),
2609 .halt_reg = DBG_BUS_VEC_B_REG,
2610 .halt_bit = 13,
2611 },
2612 .parent = &csi0_src_clk.c,
2613 .c = {
2614 .dbg_name = "csi0_clk",
2615 .ops = &clk_ops_branch,
2616 CLK_INIT(csi0_clk.c),
2617 },
2618};
2619
2620static struct branch_clk csi0_phy_clk = {
2621 .b = {
2622 .ctl_reg = CSI0_CC_REG,
2623 .en_mask = BIT(8),
2624 .reset_reg = SW_RESET_CORE_REG,
2625 .reset_mask = BIT(29),
2626 .halt_reg = DBG_BUS_VEC_I_REG,
2627 .halt_bit = 9,
2628 },
2629 .parent = &csi0_src_clk.c,
2630 .c = {
2631 .dbg_name = "csi0_phy_clk",
2632 .ops = &clk_ops_branch,
2633 CLK_INIT(csi0_phy_clk.c),
2634 },
2635};
2636
2637static struct rcg_clk csi1_src_clk = {
2638 .ns_reg = CSI1_NS_REG,
2639 .b = {
2640 .ctl_reg = CSI1_CC_REG,
2641 .halt_check = NOCHECK,
2642 },
2643 .md_reg = CSI1_MD_REG,
2644 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002645 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002646 .ctl_mask = BM(7, 6),
2647 .set_rate = set_rate_mnd,
2648 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002649 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002650 .c = {
2651 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002652 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002653 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002654 CLK_INIT(csi1_src_clk.c),
2655 },
2656};
2657
2658static struct branch_clk csi1_clk = {
2659 .b = {
2660 .ctl_reg = CSI1_CC_REG,
2661 .en_mask = BIT(0),
2662 .reset_reg = SW_RESET_CORE_REG,
2663 .reset_mask = BIT(18),
2664 .halt_reg = DBG_BUS_VEC_B_REG,
2665 .halt_bit = 14,
2666 },
2667 .parent = &csi1_src_clk.c,
2668 .c = {
2669 .dbg_name = "csi1_clk",
2670 .ops = &clk_ops_branch,
2671 CLK_INIT(csi1_clk.c),
2672 },
2673};
2674
2675static struct branch_clk csi1_phy_clk = {
2676 .b = {
2677 .ctl_reg = CSI1_CC_REG,
2678 .en_mask = BIT(8),
2679 .reset_reg = SW_RESET_CORE_REG,
2680 .reset_mask = BIT(28),
2681 .halt_reg = DBG_BUS_VEC_I_REG,
2682 .halt_bit = 10,
2683 },
2684 .parent = &csi1_src_clk.c,
2685 .c = {
2686 .dbg_name = "csi1_phy_clk",
2687 .ops = &clk_ops_branch,
2688 CLK_INIT(csi1_phy_clk.c),
2689 },
2690};
2691
Stephen Boyd94625ef2011-07-12 17:06:01 -07002692static struct rcg_clk csi2_src_clk = {
2693 .ns_reg = CSI2_NS_REG,
2694 .b = {
2695 .ctl_reg = CSI2_CC_REG,
2696 .halt_check = NOCHECK,
2697 },
2698 .md_reg = CSI2_MD_REG,
2699 .root_en_mask = BIT(2),
2700 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
2701 .ctl_mask = BM(7, 6),
2702 .set_rate = set_rate_mnd,
2703 .freq_tbl = clk_tbl_csi,
2704 .current_freq = &rcg_dummy_freq,
2705 .c = {
2706 .dbg_name = "csi2_src_clk",
2707 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002708 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002709 CLK_INIT(csi2_src_clk.c),
2710 },
2711};
2712
2713static struct branch_clk csi2_clk = {
2714 .b = {
2715 .ctl_reg = CSI2_CC_REG,
2716 .en_mask = BIT(0),
2717 .reset_reg = SW_RESET_CORE2_REG,
2718 .reset_mask = BIT(2),
2719 .halt_reg = DBG_BUS_VEC_B_REG,
2720 .halt_bit = 29,
2721 },
2722 .parent = &csi2_src_clk.c,
2723 .c = {
2724 .dbg_name = "csi2_clk",
2725 .ops = &clk_ops_branch,
2726 CLK_INIT(csi2_clk.c),
2727 },
2728};
2729
2730static struct branch_clk csi2_phy_clk = {
2731 .b = {
2732 .ctl_reg = CSI2_CC_REG,
2733 .en_mask = BIT(8),
2734 .reset_reg = SW_RESET_CORE_REG,
2735 .reset_mask = BIT(31),
2736 .halt_reg = DBG_BUS_VEC_I_REG,
2737 .halt_bit = 29,
2738 },
2739 .parent = &csi2_src_clk.c,
2740 .c = {
2741 .dbg_name = "csi2_phy_clk",
2742 .ops = &clk_ops_branch,
2743 CLK_INIT(csi2_phy_clk.c),
2744 },
2745};
2746
Stephen Boyd092fd182011-10-21 15:56:30 -07002747static struct clk *pix_rdi_mux_map[] = {
2748 [0] = &csi0_clk.c,
2749 [1] = &csi1_clk.c,
2750 [2] = &csi2_clk.c,
2751 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002752};
2753
Stephen Boyd092fd182011-10-21 15:56:30 -07002754struct pix_rdi_clk {
2755 bool enabled;
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002756 unsigned long cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002757
2758 void __iomem *const s_reg;
2759 u32 s_mask;
2760
2761 void __iomem *const s2_reg;
2762 u32 s2_mask;
2763
2764 struct branch b;
2765 struct clk c;
2766};
2767
2768static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk)
2769{
2770 return container_of(clk, struct pix_rdi_clk, c);
2771}
2772
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002773static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate)
Stephen Boyd092fd182011-10-21 15:56:30 -07002774{
2775 int ret, i;
2776 u32 reg;
2777 unsigned long flags;
2778 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2779 struct clk **mux_map = pix_rdi_mux_map;
2780
2781 /*
2782 * These clocks select three inputs via two muxes. One mux selects
2783 * between csi0 and csi1 and the second mux selects between that mux's
2784 * output and csi2. The source and destination selections for each
2785 * mux must be clocking for the switch to succeed so just turn on
2786 * all three sources because it's easier than figuring out what source
2787 * needs to be on at what time.
2788 */
2789 for (i = 0; mux_map[i]; i++) {
2790 ret = clk_enable(mux_map[i]);
2791 if (ret)
2792 goto err;
2793 }
2794 if (rate >= i) {
2795 ret = -EINVAL;
2796 goto err;
2797 }
2798 /* Keep the new source on when switching inputs of an enabled clock */
2799 if (clk->enabled) {
2800 clk_disable(mux_map[clk->cur_rate]);
2801 clk_enable(mux_map[rate]);
2802 }
2803 spin_lock_irqsave(&local_clock_reg_lock, flags);
2804 reg = readl_relaxed(clk->s2_reg);
2805 reg &= ~clk->s2_mask;
2806 reg |= rate == 2 ? clk->s2_mask : 0;
2807 writel_relaxed(reg, clk->s2_reg);
2808 /*
2809 * Wait at least 6 cycles of slowest clock
2810 * for the glitch-free MUX to fully switch sources.
2811 */
2812 mb();
2813 udelay(1);
2814 reg = readl_relaxed(clk->s_reg);
2815 reg &= ~clk->s_mask;
2816 reg |= rate == 1 ? clk->s_mask : 0;
2817 writel_relaxed(reg, clk->s_reg);
2818 /*
2819 * Wait at least 6 cycles of slowest clock
2820 * for the glitch-free MUX to fully switch sources.
2821 */
2822 mb();
2823 udelay(1);
2824 clk->cur_rate = rate;
2825 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2826err:
2827 for (i--; i >= 0; i--)
2828 clk_disable(mux_map[i]);
2829
2830 return 0;
2831}
2832
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002833static unsigned long pix_rdi_clk_get_rate(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002834{
2835 return to_pix_rdi_clk(c)->cur_rate;
2836}
2837
2838static int pix_rdi_clk_enable(struct clk *c)
2839{
2840 unsigned long flags;
2841 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2842
2843 spin_lock_irqsave(&local_clock_reg_lock, flags);
2844 __branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
2845 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2846 clk->enabled = true;
2847
2848 return 0;
2849}
2850
2851static void pix_rdi_clk_disable(struct clk *c)
2852{
2853 unsigned long flags;
2854 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2855
2856 spin_lock_irqsave(&local_clock_reg_lock, flags);
2857 __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
2858 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2859 clk->enabled = false;
2860}
2861
2862static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action)
2863{
2864 return branch_reset(&to_pix_rdi_clk(clk)->b, action);
2865}
2866
2867static struct clk *pix_rdi_clk_get_parent(struct clk *c)
2868{
2869 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2870
2871 return pix_rdi_mux_map[clk->cur_rate];
2872}
2873
2874static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
2875{
2876 if (pix_rdi_mux_map[n])
2877 return n;
2878 return -ENXIO;
2879}
2880
2881static int pix_rdi_clk_handoff(struct clk *c)
2882{
2883 u32 reg;
2884 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2885
2886 reg = readl_relaxed(clk->s_reg);
2887 clk->cur_rate = reg & clk->s_mask ? 1 : 0;
2888 reg = readl_relaxed(clk->s2_reg);
2889 clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate;
2890 return 0;
2891}
2892
2893static struct clk_ops clk_ops_pix_rdi_8960 = {
2894 .enable = pix_rdi_clk_enable,
2895 .disable = pix_rdi_clk_disable,
2896 .auto_off = pix_rdi_clk_disable,
2897 .handoff = pix_rdi_clk_handoff,
2898 .set_rate = pix_rdi_clk_set_rate,
2899 .get_rate = pix_rdi_clk_get_rate,
2900 .list_rate = pix_rdi_clk_list_rate,
2901 .reset = pix_rdi_clk_reset,
2902 .is_local = local_clk_is_local,
2903 .get_parent = pix_rdi_clk_get_parent,
2904};
2905
2906static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002907 .b = {
2908 .ctl_reg = MISC_CC_REG,
2909 .en_mask = BIT(26),
2910 .halt_check = DELAY,
2911 .reset_reg = SW_RESET_CORE_REG,
2912 .reset_mask = BIT(26),
2913 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002914 .s_reg = MISC_CC_REG,
2915 .s_mask = BIT(25),
2916 .s2_reg = MISC_CC3_REG,
2917 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002918 .c = {
2919 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002920 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002921 CLK_INIT(csi_pix_clk.c),
2922 },
2923};
2924
Stephen Boyd092fd182011-10-21 15:56:30 -07002925static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002926 .b = {
2927 .ctl_reg = MISC_CC3_REG,
2928 .en_mask = BIT(10),
2929 .halt_check = DELAY,
2930 .reset_reg = SW_RESET_CORE_REG,
2931 .reset_mask = BIT(30),
2932 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002933 .s_reg = MISC_CC3_REG,
2934 .s_mask = BIT(8),
2935 .s2_reg = MISC_CC3_REG,
2936 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002937 .c = {
2938 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002939 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002940 CLK_INIT(csi_pix1_clk.c),
2941 },
2942};
2943
Stephen Boyd092fd182011-10-21 15:56:30 -07002944static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002945 .b = {
2946 .ctl_reg = MISC_CC_REG,
2947 .en_mask = BIT(13),
2948 .halt_check = DELAY,
2949 .reset_reg = SW_RESET_CORE_REG,
2950 .reset_mask = BIT(27),
2951 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002952 .s_reg = MISC_CC_REG,
2953 .s_mask = BIT(12),
2954 .s2_reg = MISC_CC3_REG,
2955 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002956 .c = {
2957 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002958 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002959 CLK_INIT(csi_rdi_clk.c),
2960 },
2961};
2962
Stephen Boyd092fd182011-10-21 15:56:30 -07002963static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002964 .b = {
2965 .ctl_reg = MISC_CC3_REG,
2966 .en_mask = BIT(2),
2967 .halt_check = DELAY,
2968 .reset_reg = SW_RESET_CORE2_REG,
2969 .reset_mask = BIT(1),
2970 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002971 .s_reg = MISC_CC3_REG,
2972 .s_mask = BIT(0),
2973 .s2_reg = MISC_CC3_REG,
2974 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002975 .c = {
2976 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002977 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002978 CLK_INIT(csi_rdi1_clk.c),
2979 },
2980};
2981
Stephen Boyd092fd182011-10-21 15:56:30 -07002982static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002983 .b = {
2984 .ctl_reg = MISC_CC3_REG,
2985 .en_mask = BIT(6),
2986 .halt_check = DELAY,
2987 .reset_reg = SW_RESET_CORE2_REG,
2988 .reset_mask = BIT(0),
2989 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002990 .s_reg = MISC_CC3_REG,
2991 .s_mask = BIT(4),
2992 .s2_reg = MISC_CC3_REG,
2993 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002994 .c = {
2995 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002996 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002997 CLK_INIT(csi_rdi2_clk.c),
2998 },
2999};
3000
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003001#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003002 { \
3003 .freq_hz = f, \
3004 .src_clk = &s##_clk.c, \
3005 .md_val = MD8(8, m, 0, n), \
3006 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3007 .ctl_val = CC(6, n), \
3008 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003009 }
3010static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003011 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
3012 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
3013 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003014 F_END
3015};
3016
3017static struct rcg_clk csiphy_timer_src_clk = {
3018 .ns_reg = CSIPHYTIMER_NS_REG,
3019 .b = {
3020 .ctl_reg = CSIPHYTIMER_CC_REG,
3021 .halt_check = NOCHECK,
3022 },
3023 .md_reg = CSIPHYTIMER_MD_REG,
3024 .root_en_mask = BIT(2),
3025 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
3026 .ctl_mask = BM(7, 6),
3027 .set_rate = set_rate_mnd_8,
3028 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003029 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003030 .c = {
3031 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003032 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003033 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003034 CLK_INIT(csiphy_timer_src_clk.c),
3035 },
3036};
3037
3038static struct branch_clk csi0phy_timer_clk = {
3039 .b = {
3040 .ctl_reg = CSIPHYTIMER_CC_REG,
3041 .en_mask = BIT(0),
3042 .halt_reg = DBG_BUS_VEC_I_REG,
3043 .halt_bit = 17,
3044 },
3045 .parent = &csiphy_timer_src_clk.c,
3046 .c = {
3047 .dbg_name = "csi0phy_timer_clk",
3048 .ops = &clk_ops_branch,
3049 CLK_INIT(csi0phy_timer_clk.c),
3050 },
3051};
3052
3053static struct branch_clk csi1phy_timer_clk = {
3054 .b = {
3055 .ctl_reg = CSIPHYTIMER_CC_REG,
3056 .en_mask = BIT(9),
3057 .halt_reg = DBG_BUS_VEC_I_REG,
3058 .halt_bit = 18,
3059 },
3060 .parent = &csiphy_timer_src_clk.c,
3061 .c = {
3062 .dbg_name = "csi1phy_timer_clk",
3063 .ops = &clk_ops_branch,
3064 CLK_INIT(csi1phy_timer_clk.c),
3065 },
3066};
3067
Stephen Boyd94625ef2011-07-12 17:06:01 -07003068static struct branch_clk csi2phy_timer_clk = {
3069 .b = {
3070 .ctl_reg = CSIPHYTIMER_CC_REG,
3071 .en_mask = BIT(11),
3072 .halt_reg = DBG_BUS_VEC_I_REG,
3073 .halt_bit = 30,
3074 },
3075 .parent = &csiphy_timer_src_clk.c,
3076 .c = {
3077 .dbg_name = "csi2phy_timer_clk",
3078 .ops = &clk_ops_branch,
3079 CLK_INIT(csi2phy_timer_clk.c),
3080 },
3081};
3082
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003083#define F_DSI(d) \
3084 { \
3085 .freq_hz = d, \
3086 .ns_val = BVAL(15, 12, (d-1)), \
3087 }
3088/*
3089 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3090 * without this clock driver knowing. So, overload the clk_set_rate() to set
3091 * the divider (1 to 16) of the clock with respect to the PLL rate.
3092 */
3093static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3094 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3095 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3096 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3097 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3098 F_END
3099};
3100
3101static struct rcg_clk dsi1_byte_clk = {
3102 .b = {
3103 .ctl_reg = DSI1_BYTE_CC_REG,
3104 .en_mask = BIT(0),
3105 .reset_reg = SW_RESET_CORE_REG,
3106 .reset_mask = BIT(7),
3107 .halt_reg = DBG_BUS_VEC_B_REG,
3108 .halt_bit = 21,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003109 .retain_reg = DSI1_BYTE_CC_REG,
3110 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003111 },
3112 .ns_reg = DSI1_BYTE_NS_REG,
3113 .root_en_mask = BIT(2),
3114 .ns_mask = BM(15, 12),
3115 .set_rate = set_rate_nop,
3116 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003117 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003118 .c = {
3119 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003120 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003121 CLK_INIT(dsi1_byte_clk.c),
3122 },
3123};
3124
3125static struct rcg_clk dsi2_byte_clk = {
3126 .b = {
3127 .ctl_reg = DSI2_BYTE_CC_REG,
3128 .en_mask = BIT(0),
3129 .reset_reg = SW_RESET_CORE_REG,
3130 .reset_mask = BIT(25),
3131 .halt_reg = DBG_BUS_VEC_B_REG,
3132 .halt_bit = 20,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003133 .retain_reg = DSI2_BYTE_CC_REG,
3134 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003135 },
3136 .ns_reg = DSI2_BYTE_NS_REG,
3137 .root_en_mask = BIT(2),
3138 .ns_mask = BM(15, 12),
3139 .set_rate = set_rate_nop,
3140 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003141 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003142 .c = {
3143 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003144 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003145 CLK_INIT(dsi2_byte_clk.c),
3146 },
3147};
3148
3149static struct rcg_clk dsi1_esc_clk = {
3150 .b = {
3151 .ctl_reg = DSI1_ESC_CC_REG,
3152 .en_mask = BIT(0),
3153 .reset_reg = SW_RESET_CORE_REG,
3154 .halt_reg = DBG_BUS_VEC_I_REG,
3155 .halt_bit = 1,
3156 },
3157 .ns_reg = DSI1_ESC_NS_REG,
3158 .root_en_mask = BIT(2),
3159 .ns_mask = BM(15, 12),
3160 .set_rate = set_rate_nop,
3161 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003162 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003163 .c = {
3164 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003165 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003166 CLK_INIT(dsi1_esc_clk.c),
3167 },
3168};
3169
3170static struct rcg_clk dsi2_esc_clk = {
3171 .b = {
3172 .ctl_reg = DSI2_ESC_CC_REG,
3173 .en_mask = BIT(0),
3174 .halt_reg = DBG_BUS_VEC_I_REG,
3175 .halt_bit = 3,
3176 },
3177 .ns_reg = DSI2_ESC_NS_REG,
3178 .root_en_mask = BIT(2),
3179 .ns_mask = BM(15, 12),
3180 .set_rate = set_rate_nop,
3181 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003182 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003183 .c = {
3184 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003185 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003186 CLK_INIT(dsi2_esc_clk.c),
3187 },
3188};
3189
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003190#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003191 { \
3192 .freq_hz = f, \
3193 .src_clk = &s##_clk.c, \
3194 .md_val = MD4(4, m, 0, n), \
3195 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3196 .ctl_val = CC_BANKED(9, 6, n), \
3197 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003198 }
3199static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003200 F_GFX2D( 0, gnd, 0, 0),
3201 F_GFX2D( 27000000, pxo, 0, 0),
3202 F_GFX2D( 48000000, pll8, 1, 8),
3203 F_GFX2D( 54857000, pll8, 1, 7),
3204 F_GFX2D( 64000000, pll8, 1, 6),
3205 F_GFX2D( 76800000, pll8, 1, 5),
3206 F_GFX2D( 96000000, pll8, 1, 4),
3207 F_GFX2D(128000000, pll8, 1, 3),
3208 F_GFX2D(145455000, pll2, 2, 11),
3209 F_GFX2D(160000000, pll2, 1, 5),
3210 F_GFX2D(177778000, pll2, 2, 9),
3211 F_GFX2D(200000000, pll2, 1, 4),
3212 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003213 F_END
3214};
3215
3216static struct bank_masks bmnd_info_gfx2d0 = {
3217 .bank_sel_mask = BIT(11),
3218 .bank0_mask = {
3219 .md_reg = GFX2D0_MD0_REG,
3220 .ns_mask = BM(23, 20) | BM(5, 3),
3221 .rst_mask = BIT(25),
3222 .mnd_en_mask = BIT(8),
3223 .mode_mask = BM(10, 9),
3224 },
3225 .bank1_mask = {
3226 .md_reg = GFX2D0_MD1_REG,
3227 .ns_mask = BM(19, 16) | BM(2, 0),
3228 .rst_mask = BIT(24),
3229 .mnd_en_mask = BIT(5),
3230 .mode_mask = BM(7, 6),
3231 },
3232};
3233
3234static struct rcg_clk gfx2d0_clk = {
3235 .b = {
3236 .ctl_reg = GFX2D0_CC_REG,
3237 .en_mask = BIT(0),
3238 .reset_reg = SW_RESET_CORE_REG,
3239 .reset_mask = BIT(14),
3240 .halt_reg = DBG_BUS_VEC_A_REG,
3241 .halt_bit = 9,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003242 .retain_reg = GFX2D0_CC_REG,
3243 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003244 },
3245 .ns_reg = GFX2D0_NS_REG,
3246 .root_en_mask = BIT(2),
3247 .set_rate = set_rate_mnd_banked,
3248 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003249 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003250 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003251 .c = {
3252 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003253 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003254 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3255 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003256 CLK_INIT(gfx2d0_clk.c),
3257 },
3258};
3259
3260static struct bank_masks bmnd_info_gfx2d1 = {
3261 .bank_sel_mask = BIT(11),
3262 .bank0_mask = {
3263 .md_reg = GFX2D1_MD0_REG,
3264 .ns_mask = BM(23, 20) | BM(5, 3),
3265 .rst_mask = BIT(25),
3266 .mnd_en_mask = BIT(8),
3267 .mode_mask = BM(10, 9),
3268 },
3269 .bank1_mask = {
3270 .md_reg = GFX2D1_MD1_REG,
3271 .ns_mask = BM(19, 16) | BM(2, 0),
3272 .rst_mask = BIT(24),
3273 .mnd_en_mask = BIT(5),
3274 .mode_mask = BM(7, 6),
3275 },
3276};
3277
3278static struct rcg_clk gfx2d1_clk = {
3279 .b = {
3280 .ctl_reg = GFX2D1_CC_REG,
3281 .en_mask = BIT(0),
3282 .reset_reg = SW_RESET_CORE_REG,
3283 .reset_mask = BIT(13),
3284 .halt_reg = DBG_BUS_VEC_A_REG,
3285 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003286 .retain_reg = GFX2D1_CC_REG,
3287 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003288 },
3289 .ns_reg = GFX2D1_NS_REG,
3290 .root_en_mask = BIT(2),
3291 .set_rate = set_rate_mnd_banked,
3292 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003293 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003294 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003295 .c = {
3296 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003297 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003298 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3299 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003300 CLK_INIT(gfx2d1_clk.c),
3301 },
3302};
3303
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003304#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003305 { \
3306 .freq_hz = f, \
3307 .src_clk = &s##_clk.c, \
3308 .md_val = MD4(4, m, 0, n), \
3309 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3310 .ctl_val = CC_BANKED(9, 6, n), \
3311 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003312 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003313
3314static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003315 F_GFX3D( 0, gnd, 0, 0),
3316 F_GFX3D( 27000000, pxo, 0, 0),
3317 F_GFX3D( 48000000, pll8, 1, 8),
3318 F_GFX3D( 54857000, pll8, 1, 7),
3319 F_GFX3D( 64000000, pll8, 1, 6),
3320 F_GFX3D( 76800000, pll8, 1, 5),
3321 F_GFX3D( 96000000, pll8, 1, 4),
3322 F_GFX3D(128000000, pll8, 1, 3),
3323 F_GFX3D(145455000, pll2, 2, 11),
3324 F_GFX3D(160000000, pll2, 1, 5),
3325 F_GFX3D(177778000, pll2, 2, 9),
3326 F_GFX3D(200000000, pll2, 1, 4),
3327 F_GFX3D(228571000, pll2, 2, 7),
3328 F_GFX3D(266667000, pll2, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003329 F_GFX3D(300000000, pll3, 1, 4),
3330 F_GFX3D(320000000, pll2, 2, 5),
3331 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003332 F_END
3333};
3334
Tianyi Gou41515e22011-09-01 19:37:43 -07003335static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003336 F_GFX3D( 0, gnd, 0, 0),
3337 F_GFX3D( 27000000, pxo, 0, 0),
3338 F_GFX3D( 48000000, pll8, 1, 8),
3339 F_GFX3D( 54857000, pll8, 1, 7),
3340 F_GFX3D( 64000000, pll8, 1, 6),
3341 F_GFX3D( 76800000, pll8, 1, 5),
3342 F_GFX3D( 96000000, pll8, 1, 4),
3343 F_GFX3D(128000000, pll8, 1, 3),
3344 F_GFX3D(145455000, pll2, 2, 11),
3345 F_GFX3D(160000000, pll2, 1, 5),
3346 F_GFX3D(177778000, pll2, 2, 9),
3347 F_GFX3D(200000000, pll2, 1, 4),
3348 F_GFX3D(228571000, pll2, 2, 7),
3349 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07003350 F_GFX3D(325000000, pll15, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003351 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003352 F_END
3353};
3354
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003355static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3356 [VDD_DIG_LOW] = 128000000,
3357 [VDD_DIG_NOMINAL] = 325000000,
3358 [VDD_DIG_HIGH] = 400000000
3359};
3360
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003361static struct bank_masks bmnd_info_gfx3d = {
3362 .bank_sel_mask = BIT(11),
3363 .bank0_mask = {
3364 .md_reg = GFX3D_MD0_REG,
3365 .ns_mask = BM(21, 18) | BM(5, 3),
3366 .rst_mask = BIT(23),
3367 .mnd_en_mask = BIT(8),
3368 .mode_mask = BM(10, 9),
3369 },
3370 .bank1_mask = {
3371 .md_reg = GFX3D_MD1_REG,
3372 .ns_mask = BM(17, 14) | BM(2, 0),
3373 .rst_mask = BIT(22),
3374 .mnd_en_mask = BIT(5),
3375 .mode_mask = BM(7, 6),
3376 },
3377};
3378
3379static struct rcg_clk gfx3d_clk = {
3380 .b = {
3381 .ctl_reg = GFX3D_CC_REG,
3382 .en_mask = BIT(0),
3383 .reset_reg = SW_RESET_CORE_REG,
3384 .reset_mask = BIT(12),
3385 .halt_reg = DBG_BUS_VEC_A_REG,
3386 .halt_bit = 4,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003387 .retain_reg = GFX3D_CC_REG,
3388 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003389 },
3390 .ns_reg = GFX3D_NS_REG,
3391 .root_en_mask = BIT(2),
3392 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003393 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003394 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003395 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003396 .c = {
3397 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003398 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003399 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000,
3400 HIGH, 400000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003401 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003402 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003403 },
3404};
3405
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003406#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003407 { \
3408 .freq_hz = f, \
3409 .src_clk = &s##_clk.c, \
3410 .md_val = MD4(4, m, 0, n), \
3411 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3412 .ctl_val = CC_BANKED(9, 6, n), \
3413 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003414 }
3415
3416static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003417 F_VCAP( 0, gnd, 0, 0),
3418 F_VCAP( 27000000, pxo, 0, 0),
3419 F_VCAP( 54860000, pll8, 1, 7),
3420 F_VCAP( 64000000, pll8, 1, 6),
3421 F_VCAP( 76800000, pll8, 1, 5),
3422 F_VCAP(128000000, pll8, 1, 3),
3423 F_VCAP(160000000, pll2, 1, 5),
3424 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003425 F_END
3426};
3427
3428static struct bank_masks bmnd_info_vcap = {
3429 .bank_sel_mask = BIT(11),
3430 .bank0_mask = {
3431 .md_reg = VCAP_MD0_REG,
3432 .ns_mask = BM(21, 18) | BM(5, 3),
3433 .rst_mask = BIT(23),
3434 .mnd_en_mask = BIT(8),
3435 .mode_mask = BM(10, 9),
3436 },
3437 .bank1_mask = {
3438 .md_reg = VCAP_MD1_REG,
3439 .ns_mask = BM(17, 14) | BM(2, 0),
3440 .rst_mask = BIT(22),
3441 .mnd_en_mask = BIT(5),
3442 .mode_mask = BM(7, 6),
3443 },
3444};
3445
3446static struct rcg_clk vcap_clk = {
3447 .b = {
3448 .ctl_reg = VCAP_CC_REG,
3449 .en_mask = BIT(0),
3450 .halt_reg = DBG_BUS_VEC_J_REG,
3451 .halt_bit = 15,
3452 },
3453 .ns_reg = VCAP_NS_REG,
3454 .root_en_mask = BIT(2),
3455 .set_rate = set_rate_mnd_banked,
3456 .freq_tbl = clk_tbl_vcap,
3457 .bank_info = &bmnd_info_vcap,
3458 .current_freq = &rcg_dummy_freq,
3459 .c = {
3460 .dbg_name = "vcap_clk",
3461 .ops = &clk_ops_rcg_8960,
3462 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003463 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003464 CLK_INIT(vcap_clk.c),
3465 },
3466};
3467
3468static struct branch_clk vcap_npl_clk = {
3469 .b = {
3470 .ctl_reg = VCAP_CC_REG,
3471 .en_mask = BIT(13),
3472 .halt_reg = DBG_BUS_VEC_J_REG,
3473 .halt_bit = 25,
3474 },
3475 .parent = &vcap_clk.c,
3476 .c = {
3477 .dbg_name = "vcap_npl_clk",
3478 .ops = &clk_ops_branch,
3479 CLK_INIT(vcap_npl_clk.c),
3480 },
3481};
3482
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003483#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003484 { \
3485 .freq_hz = f, \
3486 .src_clk = &s##_clk.c, \
3487 .md_val = MD8(8, m, 0, n), \
3488 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3489 .ctl_val = CC(6, n), \
3490 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003491 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003492
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003493static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3494 F_IJPEG( 0, gnd, 1, 0, 0),
3495 F_IJPEG( 27000000, pxo, 1, 0, 0),
3496 F_IJPEG( 36570000, pll8, 1, 2, 21),
3497 F_IJPEG( 54860000, pll8, 7, 0, 0),
3498 F_IJPEG( 96000000, pll8, 4, 0, 0),
3499 F_IJPEG(109710000, pll8, 1, 2, 7),
3500 F_IJPEG(128000000, pll8, 3, 0, 0),
3501 F_IJPEG(153600000, pll8, 1, 2, 5),
3502 F_IJPEG(200000000, pll2, 4, 0, 0),
3503 F_IJPEG(228571000, pll2, 1, 2, 7),
3504 F_IJPEG(266667000, pll2, 1, 1, 3),
3505 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003506 F_END
3507};
3508
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003509static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3510 [VDD_DIG_LOW] = 128000000,
3511 [VDD_DIG_NOMINAL] = 266667000,
3512 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003513};
3514
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003515static struct rcg_clk ijpeg_clk = {
3516 .b = {
3517 .ctl_reg = IJPEG_CC_REG,
3518 .en_mask = BIT(0),
3519 .reset_reg = SW_RESET_CORE_REG,
3520 .reset_mask = BIT(9),
3521 .halt_reg = DBG_BUS_VEC_A_REG,
3522 .halt_bit = 24,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003523 .retain_reg = IJPEG_CC_REG,
3524 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003525 },
3526 .ns_reg = IJPEG_NS_REG,
3527 .md_reg = IJPEG_MD_REG,
3528 .root_en_mask = BIT(2),
3529 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
3530 .ctl_mask = BM(7, 6),
3531 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003532 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003533 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003534 .c = {
3535 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003536 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003537 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
3538 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003539 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003540 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003541 },
3542};
3543
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003544#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003545 { \
3546 .freq_hz = f, \
3547 .src_clk = &s##_clk.c, \
3548 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003549 }
3550static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003551 F_JPEGD( 0, gnd, 1),
3552 F_JPEGD( 64000000, pll8, 6),
3553 F_JPEGD( 76800000, pll8, 5),
3554 F_JPEGD( 96000000, pll8, 4),
3555 F_JPEGD(160000000, pll2, 5),
3556 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003557 F_END
3558};
3559
3560static struct rcg_clk jpegd_clk = {
3561 .b = {
3562 .ctl_reg = JPEGD_CC_REG,
3563 .en_mask = BIT(0),
3564 .reset_reg = SW_RESET_CORE_REG,
3565 .reset_mask = BIT(19),
3566 .halt_reg = DBG_BUS_VEC_A_REG,
3567 .halt_bit = 19,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003568 .retain_reg = JPEGD_CC_REG,
3569 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003570 },
3571 .ns_reg = JPEGD_NS_REG,
3572 .root_en_mask = BIT(2),
3573 .ns_mask = (BM(15, 12) | BM(2, 0)),
3574 .set_rate = set_rate_nop,
3575 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003576 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003577 .c = {
3578 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003579 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003580 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003581 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003582 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003583 },
3584};
3585
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003586#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003587 { \
3588 .freq_hz = f, \
3589 .src_clk = &s##_clk.c, \
3590 .md_val = MD8(8, m, 0, n), \
3591 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3592 .ctl_val = CC_BANKED(9, 6, n), \
3593 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003594 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003595static struct clk_freq_tbl clk_tbl_mdp[] = {
3596 F_MDP( 0, gnd, 0, 0),
3597 F_MDP( 9600000, pll8, 1, 40),
3598 F_MDP( 13710000, pll8, 1, 28),
3599 F_MDP( 27000000, pxo, 0, 0),
3600 F_MDP( 29540000, pll8, 1, 13),
3601 F_MDP( 34910000, pll8, 1, 11),
3602 F_MDP( 38400000, pll8, 1, 10),
3603 F_MDP( 59080000, pll8, 2, 13),
3604 F_MDP( 76800000, pll8, 1, 5),
3605 F_MDP( 85330000, pll8, 2, 9),
3606 F_MDP( 96000000, pll8, 1, 4),
3607 F_MDP(128000000, pll8, 1, 3),
3608 F_MDP(160000000, pll2, 1, 5),
3609 F_MDP(177780000, pll2, 2, 9),
3610 F_MDP(200000000, pll2, 1, 4),
3611 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003612 F_END
3613};
3614
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003615static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3616 [VDD_DIG_LOW] = 128000000,
3617 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003618};
3619
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003620static struct bank_masks bmnd_info_mdp = {
3621 .bank_sel_mask = BIT(11),
3622 .bank0_mask = {
3623 .md_reg = MDP_MD0_REG,
3624 .ns_mask = BM(29, 22) | BM(5, 3),
3625 .rst_mask = BIT(31),
3626 .mnd_en_mask = BIT(8),
3627 .mode_mask = BM(10, 9),
3628 },
3629 .bank1_mask = {
3630 .md_reg = MDP_MD1_REG,
3631 .ns_mask = BM(21, 14) | BM(2, 0),
3632 .rst_mask = BIT(30),
3633 .mnd_en_mask = BIT(5),
3634 .mode_mask = BM(7, 6),
3635 },
3636};
3637
3638static struct rcg_clk mdp_clk = {
3639 .b = {
3640 .ctl_reg = MDP_CC_REG,
3641 .en_mask = BIT(0),
3642 .reset_reg = SW_RESET_CORE_REG,
3643 .reset_mask = BIT(21),
3644 .halt_reg = DBG_BUS_VEC_C_REG,
3645 .halt_bit = 10,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003646 .retain_reg = MDP_CC_REG,
3647 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003648 },
3649 .ns_reg = MDP_NS_REG,
3650 .root_en_mask = BIT(2),
3651 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003652 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003653 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003654 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003655 .c = {
3656 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003657 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003658 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003659 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003660 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003661 },
3662};
3663
3664static struct branch_clk lut_mdp_clk = {
3665 .b = {
3666 .ctl_reg = MDP_LUT_CC_REG,
3667 .en_mask = BIT(0),
3668 .halt_reg = DBG_BUS_VEC_I_REG,
3669 .halt_bit = 13,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003670 .retain_reg = MDP_LUT_CC_REG,
3671 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003672 },
3673 .parent = &mdp_clk.c,
3674 .c = {
3675 .dbg_name = "lut_mdp_clk",
3676 .ops = &clk_ops_branch,
3677 CLK_INIT(lut_mdp_clk.c),
3678 },
3679};
3680
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003681#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003682 { \
3683 .freq_hz = f, \
3684 .src_clk = &s##_clk.c, \
3685 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003686 }
3687static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003688 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003689 F_END
3690};
3691
3692static struct rcg_clk mdp_vsync_clk = {
3693 .b = {
3694 .ctl_reg = MISC_CC_REG,
3695 .en_mask = BIT(6),
3696 .reset_reg = SW_RESET_CORE_REG,
3697 .reset_mask = BIT(3),
3698 .halt_reg = DBG_BUS_VEC_B_REG,
3699 .halt_bit = 22,
3700 },
3701 .ns_reg = MISC_CC2_REG,
3702 .ns_mask = BIT(13),
3703 .set_rate = set_rate_nop,
3704 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003705 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003706 .c = {
3707 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003708 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003709 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003710 CLK_INIT(mdp_vsync_clk.c),
3711 },
3712};
3713
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003714#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003715 { \
3716 .freq_hz = f, \
3717 .src_clk = &s##_clk.c, \
3718 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3719 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003720 }
3721static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003722 F_ROT( 0, gnd, 1),
3723 F_ROT( 27000000, pxo, 1),
3724 F_ROT( 29540000, pll8, 13),
3725 F_ROT( 32000000, pll8, 12),
3726 F_ROT( 38400000, pll8, 10),
3727 F_ROT( 48000000, pll8, 8),
3728 F_ROT( 54860000, pll8, 7),
3729 F_ROT( 64000000, pll8, 6),
3730 F_ROT( 76800000, pll8, 5),
3731 F_ROT( 96000000, pll8, 4),
3732 F_ROT(100000000, pll2, 8),
3733 F_ROT(114290000, pll2, 7),
3734 F_ROT(133330000, pll2, 6),
3735 F_ROT(160000000, pll2, 5),
3736 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003737 F_END
3738};
3739
3740static struct bank_masks bdiv_info_rot = {
3741 .bank_sel_mask = BIT(30),
3742 .bank0_mask = {
3743 .ns_mask = BM(25, 22) | BM(18, 16),
3744 },
3745 .bank1_mask = {
3746 .ns_mask = BM(29, 26) | BM(21, 19),
3747 },
3748};
3749
3750static struct rcg_clk rot_clk = {
3751 .b = {
3752 .ctl_reg = ROT_CC_REG,
3753 .en_mask = BIT(0),
3754 .reset_reg = SW_RESET_CORE_REG,
3755 .reset_mask = BIT(2),
3756 .halt_reg = DBG_BUS_VEC_C_REG,
3757 .halt_bit = 15,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003758 .retain_reg = ROT_CC_REG,
3759 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003760 },
3761 .ns_reg = ROT_NS_REG,
3762 .root_en_mask = BIT(2),
3763 .set_rate = set_rate_div_banked,
3764 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003765 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003766 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003767 .c = {
3768 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003769 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003770 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003771 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003772 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003773 },
3774};
3775
3776static int hdmi_pll_clk_enable(struct clk *clk)
3777{
3778 int ret;
3779 unsigned long flags;
3780 spin_lock_irqsave(&local_clock_reg_lock, flags);
3781 ret = hdmi_pll_enable();
3782 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3783 return ret;
3784}
3785
3786static void hdmi_pll_clk_disable(struct clk *clk)
3787{
3788 unsigned long flags;
3789 spin_lock_irqsave(&local_clock_reg_lock, flags);
3790 hdmi_pll_disable();
3791 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3792}
3793
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07003794static unsigned long hdmi_pll_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003795{
3796 return hdmi_pll_get_rate();
3797}
3798
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003799static struct clk *hdmi_pll_clk_get_parent(struct clk *clk)
3800{
3801 return &pxo_clk.c;
3802}
3803
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003804static struct clk_ops clk_ops_hdmi_pll = {
3805 .enable = hdmi_pll_clk_enable,
3806 .disable = hdmi_pll_clk_disable,
3807 .get_rate = hdmi_pll_clk_get_rate,
3808 .is_local = local_clk_is_local,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003809 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003810};
3811
3812static struct clk hdmi_pll_clk = {
3813 .dbg_name = "hdmi_pll_clk",
3814 .ops = &clk_ops_hdmi_pll,
3815 CLK_INIT(hdmi_pll_clk),
3816};
3817
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003818#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003819 { \
3820 .freq_hz = f, \
3821 .src_clk = &s##_clk.c, \
3822 .md_val = MD8(8, m, 0, n), \
3823 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3824 .ctl_val = CC(6, n), \
3825 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003826 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003827#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003828 { \
3829 .freq_hz = f, \
3830 .src_clk = &s##_clk, \
3831 .md_val = MD8(8, m, 0, n), \
3832 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3833 .ctl_val = CC(6, n), \
3834 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003835 .extra_freq_data = (void *)p_r, \
3836 }
3837/* Switching TV freqs requires PLL reconfiguration. */
3838static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003839 F_TV_GND( 0, gnd, 0, 1, 0, 0),
3840 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
3841 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
3842 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
3843 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
3844 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003845 F_END
3846};
3847
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003848static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
3849 [VDD_DIG_LOW] = 74250000,
3850 [VDD_DIG_NOMINAL] = 149000000
3851};
3852
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003853/*
3854 * Unlike other clocks, the TV rate is adjusted through PLL
3855 * re-programming. It is also routed through an MND divider.
3856 */
3857void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3858{
3859 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3860 if (pll_rate)
3861 hdmi_pll_set_rate(pll_rate);
3862 set_rate_mnd(clk, nf);
3863}
3864
3865static struct rcg_clk tv_src_clk = {
3866 .ns_reg = TV_NS_REG,
3867 .b = {
3868 .ctl_reg = TV_CC_REG,
3869 .halt_check = NOCHECK,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003870 .retain_reg = TV_CC_REG,
3871 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003872 },
3873 .md_reg = TV_MD_REG,
3874 .root_en_mask = BIT(2),
3875 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
3876 .ctl_mask = BM(7, 6),
3877 .set_rate = set_rate_tv,
3878 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003879 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003880 .c = {
3881 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003882 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003883 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003884 CLK_INIT(tv_src_clk.c),
3885 },
3886};
3887
3888static struct branch_clk tv_enc_clk = {
3889 .b = {
3890 .ctl_reg = TV_CC_REG,
3891 .en_mask = BIT(8),
3892 .reset_reg = SW_RESET_CORE_REG,
3893 .reset_mask = BIT(0),
3894 .halt_reg = DBG_BUS_VEC_D_REG,
3895 .halt_bit = 9,
3896 },
3897 .parent = &tv_src_clk.c,
3898 .c = {
3899 .dbg_name = "tv_enc_clk",
3900 .ops = &clk_ops_branch,
3901 CLK_INIT(tv_enc_clk.c),
3902 },
3903};
3904
3905static struct branch_clk tv_dac_clk = {
3906 .b = {
3907 .ctl_reg = TV_CC_REG,
3908 .en_mask = BIT(10),
3909 .halt_reg = DBG_BUS_VEC_D_REG,
3910 .halt_bit = 10,
3911 },
3912 .parent = &tv_src_clk.c,
3913 .c = {
3914 .dbg_name = "tv_dac_clk",
3915 .ops = &clk_ops_branch,
3916 CLK_INIT(tv_dac_clk.c),
3917 },
3918};
3919
3920static struct branch_clk mdp_tv_clk = {
3921 .b = {
3922 .ctl_reg = TV_CC_REG,
3923 .en_mask = BIT(0),
3924 .reset_reg = SW_RESET_CORE_REG,
3925 .reset_mask = BIT(4),
3926 .halt_reg = DBG_BUS_VEC_D_REG,
3927 .halt_bit = 12,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003928 .retain_reg = TV_CC2_REG,
3929 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003930 },
3931 .parent = &tv_src_clk.c,
3932 .c = {
3933 .dbg_name = "mdp_tv_clk",
3934 .ops = &clk_ops_branch,
3935 CLK_INIT(mdp_tv_clk.c),
3936 },
3937};
3938
3939static struct branch_clk hdmi_tv_clk = {
3940 .b = {
3941 .ctl_reg = TV_CC_REG,
3942 .en_mask = BIT(12),
3943 .reset_reg = SW_RESET_CORE_REG,
3944 .reset_mask = BIT(1),
3945 .halt_reg = DBG_BUS_VEC_D_REG,
3946 .halt_bit = 11,
3947 },
3948 .parent = &tv_src_clk.c,
3949 .c = {
3950 .dbg_name = "hdmi_tv_clk",
3951 .ops = &clk_ops_branch,
3952 CLK_INIT(hdmi_tv_clk.c),
3953 },
3954};
3955
3956static struct branch_clk hdmi_app_clk = {
3957 .b = {
3958 .ctl_reg = MISC_CC2_REG,
3959 .en_mask = BIT(11),
3960 .reset_reg = SW_RESET_CORE_REG,
3961 .reset_mask = BIT(11),
3962 .halt_reg = DBG_BUS_VEC_B_REG,
3963 .halt_bit = 25,
3964 },
3965 .c = {
3966 .dbg_name = "hdmi_app_clk",
3967 .ops = &clk_ops_branch,
3968 CLK_INIT(hdmi_app_clk.c),
3969 },
3970};
3971
3972static struct bank_masks bmnd_info_vcodec = {
3973 .bank_sel_mask = BIT(13),
3974 .bank0_mask = {
3975 .md_reg = VCODEC_MD0_REG,
3976 .ns_mask = BM(18, 11) | BM(2, 0),
3977 .rst_mask = BIT(31),
3978 .mnd_en_mask = BIT(5),
3979 .mode_mask = BM(7, 6),
3980 },
3981 .bank1_mask = {
3982 .md_reg = VCODEC_MD1_REG,
3983 .ns_mask = BM(26, 19) | BM(29, 27),
3984 .rst_mask = BIT(30),
3985 .mnd_en_mask = BIT(10),
3986 .mode_mask = BM(12, 11),
3987 },
3988};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003989#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003990 { \
3991 .freq_hz = f, \
3992 .src_clk = &s##_clk.c, \
3993 .md_val = MD8(8, m, 0, n), \
3994 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
3995 .ctl_val = CC_BANKED(6, 11, n), \
3996 .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003997 }
3998static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003999 F_VCODEC( 0, gnd, 0, 0),
4000 F_VCODEC( 27000000, pxo, 0, 0),
4001 F_VCODEC( 32000000, pll8, 1, 12),
4002 F_VCODEC( 48000000, pll8, 1, 8),
4003 F_VCODEC( 54860000, pll8, 1, 7),
4004 F_VCODEC( 96000000, pll8, 1, 4),
4005 F_VCODEC(133330000, pll2, 1, 6),
4006 F_VCODEC(200000000, pll2, 1, 4),
4007 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004008 F_END
4009};
4010
4011static struct rcg_clk vcodec_clk = {
4012 .b = {
4013 .ctl_reg = VCODEC_CC_REG,
4014 .en_mask = BIT(0),
4015 .reset_reg = SW_RESET_CORE_REG,
4016 .reset_mask = BIT(6),
4017 .halt_reg = DBG_BUS_VEC_C_REG,
4018 .halt_bit = 29,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004019 .retain_reg = VCODEC_CC_REG,
4020 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004021 },
4022 .ns_reg = VCODEC_NS_REG,
4023 .root_en_mask = BIT(2),
4024 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004025 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004026 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004027 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004028 .c = {
4029 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004030 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004031 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4032 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004033 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004034 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004035 },
4036};
4037
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004038#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004039 { \
4040 .freq_hz = f, \
4041 .src_clk = &s##_clk.c, \
4042 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004043 }
4044static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004045 F_VPE( 0, gnd, 1),
4046 F_VPE( 27000000, pxo, 1),
4047 F_VPE( 34909000, pll8, 11),
4048 F_VPE( 38400000, pll8, 10),
4049 F_VPE( 64000000, pll8, 6),
4050 F_VPE( 76800000, pll8, 5),
4051 F_VPE( 96000000, pll8, 4),
4052 F_VPE(100000000, pll2, 8),
4053 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004054 F_END
4055};
4056
4057static struct rcg_clk vpe_clk = {
4058 .b = {
4059 .ctl_reg = VPE_CC_REG,
4060 .en_mask = BIT(0),
4061 .reset_reg = SW_RESET_CORE_REG,
4062 .reset_mask = BIT(17),
4063 .halt_reg = DBG_BUS_VEC_A_REG,
4064 .halt_bit = 28,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004065 .retain_reg = VPE_CC_REG,
4066 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004067 },
4068 .ns_reg = VPE_NS_REG,
4069 .root_en_mask = BIT(2),
4070 .ns_mask = (BM(15, 12) | BM(2, 0)),
4071 .set_rate = set_rate_nop,
4072 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004073 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004074 .c = {
4075 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004076 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004077 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004078 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004079 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004080 },
4081};
4082
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004083#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004084 { \
4085 .freq_hz = f, \
4086 .src_clk = &s##_clk.c, \
4087 .md_val = MD8(8, m, 0, n), \
4088 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4089 .ctl_val = CC(6, n), \
4090 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004091 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004092
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004093static struct clk_freq_tbl clk_tbl_vfe[] = {
4094 F_VFE( 0, gnd, 1, 0, 0),
4095 F_VFE( 13960000, pll8, 1, 2, 55),
4096 F_VFE( 27000000, pxo, 1, 0, 0),
4097 F_VFE( 36570000, pll8, 1, 2, 21),
4098 F_VFE( 38400000, pll8, 2, 1, 5),
4099 F_VFE( 45180000, pll8, 1, 2, 17),
4100 F_VFE( 48000000, pll8, 2, 1, 4),
4101 F_VFE( 54860000, pll8, 1, 1, 7),
4102 F_VFE( 64000000, pll8, 2, 1, 3),
4103 F_VFE( 76800000, pll8, 1, 1, 5),
4104 F_VFE( 96000000, pll8, 2, 1, 2),
4105 F_VFE(109710000, pll8, 1, 2, 7),
4106 F_VFE(128000000, pll8, 1, 1, 3),
4107 F_VFE(153600000, pll8, 1, 2, 5),
4108 F_VFE(200000000, pll2, 2, 1, 2),
4109 F_VFE(228570000, pll2, 1, 2, 7),
4110 F_VFE(266667000, pll2, 1, 1, 3),
4111 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004112 F_END
4113};
4114
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004115static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4116 [VDD_DIG_LOW] = 128000000,
4117 [VDD_DIG_NOMINAL] = 266667000,
4118 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004119};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004120
4121static struct rcg_clk vfe_clk = {
4122 .b = {
4123 .ctl_reg = VFE_CC_REG,
4124 .reset_reg = SW_RESET_CORE_REG,
4125 .reset_mask = BIT(15),
4126 .halt_reg = DBG_BUS_VEC_B_REG,
4127 .halt_bit = 6,
4128 .en_mask = BIT(0),
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004129 .retain_reg = VFE_CC2_REG,
4130 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004131 },
4132 .ns_reg = VFE_NS_REG,
4133 .md_reg = VFE_MD_REG,
4134 .root_en_mask = BIT(2),
4135 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
4136 .ctl_mask = BM(7, 6),
4137 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004138 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004139 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004140 .c = {
4141 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004142 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08004143 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
4144 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004145 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004146 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004147 },
4148};
4149
Matt Wagantallc23eee92011-08-16 23:06:52 -07004150static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004151 .b = {
4152 .ctl_reg = VFE_CC_REG,
4153 .en_mask = BIT(12),
4154 .reset_reg = SW_RESET_CORE_REG,
4155 .reset_mask = BIT(24),
4156 .halt_reg = DBG_BUS_VEC_B_REG,
4157 .halt_bit = 8,
4158 },
4159 .parent = &vfe_clk.c,
4160 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004161 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004162 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004163 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004164 },
4165};
4166
4167/*
4168 * Low Power Audio Clocks
4169 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004170#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004171 { \
4172 .freq_hz = f, \
4173 .src_clk = &s##_clk.c, \
4174 .md_val = MD8(8, m, 0, n), \
4175 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4176 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004177 }
4178static struct clk_freq_tbl clk_tbl_aif_osr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004179 F_AIF_OSR( 0, gnd, 1, 0, 0),
4180 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4181 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4182 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4183 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4184 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4185 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4186 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4187 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4188 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4189 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4190 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004191 F_END
4192};
4193
4194#define CLK_AIF_OSR(i, ns, md, h_r) \
4195 struct rcg_clk i##_clk = { \
4196 .b = { \
4197 .ctl_reg = ns, \
4198 .en_mask = BIT(17), \
4199 .reset_reg = ns, \
4200 .reset_mask = BIT(19), \
4201 .halt_reg = h_r, \
4202 .halt_check = ENABLE, \
4203 .halt_bit = 1, \
4204 }, \
4205 .ns_reg = ns, \
4206 .md_reg = md, \
4207 .root_en_mask = BIT(9), \
4208 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4209 .set_rate = set_rate_mnd, \
4210 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004211 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004212 .c = { \
4213 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004214 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004215 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004216 CLK_INIT(i##_clk.c), \
4217 }, \
4218 }
4219#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4220 struct rcg_clk i##_clk = { \
4221 .b = { \
4222 .ctl_reg = ns, \
4223 .en_mask = BIT(21), \
4224 .reset_reg = ns, \
4225 .reset_mask = BIT(23), \
4226 .halt_reg = h_r, \
4227 .halt_check = ENABLE, \
4228 .halt_bit = 1, \
4229 }, \
4230 .ns_reg = ns, \
4231 .md_reg = md, \
4232 .root_en_mask = BIT(9), \
4233 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4234 .set_rate = set_rate_mnd, \
4235 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004236 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004237 .c = { \
4238 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004239 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004240 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004241 CLK_INIT(i##_clk.c), \
4242 }, \
4243 }
4244
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004245#define CLK_AIF_BIT(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004246 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004247 .b = { \
4248 .ctl_reg = ns, \
4249 .en_mask = BIT(15), \
4250 .halt_reg = h_r, \
4251 .halt_check = DELAY, \
4252 }, \
4253 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004254 .ext_mask = BIT(14), \
4255 .div_offset = 10, \
4256 .max_div = 16, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004257 .c = { \
4258 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004259 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004260 CLK_INIT(i##_clk.c), \
4261 }, \
4262 }
4263
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004264#define CLK_AIF_BIT_DIV(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004265 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004266 .b = { \
4267 .ctl_reg = ns, \
4268 .en_mask = BIT(19), \
4269 .halt_reg = h_r, \
Stephen Boyd7bb9cf82012-01-25 18:09:01 -08004270 .halt_check = DELAY, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004271 }, \
4272 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004273 .ext_mask = BIT(18), \
4274 .div_offset = 10, \
4275 .max_div = 256, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004276 .c = { \
4277 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004278 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004279 CLK_INIT(i##_clk.c), \
4280 }, \
4281 }
4282
4283static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4284 LCC_MI2S_STATUS_REG);
4285static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4286
4287static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4288 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4289static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4290 LCC_CODEC_I2S_MIC_STATUS_REG);
4291
4292static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4293 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4294static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4295 LCC_SPARE_I2S_MIC_STATUS_REG);
4296
4297static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4298 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4299static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4300 LCC_CODEC_I2S_SPKR_STATUS_REG);
4301
4302static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4303 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4304static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4305 LCC_SPARE_I2S_SPKR_STATUS_REG);
4306
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004307#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004308 { \
4309 .freq_hz = f, \
4310 .src_clk = &s##_clk.c, \
4311 .md_val = MD16(m, n), \
4312 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4313 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004314 }
4315static struct clk_freq_tbl clk_tbl_pcm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004316 F_PCM( 0, gnd, 1, 0, 0),
4317 F_PCM( 512000, pll4, 4, 1, 192),
4318 F_PCM( 768000, pll4, 4, 1, 128),
4319 F_PCM( 1024000, pll4, 4, 1, 96),
4320 F_PCM( 1536000, pll4, 4, 1, 64),
4321 F_PCM( 2048000, pll4, 4, 1, 48),
4322 F_PCM( 3072000, pll4, 4, 1, 32),
4323 F_PCM( 4096000, pll4, 4, 1, 24),
4324 F_PCM( 6144000, pll4, 4, 1, 16),
4325 F_PCM( 8192000, pll4, 4, 1, 12),
4326 F_PCM(12288000, pll4, 4, 1, 8),
4327 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004328 F_END
4329};
4330
4331static struct rcg_clk pcm_clk = {
4332 .b = {
4333 .ctl_reg = LCC_PCM_NS_REG,
4334 .en_mask = BIT(11),
4335 .reset_reg = LCC_PCM_NS_REG,
4336 .reset_mask = BIT(13),
4337 .halt_reg = LCC_PCM_STATUS_REG,
4338 .halt_check = ENABLE,
4339 .halt_bit = 0,
4340 },
4341 .ns_reg = LCC_PCM_NS_REG,
4342 .md_reg = LCC_PCM_MD_REG,
4343 .root_en_mask = BIT(9),
4344 .ns_mask = (BM(31, 16) | BM(6, 0)),
4345 .set_rate = set_rate_mnd,
4346 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004347 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004348 .c = {
4349 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004350 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004351 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004352 CLK_INIT(pcm_clk.c),
4353 },
4354};
4355
4356static struct rcg_clk audio_slimbus_clk = {
4357 .b = {
4358 .ctl_reg = LCC_SLIMBUS_NS_REG,
4359 .en_mask = BIT(10),
4360 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4361 .reset_mask = BIT(5),
4362 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4363 .halt_check = ENABLE,
4364 .halt_bit = 0,
4365 },
4366 .ns_reg = LCC_SLIMBUS_NS_REG,
4367 .md_reg = LCC_SLIMBUS_MD_REG,
4368 .root_en_mask = BIT(9),
4369 .ns_mask = (BM(31, 24) | BM(6, 0)),
4370 .set_rate = set_rate_mnd,
4371 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004372 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004373 .c = {
4374 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004375 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004376 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004377 CLK_INIT(audio_slimbus_clk.c),
4378 },
4379};
4380
4381static struct branch_clk sps_slimbus_clk = {
4382 .b = {
4383 .ctl_reg = LCC_SLIMBUS_NS_REG,
4384 .en_mask = BIT(12),
4385 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4386 .halt_check = ENABLE,
4387 .halt_bit = 1,
4388 },
4389 .parent = &audio_slimbus_clk.c,
4390 .c = {
4391 .dbg_name = "sps_slimbus_clk",
4392 .ops = &clk_ops_branch,
4393 CLK_INIT(sps_slimbus_clk.c),
4394 },
4395};
4396
4397static struct branch_clk slimbus_xo_src_clk = {
4398 .b = {
4399 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4400 .en_mask = BIT(2),
4401 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004402 .halt_bit = 28,
4403 },
4404 .parent = &sps_slimbus_clk.c,
4405 .c = {
4406 .dbg_name = "slimbus_xo_src_clk",
4407 .ops = &clk_ops_branch,
4408 CLK_INIT(slimbus_xo_src_clk.c),
4409 },
4410};
4411
Matt Wagantall735f01a2011-08-12 12:40:28 -07004412DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4413DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4414DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4415DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4416DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4417DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4418DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4419DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004420
4421static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4422static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
Manu Gautam7483f172011-11-08 15:22:26 +05304423static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c);
4424static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004425static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4426static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4427static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4428static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4429static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4430static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
Stephen Boyd1c51a492011-10-26 12:11:47 -07004431static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c);
Stephen Boydef5d1c42011-12-15 20:47:14 -08004432static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004433
4434static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
Stephen Boyd36466ae2012-01-18 20:58:27 -08004435static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004436
4437#ifdef CONFIG_DEBUG_FS
4438struct measure_sel {
4439 u32 test_vector;
4440 struct clk *clk;
4441};
4442
Matt Wagantall8b38f942011-08-02 18:23:18 -07004443static DEFINE_CLK_MEASURE(l2_m_clk);
4444static DEFINE_CLK_MEASURE(krait0_m_clk);
4445static DEFINE_CLK_MEASURE(krait1_m_clk);
Tianyi Gou455c13c2012-02-02 16:33:24 -08004446static DEFINE_CLK_MEASURE(krait2_m_clk);
4447static DEFINE_CLK_MEASURE(krait3_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004448static DEFINE_CLK_MEASURE(q6sw_clk);
4449static DEFINE_CLK_MEASURE(q6fw_clk);
4450static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004451
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004452static struct measure_sel measure_mux[] = {
4453 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4454 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4455 { TEST_PER_LS(0x13), &sdc1_clk.c },
4456 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4457 { TEST_PER_LS(0x15), &sdc2_clk.c },
4458 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4459 { TEST_PER_LS(0x17), &sdc3_clk.c },
4460 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4461 { TEST_PER_LS(0x19), &sdc4_clk.c },
4462 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4463 { TEST_PER_LS(0x1B), &sdc5_clk.c },
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004464 { TEST_PER_LS(0x1F), &gp0_clk.c },
4465 { TEST_PER_LS(0x20), &gp1_clk.c },
4466 { TEST_PER_LS(0x21), &gp2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004467 { TEST_PER_LS(0x25), &dfab_clk.c },
4468 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4469 { TEST_PER_LS(0x26), &pmem_clk.c },
4470 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4471 { TEST_PER_LS(0x33), &cfpb_clk.c },
4472 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4473 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4474 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4475 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4476 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4477 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4478 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4479 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4480 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4481 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4482 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4483 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4484 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4485 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4486 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4487 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4488 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4489 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4490 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4491 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4492 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4493 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4494 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4495 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4496 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4497 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4498 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4499 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4500 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4501 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4502 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4503 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4504 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4505 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4506 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4507 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4508 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004509 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4510 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4511 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4512 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4513 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4514 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4515 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4516 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4517 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004518 { TEST_PER_LS(0x78), &sfpb_clk.c },
4519 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4520 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4521 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4522 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4523 { TEST_PER_LS(0x7D), &prng_clk.c },
4524 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4525 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4526 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4527 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004528 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4529 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4530 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004531 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4532 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4533 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4534 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4535 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4536 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4537 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4538 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4539 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4540 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004541 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004542 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4543
4544 { TEST_PER_HS(0x07), &afab_clk.c },
4545 { TEST_PER_HS(0x07), &afab_a_clk.c },
4546 { TEST_PER_HS(0x18), &sfab_clk.c },
4547 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004548 { TEST_PER_HS(0x26), &q6sw_clk },
4549 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004550 { TEST_PER_HS(0x2A), &adm0_clk.c },
4551 { TEST_PER_HS(0x34), &ebi1_clk.c },
4552 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004553 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004554
4555 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4556 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4557 { TEST_MM_LS(0x02), &cam1_clk.c },
4558 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004559 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004560 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4561 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4562 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4563 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4564 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4565 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4566 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4567 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4568 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4569 { TEST_MM_LS(0x12), &imem_p_clk.c },
4570 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4571 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4572 { TEST_MM_LS(0x16), &rot_p_clk.c },
4573 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4574 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4575 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4576 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4577 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4578 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4579 { TEST_MM_LS(0x1D), &cam0_clk.c },
4580 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4581 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4582 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4583 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4584 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4585 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4586 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4587 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004588 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004589 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004590
4591 { TEST_MM_HS(0x00), &csi0_clk.c },
4592 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004593 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004594 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4595 { TEST_MM_HS(0x06), &vfe_clk.c },
4596 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4597 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4598 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4599 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4600 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4601 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4602 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4603 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4604 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4605 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4606 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4607 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4608 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4609 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4610 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4611 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4612 { TEST_MM_HS(0x1A), &mdp_clk.c },
4613 { TEST_MM_HS(0x1B), &rot_clk.c },
4614 { TEST_MM_HS(0x1C), &vpe_clk.c },
4615 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4616 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4617 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4618 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4619 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4620 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4621 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4622 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4623 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4624 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4625 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004626 { TEST_MM_HS(0x2D), &csi2_clk.c },
4627 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4628 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4629 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4630 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4631 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004632 { TEST_MM_HS(0x33), &vcap_clk.c },
4633 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Gou7747a962012-02-03 15:03:55 -08004634 { TEST_MM_HS(0x35), &vcap_axi_clk.c },
4635 { TEST_MM_HS(0x38), &gfx3d_axi_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004636
4637 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4638 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4639 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4640 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4641 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4642 { TEST_LPA(0x14), &pcm_clk.c },
4643 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004644
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004645 { TEST_LPA_HS(0x00), &q6_func_clk },
4646
Stephen Boyd46fdf0d2011-11-22 12:25:09 -08004647 { TEST_CPUL2(0x2), &l2_m_clk },
4648 { TEST_CPUL2(0x0), &krait0_m_clk },
4649 { TEST_CPUL2(0x1), &krait1_m_clk },
Tianyi Gou455c13c2012-02-02 16:33:24 -08004650 { TEST_CPUL2(0x4), &krait2_m_clk },
4651 { TEST_CPUL2(0x5), &krait3_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004652};
4653
4654static struct measure_sel *find_measure_sel(struct clk *clk)
4655{
4656 int i;
4657
4658 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4659 if (measure_mux[i].clk == clk)
4660 return &measure_mux[i];
4661 return NULL;
4662}
4663
Matt Wagantall8b38f942011-08-02 18:23:18 -07004664static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004665{
4666 int ret = 0;
4667 u32 clk_sel;
4668 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004669 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004670 unsigned long flags;
4671
4672 if (!parent)
4673 return -EINVAL;
4674
4675 p = find_measure_sel(parent);
4676 if (!p)
4677 return -EINVAL;
4678
4679 spin_lock_irqsave(&local_clock_reg_lock, flags);
4680
Matt Wagantall8b38f942011-08-02 18:23:18 -07004681 /*
4682 * Program the test vector, measurement period (sample_ticks)
4683 * and scaling multiplier.
4684 */
4685 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004686 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004687 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004688 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4689 case TEST_TYPE_PER_LS:
4690 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4691 break;
4692 case TEST_TYPE_PER_HS:
4693 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4694 break;
4695 case TEST_TYPE_MM_LS:
4696 writel_relaxed(0x4030D97, CLK_TEST_REG);
4697 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4698 break;
4699 case TEST_TYPE_MM_HS:
4700 writel_relaxed(0x402B800, CLK_TEST_REG);
4701 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4702 break;
4703 case TEST_TYPE_LPA:
4704 writel_relaxed(0x4030D98, CLK_TEST_REG);
4705 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4706 LCC_CLK_LS_DEBUG_CFG_REG);
4707 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004708 case TEST_TYPE_LPA_HS:
4709 writel_relaxed(0x402BC00, CLK_TEST_REG);
4710 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4711 LCC_CLK_HS_DEBUG_CFG_REG);
4712 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004713 case TEST_TYPE_CPUL2:
4714 writel_relaxed(0x4030400, CLK_TEST_REG);
4715 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4716 clk->sample_ticks = 0x4000;
4717 clk->multiplier = 2;
4718 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004719 default:
4720 ret = -EPERM;
4721 }
4722 /* Make sure test vector is set before starting measurements. */
4723 mb();
4724
4725 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4726
4727 return ret;
4728}
4729
4730/* Sample clock for 'ticks' reference clock ticks. */
4731static u32 run_measurement(unsigned ticks)
4732{
4733 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004734 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4735
4736 /* Wait for timer to become ready. */
4737 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4738 cpu_relax();
4739
4740 /* Run measurement and wait for completion. */
4741 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4742 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4743 cpu_relax();
4744
4745 /* Stop counters. */
4746 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4747
4748 /* Return measured ticks. */
4749 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4750}
4751
4752
4753/* Perform a hardware rate measurement for a given clock.
4754 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004755static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004756{
4757 unsigned long flags;
4758 u32 pdm_reg_backup, ringosc_reg_backup;
4759 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004760 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004761 unsigned ret;
4762
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004763 ret = clk_enable(&cxo_clk.c);
4764 if (ret) {
4765 pr_warning("CXO clock failed to enable. Can't measure\n");
4766 return 0;
4767 }
4768
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004769 spin_lock_irqsave(&local_clock_reg_lock, flags);
4770
4771 /* Enable CXO/4 and RINGOSC branch and root. */
4772 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4773 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4774 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4775 writel_relaxed(0xA00, RINGOSC_NS_REG);
4776
4777 /*
4778 * The ring oscillator counter will not reset if the measured clock
4779 * is not running. To detect this, run a short measurement before
4780 * the full measurement. If the raw results of the two are the same
4781 * then the clock must be off.
4782 */
4783
4784 /* Run a short measurement. (~1 ms) */
4785 raw_count_short = run_measurement(0x1000);
4786 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004787 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004788
4789 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4790 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4791
4792 /* Return 0 if the clock is off. */
4793 if (raw_count_full == raw_count_short)
4794 ret = 0;
4795 else {
4796 /* Compute rate in Hz. */
4797 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004798 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4799 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004800 }
4801
4802 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004803 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004804 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4805
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004806 clk_disable(&cxo_clk.c);
4807
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004808 return ret;
4809}
4810#else /* !CONFIG_DEBUG_FS */
4811static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4812{
4813 return -EINVAL;
4814}
4815
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004816static unsigned long measure_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004817{
4818 return 0;
4819}
4820#endif /* CONFIG_DEBUG_FS */
4821
4822static struct clk_ops measure_clk_ops = {
4823 .set_parent = measure_clk_set_parent,
4824 .get_rate = measure_clk_get_rate,
4825 .is_local = local_clk_is_local,
4826};
4827
Matt Wagantall8b38f942011-08-02 18:23:18 -07004828static struct measure_clk measure_clk = {
4829 .c = {
4830 .dbg_name = "measure_clk",
4831 .ops = &measure_clk_ops,
4832 CLK_INIT(measure_clk.c),
4833 },
4834 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004835};
4836
Tianyi Goua8b3cce2011-11-08 14:37:26 -08004837static struct clk_lookup msm_clocks_8064[] = {
Stephen Boyd7dd22662012-01-26 16:09:31 -08004838 CLK_LOOKUP("xo", cxo_clk.c, "msm_otg"),
Stephen Boyded630b02012-01-26 15:26:47 -08004839 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
4840 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
4841 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
4842 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
4843 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Matt Wagantall292aace2012-01-26 19:12:34 -08004844 CLK_LOOKUP("xo", cxo_clk.c, "pil_gss"),
Stephen Boyded630b02012-01-26 15:26:47 -08004845 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
4846 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
4847 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
4848 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004849
Tianyi Gou21a0e802012-02-04 22:34:10 -08004850 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
4851 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
4852 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
4853 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
4854 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
4855 CLK_LOOKUP("bus_a_clk", sfab_a_clk.c, "msm_sys_fab"),
4856 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
4857 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
4858 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
4859 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
4860 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
4861 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08004862
Tianyi Gou21a0e802012-02-04 22:34:10 -08004863 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, ""),
4864 CLK_LOOKUP("dfab_clk", dfab_clk.c, ""),
4865 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, ""),
4866 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, ""),
4867 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
4868 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004869
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004870 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
4871 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
4872 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004873 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004874 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
4875 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
4876 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
4877 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""),
4878 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004879 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004880 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, ""),
4881 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08004882 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004883 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, ""),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08004884 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004885 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
4886 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
4887 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Tianyi Gou50f23812012-02-06 16:04:19 -08004888 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Tianyi Gou05e01102012-02-08 22:15:49 -08004889 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004890 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
4891 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
4892 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
4893 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004894 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
4895 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08004896 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
4897 CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"),
4898 CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004899 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
4900 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
4901 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
4902 CLK_LOOKUP("iface_clk", ce1_p_clk.c, ""),
4903 CLK_LOOKUP("core_clk", ce1_core_clk.c, ""),
4904 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""),
4905 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07004906 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
4907 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
4908 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
4909 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
4910 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
4911 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004912 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004913 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004914 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08004915 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004916 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, ""),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08004917 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004918 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004919 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, "msm_serial_hsl.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004920 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
4921 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08004922 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Manu Gautam7483f172011-11-08 15:22:26 +05304923 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"),
4924 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004925 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
4926 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
4927 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
4928 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004929 CLK_LOOKUP("iface_clk", pcie_p_clk.c, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07004930 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
4931 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004932 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
4933 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
4934 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
4935 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
4936 CLK_LOOKUP("core_clk", amp_clk.c, ""),
4937 CLK_LOOKUP("cam_clk", cam0_clk.c, ""),
4938 CLK_LOOKUP("cam_clk", cam1_clk.c, ""),
4939 CLK_LOOKUP("cam_clk", cam0_clk.c, ""),
4940 CLK_LOOKUP("cam_clk", cam0_clk.c, ""),
4941 CLK_LOOKUP("cam_clk", cam0_clk.c, ""),
4942 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, ""),
4943 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, ""),
4944 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, ""),
4945 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, ""),
4946 CLK_LOOKUP("csi_clk", csi0_clk.c, ""),
4947 CLK_LOOKUP("csi_clk", csi1_clk.c, ""),
4948 CLK_LOOKUP("csi_clk", csi1_clk.c, ""),
4949 CLK_LOOKUP("csi_clk", csi2_clk.c, ""),
4950 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, ""),
4951 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, ""),
4952 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, ""),
4953 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, ""),
4954 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, ""),
4955 CLK_LOOKUP("csi_pix_clk", csi_pix1_clk.c, ""),
4956 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, ""),
4957 CLK_LOOKUP("csi_rdi_clk", csi_rdi1_clk.c, ""),
4958 CLK_LOOKUP("csi_rdi_clk", csi_rdi2_clk.c, ""),
4959 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, ""),
4960 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, ""),
4961 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, ""),
4962 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, ""),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08004963 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
4964 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
4965 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
4966 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004967 CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, "", OFF),
4968 CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, "", OFF),
Pu Chen86b4be92011-11-03 17:27:57 -07004969 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004970 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
4971 CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004972 CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004973 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
4974 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004975 CLK_LOOKUP("core_clk", vcap_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004976 CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004977 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004978 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004979 CLK_LOOKUP("mem_clk", imem_axi_clk.c, ""),
4980 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004981 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004982 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08004983 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004984 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08004985 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08004986 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08004987 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08004988 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07004989 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004990 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08004991 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
Greg Griscofa47b532011-11-11 10:32:06 -08004992 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004993 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08004994 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
Matt Wagantallb82a5132011-12-12 22:26:41 -08004995 CLK_DUMMY("tv_clk", MDP_TV_CLK, "footswitch-8x60.4", OFF),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004996 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, "", OFF),
4997 CLK_LOOKUP("core_clk", hdmi_app_clk.c, ""),
4998 CLK_LOOKUP("vpe_clk", vpe_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004999 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005000 CLK_LOOKUP("vfe_clk", vfe_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005001 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005002 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005003 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5004 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5005 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5006 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5007 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5008 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5009 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005010 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005011 CLK_LOOKUP("csi_pclk", csi_p_clk.c, ""),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005012 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5013 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5014 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5015 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Pu Chen86b4be92011-11-03 17:27:57 -07005016 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005017 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005018 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, ""),
5019 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, ""),
5020 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005021 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005022 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005023 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005024 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005025 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005026 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005027 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005028 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Greg Griscofa47b532011-11-11 10:32:06 -08005029 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005030 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005031 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005032 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005033 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005034 CLK_LOOKUP("iface_pclk", vpe_p_clk.c, "footswitch-8x60.9"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005035
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005036 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, ""),
5037 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, ""),
5038 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, ""),
5039 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, ""),
5040 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, ""),
5041 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, ""),
5042 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, ""),
5043 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, ""),
5044 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, ""),
5045 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, ""),
5046 CLK_LOOKUP("pcm_clk", pcm_clk.c, ""),
5047 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""),
Tianyi Gou50f23812012-02-06 16:04:19 -08005048 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005049 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""),
5050 CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""),
5051 CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""),
5052 CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""),
5053 CLK_LOOKUP("core_clk", rot_axi_clk.c, ""),
5054 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""),
5055 CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""),
5056 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""),
5057 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""),
5058 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005059
5060 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5061 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5062 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.0"),
5063 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.1"),
5064 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5065 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5066 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5067 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5068 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5069 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5070 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
5071
Manu Gautam5143b252012-01-05 19:25:23 -08005072 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5073 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5074 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5075 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5076 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005077
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005078 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5079 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5080 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5081 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5082 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5083 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5084 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5085 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5086 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5087 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.9"),
5088 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.10"),
5089 CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"),
5090
Jeff Ohlstein8c116c72011-10-27 17:34:48 -07005091 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005092
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005093 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5094 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5095 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
Tianyi Gou455c13c2012-02-02 16:33:24 -08005096 CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""),
5097 CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005098};
5099
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005100static struct clk_lookup msm_clocks_8960[] = {
Stephen Boyd7dd22662012-01-26 16:09:31 -08005101 CLK_LOOKUP("xo", cxo_clk.c, "msm_otg"),
Stephen Boyded630b02012-01-26 15:26:47 -08005102 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5103 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5104 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5105 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5106 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
5107 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5108 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5109 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5110 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005111
Matt Wagantallb2710b82011-11-16 19:55:17 -08005112 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
5113 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
5114 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5115 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5116 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
5117 CLK_LOOKUP("bus_a_clk", sfab_a_clk.c, "msm_sys_fab"),
5118 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5119 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5120 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5121 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5122 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
5123 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
5124
5125 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
5126 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
5127 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
5128 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5129 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5130 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005131
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005132 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5133 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5134 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5135 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5136 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5137 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5138 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
Matt Wagantalle2522372011-08-17 14:52:21 -07005139 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5140 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005141 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
5142 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""),
5143 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
5144 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5145 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5146 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005147 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005148 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005149 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5150 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005151 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5152 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5153 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5154 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
5155 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005156 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005157 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005158 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005159 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005160 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005161 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005162 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5163 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5164 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5165 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5166 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005167 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005168 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5169 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005170 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5171 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005172 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5173 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5174 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5175 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5176 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5177 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005178 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5179 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5180 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5181 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5182 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005183 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005184 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005185 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005186 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005187 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005188 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005189 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005190 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5191 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005192 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5193 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005194 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
5195 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
5196 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005197 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005198 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005199 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005200 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
5201 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5202 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005203 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005204 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5205 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5206 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5207 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5208 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005209 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5210 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005211 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5212 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5213 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5214 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
5215 CLK_LOOKUP("core_clk", amp_clk.c, ""),
Kevin Chan09f4e662011-12-16 08:17:02 -08005216 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
5217 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
5218 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005219 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
Sreesudhan Ramakrish Ramkumar8f11b8b2012-01-04 17:09:05 -08005220 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005221 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5222 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5223 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5224 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5225 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5226 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
Kevin Chane12c6672011-10-26 11:55:26 -07005227 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5228 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005229 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5230 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5231 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5232 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5233 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5234 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5235 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
Kevin Chanf6216f22011-10-25 18:40:11 -07005236 CLK_LOOKUP("csiphy_timer_src_clk",
5237 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5238 CLK_LOOKUP("csiphy_timer_src_clk",
5239 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5240 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5241 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005242 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5243 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5244 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5245 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005246 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005247 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005248 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005249 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005250 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005251 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5252 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Jignesh Mehta95dd6e12011-11-18 17:21:16 -08005253 CLK_LOOKUP("imem_clk", imem_axi_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005254 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005255 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005256 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005257 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005258 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005259 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005260 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005261 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005262 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005263 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005264 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005265 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005266 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005267 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
5268 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005269 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005270 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005271 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005272 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005273 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005274 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Kevin Chana0853122011-11-07 19:48:44 -08005275 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005276 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chan5827c552011-10-28 18:36:32 -07005277 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005278 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chan5827c552011-10-28 18:36:32 -07005279 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005280 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5281 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5282 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5283 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5284 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5285 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5286 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005287 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005288 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5289 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005290 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5291 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5292 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5293 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005294 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005295 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005296 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005297 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005298 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005299 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005300 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5301 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005302 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005303 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005304 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005305 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005306 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005307 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005308 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005309 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005310 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005311 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005312 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005313 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chan5827c552011-10-28 18:36:32 -07005314 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005315 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chana0853122011-11-07 19:48:44 -08005316 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005317 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005318 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
5319 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
5320 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
5321 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
5322 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
5323 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
5324 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
5325 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
5326 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
5327 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
5328 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
5329 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5330 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
Matt Wagantalle604d712011-10-21 15:38:18 -07005331 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5332 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5333 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5334 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5335 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5336 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5337 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5338 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5339 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5340 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
5341 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5342 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005343
5344 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5345 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5346 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5347 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5348 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
5349
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005350 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005351 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005352 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5353 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5354 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5355 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5356 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005357 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005358 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Stephen Boydef5d1c42011-12-15 20:47:14 -08005359 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005360
Matt Wagantalle1a86062011-08-18 17:46:10 -07005361 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005362
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005363 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5364 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5365 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5366 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5367 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5368 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005369};
5370
5371/*
5372 * Miscellaneous clock register initializations
5373 */
5374
5375/* Read, modify, then write-back a register. */
5376static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5377{
5378 uint32_t regval = readl_relaxed(reg);
5379 regval &= ~mask;
5380 regval |= val;
5381 writel_relaxed(regval, reg);
5382}
5383
Tianyi Gou41515e22011-09-01 19:37:43 -07005384static void __init set_fsm_mode(void __iomem *mode_reg)
5385{
5386 u32 regval = readl_relaxed(mode_reg);
5387
5388 /*De-assert reset to FSM */
5389 regval &= ~BIT(21);
5390 writel_relaxed(regval, mode_reg);
5391
5392 /* Program bias count */
Tianyi Gou358c3862011-10-18 17:03:41 -07005393 regval &= ~BM(19, 14);
5394 regval |= BVAL(19, 14, 0x1);
5395 writel_relaxed(regval, mode_reg);
5396
5397 /* Program lock count */
Tianyi Gou41515e22011-09-01 19:37:43 -07005398 regval &= ~BM(13, 8);
5399 regval |= BVAL(13, 8, 0x8);
5400 writel_relaxed(regval, mode_reg);
5401
5402 /*Enable PLL FSM voting */
5403 regval |= BIT(20);
5404 writel_relaxed(regval, mode_reg);
5405}
5406
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005407static void __init reg_init(void)
5408{
Stephen Boydd471e7a2011-11-19 01:37:39 -08005409 void __iomem *imem_reg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005410 /* Deassert MM SW_RESET_ALL signal. */
5411 writel_relaxed(0, SW_RESET_ALL_REG);
5412
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005413 /*
5414 * Some bits are only used on either 8960 or 8064 and are marked as
5415 * reserved bits on the other SoC. Writing to these reserved bits
5416 * should have no effect.
5417 */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005418 /*
5419 * Initialize MM AHB registers: Enable the FPB clock and disable HW
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005420 * gating on non-8960 for all clocks. Also set VFE_AHB's
Stephen Boydd471e7a2011-11-19 01:37:39 -08005421 * FORCE_CORE_ON bit to prevent its memory from being collapsed when
5422 * the clock is halted. The sleep and wake-up delays are set to safe
5423 * values.
5424 */
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005425 if (cpu_is_msm8960()) {
Stephen Boydd471e7a2011-11-19 01:37:39 -08005426 rmwreg(0x44000000, AHB_EN_REG, 0x6C000103);
5427 writel_relaxed(0x3C7097F9, AHB_EN2_REG);
5428 } else {
5429 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
5430 writel_relaxed(0x000007F9, AHB_EN2_REG);
5431 }
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005432 if (cpu_is_apq8064())
5433 rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005434
5435 /* Deassert all locally-owned MM AHB resets. */
5436 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07005437 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005438
5439 /* Initialize MM AXI registers: Enable HW gating for all clocks that
5440 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
5441 * delays to safe values. */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005442 if (cpu_is_msm8960() &&
5443 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) {
5444 rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF);
5445 rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -08005446 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08005447 } else {
5448 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
5449 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
5450 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
5451 }
Matt Wagantall53d968f2011-07-19 13:22:53 -07005452 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005453 if (cpu_is_apq8064())
5454 rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005455 if (cpu_is_msm8960())
Stephen Boydd471e7a2011-11-19 01:37:39 -08005456 rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF);
5457 else
5458 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
5459
5460 /* Enable IMEM's clk_on signal */
5461 imem_reg = ioremap(0x04b00040, 4);
5462 if (imem_reg) {
5463 writel_relaxed(0x3, imem_reg);
5464 iounmap(imem_reg);
5465 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005466
5467 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
5468 * memories retain state even when not clocked. Also, set sleep and
5469 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005470 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
5471 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
5472 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
5473 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
5474 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
5475 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
Tarun Karra6fbc00a2011-12-13 09:23:47 -07005476 rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005477 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
5478 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
5479 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
5480 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
5481 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005482 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
5483 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
5484 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005485 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005486 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005487 if (cpu_is_msm8960() || cpu_is_msm8930()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005488 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
5489 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
5490 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
5491 }
5492 if (cpu_is_apq8064()) {
5493 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07005494 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005495 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005496
Tianyi Gou41515e22011-09-01 19:37:43 -07005497 /*
5498 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
5499 * core remain active during halt state of the clk. Also, set sleep
5500 * and wake-up value to max.
5501 */
5502 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005503 if (cpu_is_apq8064()) {
5504 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
5505 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
5506 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005507
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005508 /* De-assert MM AXI resets to all hardware blocks. */
5509 writel_relaxed(0, SW_RESET_AXI_REG);
5510
5511 /* Deassert all MM core resets. */
5512 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005513 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005514
5515 /* Reset 3D core once more, with its clock enabled. This can
5516 * eventually be done as part of the GDFS footswitch driver. */
5517 clk_set_rate(&gfx3d_clk.c, 27000000);
5518 clk_enable(&gfx3d_clk.c);
5519 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
5520 mb();
5521 udelay(5);
5522 writel_relaxed(0, SW_RESET_CORE_REG);
5523 /* Make sure reset is de-asserted before clock is disabled. */
5524 mb();
5525 clk_disable(&gfx3d_clk.c);
5526
5527 /* Enable TSSC and PDM PXO sources. */
5528 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
5529 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
5530
5531 /* Source SLIMBus xo src from slimbus reference clock */
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005532 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005533 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005534
5535 /* Source the dsi_byte_clks from the DSI PHY PLLs */
5536 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
5537 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07005538
5539 /* Source the sata_phy_ref_clk from PXO */
5540 if (cpu_is_apq8064())
5541 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
5542
5543 /*
Tianyi Gou05e01102012-02-08 22:15:49 -08005544 * TODO: Programming below PLLs and prng_clk is temporary and
5545 * needs to be removed after bootloaders program them.
Tianyi Gou41515e22011-09-01 19:37:43 -07005546 */
5547 if (cpu_is_apq8064()) {
Tianyi Gou317aa862012-02-06 14:31:07 -08005548 u32 is_pll_enabled;
Tianyi Gou41515e22011-09-01 19:37:43 -07005549
5550 /* Program pxo_src_clk to source from PXO */
5551 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
5552
Tianyi Gou41515e22011-09-01 19:37:43 -07005553 /* Check if PLL14 is active */
5554 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
5555 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005556 /* Ref clk = 27MHz and program pll14 to 480MHz */
Tianyi Gou317aa862012-02-06 14:31:07 -08005557 writel_relaxed(0x00031011, BB_PLL14_L_VAL_REG);
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005558 writel_relaxed(0x7, BB_PLL14_M_VAL_REG);
5559 writel_relaxed(0x9, BB_PLL14_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005560
Tianyi Gou317aa862012-02-06 14:31:07 -08005561 /*
5562 * Enable the main output and the MN accumulator
5563 * Set pre-divider and post-divider values to 1 and 1
5564 */
5565 writel_relaxed(0x00C00000, BB_PLL14_CONFIG_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005566
Tianyi Gou41515e22011-09-01 19:37:43 -07005567 set_fsm_mode(BB_PLL14_MODE_REG);
5568 }
Tianyi Gou621f8742011-09-01 21:45:01 -07005569
Tianyi Gou621f8742011-09-01 21:45:01 -07005570 /* Program PLL15 to 975MHz with ref clk = 27MHz */
Tianyi Gou317aa862012-02-06 14:31:07 -08005571 writel_relaxed(0x31024, MM_PLL3_L_VAL_REG);
5572 writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
5573 writel_relaxed(0x9, MM_PLL3_N_VAL_REG);
Tianyi Gou621f8742011-09-01 21:45:01 -07005574
Tianyi Gou317aa862012-02-06 14:31:07 -08005575 writel_relaxed(0xC20000, MM_PLL3_CONFIG_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005576
5577 /* Check if PLL4 is active */
5578 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
5579 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005580 /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
5581 writel_relaxed(0xE, LCC_PLL0_L_VAL_REG);
5582 writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG);
5583 writel_relaxed(0x465, LCC_PLL0_N_VAL_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005584
Tianyi Gou317aa862012-02-06 14:31:07 -08005585 writel_relaxed(0xC00000, LCC_PLL0_CONFIG_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005586
5587 set_fsm_mode(LCC_PLL0_MODE_REG);
5588 }
5589
5590 /* Enable PLL4 source on the LPASS Primary PLL Mux */
5591 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou05e01102012-02-08 22:15:49 -08005592
5593 /* Program prng_clk to 64MHz if it isn't configured */
5594 if (!readl_relaxed(PRNG_CLK_NS_REG))
5595 writel_relaxed(0x2B, PRNG_CLK_NS_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005596 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005597}
5598
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005599/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07005600static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005601{
Tianyi Gou41515e22011-09-01 19:37:43 -07005602
Tianyi Goue1faaf22012-01-24 16:07:19 -08005603 if (cpu_is_msm8960()) {
Tianyi Goubf3d0b12012-01-23 14:37:28 -08005604 rpm_vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3;
Tianyi Goue1faaf22012-01-24 16:07:19 -08005605 } else if (cpu_is_apq8064()) {
5606 rpm_vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3;
5607 rpm_vreg_id_vdd_sr2_pll = RPM_VREG_ID_PM8921_LVS7;
5608 } else if (cpu_is_msm8930() || cpu_is_msm8627()) {
Tianyi Goubf3d0b12012-01-23 14:37:28 -08005609 rpm_vreg_id_vdd_dig = RPM_VREG_ID_PM8038_S1;
Tianyi Goue1faaf22012-01-24 16:07:19 -08005610 rpm_vreg_id_vdd_sr2_pll = RPM_VREG_ID_PM8038_L23;
5611 } else {
Tianyi Goubf3d0b12012-01-23 14:37:28 -08005612 BUG();
Tianyi Goue1faaf22012-01-24 16:07:19 -08005613 }
Tianyi Goubf3d0b12012-01-23 14:37:28 -08005614
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005615 xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960");
5616 if (IS_ERR(xo_pxo)) {
5617 pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
5618 BUG();
5619 }
Matt Wagantalled90b002011-12-12 21:22:43 -08005620 xo_cxo = msm_xo_get(MSM_XO_CXO, "clock-8960");
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005621 if (IS_ERR(xo_cxo)) {
5622 pr_err("%s: msm_xo_get(CXO) failed.\n", __func__);
5623 BUG();
5624 }
5625
Tianyi Gou41515e22011-09-01 19:37:43 -07005626 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005627 * Change the freq tables for and voltage requirements for
5628 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07005629 */
5630 if (cpu_is_apq8064()) {
5631 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005632
5633 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
5634 sizeof(gfx3d_clk.c.fmax));
5635 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
5636 sizeof(ijpeg_clk.c.fmax));
5637 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
5638 sizeof(ijpeg_clk.c.fmax));
5639 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
5640 sizeof(tv_src_clk.c.fmax));
5641 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
5642 sizeof(vfe_clk.c.fmax));
5643
Tianyi Gou621f8742011-09-01 21:45:01 -07005644 gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07005645 }
Stephen Boyd94625ef2011-07-12 17:06:01 -07005646
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005647 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005648
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07005649 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005650
5651 /* Initialize clock registers. */
5652 reg_init();
5653
5654 /* Initialize rates for clocks that only support one. */
5655 clk_set_rate(&pdm_clk.c, 27000000);
5656 clk_set_rate(&prng_clk.c, 64000000);
5657 clk_set_rate(&mdp_vsync_clk.c, 27000000);
5658 clk_set_rate(&tsif_ref_clk.c, 105000);
5659 clk_set_rate(&tssc_clk.c, 27000000);
5660 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07005661 if (cpu_is_apq8064()) {
5662 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
5663 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
5664 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005665 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005666 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou41515e22011-09-01 19:37:43 -07005667 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005668 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
5669 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
5670 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07005671 /*
5672 * Set the CSI rates to a safe default to avoid warnings when
5673 * switching csi pix and rdi clocks.
5674 */
5675 clk_set_rate(&csi0_src_clk.c, 27000000);
5676 clk_set_rate(&csi1_src_clk.c, 27000000);
5677 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005678
5679 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07005680 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005681 * Toggle these clocks on and off to refresh them.
5682 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07005683 rcg_clk_enable(&pdm_clk.c);
5684 rcg_clk_disable(&pdm_clk.c);
5685 rcg_clk_enable(&tssc_clk.c);
5686 rcg_clk_disable(&tssc_clk.c);
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005687 clk_enable(&usb_hsic_hsic_clk.c);
5688 clk_disable(&usb_hsic_hsic_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005689}
5690
Stephen Boydbb600ae2011-08-02 20:11:40 -07005691static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005692{
Stephen Boyda3787f32011-09-16 18:55:13 -07005693 int rc;
5694 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07005695 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07005696
5697 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
5698 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
5699 PTR_ERR(mmfpb_a_clk)))
5700 return PTR_ERR(mmfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08005701 rc = clk_set_rate(mmfpb_a_clk, 76800000);
Stephen Boyda3787f32011-09-16 18:55:13 -07005702 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
5703 return rc;
5704 rc = clk_enable(mmfpb_a_clk);
5705 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
5706 return rc;
5707
Stephen Boyd85436132011-09-16 18:55:13 -07005708 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
5709 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
5710 PTR_ERR(cfpb_a_clk)))
5711 return PTR_ERR(cfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08005712 rc = clk_set_rate(cfpb_a_clk, 64000000);
Stephen Boyd85436132011-09-16 18:55:13 -07005713 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
5714 return rc;
5715 rc = clk_enable(cfpb_a_clk);
5716 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
5717 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005718
5719 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005720}
Stephen Boydbb600ae2011-08-02 20:11:40 -07005721
5722struct clock_init_data msm8960_clock_init_data __initdata = {
5723 .table = msm_clocks_8960,
5724 .size = ARRAY_SIZE(msm_clocks_8960),
5725 .init = msm8960_clock_init,
5726 .late_init = msm8960_clock_late_init,
5727};
Tianyi Gou41515e22011-09-01 19:37:43 -07005728
5729struct clock_init_data apq8064_clock_init_data __initdata = {
5730 .table = msm_clocks_8064,
5731 .size = ARRAY_SIZE(msm_clocks_8064),
5732 .init = msm8960_clock_init,
5733 .late_init = msm8960_clock_late_init,
5734};