Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/ctype.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/spinlock.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/clk.h> |
| 22 | |
| 23 | #include <asm/clkdev.h> |
| 24 | #include <asm/mach-types.h> |
| 25 | |
| 26 | #include <mach/msm_iomap.h> |
| 27 | #include <mach/clk.h> |
| 28 | #include <mach/rpm-regulator.h> |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 29 | #include <mach/socinfo.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 30 | |
| 31 | #include "clock-local.h" |
| 32 | #include "clock-rpm.h" |
| 33 | #include "clock-voter.h" |
| 34 | #include "clock-dss-8960.h" |
| 35 | #include "devices.h" |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 36 | #include "clock-pll.h" |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 37 | |
| 38 | #define REG(off) (MSM_CLK_CTL_BASE + (off)) |
| 39 | #define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off)) |
| 40 | #define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off)) |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 41 | #define REG_GCC(off) (MSM_APCS_GCC_BASE + (off)) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 42 | |
| 43 | /* Peripheral clock registers. */ |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 44 | #define ADM0_PBUS_CLK_CTL_REG REG(0x2208) |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 45 | #define SFAB_SATA_S_HCLK_CTL_REG REG(0x2480) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 46 | #define CE1_HCLK_CTL_REG REG(0x2720) |
| 47 | #define CE1_CORE_CLK_CTL_REG REG(0x2724) |
Tianyi Gou | 05e0110 | 2012-02-08 22:15:49 -0800 | [diff] [blame] | 48 | #define PRNG_CLK_NS_REG REG(0x2E80) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 49 | #define CE3_HCLK_CTL_REG REG(0x36C4) |
| 50 | #define CE3_CORE_CLK_CTL_REG REG(0x36CC) |
| 51 | #define CE3_CLK_SRC_NS_REG REG(0x36C0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 52 | #define DMA_BAM_HCLK_CTL REG(0x25C0) |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 53 | #define CLK_HALT_AFAB_SFAB_STATEA_REG REG(0x2FC0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 54 | #define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 55 | #define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC) |
| 56 | #define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0) |
| 57 | #define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4) |
| 58 | #define CLK_HALT_DFAB_STATE_REG REG(0x2FC8) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 59 | /* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 60 | #define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC) |
| 61 | #define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8) |
Stephen Boyd | 973e4ba | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 62 | #define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 63 | #define CLK_TEST_REG REG(0x2FA0) |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 64 | #define GPn_MD_REG(n) REG(0x2D00+(0x20*(n))) |
| 65 | #define GPn_NS_REG(n) REG(0x2D24+(0x20*(n))) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 66 | #define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) |
| 67 | #define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1))) |
| 68 | #define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1))) |
| 69 | #define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1))) |
| 70 | #define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) |
| 71 | #define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 72 | #define PDM_CLK_NS_REG REG(0x2CC0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 73 | /* 8064 name BB_PLL_ENA_APCS_REG */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 74 | #define BB_PLL_ENA_SC0_REG REG(0x34C0) |
Tianyi Gou | 59608a7 | 2012-01-31 22:19:30 -0800 | [diff] [blame] | 75 | #define BB_PLL_ENA_RPM_REG REG(0x34A0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 76 | #define BB_PLL0_STATUS_REG REG(0x30D8) |
| 77 | #define BB_PLL5_STATUS_REG REG(0x30F8) |
| 78 | #define BB_PLL6_STATUS_REG REG(0x3118) |
| 79 | #define BB_PLL7_STATUS_REG REG(0x3138) |
| 80 | #define BB_PLL8_L_VAL_REG REG(0x3144) |
| 81 | #define BB_PLL8_M_VAL_REG REG(0x3148) |
| 82 | #define BB_PLL8_MODE_REG REG(0x3140) |
| 83 | #define BB_PLL8_N_VAL_REG REG(0x314C) |
| 84 | #define BB_PLL8_STATUS_REG REG(0x3158) |
| 85 | #define BB_PLL8_CONFIG_REG REG(0x3154) |
| 86 | #define BB_PLL8_TEST_CTL_REG REG(0x3150) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 87 | #define BB_MMCC_PLL2_MODE_REG REG(0x3160) |
| 88 | #define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 89 | #define BB_PLL14_MODE_REG REG(0x31C0) |
| 90 | #define BB_PLL14_L_VAL_REG REG(0x31C4) |
| 91 | #define BB_PLL14_M_VAL_REG REG(0x31C8) |
| 92 | #define BB_PLL14_N_VAL_REG REG(0x31CC) |
| 93 | #define BB_PLL14_TEST_CTL_REG REG(0x31D0) |
| 94 | #define BB_PLL14_CONFIG_REG REG(0x31D4) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 95 | #define BB_PLL14_STATUS_REG REG(0x31D8) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 96 | #define PLLTEST_PAD_CFG_REG REG(0x2FA4) |
| 97 | #define PMEM_ACLK_CTL_REG REG(0x25A0) |
| 98 | #define RINGOSC_NS_REG REG(0x2DC0) |
| 99 | #define RINGOSC_STATUS_REG REG(0x2DCC) |
| 100 | #define RINGOSC_TCXO_CTL_REG REG(0x2DC4) |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 101 | #define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 102 | #define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080) |
| 103 | #define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1))) |
| 104 | #define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1))) |
| 105 | #define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1))) |
| 106 | #define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1))) |
| 107 | #define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628) |
| 108 | #define TSIF_HCLK_CTL_REG REG(0x2700) |
| 109 | #define TSIF_REF_CLK_MD_REG REG(0x270C) |
| 110 | #define TSIF_REF_CLK_NS_REG REG(0x2710) |
| 111 | #define TSSC_CLK_CTL_REG REG(0x2CA0) |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 112 | #define SATA_HCLK_CTL_REG REG(0x2C00) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 113 | #define SATA_CLK_SRC_NS_REG REG(0x2C08) |
| 114 | #define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C) |
| 115 | #define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10) |
| 116 | #define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14) |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 117 | #define SATA_ACLK_CTL_REG REG(0x2C20) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 118 | #define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 119 | #define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1))) |
| 120 | #define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1))) |
| 121 | #define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1))) |
| 122 | #define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1))) |
| 123 | #define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1))) |
| 124 | #define USB_HS1_HCLK_CTL_REG REG(0x2900) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 125 | #define USB_HS1_HCLK_FS_REG REG(0x2904) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 126 | #define USB_HS1_RESET_REG REG(0x2910) |
| 127 | #define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908) |
| 128 | #define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 129 | #define USB_HS3_HCLK_CTL_REG REG(0x3700) |
| 130 | #define USB_HS3_HCLK_FS_REG REG(0x3704) |
| 131 | #define USB_HS3_RESET_REG REG(0x3710) |
| 132 | #define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708) |
| 133 | #define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C) |
| 134 | #define USB_HS4_HCLK_CTL_REG REG(0x3720) |
| 135 | #define USB_HS4_HCLK_FS_REG REG(0x3724) |
| 136 | #define USB_HS4_RESET_REG REG(0x3730) |
| 137 | #define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728) |
| 138 | #define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 139 | #define USB_HSIC_HCLK_CTL_REG REG(0x2920) |
| 140 | #define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44) |
| 141 | #define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40) |
| 142 | #define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48) |
| 143 | #define USB_HSIC_RESET_REG REG(0x2934) |
| 144 | #define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C) |
| 145 | #define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924) |
| 146 | #define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 147 | #define USB_PHY0_RESET_REG REG(0x2E20) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 148 | #define PCIE_ALT_REF_CLK_NS_REG REG(0x3860) |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 149 | #define PCIE_ACLK_CTL_REG REG(0x22C0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 150 | #define PCIE_HCLK_CTL_REG REG(0x22CC) |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 151 | #define PCIE_PCLK_CTL_REG REG(0x22D0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 152 | #define GPLL1_MODE_REG REG(0x3160) |
| 153 | #define GPLL1_L_VAL_REG REG(0x3164) |
| 154 | #define GPLL1_M_VAL_REG REG(0x3168) |
| 155 | #define GPLL1_N_VAL_REG REG(0x316C) |
| 156 | #define GPLL1_CONFIG_REG REG(0x3174) |
| 157 | #define GPLL1_STATUS_REG REG(0x3178) |
| 158 | #define PXO_SRC_CLK_CTL_REG REG(0x2EA0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 159 | |
| 160 | /* Multimedia clock registers. */ |
| 161 | #define AHB_EN_REG REG_MM(0x0008) |
| 162 | #define AHB_EN2_REG REG_MM(0x0038) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 163 | #define AHB_EN3_REG REG_MM(0x0248) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 164 | #define AHB_NS_REG REG_MM(0x0004) |
| 165 | #define AXI_NS_REG REG_MM(0x0014) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 166 | #define CAMCLK0_NS_REG REG_MM(0x0148) |
| 167 | #define CAMCLK0_CC_REG REG_MM(0x0140) |
| 168 | #define CAMCLK0_MD_REG REG_MM(0x0144) |
| 169 | #define CAMCLK1_NS_REG REG_MM(0x015C) |
| 170 | #define CAMCLK1_CC_REG REG_MM(0x0154) |
| 171 | #define CAMCLK1_MD_REG REG_MM(0x0158) |
| 172 | #define CAMCLK2_NS_REG REG_MM(0x0228) |
| 173 | #define CAMCLK2_CC_REG REG_MM(0x0220) |
| 174 | #define CAMCLK2_MD_REG REG_MM(0x0224) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 175 | #define CSI0_NS_REG REG_MM(0x0048) |
| 176 | #define CSI0_CC_REG REG_MM(0x0040) |
| 177 | #define CSI0_MD_REG REG_MM(0x0044) |
| 178 | #define CSI1_NS_REG REG_MM(0x0010) |
| 179 | #define CSI1_CC_REG REG_MM(0x0024) |
| 180 | #define CSI1_MD_REG REG_MM(0x0028) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 181 | #define CSI2_NS_REG REG_MM(0x0234) |
| 182 | #define CSI2_CC_REG REG_MM(0x022C) |
| 183 | #define CSI2_MD_REG REG_MM(0x0230) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 184 | #define CSIPHYTIMER_CC_REG REG_MM(0x0160) |
| 185 | #define CSIPHYTIMER_MD_REG REG_MM(0x0164) |
| 186 | #define CSIPHYTIMER_NS_REG REG_MM(0x0168) |
| 187 | #define DSI1_BYTE_NS_REG REG_MM(0x00B0) |
| 188 | #define DSI1_BYTE_CC_REG REG_MM(0x0090) |
| 189 | #define DSI2_BYTE_NS_REG REG_MM(0x00BC) |
| 190 | #define DSI2_BYTE_CC_REG REG_MM(0x00B4) |
| 191 | #define DSI1_ESC_NS_REG REG_MM(0x011C) |
| 192 | #define DSI1_ESC_CC_REG REG_MM(0x00CC) |
| 193 | #define DSI2_ESC_NS_REG REG_MM(0x0150) |
| 194 | #define DSI2_ESC_CC_REG REG_MM(0x013C) |
| 195 | #define DSI_PIXEL_CC_REG REG_MM(0x0130) |
| 196 | #define DSI2_PIXEL_CC_REG REG_MM(0x0094) |
| 197 | #define DBG_BUS_VEC_A_REG REG_MM(0x01C8) |
| 198 | #define DBG_BUS_VEC_B_REG REG_MM(0x01CC) |
| 199 | #define DBG_BUS_VEC_C_REG REG_MM(0x01D0) |
| 200 | #define DBG_BUS_VEC_D_REG REG_MM(0x01D4) |
| 201 | #define DBG_BUS_VEC_E_REG REG_MM(0x01D8) |
| 202 | #define DBG_BUS_VEC_F_REG REG_MM(0x01DC) |
| 203 | #define DBG_BUS_VEC_G_REG REG_MM(0x01E0) |
| 204 | #define DBG_BUS_VEC_H_REG REG_MM(0x01E4) |
| 205 | #define DBG_BUS_VEC_I_REG REG_MM(0x01E8) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 206 | #define DBG_BUS_VEC_J_REG REG_MM(0x0240) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 207 | #define DBG_CFG_REG_HS_REG REG_MM(0x01B4) |
| 208 | #define DBG_CFG_REG_LS_REG REG_MM(0x01B8) |
| 209 | #define GFX2D0_CC_REG REG_MM(0x0060) |
| 210 | #define GFX2D0_MD0_REG REG_MM(0x0064) |
| 211 | #define GFX2D0_MD1_REG REG_MM(0x0068) |
| 212 | #define GFX2D0_NS_REG REG_MM(0x0070) |
| 213 | #define GFX2D1_CC_REG REG_MM(0x0074) |
| 214 | #define GFX2D1_MD0_REG REG_MM(0x0078) |
| 215 | #define GFX2D1_MD1_REG REG_MM(0x006C) |
| 216 | #define GFX2D1_NS_REG REG_MM(0x007C) |
| 217 | #define GFX3D_CC_REG REG_MM(0x0080) |
| 218 | #define GFX3D_MD0_REG REG_MM(0x0084) |
| 219 | #define GFX3D_MD1_REG REG_MM(0x0088) |
| 220 | #define GFX3D_NS_REG REG_MM(0x008C) |
| 221 | #define IJPEG_CC_REG REG_MM(0x0098) |
| 222 | #define IJPEG_MD_REG REG_MM(0x009C) |
| 223 | #define IJPEG_NS_REG REG_MM(0x00A0) |
| 224 | #define JPEGD_CC_REG REG_MM(0x00A4) |
| 225 | #define JPEGD_NS_REG REG_MM(0x00AC) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 226 | #define VCAP_CC_REG REG_MM(0x0178) |
| 227 | #define VCAP_NS_REG REG_MM(0x021C) |
| 228 | #define VCAP_MD0_REG REG_MM(0x01EC) |
| 229 | #define VCAP_MD1_REG REG_MM(0x0218) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 230 | #define MAXI_EN_REG REG_MM(0x0018) |
| 231 | #define MAXI_EN2_REG REG_MM(0x0020) |
| 232 | #define MAXI_EN3_REG REG_MM(0x002C) |
| 233 | #define MAXI_EN4_REG REG_MM(0x0114) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 234 | #define MAXI_EN5_REG REG_MM(0x0244) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 235 | #define MDP_CC_REG REG_MM(0x00C0) |
| 236 | #define MDP_LUT_CC_REG REG_MM(0x016C) |
| 237 | #define MDP_MD0_REG REG_MM(0x00C4) |
| 238 | #define MDP_MD1_REG REG_MM(0x00C8) |
| 239 | #define MDP_NS_REG REG_MM(0x00D0) |
| 240 | #define MISC_CC_REG REG_MM(0x0058) |
| 241 | #define MISC_CC2_REG REG_MM(0x005C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 242 | #define MISC_CC3_REG REG_MM(0x0238) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 243 | #define MM_PLL1_MODE_REG REG_MM(0x031C) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 244 | #define MM_PLL1_L_VAL_REG REG_MM(0x0320) |
| 245 | #define MM_PLL1_M_VAL_REG REG_MM(0x0324) |
| 246 | #define MM_PLL1_N_VAL_REG REG_MM(0x0328) |
| 247 | #define MM_PLL1_CONFIG_REG REG_MM(0x032C) |
| 248 | #define MM_PLL1_TEST_CTL_REG REG_MM(0x0330) |
| 249 | #define MM_PLL1_STATUS_REG REG_MM(0x0334) |
| 250 | #define MM_PLL3_MODE_REG REG_MM(0x0338) |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 251 | #define MM_PLL3_L_VAL_REG REG_MM(0x033C) |
| 252 | #define MM_PLL3_M_VAL_REG REG_MM(0x0340) |
| 253 | #define MM_PLL3_N_VAL_REG REG_MM(0x0344) |
| 254 | #define MM_PLL3_CONFIG_REG REG_MM(0x0348) |
| 255 | #define MM_PLL3_TEST_CTL_REG REG_MM(0x034C) |
| 256 | #define MM_PLL3_STATUS_REG REG_MM(0x0350) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 257 | #define ROT_CC_REG REG_MM(0x00E0) |
| 258 | #define ROT_NS_REG REG_MM(0x00E8) |
| 259 | #define SAXI_EN_REG REG_MM(0x0030) |
| 260 | #define SW_RESET_AHB_REG REG_MM(0x020C) |
| 261 | #define SW_RESET_AHB2_REG REG_MM(0x0200) |
| 262 | #define SW_RESET_ALL_REG REG_MM(0x0204) |
| 263 | #define SW_RESET_AXI_REG REG_MM(0x0208) |
| 264 | #define SW_RESET_CORE_REG REG_MM(0x0210) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 265 | #define SW_RESET_CORE2_REG REG_MM(0x0214) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 266 | #define TV_CC_REG REG_MM(0x00EC) |
| 267 | #define TV_CC2_REG REG_MM(0x0124) |
| 268 | #define TV_MD_REG REG_MM(0x00F0) |
| 269 | #define TV_NS_REG REG_MM(0x00F4) |
| 270 | #define VCODEC_CC_REG REG_MM(0x00F8) |
| 271 | #define VCODEC_MD0_REG REG_MM(0x00FC) |
| 272 | #define VCODEC_MD1_REG REG_MM(0x0128) |
| 273 | #define VCODEC_NS_REG REG_MM(0x0100) |
| 274 | #define VFE_CC_REG REG_MM(0x0104) |
| 275 | #define VFE_MD_REG REG_MM(0x0108) |
| 276 | #define VFE_NS_REG REG_MM(0x010C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 277 | #define VFE_CC2_REG REG_MM(0x023C) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 278 | #define VPE_CC_REG REG_MM(0x0110) |
| 279 | #define VPE_NS_REG REG_MM(0x0118) |
| 280 | |
| 281 | /* Low-power Audio clock registers. */ |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 282 | #define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 283 | #define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8) |
| 284 | #define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064) |
| 285 | #define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060) |
| 286 | #define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068) |
| 287 | #define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070) |
| 288 | #define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C) |
| 289 | #define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074) |
| 290 | #define LCC_MI2S_MD_REG REG_LPA(0x004C) |
| 291 | #define LCC_MI2S_NS_REG REG_LPA(0x0048) |
| 292 | #define LCC_MI2S_STATUS_REG REG_LPA(0x0050) |
| 293 | #define LCC_PCM_MD_REG REG_LPA(0x0058) |
| 294 | #define LCC_PCM_NS_REG REG_LPA(0x0054) |
| 295 | #define LCC_PCM_STATUS_REG REG_LPA(0x005C) |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 296 | #define LCC_PLL0_MODE_REG REG_LPA(0x0000) |
| 297 | #define LCC_PLL0_L_VAL_REG REG_LPA(0x0004) |
| 298 | #define LCC_PLL0_M_VAL_REG REG_LPA(0x0008) |
| 299 | #define LCC_PLL0_N_VAL_REG REG_LPA(0x000C) |
| 300 | #define LCC_PLL0_CONFIG_REG REG_LPA(0x0014) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 301 | #define LCC_PLL0_STATUS_REG REG_LPA(0x0018) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 302 | #define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C) |
| 303 | #define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078) |
| 304 | #define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080) |
| 305 | #define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088) |
| 306 | #define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084) |
| 307 | #define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C) |
| 308 | #define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC) |
| 309 | #define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0) |
| 310 | #define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4) |
| 311 | #define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4) |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 312 | #define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 313 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 314 | #define GCC_APCS_CLK_DIAG REG_GCC(0x001C) |
| 315 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 316 | /* MUX source input identifiers. */ |
| 317 | #define pxo_to_bb_mux 0 |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 318 | #define cxo_to_bb_mux 5 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 319 | #define pll0_to_bb_mux 2 |
| 320 | #define pll8_to_bb_mux 3 |
| 321 | #define pll6_to_bb_mux 4 |
| 322 | #define gnd_to_bb_mux 5 |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 323 | #define pll3_to_bb_mux 6 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 324 | #define pxo_to_mm_mux 0 |
| 325 | #define pll1_to_mm_mux 1 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 326 | #define pll2_to_mm_mux 1 /* or MMCC_PLL1 */ |
| 327 | #define pll8_to_mm_mux 2 /* or GCC_PERF */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 328 | #define pll0_to_mm_mux 3 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 329 | #define pll15_to_mm_mux 3 /* or MM_PLL3 */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 330 | #define gnd_to_mm_mux 4 |
Stephen Boyd | 7a776cd | 2011-10-20 12:46:04 -0700 | [diff] [blame] | 331 | #define pll3_to_mm_mux 3 /* or MMCC_PLL2 */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 332 | #define hdmi_pll_to_mm_mux 3 |
| 333 | #define cxo_to_xo_mux 0 |
| 334 | #define pxo_to_xo_mux 1 |
| 335 | #define gnd_to_xo_mux 3 |
| 336 | #define pxo_to_lpa_mux 0 |
| 337 | #define cxo_to_lpa_mux 1 |
| 338 | #define pll4_to_lpa_mux 2 |
| 339 | #define gnd_to_lpa_mux 6 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 340 | #define pxo_to_pcie_mux 0 |
| 341 | #define pll3_to_pcie_mux 1 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 342 | |
| 343 | /* Test Vector Macros */ |
| 344 | #define TEST_TYPE_PER_LS 1 |
| 345 | #define TEST_TYPE_PER_HS 2 |
| 346 | #define TEST_TYPE_MM_LS 3 |
| 347 | #define TEST_TYPE_MM_HS 4 |
| 348 | #define TEST_TYPE_LPA 5 |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 349 | #define TEST_TYPE_CPUL2 6 |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 350 | #define TEST_TYPE_LPA_HS 7 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 351 | #define TEST_TYPE_SHIFT 24 |
| 352 | #define TEST_CLK_SEL_MASK BM(23, 0) |
| 353 | #define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s))) |
| 354 | #define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS) |
| 355 | #define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS) |
| 356 | #define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS) |
| 357 | #define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS) |
| 358 | #define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA) |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 359 | #define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS) |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 360 | #define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 361 | |
| 362 | #define MN_MODE_DUAL_EDGE 0x2 |
| 363 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 364 | struct pll_rate { |
| 365 | const uint32_t l_val; |
| 366 | const uint32_t m_val; |
| 367 | const uint32_t n_val; |
| 368 | const uint32_t vco; |
| 369 | const uint32_t post_div; |
| 370 | const uint32_t i_bits; |
| 371 | }; |
| 372 | #define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i } |
| 373 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 374 | enum vdd_dig_levels { |
| 375 | VDD_DIG_NONE, |
| 376 | VDD_DIG_LOW, |
| 377 | VDD_DIG_NOMINAL, |
| 378 | VDD_DIG_HIGH |
| 379 | }; |
| 380 | |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 381 | static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level) |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 382 | { |
| 383 | static const int vdd_uv[] = { |
| 384 | [VDD_DIG_NONE] = 0, |
| 385 | [VDD_DIG_LOW] = 945000, |
| 386 | [VDD_DIG_NOMINAL] = 1050000, |
| 387 | [VDD_DIG_HIGH] = 1150000 |
| 388 | }; |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 389 | return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 390 | vdd_uv[level], 1150000, 1); |
| 391 | } |
| 392 | |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 393 | static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig_8960); |
| 394 | |
| 395 | static int set_vdd_dig_8930(struct clk_vdd_class *vdd_class, int level) |
| 396 | { |
Saravana Kannan | ebaa3ac | 2012-02-08 19:55:44 -0800 | [diff] [blame] | 397 | static const int vdd_corner[] = { |
| 398 | [VDD_DIG_NONE] = RPM_VREG_CORNER_NONE, |
| 399 | [VDD_DIG_LOW] = RPM_VREG_CORNER_LOW, |
| 400 | [VDD_DIG_NOMINAL] = RPM_VREG_CORNER_NOMINAL, |
| 401 | [VDD_DIG_HIGH] = RPM_VREG_CORNER_HIGH, |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 402 | }; |
Saravana Kannan | ebaa3ac | 2012-02-08 19:55:44 -0800 | [diff] [blame] | 403 | return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_VDD_DIG_CORNER, |
| 404 | RPM_VREG_VOTER3, |
| 405 | vdd_corner[level], |
| 406 | RPM_VREG_CORNER_HIGH, 1); |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 407 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 408 | |
| 409 | #define VDD_DIG_FMAX_MAP1(l1, f1) \ |
| 410 | .vdd_class = &vdd_dig, \ |
| 411 | .fmax[VDD_DIG_##l1] = (f1) |
| 412 | #define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ |
| 413 | .vdd_class = &vdd_dig, \ |
| 414 | .fmax[VDD_DIG_##l1] = (f1), \ |
| 415 | .fmax[VDD_DIG_##l2] = (f2) |
| 416 | #define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ |
| 417 | .vdd_class = &vdd_dig, \ |
| 418 | .fmax[VDD_DIG_##l1] = (f1), \ |
| 419 | .fmax[VDD_DIG_##l2] = (f2), \ |
| 420 | .fmax[VDD_DIG_##l3] = (f3) |
| 421 | |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 422 | enum vdd_sr2_pll_levels { |
| 423 | VDD_SR2_PLL_OFF, |
| 424 | VDD_SR2_PLL_ON |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 425 | }; |
| 426 | |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 427 | static int set_vdd_sr2_pll_8960(struct clk_vdd_class *vdd_class, int level) |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 428 | { |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 429 | int rc = 0; |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 430 | |
| 431 | if (level == VDD_SR2_PLL_OFF) { |
| 432 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 433 | RPM_VREG_VOTER3, 0, 0, 1); |
| 434 | if (rc) |
| 435 | return rc; |
| 436 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
| 437 | RPM_VREG_VOTER3, 0, 0, 1); |
| 438 | if (rc) |
| 439 | rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 440 | RPM_VREG_VOTER3, 1800000, 1800000, 1); |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 441 | } else { |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 442 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
David Collins | 9a81d6c | 2012-03-29 15:11:33 -0700 | [diff] [blame] | 443 | RPM_VREG_VOTER3, 2050000, 2100000, 1); |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 444 | if (rc) |
| 445 | return rc; |
| 446 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 447 | RPM_VREG_VOTER3, 1800000, 1800000, 1); |
| 448 | if (rc) |
| 449 | rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 450 | RPM_VREG_VOTER3, 0, 0, 1); |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 451 | } |
| 452 | |
| 453 | return rc; |
| 454 | } |
| 455 | |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 456 | static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll_8960); |
| 457 | |
| 458 | static int sr2_lreg_uv[] = { |
| 459 | [VDD_SR2_PLL_OFF] = 0, |
| 460 | [VDD_SR2_PLL_ON] = 1800000, |
| 461 | }; |
| 462 | |
| 463 | static int set_vdd_sr2_pll_8064(struct clk_vdd_class *vdd_class, int level) |
| 464 | { |
| 465 | return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_LVS7, RPM_VREG_VOTER3, |
| 466 | sr2_lreg_uv[level], sr2_lreg_uv[level], 1); |
| 467 | } |
| 468 | |
| 469 | static int set_vdd_sr2_pll_8930(struct clk_vdd_class *vdd_class, int level) |
| 470 | { |
| 471 | return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23, RPM_VREG_VOTER3, |
| 472 | sr2_lreg_uv[level], sr2_lreg_uv[level], 1); |
| 473 | } |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 474 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 475 | /* |
| 476 | * Clock Descriptions |
| 477 | */ |
| 478 | |
Stephen Boyd | 72a8035 | 2012-01-26 15:57:38 -0800 | [diff] [blame] | 479 | DEFINE_CLK_RPM_BRANCH(pxo_clk, pxo_a_clk, PXO, 27000000); |
| 480 | DEFINE_CLK_RPM_BRANCH(cxo_clk, cxo_a_clk, CXO, 19200000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 481 | |
| 482 | static struct pll_clk pll2_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 483 | .mode_reg = MM_PLL1_MODE_REG, |
| 484 | .parent = &pxo_clk.c, |
| 485 | .c = { |
| 486 | .dbg_name = "pll2_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 487 | .rate = 800000000, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 488 | .ops = &clk_ops_local_pll, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 489 | CLK_INIT(pll2_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 490 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 491 | }, |
| 492 | }; |
| 493 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 494 | static struct pll_clk pll3_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 495 | .mode_reg = BB_MMCC_PLL2_MODE_REG, |
| 496 | .parent = &pxo_clk.c, |
| 497 | .c = { |
| 498 | .dbg_name = "pll3_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 499 | .rate = 1200000000, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 500 | .ops = &clk_ops_local_pll, |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 501 | .vdd_class = &vdd_sr2_pll, |
| 502 | .fmax[VDD_SR2_PLL_ON] = ULONG_MAX, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 503 | CLK_INIT(pll3_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 504 | .warned = true, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 505 | }, |
| 506 | }; |
| 507 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 508 | static struct pll_vote_clk pll4_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 509 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 510 | .en_mask = BIT(4), |
| 511 | .status_reg = LCC_PLL0_STATUS_REG, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 512 | .status_mask = BIT(16), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 513 | .parent = &pxo_clk.c, |
| 514 | .c = { |
| 515 | .dbg_name = "pll4_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 516 | .rate = 393216000, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 517 | .ops = &clk_ops_pll_vote, |
| 518 | CLK_INIT(pll4_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 519 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 520 | }, |
| 521 | }; |
| 522 | |
| 523 | static struct pll_vote_clk pll8_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 524 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 525 | .en_mask = BIT(8), |
| 526 | .status_reg = BB_PLL8_STATUS_REG, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 527 | .status_mask = BIT(16), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 528 | .parent = &pxo_clk.c, |
| 529 | .c = { |
| 530 | .dbg_name = "pll8_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 531 | .rate = 384000000, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 532 | .ops = &clk_ops_pll_vote, |
| 533 | CLK_INIT(pll8_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 534 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 535 | }, |
| 536 | }; |
| 537 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 538 | static struct pll_vote_clk pll14_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 539 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 540 | .en_mask = BIT(14), |
| 541 | .status_reg = BB_PLL14_STATUS_REG, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 542 | .status_mask = BIT(16), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 543 | .parent = &pxo_clk.c, |
| 544 | .c = { |
| 545 | .dbg_name = "pll14_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 546 | .rate = 480000000, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 547 | .ops = &clk_ops_pll_vote, |
| 548 | CLK_INIT(pll14_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 549 | .warned = true, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 550 | }, |
| 551 | }; |
| 552 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 553 | static struct pll_clk pll15_clk = { |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 554 | .mode_reg = MM_PLL3_MODE_REG, |
| 555 | .parent = &pxo_clk.c, |
| 556 | .c = { |
| 557 | .dbg_name = "pll15_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 558 | .rate = 975000000, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 559 | .ops = &clk_ops_local_pll, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 560 | CLK_INIT(pll15_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 561 | .warned = true, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 562 | }, |
| 563 | }; |
| 564 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 565 | /* AXI Interfaces */ |
| 566 | static struct branch_clk gmem_axi_clk = { |
| 567 | .b = { |
| 568 | .ctl_reg = MAXI_EN_REG, |
| 569 | .en_mask = BIT(24), |
| 570 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 571 | .halt_bit = 6, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 572 | .retain_reg = MAXI_EN2_REG, |
| 573 | .retain_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 574 | }, |
| 575 | .c = { |
| 576 | .dbg_name = "gmem_axi_clk", |
| 577 | .ops = &clk_ops_branch, |
| 578 | CLK_INIT(gmem_axi_clk.c), |
| 579 | }, |
| 580 | }; |
| 581 | |
| 582 | static struct branch_clk ijpeg_axi_clk = { |
| 583 | .b = { |
| 584 | .ctl_reg = MAXI_EN_REG, |
| 585 | .en_mask = BIT(21), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 586 | .hwcg_reg = MAXI_EN_REG, |
| 587 | .hwcg_mask = BIT(11), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 588 | .reset_reg = SW_RESET_AXI_REG, |
| 589 | .reset_mask = BIT(14), |
| 590 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 591 | .halt_bit = 4, |
| 592 | }, |
| 593 | .c = { |
| 594 | .dbg_name = "ijpeg_axi_clk", |
| 595 | .ops = &clk_ops_branch, |
| 596 | CLK_INIT(ijpeg_axi_clk.c), |
| 597 | }, |
| 598 | }; |
| 599 | |
| 600 | static struct branch_clk imem_axi_clk = { |
| 601 | .b = { |
| 602 | .ctl_reg = MAXI_EN_REG, |
| 603 | .en_mask = BIT(22), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 604 | .hwcg_reg = MAXI_EN_REG, |
| 605 | .hwcg_mask = BIT(15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 606 | .reset_reg = SW_RESET_CORE_REG, |
| 607 | .reset_mask = BIT(10), |
| 608 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 609 | .halt_bit = 7, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 610 | .retain_reg = MAXI_EN2_REG, |
| 611 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 612 | }, |
| 613 | .c = { |
| 614 | .dbg_name = "imem_axi_clk", |
| 615 | .ops = &clk_ops_branch, |
| 616 | CLK_INIT(imem_axi_clk.c), |
| 617 | }, |
| 618 | }; |
| 619 | |
| 620 | static struct branch_clk jpegd_axi_clk = { |
| 621 | .b = { |
| 622 | .ctl_reg = MAXI_EN_REG, |
| 623 | .en_mask = BIT(25), |
| 624 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 625 | .halt_bit = 5, |
| 626 | }, |
| 627 | .c = { |
| 628 | .dbg_name = "jpegd_axi_clk", |
| 629 | .ops = &clk_ops_branch, |
| 630 | CLK_INIT(jpegd_axi_clk.c), |
| 631 | }, |
| 632 | }; |
| 633 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 634 | static struct branch_clk vcodec_axi_b_clk = { |
| 635 | .b = { |
| 636 | .ctl_reg = MAXI_EN4_REG, |
| 637 | .en_mask = BIT(23), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 638 | .hwcg_reg = MAXI_EN4_REG, |
| 639 | .hwcg_mask = BIT(22), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 640 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 641 | .halt_bit = 25, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 642 | .retain_reg = MAXI_EN4_REG, |
| 643 | .retain_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 644 | }, |
| 645 | .c = { |
| 646 | .dbg_name = "vcodec_axi_b_clk", |
| 647 | .ops = &clk_ops_branch, |
| 648 | CLK_INIT(vcodec_axi_b_clk.c), |
| 649 | }, |
| 650 | }; |
| 651 | |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 652 | static struct branch_clk vcodec_axi_a_clk = { |
| 653 | .b = { |
| 654 | .ctl_reg = MAXI_EN4_REG, |
| 655 | .en_mask = BIT(25), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 656 | .hwcg_reg = MAXI_EN4_REG, |
| 657 | .hwcg_mask = BIT(24), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 658 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 659 | .halt_bit = 26, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 660 | .retain_reg = MAXI_EN4_REG, |
| 661 | .retain_mask = BIT(10), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 662 | }, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 663 | .c = { |
| 664 | .dbg_name = "vcodec_axi_a_clk", |
| 665 | .ops = &clk_ops_branch, |
| 666 | CLK_INIT(vcodec_axi_a_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 667 | .depends = &vcodec_axi_b_clk.c, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 668 | }, |
| 669 | }; |
| 670 | |
| 671 | static struct branch_clk vcodec_axi_clk = { |
| 672 | .b = { |
| 673 | .ctl_reg = MAXI_EN_REG, |
| 674 | .en_mask = BIT(19), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 675 | .hwcg_reg = MAXI_EN_REG, |
| 676 | .hwcg_mask = BIT(13), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 677 | .reset_reg = SW_RESET_AXI_REG, |
Gopikrishnaiah Anandan | 83b6e85 | 2012-01-05 17:47:02 -0800 | [diff] [blame] | 678 | .reset_mask = BIT(4)|BIT(5)|BIT(7), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 679 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 680 | .halt_bit = 3, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 681 | .retain_reg = MAXI_EN2_REG, |
| 682 | .retain_mask = BIT(28), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 683 | }, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 684 | .c = { |
| 685 | .dbg_name = "vcodec_axi_clk", |
| 686 | .ops = &clk_ops_branch, |
| 687 | CLK_INIT(vcodec_axi_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 688 | .depends = &vcodec_axi_a_clk.c, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 689 | }, |
| 690 | }; |
| 691 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 692 | static struct branch_clk vfe_axi_clk = { |
| 693 | .b = { |
| 694 | .ctl_reg = MAXI_EN_REG, |
| 695 | .en_mask = BIT(18), |
| 696 | .reset_reg = SW_RESET_AXI_REG, |
| 697 | .reset_mask = BIT(9), |
| 698 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 699 | .halt_bit = 0, |
| 700 | }, |
| 701 | .c = { |
| 702 | .dbg_name = "vfe_axi_clk", |
| 703 | .ops = &clk_ops_branch, |
| 704 | CLK_INIT(vfe_axi_clk.c), |
| 705 | }, |
| 706 | }; |
| 707 | |
| 708 | static struct branch_clk mdp_axi_clk = { |
| 709 | .b = { |
| 710 | .ctl_reg = MAXI_EN_REG, |
| 711 | .en_mask = BIT(23), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 712 | .hwcg_reg = MAXI_EN_REG, |
| 713 | .hwcg_mask = BIT(16), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 714 | .reset_reg = SW_RESET_AXI_REG, |
| 715 | .reset_mask = BIT(13), |
| 716 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 717 | .halt_bit = 8, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 718 | .retain_reg = MAXI_EN_REG, |
| 719 | .retain_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 720 | }, |
| 721 | .c = { |
| 722 | .dbg_name = "mdp_axi_clk", |
| 723 | .ops = &clk_ops_branch, |
| 724 | CLK_INIT(mdp_axi_clk.c), |
| 725 | }, |
| 726 | }; |
| 727 | |
| 728 | static struct branch_clk rot_axi_clk = { |
| 729 | .b = { |
| 730 | .ctl_reg = MAXI_EN2_REG, |
| 731 | .en_mask = BIT(24), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 732 | .hwcg_reg = MAXI_EN2_REG, |
| 733 | .hwcg_mask = BIT(25), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 734 | .reset_reg = SW_RESET_AXI_REG, |
| 735 | .reset_mask = BIT(6), |
| 736 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 737 | .halt_bit = 2, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 738 | .retain_reg = MAXI_EN3_REG, |
| 739 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 740 | }, |
| 741 | .c = { |
| 742 | .dbg_name = "rot_axi_clk", |
| 743 | .ops = &clk_ops_branch, |
| 744 | CLK_INIT(rot_axi_clk.c), |
| 745 | }, |
| 746 | }; |
| 747 | |
| 748 | static struct branch_clk vpe_axi_clk = { |
| 749 | .b = { |
| 750 | .ctl_reg = MAXI_EN2_REG, |
| 751 | .en_mask = BIT(26), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 752 | .hwcg_reg = MAXI_EN2_REG, |
| 753 | .hwcg_mask = BIT(27), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 754 | .reset_reg = SW_RESET_AXI_REG, |
| 755 | .reset_mask = BIT(15), |
| 756 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 757 | .halt_bit = 1, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 758 | .retain_reg = MAXI_EN3_REG, |
| 759 | .retain_mask = BIT(21), |
| 760 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 761 | }, |
| 762 | .c = { |
| 763 | .dbg_name = "vpe_axi_clk", |
| 764 | .ops = &clk_ops_branch, |
| 765 | CLK_INIT(vpe_axi_clk.c), |
| 766 | }, |
| 767 | }; |
| 768 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 769 | static struct branch_clk vcap_axi_clk = { |
| 770 | .b = { |
| 771 | .ctl_reg = MAXI_EN5_REG, |
| 772 | .en_mask = BIT(12), |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 773 | .hwcg_reg = MAXI_EN5_REG, |
| 774 | .hwcg_mask = BIT(11), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 775 | .reset_reg = SW_RESET_AXI_REG, |
| 776 | .reset_mask = BIT(16), |
| 777 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 778 | .halt_bit = 20, |
| 779 | }, |
| 780 | .c = { |
| 781 | .dbg_name = "vcap_axi_clk", |
| 782 | .ops = &clk_ops_branch, |
| 783 | CLK_INIT(vcap_axi_clk.c), |
| 784 | }, |
| 785 | }; |
| 786 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 787 | /* gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */ |
| 788 | static struct branch_clk gfx3d_axi_clk_8064 = { |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 789 | .b = { |
| 790 | .ctl_reg = MAXI_EN5_REG, |
| 791 | .en_mask = BIT(25), |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 792 | .hwcg_reg = MAXI_EN5_REG, |
| 793 | .hwcg_mask = BIT(24), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 794 | .reset_reg = SW_RESET_AXI_REG, |
| 795 | .reset_mask = BIT(17), |
| 796 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 797 | .halt_bit = 30, |
| 798 | }, |
| 799 | .c = { |
| 800 | .dbg_name = "gfx3d_axi_clk", |
| 801 | .ops = &clk_ops_branch, |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 802 | CLK_INIT(gfx3d_axi_clk_8064.c), |
| 803 | }, |
| 804 | }; |
| 805 | |
| 806 | static struct branch_clk gfx3d_axi_clk_8930 = { |
| 807 | .b = { |
| 808 | .ctl_reg = MAXI_EN5_REG, |
| 809 | .en_mask = BIT(12), |
| 810 | .reset_reg = SW_RESET_AXI_REG, |
| 811 | .reset_mask = BIT(16), |
| 812 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 813 | .halt_bit = 12, |
| 814 | }, |
| 815 | .c = { |
| 816 | .dbg_name = "gfx3d_axi_clk", |
| 817 | .ops = &clk_ops_branch, |
| 818 | CLK_INIT(gfx3d_axi_clk_8930.c), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 819 | }, |
| 820 | }; |
| 821 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 822 | /* AHB Interfaces */ |
| 823 | static struct branch_clk amp_p_clk = { |
| 824 | .b = { |
| 825 | .ctl_reg = AHB_EN_REG, |
| 826 | .en_mask = BIT(24), |
Matt Wagantall | d40857a | 2012-04-10 19:15:43 -0700 | [diff] [blame] | 827 | .reset_reg = SW_RESET_CORE_REG, |
| 828 | .reset_mask = BIT(20), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 829 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 830 | .halt_bit = 18, |
| 831 | }, |
| 832 | .c = { |
| 833 | .dbg_name = "amp_p_clk", |
| 834 | .ops = &clk_ops_branch, |
| 835 | CLK_INIT(amp_p_clk.c), |
| 836 | }, |
| 837 | }; |
| 838 | |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 839 | static struct branch_clk csi_p_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 840 | .b = { |
| 841 | .ctl_reg = AHB_EN_REG, |
| 842 | .en_mask = BIT(7), |
| 843 | .reset_reg = SW_RESET_AHB_REG, |
| 844 | .reset_mask = BIT(17), |
| 845 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 846 | .halt_bit = 16, |
| 847 | }, |
| 848 | .c = { |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 849 | .dbg_name = "csi_p_clk", |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 850 | .ops = &clk_ops_branch, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 851 | CLK_INIT(csi_p_clk.c), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 852 | }, |
| 853 | }; |
| 854 | |
| 855 | static struct branch_clk dsi1_m_p_clk = { |
| 856 | .b = { |
| 857 | .ctl_reg = AHB_EN_REG, |
| 858 | .en_mask = BIT(9), |
| 859 | .reset_reg = SW_RESET_AHB_REG, |
| 860 | .reset_mask = BIT(6), |
| 861 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 862 | .halt_bit = 19, |
| 863 | }, |
| 864 | .c = { |
| 865 | .dbg_name = "dsi1_m_p_clk", |
| 866 | .ops = &clk_ops_branch, |
| 867 | CLK_INIT(dsi1_m_p_clk.c), |
| 868 | }, |
| 869 | }; |
| 870 | |
| 871 | static struct branch_clk dsi1_s_p_clk = { |
| 872 | .b = { |
| 873 | .ctl_reg = AHB_EN_REG, |
| 874 | .en_mask = BIT(18), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 875 | .hwcg_reg = AHB_EN2_REG, |
| 876 | .hwcg_mask = BIT(20), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 877 | .reset_reg = SW_RESET_AHB_REG, |
| 878 | .reset_mask = BIT(5), |
| 879 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 880 | .halt_bit = 21, |
| 881 | }, |
| 882 | .c = { |
| 883 | .dbg_name = "dsi1_s_p_clk", |
| 884 | .ops = &clk_ops_branch, |
| 885 | CLK_INIT(dsi1_s_p_clk.c), |
| 886 | }, |
| 887 | }; |
| 888 | |
| 889 | static struct branch_clk dsi2_m_p_clk = { |
| 890 | .b = { |
| 891 | .ctl_reg = AHB_EN_REG, |
| 892 | .en_mask = BIT(17), |
| 893 | .reset_reg = SW_RESET_AHB2_REG, |
| 894 | .reset_mask = BIT(1), |
| 895 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 896 | .halt_bit = 18, |
| 897 | }, |
| 898 | .c = { |
| 899 | .dbg_name = "dsi2_m_p_clk", |
| 900 | .ops = &clk_ops_branch, |
| 901 | CLK_INIT(dsi2_m_p_clk.c), |
| 902 | }, |
| 903 | }; |
| 904 | |
| 905 | static struct branch_clk dsi2_s_p_clk = { |
| 906 | .b = { |
| 907 | .ctl_reg = AHB_EN_REG, |
| 908 | .en_mask = BIT(22), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 909 | .hwcg_reg = AHB_EN2_REG, |
| 910 | .hwcg_mask = BIT(15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 911 | .reset_reg = SW_RESET_AHB2_REG, |
| 912 | .reset_mask = BIT(0), |
| 913 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 914 | .halt_bit = 20, |
| 915 | }, |
| 916 | .c = { |
| 917 | .dbg_name = "dsi2_s_p_clk", |
| 918 | .ops = &clk_ops_branch, |
| 919 | CLK_INIT(dsi2_s_p_clk.c), |
| 920 | }, |
| 921 | }; |
| 922 | |
| 923 | static struct branch_clk gfx2d0_p_clk = { |
| 924 | .b = { |
| 925 | .ctl_reg = AHB_EN_REG, |
| 926 | .en_mask = BIT(19), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 927 | .hwcg_reg = AHB_EN2_REG, |
| 928 | .hwcg_mask = BIT(28), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 929 | .reset_reg = SW_RESET_AHB_REG, |
| 930 | .reset_mask = BIT(12), |
| 931 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 932 | .halt_bit = 2, |
| 933 | }, |
| 934 | .c = { |
| 935 | .dbg_name = "gfx2d0_p_clk", |
| 936 | .ops = &clk_ops_branch, |
Matt Wagantall | 158f73b | 2012-05-16 11:29:35 -0700 | [diff] [blame] | 937 | .flags = CLKFLAG_SKIP_HANDOFF, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 938 | CLK_INIT(gfx2d0_p_clk.c), |
| 939 | }, |
| 940 | }; |
| 941 | |
| 942 | static struct branch_clk gfx2d1_p_clk = { |
| 943 | .b = { |
| 944 | .ctl_reg = AHB_EN_REG, |
| 945 | .en_mask = BIT(2), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 946 | .hwcg_reg = AHB_EN2_REG, |
| 947 | .hwcg_mask = BIT(29), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 948 | .reset_reg = SW_RESET_AHB_REG, |
| 949 | .reset_mask = BIT(11), |
| 950 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 951 | .halt_bit = 3, |
| 952 | }, |
| 953 | .c = { |
| 954 | .dbg_name = "gfx2d1_p_clk", |
| 955 | .ops = &clk_ops_branch, |
Matt Wagantall | 158f73b | 2012-05-16 11:29:35 -0700 | [diff] [blame] | 956 | .flags = CLKFLAG_SKIP_HANDOFF, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 957 | CLK_INIT(gfx2d1_p_clk.c), |
| 958 | }, |
| 959 | }; |
| 960 | |
| 961 | static struct branch_clk gfx3d_p_clk = { |
| 962 | .b = { |
| 963 | .ctl_reg = AHB_EN_REG, |
| 964 | .en_mask = BIT(3), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 965 | .hwcg_reg = AHB_EN2_REG, |
| 966 | .hwcg_mask = BIT(27), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 967 | .reset_reg = SW_RESET_AHB_REG, |
| 968 | .reset_mask = BIT(10), |
| 969 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 970 | .halt_bit = 4, |
| 971 | }, |
| 972 | .c = { |
| 973 | .dbg_name = "gfx3d_p_clk", |
| 974 | .ops = &clk_ops_branch, |
| 975 | CLK_INIT(gfx3d_p_clk.c), |
| 976 | }, |
| 977 | }; |
| 978 | |
| 979 | static struct branch_clk hdmi_m_p_clk = { |
| 980 | .b = { |
| 981 | .ctl_reg = AHB_EN_REG, |
| 982 | .en_mask = BIT(14), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 983 | .hwcg_reg = AHB_EN2_REG, |
| 984 | .hwcg_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 985 | .reset_reg = SW_RESET_AHB_REG, |
| 986 | .reset_mask = BIT(9), |
| 987 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 988 | .halt_bit = 5, |
| 989 | }, |
| 990 | .c = { |
| 991 | .dbg_name = "hdmi_m_p_clk", |
| 992 | .ops = &clk_ops_branch, |
| 993 | CLK_INIT(hdmi_m_p_clk.c), |
| 994 | }, |
| 995 | }; |
| 996 | |
| 997 | static struct branch_clk hdmi_s_p_clk = { |
| 998 | .b = { |
| 999 | .ctl_reg = AHB_EN_REG, |
| 1000 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1001 | .hwcg_reg = AHB_EN2_REG, |
| 1002 | .hwcg_mask = BIT(22), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1003 | .reset_reg = SW_RESET_AHB_REG, |
| 1004 | .reset_mask = BIT(9), |
| 1005 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1006 | .halt_bit = 6, |
| 1007 | }, |
| 1008 | .c = { |
| 1009 | .dbg_name = "hdmi_s_p_clk", |
| 1010 | .ops = &clk_ops_branch, |
| 1011 | CLK_INIT(hdmi_s_p_clk.c), |
| 1012 | }, |
| 1013 | }; |
| 1014 | |
| 1015 | static struct branch_clk ijpeg_p_clk = { |
| 1016 | .b = { |
| 1017 | .ctl_reg = AHB_EN_REG, |
| 1018 | .en_mask = BIT(5), |
| 1019 | .reset_reg = SW_RESET_AHB_REG, |
| 1020 | .reset_mask = BIT(7), |
| 1021 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1022 | .halt_bit = 9, |
| 1023 | }, |
| 1024 | .c = { |
| 1025 | .dbg_name = "ijpeg_p_clk", |
| 1026 | .ops = &clk_ops_branch, |
| 1027 | CLK_INIT(ijpeg_p_clk.c), |
| 1028 | }, |
| 1029 | }; |
| 1030 | |
| 1031 | static struct branch_clk imem_p_clk = { |
| 1032 | .b = { |
| 1033 | .ctl_reg = AHB_EN_REG, |
| 1034 | .en_mask = BIT(6), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1035 | .hwcg_reg = AHB_EN2_REG, |
| 1036 | .hwcg_mask = BIT(12), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1037 | .reset_reg = SW_RESET_AHB_REG, |
| 1038 | .reset_mask = BIT(8), |
| 1039 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1040 | .halt_bit = 10, |
| 1041 | }, |
| 1042 | .c = { |
| 1043 | .dbg_name = "imem_p_clk", |
| 1044 | .ops = &clk_ops_branch, |
| 1045 | CLK_INIT(imem_p_clk.c), |
| 1046 | }, |
| 1047 | }; |
| 1048 | |
| 1049 | static struct branch_clk jpegd_p_clk = { |
| 1050 | .b = { |
| 1051 | .ctl_reg = AHB_EN_REG, |
| 1052 | .en_mask = BIT(21), |
| 1053 | .reset_reg = SW_RESET_AHB_REG, |
| 1054 | .reset_mask = BIT(4), |
| 1055 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1056 | .halt_bit = 7, |
| 1057 | }, |
| 1058 | .c = { |
| 1059 | .dbg_name = "jpegd_p_clk", |
| 1060 | .ops = &clk_ops_branch, |
| 1061 | CLK_INIT(jpegd_p_clk.c), |
| 1062 | }, |
| 1063 | }; |
| 1064 | |
| 1065 | static struct branch_clk mdp_p_clk = { |
| 1066 | .b = { |
| 1067 | .ctl_reg = AHB_EN_REG, |
| 1068 | .en_mask = BIT(10), |
| 1069 | .reset_reg = SW_RESET_AHB_REG, |
| 1070 | .reset_mask = BIT(3), |
| 1071 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1072 | .halt_bit = 11, |
| 1073 | }, |
| 1074 | .c = { |
| 1075 | .dbg_name = "mdp_p_clk", |
| 1076 | .ops = &clk_ops_branch, |
| 1077 | CLK_INIT(mdp_p_clk.c), |
| 1078 | }, |
| 1079 | }; |
| 1080 | |
| 1081 | static struct branch_clk rot_p_clk = { |
| 1082 | .b = { |
| 1083 | .ctl_reg = AHB_EN_REG, |
| 1084 | .en_mask = BIT(12), |
| 1085 | .reset_reg = SW_RESET_AHB_REG, |
| 1086 | .reset_mask = BIT(2), |
| 1087 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1088 | .halt_bit = 13, |
| 1089 | }, |
| 1090 | .c = { |
| 1091 | .dbg_name = "rot_p_clk", |
| 1092 | .ops = &clk_ops_branch, |
| 1093 | CLK_INIT(rot_p_clk.c), |
| 1094 | }, |
| 1095 | }; |
| 1096 | |
| 1097 | static struct branch_clk smmu_p_clk = { |
| 1098 | .b = { |
| 1099 | .ctl_reg = AHB_EN_REG, |
| 1100 | .en_mask = BIT(15), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1101 | .hwcg_reg = AHB_EN_REG, |
| 1102 | .hwcg_mask = BIT(26), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1103 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1104 | .halt_bit = 22, |
| 1105 | }, |
| 1106 | .c = { |
| 1107 | .dbg_name = "smmu_p_clk", |
| 1108 | .ops = &clk_ops_branch, |
| 1109 | CLK_INIT(smmu_p_clk.c), |
| 1110 | }, |
| 1111 | }; |
| 1112 | |
| 1113 | static struct branch_clk tv_enc_p_clk = { |
| 1114 | .b = { |
| 1115 | .ctl_reg = AHB_EN_REG, |
| 1116 | .en_mask = BIT(25), |
| 1117 | .reset_reg = SW_RESET_AHB_REG, |
| 1118 | .reset_mask = BIT(15), |
| 1119 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1120 | .halt_bit = 23, |
| 1121 | }, |
| 1122 | .c = { |
| 1123 | .dbg_name = "tv_enc_p_clk", |
| 1124 | .ops = &clk_ops_branch, |
| 1125 | CLK_INIT(tv_enc_p_clk.c), |
| 1126 | }, |
| 1127 | }; |
| 1128 | |
| 1129 | static struct branch_clk vcodec_p_clk = { |
| 1130 | .b = { |
| 1131 | .ctl_reg = AHB_EN_REG, |
| 1132 | .en_mask = BIT(11), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1133 | .hwcg_reg = AHB_EN2_REG, |
| 1134 | .hwcg_mask = BIT(26), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1135 | .reset_reg = SW_RESET_AHB_REG, |
| 1136 | .reset_mask = BIT(1), |
| 1137 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1138 | .halt_bit = 12, |
| 1139 | }, |
| 1140 | .c = { |
| 1141 | .dbg_name = "vcodec_p_clk", |
| 1142 | .ops = &clk_ops_branch, |
| 1143 | CLK_INIT(vcodec_p_clk.c), |
| 1144 | }, |
| 1145 | }; |
| 1146 | |
| 1147 | static struct branch_clk vfe_p_clk = { |
| 1148 | .b = { |
| 1149 | .ctl_reg = AHB_EN_REG, |
| 1150 | .en_mask = BIT(13), |
| 1151 | .reset_reg = SW_RESET_AHB_REG, |
| 1152 | .reset_mask = BIT(0), |
| 1153 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1154 | .halt_bit = 14, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 1155 | .retain_reg = AHB_EN2_REG, |
| 1156 | .retain_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1157 | }, |
| 1158 | .c = { |
| 1159 | .dbg_name = "vfe_p_clk", |
| 1160 | .ops = &clk_ops_branch, |
| 1161 | CLK_INIT(vfe_p_clk.c), |
| 1162 | }, |
| 1163 | }; |
| 1164 | |
| 1165 | static struct branch_clk vpe_p_clk = { |
| 1166 | .b = { |
| 1167 | .ctl_reg = AHB_EN_REG, |
| 1168 | .en_mask = BIT(16), |
| 1169 | .reset_reg = SW_RESET_AHB_REG, |
| 1170 | .reset_mask = BIT(14), |
| 1171 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1172 | .halt_bit = 15, |
| 1173 | }, |
| 1174 | .c = { |
| 1175 | .dbg_name = "vpe_p_clk", |
| 1176 | .ops = &clk_ops_branch, |
| 1177 | CLK_INIT(vpe_p_clk.c), |
| 1178 | }, |
| 1179 | }; |
| 1180 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1181 | static struct branch_clk vcap_p_clk = { |
| 1182 | .b = { |
| 1183 | .ctl_reg = AHB_EN3_REG, |
| 1184 | .en_mask = BIT(1), |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 1185 | .hwcg_reg = AHB_EN3_REG, |
| 1186 | .hwcg_mask = BIT(0), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1187 | .reset_reg = SW_RESET_AHB2_REG, |
| 1188 | .reset_mask = BIT(2), |
| 1189 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 1190 | .halt_bit = 23, |
| 1191 | }, |
| 1192 | .c = { |
| 1193 | .dbg_name = "vcap_p_clk", |
| 1194 | .ops = &clk_ops_branch, |
| 1195 | CLK_INIT(vcap_p_clk.c), |
| 1196 | }, |
| 1197 | }; |
| 1198 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1199 | /* |
| 1200 | * Peripheral Clocks |
| 1201 | */ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1202 | #define CLK_GP(i, n, h_r, h_b) \ |
| 1203 | struct rcg_clk i##_clk = { \ |
| 1204 | .b = { \ |
| 1205 | .ctl_reg = GPn_NS_REG(n), \ |
| 1206 | .en_mask = BIT(9), \ |
| 1207 | .halt_reg = h_r, \ |
| 1208 | .halt_bit = h_b, \ |
| 1209 | }, \ |
| 1210 | .ns_reg = GPn_NS_REG(n), \ |
| 1211 | .md_reg = GPn_MD_REG(n), \ |
| 1212 | .root_en_mask = BIT(11), \ |
| 1213 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1214 | .mnd_en_mask = BIT(8), \ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1215 | .set_rate = set_rate_mnd, \ |
| 1216 | .freq_tbl = clk_tbl_gp, \ |
| 1217 | .current_freq = &rcg_dummy_freq, \ |
| 1218 | .c = { \ |
| 1219 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1220 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1221 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \ |
| 1222 | CLK_INIT(i##_clk.c), \ |
| 1223 | }, \ |
| 1224 | } |
| 1225 | #define F_GP(f, s, d, m, n) \ |
| 1226 | { \ |
| 1227 | .freq_hz = f, \ |
| 1228 | .src_clk = &s##_clk.c, \ |
| 1229 | .md_val = MD8(16, m, 0, n), \ |
| 1230 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1231 | } |
| 1232 | static struct clk_freq_tbl clk_tbl_gp[] = { |
| 1233 | F_GP( 0, gnd, 1, 0, 0), |
| 1234 | F_GP( 9600000, cxo, 2, 0, 0), |
| 1235 | F_GP( 13500000, pxo, 2, 0, 0), |
| 1236 | F_GP( 19200000, cxo, 1, 0, 0), |
| 1237 | F_GP( 27000000, pxo, 1, 0, 0), |
| 1238 | F_GP( 64000000, pll8, 2, 1, 3), |
| 1239 | F_GP( 76800000, pll8, 1, 1, 5), |
| 1240 | F_GP( 96000000, pll8, 4, 0, 0), |
| 1241 | F_GP(128000000, pll8, 3, 0, 0), |
| 1242 | F_GP(192000000, pll8, 2, 0, 0), |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1243 | F_END |
| 1244 | }; |
| 1245 | |
| 1246 | static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7); |
| 1247 | static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6); |
| 1248 | static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5); |
| 1249 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1250 | #define CLK_GSBI_UART(i, n, h_r, h_b) \ |
| 1251 | struct rcg_clk i##_clk = { \ |
| 1252 | .b = { \ |
| 1253 | .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \ |
| 1254 | .en_mask = BIT(9), \ |
| 1255 | .reset_reg = GSBIn_RESET_REG(n), \ |
| 1256 | .reset_mask = BIT(0), \ |
| 1257 | .halt_reg = h_r, \ |
| 1258 | .halt_bit = h_b, \ |
| 1259 | }, \ |
| 1260 | .ns_reg = GSBIn_UART_APPS_NS_REG(n), \ |
| 1261 | .md_reg = GSBIn_UART_APPS_MD_REG(n), \ |
| 1262 | .root_en_mask = BIT(11), \ |
| 1263 | .ns_mask = (BM(31, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1264 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1265 | .set_rate = set_rate_mnd, \ |
| 1266 | .freq_tbl = clk_tbl_gsbi_uart, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1267 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1268 | .c = { \ |
| 1269 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1270 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1271 | VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1272 | CLK_INIT(i##_clk.c), \ |
| 1273 | }, \ |
| 1274 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1275 | #define F_GSBI_UART(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1276 | { \ |
| 1277 | .freq_hz = f, \ |
| 1278 | .src_clk = &s##_clk.c, \ |
| 1279 | .md_val = MD16(m, n), \ |
| 1280 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1281 | } |
| 1282 | static struct clk_freq_tbl clk_tbl_gsbi_uart[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1283 | F_GSBI_UART( 0, gnd, 1, 0, 0), |
Matt Wagantall | 9a561f7 | 2012-01-19 16:13:12 -0800 | [diff] [blame] | 1284 | F_GSBI_UART( 1843200, pll8, 2, 6, 625), |
| 1285 | F_GSBI_UART( 3686400, pll8, 2, 12, 625), |
| 1286 | F_GSBI_UART( 7372800, pll8, 2, 24, 625), |
| 1287 | F_GSBI_UART(14745600, pll8, 2, 48, 625), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1288 | F_GSBI_UART(16000000, pll8, 4, 1, 6), |
| 1289 | F_GSBI_UART(24000000, pll8, 4, 1, 4), |
| 1290 | F_GSBI_UART(32000000, pll8, 4, 1, 3), |
| 1291 | F_GSBI_UART(40000000, pll8, 1, 5, 48), |
| 1292 | F_GSBI_UART(46400000, pll8, 1, 29, 240), |
| 1293 | F_GSBI_UART(48000000, pll8, 4, 1, 2), |
| 1294 | F_GSBI_UART(51200000, pll8, 1, 2, 15), |
| 1295 | F_GSBI_UART(56000000, pll8, 1, 7, 48), |
| 1296 | F_GSBI_UART(58982400, pll8, 1, 96, 625), |
| 1297 | F_GSBI_UART(64000000, pll8, 2, 1, 3), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1298 | F_END |
| 1299 | }; |
| 1300 | |
| 1301 | static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10); |
| 1302 | static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6); |
| 1303 | static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2); |
| 1304 | static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26); |
| 1305 | static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22); |
| 1306 | static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18); |
| 1307 | static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14); |
| 1308 | static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10); |
| 1309 | static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6); |
| 1310 | static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2); |
| 1311 | static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17); |
| 1312 | static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13); |
| 1313 | |
| 1314 | #define CLK_GSBI_QUP(i, n, h_r, h_b) \ |
| 1315 | struct rcg_clk i##_clk = { \ |
| 1316 | .b = { \ |
| 1317 | .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \ |
| 1318 | .en_mask = BIT(9), \ |
| 1319 | .reset_reg = GSBIn_RESET_REG(n), \ |
| 1320 | .reset_mask = BIT(0), \ |
| 1321 | .halt_reg = h_r, \ |
| 1322 | .halt_bit = h_b, \ |
| 1323 | }, \ |
| 1324 | .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \ |
| 1325 | .md_reg = GSBIn_QUP_APPS_MD_REG(n), \ |
| 1326 | .root_en_mask = BIT(11), \ |
| 1327 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1328 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1329 | .set_rate = set_rate_mnd, \ |
| 1330 | .freq_tbl = clk_tbl_gsbi_qup, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1331 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1332 | .c = { \ |
| 1333 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1334 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1335 | VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1336 | CLK_INIT(i##_clk.c), \ |
| 1337 | }, \ |
| 1338 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1339 | #define F_GSBI_QUP(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1340 | { \ |
| 1341 | .freq_hz = f, \ |
| 1342 | .src_clk = &s##_clk.c, \ |
| 1343 | .md_val = MD8(16, m, 0, n), \ |
| 1344 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1345 | } |
| 1346 | static struct clk_freq_tbl clk_tbl_gsbi_qup[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1347 | F_GSBI_QUP( 0, gnd, 1, 0, 0), |
| 1348 | F_GSBI_QUP( 1100000, pxo, 1, 2, 49), |
| 1349 | F_GSBI_QUP( 5400000, pxo, 1, 1, 5), |
| 1350 | F_GSBI_QUP(10800000, pxo, 1, 2, 5), |
| 1351 | F_GSBI_QUP(15060000, pll8, 1, 2, 51), |
| 1352 | F_GSBI_QUP(24000000, pll8, 4, 1, 4), |
| 1353 | F_GSBI_QUP(25600000, pll8, 1, 1, 15), |
| 1354 | F_GSBI_QUP(27000000, pxo, 1, 0, 0), |
| 1355 | F_GSBI_QUP(48000000, pll8, 4, 1, 2), |
| 1356 | F_GSBI_QUP(51200000, pll8, 1, 2, 15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1357 | F_END |
| 1358 | }; |
| 1359 | |
| 1360 | static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9); |
| 1361 | static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4); |
| 1362 | static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0); |
| 1363 | static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24); |
| 1364 | static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20); |
| 1365 | static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16); |
| 1366 | static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12); |
| 1367 | static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8); |
| 1368 | static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4); |
| 1369 | static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0); |
| 1370 | static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15); |
| 1371 | static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11); |
| 1372 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1373 | #define F_PDM(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1374 | { \ |
| 1375 | .freq_hz = f, \ |
| 1376 | .src_clk = &s##_clk.c, \ |
| 1377 | .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1378 | } |
| 1379 | static struct clk_freq_tbl clk_tbl_pdm[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1380 | F_PDM( 0, gnd, 1), |
| 1381 | F_PDM(27000000, pxo, 1), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1382 | F_END |
| 1383 | }; |
| 1384 | |
| 1385 | static struct rcg_clk pdm_clk = { |
| 1386 | .b = { |
| 1387 | .ctl_reg = PDM_CLK_NS_REG, |
| 1388 | .en_mask = BIT(9), |
| 1389 | .reset_reg = PDM_CLK_NS_REG, |
| 1390 | .reset_mask = BIT(12), |
| 1391 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1392 | .halt_bit = 3, |
| 1393 | }, |
| 1394 | .ns_reg = PDM_CLK_NS_REG, |
| 1395 | .root_en_mask = BIT(11), |
| 1396 | .ns_mask = BM(1, 0), |
| 1397 | .set_rate = set_rate_nop, |
| 1398 | .freq_tbl = clk_tbl_pdm, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1399 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1400 | .c = { |
| 1401 | .dbg_name = "pdm_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1402 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1403 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1404 | CLK_INIT(pdm_clk.c), |
| 1405 | }, |
| 1406 | }; |
| 1407 | |
| 1408 | static struct branch_clk pmem_clk = { |
| 1409 | .b = { |
| 1410 | .ctl_reg = PMEM_ACLK_CTL_REG, |
| 1411 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1412 | .hwcg_reg = PMEM_ACLK_CTL_REG, |
| 1413 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1414 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 1415 | .halt_bit = 20, |
| 1416 | }, |
| 1417 | .c = { |
| 1418 | .dbg_name = "pmem_clk", |
| 1419 | .ops = &clk_ops_branch, |
| 1420 | CLK_INIT(pmem_clk.c), |
| 1421 | }, |
| 1422 | }; |
| 1423 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1424 | #define F_PRNG(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1425 | { \ |
| 1426 | .freq_hz = f, \ |
| 1427 | .src_clk = &s##_clk.c, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1428 | } |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 1429 | static struct clk_freq_tbl clk_tbl_prng_32[] = { |
| 1430 | F_PRNG(32000000, pll8), |
| 1431 | F_END |
| 1432 | }; |
| 1433 | |
| 1434 | static struct clk_freq_tbl clk_tbl_prng_64[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1435 | F_PRNG(64000000, pll8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1436 | F_END |
| 1437 | }; |
| 1438 | |
| 1439 | static struct rcg_clk prng_clk = { |
| 1440 | .b = { |
| 1441 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 1442 | .en_mask = BIT(10), |
| 1443 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 1444 | .halt_check = HALT_VOTED, |
| 1445 | .halt_bit = 10, |
| 1446 | }, |
| 1447 | .set_rate = set_rate_nop, |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 1448 | .freq_tbl = clk_tbl_prng_32, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1449 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1450 | .c = { |
| 1451 | .dbg_name = "prng_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1452 | .ops = &clk_ops_rcg, |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 1453 | VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1454 | CLK_INIT(prng_clk.c), |
| 1455 | }, |
| 1456 | }; |
| 1457 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1458 | #define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1459 | struct rcg_clk name = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1460 | .b = { \ |
| 1461 | .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \ |
| 1462 | .en_mask = BIT(9), \ |
| 1463 | .reset_reg = SDCn_RESET_REG(n), \ |
| 1464 | .reset_mask = BIT(0), \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1465 | .halt_reg = CLK_HALT_DFAB_STATE_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1466 | .halt_bit = h_b, \ |
| 1467 | }, \ |
| 1468 | .ns_reg = SDCn_APPS_CLK_NS_REG(n), \ |
| 1469 | .md_reg = SDCn_APPS_CLK_MD_REG(n), \ |
| 1470 | .root_en_mask = BIT(11), \ |
| 1471 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1472 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1473 | .set_rate = set_rate_mnd, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1474 | .freq_tbl = clk_tbl_sdc, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1475 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1476 | .c = { \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1477 | .dbg_name = #name, \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1478 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1479 | VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1480 | CLK_INIT(name.c), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1481 | }, \ |
| 1482 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1483 | #define F_SDC(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1484 | { \ |
| 1485 | .freq_hz = f, \ |
| 1486 | .src_clk = &s##_clk.c, \ |
| 1487 | .md_val = MD8(16, m, 0, n), \ |
| 1488 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1489 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1490 | static struct clk_freq_tbl clk_tbl_sdc[] = { |
| 1491 | F_SDC( 0, gnd, 1, 0, 0), |
| 1492 | F_SDC( 144000, pxo, 3, 2, 125), |
| 1493 | F_SDC( 400000, pll8, 4, 1, 240), |
| 1494 | F_SDC( 16000000, pll8, 4, 1, 6), |
| 1495 | F_SDC( 17070000, pll8, 1, 2, 45), |
| 1496 | F_SDC( 20210000, pll8, 1, 1, 19), |
| 1497 | F_SDC( 24000000, pll8, 4, 1, 4), |
| 1498 | F_SDC( 48000000, pll8, 4, 1, 2), |
| 1499 | F_SDC( 64000000, pll8, 3, 1, 2), |
| 1500 | F_SDC( 96000000, pll8, 4, 0, 0), |
Subhash Jadavani | bd238ba | 2011-11-24 15:12:39 +0530 | [diff] [blame] | 1501 | F_SDC(192000000, pll8, 2, 0, 0), |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1502 | F_END |
| 1503 | }; |
| 1504 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1505 | static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000); |
| 1506 | static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000); |
| 1507 | static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000); |
| 1508 | static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000); |
| 1509 | static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000); |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1510 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1511 | #define F_TSIF_REF(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1512 | { \ |
| 1513 | .freq_hz = f, \ |
| 1514 | .src_clk = &s##_clk.c, \ |
| 1515 | .md_val = MD16(m, n), \ |
| 1516 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1517 | } |
| 1518 | static struct clk_freq_tbl clk_tbl_tsif_ref[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1519 | F_TSIF_REF( 0, gnd, 1, 0, 0), |
| 1520 | F_TSIF_REF(105000, pxo, 1, 1, 256), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1521 | F_END |
| 1522 | }; |
| 1523 | |
| 1524 | static struct rcg_clk tsif_ref_clk = { |
| 1525 | .b = { |
| 1526 | .ctl_reg = TSIF_REF_CLK_NS_REG, |
| 1527 | .en_mask = BIT(9), |
| 1528 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1529 | .halt_bit = 5, |
| 1530 | }, |
| 1531 | .ns_reg = TSIF_REF_CLK_NS_REG, |
| 1532 | .md_reg = TSIF_REF_CLK_MD_REG, |
| 1533 | .root_en_mask = BIT(11), |
| 1534 | .ns_mask = (BM(31, 16) | BM(6, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1535 | .mnd_en_mask = BIT(8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1536 | .set_rate = set_rate_mnd, |
| 1537 | .freq_tbl = clk_tbl_tsif_ref, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1538 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1539 | .c = { |
| 1540 | .dbg_name = "tsif_ref_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1541 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1542 | VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1543 | CLK_INIT(tsif_ref_clk.c), |
| 1544 | }, |
| 1545 | }; |
| 1546 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1547 | #define F_TSSC(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1548 | { \ |
| 1549 | .freq_hz = f, \ |
| 1550 | .src_clk = &s##_clk.c, \ |
| 1551 | .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1552 | } |
| 1553 | static struct clk_freq_tbl clk_tbl_tssc[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1554 | F_TSSC( 0, gnd), |
| 1555 | F_TSSC(27000000, pxo), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1556 | F_END |
| 1557 | }; |
| 1558 | |
| 1559 | static struct rcg_clk tssc_clk = { |
| 1560 | .b = { |
| 1561 | .ctl_reg = TSSC_CLK_CTL_REG, |
| 1562 | .en_mask = BIT(4), |
| 1563 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1564 | .halt_bit = 4, |
| 1565 | }, |
| 1566 | .ns_reg = TSSC_CLK_CTL_REG, |
| 1567 | .ns_mask = BM(1, 0), |
| 1568 | .set_rate = set_rate_nop, |
| 1569 | .freq_tbl = clk_tbl_tssc, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1570 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1571 | .c = { |
| 1572 | .dbg_name = "tssc_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1573 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1574 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1575 | CLK_INIT(tssc_clk.c), |
| 1576 | }, |
| 1577 | }; |
| 1578 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1579 | #define CLK_USB_HS(name, n, h_b) \ |
| 1580 | static struct rcg_clk name = { \ |
| 1581 | .b = { \ |
| 1582 | .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \ |
| 1583 | .en_mask = BIT(9), \ |
| 1584 | .reset_reg = USB_HS##n##_RESET_REG, \ |
| 1585 | .reset_mask = BIT(0), \ |
| 1586 | .halt_reg = CLK_HALT_DFAB_STATE_REG, \ |
| 1587 | .halt_bit = h_b, \ |
| 1588 | }, \ |
| 1589 | .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \ |
| 1590 | .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \ |
| 1591 | .root_en_mask = BIT(11), \ |
| 1592 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1593 | .mnd_en_mask = BIT(8), \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1594 | .set_rate = set_rate_mnd, \ |
| 1595 | .freq_tbl = clk_tbl_usb, \ |
| 1596 | .current_freq = &rcg_dummy_freq, \ |
| 1597 | .c = { \ |
| 1598 | .dbg_name = #name, \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1599 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1600 | VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1601 | CLK_INIT(name.c), \ |
| 1602 | }, \ |
| 1603 | } |
| 1604 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1605 | #define F_USB(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1606 | { \ |
| 1607 | .freq_hz = f, \ |
| 1608 | .src_clk = &s##_clk.c, \ |
| 1609 | .md_val = MD8(16, m, 0, n), \ |
| 1610 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1611 | } |
| 1612 | static struct clk_freq_tbl clk_tbl_usb[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1613 | F_USB( 0, gnd, 1, 0, 0), |
| 1614 | F_USB(60000000, pll8, 1, 5, 32), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1615 | F_END |
| 1616 | }; |
| 1617 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1618 | CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0); |
| 1619 | CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30); |
| 1620 | CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1621 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1622 | static struct clk_freq_tbl clk_tbl_usb_hsic[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1623 | F_USB( 0, gnd, 1, 0, 0), |
| 1624 | F_USB(60000000, pll8, 1, 5, 32), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1625 | F_END |
| 1626 | }; |
| 1627 | |
| 1628 | static struct rcg_clk usb_hsic_xcvr_fs_clk = { |
| 1629 | .b = { |
| 1630 | .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG, |
| 1631 | .en_mask = BIT(9), |
| 1632 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1633 | .halt_bit = 26, |
| 1634 | }, |
| 1635 | .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG, |
| 1636 | .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG, |
| 1637 | .root_en_mask = BIT(11), |
| 1638 | .ns_mask = (BM(23, 16) | BM(6, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1639 | .mnd_en_mask = BIT(8), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1640 | .set_rate = set_rate_mnd, |
| 1641 | .freq_tbl = clk_tbl_usb_hsic, |
| 1642 | .current_freq = &rcg_dummy_freq, |
| 1643 | .c = { |
| 1644 | .dbg_name = "usb_hsic_xcvr_fs_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1645 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1646 | VDD_DIG_FMAX_MAP1(LOW, 60000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1647 | CLK_INIT(usb_hsic_xcvr_fs_clk.c), |
| 1648 | }, |
| 1649 | }; |
| 1650 | |
| 1651 | static struct branch_clk usb_hsic_system_clk = { |
| 1652 | .b = { |
| 1653 | .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG, |
| 1654 | .en_mask = BIT(4), |
| 1655 | .reset_reg = USB_HSIC_RESET_REG, |
| 1656 | .reset_mask = BIT(0), |
| 1657 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1658 | .halt_bit = 24, |
| 1659 | }, |
| 1660 | .parent = &usb_hsic_xcvr_fs_clk.c, |
| 1661 | .c = { |
| 1662 | .dbg_name = "usb_hsic_system_clk", |
| 1663 | .ops = &clk_ops_branch, |
| 1664 | CLK_INIT(usb_hsic_system_clk.c), |
| 1665 | }, |
| 1666 | }; |
| 1667 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1668 | #define F_USB_HSIC(f, s) \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1669 | { \ |
| 1670 | .freq_hz = f, \ |
| 1671 | .src_clk = &s##_clk.c, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1672 | } |
| 1673 | static struct clk_freq_tbl clk_tbl_usb2_hsic[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1674 | F_USB_HSIC(480000000, pll14), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1675 | F_END |
| 1676 | }; |
| 1677 | |
| 1678 | static struct rcg_clk usb_hsic_hsic_src_clk = { |
| 1679 | .b = { |
| 1680 | .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG, |
| 1681 | .halt_check = NOCHECK, |
| 1682 | }, |
| 1683 | .root_en_mask = BIT(0), |
| 1684 | .set_rate = set_rate_nop, |
| 1685 | .freq_tbl = clk_tbl_usb2_hsic, |
| 1686 | .current_freq = &rcg_dummy_freq, |
| 1687 | .c = { |
| 1688 | .dbg_name = "usb_hsic_hsic_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1689 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1690 | VDD_DIG_FMAX_MAP1(LOW, 480000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1691 | CLK_INIT(usb_hsic_hsic_src_clk.c), |
| 1692 | }, |
| 1693 | }; |
| 1694 | |
| 1695 | static struct branch_clk usb_hsic_hsic_clk = { |
| 1696 | .b = { |
| 1697 | .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG, |
| 1698 | .en_mask = BIT(0), |
| 1699 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1700 | .halt_bit = 19, |
| 1701 | }, |
| 1702 | .parent = &usb_hsic_hsic_src_clk.c, |
| 1703 | .c = { |
| 1704 | .dbg_name = "usb_hsic_hsic_clk", |
| 1705 | .ops = &clk_ops_branch, |
| 1706 | CLK_INIT(usb_hsic_hsic_clk.c), |
| 1707 | }, |
| 1708 | }; |
| 1709 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1710 | #define F_USB_HSIO_CAL(f, s) \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1711 | { \ |
| 1712 | .freq_hz = f, \ |
| 1713 | .src_clk = &s##_clk.c, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1714 | } |
| 1715 | static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1716 | F_USB_HSIO_CAL(9000000, pxo), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1717 | F_END |
| 1718 | }; |
| 1719 | |
| 1720 | static struct rcg_clk usb_hsic_hsio_cal_clk = { |
| 1721 | .b = { |
| 1722 | .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG, |
| 1723 | .en_mask = BIT(0), |
| 1724 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1725 | .halt_bit = 23, |
| 1726 | }, |
| 1727 | .set_rate = set_rate_nop, |
| 1728 | .freq_tbl = clk_tbl_usb_hsio_cal, |
| 1729 | .current_freq = &rcg_dummy_freq, |
| 1730 | .c = { |
| 1731 | .dbg_name = "usb_hsic_hsio_cal_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1732 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1733 | VDD_DIG_FMAX_MAP1(LOW, 10000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1734 | CLK_INIT(usb_hsic_hsio_cal_clk.c), |
| 1735 | }, |
| 1736 | }; |
| 1737 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1738 | static struct branch_clk usb_phy0_clk = { |
| 1739 | .b = { |
| 1740 | .reset_reg = USB_PHY0_RESET_REG, |
| 1741 | .reset_mask = BIT(0), |
| 1742 | }, |
| 1743 | .c = { |
| 1744 | .dbg_name = "usb_phy0_clk", |
| 1745 | .ops = &clk_ops_reset, |
| 1746 | CLK_INIT(usb_phy0_clk.c), |
| 1747 | }, |
| 1748 | }; |
| 1749 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1750 | #define CLK_USB_FS(i, n, fmax_nom) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1751 | struct rcg_clk i##_clk = { \ |
| 1752 | .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \ |
| 1753 | .b = { \ |
| 1754 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \ |
| 1755 | .halt_check = NOCHECK, \ |
| 1756 | }, \ |
| 1757 | .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \ |
| 1758 | .root_en_mask = BIT(11), \ |
| 1759 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1760 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1761 | .set_rate = set_rate_mnd, \ |
| 1762 | .freq_tbl = clk_tbl_usb, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1763 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1764 | .c = { \ |
| 1765 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1766 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1767 | VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1768 | CLK_INIT(i##_clk.c), \ |
| 1769 | }, \ |
| 1770 | } |
| 1771 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1772 | static CLK_USB_FS(usb_fs1_src, 1, 64000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1773 | static struct branch_clk usb_fs1_xcvr_clk = { |
| 1774 | .b = { |
| 1775 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1), |
| 1776 | .en_mask = BIT(9), |
| 1777 | .reset_reg = USB_FSn_RESET_REG(1), |
| 1778 | .reset_mask = BIT(1), |
| 1779 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1780 | .halt_bit = 15, |
| 1781 | }, |
| 1782 | .parent = &usb_fs1_src_clk.c, |
| 1783 | .c = { |
| 1784 | .dbg_name = "usb_fs1_xcvr_clk", |
| 1785 | .ops = &clk_ops_branch, |
| 1786 | CLK_INIT(usb_fs1_xcvr_clk.c), |
| 1787 | }, |
| 1788 | }; |
| 1789 | |
| 1790 | static struct branch_clk usb_fs1_sys_clk = { |
| 1791 | .b = { |
| 1792 | .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1), |
| 1793 | .en_mask = BIT(4), |
| 1794 | .reset_reg = USB_FSn_RESET_REG(1), |
| 1795 | .reset_mask = BIT(0), |
| 1796 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1797 | .halt_bit = 16, |
| 1798 | }, |
| 1799 | .parent = &usb_fs1_src_clk.c, |
| 1800 | .c = { |
| 1801 | .dbg_name = "usb_fs1_sys_clk", |
| 1802 | .ops = &clk_ops_branch, |
| 1803 | CLK_INIT(usb_fs1_sys_clk.c), |
| 1804 | }, |
| 1805 | }; |
| 1806 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1807 | static CLK_USB_FS(usb_fs2_src, 2, 60000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1808 | static struct branch_clk usb_fs2_xcvr_clk = { |
| 1809 | .b = { |
| 1810 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2), |
| 1811 | .en_mask = BIT(9), |
| 1812 | .reset_reg = USB_FSn_RESET_REG(2), |
| 1813 | .reset_mask = BIT(1), |
| 1814 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1815 | .halt_bit = 12, |
| 1816 | }, |
| 1817 | .parent = &usb_fs2_src_clk.c, |
| 1818 | .c = { |
| 1819 | .dbg_name = "usb_fs2_xcvr_clk", |
| 1820 | .ops = &clk_ops_branch, |
| 1821 | CLK_INIT(usb_fs2_xcvr_clk.c), |
| 1822 | }, |
| 1823 | }; |
| 1824 | |
| 1825 | static struct branch_clk usb_fs2_sys_clk = { |
| 1826 | .b = { |
| 1827 | .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2), |
| 1828 | .en_mask = BIT(4), |
| 1829 | .reset_reg = USB_FSn_RESET_REG(2), |
| 1830 | .reset_mask = BIT(0), |
| 1831 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1832 | .halt_bit = 13, |
| 1833 | }, |
| 1834 | .parent = &usb_fs2_src_clk.c, |
| 1835 | .c = { |
| 1836 | .dbg_name = "usb_fs2_sys_clk", |
| 1837 | .ops = &clk_ops_branch, |
| 1838 | CLK_INIT(usb_fs2_sys_clk.c), |
| 1839 | }, |
| 1840 | }; |
| 1841 | |
| 1842 | /* Fast Peripheral Bus Clocks */ |
| 1843 | static struct branch_clk ce1_core_clk = { |
| 1844 | .b = { |
| 1845 | .ctl_reg = CE1_CORE_CLK_CTL_REG, |
| 1846 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1847 | .hwcg_reg = CE1_CORE_CLK_CTL_REG, |
| 1848 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1849 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1850 | .halt_bit = 27, |
| 1851 | }, |
| 1852 | .c = { |
| 1853 | .dbg_name = "ce1_core_clk", |
| 1854 | .ops = &clk_ops_branch, |
| 1855 | CLK_INIT(ce1_core_clk.c), |
| 1856 | }, |
| 1857 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1858 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1859 | static struct branch_clk ce1_p_clk = { |
| 1860 | .b = { |
| 1861 | .ctl_reg = CE1_HCLK_CTL_REG, |
| 1862 | .en_mask = BIT(4), |
| 1863 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1864 | .halt_bit = 1, |
| 1865 | }, |
| 1866 | .c = { |
| 1867 | .dbg_name = "ce1_p_clk", |
| 1868 | .ops = &clk_ops_branch, |
| 1869 | CLK_INIT(ce1_p_clk.c), |
| 1870 | }, |
| 1871 | }; |
| 1872 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1873 | #define F_CE3(f, s, d) \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1874 | { \ |
| 1875 | .freq_hz = f, \ |
| 1876 | .src_clk = &s##_clk.c, \ |
| 1877 | .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1878 | } |
| 1879 | |
| 1880 | static struct clk_freq_tbl clk_tbl_ce3[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1881 | F_CE3( 0, gnd, 1), |
| 1882 | F_CE3( 48000000, pll8, 8), |
| 1883 | F_CE3(100000000, pll3, 12), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1884 | F_END |
| 1885 | }; |
| 1886 | |
| 1887 | static struct rcg_clk ce3_src_clk = { |
| 1888 | .b = { |
| 1889 | .ctl_reg = CE3_CLK_SRC_NS_REG, |
| 1890 | .halt_check = NOCHECK, |
| 1891 | }, |
| 1892 | .ns_reg = CE3_CLK_SRC_NS_REG, |
| 1893 | .root_en_mask = BIT(7), |
| 1894 | .ns_mask = BM(6, 0), |
| 1895 | .set_rate = set_rate_nop, |
| 1896 | .freq_tbl = clk_tbl_ce3, |
| 1897 | .current_freq = &rcg_dummy_freq, |
| 1898 | .c = { |
| 1899 | .dbg_name = "ce3_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1900 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1901 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1902 | CLK_INIT(ce3_src_clk.c), |
| 1903 | }, |
| 1904 | }; |
| 1905 | |
| 1906 | static struct branch_clk ce3_core_clk = { |
| 1907 | .b = { |
| 1908 | .ctl_reg = CE3_CORE_CLK_CTL_REG, |
| 1909 | .en_mask = BIT(4), |
| 1910 | .reset_reg = CE3_CORE_CLK_CTL_REG, |
| 1911 | .reset_mask = BIT(7), |
| 1912 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 1913 | .halt_bit = 5, |
| 1914 | }, |
| 1915 | .parent = &ce3_src_clk.c, |
| 1916 | .c = { |
| 1917 | .dbg_name = "ce3_core_clk", |
| 1918 | .ops = &clk_ops_branch, |
| 1919 | CLK_INIT(ce3_core_clk.c), |
| 1920 | } |
| 1921 | }; |
| 1922 | |
| 1923 | static struct branch_clk ce3_p_clk = { |
| 1924 | .b = { |
| 1925 | .ctl_reg = CE3_HCLK_CTL_REG, |
| 1926 | .en_mask = BIT(4), |
| 1927 | .reset_reg = CE3_HCLK_CTL_REG, |
| 1928 | .reset_mask = BIT(7), |
| 1929 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG, |
| 1930 | .halt_bit = 16, |
| 1931 | }, |
| 1932 | .parent = &ce3_src_clk.c, |
| 1933 | .c = { |
| 1934 | .dbg_name = "ce3_p_clk", |
| 1935 | .ops = &clk_ops_branch, |
| 1936 | CLK_INIT(ce3_p_clk.c), |
| 1937 | } |
| 1938 | }; |
| 1939 | |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 1940 | #define F_SATA(f, s, d) \ |
| 1941 | { \ |
| 1942 | .freq_hz = f, \ |
| 1943 | .src_clk = &s##_clk.c, \ |
| 1944 | .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \ |
| 1945 | } |
| 1946 | |
| 1947 | static struct clk_freq_tbl clk_tbl_sata[] = { |
| 1948 | F_SATA( 0, gnd, 1), |
| 1949 | F_SATA( 48000000, pll8, 8), |
| 1950 | F_SATA(100000000, pll3, 12), |
| 1951 | F_END |
| 1952 | }; |
| 1953 | |
| 1954 | static struct rcg_clk sata_src_clk = { |
| 1955 | .b = { |
| 1956 | .ctl_reg = SATA_CLK_SRC_NS_REG, |
| 1957 | .halt_check = NOCHECK, |
| 1958 | }, |
| 1959 | .ns_reg = SATA_CLK_SRC_NS_REG, |
| 1960 | .root_en_mask = BIT(7), |
| 1961 | .ns_mask = BM(6, 0), |
| 1962 | .set_rate = set_rate_nop, |
| 1963 | .freq_tbl = clk_tbl_sata, |
| 1964 | .current_freq = &rcg_dummy_freq, |
| 1965 | .c = { |
| 1966 | .dbg_name = "sata_src_clk", |
| 1967 | .ops = &clk_ops_rcg, |
| 1968 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 1969 | CLK_INIT(sata_src_clk.c), |
| 1970 | }, |
| 1971 | }; |
| 1972 | |
| 1973 | static struct branch_clk sata_rxoob_clk = { |
| 1974 | .b = { |
| 1975 | .ctl_reg = SATA_RXOOB_CLK_CTL_REG, |
| 1976 | .en_mask = BIT(4), |
| 1977 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 1978 | .halt_bit = 26, |
| 1979 | }, |
| 1980 | .parent = &sata_src_clk.c, |
| 1981 | .c = { |
| 1982 | .dbg_name = "sata_rxoob_clk", |
| 1983 | .ops = &clk_ops_branch, |
| 1984 | CLK_INIT(sata_rxoob_clk.c), |
| 1985 | }, |
| 1986 | }; |
| 1987 | |
| 1988 | static struct branch_clk sata_pmalive_clk = { |
| 1989 | .b = { |
| 1990 | .ctl_reg = SATA_PMALIVE_CLK_CTL_REG, |
| 1991 | .en_mask = BIT(4), |
| 1992 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 1993 | .halt_bit = 25, |
| 1994 | }, |
| 1995 | .parent = &sata_src_clk.c, |
| 1996 | .c = { |
| 1997 | .dbg_name = "sata_pmalive_clk", |
| 1998 | .ops = &clk_ops_branch, |
| 1999 | CLK_INIT(sata_pmalive_clk.c), |
| 2000 | }, |
| 2001 | }; |
| 2002 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2003 | static struct branch_clk sata_phy_ref_clk = { |
| 2004 | .b = { |
| 2005 | .ctl_reg = SATA_PHY_REF_CLK_CTL_REG, |
| 2006 | .en_mask = BIT(4), |
| 2007 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2008 | .halt_bit = 24, |
| 2009 | }, |
| 2010 | .parent = &pxo_clk.c, |
| 2011 | .c = { |
| 2012 | .dbg_name = "sata_phy_ref_clk", |
| 2013 | .ops = &clk_ops_branch, |
| 2014 | CLK_INIT(sata_phy_ref_clk.c), |
| 2015 | }, |
| 2016 | }; |
| 2017 | |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 2018 | static struct branch_clk sata_a_clk = { |
| 2019 | .b = { |
| 2020 | .ctl_reg = SATA_ACLK_CTL_REG, |
| 2021 | .en_mask = BIT(4), |
| 2022 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG, |
| 2023 | .halt_bit = 12, |
| 2024 | }, |
| 2025 | .c = { |
| 2026 | .dbg_name = "sata_a_clk", |
| 2027 | .ops = &clk_ops_branch, |
| 2028 | CLK_INIT(sata_a_clk.c), |
| 2029 | }, |
| 2030 | }; |
| 2031 | |
| 2032 | static struct branch_clk sata_p_clk = { |
| 2033 | .b = { |
| 2034 | .ctl_reg = SATA_HCLK_CTL_REG, |
| 2035 | .en_mask = BIT(4), |
| 2036 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2037 | .halt_bit = 27, |
| 2038 | }, |
| 2039 | .c = { |
| 2040 | .dbg_name = "sata_p_clk", |
| 2041 | .ops = &clk_ops_branch, |
| 2042 | CLK_INIT(sata_p_clk.c), |
| 2043 | }, |
| 2044 | }; |
| 2045 | |
| 2046 | static struct branch_clk sfab_sata_s_p_clk = { |
| 2047 | .b = { |
| 2048 | .ctl_reg = SFAB_SATA_S_HCLK_CTL_REG, |
| 2049 | .en_mask = BIT(4), |
| 2050 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG, |
| 2051 | .halt_bit = 14, |
| 2052 | }, |
| 2053 | .c = { |
| 2054 | .dbg_name = "sfab_sata_s_p_clk", |
| 2055 | .ops = &clk_ops_branch, |
| 2056 | CLK_INIT(sfab_sata_s_p_clk.c), |
| 2057 | }, |
| 2058 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2059 | static struct branch_clk pcie_p_clk = { |
| 2060 | .b = { |
| 2061 | .ctl_reg = PCIE_HCLK_CTL_REG, |
| 2062 | .en_mask = BIT(4), |
| 2063 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2064 | .halt_bit = 8, |
| 2065 | }, |
| 2066 | .c = { |
| 2067 | .dbg_name = "pcie_p_clk", |
| 2068 | .ops = &clk_ops_branch, |
| 2069 | CLK_INIT(pcie_p_clk.c), |
| 2070 | }, |
| 2071 | }; |
| 2072 | |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 2073 | static struct branch_clk pcie_phy_ref_clk = { |
| 2074 | .b = { |
| 2075 | .ctl_reg = PCIE_PCLK_CTL_REG, |
| 2076 | .en_mask = BIT(4), |
| 2077 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2078 | .halt_bit = 29, |
| 2079 | }, |
| 2080 | .c = { |
| 2081 | .dbg_name = "pcie_phy_ref_clk", |
| 2082 | .ops = &clk_ops_branch, |
| 2083 | CLK_INIT(pcie_phy_ref_clk.c), |
| 2084 | }, |
| 2085 | }; |
| 2086 | |
| 2087 | static struct branch_clk pcie_a_clk = { |
| 2088 | .b = { |
| 2089 | .ctl_reg = PCIE_ACLK_CTL_REG, |
| 2090 | .en_mask = BIT(4), |
| 2091 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG, |
| 2092 | .halt_bit = 13, |
| 2093 | }, |
| 2094 | .c = { |
| 2095 | .dbg_name = "pcie_a_clk", |
| 2096 | .ops = &clk_ops_branch, |
| 2097 | CLK_INIT(pcie_a_clk.c), |
| 2098 | }, |
| 2099 | }; |
| 2100 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2101 | static struct branch_clk dma_bam_p_clk = { |
| 2102 | .b = { |
| 2103 | .ctl_reg = DMA_BAM_HCLK_CTL, |
| 2104 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2105 | .hwcg_reg = DMA_BAM_HCLK_CTL, |
| 2106 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2107 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2108 | .halt_bit = 12, |
| 2109 | }, |
| 2110 | .c = { |
| 2111 | .dbg_name = "dma_bam_p_clk", |
| 2112 | .ops = &clk_ops_branch, |
| 2113 | CLK_INIT(dma_bam_p_clk.c), |
| 2114 | }, |
| 2115 | }; |
| 2116 | |
| 2117 | static struct branch_clk gsbi1_p_clk = { |
| 2118 | .b = { |
| 2119 | .ctl_reg = GSBIn_HCLK_CTL_REG(1), |
| 2120 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2121 | .hwcg_reg = GSBIn_HCLK_CTL_REG(1), |
| 2122 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2123 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2124 | .halt_bit = 11, |
| 2125 | }, |
| 2126 | .c = { |
| 2127 | .dbg_name = "gsbi1_p_clk", |
| 2128 | .ops = &clk_ops_branch, |
| 2129 | CLK_INIT(gsbi1_p_clk.c), |
| 2130 | }, |
| 2131 | }; |
| 2132 | |
| 2133 | static struct branch_clk gsbi2_p_clk = { |
| 2134 | .b = { |
| 2135 | .ctl_reg = GSBIn_HCLK_CTL_REG(2), |
| 2136 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2137 | .hwcg_reg = GSBIn_HCLK_CTL_REG(2), |
| 2138 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2139 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2140 | .halt_bit = 7, |
| 2141 | }, |
| 2142 | .c = { |
| 2143 | .dbg_name = "gsbi2_p_clk", |
| 2144 | .ops = &clk_ops_branch, |
| 2145 | CLK_INIT(gsbi2_p_clk.c), |
| 2146 | }, |
| 2147 | }; |
| 2148 | |
| 2149 | static struct branch_clk gsbi3_p_clk = { |
| 2150 | .b = { |
| 2151 | .ctl_reg = GSBIn_HCLK_CTL_REG(3), |
| 2152 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2153 | .hwcg_reg = GSBIn_HCLK_CTL_REG(3), |
| 2154 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2155 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2156 | .halt_bit = 3, |
| 2157 | }, |
| 2158 | .c = { |
| 2159 | .dbg_name = "gsbi3_p_clk", |
| 2160 | .ops = &clk_ops_branch, |
| 2161 | CLK_INIT(gsbi3_p_clk.c), |
| 2162 | }, |
| 2163 | }; |
| 2164 | |
| 2165 | static struct branch_clk gsbi4_p_clk = { |
| 2166 | .b = { |
| 2167 | .ctl_reg = GSBIn_HCLK_CTL_REG(4), |
| 2168 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2169 | .hwcg_reg = GSBIn_HCLK_CTL_REG(4), |
| 2170 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2171 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2172 | .halt_bit = 27, |
| 2173 | }, |
| 2174 | .c = { |
| 2175 | .dbg_name = "gsbi4_p_clk", |
| 2176 | .ops = &clk_ops_branch, |
| 2177 | CLK_INIT(gsbi4_p_clk.c), |
| 2178 | }, |
| 2179 | }; |
| 2180 | |
| 2181 | static struct branch_clk gsbi5_p_clk = { |
| 2182 | .b = { |
| 2183 | .ctl_reg = GSBIn_HCLK_CTL_REG(5), |
| 2184 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2185 | .hwcg_reg = GSBIn_HCLK_CTL_REG(5), |
| 2186 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2187 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2188 | .halt_bit = 23, |
| 2189 | }, |
| 2190 | .c = { |
| 2191 | .dbg_name = "gsbi5_p_clk", |
| 2192 | .ops = &clk_ops_branch, |
| 2193 | CLK_INIT(gsbi5_p_clk.c), |
| 2194 | }, |
| 2195 | }; |
| 2196 | |
| 2197 | static struct branch_clk gsbi6_p_clk = { |
| 2198 | .b = { |
| 2199 | .ctl_reg = GSBIn_HCLK_CTL_REG(6), |
| 2200 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2201 | .hwcg_reg = GSBIn_HCLK_CTL_REG(6), |
| 2202 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2203 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2204 | .halt_bit = 19, |
| 2205 | }, |
| 2206 | .c = { |
| 2207 | .dbg_name = "gsbi6_p_clk", |
| 2208 | .ops = &clk_ops_branch, |
| 2209 | CLK_INIT(gsbi6_p_clk.c), |
| 2210 | }, |
| 2211 | }; |
| 2212 | |
| 2213 | static struct branch_clk gsbi7_p_clk = { |
| 2214 | .b = { |
| 2215 | .ctl_reg = GSBIn_HCLK_CTL_REG(7), |
| 2216 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2217 | .hwcg_reg = GSBIn_HCLK_CTL_REG(7), |
| 2218 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2219 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2220 | .halt_bit = 15, |
| 2221 | }, |
| 2222 | .c = { |
| 2223 | .dbg_name = "gsbi7_p_clk", |
| 2224 | .ops = &clk_ops_branch, |
| 2225 | CLK_INIT(gsbi7_p_clk.c), |
| 2226 | }, |
| 2227 | }; |
| 2228 | |
| 2229 | static struct branch_clk gsbi8_p_clk = { |
| 2230 | .b = { |
| 2231 | .ctl_reg = GSBIn_HCLK_CTL_REG(8), |
| 2232 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2233 | .hwcg_reg = GSBIn_HCLK_CTL_REG(8), |
| 2234 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2235 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2236 | .halt_bit = 11, |
| 2237 | }, |
| 2238 | .c = { |
| 2239 | .dbg_name = "gsbi8_p_clk", |
| 2240 | .ops = &clk_ops_branch, |
| 2241 | CLK_INIT(gsbi8_p_clk.c), |
| 2242 | }, |
| 2243 | }; |
| 2244 | |
| 2245 | static struct branch_clk gsbi9_p_clk = { |
| 2246 | .b = { |
| 2247 | .ctl_reg = GSBIn_HCLK_CTL_REG(9), |
| 2248 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2249 | .hwcg_reg = GSBIn_HCLK_CTL_REG(9), |
| 2250 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2251 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2252 | .halt_bit = 7, |
| 2253 | }, |
| 2254 | .c = { |
| 2255 | .dbg_name = "gsbi9_p_clk", |
| 2256 | .ops = &clk_ops_branch, |
| 2257 | CLK_INIT(gsbi9_p_clk.c), |
| 2258 | }, |
| 2259 | }; |
| 2260 | |
| 2261 | static struct branch_clk gsbi10_p_clk = { |
| 2262 | .b = { |
| 2263 | .ctl_reg = GSBIn_HCLK_CTL_REG(10), |
| 2264 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2265 | .hwcg_reg = GSBIn_HCLK_CTL_REG(10), |
| 2266 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2267 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2268 | .halt_bit = 3, |
| 2269 | }, |
| 2270 | .c = { |
| 2271 | .dbg_name = "gsbi10_p_clk", |
| 2272 | .ops = &clk_ops_branch, |
| 2273 | CLK_INIT(gsbi10_p_clk.c), |
| 2274 | }, |
| 2275 | }; |
| 2276 | |
| 2277 | static struct branch_clk gsbi11_p_clk = { |
| 2278 | .b = { |
| 2279 | .ctl_reg = GSBIn_HCLK_CTL_REG(11), |
| 2280 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2281 | .hwcg_reg = GSBIn_HCLK_CTL_REG(11), |
| 2282 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2283 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2284 | .halt_bit = 18, |
| 2285 | }, |
| 2286 | .c = { |
| 2287 | .dbg_name = "gsbi11_p_clk", |
| 2288 | .ops = &clk_ops_branch, |
| 2289 | CLK_INIT(gsbi11_p_clk.c), |
| 2290 | }, |
| 2291 | }; |
| 2292 | |
| 2293 | static struct branch_clk gsbi12_p_clk = { |
| 2294 | .b = { |
| 2295 | .ctl_reg = GSBIn_HCLK_CTL_REG(12), |
| 2296 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2297 | .hwcg_reg = GSBIn_HCLK_CTL_REG(12), |
| 2298 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2299 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2300 | .halt_bit = 14, |
| 2301 | }, |
| 2302 | .c = { |
| 2303 | .dbg_name = "gsbi12_p_clk", |
| 2304 | .ops = &clk_ops_branch, |
| 2305 | CLK_INIT(gsbi12_p_clk.c), |
| 2306 | }, |
| 2307 | }; |
| 2308 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2309 | static struct branch_clk sata_phy_cfg_clk = { |
| 2310 | .b = { |
| 2311 | .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG, |
| 2312 | .en_mask = BIT(4), |
| 2313 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2314 | .halt_bit = 12, |
| 2315 | }, |
| 2316 | .c = { |
| 2317 | .dbg_name = "sata_phy_cfg_clk", |
| 2318 | .ops = &clk_ops_branch, |
| 2319 | CLK_INIT(sata_phy_cfg_clk.c), |
Stephen Boyd | 973e4ba | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2320 | }, |
| 2321 | }; |
| 2322 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2323 | static struct branch_clk tsif_p_clk = { |
| 2324 | .b = { |
| 2325 | .ctl_reg = TSIF_HCLK_CTL_REG, |
| 2326 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2327 | .hwcg_reg = TSIF_HCLK_CTL_REG, |
| 2328 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2329 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2330 | .halt_bit = 7, |
| 2331 | }, |
| 2332 | .c = { |
| 2333 | .dbg_name = "tsif_p_clk", |
| 2334 | .ops = &clk_ops_branch, |
| 2335 | CLK_INIT(tsif_p_clk.c), |
| 2336 | }, |
| 2337 | }; |
| 2338 | |
| 2339 | static struct branch_clk usb_fs1_p_clk = { |
| 2340 | .b = { |
| 2341 | .ctl_reg = USB_FSn_HCLK_CTL_REG(1), |
| 2342 | .en_mask = BIT(4), |
| 2343 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2344 | .halt_bit = 17, |
| 2345 | }, |
| 2346 | .c = { |
| 2347 | .dbg_name = "usb_fs1_p_clk", |
| 2348 | .ops = &clk_ops_branch, |
| 2349 | CLK_INIT(usb_fs1_p_clk.c), |
| 2350 | }, |
| 2351 | }; |
| 2352 | |
| 2353 | static struct branch_clk usb_fs2_p_clk = { |
| 2354 | .b = { |
| 2355 | .ctl_reg = USB_FSn_HCLK_CTL_REG(2), |
| 2356 | .en_mask = BIT(4), |
| 2357 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2358 | .halt_bit = 14, |
| 2359 | }, |
| 2360 | .c = { |
| 2361 | .dbg_name = "usb_fs2_p_clk", |
| 2362 | .ops = &clk_ops_branch, |
| 2363 | CLK_INIT(usb_fs2_p_clk.c), |
| 2364 | }, |
| 2365 | }; |
| 2366 | |
| 2367 | static struct branch_clk usb_hs1_p_clk = { |
| 2368 | .b = { |
| 2369 | .ctl_reg = USB_HS1_HCLK_CTL_REG, |
| 2370 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2371 | .hwcg_reg = USB_HS1_HCLK_CTL_REG, |
| 2372 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2373 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2374 | .halt_bit = 1, |
| 2375 | }, |
| 2376 | .c = { |
| 2377 | .dbg_name = "usb_hs1_p_clk", |
| 2378 | .ops = &clk_ops_branch, |
| 2379 | CLK_INIT(usb_hs1_p_clk.c), |
| 2380 | }, |
| 2381 | }; |
| 2382 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2383 | static struct branch_clk usb_hs3_p_clk = { |
| 2384 | .b = { |
| 2385 | .ctl_reg = USB_HS3_HCLK_CTL_REG, |
| 2386 | .en_mask = BIT(4), |
| 2387 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2388 | .halt_bit = 31, |
| 2389 | }, |
| 2390 | .c = { |
| 2391 | .dbg_name = "usb_hs3_p_clk", |
| 2392 | .ops = &clk_ops_branch, |
| 2393 | CLK_INIT(usb_hs3_p_clk.c), |
| 2394 | }, |
| 2395 | }; |
| 2396 | |
| 2397 | static struct branch_clk usb_hs4_p_clk = { |
| 2398 | .b = { |
| 2399 | .ctl_reg = USB_HS4_HCLK_CTL_REG, |
| 2400 | .en_mask = BIT(4), |
| 2401 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2402 | .halt_bit = 7, |
| 2403 | }, |
| 2404 | .c = { |
| 2405 | .dbg_name = "usb_hs4_p_clk", |
| 2406 | .ops = &clk_ops_branch, |
| 2407 | CLK_INIT(usb_hs4_p_clk.c), |
| 2408 | }, |
| 2409 | }; |
| 2410 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2411 | static struct branch_clk usb_hsic_p_clk = { |
| 2412 | .b = { |
| 2413 | .ctl_reg = USB_HSIC_HCLK_CTL_REG, |
| 2414 | .en_mask = BIT(4), |
| 2415 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2416 | .halt_bit = 28, |
| 2417 | }, |
| 2418 | .c = { |
| 2419 | .dbg_name = "usb_hsic_p_clk", |
| 2420 | .ops = &clk_ops_branch, |
| 2421 | CLK_INIT(usb_hsic_p_clk.c), |
| 2422 | }, |
| 2423 | }; |
| 2424 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2425 | static struct branch_clk sdc1_p_clk = { |
| 2426 | .b = { |
| 2427 | .ctl_reg = SDCn_HCLK_CTL_REG(1), |
| 2428 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2429 | .hwcg_reg = SDCn_HCLK_CTL_REG(1), |
| 2430 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2431 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2432 | .halt_bit = 11, |
| 2433 | }, |
| 2434 | .c = { |
| 2435 | .dbg_name = "sdc1_p_clk", |
| 2436 | .ops = &clk_ops_branch, |
| 2437 | CLK_INIT(sdc1_p_clk.c), |
| 2438 | }, |
| 2439 | }; |
| 2440 | |
| 2441 | static struct branch_clk sdc2_p_clk = { |
| 2442 | .b = { |
| 2443 | .ctl_reg = SDCn_HCLK_CTL_REG(2), |
| 2444 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2445 | .hwcg_reg = SDCn_HCLK_CTL_REG(2), |
| 2446 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2447 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2448 | .halt_bit = 10, |
| 2449 | }, |
| 2450 | .c = { |
| 2451 | .dbg_name = "sdc2_p_clk", |
| 2452 | .ops = &clk_ops_branch, |
| 2453 | CLK_INIT(sdc2_p_clk.c), |
| 2454 | }, |
| 2455 | }; |
| 2456 | |
| 2457 | static struct branch_clk sdc3_p_clk = { |
| 2458 | .b = { |
| 2459 | .ctl_reg = SDCn_HCLK_CTL_REG(3), |
| 2460 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2461 | .hwcg_reg = SDCn_HCLK_CTL_REG(3), |
| 2462 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2463 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2464 | .halt_bit = 9, |
| 2465 | }, |
| 2466 | .c = { |
| 2467 | .dbg_name = "sdc3_p_clk", |
| 2468 | .ops = &clk_ops_branch, |
| 2469 | CLK_INIT(sdc3_p_clk.c), |
| 2470 | }, |
| 2471 | }; |
| 2472 | |
| 2473 | static struct branch_clk sdc4_p_clk = { |
| 2474 | .b = { |
| 2475 | .ctl_reg = SDCn_HCLK_CTL_REG(4), |
| 2476 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2477 | .hwcg_reg = SDCn_HCLK_CTL_REG(4), |
| 2478 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2479 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2480 | .halt_bit = 8, |
| 2481 | }, |
| 2482 | .c = { |
| 2483 | .dbg_name = "sdc4_p_clk", |
| 2484 | .ops = &clk_ops_branch, |
| 2485 | CLK_INIT(sdc4_p_clk.c), |
| 2486 | }, |
| 2487 | }; |
| 2488 | |
| 2489 | static struct branch_clk sdc5_p_clk = { |
| 2490 | .b = { |
| 2491 | .ctl_reg = SDCn_HCLK_CTL_REG(5), |
| 2492 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2493 | .hwcg_reg = SDCn_HCLK_CTL_REG(5), |
| 2494 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2495 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2496 | .halt_bit = 7, |
| 2497 | }, |
| 2498 | .c = { |
| 2499 | .dbg_name = "sdc5_p_clk", |
| 2500 | .ops = &clk_ops_branch, |
| 2501 | CLK_INIT(sdc5_p_clk.c), |
| 2502 | }, |
| 2503 | }; |
| 2504 | |
| 2505 | /* HW-Voteable Clocks */ |
| 2506 | static struct branch_clk adm0_clk = { |
| 2507 | .b = { |
| 2508 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2509 | .en_mask = BIT(2), |
| 2510 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2511 | .halt_check = HALT_VOTED, |
| 2512 | .halt_bit = 14, |
| 2513 | }, |
| 2514 | .c = { |
| 2515 | .dbg_name = "adm0_clk", |
| 2516 | .ops = &clk_ops_branch, |
| 2517 | CLK_INIT(adm0_clk.c), |
| 2518 | }, |
| 2519 | }; |
| 2520 | |
| 2521 | static struct branch_clk adm0_p_clk = { |
| 2522 | .b = { |
| 2523 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2524 | .en_mask = BIT(3), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2525 | .hwcg_reg = ADM0_PBUS_CLK_CTL_REG, |
| 2526 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2527 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2528 | .halt_check = HALT_VOTED, |
| 2529 | .halt_bit = 13, |
| 2530 | }, |
| 2531 | .c = { |
| 2532 | .dbg_name = "adm0_p_clk", |
| 2533 | .ops = &clk_ops_branch, |
| 2534 | CLK_INIT(adm0_p_clk.c), |
| 2535 | }, |
| 2536 | }; |
| 2537 | |
| 2538 | static struct branch_clk pmic_arb0_p_clk = { |
| 2539 | .b = { |
| 2540 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2541 | .en_mask = BIT(8), |
| 2542 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2543 | .halt_check = HALT_VOTED, |
| 2544 | .halt_bit = 22, |
| 2545 | }, |
| 2546 | .c = { |
| 2547 | .dbg_name = "pmic_arb0_p_clk", |
| 2548 | .ops = &clk_ops_branch, |
| 2549 | CLK_INIT(pmic_arb0_p_clk.c), |
| 2550 | }, |
| 2551 | }; |
| 2552 | |
| 2553 | static struct branch_clk pmic_arb1_p_clk = { |
| 2554 | .b = { |
| 2555 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2556 | .en_mask = BIT(9), |
| 2557 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2558 | .halt_check = HALT_VOTED, |
| 2559 | .halt_bit = 21, |
| 2560 | }, |
| 2561 | .c = { |
| 2562 | .dbg_name = "pmic_arb1_p_clk", |
| 2563 | .ops = &clk_ops_branch, |
| 2564 | CLK_INIT(pmic_arb1_p_clk.c), |
| 2565 | }, |
| 2566 | }; |
| 2567 | |
| 2568 | static struct branch_clk pmic_ssbi2_clk = { |
| 2569 | .b = { |
| 2570 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2571 | .en_mask = BIT(7), |
| 2572 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2573 | .halt_check = HALT_VOTED, |
| 2574 | .halt_bit = 23, |
| 2575 | }, |
| 2576 | .c = { |
| 2577 | .dbg_name = "pmic_ssbi2_clk", |
| 2578 | .ops = &clk_ops_branch, |
| 2579 | CLK_INIT(pmic_ssbi2_clk.c), |
| 2580 | }, |
| 2581 | }; |
| 2582 | |
| 2583 | static struct branch_clk rpm_msg_ram_p_clk = { |
| 2584 | .b = { |
| 2585 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2586 | .en_mask = BIT(6), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2587 | .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG, |
| 2588 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2589 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2590 | .halt_check = HALT_VOTED, |
| 2591 | .halt_bit = 12, |
| 2592 | }, |
| 2593 | .c = { |
| 2594 | .dbg_name = "rpm_msg_ram_p_clk", |
| 2595 | .ops = &clk_ops_branch, |
| 2596 | CLK_INIT(rpm_msg_ram_p_clk.c), |
| 2597 | }, |
| 2598 | }; |
| 2599 | |
| 2600 | /* |
| 2601 | * Multimedia Clocks |
| 2602 | */ |
| 2603 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2604 | #define CLK_CAM(name, n, hb) \ |
| 2605 | struct rcg_clk name = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2606 | .b = { \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2607 | .ctl_reg = CAMCLK##n##_CC_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2608 | .en_mask = BIT(0), \ |
| 2609 | .halt_reg = DBG_BUS_VEC_I_REG, \ |
| 2610 | .halt_bit = hb, \ |
| 2611 | }, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2612 | .ns_reg = CAMCLK##n##_NS_REG, \ |
| 2613 | .md_reg = CAMCLK##n##_MD_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2614 | .root_en_mask = BIT(2), \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2615 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 2616 | .mnd_en_mask = BIT(5), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2617 | .ctl_mask = BM(7, 6), \ |
| 2618 | .set_rate = set_rate_mnd_8, \ |
| 2619 | .freq_tbl = clk_tbl_cam, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2620 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2621 | .c = { \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2622 | .dbg_name = #name, \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 2623 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2624 | VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2625 | CLK_INIT(name.c), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2626 | }, \ |
| 2627 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2628 | #define F_CAM(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2629 | { \ |
| 2630 | .freq_hz = f, \ |
| 2631 | .src_clk = &s##_clk.c, \ |
| 2632 | .md_val = MD8(8, m, 0, n), \ |
| 2633 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 2634 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2635 | } |
| 2636 | static struct clk_freq_tbl clk_tbl_cam[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2637 | F_CAM( 0, gnd, 1, 0, 0), |
| 2638 | F_CAM( 6000000, pll8, 4, 1, 16), |
| 2639 | F_CAM( 8000000, pll8, 4, 1, 12), |
| 2640 | F_CAM( 12000000, pll8, 4, 1, 8), |
| 2641 | F_CAM( 16000000, pll8, 4, 1, 6), |
| 2642 | F_CAM( 19200000, pll8, 4, 1, 5), |
| 2643 | F_CAM( 24000000, pll8, 4, 1, 4), |
| 2644 | F_CAM( 32000000, pll8, 4, 1, 3), |
| 2645 | F_CAM( 48000000, pll8, 4, 1, 2), |
| 2646 | F_CAM( 64000000, pll8, 3, 1, 2), |
| 2647 | F_CAM( 96000000, pll8, 4, 0, 0), |
| 2648 | F_CAM(128000000, pll8, 3, 0, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2649 | F_END |
| 2650 | }; |
| 2651 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2652 | static CLK_CAM(cam0_clk, 0, 15); |
| 2653 | static CLK_CAM(cam1_clk, 1, 16); |
| 2654 | static CLK_CAM(cam2_clk, 2, 31); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2655 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2656 | #define F_CSI(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2657 | { \ |
| 2658 | .freq_hz = f, \ |
| 2659 | .src_clk = &s##_clk.c, \ |
| 2660 | .md_val = MD8(8, m, 0, n), \ |
| 2661 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 2662 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2663 | } |
| 2664 | static struct clk_freq_tbl clk_tbl_csi[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2665 | F_CSI( 0, gnd, 1, 0, 0), |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2666 | F_CSI( 27000000, pxo, 1, 0, 0), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2667 | F_CSI( 85330000, pll8, 1, 2, 9), |
| 2668 | F_CSI(177780000, pll2, 1, 2, 9), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2669 | F_END |
| 2670 | }; |
| 2671 | |
| 2672 | static struct rcg_clk csi0_src_clk = { |
| 2673 | .ns_reg = CSI0_NS_REG, |
| 2674 | .b = { |
| 2675 | .ctl_reg = CSI0_CC_REG, |
| 2676 | .halt_check = NOCHECK, |
| 2677 | }, |
| 2678 | .md_reg = CSI0_MD_REG, |
| 2679 | .root_en_mask = BIT(2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2680 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 2681 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2682 | .ctl_mask = BM(7, 6), |
| 2683 | .set_rate = set_rate_mnd, |
| 2684 | .freq_tbl = clk_tbl_csi, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2685 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2686 | .c = { |
| 2687 | .dbg_name = "csi0_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 2688 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2689 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2690 | CLK_INIT(csi0_src_clk.c), |
| 2691 | }, |
| 2692 | }; |
| 2693 | |
| 2694 | static struct branch_clk csi0_clk = { |
| 2695 | .b = { |
| 2696 | .ctl_reg = CSI0_CC_REG, |
| 2697 | .en_mask = BIT(0), |
| 2698 | .reset_reg = SW_RESET_CORE_REG, |
| 2699 | .reset_mask = BIT(8), |
| 2700 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2701 | .halt_bit = 13, |
| 2702 | }, |
| 2703 | .parent = &csi0_src_clk.c, |
| 2704 | .c = { |
| 2705 | .dbg_name = "csi0_clk", |
| 2706 | .ops = &clk_ops_branch, |
| 2707 | CLK_INIT(csi0_clk.c), |
| 2708 | }, |
| 2709 | }; |
| 2710 | |
| 2711 | static struct branch_clk csi0_phy_clk = { |
| 2712 | .b = { |
| 2713 | .ctl_reg = CSI0_CC_REG, |
| 2714 | .en_mask = BIT(8), |
| 2715 | .reset_reg = SW_RESET_CORE_REG, |
| 2716 | .reset_mask = BIT(29), |
| 2717 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2718 | .halt_bit = 9, |
| 2719 | }, |
| 2720 | .parent = &csi0_src_clk.c, |
| 2721 | .c = { |
| 2722 | .dbg_name = "csi0_phy_clk", |
| 2723 | .ops = &clk_ops_branch, |
| 2724 | CLK_INIT(csi0_phy_clk.c), |
| 2725 | }, |
| 2726 | }; |
| 2727 | |
| 2728 | static struct rcg_clk csi1_src_clk = { |
| 2729 | .ns_reg = CSI1_NS_REG, |
| 2730 | .b = { |
| 2731 | .ctl_reg = CSI1_CC_REG, |
| 2732 | .halt_check = NOCHECK, |
| 2733 | }, |
| 2734 | .md_reg = CSI1_MD_REG, |
| 2735 | .root_en_mask = BIT(2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2736 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 2737 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2738 | .ctl_mask = BM(7, 6), |
| 2739 | .set_rate = set_rate_mnd, |
| 2740 | .freq_tbl = clk_tbl_csi, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2741 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2742 | .c = { |
| 2743 | .dbg_name = "csi1_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 2744 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2745 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2746 | CLK_INIT(csi1_src_clk.c), |
| 2747 | }, |
| 2748 | }; |
| 2749 | |
| 2750 | static struct branch_clk csi1_clk = { |
| 2751 | .b = { |
| 2752 | .ctl_reg = CSI1_CC_REG, |
| 2753 | .en_mask = BIT(0), |
| 2754 | .reset_reg = SW_RESET_CORE_REG, |
| 2755 | .reset_mask = BIT(18), |
| 2756 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2757 | .halt_bit = 14, |
| 2758 | }, |
| 2759 | .parent = &csi1_src_clk.c, |
| 2760 | .c = { |
| 2761 | .dbg_name = "csi1_clk", |
| 2762 | .ops = &clk_ops_branch, |
| 2763 | CLK_INIT(csi1_clk.c), |
| 2764 | }, |
| 2765 | }; |
| 2766 | |
| 2767 | static struct branch_clk csi1_phy_clk = { |
| 2768 | .b = { |
| 2769 | .ctl_reg = CSI1_CC_REG, |
| 2770 | .en_mask = BIT(8), |
| 2771 | .reset_reg = SW_RESET_CORE_REG, |
| 2772 | .reset_mask = BIT(28), |
| 2773 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2774 | .halt_bit = 10, |
| 2775 | }, |
| 2776 | .parent = &csi1_src_clk.c, |
| 2777 | .c = { |
| 2778 | .dbg_name = "csi1_phy_clk", |
| 2779 | .ops = &clk_ops_branch, |
| 2780 | CLK_INIT(csi1_phy_clk.c), |
| 2781 | }, |
| 2782 | }; |
| 2783 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2784 | static struct rcg_clk csi2_src_clk = { |
| 2785 | .ns_reg = CSI2_NS_REG, |
| 2786 | .b = { |
| 2787 | .ctl_reg = CSI2_CC_REG, |
| 2788 | .halt_check = NOCHECK, |
| 2789 | }, |
| 2790 | .md_reg = CSI2_MD_REG, |
| 2791 | .root_en_mask = BIT(2), |
| 2792 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 2793 | .mnd_en_mask = BIT(5), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2794 | .ctl_mask = BM(7, 6), |
| 2795 | .set_rate = set_rate_mnd, |
| 2796 | .freq_tbl = clk_tbl_csi, |
| 2797 | .current_freq = &rcg_dummy_freq, |
| 2798 | .c = { |
| 2799 | .dbg_name = "csi2_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 2800 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2801 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2802 | CLK_INIT(csi2_src_clk.c), |
| 2803 | }, |
| 2804 | }; |
| 2805 | |
| 2806 | static struct branch_clk csi2_clk = { |
| 2807 | .b = { |
| 2808 | .ctl_reg = CSI2_CC_REG, |
| 2809 | .en_mask = BIT(0), |
| 2810 | .reset_reg = SW_RESET_CORE2_REG, |
| 2811 | .reset_mask = BIT(2), |
| 2812 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2813 | .halt_bit = 29, |
| 2814 | }, |
| 2815 | .parent = &csi2_src_clk.c, |
| 2816 | .c = { |
| 2817 | .dbg_name = "csi2_clk", |
| 2818 | .ops = &clk_ops_branch, |
| 2819 | CLK_INIT(csi2_clk.c), |
| 2820 | }, |
| 2821 | }; |
| 2822 | |
| 2823 | static struct branch_clk csi2_phy_clk = { |
| 2824 | .b = { |
| 2825 | .ctl_reg = CSI2_CC_REG, |
| 2826 | .en_mask = BIT(8), |
| 2827 | .reset_reg = SW_RESET_CORE_REG, |
| 2828 | .reset_mask = BIT(31), |
| 2829 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2830 | .halt_bit = 29, |
| 2831 | }, |
| 2832 | .parent = &csi2_src_clk.c, |
| 2833 | .c = { |
| 2834 | .dbg_name = "csi2_phy_clk", |
| 2835 | .ops = &clk_ops_branch, |
| 2836 | CLK_INIT(csi2_phy_clk.c), |
| 2837 | }, |
| 2838 | }; |
| 2839 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2840 | static struct clk *pix_rdi_mux_map[] = { |
| 2841 | [0] = &csi0_clk.c, |
| 2842 | [1] = &csi1_clk.c, |
| 2843 | [2] = &csi2_clk.c, |
| 2844 | NULL, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2845 | }; |
| 2846 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2847 | struct pix_rdi_clk { |
| 2848 | bool enabled; |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2849 | unsigned long cur_rate; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2850 | |
| 2851 | void __iomem *const s_reg; |
| 2852 | u32 s_mask; |
| 2853 | |
| 2854 | void __iomem *const s2_reg; |
| 2855 | u32 s2_mask; |
| 2856 | |
| 2857 | struct branch b; |
| 2858 | struct clk c; |
| 2859 | }; |
| 2860 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2861 | static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *c) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2862 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2863 | return container_of(c, struct pix_rdi_clk, c); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2864 | } |
| 2865 | |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2866 | static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2867 | { |
| 2868 | int ret, i; |
| 2869 | u32 reg; |
| 2870 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2871 | struct pix_rdi_clk *rdi = to_pix_rdi_clk(c); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2872 | struct clk **mux_map = pix_rdi_mux_map; |
| 2873 | |
| 2874 | /* |
| 2875 | * These clocks select three inputs via two muxes. One mux selects |
| 2876 | * between csi0 and csi1 and the second mux selects between that mux's |
| 2877 | * output and csi2. The source and destination selections for each |
| 2878 | * mux must be clocking for the switch to succeed so just turn on |
| 2879 | * all three sources because it's easier than figuring out what source |
| 2880 | * needs to be on at what time. |
| 2881 | */ |
| 2882 | for (i = 0; mux_map[i]; i++) { |
| 2883 | ret = clk_enable(mux_map[i]); |
| 2884 | if (ret) |
| 2885 | goto err; |
| 2886 | } |
| 2887 | if (rate >= i) { |
| 2888 | ret = -EINVAL; |
| 2889 | goto err; |
| 2890 | } |
| 2891 | /* Keep the new source on when switching inputs of an enabled clock */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2892 | if (rdi->enabled) { |
| 2893 | clk_disable(mux_map[rdi->cur_rate]); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2894 | clk_enable(mux_map[rate]); |
| 2895 | } |
| 2896 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2897 | reg = readl_relaxed(rdi->s2_reg); |
| 2898 | reg &= ~rdi->s2_mask; |
| 2899 | reg |= rate == 2 ? rdi->s2_mask : 0; |
| 2900 | writel_relaxed(reg, rdi->s2_reg); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2901 | /* |
| 2902 | * Wait at least 6 cycles of slowest clock |
| 2903 | * for the glitch-free MUX to fully switch sources. |
| 2904 | */ |
| 2905 | mb(); |
| 2906 | udelay(1); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2907 | reg = readl_relaxed(rdi->s_reg); |
| 2908 | reg &= ~rdi->s_mask; |
| 2909 | reg |= rate == 1 ? rdi->s_mask : 0; |
| 2910 | writel_relaxed(reg, rdi->s_reg); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2911 | /* |
| 2912 | * Wait at least 6 cycles of slowest clock |
| 2913 | * for the glitch-free MUX to fully switch sources. |
| 2914 | */ |
| 2915 | mb(); |
| 2916 | udelay(1); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2917 | rdi->cur_rate = rate; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2918 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 2919 | err: |
| 2920 | for (i--; i >= 0; i--) |
| 2921 | clk_disable(mux_map[i]); |
| 2922 | |
| 2923 | return 0; |
| 2924 | } |
| 2925 | |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2926 | static unsigned long pix_rdi_clk_get_rate(struct clk *c) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2927 | { |
| 2928 | return to_pix_rdi_clk(c)->cur_rate; |
| 2929 | } |
| 2930 | |
| 2931 | static int pix_rdi_clk_enable(struct clk *c) |
| 2932 | { |
| 2933 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2934 | struct pix_rdi_clk *rdi = to_pix_rdi_clk(c); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2935 | |
| 2936 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
Matt Wagantall | 0de1b3f | 2012-06-05 19:52:43 -0700 | [diff] [blame] | 2937 | __branch_enable_reg(&rdi->b, rdi->c.dbg_name); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2938 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2939 | rdi->enabled = true; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2940 | |
| 2941 | return 0; |
| 2942 | } |
| 2943 | |
| 2944 | static void pix_rdi_clk_disable(struct clk *c) |
| 2945 | { |
| 2946 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2947 | struct pix_rdi_clk *rdi = to_pix_rdi_clk(c); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2948 | |
| 2949 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
Matt Wagantall | 0de1b3f | 2012-06-05 19:52:43 -0700 | [diff] [blame] | 2950 | __branch_disable_reg(&rdi->b, rdi->c.dbg_name); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2951 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2952 | rdi->enabled = false; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2953 | } |
| 2954 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2955 | static int pix_rdi_clk_reset(struct clk *c, enum clk_reset_action action) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2956 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2957 | return branch_reset(&to_pix_rdi_clk(c)->b, action); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2958 | } |
| 2959 | |
| 2960 | static struct clk *pix_rdi_clk_get_parent(struct clk *c) |
| 2961 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2962 | return pix_rdi_mux_map[to_pix_rdi_clk(c)->cur_rate]; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2963 | } |
| 2964 | |
| 2965 | static int pix_rdi_clk_list_rate(struct clk *c, unsigned n) |
| 2966 | { |
| 2967 | if (pix_rdi_mux_map[n]) |
| 2968 | return n; |
| 2969 | return -ENXIO; |
| 2970 | } |
| 2971 | |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 2972 | static enum handoff pix_rdi_clk_handoff(struct clk *c) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2973 | { |
| 2974 | u32 reg; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2975 | struct pix_rdi_clk *rdi = to_pix_rdi_clk(c); |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 2976 | enum handoff ret; |
| 2977 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2978 | ret = branch_handoff(&rdi->b, &rdi->c); |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 2979 | if (ret == HANDOFF_DISABLED_CLK) |
| 2980 | return ret; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2981 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2982 | reg = readl_relaxed(rdi->s_reg); |
| 2983 | rdi->cur_rate = reg & rdi->s_mask ? 1 : 0; |
| 2984 | reg = readl_relaxed(rdi->s2_reg); |
| 2985 | rdi->cur_rate = reg & rdi->s2_mask ? 2 : rdi->cur_rate; |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 2986 | |
| 2987 | return HANDOFF_ENABLED_CLK; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2988 | } |
| 2989 | |
| 2990 | static struct clk_ops clk_ops_pix_rdi_8960 = { |
| 2991 | .enable = pix_rdi_clk_enable, |
| 2992 | .disable = pix_rdi_clk_disable, |
| 2993 | .auto_off = pix_rdi_clk_disable, |
| 2994 | .handoff = pix_rdi_clk_handoff, |
| 2995 | .set_rate = pix_rdi_clk_set_rate, |
| 2996 | .get_rate = pix_rdi_clk_get_rate, |
| 2997 | .list_rate = pix_rdi_clk_list_rate, |
| 2998 | .reset = pix_rdi_clk_reset, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2999 | .get_parent = pix_rdi_clk_get_parent, |
| 3000 | }; |
| 3001 | |
| 3002 | static struct pix_rdi_clk csi_pix_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3003 | .b = { |
| 3004 | .ctl_reg = MISC_CC_REG, |
| 3005 | .en_mask = BIT(26), |
| 3006 | .halt_check = DELAY, |
| 3007 | .reset_reg = SW_RESET_CORE_REG, |
| 3008 | .reset_mask = BIT(26), |
| 3009 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3010 | .s_reg = MISC_CC_REG, |
| 3011 | .s_mask = BIT(25), |
| 3012 | .s2_reg = MISC_CC3_REG, |
| 3013 | .s2_mask = BIT(13), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3014 | .c = { |
| 3015 | .dbg_name = "csi_pix_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3016 | .ops = &clk_ops_pix_rdi_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3017 | CLK_INIT(csi_pix_clk.c), |
| 3018 | }, |
| 3019 | }; |
| 3020 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3021 | static struct pix_rdi_clk csi_pix1_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3022 | .b = { |
| 3023 | .ctl_reg = MISC_CC3_REG, |
| 3024 | .en_mask = BIT(10), |
| 3025 | .halt_check = DELAY, |
| 3026 | .reset_reg = SW_RESET_CORE_REG, |
| 3027 | .reset_mask = BIT(30), |
| 3028 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3029 | .s_reg = MISC_CC3_REG, |
| 3030 | .s_mask = BIT(8), |
| 3031 | .s2_reg = MISC_CC3_REG, |
| 3032 | .s2_mask = BIT(9), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3033 | .c = { |
| 3034 | .dbg_name = "csi_pix1_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3035 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3036 | CLK_INIT(csi_pix1_clk.c), |
| 3037 | }, |
| 3038 | }; |
| 3039 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3040 | static struct pix_rdi_clk csi_rdi_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3041 | .b = { |
| 3042 | .ctl_reg = MISC_CC_REG, |
| 3043 | .en_mask = BIT(13), |
| 3044 | .halt_check = DELAY, |
| 3045 | .reset_reg = SW_RESET_CORE_REG, |
| 3046 | .reset_mask = BIT(27), |
| 3047 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3048 | .s_reg = MISC_CC_REG, |
| 3049 | .s_mask = BIT(12), |
| 3050 | .s2_reg = MISC_CC3_REG, |
| 3051 | .s2_mask = BIT(12), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3052 | .c = { |
| 3053 | .dbg_name = "csi_rdi_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3054 | .ops = &clk_ops_pix_rdi_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3055 | CLK_INIT(csi_rdi_clk.c), |
| 3056 | }, |
| 3057 | }; |
| 3058 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3059 | static struct pix_rdi_clk csi_rdi1_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3060 | .b = { |
| 3061 | .ctl_reg = MISC_CC3_REG, |
| 3062 | .en_mask = BIT(2), |
| 3063 | .halt_check = DELAY, |
| 3064 | .reset_reg = SW_RESET_CORE2_REG, |
| 3065 | .reset_mask = BIT(1), |
| 3066 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3067 | .s_reg = MISC_CC3_REG, |
| 3068 | .s_mask = BIT(0), |
| 3069 | .s2_reg = MISC_CC3_REG, |
| 3070 | .s2_mask = BIT(1), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3071 | .c = { |
| 3072 | .dbg_name = "csi_rdi1_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3073 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3074 | CLK_INIT(csi_rdi1_clk.c), |
| 3075 | }, |
| 3076 | }; |
| 3077 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3078 | static struct pix_rdi_clk csi_rdi2_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3079 | .b = { |
| 3080 | .ctl_reg = MISC_CC3_REG, |
| 3081 | .en_mask = BIT(6), |
| 3082 | .halt_check = DELAY, |
| 3083 | .reset_reg = SW_RESET_CORE2_REG, |
| 3084 | .reset_mask = BIT(0), |
| 3085 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3086 | .s_reg = MISC_CC3_REG, |
| 3087 | .s_mask = BIT(4), |
| 3088 | .s2_reg = MISC_CC3_REG, |
| 3089 | .s2_mask = BIT(5), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3090 | .c = { |
| 3091 | .dbg_name = "csi_rdi2_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3092 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3093 | CLK_INIT(csi_rdi2_clk.c), |
| 3094 | }, |
| 3095 | }; |
| 3096 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3097 | #define F_CSI_PHYTIMER(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3098 | { \ |
| 3099 | .freq_hz = f, \ |
| 3100 | .src_clk = &s##_clk.c, \ |
| 3101 | .md_val = MD8(8, m, 0, n), \ |
| 3102 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 3103 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3104 | } |
| 3105 | static struct clk_freq_tbl clk_tbl_csi_phytimer[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3106 | F_CSI_PHYTIMER( 0, gnd, 1, 0, 0), |
| 3107 | F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9), |
| 3108 | F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3109 | F_END |
| 3110 | }; |
| 3111 | |
| 3112 | static struct rcg_clk csiphy_timer_src_clk = { |
| 3113 | .ns_reg = CSIPHYTIMER_NS_REG, |
| 3114 | .b = { |
| 3115 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3116 | .halt_check = NOCHECK, |
| 3117 | }, |
| 3118 | .md_reg = CSIPHYTIMER_MD_REG, |
| 3119 | .root_en_mask = BIT(2), |
| 3120 | .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 3121 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3122 | .ctl_mask = BM(7, 6), |
| 3123 | .set_rate = set_rate_mnd_8, |
| 3124 | .freq_tbl = clk_tbl_csi_phytimer, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3125 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3126 | .c = { |
| 3127 | .dbg_name = "csiphy_timer_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3128 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3129 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3130 | CLK_INIT(csiphy_timer_src_clk.c), |
| 3131 | }, |
| 3132 | }; |
| 3133 | |
| 3134 | static struct branch_clk csi0phy_timer_clk = { |
| 3135 | .b = { |
| 3136 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3137 | .en_mask = BIT(0), |
| 3138 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3139 | .halt_bit = 17, |
| 3140 | }, |
| 3141 | .parent = &csiphy_timer_src_clk.c, |
| 3142 | .c = { |
| 3143 | .dbg_name = "csi0phy_timer_clk", |
| 3144 | .ops = &clk_ops_branch, |
| 3145 | CLK_INIT(csi0phy_timer_clk.c), |
| 3146 | }, |
| 3147 | }; |
| 3148 | |
| 3149 | static struct branch_clk csi1phy_timer_clk = { |
| 3150 | .b = { |
| 3151 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3152 | .en_mask = BIT(9), |
| 3153 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3154 | .halt_bit = 18, |
| 3155 | }, |
| 3156 | .parent = &csiphy_timer_src_clk.c, |
| 3157 | .c = { |
| 3158 | .dbg_name = "csi1phy_timer_clk", |
| 3159 | .ops = &clk_ops_branch, |
| 3160 | CLK_INIT(csi1phy_timer_clk.c), |
| 3161 | }, |
| 3162 | }; |
| 3163 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3164 | static struct branch_clk csi2phy_timer_clk = { |
| 3165 | .b = { |
| 3166 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3167 | .en_mask = BIT(11), |
| 3168 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3169 | .halt_bit = 30, |
| 3170 | }, |
| 3171 | .parent = &csiphy_timer_src_clk.c, |
| 3172 | .c = { |
| 3173 | .dbg_name = "csi2phy_timer_clk", |
| 3174 | .ops = &clk_ops_branch, |
| 3175 | CLK_INIT(csi2phy_timer_clk.c), |
| 3176 | }, |
| 3177 | }; |
| 3178 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3179 | #define F_DSI(d) \ |
| 3180 | { \ |
| 3181 | .freq_hz = d, \ |
| 3182 | .ns_val = BVAL(15, 12, (d-1)), \ |
| 3183 | } |
| 3184 | /* |
| 3185 | * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate |
| 3186 | * without this clock driver knowing. So, overload the clk_set_rate() to set |
| 3187 | * the divider (1 to 16) of the clock with respect to the PLL rate. |
| 3188 | */ |
| 3189 | static struct clk_freq_tbl clk_tbl_dsi_byte[] = { |
| 3190 | F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4), |
| 3191 | F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8), |
| 3192 | F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12), |
| 3193 | F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16), |
| 3194 | F_END |
| 3195 | }; |
| 3196 | |
| 3197 | static struct rcg_clk dsi1_byte_clk = { |
| 3198 | .b = { |
| 3199 | .ctl_reg = DSI1_BYTE_CC_REG, |
| 3200 | .en_mask = BIT(0), |
| 3201 | .reset_reg = SW_RESET_CORE_REG, |
| 3202 | .reset_mask = BIT(7), |
| 3203 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3204 | .halt_bit = 21, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3205 | .retain_reg = DSI1_BYTE_CC_REG, |
| 3206 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3207 | }, |
| 3208 | .ns_reg = DSI1_BYTE_NS_REG, |
| 3209 | .root_en_mask = BIT(2), |
| 3210 | .ns_mask = BM(15, 12), |
| 3211 | .set_rate = set_rate_nop, |
| 3212 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3213 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3214 | .c = { |
| 3215 | .dbg_name = "dsi1_byte_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3216 | .ops = &clk_ops_rcg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3217 | CLK_INIT(dsi1_byte_clk.c), |
| 3218 | }, |
| 3219 | }; |
| 3220 | |
| 3221 | static struct rcg_clk dsi2_byte_clk = { |
| 3222 | .b = { |
| 3223 | .ctl_reg = DSI2_BYTE_CC_REG, |
| 3224 | .en_mask = BIT(0), |
| 3225 | .reset_reg = SW_RESET_CORE_REG, |
| 3226 | .reset_mask = BIT(25), |
| 3227 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3228 | .halt_bit = 20, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3229 | .retain_reg = DSI2_BYTE_CC_REG, |
| 3230 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3231 | }, |
| 3232 | .ns_reg = DSI2_BYTE_NS_REG, |
| 3233 | .root_en_mask = BIT(2), |
| 3234 | .ns_mask = BM(15, 12), |
| 3235 | .set_rate = set_rate_nop, |
| 3236 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3237 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3238 | .c = { |
| 3239 | .dbg_name = "dsi2_byte_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3240 | .ops = &clk_ops_rcg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3241 | CLK_INIT(dsi2_byte_clk.c), |
| 3242 | }, |
| 3243 | }; |
| 3244 | |
| 3245 | static struct rcg_clk dsi1_esc_clk = { |
| 3246 | .b = { |
| 3247 | .ctl_reg = DSI1_ESC_CC_REG, |
| 3248 | .en_mask = BIT(0), |
| 3249 | .reset_reg = SW_RESET_CORE_REG, |
| 3250 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3251 | .halt_bit = 1, |
| 3252 | }, |
| 3253 | .ns_reg = DSI1_ESC_NS_REG, |
| 3254 | .root_en_mask = BIT(2), |
| 3255 | .ns_mask = BM(15, 12), |
| 3256 | .set_rate = set_rate_nop, |
| 3257 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3258 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3259 | .c = { |
| 3260 | .dbg_name = "dsi1_esc_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3261 | .ops = &clk_ops_rcg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3262 | CLK_INIT(dsi1_esc_clk.c), |
| 3263 | }, |
| 3264 | }; |
| 3265 | |
| 3266 | static struct rcg_clk dsi2_esc_clk = { |
| 3267 | .b = { |
| 3268 | .ctl_reg = DSI2_ESC_CC_REG, |
| 3269 | .en_mask = BIT(0), |
| 3270 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3271 | .halt_bit = 3, |
| 3272 | }, |
| 3273 | .ns_reg = DSI2_ESC_NS_REG, |
| 3274 | .root_en_mask = BIT(2), |
| 3275 | .ns_mask = BM(15, 12), |
| 3276 | .set_rate = set_rate_nop, |
| 3277 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3278 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3279 | .c = { |
| 3280 | .dbg_name = "dsi2_esc_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3281 | .ops = &clk_ops_rcg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3282 | CLK_INIT(dsi2_esc_clk.c), |
| 3283 | }, |
| 3284 | }; |
| 3285 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3286 | #define F_GFX2D(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3287 | { \ |
| 3288 | .freq_hz = f, \ |
| 3289 | .src_clk = &s##_clk.c, \ |
| 3290 | .md_val = MD4(4, m, 0, n), \ |
| 3291 | .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \ |
| 3292 | .ctl_val = CC_BANKED(9, 6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3293 | } |
| 3294 | static struct clk_freq_tbl clk_tbl_gfx2d[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3295 | F_GFX2D( 0, gnd, 0, 0), |
| 3296 | F_GFX2D( 27000000, pxo, 0, 0), |
| 3297 | F_GFX2D( 48000000, pll8, 1, 8), |
| 3298 | F_GFX2D( 54857000, pll8, 1, 7), |
| 3299 | F_GFX2D( 64000000, pll8, 1, 6), |
| 3300 | F_GFX2D( 76800000, pll8, 1, 5), |
| 3301 | F_GFX2D( 96000000, pll8, 1, 4), |
| 3302 | F_GFX2D(128000000, pll8, 1, 3), |
| 3303 | F_GFX2D(145455000, pll2, 2, 11), |
| 3304 | F_GFX2D(160000000, pll2, 1, 5), |
| 3305 | F_GFX2D(177778000, pll2, 2, 9), |
| 3306 | F_GFX2D(200000000, pll2, 1, 4), |
| 3307 | F_GFX2D(228571000, pll2, 2, 7), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3308 | F_END |
| 3309 | }; |
| 3310 | |
| 3311 | static struct bank_masks bmnd_info_gfx2d0 = { |
| 3312 | .bank_sel_mask = BIT(11), |
| 3313 | .bank0_mask = { |
| 3314 | .md_reg = GFX2D0_MD0_REG, |
| 3315 | .ns_mask = BM(23, 20) | BM(5, 3), |
| 3316 | .rst_mask = BIT(25), |
| 3317 | .mnd_en_mask = BIT(8), |
| 3318 | .mode_mask = BM(10, 9), |
| 3319 | }, |
| 3320 | .bank1_mask = { |
| 3321 | .md_reg = GFX2D0_MD1_REG, |
| 3322 | .ns_mask = BM(19, 16) | BM(2, 0), |
| 3323 | .rst_mask = BIT(24), |
| 3324 | .mnd_en_mask = BIT(5), |
| 3325 | .mode_mask = BM(7, 6), |
| 3326 | }, |
| 3327 | }; |
| 3328 | |
| 3329 | static struct rcg_clk gfx2d0_clk = { |
| 3330 | .b = { |
| 3331 | .ctl_reg = GFX2D0_CC_REG, |
| 3332 | .en_mask = BIT(0), |
| 3333 | .reset_reg = SW_RESET_CORE_REG, |
| 3334 | .reset_mask = BIT(14), |
| 3335 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3336 | .halt_bit = 9, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3337 | .retain_reg = GFX2D0_CC_REG, |
| 3338 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3339 | }, |
| 3340 | .ns_reg = GFX2D0_NS_REG, |
| 3341 | .root_en_mask = BIT(2), |
| 3342 | .set_rate = set_rate_mnd_banked, |
| 3343 | .freq_tbl = clk_tbl_gfx2d, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3344 | .bank_info = &bmnd_info_gfx2d0, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3345 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3346 | .c = { |
| 3347 | .dbg_name = "gfx2d0_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3348 | .ops = &clk_ops_rcg, |
Matt Wagantall | 158f73b | 2012-05-16 11:29:35 -0700 | [diff] [blame] | 3349 | .flags = CLKFLAG_SKIP_HANDOFF, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3350 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 3351 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3352 | CLK_INIT(gfx2d0_clk.c), |
| 3353 | }, |
| 3354 | }; |
| 3355 | |
| 3356 | static struct bank_masks bmnd_info_gfx2d1 = { |
| 3357 | .bank_sel_mask = BIT(11), |
| 3358 | .bank0_mask = { |
| 3359 | .md_reg = GFX2D1_MD0_REG, |
| 3360 | .ns_mask = BM(23, 20) | BM(5, 3), |
| 3361 | .rst_mask = BIT(25), |
| 3362 | .mnd_en_mask = BIT(8), |
| 3363 | .mode_mask = BM(10, 9), |
| 3364 | }, |
| 3365 | .bank1_mask = { |
| 3366 | .md_reg = GFX2D1_MD1_REG, |
| 3367 | .ns_mask = BM(19, 16) | BM(2, 0), |
| 3368 | .rst_mask = BIT(24), |
| 3369 | .mnd_en_mask = BIT(5), |
| 3370 | .mode_mask = BM(7, 6), |
| 3371 | }, |
| 3372 | }; |
| 3373 | |
| 3374 | static struct rcg_clk gfx2d1_clk = { |
| 3375 | .b = { |
| 3376 | .ctl_reg = GFX2D1_CC_REG, |
| 3377 | .en_mask = BIT(0), |
| 3378 | .reset_reg = SW_RESET_CORE_REG, |
| 3379 | .reset_mask = BIT(13), |
| 3380 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3381 | .halt_bit = 14, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3382 | .retain_reg = GFX2D1_CC_REG, |
| 3383 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3384 | }, |
| 3385 | .ns_reg = GFX2D1_NS_REG, |
| 3386 | .root_en_mask = BIT(2), |
| 3387 | .set_rate = set_rate_mnd_banked, |
| 3388 | .freq_tbl = clk_tbl_gfx2d, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3389 | .bank_info = &bmnd_info_gfx2d1, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3390 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3391 | .c = { |
| 3392 | .dbg_name = "gfx2d1_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3393 | .ops = &clk_ops_rcg, |
Matt Wagantall | 158f73b | 2012-05-16 11:29:35 -0700 | [diff] [blame] | 3394 | .flags = CLKFLAG_SKIP_HANDOFF, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3395 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 3396 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3397 | CLK_INIT(gfx2d1_clk.c), |
| 3398 | }, |
| 3399 | }; |
| 3400 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3401 | #define F_GFX3D(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3402 | { \ |
| 3403 | .freq_hz = f, \ |
| 3404 | .src_clk = &s##_clk.c, \ |
| 3405 | .md_val = MD4(4, m, 0, n), \ |
| 3406 | .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3407 | .ctl_val = CC_BANKED(9, 6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3408 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3409 | |
| 3410 | static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3411 | F_GFX3D( 0, gnd, 0, 0), |
| 3412 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3413 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3414 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3415 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3416 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3417 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3418 | F_GFX3D(128000000, pll8, 1, 3), |
| 3419 | F_GFX3D(145455000, pll2, 2, 11), |
| 3420 | F_GFX3D(160000000, pll2, 1, 5), |
| 3421 | F_GFX3D(177778000, pll2, 2, 9), |
| 3422 | F_GFX3D(200000000, pll2, 1, 4), |
| 3423 | F_GFX3D(228571000, pll2, 2, 7), |
| 3424 | F_GFX3D(266667000, pll2, 1, 3), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3425 | F_GFX3D(300000000, pll3, 1, 4), |
| 3426 | F_GFX3D(320000000, pll2, 2, 5), |
| 3427 | F_GFX3D(400000000, pll2, 1, 2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3428 | F_END |
| 3429 | }; |
| 3430 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3431 | static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3432 | F_GFX3D( 0, gnd, 0, 0), |
| 3433 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3434 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3435 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3436 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3437 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3438 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3439 | F_GFX3D(128000000, pll8, 1, 3), |
| 3440 | F_GFX3D(145455000, pll2, 2, 11), |
| 3441 | F_GFX3D(160000000, pll2, 1, 5), |
| 3442 | F_GFX3D(177778000, pll2, 2, 9), |
| 3443 | F_GFX3D(200000000, pll2, 1, 4), |
| 3444 | F_GFX3D(228571000, pll2, 2, 7), |
| 3445 | F_GFX3D(266667000, pll2, 1, 3), |
Tianyi Gou | 0c50fe3 | 2011-10-19 15:50:35 -0700 | [diff] [blame] | 3446 | F_GFX3D(325000000, pll15, 1, 3), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3447 | F_GFX3D(400000000, pll2, 1, 2), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3448 | F_END |
| 3449 | }; |
| 3450 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3451 | static struct clk_freq_tbl clk_tbl_gfx3d_8930[] = { |
| 3452 | F_GFX3D( 0, gnd, 0, 0), |
| 3453 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3454 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3455 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3456 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3457 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3458 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3459 | F_GFX3D(128000000, pll8, 1, 3), |
| 3460 | F_GFX3D(145455000, pll2, 2, 11), |
| 3461 | F_GFX3D(160000000, pll2, 1, 5), |
| 3462 | F_GFX3D(177778000, pll2, 2, 9), |
Tianyi Gou | 4d33c9c | 2012-03-30 11:10:15 -0700 | [diff] [blame] | 3463 | F_GFX3D(192000000, pll8, 1, 2), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3464 | F_GFX3D(200000000, pll2, 1, 4), |
| 3465 | F_GFX3D(228571000, pll2, 2, 7), |
| 3466 | F_GFX3D(266667000, pll2, 1, 3), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3467 | F_GFX3D(320000000, pll2, 2, 5), |
| 3468 | F_GFX3D(400000000, pll2, 1, 2), |
| 3469 | F_GFX3D(450000000, pll15, 1, 2), |
| 3470 | F_END |
| 3471 | }; |
| 3472 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3473 | static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = { |
| 3474 | [VDD_DIG_LOW] = 128000000, |
| 3475 | [VDD_DIG_NOMINAL] = 325000000, |
| 3476 | [VDD_DIG_HIGH] = 400000000 |
| 3477 | }; |
| 3478 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3479 | static unsigned long fmax_gfx3d_8930[MAX_VDD_LEVELS] __initdata = { |
Tianyi Gou | 4d33c9c | 2012-03-30 11:10:15 -0700 | [diff] [blame] | 3480 | [VDD_DIG_LOW] = 192000000, |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3481 | [VDD_DIG_NOMINAL] = 320000000, |
| 3482 | [VDD_DIG_HIGH] = 450000000 |
| 3483 | }; |
| 3484 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3485 | static struct bank_masks bmnd_info_gfx3d = { |
| 3486 | .bank_sel_mask = BIT(11), |
| 3487 | .bank0_mask = { |
| 3488 | .md_reg = GFX3D_MD0_REG, |
| 3489 | .ns_mask = BM(21, 18) | BM(5, 3), |
| 3490 | .rst_mask = BIT(23), |
| 3491 | .mnd_en_mask = BIT(8), |
| 3492 | .mode_mask = BM(10, 9), |
| 3493 | }, |
| 3494 | .bank1_mask = { |
| 3495 | .md_reg = GFX3D_MD1_REG, |
| 3496 | .ns_mask = BM(17, 14) | BM(2, 0), |
| 3497 | .rst_mask = BIT(22), |
| 3498 | .mnd_en_mask = BIT(5), |
| 3499 | .mode_mask = BM(7, 6), |
| 3500 | }, |
| 3501 | }; |
| 3502 | |
| 3503 | static struct rcg_clk gfx3d_clk = { |
| 3504 | .b = { |
| 3505 | .ctl_reg = GFX3D_CC_REG, |
| 3506 | .en_mask = BIT(0), |
| 3507 | .reset_reg = SW_RESET_CORE_REG, |
| 3508 | .reset_mask = BIT(12), |
| 3509 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3510 | .halt_bit = 4, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3511 | .retain_reg = GFX3D_CC_REG, |
| 3512 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3513 | }, |
| 3514 | .ns_reg = GFX3D_NS_REG, |
| 3515 | .root_en_mask = BIT(2), |
| 3516 | .set_rate = set_rate_mnd_banked, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3517 | .freq_tbl = clk_tbl_gfx3d_8960, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3518 | .bank_info = &bmnd_info_gfx3d, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3519 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3520 | .c = { |
| 3521 | .dbg_name = "gfx3d_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3522 | .ops = &clk_ops_rcg, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 3523 | VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000, |
| 3524 | HIGH, 400000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3525 | CLK_INIT(gfx3d_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3526 | .depends = &gmem_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3527 | }, |
| 3528 | }; |
| 3529 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3530 | #define F_VCAP(f, s, m, n) \ |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3531 | { \ |
| 3532 | .freq_hz = f, \ |
| 3533 | .src_clk = &s##_clk.c, \ |
| 3534 | .md_val = MD4(4, m, 0, n), \ |
| 3535 | .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3536 | .ctl_val = CC_BANKED(9, 6, n), \ |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3537 | } |
| 3538 | |
| 3539 | static struct clk_freq_tbl clk_tbl_vcap[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3540 | F_VCAP( 0, gnd, 0, 0), |
| 3541 | F_VCAP( 27000000, pxo, 0, 0), |
| 3542 | F_VCAP( 54860000, pll8, 1, 7), |
| 3543 | F_VCAP( 64000000, pll8, 1, 6), |
| 3544 | F_VCAP( 76800000, pll8, 1, 5), |
| 3545 | F_VCAP(128000000, pll8, 1, 3), |
| 3546 | F_VCAP(160000000, pll2, 1, 5), |
| 3547 | F_VCAP(200000000, pll2, 1, 4), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3548 | F_END |
| 3549 | }; |
| 3550 | |
| 3551 | static struct bank_masks bmnd_info_vcap = { |
| 3552 | .bank_sel_mask = BIT(11), |
| 3553 | .bank0_mask = { |
| 3554 | .md_reg = VCAP_MD0_REG, |
| 3555 | .ns_mask = BM(21, 18) | BM(5, 3), |
| 3556 | .rst_mask = BIT(23), |
| 3557 | .mnd_en_mask = BIT(8), |
| 3558 | .mode_mask = BM(10, 9), |
| 3559 | }, |
| 3560 | .bank1_mask = { |
| 3561 | .md_reg = VCAP_MD1_REG, |
| 3562 | .ns_mask = BM(17, 14) | BM(2, 0), |
| 3563 | .rst_mask = BIT(22), |
| 3564 | .mnd_en_mask = BIT(5), |
| 3565 | .mode_mask = BM(7, 6), |
| 3566 | }, |
| 3567 | }; |
| 3568 | |
| 3569 | static struct rcg_clk vcap_clk = { |
| 3570 | .b = { |
| 3571 | .ctl_reg = VCAP_CC_REG, |
| 3572 | .en_mask = BIT(0), |
| 3573 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 3574 | .halt_bit = 15, |
| 3575 | }, |
| 3576 | .ns_reg = VCAP_NS_REG, |
| 3577 | .root_en_mask = BIT(2), |
| 3578 | .set_rate = set_rate_mnd_banked, |
| 3579 | .freq_tbl = clk_tbl_vcap, |
| 3580 | .bank_info = &bmnd_info_vcap, |
| 3581 | .current_freq = &rcg_dummy_freq, |
| 3582 | .c = { |
| 3583 | .dbg_name = "vcap_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3584 | .ops = &clk_ops_rcg, |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3585 | .depends = &vcap_axi_clk.c, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3586 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3587 | CLK_INIT(vcap_clk.c), |
| 3588 | }, |
| 3589 | }; |
| 3590 | |
| 3591 | static struct branch_clk vcap_npl_clk = { |
| 3592 | .b = { |
| 3593 | .ctl_reg = VCAP_CC_REG, |
| 3594 | .en_mask = BIT(13), |
| 3595 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 3596 | .halt_bit = 25, |
| 3597 | }, |
| 3598 | .parent = &vcap_clk.c, |
| 3599 | .c = { |
| 3600 | .dbg_name = "vcap_npl_clk", |
| 3601 | .ops = &clk_ops_branch, |
| 3602 | CLK_INIT(vcap_npl_clk.c), |
| 3603 | }, |
| 3604 | }; |
| 3605 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3606 | #define F_IJPEG(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3607 | { \ |
| 3608 | .freq_hz = f, \ |
| 3609 | .src_clk = &s##_clk.c, \ |
| 3610 | .md_val = MD8(8, m, 0, n), \ |
| 3611 | .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \ |
| 3612 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3613 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3614 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3615 | static struct clk_freq_tbl clk_tbl_ijpeg[] = { |
| 3616 | F_IJPEG( 0, gnd, 1, 0, 0), |
| 3617 | F_IJPEG( 27000000, pxo, 1, 0, 0), |
| 3618 | F_IJPEG( 36570000, pll8, 1, 2, 21), |
| 3619 | F_IJPEG( 54860000, pll8, 7, 0, 0), |
| 3620 | F_IJPEG( 96000000, pll8, 4, 0, 0), |
| 3621 | F_IJPEG(109710000, pll8, 1, 2, 7), |
| 3622 | F_IJPEG(128000000, pll8, 3, 0, 0), |
| 3623 | F_IJPEG(153600000, pll8, 1, 2, 5), |
| 3624 | F_IJPEG(200000000, pll2, 4, 0, 0), |
| 3625 | F_IJPEG(228571000, pll2, 1, 2, 7), |
| 3626 | F_IJPEG(266667000, pll2, 1, 1, 3), |
| 3627 | F_IJPEG(320000000, pll2, 1, 2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3628 | F_END |
| 3629 | }; |
| 3630 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3631 | static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = { |
| 3632 | [VDD_DIG_LOW] = 128000000, |
| 3633 | [VDD_DIG_NOMINAL] = 266667000, |
| 3634 | [VDD_DIG_HIGH] = 320000000 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3635 | }; |
| 3636 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3637 | static struct rcg_clk ijpeg_clk = { |
| 3638 | .b = { |
| 3639 | .ctl_reg = IJPEG_CC_REG, |
| 3640 | .en_mask = BIT(0), |
| 3641 | .reset_reg = SW_RESET_CORE_REG, |
| 3642 | .reset_mask = BIT(9), |
| 3643 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3644 | .halt_bit = 24, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3645 | .retain_reg = IJPEG_CC_REG, |
| 3646 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3647 | }, |
| 3648 | .ns_reg = IJPEG_NS_REG, |
| 3649 | .md_reg = IJPEG_MD_REG, |
| 3650 | .root_en_mask = BIT(2), |
| 3651 | .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 3652 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3653 | .ctl_mask = BM(7, 6), |
| 3654 | .set_rate = set_rate_mnd, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3655 | .freq_tbl = clk_tbl_ijpeg, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3656 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3657 | .c = { |
| 3658 | .dbg_name = "ijpeg_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3659 | .ops = &clk_ops_rcg, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 3660 | VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000, |
| 3661 | HIGH, 320000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3662 | CLK_INIT(ijpeg_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3663 | .depends = &ijpeg_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3664 | }, |
| 3665 | }; |
| 3666 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3667 | #define F_JPEGD(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3668 | { \ |
| 3669 | .freq_hz = f, \ |
| 3670 | .src_clk = &s##_clk.c, \ |
| 3671 | .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3672 | } |
| 3673 | static struct clk_freq_tbl clk_tbl_jpegd[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3674 | F_JPEGD( 0, gnd, 1), |
| 3675 | F_JPEGD( 64000000, pll8, 6), |
| 3676 | F_JPEGD( 76800000, pll8, 5), |
| 3677 | F_JPEGD( 96000000, pll8, 4), |
| 3678 | F_JPEGD(160000000, pll2, 5), |
| 3679 | F_JPEGD(200000000, pll2, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3680 | F_END |
| 3681 | }; |
| 3682 | |
| 3683 | static struct rcg_clk jpegd_clk = { |
| 3684 | .b = { |
| 3685 | .ctl_reg = JPEGD_CC_REG, |
| 3686 | .en_mask = BIT(0), |
| 3687 | .reset_reg = SW_RESET_CORE_REG, |
| 3688 | .reset_mask = BIT(19), |
| 3689 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3690 | .halt_bit = 19, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3691 | .retain_reg = JPEGD_CC_REG, |
| 3692 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3693 | }, |
| 3694 | .ns_reg = JPEGD_NS_REG, |
| 3695 | .root_en_mask = BIT(2), |
| 3696 | .ns_mask = (BM(15, 12) | BM(2, 0)), |
| 3697 | .set_rate = set_rate_nop, |
| 3698 | .freq_tbl = clk_tbl_jpegd, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3699 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3700 | .c = { |
| 3701 | .dbg_name = "jpegd_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3702 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3703 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3704 | CLK_INIT(jpegd_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3705 | .depends = &jpegd_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3706 | }, |
| 3707 | }; |
| 3708 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3709 | #define F_MDP(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3710 | { \ |
| 3711 | .freq_hz = f, \ |
| 3712 | .src_clk = &s##_clk.c, \ |
| 3713 | .md_val = MD8(8, m, 0, n), \ |
| 3714 | .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3715 | .ctl_val = CC_BANKED(9, 6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3716 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3717 | static struct clk_freq_tbl clk_tbl_mdp[] = { |
| 3718 | F_MDP( 0, gnd, 0, 0), |
| 3719 | F_MDP( 9600000, pll8, 1, 40), |
| 3720 | F_MDP( 13710000, pll8, 1, 28), |
| 3721 | F_MDP( 27000000, pxo, 0, 0), |
| 3722 | F_MDP( 29540000, pll8, 1, 13), |
| 3723 | F_MDP( 34910000, pll8, 1, 11), |
| 3724 | F_MDP( 38400000, pll8, 1, 10), |
| 3725 | F_MDP( 59080000, pll8, 2, 13), |
| 3726 | F_MDP( 76800000, pll8, 1, 5), |
| 3727 | F_MDP( 85330000, pll8, 2, 9), |
| 3728 | F_MDP( 96000000, pll8, 1, 4), |
| 3729 | F_MDP(128000000, pll8, 1, 3), |
| 3730 | F_MDP(160000000, pll2, 1, 5), |
| 3731 | F_MDP(177780000, pll2, 2, 9), |
| 3732 | F_MDP(200000000, pll2, 1, 4), |
| 3733 | F_MDP(266667000, pll2, 1, 3), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3734 | F_END |
| 3735 | }; |
| 3736 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3737 | static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = { |
| 3738 | [VDD_DIG_LOW] = 128000000, |
| 3739 | [VDD_DIG_NOMINAL] = 266667000 |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3740 | }; |
| 3741 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3742 | static struct bank_masks bmnd_info_mdp = { |
| 3743 | .bank_sel_mask = BIT(11), |
| 3744 | .bank0_mask = { |
| 3745 | .md_reg = MDP_MD0_REG, |
| 3746 | .ns_mask = BM(29, 22) | BM(5, 3), |
| 3747 | .rst_mask = BIT(31), |
| 3748 | .mnd_en_mask = BIT(8), |
| 3749 | .mode_mask = BM(10, 9), |
| 3750 | }, |
| 3751 | .bank1_mask = { |
| 3752 | .md_reg = MDP_MD1_REG, |
| 3753 | .ns_mask = BM(21, 14) | BM(2, 0), |
| 3754 | .rst_mask = BIT(30), |
| 3755 | .mnd_en_mask = BIT(5), |
| 3756 | .mode_mask = BM(7, 6), |
| 3757 | }, |
| 3758 | }; |
| 3759 | |
| 3760 | static struct rcg_clk mdp_clk = { |
| 3761 | .b = { |
| 3762 | .ctl_reg = MDP_CC_REG, |
| 3763 | .en_mask = BIT(0), |
| 3764 | .reset_reg = SW_RESET_CORE_REG, |
| 3765 | .reset_mask = BIT(21), |
| 3766 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 3767 | .halt_bit = 10, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3768 | .retain_reg = MDP_CC_REG, |
| 3769 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3770 | }, |
| 3771 | .ns_reg = MDP_NS_REG, |
| 3772 | .root_en_mask = BIT(2), |
| 3773 | .set_rate = set_rate_mnd_banked, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3774 | .freq_tbl = clk_tbl_mdp, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3775 | .bank_info = &bmnd_info_mdp, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3776 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3777 | .c = { |
| 3778 | .dbg_name = "mdp_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3779 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3780 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3781 | CLK_INIT(mdp_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3782 | .depends = &mdp_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3783 | }, |
| 3784 | }; |
| 3785 | |
| 3786 | static struct branch_clk lut_mdp_clk = { |
| 3787 | .b = { |
| 3788 | .ctl_reg = MDP_LUT_CC_REG, |
| 3789 | .en_mask = BIT(0), |
| 3790 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3791 | .halt_bit = 13, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3792 | .retain_reg = MDP_LUT_CC_REG, |
| 3793 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3794 | }, |
| 3795 | .parent = &mdp_clk.c, |
| 3796 | .c = { |
| 3797 | .dbg_name = "lut_mdp_clk", |
| 3798 | .ops = &clk_ops_branch, |
| 3799 | CLK_INIT(lut_mdp_clk.c), |
| 3800 | }, |
| 3801 | }; |
| 3802 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3803 | #define F_MDP_VSYNC(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3804 | { \ |
| 3805 | .freq_hz = f, \ |
| 3806 | .src_clk = &s##_clk.c, \ |
| 3807 | .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3808 | } |
| 3809 | static struct clk_freq_tbl clk_tbl_mdp_vsync[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3810 | F_MDP_VSYNC(27000000, pxo), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3811 | F_END |
| 3812 | }; |
| 3813 | |
| 3814 | static struct rcg_clk mdp_vsync_clk = { |
| 3815 | .b = { |
| 3816 | .ctl_reg = MISC_CC_REG, |
| 3817 | .en_mask = BIT(6), |
| 3818 | .reset_reg = SW_RESET_CORE_REG, |
| 3819 | .reset_mask = BIT(3), |
| 3820 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3821 | .halt_bit = 22, |
| 3822 | }, |
| 3823 | .ns_reg = MISC_CC2_REG, |
| 3824 | .ns_mask = BIT(13), |
| 3825 | .set_rate = set_rate_nop, |
| 3826 | .freq_tbl = clk_tbl_mdp_vsync, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3827 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3828 | .c = { |
| 3829 | .dbg_name = "mdp_vsync_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3830 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3831 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3832 | CLK_INIT(mdp_vsync_clk.c), |
| 3833 | }, |
| 3834 | }; |
| 3835 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3836 | #define F_ROT(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3837 | { \ |
| 3838 | .freq_hz = f, \ |
| 3839 | .src_clk = &s##_clk.c, \ |
| 3840 | .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \ |
| 3841 | 21, 19, 18, 16, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3842 | } |
| 3843 | static struct clk_freq_tbl clk_tbl_rot[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3844 | F_ROT( 0, gnd, 1), |
| 3845 | F_ROT( 27000000, pxo, 1), |
| 3846 | F_ROT( 29540000, pll8, 13), |
| 3847 | F_ROT( 32000000, pll8, 12), |
| 3848 | F_ROT( 38400000, pll8, 10), |
| 3849 | F_ROT( 48000000, pll8, 8), |
| 3850 | F_ROT( 54860000, pll8, 7), |
| 3851 | F_ROT( 64000000, pll8, 6), |
| 3852 | F_ROT( 76800000, pll8, 5), |
| 3853 | F_ROT( 96000000, pll8, 4), |
| 3854 | F_ROT(100000000, pll2, 8), |
| 3855 | F_ROT(114290000, pll2, 7), |
| 3856 | F_ROT(133330000, pll2, 6), |
| 3857 | F_ROT(160000000, pll2, 5), |
| 3858 | F_ROT(200000000, pll2, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3859 | F_END |
| 3860 | }; |
| 3861 | |
| 3862 | static struct bank_masks bdiv_info_rot = { |
| 3863 | .bank_sel_mask = BIT(30), |
| 3864 | .bank0_mask = { |
| 3865 | .ns_mask = BM(25, 22) | BM(18, 16), |
| 3866 | }, |
| 3867 | .bank1_mask = { |
| 3868 | .ns_mask = BM(29, 26) | BM(21, 19), |
| 3869 | }, |
| 3870 | }; |
| 3871 | |
| 3872 | static struct rcg_clk rot_clk = { |
| 3873 | .b = { |
| 3874 | .ctl_reg = ROT_CC_REG, |
| 3875 | .en_mask = BIT(0), |
| 3876 | .reset_reg = SW_RESET_CORE_REG, |
| 3877 | .reset_mask = BIT(2), |
| 3878 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 3879 | .halt_bit = 15, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3880 | .retain_reg = ROT_CC_REG, |
| 3881 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3882 | }, |
| 3883 | .ns_reg = ROT_NS_REG, |
| 3884 | .root_en_mask = BIT(2), |
| 3885 | .set_rate = set_rate_div_banked, |
| 3886 | .freq_tbl = clk_tbl_rot, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3887 | .bank_info = &bdiv_info_rot, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3888 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3889 | .c = { |
| 3890 | .dbg_name = "rot_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3891 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3892 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3893 | CLK_INIT(rot_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3894 | .depends = &rot_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3895 | }, |
| 3896 | }; |
| 3897 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3898 | static int hdmi_pll_clk_enable(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3899 | { |
| 3900 | int ret; |
| 3901 | unsigned long flags; |
| 3902 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 3903 | ret = hdmi_pll_enable(); |
| 3904 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 3905 | return ret; |
| 3906 | } |
| 3907 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3908 | static void hdmi_pll_clk_disable(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3909 | { |
| 3910 | unsigned long flags; |
| 3911 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 3912 | hdmi_pll_disable(); |
| 3913 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 3914 | } |
| 3915 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3916 | static unsigned long hdmi_pll_clk_get_rate(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3917 | { |
| 3918 | return hdmi_pll_get_rate(); |
| 3919 | } |
| 3920 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3921 | static struct clk *hdmi_pll_clk_get_parent(struct clk *c) |
Stephen Boyd | 5b35dee | 2011-09-21 12:17:38 -0700 | [diff] [blame] | 3922 | { |
| 3923 | return &pxo_clk.c; |
| 3924 | } |
| 3925 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3926 | static struct clk_ops clk_ops_hdmi_pll = { |
| 3927 | .enable = hdmi_pll_clk_enable, |
| 3928 | .disable = hdmi_pll_clk_disable, |
| 3929 | .get_rate = hdmi_pll_clk_get_rate, |
Stephen Boyd | 5b35dee | 2011-09-21 12:17:38 -0700 | [diff] [blame] | 3930 | .get_parent = hdmi_pll_clk_get_parent, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3931 | }; |
| 3932 | |
| 3933 | static struct clk hdmi_pll_clk = { |
| 3934 | .dbg_name = "hdmi_pll_clk", |
| 3935 | .ops = &clk_ops_hdmi_pll, |
| 3936 | CLK_INIT(hdmi_pll_clk), |
| 3937 | }; |
| 3938 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3939 | #define F_TV_GND(f, s, p_r, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3940 | { \ |
| 3941 | .freq_hz = f, \ |
| 3942 | .src_clk = &s##_clk.c, \ |
| 3943 | .md_val = MD8(8, m, 0, n), \ |
| 3944 | .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 3945 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3946 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3947 | #define F_TV(f, s, p_r, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3948 | { \ |
| 3949 | .freq_hz = f, \ |
| 3950 | .src_clk = &s##_clk, \ |
| 3951 | .md_val = MD8(8, m, 0, n), \ |
| 3952 | .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 3953 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3954 | .extra_freq_data = (void *)p_r, \ |
| 3955 | } |
| 3956 | /* Switching TV freqs requires PLL reconfiguration. */ |
| 3957 | static struct clk_freq_tbl clk_tbl_tv[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3958 | F_TV_GND( 0, gnd, 0, 1, 0, 0), |
| 3959 | F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0), |
| 3960 | F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0), |
| 3961 | F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0), |
| 3962 | F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0), |
| 3963 | F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3964 | F_END |
| 3965 | }; |
| 3966 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3967 | static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = { |
| 3968 | [VDD_DIG_LOW] = 74250000, |
| 3969 | [VDD_DIG_NOMINAL] = 149000000 |
| 3970 | }; |
| 3971 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3972 | /* |
| 3973 | * Unlike other clocks, the TV rate is adjusted through PLL |
| 3974 | * re-programming. It is also routed through an MND divider. |
| 3975 | */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3976 | void set_rate_tv(struct rcg_clk *rcg, struct clk_freq_tbl *nf) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3977 | { |
| 3978 | unsigned long pll_rate = (unsigned long)nf->extra_freq_data; |
| 3979 | if (pll_rate) |
| 3980 | hdmi_pll_set_rate(pll_rate); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3981 | set_rate_mnd(rcg, nf); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3982 | } |
| 3983 | |
| 3984 | static struct rcg_clk tv_src_clk = { |
| 3985 | .ns_reg = TV_NS_REG, |
| 3986 | .b = { |
| 3987 | .ctl_reg = TV_CC_REG, |
| 3988 | .halt_check = NOCHECK, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3989 | .retain_reg = TV_CC_REG, |
| 3990 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3991 | }, |
| 3992 | .md_reg = TV_MD_REG, |
| 3993 | .root_en_mask = BIT(2), |
| 3994 | .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 3995 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3996 | .ctl_mask = BM(7, 6), |
| 3997 | .set_rate = set_rate_tv, |
| 3998 | .freq_tbl = clk_tbl_tv, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3999 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4000 | .c = { |
| 4001 | .dbg_name = "tv_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4002 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4003 | VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4004 | CLK_INIT(tv_src_clk.c), |
| 4005 | }, |
| 4006 | }; |
| 4007 | |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 4008 | static struct cdiv_clk tv_src_div_clk = { |
| 4009 | .b = { |
| 4010 | .ctl_reg = TV_NS_REG, |
| 4011 | .halt_check = NOCHECK, |
| 4012 | }, |
| 4013 | .ns_reg = TV_NS_REG, |
| 4014 | .div_offset = 6, |
| 4015 | .max_div = 2, |
| 4016 | .c = { |
| 4017 | .dbg_name = "tv_src_div_clk", |
| 4018 | .ops = &clk_ops_cdiv, |
| 4019 | CLK_INIT(tv_src_div_clk.c), |
| 4020 | }, |
| 4021 | }; |
| 4022 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4023 | static struct branch_clk tv_enc_clk = { |
| 4024 | .b = { |
| 4025 | .ctl_reg = TV_CC_REG, |
| 4026 | .en_mask = BIT(8), |
| 4027 | .reset_reg = SW_RESET_CORE_REG, |
| 4028 | .reset_mask = BIT(0), |
| 4029 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 4030 | .halt_bit = 9, |
| 4031 | }, |
| 4032 | .parent = &tv_src_clk.c, |
| 4033 | .c = { |
| 4034 | .dbg_name = "tv_enc_clk", |
| 4035 | .ops = &clk_ops_branch, |
| 4036 | CLK_INIT(tv_enc_clk.c), |
| 4037 | }, |
| 4038 | }; |
| 4039 | |
| 4040 | static struct branch_clk tv_dac_clk = { |
| 4041 | .b = { |
| 4042 | .ctl_reg = TV_CC_REG, |
| 4043 | .en_mask = BIT(10), |
| 4044 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 4045 | .halt_bit = 10, |
| 4046 | }, |
| 4047 | .parent = &tv_src_clk.c, |
| 4048 | .c = { |
| 4049 | .dbg_name = "tv_dac_clk", |
| 4050 | .ops = &clk_ops_branch, |
| 4051 | CLK_INIT(tv_dac_clk.c), |
| 4052 | }, |
| 4053 | }; |
| 4054 | |
| 4055 | static struct branch_clk mdp_tv_clk = { |
| 4056 | .b = { |
| 4057 | .ctl_reg = TV_CC_REG, |
| 4058 | .en_mask = BIT(0), |
| 4059 | .reset_reg = SW_RESET_CORE_REG, |
| 4060 | .reset_mask = BIT(4), |
| 4061 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 4062 | .halt_bit = 12, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4063 | .retain_reg = TV_CC2_REG, |
| 4064 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4065 | }, |
| 4066 | .parent = &tv_src_clk.c, |
| 4067 | .c = { |
| 4068 | .dbg_name = "mdp_tv_clk", |
| 4069 | .ops = &clk_ops_branch, |
| 4070 | CLK_INIT(mdp_tv_clk.c), |
| 4071 | }, |
| 4072 | }; |
| 4073 | |
| 4074 | static struct branch_clk hdmi_tv_clk = { |
| 4075 | .b = { |
| 4076 | .ctl_reg = TV_CC_REG, |
| 4077 | .en_mask = BIT(12), |
| 4078 | .reset_reg = SW_RESET_CORE_REG, |
| 4079 | .reset_mask = BIT(1), |
| 4080 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 4081 | .halt_bit = 11, |
| 4082 | }, |
| 4083 | .parent = &tv_src_clk.c, |
| 4084 | .c = { |
| 4085 | .dbg_name = "hdmi_tv_clk", |
| 4086 | .ops = &clk_ops_branch, |
| 4087 | CLK_INIT(hdmi_tv_clk.c), |
| 4088 | }, |
| 4089 | }; |
| 4090 | |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 4091 | static struct branch_clk rgb_tv_clk = { |
| 4092 | .b = { |
| 4093 | .ctl_reg = TV_CC2_REG, |
| 4094 | .en_mask = BIT(14), |
| 4095 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 4096 | .halt_bit = 27, |
| 4097 | }, |
| 4098 | .parent = &tv_src_clk.c, |
| 4099 | .c = { |
| 4100 | .dbg_name = "rgb_tv_clk", |
| 4101 | .ops = &clk_ops_branch, |
| 4102 | CLK_INIT(rgb_tv_clk.c), |
| 4103 | }, |
| 4104 | }; |
| 4105 | |
| 4106 | static struct branch_clk npl_tv_clk = { |
| 4107 | .b = { |
| 4108 | .ctl_reg = TV_CC2_REG, |
| 4109 | .en_mask = BIT(16), |
| 4110 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 4111 | .halt_bit = 26, |
| 4112 | }, |
| 4113 | .parent = &tv_src_clk.c, |
| 4114 | .c = { |
| 4115 | .dbg_name = "npl_tv_clk", |
| 4116 | .ops = &clk_ops_branch, |
| 4117 | CLK_INIT(npl_tv_clk.c), |
| 4118 | }, |
| 4119 | }; |
| 4120 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4121 | static struct branch_clk hdmi_app_clk = { |
| 4122 | .b = { |
| 4123 | .ctl_reg = MISC_CC2_REG, |
| 4124 | .en_mask = BIT(11), |
| 4125 | .reset_reg = SW_RESET_CORE_REG, |
| 4126 | .reset_mask = BIT(11), |
| 4127 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 4128 | .halt_bit = 25, |
| 4129 | }, |
| 4130 | .c = { |
| 4131 | .dbg_name = "hdmi_app_clk", |
| 4132 | .ops = &clk_ops_branch, |
| 4133 | CLK_INIT(hdmi_app_clk.c), |
| 4134 | }, |
| 4135 | }; |
| 4136 | |
| 4137 | static struct bank_masks bmnd_info_vcodec = { |
| 4138 | .bank_sel_mask = BIT(13), |
| 4139 | .bank0_mask = { |
| 4140 | .md_reg = VCODEC_MD0_REG, |
| 4141 | .ns_mask = BM(18, 11) | BM(2, 0), |
| 4142 | .rst_mask = BIT(31), |
| 4143 | .mnd_en_mask = BIT(5), |
| 4144 | .mode_mask = BM(7, 6), |
| 4145 | }, |
| 4146 | .bank1_mask = { |
| 4147 | .md_reg = VCODEC_MD1_REG, |
| 4148 | .ns_mask = BM(26, 19) | BM(29, 27), |
| 4149 | .rst_mask = BIT(30), |
| 4150 | .mnd_en_mask = BIT(10), |
| 4151 | .mode_mask = BM(12, 11), |
| 4152 | }, |
| 4153 | }; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4154 | #define F_VCODEC(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4155 | { \ |
| 4156 | .freq_hz = f, \ |
| 4157 | .src_clk = &s##_clk.c, \ |
| 4158 | .md_val = MD8(8, m, 0, n), \ |
| 4159 | .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \ |
| 4160 | .ctl_val = CC_BANKED(6, 11, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4161 | } |
| 4162 | static struct clk_freq_tbl clk_tbl_vcodec[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4163 | F_VCODEC( 0, gnd, 0, 0), |
| 4164 | F_VCODEC( 27000000, pxo, 0, 0), |
| 4165 | F_VCODEC( 32000000, pll8, 1, 12), |
| 4166 | F_VCODEC( 48000000, pll8, 1, 8), |
| 4167 | F_VCODEC( 54860000, pll8, 1, 7), |
| 4168 | F_VCODEC( 96000000, pll8, 1, 4), |
| 4169 | F_VCODEC(133330000, pll2, 1, 6), |
| 4170 | F_VCODEC(200000000, pll2, 1, 4), |
| 4171 | F_VCODEC(228570000, pll2, 2, 7), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4172 | F_END |
| 4173 | }; |
| 4174 | |
| 4175 | static struct rcg_clk vcodec_clk = { |
| 4176 | .b = { |
| 4177 | .ctl_reg = VCODEC_CC_REG, |
| 4178 | .en_mask = BIT(0), |
| 4179 | .reset_reg = SW_RESET_CORE_REG, |
| 4180 | .reset_mask = BIT(6), |
| 4181 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 4182 | .halt_bit = 29, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4183 | .retain_reg = VCODEC_CC_REG, |
| 4184 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4185 | }, |
| 4186 | .ns_reg = VCODEC_NS_REG, |
| 4187 | .root_en_mask = BIT(2), |
| 4188 | .set_rate = set_rate_mnd_banked, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 4189 | .bank_info = &bmnd_info_vcodec, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4190 | .freq_tbl = clk_tbl_vcodec, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4191 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4192 | .c = { |
| 4193 | .dbg_name = "vcodec_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4194 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4195 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 4196 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4197 | CLK_INIT(vcodec_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4198 | .depends = &vcodec_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4199 | }, |
| 4200 | }; |
| 4201 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4202 | #define F_VPE(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4203 | { \ |
| 4204 | .freq_hz = f, \ |
| 4205 | .src_clk = &s##_clk.c, \ |
| 4206 | .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4207 | } |
| 4208 | static struct clk_freq_tbl clk_tbl_vpe[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4209 | F_VPE( 0, gnd, 1), |
| 4210 | F_VPE( 27000000, pxo, 1), |
| 4211 | F_VPE( 34909000, pll8, 11), |
| 4212 | F_VPE( 38400000, pll8, 10), |
| 4213 | F_VPE( 64000000, pll8, 6), |
| 4214 | F_VPE( 76800000, pll8, 5), |
| 4215 | F_VPE( 96000000, pll8, 4), |
| 4216 | F_VPE(100000000, pll2, 8), |
| 4217 | F_VPE(160000000, pll2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4218 | F_END |
| 4219 | }; |
| 4220 | |
| 4221 | static struct rcg_clk vpe_clk = { |
| 4222 | .b = { |
| 4223 | .ctl_reg = VPE_CC_REG, |
| 4224 | .en_mask = BIT(0), |
| 4225 | .reset_reg = SW_RESET_CORE_REG, |
| 4226 | .reset_mask = BIT(17), |
| 4227 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 4228 | .halt_bit = 28, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4229 | .retain_reg = VPE_CC_REG, |
| 4230 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4231 | }, |
| 4232 | .ns_reg = VPE_NS_REG, |
| 4233 | .root_en_mask = BIT(2), |
| 4234 | .ns_mask = (BM(15, 12) | BM(2, 0)), |
| 4235 | .set_rate = set_rate_nop, |
| 4236 | .freq_tbl = clk_tbl_vpe, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4237 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4238 | .c = { |
| 4239 | .dbg_name = "vpe_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4240 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4241 | VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4242 | CLK_INIT(vpe_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4243 | .depends = &vpe_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4244 | }, |
| 4245 | }; |
| 4246 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4247 | #define F_VFE(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4248 | { \ |
| 4249 | .freq_hz = f, \ |
| 4250 | .src_clk = &s##_clk.c, \ |
| 4251 | .md_val = MD8(8, m, 0, n), \ |
| 4252 | .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \ |
| 4253 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4254 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4255 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4256 | static struct clk_freq_tbl clk_tbl_vfe[] = { |
| 4257 | F_VFE( 0, gnd, 1, 0, 0), |
| 4258 | F_VFE( 13960000, pll8, 1, 2, 55), |
| 4259 | F_VFE( 27000000, pxo, 1, 0, 0), |
| 4260 | F_VFE( 36570000, pll8, 1, 2, 21), |
| 4261 | F_VFE( 38400000, pll8, 2, 1, 5), |
| 4262 | F_VFE( 45180000, pll8, 1, 2, 17), |
| 4263 | F_VFE( 48000000, pll8, 2, 1, 4), |
| 4264 | F_VFE( 54860000, pll8, 1, 1, 7), |
| 4265 | F_VFE( 64000000, pll8, 2, 1, 3), |
| 4266 | F_VFE( 76800000, pll8, 1, 1, 5), |
| 4267 | F_VFE( 96000000, pll8, 2, 1, 2), |
| 4268 | F_VFE(109710000, pll8, 1, 2, 7), |
| 4269 | F_VFE(128000000, pll8, 1, 1, 3), |
| 4270 | F_VFE(153600000, pll8, 1, 2, 5), |
| 4271 | F_VFE(200000000, pll2, 2, 1, 2), |
| 4272 | F_VFE(228570000, pll2, 1, 2, 7), |
| 4273 | F_VFE(266667000, pll2, 1, 1, 3), |
| 4274 | F_VFE(320000000, pll2, 1, 2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4275 | F_END |
| 4276 | }; |
| 4277 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4278 | static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = { |
| 4279 | [VDD_DIG_LOW] = 128000000, |
| 4280 | [VDD_DIG_NOMINAL] = 266667000, |
| 4281 | [VDD_DIG_HIGH] = 320000000 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4282 | }; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4283 | |
| 4284 | static struct rcg_clk vfe_clk = { |
| 4285 | .b = { |
| 4286 | .ctl_reg = VFE_CC_REG, |
| 4287 | .reset_reg = SW_RESET_CORE_REG, |
| 4288 | .reset_mask = BIT(15), |
| 4289 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 4290 | .halt_bit = 6, |
| 4291 | .en_mask = BIT(0), |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4292 | .retain_reg = VFE_CC2_REG, |
| 4293 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4294 | }, |
| 4295 | .ns_reg = VFE_NS_REG, |
| 4296 | .md_reg = VFE_MD_REG, |
| 4297 | .root_en_mask = BIT(2), |
| 4298 | .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4299 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4300 | .ctl_mask = BM(7, 6), |
| 4301 | .set_rate = set_rate_mnd, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4302 | .freq_tbl = clk_tbl_vfe, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4303 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4304 | .c = { |
| 4305 | .dbg_name = "vfe_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4306 | .ops = &clk_ops_rcg, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 4307 | VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000, |
| 4308 | HIGH, 320000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4309 | CLK_INIT(vfe_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4310 | .depends = &vfe_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4311 | }, |
| 4312 | }; |
| 4313 | |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4314 | static struct branch_clk csi_vfe_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4315 | .b = { |
| 4316 | .ctl_reg = VFE_CC_REG, |
| 4317 | .en_mask = BIT(12), |
| 4318 | .reset_reg = SW_RESET_CORE_REG, |
| 4319 | .reset_mask = BIT(24), |
| 4320 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 4321 | .halt_bit = 8, |
| 4322 | }, |
| 4323 | .parent = &vfe_clk.c, |
| 4324 | .c = { |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4325 | .dbg_name = "csi_vfe_clk", |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4326 | .ops = &clk_ops_branch, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4327 | CLK_INIT(csi_vfe_clk.c), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4328 | }, |
| 4329 | }; |
| 4330 | |
| 4331 | /* |
| 4332 | * Low Power Audio Clocks |
| 4333 | */ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4334 | #define F_AIF_OSR(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4335 | { \ |
| 4336 | .freq_hz = f, \ |
| 4337 | .src_clk = &s##_clk.c, \ |
| 4338 | .md_val = MD8(8, m, 0, n), \ |
| 4339 | .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4340 | } |
| 4341 | static struct clk_freq_tbl clk_tbl_aif_osr[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4342 | F_AIF_OSR( 0, gnd, 1, 0, 0), |
| 4343 | F_AIF_OSR( 512000, pll4, 4, 1, 192), |
| 4344 | F_AIF_OSR( 768000, pll4, 4, 1, 128), |
| 4345 | F_AIF_OSR( 1024000, pll4, 4, 1, 96), |
| 4346 | F_AIF_OSR( 1536000, pll4, 4, 1, 64), |
| 4347 | F_AIF_OSR( 2048000, pll4, 4, 1, 48), |
| 4348 | F_AIF_OSR( 3072000, pll4, 4, 1, 32), |
| 4349 | F_AIF_OSR( 4096000, pll4, 4, 1, 24), |
| 4350 | F_AIF_OSR( 6144000, pll4, 4, 1, 16), |
| 4351 | F_AIF_OSR( 8192000, pll4, 4, 1, 12), |
| 4352 | F_AIF_OSR(12288000, pll4, 4, 1, 8), |
| 4353 | F_AIF_OSR(24576000, pll4, 4, 1, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4354 | F_END |
| 4355 | }; |
| 4356 | |
| 4357 | #define CLK_AIF_OSR(i, ns, md, h_r) \ |
| 4358 | struct rcg_clk i##_clk = { \ |
| 4359 | .b = { \ |
| 4360 | .ctl_reg = ns, \ |
| 4361 | .en_mask = BIT(17), \ |
| 4362 | .reset_reg = ns, \ |
| 4363 | .reset_mask = BIT(19), \ |
| 4364 | .halt_reg = h_r, \ |
| 4365 | .halt_check = ENABLE, \ |
| 4366 | .halt_bit = 1, \ |
| 4367 | }, \ |
| 4368 | .ns_reg = ns, \ |
| 4369 | .md_reg = md, \ |
| 4370 | .root_en_mask = BIT(9), \ |
| 4371 | .ns_mask = (BM(31, 24) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4372 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4373 | .set_rate = set_rate_mnd, \ |
| 4374 | .freq_tbl = clk_tbl_aif_osr, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4375 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4376 | .c = { \ |
| 4377 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4378 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4379 | VDD_DIG_FMAX_MAP1(LOW, 24576000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4380 | CLK_INIT(i##_clk.c), \ |
| 4381 | }, \ |
| 4382 | } |
| 4383 | #define CLK_AIF_OSR_DIV(i, ns, md, h_r) \ |
| 4384 | struct rcg_clk i##_clk = { \ |
| 4385 | .b = { \ |
| 4386 | .ctl_reg = ns, \ |
| 4387 | .en_mask = BIT(21), \ |
| 4388 | .reset_reg = ns, \ |
| 4389 | .reset_mask = BIT(23), \ |
| 4390 | .halt_reg = h_r, \ |
| 4391 | .halt_check = ENABLE, \ |
| 4392 | .halt_bit = 1, \ |
| 4393 | }, \ |
| 4394 | .ns_reg = ns, \ |
| 4395 | .md_reg = md, \ |
| 4396 | .root_en_mask = BIT(9), \ |
| 4397 | .ns_mask = (BM(31, 24) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4398 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4399 | .set_rate = set_rate_mnd, \ |
| 4400 | .freq_tbl = clk_tbl_aif_osr, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4401 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4402 | .c = { \ |
| 4403 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4404 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4405 | VDD_DIG_FMAX_MAP1(LOW, 24576000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4406 | CLK_INIT(i##_clk.c), \ |
| 4407 | }, \ |
| 4408 | } |
| 4409 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4410 | #define CLK_AIF_BIT(i, ns, h_r) \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4411 | struct cdiv_clk i##_clk = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4412 | .b = { \ |
| 4413 | .ctl_reg = ns, \ |
| 4414 | .en_mask = BIT(15), \ |
| 4415 | .halt_reg = h_r, \ |
| 4416 | .halt_check = DELAY, \ |
| 4417 | }, \ |
| 4418 | .ns_reg = ns, \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4419 | .ext_mask = BIT(14), \ |
| 4420 | .div_offset = 10, \ |
| 4421 | .max_div = 16, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4422 | .c = { \ |
| 4423 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4424 | .ops = &clk_ops_cdiv, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4425 | CLK_INIT(i##_clk.c), \ |
| 4426 | }, \ |
| 4427 | } |
| 4428 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4429 | #define CLK_AIF_BIT_DIV(i, ns, h_r) \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4430 | struct cdiv_clk i##_clk = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4431 | .b = { \ |
| 4432 | .ctl_reg = ns, \ |
| 4433 | .en_mask = BIT(19), \ |
| 4434 | .halt_reg = h_r, \ |
Stephen Boyd | 7bb9cf8 | 2012-01-25 18:09:01 -0800 | [diff] [blame] | 4435 | .halt_check = DELAY, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4436 | }, \ |
| 4437 | .ns_reg = ns, \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4438 | .ext_mask = BIT(18), \ |
| 4439 | .div_offset = 10, \ |
| 4440 | .max_div = 256, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4441 | .c = { \ |
| 4442 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4443 | .ops = &clk_ops_cdiv, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4444 | CLK_INIT(i##_clk.c), \ |
| 4445 | }, \ |
| 4446 | } |
| 4447 | |
| 4448 | static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG, |
| 4449 | LCC_MI2S_STATUS_REG); |
| 4450 | static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG); |
| 4451 | |
| 4452 | static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG, |
| 4453 | LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG); |
| 4454 | static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG, |
| 4455 | LCC_CODEC_I2S_MIC_STATUS_REG); |
| 4456 | |
| 4457 | static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG, |
| 4458 | LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG); |
| 4459 | static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG, |
| 4460 | LCC_SPARE_I2S_MIC_STATUS_REG); |
| 4461 | |
| 4462 | static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG, |
| 4463 | LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG); |
| 4464 | static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG, |
| 4465 | LCC_CODEC_I2S_SPKR_STATUS_REG); |
| 4466 | |
| 4467 | static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG, |
| 4468 | LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG); |
| 4469 | static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG, |
| 4470 | LCC_SPARE_I2S_SPKR_STATUS_REG); |
| 4471 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4472 | #define F_PCM(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4473 | { \ |
| 4474 | .freq_hz = f, \ |
| 4475 | .src_clk = &s##_clk.c, \ |
| 4476 | .md_val = MD16(m, n), \ |
| 4477 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4478 | } |
| 4479 | static struct clk_freq_tbl clk_tbl_pcm[] = { |
Stephen Boyd | 630f325 | 2012-01-31 00:10:08 -0800 | [diff] [blame] | 4480 | { .ns_val = BIT(10) /* external input */ }, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4481 | F_PCM( 512000, pll4, 4, 1, 192), |
| 4482 | F_PCM( 768000, pll4, 4, 1, 128), |
| 4483 | F_PCM( 1024000, pll4, 4, 1, 96), |
| 4484 | F_PCM( 1536000, pll4, 4, 1, 64), |
| 4485 | F_PCM( 2048000, pll4, 4, 1, 48), |
| 4486 | F_PCM( 3072000, pll4, 4, 1, 32), |
| 4487 | F_PCM( 4096000, pll4, 4, 1, 24), |
| 4488 | F_PCM( 6144000, pll4, 4, 1, 16), |
| 4489 | F_PCM( 8192000, pll4, 4, 1, 12), |
| 4490 | F_PCM(12288000, pll4, 4, 1, 8), |
| 4491 | F_PCM(24576000, pll4, 4, 1, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4492 | F_END |
| 4493 | }; |
| 4494 | |
| 4495 | static struct rcg_clk pcm_clk = { |
| 4496 | .b = { |
| 4497 | .ctl_reg = LCC_PCM_NS_REG, |
| 4498 | .en_mask = BIT(11), |
| 4499 | .reset_reg = LCC_PCM_NS_REG, |
| 4500 | .reset_mask = BIT(13), |
| 4501 | .halt_reg = LCC_PCM_STATUS_REG, |
| 4502 | .halt_check = ENABLE, |
| 4503 | .halt_bit = 0, |
| 4504 | }, |
| 4505 | .ns_reg = LCC_PCM_NS_REG, |
| 4506 | .md_reg = LCC_PCM_MD_REG, |
| 4507 | .root_en_mask = BIT(9), |
Stephen Boyd | 630f325 | 2012-01-31 00:10:08 -0800 | [diff] [blame] | 4508 | .ns_mask = BM(31, 16) | BIT(10) | BM(6, 0), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4509 | .mnd_en_mask = BIT(8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4510 | .set_rate = set_rate_mnd, |
| 4511 | .freq_tbl = clk_tbl_pcm, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4512 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4513 | .c = { |
| 4514 | .dbg_name = "pcm_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4515 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4516 | VDD_DIG_FMAX_MAP1(LOW, 24576000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4517 | CLK_INIT(pcm_clk.c), |
| 4518 | }, |
| 4519 | }; |
| 4520 | |
| 4521 | static struct rcg_clk audio_slimbus_clk = { |
| 4522 | .b = { |
| 4523 | .ctl_reg = LCC_SLIMBUS_NS_REG, |
| 4524 | .en_mask = BIT(10), |
| 4525 | .reset_reg = LCC_AHBEX_BRANCH_CTL_REG, |
| 4526 | .reset_mask = BIT(5), |
| 4527 | .halt_reg = LCC_SLIMBUS_STATUS_REG, |
| 4528 | .halt_check = ENABLE, |
| 4529 | .halt_bit = 0, |
| 4530 | }, |
| 4531 | .ns_reg = LCC_SLIMBUS_NS_REG, |
| 4532 | .md_reg = LCC_SLIMBUS_MD_REG, |
| 4533 | .root_en_mask = BIT(9), |
| 4534 | .ns_mask = (BM(31, 24) | BM(6, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4535 | .mnd_en_mask = BIT(8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4536 | .set_rate = set_rate_mnd, |
| 4537 | .freq_tbl = clk_tbl_aif_osr, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4538 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4539 | .c = { |
| 4540 | .dbg_name = "audio_slimbus_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4541 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4542 | VDD_DIG_FMAX_MAP1(LOW, 24576000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4543 | CLK_INIT(audio_slimbus_clk.c), |
| 4544 | }, |
| 4545 | }; |
| 4546 | |
| 4547 | static struct branch_clk sps_slimbus_clk = { |
| 4548 | .b = { |
| 4549 | .ctl_reg = LCC_SLIMBUS_NS_REG, |
| 4550 | .en_mask = BIT(12), |
| 4551 | .halt_reg = LCC_SLIMBUS_STATUS_REG, |
| 4552 | .halt_check = ENABLE, |
| 4553 | .halt_bit = 1, |
| 4554 | }, |
| 4555 | .parent = &audio_slimbus_clk.c, |
| 4556 | .c = { |
| 4557 | .dbg_name = "sps_slimbus_clk", |
| 4558 | .ops = &clk_ops_branch, |
| 4559 | CLK_INIT(sps_slimbus_clk.c), |
| 4560 | }, |
| 4561 | }; |
| 4562 | |
| 4563 | static struct branch_clk slimbus_xo_src_clk = { |
| 4564 | .b = { |
| 4565 | .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG, |
| 4566 | .en_mask = BIT(2), |
| 4567 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4568 | .halt_bit = 28, |
| 4569 | }, |
| 4570 | .parent = &sps_slimbus_clk.c, |
| 4571 | .c = { |
| 4572 | .dbg_name = "slimbus_xo_src_clk", |
| 4573 | .ops = &clk_ops_branch, |
| 4574 | CLK_INIT(slimbus_xo_src_clk.c), |
| 4575 | }, |
| 4576 | }; |
| 4577 | |
Matt Wagantall | 735f01a | 2011-08-12 12:40:28 -0700 | [diff] [blame] | 4578 | DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL); |
| 4579 | DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL); |
| 4580 | DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL); |
| 4581 | DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL); |
| 4582 | DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL); |
| 4583 | DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL); |
| 4584 | DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL); |
| 4585 | DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4586 | |
Matt Wagantall | 35e78fc | 2012-04-05 14:18:44 -0700 | [diff] [blame] | 4587 | static DEFINE_CLK_VOTER(sfab_msmbus_a_clk, &sfab_a_clk.c, 0); |
| 4588 | static DEFINE_CLK_VOTER(sfab_tmr_a_clk, &sfab_a_clk.c, 0); |
Stephen Boyd | d7a143a | 2012-02-16 17:59:26 -0800 | [diff] [blame] | 4589 | |
Matt Wagantall | 35e78fc | 2012-04-05 14:18:44 -0700 | [diff] [blame] | 4590 | static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c, 0); |
| 4591 | static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c, 0); |
| 4592 | static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c, 0); |
| 4593 | static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c, 0); |
| 4594 | static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c, 0); |
| 4595 | static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c, 0); |
| 4596 | static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c, 0); |
| 4597 | static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c, 0); |
| 4598 | static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c, 0); |
| 4599 | static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c, 0); |
| 4600 | static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c, 0); |
| 4601 | static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c, 0); |
| 4602 | static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c, 0); |
Matt Wagantall | 35e78fc | 2012-04-05 14:18:44 -0700 | [diff] [blame] | 4603 | static DEFINE_CLK_VOTER(dfab_msmbus_clk, &dfab_clk.c, 0); |
| 4604 | static DEFINE_CLK_VOTER(dfab_msmbus_a_clk, &dfab_a_clk.c, 0); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4605 | |
Matt Wagantall | 42cd12a | 2012-03-30 18:02:40 -0700 | [diff] [blame] | 4606 | static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c, LONG_MAX); |
Matt Wagantall | 35e78fc | 2012-04-05 14:18:44 -0700 | [diff] [blame] | 4607 | static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c, 0); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4608 | |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 4609 | static DEFINE_CLK_VOTER(ebi1_acpu_a_clk, &ebi1_a_clk.c, LONG_MAX); |
| 4610 | static DEFINE_CLK_VOTER(ebi1_msmbus_a_clk, &ebi1_a_clk.c, LONG_MAX); |
| 4611 | static DEFINE_CLK_VOTER(afab_acpu_a_clk, &afab_a_clk.c, LONG_MAX); |
| 4612 | static DEFINE_CLK_VOTER(afab_msmbus_a_clk, &afab_a_clk.c, LONG_MAX); |
| 4613 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4614 | #ifdef CONFIG_DEBUG_FS |
| 4615 | struct measure_sel { |
| 4616 | u32 test_vector; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4617 | struct clk *c; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4618 | }; |
| 4619 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4620 | static DEFINE_CLK_MEASURE(l2_m_clk); |
| 4621 | static DEFINE_CLK_MEASURE(krait0_m_clk); |
| 4622 | static DEFINE_CLK_MEASURE(krait1_m_clk); |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 4623 | static DEFINE_CLK_MEASURE(krait2_m_clk); |
| 4624 | static DEFINE_CLK_MEASURE(krait3_m_clk); |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4625 | static DEFINE_CLK_MEASURE(q6sw_clk); |
| 4626 | static DEFINE_CLK_MEASURE(q6fw_clk); |
| 4627 | static DEFINE_CLK_MEASURE(q6_func_clk); |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4628 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4629 | static struct measure_sel measure_mux[] = { |
| 4630 | { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c }, |
| 4631 | { TEST_PER_LS(0x12), &sdc1_p_clk.c }, |
| 4632 | { TEST_PER_LS(0x13), &sdc1_clk.c }, |
| 4633 | { TEST_PER_LS(0x14), &sdc2_p_clk.c }, |
| 4634 | { TEST_PER_LS(0x15), &sdc2_clk.c }, |
| 4635 | { TEST_PER_LS(0x16), &sdc3_p_clk.c }, |
| 4636 | { TEST_PER_LS(0x17), &sdc3_clk.c }, |
| 4637 | { TEST_PER_LS(0x18), &sdc4_p_clk.c }, |
| 4638 | { TEST_PER_LS(0x19), &sdc4_clk.c }, |
| 4639 | { TEST_PER_LS(0x1A), &sdc5_p_clk.c }, |
| 4640 | { TEST_PER_LS(0x1B), &sdc5_clk.c }, |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 4641 | { TEST_PER_LS(0x1F), &gp0_clk.c }, |
| 4642 | { TEST_PER_LS(0x20), &gp1_clk.c }, |
| 4643 | { TEST_PER_LS(0x21), &gp2_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4644 | { TEST_PER_LS(0x25), &dfab_clk.c }, |
| 4645 | { TEST_PER_LS(0x25), &dfab_a_clk.c }, |
| 4646 | { TEST_PER_LS(0x26), &pmem_clk.c }, |
| 4647 | { TEST_PER_LS(0x32), &dma_bam_p_clk.c }, |
| 4648 | { TEST_PER_LS(0x33), &cfpb_clk.c }, |
| 4649 | { TEST_PER_LS(0x33), &cfpb_a_clk.c }, |
| 4650 | { TEST_PER_LS(0x3D), &gsbi1_p_clk.c }, |
| 4651 | { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c }, |
| 4652 | { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c }, |
| 4653 | { TEST_PER_LS(0x41), &gsbi2_p_clk.c }, |
| 4654 | { TEST_PER_LS(0x42), &gsbi2_uart_clk.c }, |
| 4655 | { TEST_PER_LS(0x44), &gsbi2_qup_clk.c }, |
| 4656 | { TEST_PER_LS(0x45), &gsbi3_p_clk.c }, |
| 4657 | { TEST_PER_LS(0x46), &gsbi3_uart_clk.c }, |
| 4658 | { TEST_PER_LS(0x48), &gsbi3_qup_clk.c }, |
| 4659 | { TEST_PER_LS(0x49), &gsbi4_p_clk.c }, |
| 4660 | { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c }, |
| 4661 | { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c }, |
| 4662 | { TEST_PER_LS(0x4D), &gsbi5_p_clk.c }, |
| 4663 | { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c }, |
| 4664 | { TEST_PER_LS(0x50), &gsbi5_qup_clk.c }, |
| 4665 | { TEST_PER_LS(0x51), &gsbi6_p_clk.c }, |
| 4666 | { TEST_PER_LS(0x52), &gsbi6_uart_clk.c }, |
| 4667 | { TEST_PER_LS(0x54), &gsbi6_qup_clk.c }, |
| 4668 | { TEST_PER_LS(0x55), &gsbi7_p_clk.c }, |
| 4669 | { TEST_PER_LS(0x56), &gsbi7_uart_clk.c }, |
| 4670 | { TEST_PER_LS(0x58), &gsbi7_qup_clk.c }, |
| 4671 | { TEST_PER_LS(0x59), &gsbi8_p_clk.c }, |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 4672 | { TEST_PER_LS(0x59), &sfab_sata_s_p_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4673 | { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c }, |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 4674 | { TEST_PER_LS(0x5A), &sata_p_clk.c }, |
| 4675 | { TEST_PER_LS(0x5B), &sata_rxoob_clk.c }, |
| 4676 | { TEST_PER_LS(0x5C), &sata_pmalive_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4677 | { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c }, |
| 4678 | { TEST_PER_LS(0x5D), &gsbi9_p_clk.c }, |
| 4679 | { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c }, |
| 4680 | { TEST_PER_LS(0x60), &gsbi9_qup_clk.c }, |
| 4681 | { TEST_PER_LS(0x61), &gsbi10_p_clk.c }, |
| 4682 | { TEST_PER_LS(0x62), &gsbi10_uart_clk.c }, |
| 4683 | { TEST_PER_LS(0x64), &gsbi10_qup_clk.c }, |
| 4684 | { TEST_PER_LS(0x65), &gsbi11_p_clk.c }, |
| 4685 | { TEST_PER_LS(0x66), &gsbi11_uart_clk.c }, |
| 4686 | { TEST_PER_LS(0x68), &gsbi11_qup_clk.c }, |
| 4687 | { TEST_PER_LS(0x69), &gsbi12_p_clk.c }, |
| 4688 | { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c }, |
| 4689 | { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c }, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4690 | { TEST_PER_LS(0x5E), &pcie_p_clk.c }, |
| 4691 | { TEST_PER_LS(0x5F), &ce3_p_clk.c }, |
| 4692 | { TEST_PER_LS(0x60), &ce3_core_clk.c }, |
| 4693 | { TEST_PER_LS(0x63), &usb_hs3_p_clk.c }, |
| 4694 | { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c }, |
| 4695 | { TEST_PER_LS(0x65), &usb_hs4_p_clk.c }, |
| 4696 | { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c }, |
| 4697 | { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c }, |
| 4698 | { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4699 | { TEST_PER_LS(0x78), &sfpb_clk.c }, |
| 4700 | { TEST_PER_LS(0x78), &sfpb_a_clk.c }, |
| 4701 | { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c }, |
| 4702 | { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c }, |
| 4703 | { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c }, |
| 4704 | { TEST_PER_LS(0x7D), &prng_clk.c }, |
| 4705 | { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c }, |
| 4706 | { TEST_PER_LS(0x80), &adm0_p_clk.c }, |
| 4707 | { TEST_PER_LS(0x84), &usb_hs1_p_clk.c }, |
| 4708 | { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4709 | { TEST_PER_LS(0x86), &usb_hsic_p_clk.c }, |
| 4710 | { TEST_PER_LS(0x87), &usb_hsic_system_clk.c }, |
| 4711 | { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4712 | { TEST_PER_LS(0x89), &usb_fs1_p_clk.c }, |
| 4713 | { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c }, |
| 4714 | { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c }, |
| 4715 | { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c }, |
| 4716 | { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c }, |
| 4717 | { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c }, |
| 4718 | { TEST_PER_LS(0x8F), &tsif_p_clk.c }, |
| 4719 | { TEST_PER_LS(0x91), &tsif_ref_clk.c }, |
| 4720 | { TEST_PER_LS(0x92), &ce1_p_clk.c }, |
| 4721 | { TEST_PER_LS(0x94), &tssc_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4722 | { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4723 | { TEST_PER_LS(0xA4), &ce1_core_clk.c }, |
| 4724 | |
| 4725 | { TEST_PER_HS(0x07), &afab_clk.c }, |
| 4726 | { TEST_PER_HS(0x07), &afab_a_clk.c }, |
| 4727 | { TEST_PER_HS(0x18), &sfab_clk.c }, |
| 4728 | { TEST_PER_HS(0x18), &sfab_a_clk.c }, |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4729 | { TEST_PER_HS(0x26), &q6sw_clk }, |
| 4730 | { TEST_PER_HS(0x27), &q6fw_clk }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4731 | { TEST_PER_HS(0x2A), &adm0_clk.c }, |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 4732 | { TEST_PER_HS(0x31), &sata_a_clk.c }, |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 4733 | { TEST_PER_HS(0x2D), &pcie_phy_ref_clk.c }, |
| 4734 | { TEST_PER_HS(0x32), &pcie_a_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4735 | { TEST_PER_HS(0x34), &ebi1_clk.c }, |
| 4736 | { TEST_PER_HS(0x34), &ebi1_a_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4737 | { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4738 | |
| 4739 | { TEST_MM_LS(0x00), &dsi1_byte_clk.c }, |
| 4740 | { TEST_MM_LS(0x01), &dsi2_byte_clk.c }, |
| 4741 | { TEST_MM_LS(0x02), &cam1_clk.c }, |
| 4742 | { TEST_MM_LS(0x06), &_p_clk.c }, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4743 | { TEST_MM_LS(0x07), &csi_p_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4744 | { TEST_MM_LS(0x08), &dsi2_s_p_clk.c }, |
| 4745 | { TEST_MM_LS(0x09), &dsi1_m_p_clk.c }, |
| 4746 | { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c }, |
| 4747 | { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c }, |
| 4748 | { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c }, |
| 4749 | { TEST_MM_LS(0x0E), &gfx3d_p_clk.c }, |
| 4750 | { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c }, |
| 4751 | { TEST_MM_LS(0x10), &hdmi_s_p_clk.c }, |
| 4752 | { TEST_MM_LS(0x11), &ijpeg_p_clk.c }, |
| 4753 | { TEST_MM_LS(0x12), &imem_p_clk.c }, |
| 4754 | { TEST_MM_LS(0x13), &jpegd_p_clk.c }, |
| 4755 | { TEST_MM_LS(0x14), &mdp_p_clk.c }, |
| 4756 | { TEST_MM_LS(0x16), &rot_p_clk.c }, |
| 4757 | { TEST_MM_LS(0x17), &dsi1_esc_clk.c }, |
| 4758 | { TEST_MM_LS(0x18), &smmu_p_clk.c }, |
| 4759 | { TEST_MM_LS(0x19), &tv_enc_p_clk.c }, |
| 4760 | { TEST_MM_LS(0x1A), &vcodec_p_clk.c }, |
| 4761 | { TEST_MM_LS(0x1B), &vfe_p_clk.c }, |
| 4762 | { TEST_MM_LS(0x1C), &vpe_p_clk.c }, |
| 4763 | { TEST_MM_LS(0x1D), &cam0_clk.c }, |
| 4764 | { TEST_MM_LS(0x1F), &hdmi_app_clk.c }, |
| 4765 | { TEST_MM_LS(0x20), &mdp_vsync_clk.c }, |
| 4766 | { TEST_MM_LS(0x21), &tv_dac_clk.c }, |
| 4767 | { TEST_MM_LS(0x22), &tv_enc_clk.c }, |
| 4768 | { TEST_MM_LS(0x23), &dsi2_esc_clk.c }, |
| 4769 | { TEST_MM_LS(0x25), &mmfpb_clk.c }, |
| 4770 | { TEST_MM_LS(0x25), &mmfpb_a_clk.c }, |
| 4771 | { TEST_MM_LS(0x26), &dsi2_m_p_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4772 | { TEST_MM_LS(0x27), &cam2_clk.c }, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4773 | { TEST_MM_LS(0x28), &vcap_p_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4774 | |
| 4775 | { TEST_MM_HS(0x00), &csi0_clk.c }, |
| 4776 | { TEST_MM_HS(0x01), &csi1_clk.c }, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4777 | { TEST_MM_HS(0x04), &csi_vfe_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4778 | { TEST_MM_HS(0x05), &ijpeg_clk.c }, |
| 4779 | { TEST_MM_HS(0x06), &vfe_clk.c }, |
| 4780 | { TEST_MM_HS(0x07), &gfx2d0_clk.c }, |
| 4781 | { TEST_MM_HS(0x08), &gfx2d1_clk.c }, |
| 4782 | { TEST_MM_HS(0x09), &gfx3d_clk.c }, |
| 4783 | { TEST_MM_HS(0x0A), &jpegd_clk.c }, |
| 4784 | { TEST_MM_HS(0x0B), &vcodec_clk.c }, |
| 4785 | { TEST_MM_HS(0x0F), &mmfab_clk.c }, |
| 4786 | { TEST_MM_HS(0x0F), &mmfab_a_clk.c }, |
| 4787 | { TEST_MM_HS(0x11), &gmem_axi_clk.c }, |
| 4788 | { TEST_MM_HS(0x12), &ijpeg_axi_clk.c }, |
| 4789 | { TEST_MM_HS(0x13), &imem_axi_clk.c }, |
| 4790 | { TEST_MM_HS(0x14), &jpegd_axi_clk.c }, |
| 4791 | { TEST_MM_HS(0x15), &mdp_axi_clk.c }, |
| 4792 | { TEST_MM_HS(0x16), &rot_axi_clk.c }, |
| 4793 | { TEST_MM_HS(0x17), &vcodec_axi_clk.c }, |
| 4794 | { TEST_MM_HS(0x18), &vfe_axi_clk.c }, |
| 4795 | { TEST_MM_HS(0x19), &vpe_axi_clk.c }, |
| 4796 | { TEST_MM_HS(0x1A), &mdp_clk.c }, |
| 4797 | { TEST_MM_HS(0x1B), &rot_clk.c }, |
| 4798 | { TEST_MM_HS(0x1C), &vpe_clk.c }, |
| 4799 | { TEST_MM_HS(0x1E), &hdmi_tv_clk.c }, |
| 4800 | { TEST_MM_HS(0x1F), &mdp_tv_clk.c }, |
| 4801 | { TEST_MM_HS(0x24), &csi0_phy_clk.c }, |
| 4802 | { TEST_MM_HS(0x25), &csi1_phy_clk.c }, |
| 4803 | { TEST_MM_HS(0x26), &csi_pix_clk.c }, |
| 4804 | { TEST_MM_HS(0x27), &csi_rdi_clk.c }, |
| 4805 | { TEST_MM_HS(0x28), &lut_mdp_clk.c }, |
| 4806 | { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c }, |
| 4807 | { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c }, |
| 4808 | { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c }, |
| 4809 | { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4810 | { TEST_MM_HS(0x2D), &csi2_clk.c }, |
| 4811 | { TEST_MM_HS(0x2E), &csi2_phy_clk.c }, |
| 4812 | { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c }, |
| 4813 | { TEST_MM_HS(0x30), &csi_pix1_clk.c }, |
| 4814 | { TEST_MM_HS(0x31), &csi_rdi1_clk.c }, |
| 4815 | { TEST_MM_HS(0x32), &csi_rdi2_clk.c }, |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 4816 | { TEST_MM_HS(0x33), &vcap_clk.c }, |
| 4817 | { TEST_MM_HS(0x34), &vcap_npl_clk.c }, |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 4818 | { TEST_MM_HS(0x34), &gfx3d_axi_clk_8930.c }, |
Tianyi Gou | 7747a96 | 2012-02-03 15:03:55 -0800 | [diff] [blame] | 4819 | { TEST_MM_HS(0x35), &vcap_axi_clk.c }, |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 4820 | { TEST_MM_HS(0x36), &rgb_tv_clk.c }, |
| 4821 | { TEST_MM_HS(0x37), &npl_tv_clk.c }, |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 4822 | { TEST_MM_HS(0x38), &gfx3d_axi_clk_8064.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4823 | |
| 4824 | { TEST_LPA(0x0F), &mi2s_bit_clk.c }, |
| 4825 | { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c }, |
| 4826 | { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c }, |
| 4827 | { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c }, |
| 4828 | { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c }, |
| 4829 | { TEST_LPA(0x14), &pcm_clk.c }, |
| 4830 | { TEST_LPA(0x1D), &audio_slimbus_clk.c }, |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4831 | |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4832 | { TEST_LPA_HS(0x00), &q6_func_clk }, |
| 4833 | |
Stephen Boyd | 46fdf0d | 2011-11-22 12:25:09 -0800 | [diff] [blame] | 4834 | { TEST_CPUL2(0x2), &l2_m_clk }, |
| 4835 | { TEST_CPUL2(0x0), &krait0_m_clk }, |
| 4836 | { TEST_CPUL2(0x1), &krait1_m_clk }, |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 4837 | { TEST_CPUL2(0x4), &krait2_m_clk }, |
| 4838 | { TEST_CPUL2(0x5), &krait3_m_clk }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4839 | }; |
| 4840 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4841 | static struct measure_sel *find_measure_sel(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4842 | { |
| 4843 | int i; |
| 4844 | |
| 4845 | for (i = 0; i < ARRAY_SIZE(measure_mux); i++) |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4846 | if (measure_mux[i].c == c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4847 | return &measure_mux[i]; |
| 4848 | return NULL; |
| 4849 | } |
| 4850 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4851 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4852 | { |
| 4853 | int ret = 0; |
| 4854 | u32 clk_sel; |
| 4855 | struct measure_sel *p; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4856 | struct measure_clk *measure = to_measure_clk(c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4857 | unsigned long flags; |
| 4858 | |
| 4859 | if (!parent) |
| 4860 | return -EINVAL; |
| 4861 | |
| 4862 | p = find_measure_sel(parent); |
| 4863 | if (!p) |
| 4864 | return -EINVAL; |
| 4865 | |
| 4866 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 4867 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4868 | /* |
| 4869 | * Program the test vector, measurement period (sample_ticks) |
| 4870 | * and scaling multiplier. |
| 4871 | */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4872 | measure->sample_ticks = 0x10000; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4873 | clk_sel = p->test_vector & TEST_CLK_SEL_MASK; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4874 | measure->multiplier = 1; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4875 | switch (p->test_vector >> TEST_TYPE_SHIFT) { |
| 4876 | case TEST_TYPE_PER_LS: |
| 4877 | writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG); |
| 4878 | break; |
| 4879 | case TEST_TYPE_PER_HS: |
| 4880 | writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG); |
| 4881 | break; |
| 4882 | case TEST_TYPE_MM_LS: |
| 4883 | writel_relaxed(0x4030D97, CLK_TEST_REG); |
| 4884 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG); |
| 4885 | break; |
| 4886 | case TEST_TYPE_MM_HS: |
| 4887 | writel_relaxed(0x402B800, CLK_TEST_REG); |
| 4888 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG); |
| 4889 | break; |
| 4890 | case TEST_TYPE_LPA: |
| 4891 | writel_relaxed(0x4030D98, CLK_TEST_REG); |
| 4892 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), |
| 4893 | LCC_CLK_LS_DEBUG_CFG_REG); |
| 4894 | break; |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4895 | case TEST_TYPE_LPA_HS: |
| 4896 | writel_relaxed(0x402BC00, CLK_TEST_REG); |
| 4897 | writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0), |
| 4898 | LCC_CLK_HS_DEBUG_CFG_REG); |
| 4899 | break; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4900 | case TEST_TYPE_CPUL2: |
| 4901 | writel_relaxed(0x4030400, CLK_TEST_REG); |
| 4902 | writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4903 | measure->sample_ticks = 0x4000; |
| 4904 | measure->multiplier = 2; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4905 | break; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4906 | default: |
| 4907 | ret = -EPERM; |
| 4908 | } |
| 4909 | /* Make sure test vector is set before starting measurements. */ |
| 4910 | mb(); |
| 4911 | |
| 4912 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 4913 | |
| 4914 | return ret; |
| 4915 | } |
| 4916 | |
| 4917 | /* Sample clock for 'ticks' reference clock ticks. */ |
| 4918 | static u32 run_measurement(unsigned ticks) |
| 4919 | { |
| 4920 | /* Stop counters and set the XO4 counter start value. */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4921 | writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG); |
| 4922 | |
| 4923 | /* Wait for timer to become ready. */ |
| 4924 | while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0) |
| 4925 | cpu_relax(); |
| 4926 | |
| 4927 | /* Run measurement and wait for completion. */ |
| 4928 | writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG); |
| 4929 | while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0) |
| 4930 | cpu_relax(); |
| 4931 | |
| 4932 | /* Stop counters. */ |
| 4933 | writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG); |
| 4934 | |
| 4935 | /* Return measured ticks. */ |
| 4936 | return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0); |
| 4937 | } |
| 4938 | |
| 4939 | |
| 4940 | /* Perform a hardware rate measurement for a given clock. |
| 4941 | FOR DEBUG USE ONLY: Measurements take ~15 ms! */ |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 4942 | static unsigned long measure_clk_get_rate(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4943 | { |
| 4944 | unsigned long flags; |
| 4945 | u32 pdm_reg_backup, ringosc_reg_backup; |
| 4946 | u64 raw_count_short, raw_count_full; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4947 | struct measure_clk *measure = to_measure_clk(c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4948 | unsigned ret; |
| 4949 | |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 4950 | ret = clk_prepare_enable(&cxo_clk.c); |
Stephen Boyd | 3a35f0b | 2012-01-11 16:18:26 -0800 | [diff] [blame] | 4951 | if (ret) { |
| 4952 | pr_warning("CXO clock failed to enable. Can't measure\n"); |
| 4953 | return 0; |
| 4954 | } |
| 4955 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4956 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 4957 | |
| 4958 | /* Enable CXO/4 and RINGOSC branch and root. */ |
| 4959 | pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG); |
| 4960 | ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG); |
| 4961 | writel_relaxed(0x2898, PDM_CLK_NS_REG); |
| 4962 | writel_relaxed(0xA00, RINGOSC_NS_REG); |
| 4963 | |
| 4964 | /* |
| 4965 | * The ring oscillator counter will not reset if the measured clock |
| 4966 | * is not running. To detect this, run a short measurement before |
| 4967 | * the full measurement. If the raw results of the two are the same |
| 4968 | * then the clock must be off. |
| 4969 | */ |
| 4970 | |
| 4971 | /* Run a short measurement. (~1 ms) */ |
| 4972 | raw_count_short = run_measurement(0x1000); |
| 4973 | /* Run a full measurement. (~14 ms) */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4974 | raw_count_full = run_measurement(measure->sample_ticks); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4975 | |
| 4976 | writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG); |
| 4977 | writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG); |
| 4978 | |
| 4979 | /* Return 0 if the clock is off. */ |
| 4980 | if (raw_count_full == raw_count_short) |
| 4981 | ret = 0; |
| 4982 | else { |
| 4983 | /* Compute rate in Hz. */ |
| 4984 | raw_count_full = ((raw_count_full * 10) + 15) * 4800000; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4985 | do_div(raw_count_full, ((measure->sample_ticks * 10) + 35)); |
| 4986 | ret = (raw_count_full * measure->multiplier); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4987 | } |
| 4988 | |
| 4989 | /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */ |
Stephen Boyd | 69da840 | 2011-07-14 17:45:31 -0700 | [diff] [blame] | 4990 | writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4991 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 4992 | |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 4993 | clk_disable_unprepare(&cxo_clk.c); |
Stephen Boyd | 3a35f0b | 2012-01-11 16:18:26 -0800 | [diff] [blame] | 4994 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4995 | return ret; |
| 4996 | } |
| 4997 | #else /* !CONFIG_DEBUG_FS */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4998 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4999 | { |
| 5000 | return -EINVAL; |
| 5001 | } |
| 5002 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 5003 | static unsigned long measure_clk_get_rate(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5004 | { |
| 5005 | return 0; |
| 5006 | } |
| 5007 | #endif /* CONFIG_DEBUG_FS */ |
| 5008 | |
Matt Wagantall | ae05322 | 2012-05-14 19:42:07 -0700 | [diff] [blame] | 5009 | static struct clk_ops clk_ops_measure = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5010 | .set_parent = measure_clk_set_parent, |
| 5011 | .get_rate = measure_clk_get_rate, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5012 | }; |
| 5013 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5014 | static struct measure_clk measure_clk = { |
| 5015 | .c = { |
| 5016 | .dbg_name = "measure_clk", |
Matt Wagantall | ae05322 | 2012-05-14 19:42:07 -0700 | [diff] [blame] | 5017 | .ops = &clk_ops_measure, |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5018 | CLK_INIT(measure_clk.c), |
| 5019 | }, |
| 5020 | .multiplier = 1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5021 | }; |
| 5022 | |
Tianyi Gou | a8b3cce | 2011-11-08 14:37:26 -0800 | [diff] [blame] | 5023 | static struct clk_lookup msm_clocks_8064[] = { |
Stephen Boyd | 72a8035 | 2012-01-26 15:57:38 -0800 | [diff] [blame] | 5024 | CLK_LOOKUP("xo", cxo_a_clk.c, ""), |
| 5025 | CLK_LOOKUP("xo", pxo_a_clk.c, ""), |
Mohan Pallaka | 804ca59 | 2012-06-14 14:37:38 +0530 | [diff] [blame] | 5026 | CLK_LOOKUP("pwm_clk", cxo_clk.c, "0-0048"), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5027 | CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"), |
| 5028 | CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"), |
| 5029 | CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"), |
| 5030 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"), |
| 5031 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"), |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 5032 | CLK_LOOKUP("xo", cxo_clk.c, "pil_gss"), |
Stephen Boyd | 69d35e3 | 2012-02-14 15:33:30 -0800 | [diff] [blame] | 5033 | CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"), |
Stephen Boyd | 5a190a8 | 2012-03-01 14:45:15 -0800 | [diff] [blame] | 5034 | CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5035 | CLK_LOOKUP("pll2", pll2_clk.c, NULL), |
| 5036 | CLK_LOOKUP("pll8", pll8_clk.c, NULL), |
| 5037 | CLK_LOOKUP("pll4", pll4_clk.c, NULL), |
| 5038 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5039 | |
Matt Wagantall | d75f131 | 2012-05-23 16:17:35 -0700 | [diff] [blame] | 5040 | CLK_LOOKUP("bus_clk", afab_clk.c, ""), |
| 5041 | CLK_LOOKUP("bus_clk", afab_a_clk.c, ""), |
| 5042 | CLK_LOOKUP("bus_clk", cfpb_clk.c, ""), |
| 5043 | CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""), |
| 5044 | CLK_LOOKUP("bus_clk", dfab_clk.c, ""), |
| 5045 | CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""), |
| 5046 | CLK_LOOKUP("mem_clk", ebi1_clk.c, ""), |
| 5047 | CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""), |
| 5048 | CLK_LOOKUP("bus_clk", mmfab_clk.c, ""), |
| 5049 | CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""), |
| 5050 | CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""), |
| 5051 | CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""), |
| 5052 | CLK_LOOKUP("bus_clk", sfab_clk.c, ""), |
| 5053 | CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""), |
| 5054 | CLK_LOOKUP("bus_clk", sfpb_clk.c, ""), |
| 5055 | CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""), |
| 5056 | |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5057 | CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5058 | CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5059 | CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"), |
| 5060 | CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"), |
| 5061 | CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"), |
Stephen Boyd | d7a143a | 2012-02-16 17:59:26 -0800 | [diff] [blame] | 5062 | CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5063 | CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"), |
| 5064 | CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"), |
| 5065 | CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"), |
| 5066 | CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"), |
| 5067 | CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5068 | CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"), |
Gagan Mac | bc5f81d | 2012-04-04 15:03:12 -0600 | [diff] [blame] | 5069 | CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"), |
| 5070 | CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5071 | |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5072 | CLK_LOOKUP("ebi1_clk", ebi1_clk.c, ""), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5073 | CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, ""), |
| 5074 | CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"), |
| 5075 | CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5076 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5077 | CLK_LOOKUP("core_clk", gp0_clk.c, ""), |
| 5078 | CLK_LOOKUP("core_clk", gp1_clk.c, ""), |
| 5079 | CLK_LOOKUP("core_clk", gp2_clk.c, ""), |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame] | 5080 | CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5081 | CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), |
| 5082 | CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), |
| 5083 | CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), |
| 5084 | CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""), |
| 5085 | CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""), |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame] | 5086 | CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"), |
David Keitel | 3c40fc5 | 2012-02-09 17:53:52 -0800 | [diff] [blame] | 5087 | CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5088 | CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), |
Jing Lin | 04601f9 | 2012-02-05 15:36:07 -0800 | [diff] [blame] | 5089 | CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5090 | CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"), |
Stepan Moskovchenko | 6499900 | 2012-01-31 15:52:59 -0800 | [diff] [blame] | 5091 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "spi_qsd.0"), |
Joel King | 8f839b9 | 2012-04-01 14:37:46 -0700 | [diff] [blame] | 5092 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "qup_i2c.5"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5093 | CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""), |
| 5094 | CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""), |
| 5095 | CLK_LOOKUP("core_clk", pdm_clk.c, ""), |
Tianyi Gou | 50f2381 | 2012-02-06 16:04:19 -0800 | [diff] [blame] | 5096 | CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"), |
Tianyi Gou | 05e0110 | 2012-02-08 22:15:49 -0800 | [diff] [blame] | 5097 | CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"), |
Tianyi Gou | 43208a0 | 2011-09-27 15:35:13 -0700 | [diff] [blame] | 5098 | CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"), |
| 5099 | CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"), |
| 5100 | CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"), |
| 5101 | CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5102 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""), |
| 5103 | CLK_LOOKUP("core_clk", tssc_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5104 | CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"), |
| 5105 | CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"), |
| 5106 | CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5107 | CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""), |
| 5108 | CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""), |
| 5109 | CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5110 | CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""), |
| 5111 | CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""), |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 5112 | CLK_LOOKUP("src_clk", sata_src_clk.c, ""), |
| 5113 | CLK_LOOKUP("core_rxoob_clk", sata_rxoob_clk.c, ""), |
| 5114 | CLK_LOOKUP("core_pmalive_clk", sata_pmalive_clk.c, ""), |
| 5115 | CLK_LOOKUP("bus_clk", sata_a_clk.c, ""), |
| 5116 | CLK_LOOKUP("iface_clk", sata_p_clk.c, ""), |
| 5117 | CLK_LOOKUP("slave_iface_clk", sfab_sata_s_p_clk.c, ""), |
Ramesh Masavarapu | 2831191 | 2011-10-27 11:04:12 -0700 | [diff] [blame] | 5118 | CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"), |
| 5119 | CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"), |
| 5120 | CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"), |
| 5121 | CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"), |
| 5122 | CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"), |
| 5123 | CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5124 | CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame] | 5125 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"), |
David Keitel | 3c40fc5 | 2012-02-09 17:53:52 -0800 | [diff] [blame] | 5126 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "qup_i2c.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5127 | CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), |
Jing Lin | 04601f9 | 2012-02-05 15:36:07 -0800 | [diff] [blame] | 5128 | CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5129 | CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"), |
Stepan Moskovchenko | 6499900 | 2012-01-31 15:52:59 -0800 | [diff] [blame] | 5130 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"), |
Joel King | 8f839b9 | 2012-04-01 14:37:46 -0700 | [diff] [blame] | 5131 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "qup_i2c.5"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5132 | CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, ""), |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame] | 5133 | CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, "msm_serial_hsl.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5134 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""), |
| 5135 | CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5136 | CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"), |
Manu Gautam | 7483f17 | 2011-11-08 15:22:26 +0530 | [diff] [blame] | 5137 | CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"), |
| 5138 | CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"), |
Tianyi Gou | 43208a0 | 2011-09-27 15:35:13 -0700 | [diff] [blame] | 5139 | CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"), |
| 5140 | CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"), |
| 5141 | CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"), |
| 5142 | CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"), |
Niranjana Vishwanathapura | 06f8933 | 2012-05-03 17:11:13 -0600 | [diff] [blame] | 5143 | CLK_LOOKUP("iface_clk", pcie_p_clk.c, "msm_pcie"), |
| 5144 | CLK_LOOKUP("ref_clk", pcie_phy_ref_clk.c, "msm_pcie"), |
| 5145 | CLK_LOOKUP("bus_clk", pcie_a_clk.c, "msm_pcie"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5146 | CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"), |
| 5147 | CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5148 | CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""), |
| 5149 | CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""), |
| 5150 | CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""), |
| 5151 | CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5152 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"), |
Sreesudhan Ramakrish Ramkumar | 3381da7 | 2012-01-27 08:08:32 -0800 | [diff] [blame] | 5153 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"), |
Sreesudhan Ramakrish Ramkumar | 8002a79 | 2012-04-09 17:42:58 -0700 | [diff] [blame] | 5154 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"), |
Sreesudhan Ramakrish Ramkumar | 6c6f57c | 2012-02-21 15:12:44 -0800 | [diff] [blame] | 5155 | CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5156 | CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"), |
| 5157 | CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"), |
| 5158 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"), |
| 5159 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"), |
| 5160 | CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"), |
| 5161 | CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"), |
| 5162 | CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"), |
| 5163 | CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"), |
| 5164 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"), |
| 5165 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"), |
| 5166 | CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"), |
| 5167 | CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"), |
| 5168 | CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"), |
| 5169 | CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"), |
| 5170 | CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"), |
| 5171 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5172 | csiphy_timer_src_clk.c, "msm_csiphy.0"), |
| 5173 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5174 | csiphy_timer_src_clk.c, "msm_csiphy.1"), |
| 5175 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5176 | csiphy_timer_src_clk.c, "msm_csiphy.2"), |
| 5177 | CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"), |
| 5178 | CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"), |
| 5179 | CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5180 | CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"), |
| 5181 | CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"), |
| 5182 | CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"), |
| 5183 | CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"), |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 5184 | CLK_LOOKUP("rgb_clk", rgb_tv_clk.c, ""), |
| 5185 | CLK_LOOKUP("npl_clk", npl_tv_clk.c, ""), |
| 5186 | |
Pu Chen | 86b4be9 | 2011-11-03 17:27:57 -0700 | [diff] [blame] | 5187 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5188 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5189 | CLK_LOOKUP("bus_clk", |
| 5190 | gfx3d_axi_clk_8064.c, "footswitch-8x60.2"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5191 | CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""), |
Terence Hampson | 2e1705f | 2012-04-11 19:55:29 -0400 | [diff] [blame] | 5192 | CLK_LOOKUP("iface_clk", vcap_p_clk.c, "msm_vcap.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5193 | CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"), |
| 5194 | CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5195 | CLK_LOOKUP("core_clk", vcap_clk.c, ""), |
Terence Hampson | 2e1705f | 2012-04-11 19:55:29 -0400 | [diff] [blame] | 5196 | CLK_LOOKUP("core_clk", vcap_clk.c, "msm_vcap.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5197 | CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5198 | CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""), |
Terence Hampson | 2e1705f | 2012-04-11 19:55:29 -0400 | [diff] [blame] | 5199 | CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, "msm_vcap.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5200 | CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5201 | CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"), |
| 5202 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5203 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5204 | CLK_LOOKUP("core_clk", jpegd_clk.c, ""), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5205 | CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5206 | CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5207 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5208 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5209 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5210 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5211 | CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5212 | CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"), |
Matt Wagantall | 6128631 | 2012-02-22 15:55:09 -0800 | [diff] [blame] | 5213 | CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5214 | CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"), |
| 5215 | CLK_LOOKUP("div_clk", tv_src_div_clk.c, ""), |
Greg Grisco | fa47b53 | 2011-11-11 10:32:06 -0800 | [diff] [blame] | 5216 | CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5217 | CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5218 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"), |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 5219 | CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5220 | CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"), |
Aravind Venkateswaran | 0507c8c | 2012-02-16 17:16:05 -0800 | [diff] [blame] | 5221 | CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"), |
Ujwal Patel | d041f98 | 2012-03-27 19:51:44 -0700 | [diff] [blame] | 5222 | CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5223 | CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5224 | CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5225 | CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5226 | CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5227 | CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"), |
| 5228 | CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"), |
| 5229 | CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"), |
| 5230 | CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"), |
| 5231 | CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"), |
| 5232 | CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"), |
| 5233 | CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5234 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"), |
| 5235 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5236 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"), |
| 5237 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"), |
| 5238 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5239 | CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"), |
| 5240 | CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"), |
| 5241 | CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"), |
| 5242 | CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"), |
Pu Chen | 86b4be9 | 2011-11-03 17:27:57 -0700 | [diff] [blame] | 5243 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5244 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"), |
Aravind Venkateswaran | 0507c8c | 2012-02-16 17:16:05 -0800 | [diff] [blame] | 5245 | CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"), |
| 5246 | CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5247 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5248 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5249 | CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""), |
Matt Wagantall | 5d44ef2 | 2012-01-23 11:01:05 -0800 | [diff] [blame] | 5250 | CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5251 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5252 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"), |
Stepan Moskovchenko | 279b785 | 2012-01-31 20:42:46 -0800 | [diff] [blame] | 5253 | CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5254 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5255 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"), |
Greg Grisco | fa47b53 | 2011-11-11 10:32:06 -0800 | [diff] [blame] | 5256 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5257 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5258 | CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5259 | CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"), |
Kevin Chan | b20742b | 2012-02-27 15:47:35 -0800 | [diff] [blame] | 5260 | CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"), |
Matt Wagantall | 6128631 | 2012-02-22 15:55:09 -0800 | [diff] [blame] | 5261 | CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5262 | |
Patrick Lai | 04baee94 | 2012-05-01 14:38:47 -0700 | [diff] [blame] | 5263 | CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, |
| 5264 | "msm-dai-q6-mi2s"), |
| 5265 | CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, |
| 5266 | "msm-dai-q6-mi2s"), |
Kuirong Wang | a9c3acc | 2012-02-09 17:00:45 -0800 | [diff] [blame] | 5267 | CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c, |
| 5268 | "msm-dai-q6.1"), |
| 5269 | CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c, |
| 5270 | "msm-dai-q6.1"), |
| 5271 | CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c, |
| 5272 | "msm-dai-q6.5"), |
| 5273 | CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c, |
| 5274 | "msm-dai-q6.5"), |
| 5275 | CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c, |
| 5276 | "msm-dai-q6.16384"), |
| 5277 | CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c, |
| 5278 | "msm-dai-q6.16384"), |
| 5279 | CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c, |
| 5280 | "msm-dai-q6.4"), |
| 5281 | CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c, |
| 5282 | "msm-dai-q6.4"), |
| 5283 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"), |
Kiran Kandi | 5f4ab69 | 2012-02-23 11:23:56 -0800 | [diff] [blame] | 5284 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5285 | CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""), |
Tianyi Gou | 44a81b0 | 2012-02-06 17:49:07 -0800 | [diff] [blame] | 5286 | CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5287 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""), |
| 5288 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""), |
| 5289 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""), |
| 5290 | CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""), |
| 5291 | CLK_LOOKUP("core_clk", rot_axi_clk.c, ""), |
| 5292 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""), |
| 5293 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""), |
| 5294 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""), |
| 5295 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5296 | CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, ""), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5297 | |
| 5298 | CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL), |
| 5299 | CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"), |
| 5300 | CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.0"), |
| 5301 | CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.1"), |
| 5302 | CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"), |
| 5303 | CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"), |
| 5304 | CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"), |
| 5305 | CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"), |
| 5306 | CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"), |
| 5307 | CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"), |
| 5308 | CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"), |
Ramesh Masavarapu | a1bc0e4 | 2012-03-05 07:42:48 -0800 | [diff] [blame] | 5309 | CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5310 | |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5311 | CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"), |
| 5312 | CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"), |
| 5313 | CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"), |
| 5314 | CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"), |
| 5315 | CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5316 | |
Stepan Moskovchenko | 279b785 | 2012-01-31 20:42:46 -0800 | [diff] [blame] | 5317 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"), |
| 5318 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"), |
| 5319 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"), |
| 5320 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"), |
| 5321 | CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"), |
| 5322 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"), |
| 5323 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"), |
| 5324 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"), |
| 5325 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5326 | CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.9"), |
| 5327 | CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.10"), |
Stepan Moskovchenko | 279b785 | 2012-01-31 20:42:46 -0800 | [diff] [blame] | 5328 | CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"), |
| 5329 | |
Deepak Kotur | 954b178 | 2012-04-24 17:58:19 -0700 | [diff] [blame] | 5330 | CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"), |
| 5331 | CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"), |
| 5332 | CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"), |
| 5333 | CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"), |
| 5334 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"), |
Stephen Boyd | 7b973de | 2012-03-09 12:26:16 -0800 | [diff] [blame] | 5335 | CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"), |
| 5336 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"), |
| 5337 | |
Jeff Ohlstein | 8c116c7 | 2011-10-27 17:34:48 -0700 | [diff] [blame] | 5338 | CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5339 | CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""), |
| 5340 | CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5341 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5342 | CLK_LOOKUP("l2_mclk", l2_m_clk, ""), |
| 5343 | CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""), |
| 5344 | CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""), |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 5345 | CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""), |
| 5346 | CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5347 | }; |
| 5348 | |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5349 | static struct clk_lookup msm_clocks_8960[] = { |
Stephen Boyd | 72a8035 | 2012-01-26 15:57:38 -0800 | [diff] [blame] | 5350 | CLK_LOOKUP("xo", cxo_a_clk.c, ""), |
| 5351 | CLK_LOOKUP("xo", pxo_a_clk.c, ""), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5352 | CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"), |
| 5353 | CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"), |
| 5354 | CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"), |
| 5355 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"), |
| 5356 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"), |
Stephen Boyd | 69d35e3 | 2012-02-14 15:33:30 -0800 | [diff] [blame] | 5357 | CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"), |
Stephen Boyd | 5a190a8 | 2012-03-01 14:45:15 -0800 | [diff] [blame] | 5358 | CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5359 | CLK_LOOKUP("pll2", pll2_clk.c, NULL), |
| 5360 | CLK_LOOKUP("pll8", pll8_clk.c, NULL), |
| 5361 | CLK_LOOKUP("pll4", pll4_clk.c, NULL), |
| 5362 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5363 | |
Matt Wagantall | d75f131 | 2012-05-23 16:17:35 -0700 | [diff] [blame] | 5364 | CLK_LOOKUP("bus_clk", afab_clk.c, ""), |
| 5365 | CLK_LOOKUP("bus_clk", afab_a_clk.c, ""), |
| 5366 | CLK_LOOKUP("bus_clk", cfpb_clk.c, ""), |
| 5367 | CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""), |
| 5368 | CLK_LOOKUP("bus_clk", dfab_clk.c, ""), |
| 5369 | CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""), |
| 5370 | CLK_LOOKUP("mem_clk", ebi1_clk.c, ""), |
| 5371 | CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""), |
| 5372 | CLK_LOOKUP("bus_clk", mmfab_clk.c, ""), |
| 5373 | CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""), |
| 5374 | CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""), |
| 5375 | CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""), |
| 5376 | CLK_LOOKUP("bus_clk", sfab_clk.c, ""), |
| 5377 | CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""), |
| 5378 | CLK_LOOKUP("bus_clk", sfpb_clk.c, ""), |
| 5379 | CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""), |
| 5380 | |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5381 | CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5382 | CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5383 | CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"), |
| 5384 | CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"), |
| 5385 | CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"), |
Stephen Boyd | d7a143a | 2012-02-16 17:59:26 -0800 | [diff] [blame] | 5386 | CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5387 | CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"), |
| 5388 | CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"), |
| 5389 | CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"), |
| 5390 | CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"), |
| 5391 | CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5392 | CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"), |
Gagan Mac | bc5f81d | 2012-04-04 15:03:12 -0600 | [diff] [blame] | 5393 | CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"), |
| 5394 | CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5395 | |
| 5396 | CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5397 | CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL), |
| 5398 | CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"), |
| 5399 | CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5400 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5401 | CLK_LOOKUP("core_clk", gp0_clk.c, ""), |
| 5402 | CLK_LOOKUP("core_clk", gp1_clk.c, ""), |
| 5403 | CLK_LOOKUP("core_clk", gp2_clk.c, ""), |
| 5404 | CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""), |
| 5405 | CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), |
| 5406 | CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), |
| 5407 | CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 5408 | CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"), |
| 5409 | CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5410 | CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""), |
Stepan Moskovchenko | 2b4b1cd | 2012-03-29 18:21:04 -0700 | [diff] [blame] | 5411 | CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hsl.1"), |
Mayank Rana | e009c92 | 2012-03-22 03:02:06 +0530 | [diff] [blame] | 5412 | CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, "msm_serial_hs.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5413 | CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""), |
| 5414 | CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""), |
| 5415 | CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5416 | CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5417 | CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5418 | CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"), |
| 5419 | CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5420 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""), |
| 5421 | CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""), |
| 5422 | CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""), |
| 5423 | CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5424 | CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5425 | CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5426 | CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5427 | CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5428 | CLK_LOOKUP("core_clk", pdm_clk.c, ""), |
Vikram Mulukutla | dd0a237 | 2011-09-19 15:58:21 -0700 | [diff] [blame] | 5429 | CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"), |
Matt Wagantall | c120529 | 2011-08-11 17:19:31 -0700 | [diff] [blame] | 5430 | CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5431 | CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"), |
| 5432 | CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"), |
| 5433 | CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"), |
| 5434 | CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"), |
| 5435 | CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5436 | CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5437 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""), |
| 5438 | CLK_LOOKUP("core_clk", tssc_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5439 | CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"), |
| 5440 | CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5441 | CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""), |
| 5442 | CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""), |
| 5443 | CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""), |
| 5444 | CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""), |
| 5445 | CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""), |
| 5446 | CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5447 | CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"), |
| 5448 | CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"), |
| 5449 | CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"), |
| 5450 | CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"), |
| 5451 | CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"), |
Matt Wagantall | c4b3a4d | 2011-08-17 16:58:39 -0700 | [diff] [blame] | 5452 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"), |
Matt Wagantall | e0b1145 | 2011-09-13 17:25:33 -0700 | [diff] [blame] | 5453 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"), |
Matt Wagantall | c4b3a4d | 2011-08-17 16:58:39 -0700 | [diff] [blame] | 5454 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"), |
Matt Wagantall | e0b1145 | 2011-09-13 17:25:33 -0700 | [diff] [blame] | 5455 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5456 | CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5457 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5458 | CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5459 | CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"), |
| 5460 | CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 5461 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"), |
| 5462 | CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5463 | CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""), |
Stepan Moskovchenko | 2b4b1cd | 2012-03-29 18:21:04 -0700 | [diff] [blame] | 5464 | CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hsl.1"), |
Mayank Rana | e009c92 | 2012-03-22 03:02:06 +0530 | [diff] [blame] | 5465 | CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "msm_serial_hs.1"), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5466 | CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5467 | CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5468 | CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5469 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""), |
| 5470 | CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""), |
| 5471 | CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5472 | CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5473 | CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"), |
| 5474 | CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"), |
| 5475 | CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"), |
| 5476 | CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"), |
| 5477 | CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"), |
Matt Wagantall | e1a8606 | 2011-08-18 17:46:10 -0700 | [diff] [blame] | 5478 | CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"), |
| 5479 | CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5480 | CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""), |
| 5481 | CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""), |
| 5482 | CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""), |
| 5483 | CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""), |
Kevin Chan | 09f4e66 | 2011-12-16 08:17:02 -0800 | [diff] [blame] | 5484 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"), |
| 5485 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"), |
| 5486 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5487 | CLK_LOOKUP("cam_clk", cam2_clk.c, NULL), |
Sreesudhan Ramakrish Ramkumar | 8f11b8b | 2012-01-04 17:09:05 -0800 | [diff] [blame] | 5488 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"), |
Sreesudhan Ramakrish Ramkumar | 3381da7 | 2012-01-27 08:08:32 -0800 | [diff] [blame] | 5489 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5490 | CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"), |
| 5491 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5492 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5493 | CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"), |
| 5494 | CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5495 | CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5496 | CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"), |
| 5497 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5498 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"), |
Kevin Chan | e12c667 | 2011-10-26 11:55:26 -0700 | [diff] [blame] | 5499 | CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"), |
| 5500 | CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5501 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL), |
| 5502 | CLK_LOOKUP("csi_clk", csi2_clk.c, NULL), |
| 5503 | CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"), |
| 5504 | CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"), |
| 5505 | CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"), |
| 5506 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL), |
| 5507 | CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL), |
Kevin Chan | f6216f2 | 2011-10-25 18:40:11 -0700 | [diff] [blame] | 5508 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5509 | csiphy_timer_src_clk.c, "msm_csiphy.0"), |
| 5510 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5511 | csiphy_timer_src_clk.c, "msm_csiphy.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5512 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5513 | csiphy_timer_src_clk.c, "msm_csiphy.2"), |
Kevin Chan | f6216f2 | 2011-10-25 18:40:11 -0700 | [diff] [blame] | 5514 | CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"), |
| 5515 | CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5516 | CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5517 | CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"), |
| 5518 | CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"), |
| 5519 | CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"), |
| 5520 | CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5521 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5522 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5523 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5524 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5525 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5526 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"), |
| 5527 | CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5528 | CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"), |
| 5529 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5530 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"), |
Kalyani Oruganti | 465d1e1 | 2012-05-15 10:23:05 -0700 | [diff] [blame] | 5531 | CLK_LOOKUP("core_clk", jpegd_clk.c, "msm_mercury.0"), |
| 5532 | CLK_LOOKUP("iface_clk", jpegd_p_clk.c, "msm_mercury.0"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5533 | CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5534 | CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5535 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5536 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5537 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5538 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5539 | CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5540 | CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5541 | CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"), |
| 5542 | CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5543 | CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5544 | CLK_LOOKUP("enc_clk", tv_enc_clk.c, "tvenc.0"), |
| 5545 | CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"), |
Matt Wagantall | 3f7660b | 2011-08-17 21:25:13 -0700 | [diff] [blame] | 5546 | CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5547 | CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5548 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"), |
| 5549 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5550 | CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5551 | CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"), |
Matt Wagantall | 5a4f1ba | 2011-08-18 18:13:03 -0700 | [diff] [blame] | 5552 | CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"), |
Kevin Chan | a085312 | 2011-11-07 19:48:44 -0800 | [diff] [blame] | 5553 | CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5554 | CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5555 | CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5556 | CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5557 | CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5558 | CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"), |
| 5559 | CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"), |
| 5560 | CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"), |
| 5561 | CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"), |
| 5562 | CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"), |
| 5563 | CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"), |
| 5564 | CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5565 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"), |
| 5566 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5567 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"), |
| 5568 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5569 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5570 | CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"), |
| 5571 | CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"), |
| 5572 | CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"), |
| 5573 | CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5574 | CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5575 | CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5576 | CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5577 | CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5578 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5579 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"), |
Matt Wagantall | 5a4f1ba | 2011-08-18 18:13:03 -0700 | [diff] [blame] | 5580 | CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"), |
| 5581 | CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5582 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5583 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5584 | CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""), |
Matt Wagantall | 5d44ef2 | 2012-01-23 11:01:05 -0800 | [diff] [blame] | 5585 | CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5586 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5587 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | e604d71 | 2011-10-21 15:38:18 -0700 | [diff] [blame] | 5588 | CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5589 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5590 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5591 | CLK_LOOKUP("iface_clk", tv_enc_p_clk.c, "tvenc.0"), |
Matt Wagantall | 3f7660b | 2011-08-17 21:25:13 -0700 | [diff] [blame] | 5592 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5593 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5594 | CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5595 | CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"), |
Kevin Chan | a085312 | 2011-11-07 19:48:44 -0800 | [diff] [blame] | 5596 | CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5597 | CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"), |
Patrick Lai | 04baee94 | 2012-05-01 14:38:47 -0700 | [diff] [blame] | 5598 | CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, |
| 5599 | "msm-dai-q6-mi2s"), |
| 5600 | CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, |
| 5601 | "msm-dai-q6-mi2s"), |
Kuirong Wang | a9c3acc | 2012-02-09 17:00:45 -0800 | [diff] [blame] | 5602 | CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c, |
| 5603 | "msm-dai-q6.1"), |
| 5604 | CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c, |
| 5605 | "msm-dai-q6.1"), |
| 5606 | CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c, |
| 5607 | "msm-dai-q6.5"), |
| 5608 | CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c, |
| 5609 | "msm-dai-q6.5"), |
| 5610 | CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c, |
| 5611 | "msm-dai-q6.16384"), |
| 5612 | CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c, |
| 5613 | "msm-dai-q6.16384"), |
| 5614 | CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c, |
| 5615 | "msm-dai-q6.4"), |
| 5616 | CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c, |
| 5617 | "msm-dai-q6.4"), |
| 5618 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"), |
Kiran Kandi | 5f4ab69 | 2012-02-23 11:23:56 -0800 | [diff] [blame] | 5619 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5620 | CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL), |
Tianyi Gou | 44a81b0 | 2012-02-06 17:49:07 -0800 | [diff] [blame] | 5621 | CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"), |
Matt Wagantall | e604d71 | 2011-10-21 15:38:18 -0700 | [diff] [blame] | 5622 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"), |
| 5623 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"), |
| 5624 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"), |
| 5625 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"), |
| 5626 | CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"), |
| 5627 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"), |
| 5628 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"), |
| 5629 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"), |
| 5630 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"), |
| 5631 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"), |
| 5632 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"), |
| 5633 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"), |
Gopikrishnaiah Anandan | 4d05ed3 | 2012-01-13 11:08:44 -0800 | [diff] [blame] | 5634 | |
| 5635 | CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"), |
| 5636 | CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"), |
| 5637 | CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"), |
| 5638 | CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"), |
| 5639 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"), |
Stephen Boyd | 7b973de | 2012-03-09 12:26:16 -0800 | [diff] [blame] | 5640 | CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"), |
| 5641 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"), |
Gopikrishnaiah Anandan | 4d05ed3 | 2012-01-13 11:08:44 -0800 | [diff] [blame] | 5642 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5643 | CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5644 | CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5645 | CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"), |
| 5646 | CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"), |
| 5647 | CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"), |
| 5648 | CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"), |
| 5649 | CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"), |
Yan He | 160633e | 2011-06-30 12:18:56 -0700 | [diff] [blame] | 5650 | CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"), |
Stephen Boyd | 1c51a49 | 2011-10-26 12:11:47 -0700 | [diff] [blame] | 5651 | CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"), |
Stephen Boyd | ef5d1c4 | 2011-12-15 20:47:14 -0800 | [diff] [blame] | 5652 | CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"), |
Ramesh Masavarapu | a1bc0e4 | 2012-03-05 07:42:48 -0800 | [diff] [blame] | 5653 | CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5654 | |
Matt Wagantall | e1a8606 | 2011-08-18 17:46:10 -0700 | [diff] [blame] | 5655 | CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5656 | CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""), |
| 5657 | CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""), |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5658 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5659 | CLK_LOOKUP("l2_mclk", l2_m_clk, ""), |
| 5660 | CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""), |
| 5661 | CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""), |
| 5662 | CLK_LOOKUP("q6sw_clk", q6sw_clk, ""), |
| 5663 | CLK_LOOKUP("q6fw_clk", q6fw_clk, ""), |
| 5664 | CLK_LOOKUP("q6_func_clk", q6_func_clk, ""), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5665 | }; |
| 5666 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5667 | static struct clk_lookup msm_clocks_8930[] = { |
Stephen Boyd | be1a739 | 2012-04-02 20:17:11 -0700 | [diff] [blame] | 5668 | CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5669 | CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"), |
| 5670 | CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"), |
| 5671 | CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"), |
| 5672 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"), |
| 5673 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"), |
| 5674 | CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"), |
| 5675 | CLK_LOOKUP("pll2", pll2_clk.c, NULL), |
| 5676 | CLK_LOOKUP("pll8", pll8_clk.c, NULL), |
| 5677 | CLK_LOOKUP("pll4", pll4_clk.c, NULL), |
| 5678 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
| 5679 | |
Matt Wagantall | d75f131 | 2012-05-23 16:17:35 -0700 | [diff] [blame] | 5680 | CLK_LOOKUP("bus_clk", afab_clk.c, ""), |
| 5681 | CLK_LOOKUP("bus_clk", afab_a_clk.c, ""), |
| 5682 | CLK_LOOKUP("bus_clk", cfpb_clk.c, ""), |
| 5683 | CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""), |
| 5684 | CLK_LOOKUP("bus_clk", dfab_clk.c, ""), |
| 5685 | CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""), |
| 5686 | CLK_LOOKUP("mem_clk", ebi1_clk.c, ""), |
| 5687 | CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""), |
| 5688 | CLK_LOOKUP("bus_clk", mmfab_clk.c, ""), |
| 5689 | CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""), |
| 5690 | CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""), |
| 5691 | CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""), |
| 5692 | CLK_LOOKUP("bus_clk", sfab_clk.c, ""), |
| 5693 | CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""), |
| 5694 | CLK_LOOKUP("bus_clk", sfpb_clk.c, ""), |
| 5695 | CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""), |
| 5696 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5697 | CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5698 | CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5699 | CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"), |
| 5700 | CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"), |
| 5701 | CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"), |
| 5702 | CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"), |
| 5703 | CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"), |
| 5704 | CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"), |
| 5705 | CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"), |
| 5706 | CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"), |
| 5707 | CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5708 | CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"), |
Gagan Mac | bc5f81d | 2012-04-04 15:03:12 -0600 | [diff] [blame] | 5709 | CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"), |
| 5710 | CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5711 | |
| 5712 | CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5713 | CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL), |
| 5714 | CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"), |
| 5715 | CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"), |
| 5716 | |
| 5717 | CLK_LOOKUP("core_clk", gp0_clk.c, ""), |
| 5718 | CLK_LOOKUP("core_clk", gp1_clk.c, ""), |
| 5719 | CLK_LOOKUP("core_clk", gp2_clk.c, ""), |
| 5720 | CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""), |
| 5721 | CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), |
| 5722 | CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), |
| 5723 | CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), |
| 5724 | CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"), |
| 5725 | CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"), |
| 5726 | CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""), |
| 5727 | CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""), |
| 5728 | CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""), |
| 5729 | CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""), |
| 5730 | CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""), |
| 5731 | CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""), |
| 5732 | CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"), |
| 5733 | CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), |
| 5734 | CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"), |
| 5735 | CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"), |
| 5736 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""), |
| 5737 | CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""), |
| 5738 | CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""), |
| 5739 | CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""), |
| 5740 | CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"), |
| 5741 | CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"), |
| 5742 | CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""), |
| 5743 | CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"), |
| 5744 | CLK_LOOKUP("core_clk", pdm_clk.c, ""), |
| 5745 | CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"), |
| 5746 | CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"), |
| 5747 | CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"), |
| 5748 | CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"), |
| 5749 | CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"), |
| 5750 | CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"), |
| 5751 | CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"), |
| 5752 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""), |
| 5753 | CLK_LOOKUP("core_clk", tssc_clk.c, ""), |
| 5754 | CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"), |
| 5755 | CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"), |
| 5756 | CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""), |
| 5757 | CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""), |
| 5758 | CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""), |
| 5759 | CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""), |
| 5760 | CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""), |
| 5761 | CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""), |
| 5762 | CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"), |
| 5763 | CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"), |
| 5764 | CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"), |
| 5765 | CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"), |
| 5766 | CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"), |
| 5767 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"), |
| 5768 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"), |
| 5769 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"), |
| 5770 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"), |
| 5771 | CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), |
| 5772 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"), |
| 5773 | CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), |
| 5774 | CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"), |
| 5775 | CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"), |
| 5776 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"), |
| 5777 | CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"), |
| 5778 | CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""), |
| 5779 | CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""), |
| 5780 | CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"), |
| 5781 | CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"), |
| 5782 | CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""), |
| 5783 | CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"), |
| 5784 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""), |
| 5785 | CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""), |
| 5786 | CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""), |
| 5787 | CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"), |
| 5788 | CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"), |
| 5789 | CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"), |
| 5790 | CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"), |
| 5791 | CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"), |
| 5792 | CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"), |
| 5793 | CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"), |
| 5794 | CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"), |
| 5795 | CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""), |
| 5796 | CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""), |
| 5797 | CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""), |
| 5798 | CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5799 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"), |
Hody Hung | 994f462 | 2012-04-24 10:27:45 -0700 | [diff] [blame] | 5800 | CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"), |
Sreesudhan Ramakrish Ramkumar | 981c82c | 2012-04-30 17:31:37 -0700 | [diff] [blame] | 5801 | CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5802 | CLK_LOOKUP("cam_clk", cam2_clk.c, NULL), |
| 5803 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"), |
| 5804 | CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"), |
| 5805 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"), |
| 5806 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"), |
| 5807 | CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"), |
| 5808 | CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"), |
| 5809 | CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"), |
| 5810 | CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"), |
| 5811 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"), |
| 5812 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"), |
| 5813 | CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"), |
| 5814 | CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"), |
| 5815 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL), |
| 5816 | CLK_LOOKUP("csi_clk", csi2_clk.c, NULL), |
| 5817 | CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"), |
| 5818 | CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"), |
| 5819 | CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"), |
| 5820 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL), |
| 5821 | CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL), |
| 5822 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5823 | csiphy_timer_src_clk.c, "msm_csiphy.0"), |
| 5824 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5825 | csiphy_timer_src_clk.c, "msm_csiphy.1"), |
| 5826 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5827 | csiphy_timer_src_clk.c, "msm_csiphy.2"), |
| 5828 | CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"), |
| 5829 | CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"), |
| 5830 | CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5831 | CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"), |
| 5832 | CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5833 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"), |
| 5834 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"), |
| 5835 | CLK_LOOKUP("bus_clk", |
| 5836 | gfx3d_axi_clk_8930.c, "footswitch-8x60.2"), |
| 5837 | CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5838 | CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"), |
| 5839 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5840 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5841 | CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5842 | CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5843 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5844 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5845 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5846 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"), |
| 5847 | CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"), |
| 5848 | CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5849 | CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"), |
| 5850 | CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5851 | CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5852 | CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5853 | CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"), |
| 5854 | CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5855 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"), |
| 5856 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5857 | CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5858 | CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5859 | CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"), |
| 5860 | CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"), |
| 5861 | CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"), |
| 5862 | CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"), |
| 5863 | CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"), |
| 5864 | CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"), |
| 5865 | CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"), |
| 5866 | CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"), |
| 5867 | CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"), |
| 5868 | CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"), |
| 5869 | CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"), |
| 5870 | CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"), |
| 5871 | CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5872 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5873 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"), |
| 5874 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"), |
| 5875 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5876 | CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"), |
| 5877 | CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5878 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"), |
| 5879 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"), |
| 5880 | CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"), |
| 5881 | CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5882 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5883 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"), |
| 5884 | CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5885 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5886 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"), |
| 5887 | CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"), |
| 5888 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"), |
| 5889 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"), |
| 5890 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"), |
| 5891 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"), |
| 5892 | CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"), |
| 5893 | CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"), |
| 5894 | CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"), |
| 5895 | CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"), |
| 5896 | CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"), |
| 5897 | CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"), |
| 5898 | CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c, |
| 5899 | "msm-dai-q6.1"), |
| 5900 | CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c, |
| 5901 | "msm-dai-q6.1"), |
| 5902 | CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c, |
| 5903 | "msm-dai-q6.5"), |
| 5904 | CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c, |
| 5905 | "msm-dai-q6.5"), |
| 5906 | CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c, |
| 5907 | "msm-dai-q6.16384"), |
| 5908 | CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c, |
| 5909 | "msm-dai-q6.16384"), |
| 5910 | CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c, |
| 5911 | "msm-dai-q6.4"), |
| 5912 | CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c, |
| 5913 | "msm-dai-q6.4"), |
| 5914 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"), |
| 5915 | CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL), |
| 5916 | CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"), |
| 5917 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"), |
| 5918 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"), |
| 5919 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"), |
| 5920 | CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"), |
| 5921 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"), |
| 5922 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"), |
| 5923 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"), |
| 5924 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"), |
| 5925 | CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.9"), |
| 5926 | CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.10"), |
| 5927 | |
| 5928 | CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"), |
| 5929 | CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"), |
| 5930 | CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"), |
| 5931 | CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"), |
| 5932 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"), |
Stephen Boyd | 7b973de | 2012-03-09 12:26:16 -0800 | [diff] [blame] | 5933 | CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"), |
| 5934 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5935 | |
| 5936 | CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL), |
| 5937 | CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"), |
| 5938 | CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"), |
| 5939 | CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"), |
| 5940 | CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"), |
| 5941 | CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"), |
| 5942 | CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"), |
| 5943 | CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"), |
| 5944 | CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"), |
| 5945 | CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"), |
| 5946 | CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"), |
| 5947 | |
| 5948 | CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5949 | CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""), |
| 5950 | CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5951 | |
| 5952 | CLK_LOOKUP("l2_mclk", l2_m_clk, ""), |
| 5953 | CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""), |
| 5954 | CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""), |
| 5955 | CLK_LOOKUP("q6sw_clk", q6sw_clk, ""), |
| 5956 | CLK_LOOKUP("q6fw_clk", q6fw_clk, ""), |
| 5957 | CLK_LOOKUP("q6_func_clk", q6_func_clk, ""), |
| 5958 | }; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5959 | /* |
| 5960 | * Miscellaneous clock register initializations |
| 5961 | */ |
| 5962 | |
| 5963 | /* Read, modify, then write-back a register. */ |
| 5964 | static void __init rmwreg(uint32_t val, void *reg, uint32_t mask) |
| 5965 | { |
| 5966 | uint32_t regval = readl_relaxed(reg); |
| 5967 | regval &= ~mask; |
| 5968 | regval |= val; |
| 5969 | writel_relaxed(regval, reg); |
| 5970 | } |
| 5971 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 5972 | static struct pll_config_regs pll4_regs __initdata = { |
| 5973 | .l_reg = LCC_PLL0_L_VAL_REG, |
| 5974 | .m_reg = LCC_PLL0_M_VAL_REG, |
| 5975 | .n_reg = LCC_PLL0_N_VAL_REG, |
| 5976 | .config_reg = LCC_PLL0_CONFIG_REG, |
| 5977 | .mode_reg = LCC_PLL0_MODE_REG, |
| 5978 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5979 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 5980 | static struct pll_config pll4_config __initdata = { |
| 5981 | .l = 0xE, |
| 5982 | .m = 0x27A, |
| 5983 | .n = 0x465, |
| 5984 | .vco_val = 0x0, |
| 5985 | .vco_mask = BM(17, 16), |
| 5986 | .pre_div_val = 0x0, |
| 5987 | .pre_div_mask = BIT(19), |
| 5988 | .post_div_val = 0x0, |
| 5989 | .post_div_mask = BM(21, 20), |
| 5990 | .mn_ena_val = BIT(22), |
| 5991 | .mn_ena_mask = BIT(22), |
| 5992 | .main_output_val = BIT(23), |
| 5993 | .main_output_mask = BIT(23), |
| 5994 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5995 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 5996 | static struct pll_config_regs pll15_regs __initdata = { |
| 5997 | .l_reg = MM_PLL3_L_VAL_REG, |
| 5998 | .m_reg = MM_PLL3_M_VAL_REG, |
| 5999 | .n_reg = MM_PLL3_N_VAL_REG, |
| 6000 | .config_reg = MM_PLL3_CONFIG_REG, |
| 6001 | .mode_reg = MM_PLL3_MODE_REG, |
| 6002 | }; |
Tianyi Gou | 358c386 | 2011-10-18 17:03:41 -0700 | [diff] [blame] | 6003 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6004 | static struct pll_config pll15_config __initdata = { |
| 6005 | .l = (0x24 | BVAL(31, 7, 0x620)), |
| 6006 | .m = 0x1, |
| 6007 | .n = 0x9, |
| 6008 | .vco_val = BVAL(17, 16, 0x2), |
| 6009 | .vco_mask = BM(17, 16), |
| 6010 | .pre_div_val = 0x0, |
| 6011 | .pre_div_mask = BIT(19), |
| 6012 | .post_div_val = 0x0, |
| 6013 | .post_div_mask = BM(21, 20), |
| 6014 | .mn_ena_val = BIT(22), |
| 6015 | .mn_ena_mask = BIT(22), |
| 6016 | .main_output_val = BIT(23), |
| 6017 | .main_output_mask = BIT(23), |
| 6018 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6019 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6020 | static struct pll_config_regs pll14_regs __initdata = { |
| 6021 | .l_reg = BB_PLL14_L_VAL_REG, |
| 6022 | .m_reg = BB_PLL14_M_VAL_REG, |
| 6023 | .n_reg = BB_PLL14_N_VAL_REG, |
| 6024 | .config_reg = BB_PLL14_CONFIG_REG, |
| 6025 | .mode_reg = BB_PLL14_MODE_REG, |
| 6026 | }; |
| 6027 | |
| 6028 | static struct pll_config pll14_config __initdata = { |
| 6029 | .l = (0x11 | BVAL(31, 7, 0x620)), |
| 6030 | .m = 0x7, |
| 6031 | .n = 0x9, |
| 6032 | .vco_val = 0x0, |
| 6033 | .vco_mask = BM(17, 16), |
| 6034 | .pre_div_val = 0x0, |
| 6035 | .pre_div_mask = BIT(19), |
| 6036 | .post_div_val = 0x0, |
| 6037 | .post_div_mask = BM(21, 20), |
| 6038 | .mn_ena_val = BIT(22), |
| 6039 | .mn_ena_mask = BIT(22), |
| 6040 | .main_output_val = BIT(23), |
| 6041 | .main_output_mask = BIT(23), |
| 6042 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6043 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6044 | static void __init reg_init(void) |
| 6045 | { |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6046 | void __iomem *imem_reg; |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6047 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6048 | /* Deassert MM SW_RESET_ALL signal. */ |
| 6049 | writel_relaxed(0, SW_RESET_ALL_REG); |
| 6050 | |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6051 | /* |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6052 | * Some bits are only used on 8960 or 8064 or 8930 and are marked as |
| 6053 | * reserved bits on the other SoCs. Writing to these reserved bits |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6054 | * should have no effect. |
| 6055 | */ |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6056 | /* |
| 6057 | * Initialize MM AHB registers: Enable the FPB clock and disable HW |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 6058 | * gating on non-8960 for all clocks. Also set VFE_AHB's |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6059 | * FORCE_CORE_ON bit to prevent its memory from being collapsed when |
| 6060 | * the clock is halted. The sleep and wake-up delays are set to safe |
| 6061 | * values. |
| 6062 | */ |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 6063 | if (cpu_is_msm8960() || cpu_is_apq8064()) { |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6064 | rmwreg(0x44000000, AHB_EN_REG, 0x6C000103); |
| 6065 | writel_relaxed(0x3C7097F9, AHB_EN2_REG); |
| 6066 | } else { |
| 6067 | rmwreg(0x00000003, AHB_EN_REG, 0x6C000103); |
| 6068 | writel_relaxed(0x000007F9, AHB_EN2_REG); |
| 6069 | } |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6070 | if (cpu_is_apq8064()) |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 6071 | rmwreg(0x00000001, AHB_EN3_REG, 0x00000001); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6072 | |
| 6073 | /* Deassert all locally-owned MM AHB resets. */ |
| 6074 | rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6075 | rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6076 | |
| 6077 | /* Initialize MM AXI registers: Enable HW gating for all clocks that |
| 6078 | * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up |
| 6079 | * delays to safe values. */ |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 6080 | if ((cpu_is_msm8960() && |
| 6081 | SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) || |
| 6082 | cpu_is_apq8064()) { |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6083 | rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF); |
| 6084 | rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF); |
Gopikrishnaiah Anandan | 83b6e85 | 2012-01-05 17:47:02 -0800 | [diff] [blame] | 6085 | rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF); |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6086 | } else { |
| 6087 | rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF); |
| 6088 | rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF); |
| 6089 | rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF); |
| 6090 | } |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6091 | rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6092 | if (cpu_is_apq8064()) |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 6093 | rmwreg(0x019FECFF, MAXI_EN5_REG, 0x01FFEFFF); |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6094 | if (cpu_is_msm8930()) |
| 6095 | rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF); |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 6096 | if (cpu_is_msm8960() || cpu_is_apq8064()) |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6097 | rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF); |
| 6098 | else |
| 6099 | rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF); |
| 6100 | |
| 6101 | /* Enable IMEM's clk_on signal */ |
| 6102 | imem_reg = ioremap(0x04b00040, 4); |
| 6103 | if (imem_reg) { |
| 6104 | writel_relaxed(0x3, imem_reg); |
| 6105 | iounmap(imem_reg); |
| 6106 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6107 | |
| 6108 | /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core |
| 6109 | * memories retain state even when not clocked. Also, set sleep and |
| 6110 | * wake-up delays to safe values. */ |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6111 | rmwreg(0x00000000, CSI0_CC_REG, 0x00000410); |
| 6112 | rmwreg(0x00000000, CSI1_CC_REG, 0x00000410); |
| 6113 | rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6114 | rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010); |
Tarun Karra | 6fbc00a | 2011-12-13 09:23:47 -0700 | [diff] [blame] | 6115 | rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6116 | rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6117 | rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010); |
| 6118 | rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010); |
| 6119 | rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6120 | rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF); |
| 6121 | rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010); |
| 6122 | rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010); |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 6123 | rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6124 | rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010); |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6125 | if (cpu_is_msm8960() || cpu_is_apq8064()) { |
| 6126 | rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010); |
| 6127 | rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010); |
| 6128 | rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010); |
| 6129 | } |
| 6130 | if (cpu_is_msm8960() || cpu_is_msm8930()) |
| 6131 | rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010); |
| 6132 | |
| 6133 | if (cpu_is_msm8960()) { |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6134 | rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010); |
| 6135 | rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6136 | } |
| 6137 | if (cpu_is_apq8064()) { |
| 6138 | rmwreg(0x00000000, TV_CC_REG, 0x00004010); |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 6139 | rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6140 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6141 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6142 | /* |
| 6143 | * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that |
| 6144 | * core remain active during halt state of the clk. Also, set sleep |
| 6145 | * and wake-up value to max. |
| 6146 | */ |
| 6147 | rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6148 | if (cpu_is_apq8064()) { |
| 6149 | rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F); |
| 6150 | rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F); |
| 6151 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6152 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6153 | /* De-assert MM AXI resets to all hardware blocks. */ |
| 6154 | writel_relaxed(0, SW_RESET_AXI_REG); |
| 6155 | |
| 6156 | /* Deassert all MM core resets. */ |
| 6157 | writel_relaxed(0, SW_RESET_CORE_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6158 | writel_relaxed(0, SW_RESET_CORE2_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6159 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6160 | /* Enable TSSC and PDM PXO sources. */ |
| 6161 | writel_relaxed(BIT(11), TSSC_CLK_CTL_REG); |
| 6162 | writel_relaxed(BIT(15), PDM_CLK_NS_REG); |
| 6163 | |
| 6164 | /* Source SLIMBus xo src from slimbus reference clock */ |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6165 | if (cpu_is_msm8960()) |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6166 | writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6167 | |
| 6168 | /* Source the dsi_byte_clks from the DSI PHY PLLs */ |
| 6169 | rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7); |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6170 | if (cpu_is_msm8960() || cpu_is_apq8064()) |
| 6171 | rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6172 | |
Siddhartha Agrawal | 482459c | 2012-05-24 15:28:53 -0700 | [diff] [blame] | 6173 | /* Source the dsi1_esc_clk from the DSI1 PHY PLLs */ |
| 6174 | rmwreg(0x1, DSI1_ESC_NS_REG, 0x7); |
| 6175 | |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 6176 | /* |
| 6177 | * Source the sata_phy_ref_clk from PXO and set predivider of |
| 6178 | * sata_pmalive_clk to 1. |
| 6179 | */ |
| 6180 | if (cpu_is_apq8064()) { |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6181 | rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1); |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 6182 | rmwreg(0, SATA_PMALIVE_CLK_CTL_REG, 0x3); |
| 6183 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6184 | |
| 6185 | /* |
Tianyi Gou | 05e0110 | 2012-02-08 22:15:49 -0800 | [diff] [blame] | 6186 | * TODO: Programming below PLLs and prng_clk is temporary and |
| 6187 | * needs to be removed after bootloaders program them. |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6188 | */ |
| 6189 | if (cpu_is_apq8064()) { |
Tianyi Gou | 317aa86 | 2012-02-06 14:31:07 -0800 | [diff] [blame] | 6190 | u32 is_pll_enabled; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6191 | |
| 6192 | /* Program pxo_src_clk to source from PXO */ |
| 6193 | rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7); |
| 6194 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6195 | /* Check if PLL14 is active */ |
| 6196 | is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16); |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6197 | if (!is_pll_enabled) |
Tianyi Gou | df71f2e | 2011-10-24 22:25:04 -0700 | [diff] [blame] | 6198 | /* Ref clk = 27MHz and program pll14 to 480MHz */ |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6199 | configure_pll(&pll14_config, &pll14_regs, 1); |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 6200 | |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 6201 | /* Program PLL15 to 975MHz with ref clk = 27MHz */ |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6202 | configure_pll(&pll15_config, &pll15_regs, 0); |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 6203 | |
| 6204 | /* Check if PLL4 is active */ |
| 6205 | is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16); |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6206 | if (!is_pll_enabled) |
Tianyi Gou | df71f2e | 2011-10-24 22:25:04 -0700 | [diff] [blame] | 6207 | /* Ref clk = 27MHz and program pll4 to 393.2160MHz */ |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6208 | configure_pll(&pll4_config, &pll4_regs, 1); |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 6209 | |
| 6210 | /* Enable PLL4 source on the LPASS Primary PLL Mux */ |
| 6211 | writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG); |
Tianyi Gou | 05e0110 | 2012-02-08 22:15:49 -0800 | [diff] [blame] | 6212 | |
| 6213 | /* Program prng_clk to 64MHz if it isn't configured */ |
| 6214 | if (!readl_relaxed(PRNG_CLK_NS_REG)) |
| 6215 | writel_relaxed(0x2B, PRNG_CLK_NS_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6216 | } |
Tianyi Gou | 65c536a | 2012-03-20 23:20:29 -0700 | [diff] [blame] | 6217 | |
| 6218 | /* |
| 6219 | * Program PLL15 to 900MHz with ref clk = 27MHz and |
| 6220 | * only enable PLL main output. |
| 6221 | */ |
| 6222 | if (cpu_is_msm8930()) { |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6223 | pll15_config.l = 0x21 | BVAL(31, 7, 0x600); |
| 6224 | pll15_config.m = 0x1; |
| 6225 | pll15_config.n = 0x3; |
| 6226 | configure_pll(&pll15_config, &pll15_regs, 0); |
| 6227 | /* Disable AUX and BIST outputs */ |
| 6228 | writel_relaxed(0, MM_PLL3_TEST_CTL_REG); |
Tianyi Gou | 65c536a | 2012-03-20 23:20:29 -0700 | [diff] [blame] | 6229 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6230 | } |
| 6231 | |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6232 | static void __init msm8960_clock_pre_init(void) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6233 | { |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 6234 | if (cpu_is_apq8064()) { |
| 6235 | vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8064; |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 6236 | } else if (cpu_is_msm8930() || cpu_is_msm8627()) { |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 6237 | vdd_dig.set_vdd = set_vdd_dig_8930; |
| 6238 | vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8930; |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 6239 | } |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 6240 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6241 | /* |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 6242 | * Change the freq tables for and voltage requirements for |
| 6243 | * clocks which differ between 8960 and 8064. |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6244 | */ |
| 6245 | if (cpu_is_apq8064()) { |
| 6246 | gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 6247 | |
| 6248 | memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064, |
| 6249 | sizeof(gfx3d_clk.c.fmax)); |
| 6250 | memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064, |
| 6251 | sizeof(ijpeg_clk.c.fmax)); |
| 6252 | memcpy(mdp_clk.c.fmax, fmax_mdp_8064, |
| 6253 | sizeof(ijpeg_clk.c.fmax)); |
| 6254 | memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064, |
| 6255 | sizeof(tv_src_clk.c.fmax)); |
| 6256 | memcpy(vfe_clk.c.fmax, fmax_vfe_8064, |
| 6257 | sizeof(vfe_clk.c.fmax)); |
| 6258 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6259 | gmem_axi_clk.c.depends = &gfx3d_axi_clk_8064.c; |
| 6260 | } |
| 6261 | |
| 6262 | /* |
| 6263 | * Change the freq tables and voltage requirements for |
| 6264 | * clocks which differ between 8960 and 8930. |
| 6265 | */ |
| 6266 | if (cpu_is_msm8930()) { |
| 6267 | gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930; |
| 6268 | |
| 6269 | memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930, |
| 6270 | sizeof(gfx3d_clk.c.fmax)); |
| 6271 | |
| 6272 | pll15_clk.c.rate = 900000000; |
| 6273 | gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6274 | } |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 6275 | if ((readl_relaxed(PRNG_CLK_NS_REG) & 0x7F) == 0x2B) |
| 6276 | prng_clk.freq_tbl = clk_tbl_prng_64; |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 6277 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 6278 | vote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6279 | |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 6280 | clk_ops_local_pll.enable = sr_pll_clk_enable; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6281 | |
| 6282 | /* Initialize clock registers. */ |
| 6283 | reg_init(); |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6284 | } |
| 6285 | |
| 6286 | static void __init msm8960_clock_post_init(void) |
| 6287 | { |
| 6288 | /* Keep PXO on whenever APPS cpu is active */ |
| 6289 | clk_prepare_enable(&pxo_a_clk.c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6290 | |
Matt Wagantall | e655cd7 | 2012-04-09 10:15:03 -0700 | [diff] [blame] | 6291 | /* Reset 3D core while clocked to ensure it resets completely. */ |
| 6292 | clk_set_rate(&gfx3d_clk.c, 27000000); |
| 6293 | clk_prepare_enable(&gfx3d_clk.c); |
| 6294 | clk_reset(&gfx3d_clk.c, CLK_RESET_ASSERT); |
| 6295 | udelay(5); |
| 6296 | clk_reset(&gfx3d_clk.c, CLK_RESET_DEASSERT); |
| 6297 | clk_disable_unprepare(&gfx3d_clk.c); |
| 6298 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6299 | /* Initialize rates for clocks that only support one. */ |
| 6300 | clk_set_rate(&pdm_clk.c, 27000000); |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 6301 | clk_set_rate(&prng_clk.c, prng_clk.freq_tbl->freq_hz); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6302 | clk_set_rate(&mdp_vsync_clk.c, 27000000); |
| 6303 | clk_set_rate(&tsif_ref_clk.c, 105000); |
| 6304 | clk_set_rate(&tssc_clk.c, 27000000); |
| 6305 | clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6306 | if (cpu_is_apq8064()) { |
| 6307 | clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000); |
| 6308 | clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000); |
| 6309 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6310 | clk_set_rate(&usb_fs1_src_clk.c, 60000000); |
Stepan Moskovchenko | 2429f15 | 2011-10-25 14:42:35 -0700 | [diff] [blame] | 6311 | if (cpu_is_msm8960() || cpu_is_msm8930()) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6312 | clk_set_rate(&usb_fs2_src_clk.c, 60000000); |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 6313 | clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000); |
| 6314 | clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000); |
| 6315 | clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000); |
Lena Salman | 127823f | 2012-02-14 17:13:53 +0200 | [diff] [blame] | 6316 | clk_set_rate(&usb_hsic_system_clk.c, 60000000); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 6317 | /* |
| 6318 | * Set the CSI rates to a safe default to avoid warnings when |
| 6319 | * switching csi pix and rdi clocks. |
| 6320 | */ |
| 6321 | clk_set_rate(&csi0_src_clk.c, 27000000); |
| 6322 | clk_set_rate(&csi1_src_clk.c, 27000000); |
| 6323 | clk_set_rate(&csi2_src_clk.c, 27000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6324 | |
| 6325 | /* |
Stephen Boyd | 60496bb | 2011-10-17 13:51:37 -0700 | [diff] [blame] | 6326 | * The halt status bits for these clocks may be incorrect at boot. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6327 | * Toggle these clocks on and off to refresh them. |
| 6328 | */ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 6329 | clk_prepare_enable(&pdm_clk.c); |
| 6330 | clk_disable_unprepare(&pdm_clk.c); |
| 6331 | clk_prepare_enable(&tssc_clk.c); |
| 6332 | clk_disable_unprepare(&tssc_clk.c); |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 6333 | clk_prepare_enable(&usb_hsic_hsic_clk.c); |
| 6334 | clk_disable_unprepare(&usb_hsic_hsic_clk.c); |
Stephen Boyd | d7a143a | 2012-02-16 17:59:26 -0800 | [diff] [blame] | 6335 | |
| 6336 | /* |
| 6337 | * Keep sfab floor @ 54MHz so that Krait AHB is at least 27MHz at all |
| 6338 | * times when Apps CPU is active. This ensures the timer's requirement |
| 6339 | * of Krait AHB running 4 times as fast as the timer itself. |
| 6340 | */ |
| 6341 | clk_set_rate(&sfab_tmr_a_clk.c, 54000000); |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 6342 | clk_prepare_enable(&sfab_tmr_a_clk.c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6343 | } |
| 6344 | |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 6345 | static int __init msm8960_clock_late_init(void) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6346 | { |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6347 | int rc; |
| 6348 | struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk"); |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6349 | struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk"); |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6350 | |
| 6351 | /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */ |
| 6352 | if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n", |
| 6353 | PTR_ERR(mmfpb_a_clk))) |
| 6354 | return PTR_ERR(mmfpb_a_clk); |
Matt Wagantall | de555f56 | 2011-11-08 14:18:07 -0800 | [diff] [blame] | 6355 | rc = clk_set_rate(mmfpb_a_clk, 76800000); |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6356 | if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc)) |
| 6357 | return rc; |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 6358 | rc = clk_prepare_enable(mmfpb_a_clk); |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6359 | if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc)) |
| 6360 | return rc; |
| 6361 | |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6362 | /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */ |
| 6363 | if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n", |
| 6364 | PTR_ERR(cfpb_a_clk))) |
| 6365 | return PTR_ERR(cfpb_a_clk); |
Matt Wagantall | de555f56 | 2011-11-08 14:18:07 -0800 | [diff] [blame] | 6366 | rc = clk_set_rate(cfpb_a_clk, 64000000); |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6367 | if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc)) |
| 6368 | return rc; |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 6369 | rc = clk_prepare_enable(cfpb_a_clk); |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6370 | if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc)) |
| 6371 | return rc; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 6372 | |
| 6373 | return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6374 | } |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 6375 | |
| 6376 | struct clock_init_data msm8960_clock_init_data __initdata = { |
| 6377 | .table = msm_clocks_8960, |
| 6378 | .size = ARRAY_SIZE(msm_clocks_8960), |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6379 | .pre_init = msm8960_clock_pre_init, |
| 6380 | .post_init = msm8960_clock_post_init, |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 6381 | .late_init = msm8960_clock_late_init, |
| 6382 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6383 | |
| 6384 | struct clock_init_data apq8064_clock_init_data __initdata = { |
| 6385 | .table = msm_clocks_8064, |
| 6386 | .size = ARRAY_SIZE(msm_clocks_8064), |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6387 | .pre_init = msm8960_clock_pre_init, |
| 6388 | .post_init = msm8960_clock_post_init, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6389 | .late_init = msm8960_clock_late_init, |
| 6390 | }; |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6391 | |
| 6392 | struct clock_init_data msm8930_clock_init_data __initdata = { |
| 6393 | .table = msm_clocks_8930, |
| 6394 | .size = ARRAY_SIZE(msm_clocks_8930), |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6395 | .pre_init = msm8960_clock_pre_init, |
| 6396 | .post_init = msm8960_clock_post_init, |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6397 | .late_init = msm8960_clock_late_init, |
| 6398 | }; |