Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 42 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
| 43 | bool write); |
| 44 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
| 45 | uint64_t offset, |
| 46 | uint64_t size); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 48 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 49 | unsigned alignment, |
| 50 | bool map_and_fenceable); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 51 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
| 52 | struct drm_i915_fence_reg *reg); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 53 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 54 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 55 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 56 | struct drm_file *file); |
| 57 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 58 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 59 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 60 | struct shrink_control *sc); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 61 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 62 | /* some bookkeeping */ |
| 63 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 64 | size_t size) |
| 65 | { |
| 66 | dev_priv->mm.object_count++; |
| 67 | dev_priv->mm.object_memory += size; |
| 68 | } |
| 69 | |
| 70 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 71 | size_t size) |
| 72 | { |
| 73 | dev_priv->mm.object_count--; |
| 74 | dev_priv->mm.object_memory -= size; |
| 75 | } |
| 76 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 77 | static int |
| 78 | i915_gem_wait_for_error(struct drm_device *dev) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 79 | { |
| 80 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 81 | struct completion *x = &dev_priv->error_completion; |
| 82 | unsigned long flags; |
| 83 | int ret; |
| 84 | |
| 85 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 86 | return 0; |
| 87 | |
| 88 | ret = wait_for_completion_interruptible(x); |
| 89 | if (ret) |
| 90 | return ret; |
| 91 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 92 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 93 | /* GPU is hung, bump the completion count to account for |
| 94 | * the token we just consumed so that we never hit zero and |
| 95 | * end up waiting upon a subsequent completion event that |
| 96 | * will never happen. |
| 97 | */ |
| 98 | spin_lock_irqsave(&x->wait.lock, flags); |
| 99 | x->done++; |
| 100 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 101 | } |
| 102 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 103 | } |
| 104 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 105 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 106 | { |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 107 | int ret; |
| 108 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 109 | ret = i915_gem_wait_for_error(dev); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 110 | if (ret) |
| 111 | return ret; |
| 112 | |
| 113 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 114 | if (ret) |
| 115 | return ret; |
| 116 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 117 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 118 | return 0; |
| 119 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 120 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 121 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 122 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 123 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 124 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 125 | } |
| 126 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 127 | void i915_gem_do_init(struct drm_device *dev, |
| 128 | unsigned long start, |
| 129 | unsigned long mappable_end, |
| 130 | unsigned long end) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 131 | { |
| 132 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 133 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 134 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 135 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 136 | dev_priv->mm.gtt_start = start; |
| 137 | dev_priv->mm.gtt_mappable_end = mappable_end; |
| 138 | dev_priv->mm.gtt_end = end; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 139 | dev_priv->mm.gtt_total = end - start; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 140 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 141 | |
| 142 | /* Take over this portion of the GTT */ |
| 143 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 144 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 145 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 146 | int |
| 147 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 148 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 149 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 150 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 151 | |
| 152 | if (args->gtt_start >= args->gtt_end || |
| 153 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 154 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 155 | |
| 156 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 157 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 158 | mutex_unlock(&dev->struct_mutex); |
| 159 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 160 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 161 | } |
| 162 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 163 | int |
| 164 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 165 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 166 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 168 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 169 | struct drm_i915_gem_object *obj; |
| 170 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 171 | |
| 172 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 173 | return -ENODEV; |
| 174 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 175 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 176 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 177 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
| 178 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 179 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 180 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 181 | args->aper_size = dev_priv->mm.gtt_total; |
| 182 | args->aper_available_size = args->aper_size -pinned; |
| 183 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 184 | return 0; |
| 185 | } |
| 186 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 187 | static int |
| 188 | i915_gem_create(struct drm_file *file, |
| 189 | struct drm_device *dev, |
| 190 | uint64_t size, |
| 191 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 192 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 193 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 194 | int ret; |
| 195 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 196 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 197 | size = roundup(size, PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 198 | |
| 199 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 200 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 201 | if (obj == NULL) |
| 202 | return -ENOMEM; |
| 203 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 204 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 205 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 206 | drm_gem_object_release(&obj->base); |
| 207 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 208 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 209 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 210 | } |
| 211 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 212 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 213 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 214 | trace_i915_gem_object_create(obj); |
| 215 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 216 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 217 | return 0; |
| 218 | } |
| 219 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 220 | int |
| 221 | i915_gem_dumb_create(struct drm_file *file, |
| 222 | struct drm_device *dev, |
| 223 | struct drm_mode_create_dumb *args) |
| 224 | { |
| 225 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 226 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 227 | args->size = args->pitch * args->height; |
| 228 | return i915_gem_create(file, dev, |
| 229 | args->size, &args->handle); |
| 230 | } |
| 231 | |
| 232 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 233 | struct drm_device *dev, |
| 234 | uint32_t handle) |
| 235 | { |
| 236 | return drm_gem_handle_delete(file, handle); |
| 237 | } |
| 238 | |
| 239 | /** |
| 240 | * Creates a new mm object and returns a handle to it. |
| 241 | */ |
| 242 | int |
| 243 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 244 | struct drm_file *file) |
| 245 | { |
| 246 | struct drm_i915_gem_create *args = data; |
| 247 | return i915_gem_create(file, dev, |
| 248 | args->size, &args->handle); |
| 249 | } |
| 250 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 251 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 252 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 253 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 254 | |
| 255 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 256 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 257 | } |
| 258 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 259 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 260 | slow_shmem_copy(struct page *dst_page, |
| 261 | int dst_offset, |
| 262 | struct page *src_page, |
| 263 | int src_offset, |
| 264 | int length) |
| 265 | { |
| 266 | char *dst_vaddr, *src_vaddr; |
| 267 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 268 | dst_vaddr = kmap(dst_page); |
| 269 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 270 | |
| 271 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 272 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 273 | kunmap(src_page); |
| 274 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 275 | } |
| 276 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 277 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 278 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 279 | int gpu_offset, |
| 280 | struct page *cpu_page, |
| 281 | int cpu_offset, |
| 282 | int length, |
| 283 | int is_read) |
| 284 | { |
| 285 | char *gpu_vaddr, *cpu_vaddr; |
| 286 | |
| 287 | /* Use the unswizzled path if this page isn't affected. */ |
| 288 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 289 | if (is_read) |
| 290 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 291 | gpu_page, gpu_offset, length); |
| 292 | else |
| 293 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 294 | cpu_page, cpu_offset, length); |
| 295 | } |
| 296 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 297 | gpu_vaddr = kmap(gpu_page); |
| 298 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 299 | |
| 300 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 301 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 302 | */ |
| 303 | while (length > 0) { |
| 304 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 305 | int this_length = min(cacheline_end - gpu_offset, length); |
| 306 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 307 | |
| 308 | if (is_read) { |
| 309 | memcpy(cpu_vaddr + cpu_offset, |
| 310 | gpu_vaddr + swizzled_gpu_offset, |
| 311 | this_length); |
| 312 | } else { |
| 313 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 314 | cpu_vaddr + cpu_offset, |
| 315 | this_length); |
| 316 | } |
| 317 | cpu_offset += this_length; |
| 318 | gpu_offset += this_length; |
| 319 | length -= this_length; |
| 320 | } |
| 321 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 322 | kunmap(cpu_page); |
| 323 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 324 | } |
| 325 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 326 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 327 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 328 | * from the backing pages of the object to the user's address space. On a |
| 329 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 330 | */ |
| 331 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 332 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
| 333 | struct drm_i915_gem_object *obj, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 334 | struct drm_i915_gem_pread *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 335 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 336 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 337 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 338 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 339 | loff_t offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 340 | char __user *user_data; |
| 341 | int page_offset, page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 342 | |
| 343 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 344 | remain = args->size; |
| 345 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 346 | offset = args->offset; |
| 347 | |
| 348 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 349 | struct page *page; |
| 350 | char *vaddr; |
| 351 | int ret; |
| 352 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 353 | /* Operation in this page |
| 354 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 355 | * page_offset = offset within page |
| 356 | * page_length = bytes to copy for this page |
| 357 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 358 | page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 359 | page_length = remain; |
| 360 | if ((page_offset + remain) > PAGE_SIZE) |
| 361 | page_length = PAGE_SIZE - page_offset; |
| 362 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 363 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 364 | if (IS_ERR(page)) |
| 365 | return PTR_ERR(page); |
| 366 | |
| 367 | vaddr = kmap_atomic(page); |
| 368 | ret = __copy_to_user_inatomic(user_data, |
| 369 | vaddr + page_offset, |
| 370 | page_length); |
| 371 | kunmap_atomic(vaddr); |
| 372 | |
| 373 | mark_page_accessed(page); |
| 374 | page_cache_release(page); |
| 375 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 376 | return -EFAULT; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 377 | |
| 378 | remain -= page_length; |
| 379 | user_data += page_length; |
| 380 | offset += page_length; |
| 381 | } |
| 382 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 383 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | /** |
| 387 | * This is the fallback shmem pread path, which allocates temporary storage |
| 388 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 389 | * can copy out of the object's backing pages while holding the struct mutex |
| 390 | * and not take page faults. |
| 391 | */ |
| 392 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 393 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
| 394 | struct drm_i915_gem_object *obj, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 395 | struct drm_i915_gem_pread *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 396 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 397 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 398 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 399 | struct mm_struct *mm = current->mm; |
| 400 | struct page **user_pages; |
| 401 | ssize_t remain; |
| 402 | loff_t offset, pinned_pages, i; |
| 403 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 404 | int shmem_page_offset; |
| 405 | int data_page_index, data_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 406 | int page_length; |
| 407 | int ret; |
| 408 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 409 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 410 | |
| 411 | remain = args->size; |
| 412 | |
| 413 | /* Pin the user pages containing the data. We can't fault while |
| 414 | * holding the struct mutex, yet we want to hold it while |
| 415 | * dereferencing the user data. |
| 416 | */ |
| 417 | first_data_page = data_ptr / PAGE_SIZE; |
| 418 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 419 | num_pages = last_data_page - first_data_page + 1; |
| 420 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 421 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 422 | if (user_pages == NULL) |
| 423 | return -ENOMEM; |
| 424 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 425 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 426 | down_read(&mm->mmap_sem); |
| 427 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 428 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 429 | up_read(&mm->mmap_sem); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 430 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 431 | if (pinned_pages < num_pages) { |
| 432 | ret = -EFAULT; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 433 | goto out; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 434 | } |
| 435 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 436 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 437 | args->offset, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 438 | args->size); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 439 | if (ret) |
| 440 | goto out; |
| 441 | |
| 442 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 443 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 444 | offset = args->offset; |
| 445 | |
| 446 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 447 | struct page *page; |
| 448 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 449 | /* Operation in this page |
| 450 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 451 | * shmem_page_offset = offset within page in shmem file |
| 452 | * data_page_index = page number in get_user_pages return |
| 453 | * data_page_offset = offset with data_page_index page. |
| 454 | * page_length = bytes to copy for this page |
| 455 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 456 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 457 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 458 | data_page_offset = offset_in_page(data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 459 | |
| 460 | page_length = remain; |
| 461 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 462 | page_length = PAGE_SIZE - shmem_page_offset; |
| 463 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 464 | page_length = PAGE_SIZE - data_page_offset; |
| 465 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 466 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
Jesper Juhl | b65552f | 2011-06-12 20:53:44 +0000 | [diff] [blame] | 467 | if (IS_ERR(page)) { |
| 468 | ret = PTR_ERR(page); |
| 469 | goto out; |
| 470 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 471 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 472 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 473 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 474 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 475 | user_pages[data_page_index], |
| 476 | data_page_offset, |
| 477 | page_length, |
| 478 | 1); |
| 479 | } else { |
| 480 | slow_shmem_copy(user_pages[data_page_index], |
| 481 | data_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 482 | page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 483 | shmem_page_offset, |
| 484 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 485 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 486 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 487 | mark_page_accessed(page); |
| 488 | page_cache_release(page); |
| 489 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 490 | remain -= page_length; |
| 491 | data_ptr += page_length; |
| 492 | offset += page_length; |
| 493 | } |
| 494 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 495 | out: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 496 | for (i = 0; i < pinned_pages; i++) { |
| 497 | SetPageDirty(user_pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 498 | mark_page_accessed(user_pages[i]); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 499 | page_cache_release(user_pages[i]); |
| 500 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 501 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 502 | |
| 503 | return ret; |
| 504 | } |
| 505 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 506 | /** |
| 507 | * Reads data from the object referenced by handle. |
| 508 | * |
| 509 | * On error, the contents of *data are undefined. |
| 510 | */ |
| 511 | int |
| 512 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 513 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 514 | { |
| 515 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 516 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 517 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 518 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 519 | if (args->size == 0) |
| 520 | return 0; |
| 521 | |
| 522 | if (!access_ok(VERIFY_WRITE, |
| 523 | (char __user *)(uintptr_t)args->data_ptr, |
| 524 | args->size)) |
| 525 | return -EFAULT; |
| 526 | |
| 527 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
| 528 | args->size); |
| 529 | if (ret) |
| 530 | return -EFAULT; |
| 531 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 532 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 533 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 534 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 535 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 536 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 537 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 538 | ret = -ENOENT; |
| 539 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 540 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 541 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 542 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 543 | if (args->offset > obj->base.size || |
| 544 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 545 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 546 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 547 | } |
| 548 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 549 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 550 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 551 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 552 | args->offset, |
| 553 | args->size); |
| 554 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 555 | goto out; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 556 | |
| 557 | ret = -EFAULT; |
| 558 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 559 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 560 | if (ret == -EFAULT) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 561 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 562 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 563 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 564 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 565 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 566 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 567 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 568 | } |
| 569 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 570 | /* This is the fast write path which cannot handle |
| 571 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 572 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 573 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 574 | static inline int |
| 575 | fast_user_write(struct io_mapping *mapping, |
| 576 | loff_t page_base, int page_offset, |
| 577 | char __user *user_data, |
| 578 | int length) |
| 579 | { |
| 580 | char *vaddr_atomic; |
| 581 | unsigned long unwritten; |
| 582 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 583 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 584 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 585 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 586 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 587 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 588 | } |
| 589 | |
| 590 | /* Here's the write path which can sleep for |
| 591 | * page faults |
| 592 | */ |
| 593 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 594 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 595 | slow_kernel_write(struct io_mapping *mapping, |
| 596 | loff_t gtt_base, int gtt_offset, |
| 597 | struct page *user_page, int user_offset, |
| 598 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 599 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 600 | char __iomem *dst_vaddr; |
| 601 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 602 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 603 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 604 | src_vaddr = kmap(user_page); |
| 605 | |
| 606 | memcpy_toio(dst_vaddr + gtt_offset, |
| 607 | src_vaddr + user_offset, |
| 608 | length); |
| 609 | |
| 610 | kunmap(user_page); |
| 611 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 612 | } |
| 613 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 614 | /** |
| 615 | * This is the fast pwrite path, where we copy the data directly from the |
| 616 | * user into the GTT, uncached. |
| 617 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 618 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 619 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 620 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 621 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 622 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 623 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 624 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 625 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 626 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 627 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 628 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 629 | |
| 630 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 631 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 632 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 633 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 634 | |
| 635 | while (remain > 0) { |
| 636 | /* Operation in this page |
| 637 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 638 | * page_base = page offset within aperture |
| 639 | * page_offset = offset within page |
| 640 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 641 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 642 | page_base = offset & PAGE_MASK; |
| 643 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 644 | page_length = remain; |
| 645 | if ((page_offset + remain) > PAGE_SIZE) |
| 646 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 647 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 648 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 649 | * source page isn't available. Return the error and we'll |
| 650 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 651 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 652 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
| 653 | page_offset, user_data, page_length)) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 654 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 655 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 656 | remain -= page_length; |
| 657 | user_data += page_length; |
| 658 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 659 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 660 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 661 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 662 | } |
| 663 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 664 | /** |
| 665 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 666 | * the memory and maps it using kmap_atomic for copying. |
| 667 | * |
| 668 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 669 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 670 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 671 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 672 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
| 673 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 674 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 675 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 676 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 677 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 678 | ssize_t remain; |
| 679 | loff_t gtt_page_base, offset; |
| 680 | loff_t first_data_page, last_data_page, num_pages; |
| 681 | loff_t pinned_pages, i; |
| 682 | struct page **user_pages; |
| 683 | struct mm_struct *mm = current->mm; |
| 684 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 685 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 686 | uint64_t data_ptr = args->data_ptr; |
| 687 | |
| 688 | remain = args->size; |
| 689 | |
| 690 | /* Pin the user pages containing the data. We can't fault while |
| 691 | * holding the struct mutex, and all of the pwrite implementations |
| 692 | * want to hold it while dereferencing the user data. |
| 693 | */ |
| 694 | first_data_page = data_ptr / PAGE_SIZE; |
| 695 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 696 | num_pages = last_data_page - first_data_page + 1; |
| 697 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 698 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 699 | if (user_pages == NULL) |
| 700 | return -ENOMEM; |
| 701 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 702 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 703 | down_read(&mm->mmap_sem); |
| 704 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 705 | num_pages, 0, 0, user_pages, NULL); |
| 706 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 707 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 708 | if (pinned_pages < num_pages) { |
| 709 | ret = -EFAULT; |
| 710 | goto out_unpin_pages; |
| 711 | } |
| 712 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 713 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 714 | if (ret) |
| 715 | goto out_unpin_pages; |
| 716 | |
| 717 | ret = i915_gem_object_put_fence(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 718 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 719 | goto out_unpin_pages; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 720 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 721 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 722 | |
| 723 | while (remain > 0) { |
| 724 | /* Operation in this page |
| 725 | * |
| 726 | * gtt_page_base = page offset within aperture |
| 727 | * gtt_page_offset = offset within page in aperture |
| 728 | * data_page_index = page number in get_user_pages return |
| 729 | * data_page_offset = offset with data_page_index page. |
| 730 | * page_length = bytes to copy for this page |
| 731 | */ |
| 732 | gtt_page_base = offset & PAGE_MASK; |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 733 | gtt_page_offset = offset_in_page(offset); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 734 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 735 | data_page_offset = offset_in_page(data_ptr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 736 | |
| 737 | page_length = remain; |
| 738 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 739 | page_length = PAGE_SIZE - gtt_page_offset; |
| 740 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 741 | page_length = PAGE_SIZE - data_page_offset; |
| 742 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 743 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 744 | gtt_page_base, gtt_page_offset, |
| 745 | user_pages[data_page_index], |
| 746 | data_page_offset, |
| 747 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 748 | |
| 749 | remain -= page_length; |
| 750 | offset += page_length; |
| 751 | data_ptr += page_length; |
| 752 | } |
| 753 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 754 | out_unpin_pages: |
| 755 | for (i = 0; i < pinned_pages; i++) |
| 756 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 757 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 758 | |
| 759 | return ret; |
| 760 | } |
| 761 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 762 | /** |
| 763 | * This is the fast shmem pwrite path, which attempts to directly |
| 764 | * copy_from_user into the kmapped pages backing the object. |
| 765 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 766 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 767 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
| 768 | struct drm_i915_gem_object *obj, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 769 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 770 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 771 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 772 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 773 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 774 | loff_t offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 775 | char __user *user_data; |
| 776 | int page_offset, page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 777 | |
| 778 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 779 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 780 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 781 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 782 | obj->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 783 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 784 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 785 | struct page *page; |
| 786 | char *vaddr; |
| 787 | int ret; |
| 788 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 789 | /* Operation in this page |
| 790 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 791 | * page_offset = offset within page |
| 792 | * page_length = bytes to copy for this page |
| 793 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 794 | page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 795 | page_length = remain; |
| 796 | if ((page_offset + remain) > PAGE_SIZE) |
| 797 | page_length = PAGE_SIZE - page_offset; |
| 798 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 799 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 800 | if (IS_ERR(page)) |
| 801 | return PTR_ERR(page); |
| 802 | |
| 803 | vaddr = kmap_atomic(page, KM_USER0); |
| 804 | ret = __copy_from_user_inatomic(vaddr + page_offset, |
| 805 | user_data, |
| 806 | page_length); |
| 807 | kunmap_atomic(vaddr, KM_USER0); |
| 808 | |
| 809 | set_page_dirty(page); |
| 810 | mark_page_accessed(page); |
| 811 | page_cache_release(page); |
| 812 | |
| 813 | /* If we get a fault while copying data, then (presumably) our |
| 814 | * source page isn't available. Return the error and we'll |
| 815 | * retry in the slow path. |
| 816 | */ |
| 817 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 818 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 819 | |
| 820 | remain -= page_length; |
| 821 | user_data += page_length; |
| 822 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 823 | } |
| 824 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 825 | return 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 826 | } |
| 827 | |
| 828 | /** |
| 829 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 830 | * the memory and maps it using kmap_atomic for copying. |
| 831 | * |
| 832 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 833 | * struct_mutex is held. |
| 834 | */ |
| 835 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 836 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
| 837 | struct drm_i915_gem_object *obj, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 838 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 839 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 840 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 841 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 842 | struct mm_struct *mm = current->mm; |
| 843 | struct page **user_pages; |
| 844 | ssize_t remain; |
| 845 | loff_t offset, pinned_pages, i; |
| 846 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 847 | int shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 848 | int data_page_index, data_page_offset; |
| 849 | int page_length; |
| 850 | int ret; |
| 851 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 852 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 853 | |
| 854 | remain = args->size; |
| 855 | |
| 856 | /* Pin the user pages containing the data. We can't fault while |
| 857 | * holding the struct mutex, and all of the pwrite implementations |
| 858 | * want to hold it while dereferencing the user data. |
| 859 | */ |
| 860 | first_data_page = data_ptr / PAGE_SIZE; |
| 861 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 862 | num_pages = last_data_page - first_data_page + 1; |
| 863 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 864 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 865 | if (user_pages == NULL) |
| 866 | return -ENOMEM; |
| 867 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 868 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 869 | down_read(&mm->mmap_sem); |
| 870 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 871 | num_pages, 0, 0, user_pages, NULL); |
| 872 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 873 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 874 | if (pinned_pages < num_pages) { |
| 875 | ret = -EFAULT; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 876 | goto out; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 877 | } |
| 878 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 879 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 880 | if (ret) |
| 881 | goto out; |
| 882 | |
| 883 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 884 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 885 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 886 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 887 | |
| 888 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 889 | struct page *page; |
| 890 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 891 | /* Operation in this page |
| 892 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 893 | * shmem_page_offset = offset within page in shmem file |
| 894 | * data_page_index = page number in get_user_pages return |
| 895 | * data_page_offset = offset with data_page_index page. |
| 896 | * page_length = bytes to copy for this page |
| 897 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 898 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 899 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 900 | data_page_offset = offset_in_page(data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 901 | |
| 902 | page_length = remain; |
| 903 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 904 | page_length = PAGE_SIZE - shmem_page_offset; |
| 905 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 906 | page_length = PAGE_SIZE - data_page_offset; |
| 907 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 908 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 909 | if (IS_ERR(page)) { |
| 910 | ret = PTR_ERR(page); |
| 911 | goto out; |
| 912 | } |
| 913 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 914 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 915 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 916 | shmem_page_offset, |
| 917 | user_pages[data_page_index], |
| 918 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 919 | page_length, |
| 920 | 0); |
| 921 | } else { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 922 | slow_shmem_copy(page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 923 | shmem_page_offset, |
| 924 | user_pages[data_page_index], |
| 925 | data_page_offset, |
| 926 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 927 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 928 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 929 | set_page_dirty(page); |
| 930 | mark_page_accessed(page); |
| 931 | page_cache_release(page); |
| 932 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 933 | remain -= page_length; |
| 934 | data_ptr += page_length; |
| 935 | offset += page_length; |
| 936 | } |
| 937 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 938 | out: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 939 | for (i = 0; i < pinned_pages; i++) |
| 940 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 941 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 942 | |
| 943 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 944 | } |
| 945 | |
| 946 | /** |
| 947 | * Writes data to the object referenced by handle. |
| 948 | * |
| 949 | * On error, the contents of the buffer that were to be modified are undefined. |
| 950 | */ |
| 951 | int |
| 952 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 953 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 954 | { |
| 955 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 956 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 957 | int ret; |
| 958 | |
| 959 | if (args->size == 0) |
| 960 | return 0; |
| 961 | |
| 962 | if (!access_ok(VERIFY_READ, |
| 963 | (char __user *)(uintptr_t)args->data_ptr, |
| 964 | args->size)) |
| 965 | return -EFAULT; |
| 966 | |
| 967 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 968 | args->size); |
| 969 | if (ret) |
| 970 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 971 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 972 | ret = i915_mutex_lock_interruptible(dev); |
| 973 | if (ret) |
| 974 | return ret; |
| 975 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 976 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 977 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 978 | ret = -ENOENT; |
| 979 | goto unlock; |
| 980 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 981 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 982 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 983 | if (args->offset > obj->base.size || |
| 984 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 985 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 986 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 987 | } |
| 988 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 989 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 990 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 991 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 992 | * it would end up going through the fenced access, and we'll get |
| 993 | * different detiling behavior between reading and writing. |
| 994 | * pread/pwrite currently are reading and writing from the CPU |
| 995 | * perspective, requiring manual detiling by the client. |
| 996 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 997 | if (obj->phys_obj) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 998 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 999 | else if (obj->gtt_space && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1000 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1001 | ret = i915_gem_object_pin(obj, 0, true); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1002 | if (ret) |
| 1003 | goto out; |
| 1004 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1005 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1006 | if (ret) |
| 1007 | goto out_unpin; |
| 1008 | |
| 1009 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1010 | if (ret) |
| 1011 | goto out_unpin; |
| 1012 | |
| 1013 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1014 | if (ret == -EFAULT) |
| 1015 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); |
| 1016 | |
| 1017 | out_unpin: |
| 1018 | i915_gem_object_unpin(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1019 | } else { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1020 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 1021 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1022 | goto out; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1023 | |
| 1024 | ret = -EFAULT; |
| 1025 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 1026 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); |
| 1027 | if (ret == -EFAULT) |
| 1028 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1029 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1030 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1031 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1032 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1033 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1034 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1035 | return ret; |
| 1036 | } |
| 1037 | |
| 1038 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1039 | * Called when user space prepares to use an object with the CPU, either |
| 1040 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1041 | */ |
| 1042 | int |
| 1043 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1044 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1045 | { |
| 1046 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1047 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1048 | uint32_t read_domains = args->read_domains; |
| 1049 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1050 | int ret; |
| 1051 | |
| 1052 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1053 | return -ENODEV; |
| 1054 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1055 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1056 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1057 | return -EINVAL; |
| 1058 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1059 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1060 | return -EINVAL; |
| 1061 | |
| 1062 | /* Having something in the write domain implies it's in the read |
| 1063 | * domain, and only that read domain. Enforce that in the request. |
| 1064 | */ |
| 1065 | if (write_domain != 0 && read_domains != write_domain) |
| 1066 | return -EINVAL; |
| 1067 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1068 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1069 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1070 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1071 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1072 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1073 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1074 | ret = -ENOENT; |
| 1075 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1076 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1077 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1078 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1079 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1080 | |
| 1081 | /* Silently promote "you're not bound, there was nothing to do" |
| 1082 | * to success, since the client was just asking us to |
| 1083 | * make sure everything was done. |
| 1084 | */ |
| 1085 | if (ret == -EINVAL) |
| 1086 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1087 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1088 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1089 | } |
| 1090 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1091 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1092 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1093 | mutex_unlock(&dev->struct_mutex); |
| 1094 | return ret; |
| 1095 | } |
| 1096 | |
| 1097 | /** |
| 1098 | * Called when user space has done writes to this buffer |
| 1099 | */ |
| 1100 | int |
| 1101 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1102 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1103 | { |
| 1104 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1105 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1106 | int ret = 0; |
| 1107 | |
| 1108 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1109 | return -ENODEV; |
| 1110 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1111 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1112 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1113 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1114 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1115 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1116 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1117 | ret = -ENOENT; |
| 1118 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1119 | } |
| 1120 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1121 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1122 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1123 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1124 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1125 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1126 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1127 | mutex_unlock(&dev->struct_mutex); |
| 1128 | return ret; |
| 1129 | } |
| 1130 | |
| 1131 | /** |
| 1132 | * Maps the contents of an object, returning the address it is mapped |
| 1133 | * into. |
| 1134 | * |
| 1135 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1136 | * imply a ref on the object itself. |
| 1137 | */ |
| 1138 | int |
| 1139 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1140 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1141 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1142 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1143 | struct drm_i915_gem_mmap *args = data; |
| 1144 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1145 | unsigned long addr; |
| 1146 | |
| 1147 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1148 | return -ENODEV; |
| 1149 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1150 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1151 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1152 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1153 | |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1154 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
| 1155 | drm_gem_object_unreference_unlocked(obj); |
| 1156 | return -E2BIG; |
| 1157 | } |
| 1158 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1159 | down_write(¤t->mm->mmap_sem); |
| 1160 | addr = do_mmap(obj->filp, 0, args->size, |
| 1161 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1162 | args->offset); |
| 1163 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1164 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1165 | if (IS_ERR((void *)addr)) |
| 1166 | return addr; |
| 1167 | |
| 1168 | args->addr_ptr = (uint64_t) addr; |
| 1169 | |
| 1170 | return 0; |
| 1171 | } |
| 1172 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1173 | /** |
| 1174 | * i915_gem_fault - fault a page into the GTT |
| 1175 | * vma: VMA in question |
| 1176 | * vmf: fault info |
| 1177 | * |
| 1178 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1179 | * from userspace. The fault handler takes care of binding the object to |
| 1180 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1181 | * only if needed based on whether the old reg is still valid or the object |
| 1182 | * is tiled) and inserting a new PTE into the faulting process. |
| 1183 | * |
| 1184 | * Note that the faulting process may involve evicting existing objects |
| 1185 | * from the GTT and/or fence registers to make room. So performance may |
| 1186 | * suffer if the GTT working set is large or there are few fence registers |
| 1187 | * left. |
| 1188 | */ |
| 1189 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1190 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1191 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1192 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1193 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1194 | pgoff_t page_offset; |
| 1195 | unsigned long pfn; |
| 1196 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1197 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1198 | |
| 1199 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1200 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1201 | PAGE_SHIFT; |
| 1202 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1203 | ret = i915_mutex_lock_interruptible(dev); |
| 1204 | if (ret) |
| 1205 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1206 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1207 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1208 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1209 | /* Now bind it into the GTT if needed */ |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1210 | if (!obj->map_and_fenceable) { |
| 1211 | ret = i915_gem_object_unbind(obj); |
| 1212 | if (ret) |
| 1213 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1214 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1215 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1216 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1217 | if (ret) |
| 1218 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1219 | |
Eric Anholt | e92d03b | 2011-06-14 16:43:09 -0700 | [diff] [blame] | 1220 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1221 | if (ret) |
| 1222 | goto unlock; |
| 1223 | } |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1224 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1225 | if (obj->tiling_mode == I915_TILING_NONE) |
| 1226 | ret = i915_gem_object_put_fence(obj); |
| 1227 | else |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1228 | ret = i915_gem_object_get_fence(obj, NULL); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1229 | if (ret) |
| 1230 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1231 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1232 | if (i915_gem_object_is_inactive(obj)) |
| 1233 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1234 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1235 | obj->fault_mappable = true; |
| 1236 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1237 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1238 | page_offset; |
| 1239 | |
| 1240 | /* Finally, remap it using the new GTT offset */ |
| 1241 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1242 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1243 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1244 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1245 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1246 | case -EIO: |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1247 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1248 | /* Give the error handler a chance to run and move the |
| 1249 | * objects off the GPU active list. Next time we service the |
| 1250 | * fault, we should be able to transition the page into the |
| 1251 | * GTT without touching the GPU (and so avoid further |
| 1252 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1253 | * with coherency, just lost writes. |
| 1254 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1255 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1256 | case 0: |
| 1257 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1258 | case -EINTR: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1259 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1260 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1261 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1262 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1263 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1264 | } |
| 1265 | } |
| 1266 | |
| 1267 | /** |
| 1268 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1269 | * @obj: obj in question |
| 1270 | * |
| 1271 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1272 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1273 | * up the object based on the offset and sets up the various memory mapping |
| 1274 | * structures. |
| 1275 | * |
| 1276 | * This routine allocates and attaches a fake offset for @obj. |
| 1277 | */ |
| 1278 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1279 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1280 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1281 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1282 | struct drm_gem_mm *mm = dev->mm_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1283 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1284 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1285 | int ret = 0; |
| 1286 | |
| 1287 | /* Set the object up for mmap'ing */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1288 | list = &obj->base.map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1289 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1290 | if (!list->map) |
| 1291 | return -ENOMEM; |
| 1292 | |
| 1293 | map = list->map; |
| 1294 | map->type = _DRM_GEM; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1295 | map->size = obj->base.size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1296 | map->handle = obj; |
| 1297 | |
| 1298 | /* Get a DRM GEM mmap offset allocated... */ |
| 1299 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1300 | obj->base.size / PAGE_SIZE, |
| 1301 | 0, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1302 | if (!list->file_offset_node) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1303 | DRM_ERROR("failed to allocate offset for bo %d\n", |
| 1304 | obj->base.name); |
Chris Wilson | 9e0ae53 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1305 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1306 | goto out_free_list; |
| 1307 | } |
| 1308 | |
| 1309 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1310 | obj->base.size / PAGE_SIZE, |
| 1311 | 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1312 | if (!list->file_offset_node) { |
| 1313 | ret = -ENOMEM; |
| 1314 | goto out_free_list; |
| 1315 | } |
| 1316 | |
| 1317 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae53 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1318 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1319 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1320 | DRM_ERROR("failed to add to map hash\n"); |
| 1321 | goto out_free_mm; |
| 1322 | } |
| 1323 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1324 | return 0; |
| 1325 | |
| 1326 | out_free_mm: |
| 1327 | drm_mm_put_block(list->file_offset_node); |
| 1328 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1329 | kfree(list->map); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1330 | list->map = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1331 | |
| 1332 | return ret; |
| 1333 | } |
| 1334 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1335 | /** |
| 1336 | * i915_gem_release_mmap - remove physical page mappings |
| 1337 | * @obj: obj in question |
| 1338 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1339 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1340 | * relinquish ownership of the pages back to the system. |
| 1341 | * |
| 1342 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1343 | * object through the GTT and then lose the fence register due to |
| 1344 | * resource pressure. Similarly if the object has been moved out of the |
| 1345 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1346 | * mapping will then trigger a page fault on the next user access, allowing |
| 1347 | * fixup by i915_gem_fault(). |
| 1348 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1349 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1350 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1351 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1352 | if (!obj->fault_mappable) |
| 1353 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1354 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1355 | if (obj->base.dev->dev_mapping) |
| 1356 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1357 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1358 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1359 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1360 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1361 | } |
| 1362 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1363 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1364 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1365 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1366 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1367 | struct drm_gem_mm *mm = dev->mm_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1368 | struct drm_map_list *list = &obj->base.map_list; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1369 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1370 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1371 | drm_mm_put_block(list->file_offset_node); |
| 1372 | kfree(list->map); |
| 1373 | list->map = NULL; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1374 | } |
| 1375 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1376 | static uint32_t |
| 1377 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) |
| 1378 | { |
| 1379 | struct drm_device *dev = obj->base.dev; |
| 1380 | uint32_t size; |
| 1381 | |
| 1382 | if (INTEL_INFO(dev)->gen >= 4 || |
| 1383 | obj->tiling_mode == I915_TILING_NONE) |
| 1384 | return obj->base.size; |
| 1385 | |
| 1386 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1387 | if (INTEL_INFO(dev)->gen == 3) |
| 1388 | size = 1024*1024; |
| 1389 | else |
| 1390 | size = 512*1024; |
| 1391 | |
| 1392 | while (size < obj->base.size) |
| 1393 | size <<= 1; |
| 1394 | |
| 1395 | return size; |
| 1396 | } |
| 1397 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1398 | /** |
| 1399 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1400 | * @obj: object to check |
| 1401 | * |
| 1402 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1403 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1404 | */ |
| 1405 | static uint32_t |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1406 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1407 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1408 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1409 | |
| 1410 | /* |
| 1411 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1412 | * if a fence register is needed for the object. |
| 1413 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1414 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1415 | obj->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1416 | return 4096; |
| 1417 | |
| 1418 | /* |
| 1419 | * Previous chips need to be aligned to the size of the smallest |
| 1420 | * fence register that can contain the object. |
| 1421 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1422 | return i915_gem_get_gtt_size(obj); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1423 | } |
| 1424 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1425 | /** |
| 1426 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1427 | * unfenced object |
| 1428 | * @obj: object to check |
| 1429 | * |
| 1430 | * Return the required GTT alignment for an object, only taking into account |
| 1431 | * unfenced tiled surface requirements. |
| 1432 | */ |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1433 | uint32_t |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1434 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1435 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1436 | struct drm_device *dev = obj->base.dev; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1437 | int tile_height; |
| 1438 | |
| 1439 | /* |
| 1440 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1441 | */ |
| 1442 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1443 | obj->tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1444 | return 4096; |
| 1445 | |
| 1446 | /* |
| 1447 | * Older chips need unfenced tiled buffers to be aligned to the left |
| 1448 | * edge of an even tile row (where tile rows are counted as if the bo is |
| 1449 | * placed in a fenced gtt region). |
| 1450 | */ |
Daniel Vetter | c8ebc2b | 2011-05-12 22:17:20 +0100 | [diff] [blame] | 1451 | if (IS_GEN2(dev)) |
| 1452 | tile_height = 16; |
| 1453 | else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1454 | tile_height = 32; |
| 1455 | else |
| 1456 | tile_height = 8; |
| 1457 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1458 | return tile_height * obj->stride * 2; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1459 | } |
| 1460 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1461 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1462 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1463 | struct drm_device *dev, |
| 1464 | uint32_t handle, |
| 1465 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1466 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1467 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1468 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1469 | int ret; |
| 1470 | |
| 1471 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1472 | return -ENODEV; |
| 1473 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1474 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1475 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1476 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1477 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1478 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1479 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1480 | ret = -ENOENT; |
| 1481 | goto unlock; |
| 1482 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1483 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1484 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1485 | ret = -E2BIG; |
| 1486 | goto unlock; |
| 1487 | } |
| 1488 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1489 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1490 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1491 | ret = -EINVAL; |
| 1492 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1493 | } |
| 1494 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1495 | if (!obj->base.map_list.map) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1496 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1497 | if (ret) |
| 1498 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1499 | } |
| 1500 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1501 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1502 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1503 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1504 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1505 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1506 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1507 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1508 | } |
| 1509 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1510 | /** |
| 1511 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1512 | * @dev: DRM device |
| 1513 | * @data: GTT mapping ioctl data |
| 1514 | * @file: GEM object info |
| 1515 | * |
| 1516 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1517 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1518 | * up so we can get faults in the handler above. |
| 1519 | * |
| 1520 | * The fault handler will take care of binding the object into the GTT |
| 1521 | * (since it may have been evicted to make room for something), allocating |
| 1522 | * a fence register, and mapping the appropriate aperture address into |
| 1523 | * userspace. |
| 1524 | */ |
| 1525 | int |
| 1526 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1527 | struct drm_file *file) |
| 1528 | { |
| 1529 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1530 | |
| 1531 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1532 | return -ENODEV; |
| 1533 | |
| 1534 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1535 | } |
| 1536 | |
| 1537 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1538 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1539 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1540 | gfp_t gfpmask) |
| 1541 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1542 | int page_count, i; |
| 1543 | struct address_space *mapping; |
| 1544 | struct inode *inode; |
| 1545 | struct page *page; |
| 1546 | |
| 1547 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1548 | * at this point until we release them. |
| 1549 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1550 | page_count = obj->base.size / PAGE_SIZE; |
| 1551 | BUG_ON(obj->pages != NULL); |
| 1552 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1553 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1554 | return -ENOMEM; |
| 1555 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1556 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1557 | mapping = inode->i_mapping; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1558 | gfpmask |= mapping_gfp_mask(mapping); |
| 1559 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1560 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1561 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1562 | if (IS_ERR(page)) |
| 1563 | goto err_pages; |
| 1564 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1565 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1566 | } |
| 1567 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1568 | if (obj->tiling_mode != I915_TILING_NONE) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1569 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1570 | |
| 1571 | return 0; |
| 1572 | |
| 1573 | err_pages: |
| 1574 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1575 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1576 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1577 | drm_free_large(obj->pages); |
| 1578 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1579 | return PTR_ERR(page); |
| 1580 | } |
| 1581 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1582 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1583 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1584 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1585 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1586 | int i; |
| 1587 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1588 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1589 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1590 | if (obj->tiling_mode != I915_TILING_NONE) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1591 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1592 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1593 | if (obj->madv == I915_MADV_DONTNEED) |
| 1594 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1595 | |
| 1596 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1597 | if (obj->dirty) |
| 1598 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1599 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1600 | if (obj->madv == I915_MADV_WILLNEED) |
| 1601 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1602 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1603 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1604 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1605 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1606 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1607 | drm_free_large(obj->pages); |
| 1608 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1609 | } |
| 1610 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1611 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1612 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1613 | struct intel_ring_buffer *ring, |
| 1614 | u32 seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1615 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1616 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1617 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1618 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1619 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1620 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1621 | |
| 1622 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1623 | if (!obj->active) { |
| 1624 | drm_gem_object_reference(&obj->base); |
| 1625 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1626 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1627 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1628 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1629 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1630 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1631 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1632 | obj->last_rendering_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1633 | if (obj->fenced_gpu_access) { |
| 1634 | struct drm_i915_fence_reg *reg; |
| 1635 | |
| 1636 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); |
| 1637 | |
| 1638 | obj->last_fenced_seqno = seqno; |
| 1639 | obj->last_fenced_ring = ring; |
| 1640 | |
| 1641 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1642 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 1643 | } |
| 1644 | } |
| 1645 | |
| 1646 | static void |
| 1647 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1648 | { |
| 1649 | list_del_init(&obj->ring_list); |
| 1650 | obj->last_rendering_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1651 | } |
| 1652 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1653 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1654 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1655 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1656 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1657 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1658 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1659 | BUG_ON(!obj->active); |
| 1660 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1661 | |
| 1662 | i915_gem_object_move_off_active(obj); |
| 1663 | } |
| 1664 | |
| 1665 | static void |
| 1666 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1667 | { |
| 1668 | struct drm_device *dev = obj->base.dev; |
| 1669 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1670 | |
| 1671 | if (obj->pin_count != 0) |
| 1672 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); |
| 1673 | else |
| 1674 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1675 | |
| 1676 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1677 | BUG_ON(!obj->active); |
| 1678 | obj->ring = NULL; |
| 1679 | |
| 1680 | i915_gem_object_move_off_active(obj); |
| 1681 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1682 | |
| 1683 | obj->active = 0; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 1684 | obj->pending_gpu_write = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1685 | drm_gem_object_unreference(&obj->base); |
| 1686 | |
| 1687 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1688 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1689 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1690 | /* Immediately discard the backing storage */ |
| 1691 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1692 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1693 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1694 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1695 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1696 | /* Our goal here is to return as much of the memory as |
| 1697 | * is possible back to the system as we are called from OOM. |
| 1698 | * To do this we must instruct the shmfs to drop all of its |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1699 | * backing pages, *now*. |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1700 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1701 | inode = obj->base.filp->f_path.dentry->d_inode; |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1702 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1703 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1704 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1705 | } |
| 1706 | |
| 1707 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1708 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1709 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1710 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1711 | } |
| 1712 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1713 | static void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1714 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
| 1715 | uint32_t flush_domains) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1716 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1717 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1718 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1719 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1720 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1721 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1722 | if (obj->base.write_domain & flush_domains) { |
| 1723 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1724 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1725 | obj->base.write_domain = 0; |
| 1726 | list_del_init(&obj->gpu_write_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1727 | i915_gem_object_move_to_active(obj, ring, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1728 | i915_gem_next_request_seqno(ring)); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1729 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1730 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1731 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1732 | old_write_domain); |
| 1733 | } |
| 1734 | } |
| 1735 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1736 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1737 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1738 | i915_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1739 | struct drm_file *file, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1740 | struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1741 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1742 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1743 | uint32_t seqno; |
| 1744 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1745 | int ret; |
| 1746 | |
| 1747 | BUG_ON(request == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1748 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1749 | ret = ring->add_request(ring, &seqno); |
| 1750 | if (ret) |
| 1751 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1752 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1753 | trace_i915_gem_request_add(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1754 | |
| 1755 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1756 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1757 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1758 | was_empty = list_empty(&ring->request_list); |
| 1759 | list_add_tail(&request->list, &ring->request_list); |
| 1760 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1761 | if (file) { |
| 1762 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 1763 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1764 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1765 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1766 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1767 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1768 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1769 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1770 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1771 | ring->outstanding_lazy_request = false; |
| 1772 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1773 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1774 | mod_timer(&dev_priv->hangcheck_timer, |
| 1775 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1776 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1777 | queue_delayed_work(dev_priv->wq, |
| 1778 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1779 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1780 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1781 | } |
| 1782 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1783 | static inline void |
| 1784 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1785 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1786 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1787 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1788 | if (!file_priv) |
| 1789 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1790 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1791 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 1792 | if (request->file_priv) { |
| 1793 | list_del(&request->client_list); |
| 1794 | request->file_priv = NULL; |
| 1795 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1796 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1797 | } |
| 1798 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1799 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1800 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1801 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1802 | while (!list_empty(&ring->request_list)) { |
| 1803 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1804 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1805 | request = list_first_entry(&ring->request_list, |
| 1806 | struct drm_i915_gem_request, |
| 1807 | list); |
| 1808 | |
| 1809 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1810 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1811 | kfree(request); |
| 1812 | } |
| 1813 | |
| 1814 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1815 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1816 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1817 | obj = list_first_entry(&ring->active_list, |
| 1818 | struct drm_i915_gem_object, |
| 1819 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1820 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1821 | obj->base.write_domain = 0; |
| 1822 | list_del_init(&obj->gpu_write_list); |
| 1823 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1824 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1825 | } |
| 1826 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1827 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 1828 | { |
| 1829 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1830 | int i; |
| 1831 | |
| 1832 | for (i = 0; i < 16; i++) { |
| 1833 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1834 | struct drm_i915_gem_object *obj = reg->obj; |
| 1835 | |
| 1836 | if (!obj) |
| 1837 | continue; |
| 1838 | |
| 1839 | if (obj->tiling_mode) |
| 1840 | i915_gem_release_mmap(obj); |
| 1841 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1842 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
| 1843 | reg->obj->fenced_gpu_access = false; |
| 1844 | reg->obj->last_fenced_seqno = 0; |
| 1845 | reg->obj->last_fenced_ring = NULL; |
| 1846 | i915_gem_clear_fence_reg(dev, reg); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1847 | } |
| 1848 | } |
| 1849 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1850 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1851 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1852 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1853 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1854 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1855 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1856 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 1857 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1858 | |
| 1859 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1860 | * to be lost on reset along with the data, so simply move the |
| 1861 | * lost bo to the inactive list. |
| 1862 | */ |
| 1863 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1864 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
| 1865 | struct drm_i915_gem_object, |
| 1866 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1867 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1868 | obj->base.write_domain = 0; |
| 1869 | list_del_init(&obj->gpu_write_list); |
| 1870 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1871 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1872 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1873 | /* Move everything out of the GPU domains to ensure we do any |
| 1874 | * necessary invalidation upon reuse. |
| 1875 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1876 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1877 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1878 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1879 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1880 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1881 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1882 | |
| 1883 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1884 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1885 | } |
| 1886 | |
| 1887 | /** |
| 1888 | * This function clears the request list as sequence numbers are passed. |
| 1889 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1890 | static void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1891 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1892 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1893 | uint32_t seqno; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1894 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1895 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1896 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1897 | return; |
| 1898 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1899 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1900 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1901 | seqno = ring->get_seqno(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1902 | |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 1903 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1904 | if (seqno >= ring->sync_seqno[i]) |
| 1905 | ring->sync_seqno[i] = 0; |
| 1906 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1907 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1908 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1909 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1910 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1911 | struct drm_i915_gem_request, |
| 1912 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1913 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1914 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1915 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1916 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1917 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1918 | |
| 1919 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1920 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1921 | kfree(request); |
| 1922 | } |
| 1923 | |
| 1924 | /* Move any buffers on the active list that are no longer referenced |
| 1925 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1926 | */ |
| 1927 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1928 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1929 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1930 | obj= list_first_entry(&ring->active_list, |
| 1931 | struct drm_i915_gem_object, |
| 1932 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1933 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1934 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1935 | break; |
| 1936 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1937 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1938 | i915_gem_object_move_to_flushing(obj); |
| 1939 | else |
| 1940 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1941 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1942 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1943 | if (unlikely(ring->trace_irq_seqno && |
| 1944 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1945 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1946 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1947 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1948 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1949 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1950 | } |
| 1951 | |
| 1952 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1953 | i915_gem_retire_requests(struct drm_device *dev) |
| 1954 | { |
| 1955 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1956 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1957 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1958 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1959 | struct drm_i915_gem_object *obj, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1960 | |
| 1961 | /* We must be careful that during unbind() we do not |
| 1962 | * accidentally infinitely recurse into retire requests. |
| 1963 | * Currently: |
| 1964 | * retire -> free -> unbind -> wait -> retire_ring |
| 1965 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1966 | list_for_each_entry_safe(obj, next, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1967 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1968 | mm_list) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1969 | i915_gem_free_object_tail(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1970 | } |
| 1971 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1972 | for (i = 0; i < I915_NUM_RINGS; i++) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1973 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1974 | } |
| 1975 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1976 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1977 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1978 | { |
| 1979 | drm_i915_private_t *dev_priv; |
| 1980 | struct drm_device *dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1981 | bool idle; |
| 1982 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1983 | |
| 1984 | dev_priv = container_of(work, drm_i915_private_t, |
| 1985 | mm.retire_work.work); |
| 1986 | dev = dev_priv->dev; |
| 1987 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1988 | /* Come back later if the device is busy... */ |
| 1989 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1990 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1991 | return; |
| 1992 | } |
| 1993 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1994 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1995 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1996 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 1997 | * objects indefinitely. |
| 1998 | */ |
| 1999 | idle = true; |
| 2000 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 2001 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; |
| 2002 | |
| 2003 | if (!list_empty(&ring->gpu_write_list)) { |
| 2004 | struct drm_i915_gem_request *request; |
| 2005 | int ret; |
| 2006 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2007 | ret = i915_gem_flush_ring(ring, |
| 2008 | 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2009 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 2010 | if (ret || request == NULL || |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2011 | i915_add_request(ring, NULL, request)) |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2012 | kfree(request); |
| 2013 | } |
| 2014 | |
| 2015 | idle &= list_empty(&ring->request_list); |
| 2016 | } |
| 2017 | |
| 2018 | if (!dev_priv->mm.suspended && !idle) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 2019 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2020 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2021 | mutex_unlock(&dev->struct_mutex); |
| 2022 | } |
| 2023 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2024 | /** |
| 2025 | * Waits for a sequence number to be signaled, and cleans up the |
| 2026 | * request and object lists appropriately for that event. |
| 2027 | */ |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 2028 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2029 | i915_wait_request(struct intel_ring_buffer *ring, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2030 | uint32_t seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2031 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2032 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2033 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2034 | int ret = 0; |
| 2035 | |
| 2036 | BUG_ON(seqno == 0); |
| 2037 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 2038 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 2039 | struct completion *x = &dev_priv->error_completion; |
| 2040 | bool recovery_complete; |
| 2041 | unsigned long flags; |
| 2042 | |
| 2043 | /* Give the error handler a chance to run. */ |
| 2044 | spin_lock_irqsave(&x->wait.lock, flags); |
| 2045 | recovery_complete = x->done > 0; |
| 2046 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 2047 | |
| 2048 | return recovery_complete ? -EIO : -EAGAIN; |
| 2049 | } |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 2050 | |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 2051 | if (seqno == ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2052 | struct drm_i915_gem_request *request; |
| 2053 | |
| 2054 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 2055 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2056 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2057 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2058 | ret = i915_add_request(ring, NULL, request); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2059 | if (ret) { |
| 2060 | kfree(request); |
| 2061 | return ret; |
| 2062 | } |
| 2063 | |
| 2064 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2065 | } |
| 2066 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2067 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2068 | if (HAS_PCH_SPLIT(ring->dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2069 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 2070 | else |
| 2071 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2072 | if (!ier) { |
| 2073 | DRM_ERROR("something (likely vbetool) disabled " |
| 2074 | "interrupts, re-enabling\n"); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2075 | i915_driver_irq_preinstall(ring->dev); |
| 2076 | i915_driver_irq_postinstall(ring->dev); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2077 | } |
| 2078 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2079 | trace_i915_gem_request_wait_begin(ring, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2080 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2081 | ring->waiting_seqno = seqno; |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 2082 | if (ring->irq_get(ring)) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2083 | if (dev_priv->mm.interruptible) |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 2084 | ret = wait_event_interruptible(ring->irq_queue, |
| 2085 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 2086 | || atomic_read(&dev_priv->mm.wedged)); |
| 2087 | else |
| 2088 | wait_event(ring->irq_queue, |
| 2089 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 2090 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2091 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 2092 | ring->irq_put(ring); |
Chris Wilson | b5ba177 | 2010-12-14 12:17:15 +0000 | [diff] [blame] | 2093 | } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring), |
| 2094 | seqno) || |
| 2095 | atomic_read(&dev_priv->mm.wedged), 3000)) |
| 2096 | ret = -EBUSY; |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2097 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2098 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2099 | trace_i915_gem_request_wait_end(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2100 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2101 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2102 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2103 | |
| 2104 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2105 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2106 | __func__, ret, seqno, ring->get_seqno(ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2107 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2108 | |
| 2109 | /* Directly dispatch request retiring. While we have the work queue |
| 2110 | * to handle this, the waiter on a request often wants an associated |
| 2111 | * buffer to have made it to the inactive list, and we would need |
| 2112 | * a separate wait queue to handle that. |
| 2113 | */ |
| 2114 | if (ret == 0) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2115 | i915_gem_retire_requests_ring(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2116 | |
| 2117 | return ret; |
| 2118 | } |
| 2119 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2120 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2121 | * Ensures that all rendering to the object has completed and the object is |
| 2122 | * safe to unbind from the GTT or access from the CPU. |
| 2123 | */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2124 | int |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2125 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2126 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2127 | int ret; |
| 2128 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2129 | /* This function only exists to support waiting for existing rendering, |
| 2130 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2131 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2132 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2133 | |
| 2134 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2135 | * it. |
| 2136 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2137 | if (obj->active) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2138 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2139 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2140 | return ret; |
| 2141 | } |
| 2142 | |
| 2143 | return 0; |
| 2144 | } |
| 2145 | |
| 2146 | /** |
| 2147 | * Unbinds an object from the GTT aperture. |
| 2148 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2149 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2150 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2151 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2152 | int ret = 0; |
| 2153 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2154 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2155 | return 0; |
| 2156 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2157 | if (obj->pin_count != 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2158 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2159 | return -EINVAL; |
| 2160 | } |
| 2161 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2162 | /* blow away mappings if mapped through GTT */ |
| 2163 | i915_gem_release_mmap(obj); |
| 2164 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2165 | /* Move the object to the CPU domain to ensure that |
| 2166 | * any possible CPU writes while it's not in the GTT |
| 2167 | * are flushed when we go to remap it. This will |
| 2168 | * also ensure that all pending GPU writes are finished |
| 2169 | * before we unbind. |
| 2170 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2171 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2172 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2173 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2174 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2175 | * should be safe and we need to cleanup or else we might |
| 2176 | * cause memory corruption through use-after-free. |
| 2177 | */ |
Chris Wilson | 812ed49 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2178 | if (ret) { |
| 2179 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2180 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed49 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2181 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2182 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2183 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2184 | ret = i915_gem_object_put_fence(obj); |
| 2185 | if (ret == -ERESTARTSYS) |
| 2186 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2187 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2188 | trace_i915_gem_object_unbind(obj); |
| 2189 | |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2190 | i915_gem_gtt_unbind_object(obj); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2191 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2192 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2193 | list_del_init(&obj->gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2194 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2195 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2196 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2197 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2198 | drm_mm_put_block(obj->gtt_space); |
| 2199 | obj->gtt_space = NULL; |
| 2200 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2201 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2202 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2203 | i915_gem_object_truncate(obj); |
| 2204 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2205 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2206 | } |
| 2207 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2208 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2209 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2210 | uint32_t invalidate_domains, |
| 2211 | uint32_t flush_domains) |
| 2212 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2213 | int ret; |
| 2214 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2215 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
| 2216 | return 0; |
| 2217 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2218 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
| 2219 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2220 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
| 2221 | if (ret) |
| 2222 | return ret; |
| 2223 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2224 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
| 2225 | i915_gem_process_flushing_list(ring, flush_domains); |
| 2226 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2227 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2228 | } |
| 2229 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2230 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2231 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2232 | int ret; |
| 2233 | |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2234 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2235 | return 0; |
| 2236 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2237 | if (!list_empty(&ring->gpu_write_list)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2238 | ret = i915_gem_flush_ring(ring, |
Chris Wilson | 0ac74c6 | 2010-12-06 14:36:02 +0000 | [diff] [blame] | 2239 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2240 | if (ret) |
| 2241 | return ret; |
| 2242 | } |
| 2243 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2244 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring)); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2245 | } |
| 2246 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2247 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2248 | i915_gpu_idle(struct drm_device *dev) |
| 2249 | { |
| 2250 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2251 | bool lists_empty; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2252 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2253 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2254 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2255 | list_empty(&dev_priv->mm.active_list)); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2256 | if (lists_empty) |
| 2257 | return 0; |
| 2258 | |
| 2259 | /* Flush everything onto the inactive list. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2260 | for (i = 0; i < I915_NUM_RINGS; i++) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2261 | ret = i915_ring_idle(&dev_priv->ring[i]); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2262 | if (ret) |
| 2263 | return ret; |
| 2264 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2265 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2266 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2267 | } |
| 2268 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2269 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2270 | struct intel_ring_buffer *pipelined) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2271 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2272 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2273 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2274 | u32 size = obj->gtt_space->size; |
| 2275 | int regnum = obj->fence_reg; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2276 | uint64_t val; |
| 2277 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2278 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2279 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2280 | val |= obj->gtt_offset & 0xfffff000; |
| 2281 | val |= (uint64_t)((obj->stride / 128) - 1) << |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2282 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2283 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2284 | if (obj->tiling_mode == I915_TILING_Y) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2285 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2286 | val |= I965_FENCE_REG_VALID; |
| 2287 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2288 | if (pipelined) { |
| 2289 | int ret = intel_ring_begin(pipelined, 6); |
| 2290 | if (ret) |
| 2291 | return ret; |
| 2292 | |
| 2293 | intel_ring_emit(pipelined, MI_NOOP); |
| 2294 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2295 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); |
| 2296 | intel_ring_emit(pipelined, (u32)val); |
| 2297 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); |
| 2298 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2299 | intel_ring_advance(pipelined); |
| 2300 | } else |
| 2301 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); |
| 2302 | |
| 2303 | return 0; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2304 | } |
| 2305 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2306 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2307 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2308 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2309 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2310 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2311 | u32 size = obj->gtt_space->size; |
| 2312 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2313 | uint64_t val; |
| 2314 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2315 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2316 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2317 | val |= obj->gtt_offset & 0xfffff000; |
| 2318 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2319 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2320 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2321 | val |= I965_FENCE_REG_VALID; |
| 2322 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2323 | if (pipelined) { |
| 2324 | int ret = intel_ring_begin(pipelined, 6); |
| 2325 | if (ret) |
| 2326 | return ret; |
| 2327 | |
| 2328 | intel_ring_emit(pipelined, MI_NOOP); |
| 2329 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2330 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); |
| 2331 | intel_ring_emit(pipelined, (u32)val); |
| 2332 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); |
| 2333 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2334 | intel_ring_advance(pipelined); |
| 2335 | } else |
| 2336 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); |
| 2337 | |
| 2338 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2339 | } |
| 2340 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2341 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2342 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2343 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2344 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2345 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2346 | u32 size = obj->gtt_space->size; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2347 | u32 fence_reg, val, pitch_val; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2348 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2349 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2350 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2351 | (size & -size) != size || |
| 2352 | (obj->gtt_offset & (size - 1)), |
| 2353 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2354 | obj->gtt_offset, obj->map_and_fenceable, size)) |
| 2355 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2356 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2357 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2358 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2359 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2360 | tile_width = 512; |
| 2361 | |
| 2362 | /* Note: pitch better be a power of two tile widths */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2363 | pitch_val = obj->stride / tile_width; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2364 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2365 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2366 | val = obj->gtt_offset; |
| 2367 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2368 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2369 | val |= I915_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2370 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2371 | val |= I830_FENCE_REG_VALID; |
| 2372 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2373 | fence_reg = obj->fence_reg; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2374 | if (fence_reg < 8) |
| 2375 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2376 | else |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2377 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2378 | |
| 2379 | if (pipelined) { |
| 2380 | int ret = intel_ring_begin(pipelined, 4); |
| 2381 | if (ret) |
| 2382 | return ret; |
| 2383 | |
| 2384 | intel_ring_emit(pipelined, MI_NOOP); |
| 2385 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2386 | intel_ring_emit(pipelined, fence_reg); |
| 2387 | intel_ring_emit(pipelined, val); |
| 2388 | intel_ring_advance(pipelined); |
| 2389 | } else |
| 2390 | I915_WRITE(fence_reg, val); |
| 2391 | |
| 2392 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2393 | } |
| 2394 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2395 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2396 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2397 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2398 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2399 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2400 | u32 size = obj->gtt_space->size; |
| 2401 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2402 | uint32_t val; |
| 2403 | uint32_t pitch_val; |
| 2404 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2405 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2406 | (size & -size) != size || |
| 2407 | (obj->gtt_offset & (size - 1)), |
| 2408 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2409 | obj->gtt_offset, size)) |
| 2410 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2411 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2412 | pitch_val = obj->stride / 128; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2413 | pitch_val = ffs(pitch_val) - 1; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2414 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2415 | val = obj->gtt_offset; |
| 2416 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2417 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2418 | val |= I830_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2419 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2420 | val |= I830_FENCE_REG_VALID; |
| 2421 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2422 | if (pipelined) { |
| 2423 | int ret = intel_ring_begin(pipelined, 4); |
| 2424 | if (ret) |
| 2425 | return ret; |
| 2426 | |
| 2427 | intel_ring_emit(pipelined, MI_NOOP); |
| 2428 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2429 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); |
| 2430 | intel_ring_emit(pipelined, val); |
| 2431 | intel_ring_advance(pipelined); |
| 2432 | } else |
| 2433 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); |
| 2434 | |
| 2435 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2436 | } |
| 2437 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2438 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 2439 | { |
| 2440 | return i915_seqno_passed(ring->get_seqno(ring), seqno); |
| 2441 | } |
| 2442 | |
| 2443 | static int |
| 2444 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2445 | struct intel_ring_buffer *pipelined) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2446 | { |
| 2447 | int ret; |
| 2448 | |
| 2449 | if (obj->fenced_gpu_access) { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2450 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2451 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2452 | 0, obj->base.write_domain); |
| 2453 | if (ret) |
| 2454 | return ret; |
| 2455 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2456 | |
| 2457 | obj->fenced_gpu_access = false; |
| 2458 | } |
| 2459 | |
| 2460 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { |
| 2461 | if (!ring_passed_seqno(obj->last_fenced_ring, |
| 2462 | obj->last_fenced_seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2463 | ret = i915_wait_request(obj->last_fenced_ring, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2464 | obj->last_fenced_seqno); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2465 | if (ret) |
| 2466 | return ret; |
| 2467 | } |
| 2468 | |
| 2469 | obj->last_fenced_seqno = 0; |
| 2470 | obj->last_fenced_ring = NULL; |
| 2471 | } |
| 2472 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2473 | /* Ensure that all CPU reads are completed before installing a fence |
| 2474 | * and all writes before removing the fence. |
| 2475 | */ |
| 2476 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) |
| 2477 | mb(); |
| 2478 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2479 | return 0; |
| 2480 | } |
| 2481 | |
| 2482 | int |
| 2483 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2484 | { |
| 2485 | int ret; |
| 2486 | |
| 2487 | if (obj->tiling_mode) |
| 2488 | i915_gem_release_mmap(obj); |
| 2489 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2490 | ret = i915_gem_object_flush_fence(obj, NULL); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2491 | if (ret) |
| 2492 | return ret; |
| 2493 | |
| 2494 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2495 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2496 | i915_gem_clear_fence_reg(obj->base.dev, |
| 2497 | &dev_priv->fence_regs[obj->fence_reg]); |
| 2498 | |
| 2499 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2500 | } |
| 2501 | |
| 2502 | return 0; |
| 2503 | } |
| 2504 | |
| 2505 | static struct drm_i915_fence_reg * |
| 2506 | i915_find_fence_reg(struct drm_device *dev, |
| 2507 | struct intel_ring_buffer *pipelined) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2508 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2509 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2510 | struct drm_i915_fence_reg *reg, *first, *avail; |
| 2511 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2512 | |
| 2513 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2514 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2515 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2516 | reg = &dev_priv->fence_regs[i]; |
| 2517 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2518 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2519 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2520 | if (!reg->obj->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2521 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2522 | } |
| 2523 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2524 | if (avail == NULL) |
| 2525 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2526 | |
| 2527 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2528 | avail = first = NULL; |
| 2529 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
| 2530 | if (reg->obj->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2531 | continue; |
| 2532 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2533 | if (first == NULL) |
| 2534 | first = reg; |
| 2535 | |
| 2536 | if (!pipelined || |
| 2537 | !reg->obj->last_fenced_ring || |
| 2538 | reg->obj->last_fenced_ring == pipelined) { |
| 2539 | avail = reg; |
| 2540 | break; |
| 2541 | } |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2542 | } |
| 2543 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2544 | if (avail == NULL) |
| 2545 | avail = first; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2546 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2547 | return avail; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2548 | } |
| 2549 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2550 | /** |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2551 | * i915_gem_object_get_fence - set up a fence reg for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2552 | * @obj: object to map through a fence reg |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2553 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
| 2554 | * @interruptible: must we wait uninterruptibly for the register to retire? |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2555 | * |
| 2556 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2557 | * to them without having to worry about swizzling if the object is tiled. |
| 2558 | * |
| 2559 | * This function walks the fence regs looking for a free one for @obj, |
| 2560 | * stealing one if it can't find any. |
| 2561 | * |
| 2562 | * It then sets up the reg based on the object's properties: address, pitch |
| 2563 | * and tiling format. |
| 2564 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2565 | int |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2566 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2567 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2568 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2569 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2570 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2571 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2572 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2573 | |
Chris Wilson | 6bda10d | 2010-12-05 21:04:18 +0000 | [diff] [blame] | 2574 | /* XXX disable pipelining. There are bugs. Shocking. */ |
| 2575 | pipelined = NULL; |
| 2576 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2577 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2578 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2579 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2580 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2581 | |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2582 | if (obj->tiling_changed) { |
| 2583 | ret = i915_gem_object_flush_fence(obj, pipelined); |
| 2584 | if (ret) |
| 2585 | return ret; |
| 2586 | |
| 2587 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) |
| 2588 | pipelined = NULL; |
| 2589 | |
| 2590 | if (pipelined) { |
| 2591 | reg->setup_seqno = |
| 2592 | i915_gem_next_request_seqno(pipelined); |
| 2593 | obj->last_fenced_seqno = reg->setup_seqno; |
| 2594 | obj->last_fenced_ring = pipelined; |
| 2595 | } |
| 2596 | |
| 2597 | goto update; |
| 2598 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2599 | |
| 2600 | if (!pipelined) { |
| 2601 | if (reg->setup_seqno) { |
| 2602 | if (!ring_passed_seqno(obj->last_fenced_ring, |
| 2603 | reg->setup_seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2604 | ret = i915_wait_request(obj->last_fenced_ring, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2605 | reg->setup_seqno); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2606 | if (ret) |
| 2607 | return ret; |
| 2608 | } |
| 2609 | |
| 2610 | reg->setup_seqno = 0; |
| 2611 | } |
| 2612 | } else if (obj->last_fenced_ring && |
| 2613 | obj->last_fenced_ring != pipelined) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2614 | ret = i915_gem_object_flush_fence(obj, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2615 | if (ret) |
| 2616 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2617 | } |
| 2618 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2619 | return 0; |
| 2620 | } |
| 2621 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2622 | reg = i915_find_fence_reg(dev, pipelined); |
| 2623 | if (reg == NULL) |
| 2624 | return -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2625 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2626 | ret = i915_gem_object_flush_fence(obj, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2627 | if (ret) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2628 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2629 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2630 | if (reg->obj) { |
| 2631 | struct drm_i915_gem_object *old = reg->obj; |
| 2632 | |
| 2633 | drm_gem_object_reference(&old->base); |
| 2634 | |
| 2635 | if (old->tiling_mode) |
| 2636 | i915_gem_release_mmap(old); |
| 2637 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2638 | ret = i915_gem_object_flush_fence(old, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2639 | if (ret) { |
| 2640 | drm_gem_object_unreference(&old->base); |
| 2641 | return ret; |
| 2642 | } |
| 2643 | |
| 2644 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) |
| 2645 | pipelined = NULL; |
| 2646 | |
| 2647 | old->fence_reg = I915_FENCE_REG_NONE; |
| 2648 | old->last_fenced_ring = pipelined; |
| 2649 | old->last_fenced_seqno = |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2650 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2651 | |
| 2652 | drm_gem_object_unreference(&old->base); |
| 2653 | } else if (obj->last_fenced_seqno == 0) |
| 2654 | pipelined = NULL; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2655 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2656 | reg->obj = obj; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2657 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 2658 | obj->fence_reg = reg - dev_priv->fence_regs; |
| 2659 | obj->last_fenced_ring = pipelined; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2660 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2661 | reg->setup_seqno = |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2662 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2663 | obj->last_fenced_seqno = reg->setup_seqno; |
| 2664 | |
| 2665 | update: |
| 2666 | obj->tiling_changed = false; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2667 | switch (INTEL_INFO(dev)->gen) { |
Eric Anholt | 25aebfc | 2011-05-06 13:55:53 -0700 | [diff] [blame] | 2668 | case 7: |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2669 | case 6: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2670 | ret = sandybridge_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2671 | break; |
| 2672 | case 5: |
| 2673 | case 4: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2674 | ret = i965_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2675 | break; |
| 2676 | case 3: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2677 | ret = i915_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2678 | break; |
| 2679 | case 2: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2680 | ret = i830_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2681 | break; |
| 2682 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2683 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2684 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2685 | } |
| 2686 | |
| 2687 | /** |
| 2688 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2689 | * @obj: object to clear |
| 2690 | * |
| 2691 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2692 | * data structures in dev_priv and obj. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2693 | */ |
| 2694 | static void |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2695 | i915_gem_clear_fence_reg(struct drm_device *dev, |
| 2696 | struct drm_i915_fence_reg *reg) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2697 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2698 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2699 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2700 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2701 | switch (INTEL_INFO(dev)->gen) { |
Eric Anholt | 25aebfc | 2011-05-06 13:55:53 -0700 | [diff] [blame] | 2702 | case 7: |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2703 | case 6: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2704 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2705 | break; |
| 2706 | case 5: |
| 2707 | case 4: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2708 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2709 | break; |
| 2710 | case 3: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2711 | if (fence_reg >= 8) |
| 2712 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2713 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2714 | case 2: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2715 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2716 | |
| 2717 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2718 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2719 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2720 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2721 | list_del_init(®->lru_list); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2722 | reg->obj = NULL; |
| 2723 | reg->setup_seqno = 0; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2724 | } |
| 2725 | |
| 2726 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | * Finds free space in the GTT aperture and binds the object there. |
| 2728 | */ |
| 2729 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2730 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2731 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2732 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2733 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2734 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2735 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2736 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2737 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2738 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2739 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2740 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2741 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2742 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2743 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2744 | return -EINVAL; |
| 2745 | } |
| 2746 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2747 | fence_size = i915_gem_get_gtt_size(obj); |
| 2748 | fence_alignment = i915_gem_get_gtt_alignment(obj); |
| 2749 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2750 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2751 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2752 | alignment = map_and_fenceable ? fence_alignment : |
| 2753 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2754 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2755 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2756 | return -EINVAL; |
| 2757 | } |
| 2758 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2759 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2760 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2761 | /* If the object is bigger than the entire aperture, reject it early |
| 2762 | * before evicting everything in a vain attempt to find space. |
| 2763 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2764 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2765 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2766 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2767 | return -E2BIG; |
| 2768 | } |
| 2769 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2770 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2771 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2772 | free_space = |
| 2773 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2774 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2775 | dev_priv->mm.gtt_mappable_end, |
| 2776 | 0); |
| 2777 | else |
| 2778 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2779 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2780 | |
| 2781 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2782 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2783 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2784 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2785 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2786 | dev_priv->mm.gtt_mappable_end, |
| 2787 | 0); |
| 2788 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2789 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2790 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2791 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2792 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2793 | /* If the gtt is empty and we're still having trouble |
| 2794 | * fitting our object in, we're out of memory. |
| 2795 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2796 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2797 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2798 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2799 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2800 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2801 | goto search_free; |
| 2802 | } |
| 2803 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2804 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2805 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2806 | drm_mm_put_block(obj->gtt_space); |
| 2807 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2808 | |
| 2809 | if (ret == -ENOMEM) { |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2810 | /* first try to reclaim some memory by clearing the GTT */ |
| 2811 | ret = i915_gem_evict_everything(dev, false); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2812 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2813 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2814 | if (gfpmask) { |
| 2815 | gfpmask = 0; |
| 2816 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2817 | } |
| 2818 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2819 | return -ENOMEM; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2820 | } |
| 2821 | |
| 2822 | goto search_free; |
| 2823 | } |
| 2824 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2825 | return ret; |
| 2826 | } |
| 2827 | |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2828 | ret = i915_gem_gtt_bind_object(obj); |
| 2829 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2830 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2831 | drm_mm_put_block(obj->gtt_space); |
| 2832 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2833 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2834 | if (i915_gem_evict_everything(dev, false)) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2835 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2836 | |
| 2837 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2838 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2839 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2840 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2841 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2842 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2843 | /* Assert that the object is not currently in any GPU domain. As it |
| 2844 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2845 | * a GPU cache |
| 2846 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2847 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2848 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2849 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2850 | obj->gtt_offset = obj->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2851 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2852 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2853 | obj->gtt_space->size == fence_size && |
| 2854 | (obj->gtt_space->start & (fence_alignment -1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2855 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2856 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2857 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2858 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2859 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2860 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2861 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2862 | return 0; |
| 2863 | } |
| 2864 | |
| 2865 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2866 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2867 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2868 | /* If we don't have a page list set up, then we're not pinned |
| 2869 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2870 | * again at bind time. |
| 2871 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2872 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2873 | return; |
| 2874 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 2875 | /* If the GPU is snooping the contents of the CPU cache, |
| 2876 | * we do not need to manually clear the CPU cache lines. However, |
| 2877 | * the caches are only snooped when the render cache is |
| 2878 | * flushed/invalidated. As we always have to emit invalidations |
| 2879 | * and flushes when moving into and out of the RENDER domain, correct |
| 2880 | * snooping behaviour occurs naturally as the result of our domain |
| 2881 | * tracking. |
| 2882 | */ |
| 2883 | if (obj->cache_level != I915_CACHE_NONE) |
| 2884 | return; |
| 2885 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2886 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2887 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2888 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2889 | } |
| 2890 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2891 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2892 | static int |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2893 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2894 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2895 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2896 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2897 | |
| 2898 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2899 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2900 | } |
| 2901 | |
| 2902 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2903 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2904 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2905 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2906 | uint32_t old_write_domain; |
| 2907 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2908 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2909 | return; |
| 2910 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2911 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2912 | * to it immediately go to main memory as far as we know, so there's |
| 2913 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2914 | * |
| 2915 | * However, we do have to enforce the order so that all writes through |
| 2916 | * the GTT land before any writes to the device, such as updates to |
| 2917 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2918 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2919 | wmb(); |
| 2920 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2921 | old_write_domain = obj->base.write_domain; |
| 2922 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2923 | |
| 2924 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2925 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2926 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2927 | } |
| 2928 | |
| 2929 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2930 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2931 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2932 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2933 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2934 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2935 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2936 | return; |
| 2937 | |
| 2938 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2939 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2940 | old_write_domain = obj->base.write_domain; |
| 2941 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2942 | |
| 2943 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2944 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2945 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2946 | } |
| 2947 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2948 | /** |
| 2949 | * Moves a single object to the GTT read, and possibly write domain. |
| 2950 | * |
| 2951 | * This function returns when the move is complete, including waiting on |
| 2952 | * flushes to occur. |
| 2953 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2954 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2955 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2956 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2957 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2958 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2959 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2960 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2961 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2962 | return -EINVAL; |
| 2963 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 2964 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 2965 | return 0; |
| 2966 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2967 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2968 | if (ret) |
| 2969 | return ret; |
| 2970 | |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2971 | if (obj->pending_gpu_write || write) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2972 | ret = i915_gem_object_wait_rendering(obj); |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2973 | if (ret) |
| 2974 | return ret; |
| 2975 | } |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2976 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2977 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2978 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2979 | old_write_domain = obj->base.write_domain; |
| 2980 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2981 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2982 | /* It should now be out of any other write domains, and we can update |
| 2983 | * the domain values for our changes. |
| 2984 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2985 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2986 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2987 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2988 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2989 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2990 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2991 | } |
| 2992 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2993 | trace_i915_gem_object_change_domain(obj, |
| 2994 | old_read_domains, |
| 2995 | old_write_domain); |
| 2996 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2997 | return 0; |
| 2998 | } |
| 2999 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3000 | /* |
| 3001 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 3002 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 3003 | */ |
| 3004 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3005 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3006 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3007 | { |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3008 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3009 | int ret; |
| 3010 | |
| 3011 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3012 | if (obj->gtt_space == NULL) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3013 | return -EINVAL; |
| 3014 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3015 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3016 | if (ret) |
| 3017 | return ret; |
| 3018 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3019 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 3020 | /* Currently, we are always called from an non-interruptible context. */ |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3021 | if (pipelined != obj->ring) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3022 | ret = i915_gem_object_wait_rendering(obj); |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 3023 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3024 | return ret; |
| 3025 | } |
| 3026 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3027 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3028 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3029 | old_read_domains = obj->base.read_domains; |
| 3030 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3031 | |
| 3032 | trace_i915_gem_object_change_domain(obj, |
| 3033 | old_read_domains, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3034 | obj->base.write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3035 | |
| 3036 | return 0; |
| 3037 | } |
| 3038 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3039 | int |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3040 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3041 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3042 | int ret; |
| 3043 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3044 | if (!obj->active) |
| 3045 | return 0; |
| 3046 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3047 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3048 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3049 | if (ret) |
| 3050 | return ret; |
| 3051 | } |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3052 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3053 | return i915_gem_object_wait_rendering(obj); |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3054 | } |
| 3055 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3056 | /** |
| 3057 | * Moves a single object to the CPU read, and possibly write domain. |
| 3058 | * |
| 3059 | * This function returns when the move is complete, including waiting on |
| 3060 | * flushes to occur. |
| 3061 | */ |
| 3062 | static int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3063 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3064 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3065 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3066 | int ret; |
| 3067 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3068 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3069 | return 0; |
| 3070 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3071 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3072 | if (ret) |
| 3073 | return ret; |
| 3074 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3075 | ret = i915_gem_object_wait_rendering(obj); |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 3076 | if (ret) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3077 | return ret; |
| 3078 | |
| 3079 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3080 | |
| 3081 | /* If we have a partially-valid cache of the object in the CPU, |
| 3082 | * finish invalidating it and free the per-page flags. |
| 3083 | */ |
| 3084 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 3085 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3086 | old_write_domain = obj->base.write_domain; |
| 3087 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3088 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3089 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3090 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3091 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3092 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3093 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3094 | } |
| 3095 | |
| 3096 | /* It should now be out of any other write domains, and we can update |
| 3097 | * the domain values for our changes. |
| 3098 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3099 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3100 | |
| 3101 | /* If we're writing through the CPU, then the GPU read domains will |
| 3102 | * need to be invalidated at next use. |
| 3103 | */ |
| 3104 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3105 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3106 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3107 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3108 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3109 | trace_i915_gem_object_change_domain(obj, |
| 3110 | old_read_domains, |
| 3111 | old_write_domain); |
| 3112 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3113 | return 0; |
| 3114 | } |
| 3115 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3116 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3117 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3118 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3119 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3120 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3121 | */ |
| 3122 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3123 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3124 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3125 | if (!obj->page_cpu_valid) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3126 | return; |
| 3127 | |
| 3128 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3129 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3130 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3131 | int i; |
| 3132 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3133 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
| 3134 | if (obj->page_cpu_valid[i]) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3135 | continue; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3136 | drm_clflush_pages(obj->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3137 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3138 | } |
| 3139 | |
| 3140 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3141 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3142 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3143 | kfree(obj->page_cpu_valid); |
| 3144 | obj->page_cpu_valid = NULL; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3145 | } |
| 3146 | |
| 3147 | /** |
| 3148 | * Set the CPU read domain on a range of the object. |
| 3149 | * |
| 3150 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3151 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3152 | * pages have been flushed, and will be respected by |
| 3153 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3154 | * of the whole object. |
| 3155 | * |
| 3156 | * This function returns when the move is complete, including waiting on |
| 3157 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3158 | */ |
| 3159 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3160 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3161 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3162 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3163 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3164 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3165 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3166 | if (offset == 0 && size == obj->base.size) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3167 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3168 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3169 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3170 | if (ret) |
| 3171 | return ret; |
| 3172 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3173 | ret = i915_gem_object_wait_rendering(obj); |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 3174 | if (ret) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3175 | return ret; |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 3176 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3177 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3178 | |
| 3179 | /* If we're already fully in the CPU read domain, we're done. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3180 | if (obj->page_cpu_valid == NULL && |
| 3181 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3182 | return 0; |
| 3183 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3184 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3185 | * newly adding I915_GEM_DOMAIN_CPU |
| 3186 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3187 | if (obj->page_cpu_valid == NULL) { |
| 3188 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, |
| 3189 | GFP_KERNEL); |
| 3190 | if (obj->page_cpu_valid == NULL) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3191 | return -ENOMEM; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3192 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3193 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3194 | |
| 3195 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3196 | * perspective. |
| 3197 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3198 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3199 | i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3200 | if (obj->page_cpu_valid[i]) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3201 | continue; |
| 3202 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3203 | drm_clflush_pages(obj->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3204 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3205 | obj->page_cpu_valid[i] = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3206 | } |
| 3207 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3208 | /* It should now be out of any other write domains, and we can update |
| 3209 | * the domain values for our changes. |
| 3210 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3211 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3212 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3213 | old_read_domains = obj->base.read_domains; |
| 3214 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3215 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3216 | trace_i915_gem_object_change_domain(obj, |
| 3217 | old_read_domains, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3218 | obj->base.write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3219 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3220 | return 0; |
| 3221 | } |
| 3222 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3223 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3224 | * emitted over 20 msec ago. |
| 3225 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3226 | * Note that if we were to use the current jiffies each time around the loop, |
| 3227 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3228 | * render a frame was over 20ms. |
| 3229 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3230 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3231 | * relatively low latency when blocking on a particular request to finish. |
| 3232 | */ |
| 3233 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3234 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3235 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3236 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3237 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3238 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3239 | struct drm_i915_gem_request *request; |
| 3240 | struct intel_ring_buffer *ring = NULL; |
| 3241 | u32 seqno = 0; |
| 3242 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3243 | |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3244 | if (atomic_read(&dev_priv->mm.wedged)) |
| 3245 | return -EIO; |
| 3246 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3247 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3248 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3249 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3250 | break; |
| 3251 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3252 | ring = request->ring; |
| 3253 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3254 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3255 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3256 | |
| 3257 | if (seqno == 0) |
| 3258 | return 0; |
| 3259 | |
| 3260 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3261 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3262 | /* And wait for the seqno passing without holding any locks and |
| 3263 | * causing extra latency for others. This is safe as the irq |
| 3264 | * generation is designed to be run atomically and so is |
| 3265 | * lockless. |
| 3266 | */ |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3267 | if (ring->irq_get(ring)) { |
| 3268 | ret = wait_event_interruptible(ring->irq_queue, |
| 3269 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 3270 | || atomic_read(&dev_priv->mm.wedged)); |
| 3271 | ring->irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3272 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3273 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3274 | ret = -EIO; |
| 3275 | } |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3276 | } |
| 3277 | |
| 3278 | if (ret == 0) |
| 3279 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3280 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3281 | return ret; |
| 3282 | } |
| 3283 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3284 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3285 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3286 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3287 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3288 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3289 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3290 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3291 | int ret; |
| 3292 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3293 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3294 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3295 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3296 | if (obj->gtt_space != NULL) { |
| 3297 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3298 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3299 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3300 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3301 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3302 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3303 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3304 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3305 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3306 | ret = i915_gem_object_unbind(obj); |
| 3307 | if (ret) |
| 3308 | return ret; |
| 3309 | } |
| 3310 | } |
| 3311 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3312 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3313 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3314 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3315 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3316 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3317 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3318 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3319 | if (obj->pin_count++ == 0) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3320 | if (!obj->active) |
| 3321 | list_move_tail(&obj->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3322 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3323 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3324 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3325 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3326 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3327 | return 0; |
| 3328 | } |
| 3329 | |
| 3330 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3331 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3332 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3333 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3334 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3335 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3336 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3337 | BUG_ON(obj->pin_count == 0); |
| 3338 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3339 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3340 | if (--obj->pin_count == 0) { |
| 3341 | if (!obj->active) |
| 3342 | list_move_tail(&obj->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3343 | &dev_priv->mm.inactive_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3344 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3345 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3346 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3347 | } |
| 3348 | |
| 3349 | int |
| 3350 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3351 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3352 | { |
| 3353 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3354 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3355 | int ret; |
| 3356 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3357 | ret = i915_mutex_lock_interruptible(dev); |
| 3358 | if (ret) |
| 3359 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3360 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3361 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3362 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3363 | ret = -ENOENT; |
| 3364 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3365 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3366 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3367 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3368 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3369 | ret = -EINVAL; |
| 3370 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3371 | } |
| 3372 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3373 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3374 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3375 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3376 | ret = -EINVAL; |
| 3377 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3378 | } |
| 3379 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3380 | obj->user_pin_count++; |
| 3381 | obj->pin_filp = file; |
| 3382 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3383 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3384 | if (ret) |
| 3385 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3386 | } |
| 3387 | |
| 3388 | /* XXX - flush the CPU caches for pinned objects |
| 3389 | * as the X server doesn't manage domains yet |
| 3390 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3391 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3392 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3393 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3394 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3395 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3396 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3397 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3398 | } |
| 3399 | |
| 3400 | int |
| 3401 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3402 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3403 | { |
| 3404 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3405 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3406 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3407 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3408 | ret = i915_mutex_lock_interruptible(dev); |
| 3409 | if (ret) |
| 3410 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3411 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3412 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3413 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3414 | ret = -ENOENT; |
| 3415 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3416 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3417 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3418 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3419 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3420 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3421 | ret = -EINVAL; |
| 3422 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3423 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3424 | obj->user_pin_count--; |
| 3425 | if (obj->user_pin_count == 0) { |
| 3426 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3427 | i915_gem_object_unpin(obj); |
| 3428 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3429 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3430 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3431 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3432 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3433 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3434 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3435 | } |
| 3436 | |
| 3437 | int |
| 3438 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3439 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3440 | { |
| 3441 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3442 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3443 | int ret; |
| 3444 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3445 | ret = i915_mutex_lock_interruptible(dev); |
| 3446 | if (ret) |
| 3447 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3448 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3449 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3450 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3451 | ret = -ENOENT; |
| 3452 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3453 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3454 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3455 | /* Count all active objects as busy, even if they are currently not used |
| 3456 | * by the gpu. Users of this interface expect objects to eventually |
| 3457 | * become non-busy without any further actions, therefore emit any |
| 3458 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3459 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3460 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3461 | if (args->busy) { |
| 3462 | /* Unconditionally flush objects, even when the gpu still uses this |
| 3463 | * object. Userspace calling this function indicates that it wants to |
| 3464 | * use this buffer rather sooner than later, so issuing the required |
| 3465 | * flush earlier is beneficial. |
| 3466 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3467 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3468 | ret = i915_gem_flush_ring(obj->ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3469 | 0, obj->base.write_domain); |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3470 | } else if (obj->ring->outstanding_lazy_request == |
| 3471 | obj->last_rendering_seqno) { |
| 3472 | struct drm_i915_gem_request *request; |
| 3473 | |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3474 | /* This ring is not being cleared by active usage, |
| 3475 | * so emit a request to do so. |
| 3476 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3477 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 3478 | if (request) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3479 | ret = i915_add_request(obj->ring, NULL,request); |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3480 | else |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3481 | ret = -ENOMEM; |
| 3482 | } |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3483 | |
| 3484 | /* Update the active list for the hardware's current position. |
| 3485 | * Otherwise this only updates on a delayed timer or when irqs |
| 3486 | * are actually unmasked, and our working set ends up being |
| 3487 | * larger than required. |
| 3488 | */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3489 | i915_gem_retire_requests_ring(obj->ring); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3490 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3491 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3492 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3493 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3494 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3495 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3496 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3497 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3498 | } |
| 3499 | |
| 3500 | int |
| 3501 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3502 | struct drm_file *file_priv) |
| 3503 | { |
| 3504 | return i915_gem_ring_throttle(dev, file_priv); |
| 3505 | } |
| 3506 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3507 | int |
| 3508 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3509 | struct drm_file *file_priv) |
| 3510 | { |
| 3511 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3512 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3513 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3514 | |
| 3515 | switch (args->madv) { |
| 3516 | case I915_MADV_DONTNEED: |
| 3517 | case I915_MADV_WILLNEED: |
| 3518 | break; |
| 3519 | default: |
| 3520 | return -EINVAL; |
| 3521 | } |
| 3522 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3523 | ret = i915_mutex_lock_interruptible(dev); |
| 3524 | if (ret) |
| 3525 | return ret; |
| 3526 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3527 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3528 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3529 | ret = -ENOENT; |
| 3530 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3531 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3532 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3533 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3534 | ret = -EINVAL; |
| 3535 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3536 | } |
| 3537 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3538 | if (obj->madv != __I915_MADV_PURGED) |
| 3539 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3540 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3541 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3542 | if (i915_gem_object_is_purgeable(obj) && |
| 3543 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3544 | i915_gem_object_truncate(obj); |
| 3545 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3546 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3547 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3548 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3549 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3550 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3551 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3552 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3553 | } |
| 3554 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3555 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3556 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3557 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3558 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3559 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3560 | struct address_space *mapping; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3561 | |
| 3562 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 3563 | if (obj == NULL) |
| 3564 | return NULL; |
| 3565 | |
| 3566 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 3567 | kfree(obj); |
| 3568 | return NULL; |
| 3569 | } |
| 3570 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3571 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
| 3572 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 3573 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3574 | i915_gem_info_add_obj(dev_priv, size); |
| 3575 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3576 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3577 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3578 | |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 3579 | obj->cache_level = I915_CACHE_NONE; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 3580 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3581 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3582 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3583 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3584 | INIT_LIST_HEAD(&obj->ring_list); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 3585 | INIT_LIST_HEAD(&obj->exec_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3586 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3587 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3588 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3589 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3590 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3591 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3592 | } |
| 3593 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3594 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3595 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3596 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3597 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3598 | return 0; |
| 3599 | } |
| 3600 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3601 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3602 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3603 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3604 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3605 | int ret; |
| 3606 | |
| 3607 | ret = i915_gem_object_unbind(obj); |
| 3608 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3609 | list_move(&obj->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3610 | &dev_priv->mm.deferred_free_list); |
| 3611 | return; |
| 3612 | } |
| 3613 | |
Chris Wilson | 26e12f8 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3614 | trace_i915_gem_object_destroy(obj); |
| 3615 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3616 | if (obj->base.map_list.map) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3617 | i915_gem_free_mmap_offset(obj); |
| 3618 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3619 | drm_gem_object_release(&obj->base); |
| 3620 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3621 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3622 | kfree(obj->page_cpu_valid); |
| 3623 | kfree(obj->bit_17); |
| 3624 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3625 | } |
| 3626 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3627 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3628 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3629 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 3630 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3631 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3632 | while (obj->pin_count > 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3633 | i915_gem_object_unpin(obj); |
| 3634 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3635 | if (obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3636 | i915_gem_detach_phys_object(dev, obj); |
| 3637 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3638 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3639 | } |
| 3640 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3641 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3642 | i915_gem_idle(struct drm_device *dev) |
| 3643 | { |
| 3644 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3645 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3646 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3647 | mutex_lock(&dev->struct_mutex); |
| 3648 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3649 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3650 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3651 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3652 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3653 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3654 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3655 | if (ret) { |
| 3656 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3657 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3658 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3659 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3660 | /* Under UMS, be paranoid and evict. */ |
| 3661 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3662 | ret = i915_gem_evict_inactive(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3663 | if (ret) { |
| 3664 | mutex_unlock(&dev->struct_mutex); |
| 3665 | return ret; |
| 3666 | } |
| 3667 | } |
| 3668 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3669 | i915_gem_reset_fences(dev); |
| 3670 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3671 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3672 | * We need to replace this with a semaphore, or something. |
| 3673 | * And not confound mm.suspended! |
| 3674 | */ |
| 3675 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 3676 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3677 | |
| 3678 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3679 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3680 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3681 | mutex_unlock(&dev->struct_mutex); |
| 3682 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3683 | /* Cancel the retire work handler, which should be idle now. */ |
| 3684 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3685 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3686 | return 0; |
| 3687 | } |
| 3688 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3689 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3690 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 3691 | { |
| 3692 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3693 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3694 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3695 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3696 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3697 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3698 | |
| 3699 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3700 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3701 | if (ret) |
| 3702 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3703 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3704 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3705 | if (HAS_BLT(dev)) { |
| 3706 | ret = intel_init_blt_ring_buffer(dev); |
| 3707 | if (ret) |
| 3708 | goto cleanup_bsd_ring; |
| 3709 | } |
| 3710 | |
Chris Wilson | 6f392d5 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 3711 | dev_priv->next_seqno = 1; |
| 3712 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3713 | return 0; |
| 3714 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3715 | cleanup_bsd_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3716 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3717 | cleanup_render_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3718 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3719 | return ret; |
| 3720 | } |
| 3721 | |
| 3722 | void |
| 3723 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 3724 | { |
| 3725 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3726 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3727 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3728 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3729 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3730 | } |
| 3731 | |
| 3732 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3733 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 3734 | struct drm_file *file_priv) |
| 3735 | { |
| 3736 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3737 | int ret, i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3738 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3739 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3740 | return 0; |
| 3741 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3742 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3743 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3744 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3745 | } |
| 3746 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3747 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3748 | dev_priv->mm.suspended = 0; |
| 3749 | |
| 3750 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3751 | if (ret != 0) { |
| 3752 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3753 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3754 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3755 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3756 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3757 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 3758 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3759 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3760 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); |
| 3761 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); |
| 3762 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3763 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3764 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3765 | ret = drm_irq_install(dev); |
| 3766 | if (ret) |
| 3767 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3768 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3769 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3770 | |
| 3771 | cleanup_ringbuffer: |
| 3772 | mutex_lock(&dev->struct_mutex); |
| 3773 | i915_gem_cleanup_ringbuffer(dev); |
| 3774 | dev_priv->mm.suspended = 1; |
| 3775 | mutex_unlock(&dev->struct_mutex); |
| 3776 | |
| 3777 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3778 | } |
| 3779 | |
| 3780 | int |
| 3781 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 3782 | struct drm_file *file_priv) |
| 3783 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3784 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3785 | return 0; |
| 3786 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3787 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 3788 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3789 | } |
| 3790 | |
| 3791 | void |
| 3792 | i915_gem_lastclose(struct drm_device *dev) |
| 3793 | { |
| 3794 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3795 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 3796 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3797 | return; |
| 3798 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3799 | ret = i915_gem_idle(dev); |
| 3800 | if (ret) |
| 3801 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3802 | } |
| 3803 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3804 | static void |
| 3805 | init_ring_lists(struct intel_ring_buffer *ring) |
| 3806 | { |
| 3807 | INIT_LIST_HEAD(&ring->active_list); |
| 3808 | INIT_LIST_HEAD(&ring->request_list); |
| 3809 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 3810 | } |
| 3811 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3812 | void |
| 3813 | i915_gem_load(struct drm_device *dev) |
| 3814 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3815 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3816 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3817 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3818 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3819 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 3820 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3821 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3822 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3823 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3824 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3825 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3826 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 3827 | for (i = 0; i < 16; i++) |
| 3828 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3829 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 3830 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3831 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3832 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3833 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 3834 | if (IS_GEN3(dev)) { |
| 3835 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 3836 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 3837 | /* arb state is a masked write, so set bit + bit in mask */ |
| 3838 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 3839 | I915_WRITE(MI_ARB_STATE, tmp); |
| 3840 | } |
| 3841 | } |
| 3842 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 3843 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 3844 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3845 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 3846 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3847 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3848 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3849 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3850 | dev_priv->num_fence_regs = 16; |
| 3851 | else |
| 3852 | dev_priv->num_fence_regs = 8; |
| 3853 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3854 | /* Initialize fence registers to zero */ |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3855 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
| 3856 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3857 | } |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3858 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3859 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3860 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3861 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3862 | dev_priv->mm.interruptible = true; |
| 3863 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3864 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 3865 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 3866 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3867 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3868 | |
| 3869 | /* |
| 3870 | * Create a physically contiguous memory object for this object |
| 3871 | * e.g. for cursor + overlay regs |
| 3872 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3873 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 3874 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3875 | { |
| 3876 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3877 | struct drm_i915_gem_phys_object *phys_obj; |
| 3878 | int ret; |
| 3879 | |
| 3880 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 3881 | return 0; |
| 3882 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3883 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3884 | if (!phys_obj) |
| 3885 | return -ENOMEM; |
| 3886 | |
| 3887 | phys_obj->id = id; |
| 3888 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3889 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3890 | if (!phys_obj->handle) { |
| 3891 | ret = -ENOMEM; |
| 3892 | goto kfree_obj; |
| 3893 | } |
| 3894 | #ifdef CONFIG_X86 |
| 3895 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3896 | #endif |
| 3897 | |
| 3898 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 3899 | |
| 3900 | return 0; |
| 3901 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3902 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3903 | return ret; |
| 3904 | } |
| 3905 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3906 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3907 | { |
| 3908 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3909 | struct drm_i915_gem_phys_object *phys_obj; |
| 3910 | |
| 3911 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 3912 | return; |
| 3913 | |
| 3914 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3915 | if (phys_obj->cur_obj) { |
| 3916 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 3917 | } |
| 3918 | |
| 3919 | #ifdef CONFIG_X86 |
| 3920 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3921 | #endif |
| 3922 | drm_pci_free(dev, phys_obj->handle); |
| 3923 | kfree(phys_obj); |
| 3924 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 3925 | } |
| 3926 | |
| 3927 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 3928 | { |
| 3929 | int i; |
| 3930 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 3931 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3932 | i915_gem_free_phys_object(dev, i); |
| 3933 | } |
| 3934 | |
| 3935 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3936 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3937 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3938 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3939 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3940 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3941 | int page_count; |
| 3942 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3943 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3944 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3945 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3946 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3947 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3948 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3949 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3950 | if (!IS_ERR(page)) { |
| 3951 | char *dst = kmap_atomic(page); |
| 3952 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 3953 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3954 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3955 | drm_clflush_pages(&page, 1); |
| 3956 | |
| 3957 | set_page_dirty(page); |
| 3958 | mark_page_accessed(page); |
| 3959 | page_cache_release(page); |
| 3960 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3961 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3962 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 3963 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3964 | obj->phys_obj->cur_obj = NULL; |
| 3965 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3966 | } |
| 3967 | |
| 3968 | int |
| 3969 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3970 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3971 | int id, |
| 3972 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3973 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3974 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3975 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3976 | int ret = 0; |
| 3977 | int page_count; |
| 3978 | int i; |
| 3979 | |
| 3980 | if (id > I915_MAX_PHYS_OBJECT) |
| 3981 | return -EINVAL; |
| 3982 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3983 | if (obj->phys_obj) { |
| 3984 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3985 | return 0; |
| 3986 | i915_gem_detach_phys_object(dev, obj); |
| 3987 | } |
| 3988 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3989 | /* create a new object */ |
| 3990 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 3991 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3992 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3993 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3994 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 3995 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3996 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3997 | } |
| 3998 | } |
| 3999 | |
| 4000 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4001 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4002 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4003 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4004 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4005 | |
| 4006 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4007 | struct page *page; |
| 4008 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4009 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4010 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4011 | if (IS_ERR(page)) |
| 4012 | return PTR_ERR(page); |
| 4013 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 4014 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4015 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4016 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4017 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4018 | |
| 4019 | mark_page_accessed(page); |
| 4020 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4021 | } |
| 4022 | |
| 4023 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4024 | } |
| 4025 | |
| 4026 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4027 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 4028 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4029 | struct drm_i915_gem_pwrite *args, |
| 4030 | struct drm_file *file_priv) |
| 4031 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4032 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4033 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4034 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4035 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 4036 | unsigned long unwritten; |
| 4037 | |
| 4038 | /* The physical object once assigned is fixed for the lifetime |
| 4039 | * of the obj, so we can safely drop the lock and continue |
| 4040 | * to access vaddr. |
| 4041 | */ |
| 4042 | mutex_unlock(&dev->struct_mutex); |
| 4043 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 4044 | mutex_lock(&dev->struct_mutex); |
| 4045 | if (unwritten) |
| 4046 | return -EFAULT; |
| 4047 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4048 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 4049 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4050 | return 0; |
| 4051 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4052 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4053 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4054 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4055 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4056 | |
| 4057 | /* Clean up our request list when the client is going away, so that |
| 4058 | * later retire_requests won't dereference our soon-to-be-gone |
| 4059 | * file_priv. |
| 4060 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4061 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4062 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4063 | struct drm_i915_gem_request *request; |
| 4064 | |
| 4065 | request = list_first_entry(&file_priv->mm.request_list, |
| 4066 | struct drm_i915_gem_request, |
| 4067 | client_list); |
| 4068 | list_del(&request->client_list); |
| 4069 | request->file_priv = NULL; |
| 4070 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4071 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4072 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4073 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4074 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4075 | i915_gpu_is_active(struct drm_device *dev) |
| 4076 | { |
| 4077 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4078 | int lists_empty; |
| 4079 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4080 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4081 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4082 | |
| 4083 | return !lists_empty; |
| 4084 | } |
| 4085 | |
| 4086 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4087 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4088 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4089 | struct drm_i915_private *dev_priv = |
| 4090 | container_of(shrinker, |
| 4091 | struct drm_i915_private, |
| 4092 | mm.inactive_shrinker); |
| 4093 | struct drm_device *dev = dev_priv->dev; |
| 4094 | struct drm_i915_gem_object *obj, *next; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4095 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4096 | int cnt; |
| 4097 | |
| 4098 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 4099 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4100 | |
| 4101 | /* "fast-path" to count number of available objects */ |
| 4102 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4103 | cnt = 0; |
| 4104 | list_for_each_entry(obj, |
| 4105 | &dev_priv->mm.inactive_list, |
| 4106 | mm_list) |
| 4107 | cnt++; |
| 4108 | mutex_unlock(&dev->struct_mutex); |
| 4109 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4110 | } |
| 4111 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4112 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4113 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4114 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4115 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4116 | list_for_each_entry_safe(obj, next, |
| 4117 | &dev_priv->mm.inactive_list, |
| 4118 | mm_list) { |
| 4119 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4120 | if (i915_gem_object_unbind(obj) == 0 && |
| 4121 | --nr_to_scan == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4122 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4123 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4124 | } |
| 4125 | |
| 4126 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4127 | cnt = 0; |
| 4128 | list_for_each_entry_safe(obj, next, |
| 4129 | &dev_priv->mm.inactive_list, |
| 4130 | mm_list) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4131 | if (nr_to_scan && |
| 4132 | i915_gem_object_unbind(obj) == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4133 | nr_to_scan--; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4134 | else |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4135 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4136 | } |
| 4137 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4138 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4139 | /* |
| 4140 | * We are desperate for pages, so as a last resort, wait |
| 4141 | * for the GPU to finish and discard whatever we can. |
| 4142 | * This has a dramatic impact to reduce the number of |
| 4143 | * OOM-killer events whilst running the GPU aggressively. |
| 4144 | */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4145 | if (i915_gpu_idle(dev) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4146 | goto rescan; |
| 4147 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4148 | mutex_unlock(&dev->struct_mutex); |
| 4149 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4150 | } |