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gerrit-public.fairphone.software / kernel / msm / e1c7a9fdeb38d37bfe441b73dcfd67298a8f1c23 / . / arch / arm / mach-msm / clock-8226.c
blob: 993ce58dccf4682b130d1677691c5c562b8eed84 [file] [log] [blame]
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/iopoll.h>
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]22#include <linux/regulator/consumer.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]23
24#include <mach/rpm-regulator-smd.h>
25#include <mach/socinfo.h>
26#include <mach/rpm-smd.h>
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]27#include <mach/clock-generic.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]28
29#include "clock-local2.h"
30#include "clock-pll.h"
31#include "clock-rpm.h"
32#include "clock-voter.h"
33#include "clock-mdss-8974.h"
34#include "clock.h"
35
36enum {
37 GCC_BASE,
38 MMSS_BASE,
39 LPASS_BASE,
40 APCS_BASE,
41 APCS_PLL_BASE,
42 N_BASES,
43};
44
45static void __iomem *virt_bases[N_BASES];
46
47#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
48#define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x))
49#define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x))
50#define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x))
51
52/* Mux source select values */
53#define xo_source_val 0
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]54#define xo_a_clk_source_val 0
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]55#define gpll0_source_val 1
56#define gpll1_source_val 2
57
58#define xo_mm_source_val 0
59#define mmpll0_pll_mm_source_val 1
60#define mmpll1_pll_mm_source_val 2
61#define mmpll2_pll_mm_source_val 3
62#define gpll0_mm_source_val 5
63#define dsipll_750_mm_source_val 1
64#define dsipll_667_mm_source_val 1
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]65#define dsipll0_byte_mm_source_val 1
66#define dsipll0_pixel_mm_source_val 1
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]67
68#define gpll1_hsic_source_val 4
69
70#define xo_lpass_source_val 0
71#define lpaaudio_pll_lpass_source_val 1
72#define gpll0_lpass_source_val 5
73
74/* Prevent a divider of -1 */
75#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
76
77#define F_GCC(f, s, div, m, n) \
78 { \
79 .freq_hz = (f), \
80 .src_clk = &s.c, \
81 .m_val = (m), \
82 .n_val = ~((n)-(m)) * !!(n), \
83 .d_val = ~(n),\
84 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
85 | BVAL(10, 8, s##_source_val), \
86 }
87
88#define F_MMSS(f, s, div, m, n) \
89 { \
90 .freq_hz = (f), \
91 .src_clk = &s.c, \
92 .m_val = (m), \
93 .n_val = ~((n)-(m)) * !!(n), \
94 .d_val = ~(n),\
95 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
96 | BVAL(10, 8, s##_mm_source_val), \
97 }
98
99#define F_MDSS(f, s, div, m, n) \
100 { \
101 .freq_hz = (f), \
102 .m_val = (m), \
103 .n_val = ~((n)-(m)) * !!(n), \
104 .d_val = ~(n),\
105 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
106 | BVAL(10, 8, s##_mm_source_val), \
107 }
108
109#define F_HSIC(f, s, div, m, n) \
110 { \
111 .freq_hz = (f), \
112 .src_clk = &s.c, \
113 .m_val = (m), \
114 .n_val = ~((n)-(m)) * !!(n), \
115 .d_val = ~(n),\
116 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
117 | BVAL(10, 8, s##_hsic_source_val), \
118 }
119
120#define F_LPASS(f, s, div, m, n) \
121 { \
122 .freq_hz = (f), \
123 .src_clk = &s.c, \
124 .m_val = (m), \
125 .n_val = ~((n)-(m)) * !!(n), \
126 .d_val = ~(n),\
127 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
128 | BVAL(10, 8, s##_lpass_source_val), \
129 }
130
131#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \
132 { \
133 .freq_hz = (f), \
134 .l_val = (l), \
135 .m_val = (m), \
136 .n_val = (n), \
137 .pre_div_val = BVAL(12, 12, (pre_div)), \
138 .post_div_val = BVAL(9, 8, (post_div)), \
139 .vco_val = BVAL(29, 28, (vco)), \
140 }
141
142#define VDD_DIG_FMAX_MAP1(l1, f1) \
143 .vdd_class = &vdd_dig, \
144 .fmax = (unsigned long[VDD_DIG_NUM]) { \
145 [VDD_DIG_##l1] = (f1), \
146 }, \
147 .num_fmax = VDD_DIG_NUM
148
149#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
150 .vdd_class = &vdd_dig, \
151 .fmax = (unsigned long[VDD_DIG_NUM]) { \
152 [VDD_DIG_##l1] = (f1), \
153 [VDD_DIG_##l2] = (f2), \
154 }, \
155 .num_fmax = VDD_DIG_NUM
156
157#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
158 .vdd_class = &vdd_dig, \
159 .fmax = (unsigned long[VDD_DIG_NUM]) { \
160 [VDD_DIG_##l1] = (f1), \
161 [VDD_DIG_##l2] = (f2), \
162 [VDD_DIG_##l3] = (f3), \
163 }, \
164 .num_fmax = VDD_DIG_NUM
165
166enum vdd_dig_levels {
167 VDD_DIG_NONE,
168 VDD_DIG_LOW,
169 VDD_DIG_NOMINAL,
170 VDD_DIG_HIGH,
171 VDD_DIG_NUM
172};
173
Junjie Wubb5a79e2013-05-15 13:12:39 -0700[diff] [blame]174static int vdd_corner[] = {
175 RPM_REGULATOR_CORNER_NONE, /* VDD_DIG_NONE */
176 RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_DIG_LOW */
177 RPM_REGULATOR_CORNER_NORMAL, /* VDD_DIG_NOMINAL */
178 RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_DIG_HIGH */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]179};
180
Patrick Daly653c0b52013-04-16 17:18:28 -0700[diff] [blame]181static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]182
183#define RPM_MISC_CLK_TYPE 0x306b6c63
184#define RPM_BUS_CLK_TYPE 0x316b6c63
185#define RPM_MEM_CLK_TYPE 0x326b6c63
186
187#define RPM_SMD_KEY_ENABLE 0x62616E45
188
189#define CXO_ID 0x0
190#define QDSS_ID 0x1
191
192#define PNOC_ID 0x0
193#define SNOC_ID 0x1
194#define CNOC_ID 0x2
195#define MMSSNOC_AHB_ID 0x3
196
197#define BIMC_ID 0x0
198#define OXILI_ID 0x1
199#define OCMEM_ID 0x2
200
201#define D0_ID 1
202#define D1_ID 2
203#define A0_ID 4
204#define A1_ID 5
205#define A2_ID 6
206#define DIFF_CLK_ID 7
207#define DIV_CLK1_ID 11
208#define DIV_CLK2_ID 12
209
210DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL);
211DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
212DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL);
213DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE,
214 MMSSNOC_AHB_ID, NULL);
215
216DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
217DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID,
218 NULL);
219DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID,
220 NULL);
221
222DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk,
223 RPM_MISC_CLK_TYPE, CXO_ID, 19200000);
224DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
225
226DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID);
227DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID);
228DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID);
229DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID);
230DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID);
231DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID);
232DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID);
233DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID);
234
235DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID);
236DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID);
237DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID);
238DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID);
239DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID);
240
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]241static struct branch_clk oxilicx_axi_clk;
242
243#define MSS_DEBUG_CLOCK_CTL 0x0078
244#define LPASS_DEBUG_CLK_CTL 0x29000
245#define GLB_CLK_DIAG 0x01C
246#define GLB_TEST_BUS_SEL 0x020
247
248#define MMPLL0_PLL_MODE (0x0000)
249#define MMPLL0_PLL_L_VAL (0x0004)
250#define MMPLL0_PLL_M_VAL (0x0008)
251#define MMPLL0_PLL_N_VAL (0x000C)
252#define MMPLL0_PLL_USER_CTL (0x0010)
253#define MMPLL0_PLL_STATUS (0x001C)
254#define MMPLL1_PLL_MODE (0x0040)
255#define MMPLL1_PLL_L_VAL (0x0044)
256#define MMPLL1_PLL_M_VAL (0x0048)
257#define MMPLL1_PLL_N_VAL (0x004C)
258#define MMPLL1_PLL_USER_CTL (0x0050)
259#define MMPLL1_PLL_STATUS (0x005C)
260#define MMSS_PLL_VOTE_APCS (0x0100)
261#define VCODEC0_CMD_RCGR (0x1000)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]262#define VENUS0_BCR (0x1020)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]263#define VENUS0_VCODEC0_CBCR (0x1028)
264#define VENUS0_AHB_CBCR (0x1030)
265#define VENUS0_AXI_CBCR (0x1034)
266#define PCLK0_CMD_RCGR (0x2000)
267#define MDP_CMD_RCGR (0x2040)
268#define VSYNC_CMD_RCGR (0x2080)
269#define BYTE0_CMD_RCGR (0x2120)
270#define ESC0_CMD_RCGR (0x2160)
271#define MDSS_AHB_CBCR (0x2308)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]272#define MDSS_BCR (0x2300)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]273#define MDSS_AXI_CBCR (0x2310)
274#define MDSS_PCLK0_CBCR (0x2314)
275#define MDSS_MDP_CBCR (0x231C)
276#define MDSS_MDP_LUT_CBCR (0x2320)
277#define MDSS_VSYNC_CBCR (0x2328)
278#define MDSS_BYTE0_CBCR (0x233C)
279#define MDSS_ESC0_CBCR (0x2344)
280#define CSI0PHYTIMER_CMD_RCGR (0x3000)
281#define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024)
282#define CSI1PHYTIMER_CMD_RCGR (0x3030)
283#define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054)
284#define CSI0_CMD_RCGR (0x3090)
285#define CAMSS_CSI0_CBCR (0x30B4)
286#define CAMSS_CSI0_AHB_CBCR (0x30BC)
287#define CAMSS_CSI0PHY_CBCR (0x30C4)
288#define CAMSS_CSI0RDI_CBCR (0x30D4)
289#define CAMSS_CSI0PIX_CBCR (0x30E4)
290#define CSI1_CMD_RCGR (0x3100)
291#define CAMSS_CSI1_CBCR (0x3124)
292#define CAMSS_CSI1_AHB_CBCR (0x3128)
293#define CAMSS_CSI1PHY_CBCR (0x3134)
294#define CAMSS_CSI1RDI_CBCR (0x3144)
295#define CAMSS_CSI1PIX_CBCR (0x3154)
296#define CAMSS_ISPIF_AHB_CBCR (0x3224)
297#define CCI_CMD_RCGR (0x3300)
298#define CAMSS_CCI_CCI_CBCR (0x3344)
299#define CAMSS_CCI_CCI_AHB_CBCR (0x3348)
300#define MCLK0_CMD_RCGR (0x3360)
301#define CAMSS_MCLK0_CBCR (0x3384)
302#define MCLK1_CMD_RCGR (0x3390)
303#define CAMSS_MCLK1_CBCR (0x33B4)
304#define MMSS_GP0_CMD_RCGR (0x3420)
305#define CAMSS_GP0_CBCR (0x3444)
306#define MMSS_GP1_CMD_RCGR (0x3450)
307#define CAMSS_GP1_CBCR (0x3474)
308#define CAMSS_TOP_AHB_CBCR (0x3484)
309#define CAMSS_MICRO_AHB_CBCR (0x3494)
310#define JPEG0_CMD_RCGR (0x3500)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]311#define CAMSS_JPEG_BCR (0x35A0)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]312#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
313#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
314#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
315#define VFE0_CMD_RCGR (0x3600)
316#define CPP_CMD_RCGR (0x3640)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]317#define CAMSS_VFE_BCR (0x36A0)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]318#define CAMSS_VFE_VFE0_CBCR (0x36A8)
319#define CAMSS_VFE_CPP_CBCR (0x36B0)
320#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
321#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
322#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]323#define CAMSS_CSI_VFE0_BCR (0x3700)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]324#define CAMSS_CSI_VFE0_CBCR (0x3704)
Rajakumar Govindaram4c2482b2013-09-05 19:45:01 -0700[diff] [blame]325#define CAMSS_MICRO_BCR (0x3490)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]326#define OXILI_GFX3D_CBCR (0x4028)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]327#define OXILICX_BCR (0x4030)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]328#define OXILICX_AXI_CBCR (0x4038)
329#define OXILICX_AHB_CBCR (0x403C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]330#define MMPLL2_PLL_MODE (0x4100)
331#define MMPLL2_PLL_STATUS (0x411C)
332#define MMSS_MMSSNOC_AHB_CBCR (0x5024)
333#define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028)
334#define MMSS_MISC_AHB_CBCR (0x502C)
335#define AXI_CMD_RCGR (0x5040)
336#define MMSS_S0_AXI_CBCR (0x5064)
337#define MMSS_MMSSNOC_AXI_CBCR (0x506C)
338#define MMSS_DEBUG_CLK_CTL (0x0900)
339#define GPLL0_MODE (0x0000)
340#define GPLL0_L_VAL (0x0004)
341#define GPLL0_M_VAL (0x0008)
342#define GPLL0_N_VAL (0x000C)
343#define GPLL0_USER_CTL (0x0010)
344#define GPLL0_STATUS (0x001C)
345#define GPLL1_MODE (0x0040)
346#define GPLL1_L_VAL (0x0044)
347#define GPLL1_M_VAL (0x0048)
348#define GPLL1_N_VAL (0x004C)
349#define GPLL1_USER_CTL (0x0050)
350#define GPLL1_STATUS (0x005C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]351#define NOC_CONF_XPU_AHB_CBCR (0x01C0)
352#define MMSS_NOC_CFG_AHB_CBCR (0x024C)
353#define MSS_CFG_AHB_CBCR (0x0280)
354#define MSS_Q6_BIMC_AXI_CBCR (0x0284)
355#define USB_HS_HSIC_BCR (0x0400)
356#define USB_HSIC_AHB_CBCR (0x0408)
357#define USB_HSIC_SYSTEM_CMD_RCGR (0x041C)
358#define USB_HSIC_SYSTEM_CBCR (0x040C)
359#define USB_HSIC_CMD_RCGR (0x0440)
360#define USB_HSIC_CBCR (0x0410)
361#define USB_HSIC_IO_CAL_CMD_RCGR (0x0458)
362#define USB_HSIC_IO_CAL_CBCR (0x0414)
363#define USB_HS_BCR (0x0480)
364#define USB_HS_SYSTEM_CBCR (0x0484)
365#define USB_HS_AHB_CBCR (0x0488)
366#define USB_HS_SYSTEM_CMD_RCGR (0x0490)
367#define USB2A_PHY_SLEEP_CBCR (0x04AC)
368#define SDCC1_APPS_CMD_RCGR (0x04D0)
369#define SDCC1_APPS_CBCR (0x04C4)
370#define SDCC1_AHB_CBCR (0x04C8)
371#define SDCC2_APPS_CMD_RCGR (0x0510)
372#define SDCC2_APPS_CBCR (0x0504)
373#define SDCC2_AHB_CBCR (0x0508)
374#define SDCC3_APPS_CMD_RCGR (0x0550)
375#define SDCC3_APPS_CBCR (0x0544)
376#define SDCC3_AHB_CBCR (0x0548)
377#define BLSP1_AHB_CBCR (0x05C4)
378#define BLSP1_QUP1_SPI_APPS_CBCR (0x0644)
379#define BLSP1_QUP1_I2C_APPS_CBCR (0x0648)
380#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660)
381#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0)
382#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760)
383#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0)
384#define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860)
385#define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0)
386#define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C)
387#define BLSP1_UART1_APPS_CBCR (0x0684)
388#define BLSP1_UART1_APPS_CMD_RCGR (0x068C)
389#define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4)
390#define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8)
391#define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC)
392#define BLSP1_UART2_APPS_CBCR (0x0704)
393#define BLSP1_UART2_APPS_CMD_RCGR (0x070C)
394#define BLSP1_QUP3_SPI_APPS_CBCR (0x0744)
395#define BLSP1_QUP3_I2C_APPS_CBCR (0x0748)
396#define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C)
397#define BLSP1_UART3_APPS_CBCR (0x0784)
398#define BLSP1_UART3_APPS_CMD_RCGR (0x078C)
399#define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4)
400#define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8)
401#define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC)
402#define BLSP1_UART4_APPS_CBCR (0x0804)
403#define BLSP1_UART4_APPS_CMD_RCGR (0x080C)
404#define BLSP1_QUP5_SPI_APPS_CBCR (0x0844)
405#define BLSP1_QUP5_I2C_APPS_CBCR (0x0848)
406#define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C)
407#define BLSP1_UART5_APPS_CBCR (0x0884)
408#define BLSP1_UART5_APPS_CMD_RCGR (0x088C)
409#define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4)
410#define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8)
411#define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC)
412#define BLSP1_UART6_APPS_CBCR (0x0904)
413#define BLSP1_UART6_APPS_CMD_RCGR (0x090C)
414#define PDM_AHB_CBCR (0x0CC4)
415#define PDM_XO4_CBCR (0x0CC8)
416#define PDM2_CBCR (0x0CCC)
417#define PDM2_CMD_RCGR (0x0CD0)
418#define PRNG_AHB_CBCR (0x0D04)
419#define BAM_DMA_AHB_CBCR (0x0D44)
420#define BOOT_ROM_AHB_CBCR (0x0E04)
421#define CE1_CMD_RCGR (0x1050)
422#define CE1_CBCR (0x1044)
423#define CE1_AXI_CBCR (0x1048)
424#define CE1_AHB_CBCR (0x104C)
425#define GCC_XO_DIV4_CBCR (0x10C8)
426#define LPASS_Q6_AXI_CBCR (0x11C0)
427#define APCS_GPLL_ENA_VOTE (0x1480)
428#define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484)
429#define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488)
430#define GCC_DEBUG_CLK_CTL (0x1880)
431#define CLOCK_FRQ_MEASURE_CTL (0x1884)
432#define CLOCK_FRQ_MEASURE_STATUS (0x1888)
433#define PLLTEST_PAD_CFG (0x188C)
434#define GP1_CBCR (0x1900)
435#define GP1_CMD_RCGR (0x1904)
436#define GP2_CBCR (0x1940)
437#define GP2_CMD_RCGR (0x1944)
438#define GP3_CBCR (0x1980)
439#define GP3_CMD_RCGR (0x1984)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]440#define Q6SS_BCR (0x6000)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]441#define Q6SS_AHB_LFABIF_CBCR (0x22000)
442#define Q6SS_AHBM_CBCR (0x22004)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]443#define Q6SS_XO_CBCR (0x26000)
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]444#define KPSS_AHB_CMD_RCGR (0x120C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]445
446static unsigned int soft_vote_gpll0;
447
448static struct pll_vote_clk gpll0 = {
449 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
450 .en_mask = BIT(0),
451 .status_reg = (void __iomem *)GPLL0_STATUS,
452 .status_mask = BIT(17),
453 .soft_vote = &soft_vote_gpll0,
454 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
455 .base = &virt_bases[GCC_BASE],
456 .c = {
457 .rate = 600000000,
458 .parent = &xo.c,
459 .dbg_name = "gpll0",
460 .ops = &clk_ops_pll_acpu_vote,
461 CLK_INIT(gpll0.c),
462 },
463};
464
465/*Don't vote for xo if using this clock to allow xo shutdown*/
466static struct pll_vote_clk gpll0_ao = {
467 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
468 .en_mask = BIT(0),
469 .status_reg = (void __iomem *)GPLL0_STATUS,
470 .status_mask = BIT(17),
471 .soft_vote = &soft_vote_gpll0,
472 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
473 .base = &virt_bases[GCC_BASE],
474 .c = {
475 .rate = 600000000,
476 .dbg_name = "gpll0_ao",
477 .ops = &clk_ops_pll_acpu_vote,
478 CLK_INIT(gpll0_ao.c),
479 },
480};
481
482static struct pll_vote_clk gpll1 = {
483 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
484 .en_mask = BIT(1),
485 .status_reg = (void __iomem *)GPLL1_STATUS,
486 .status_mask = BIT(17),
487 .base = &virt_bases[GCC_BASE],
488 .c = {
489 .rate = 480000000,
490 .parent = &xo.c,
491 .dbg_name = "gpll1",
492 .ops = &clk_ops_pll_vote,
493 CLK_INIT(gpll1.c),
494 },
495};
496
497static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]498 F_GCC( 19200000, xo, 1, 0, 0),
499 F_GCC( 50000000, gpll0, 12, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]500 F_END
501};
502
503static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
504 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
505 .set_rate = set_rate_hid,
506 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
507 .current_freq = &rcg_dummy_freq,
508 .base = &virt_bases[GCC_BASE],
509 .c = {
510 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
511 .ops = &clk_ops_rcg,
512 VDD_DIG_FMAX_MAP1(LOW, 50000000),
513 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
514 },
515};
516
517static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
518 F_GCC( 960000, xo, 10, 1, 2),
519 F_GCC( 4800000, xo, 4, 0, 0),
520 F_GCC( 9600000, xo, 2, 0, 0),
521 F_GCC( 15000000, gpll0, 10, 1, 4),
522 F_GCC( 19200000, xo, 1, 0, 0),
523 F_GCC( 25000000, gpll0, 12, 1, 2),
524 F_GCC( 50000000, gpll0, 12, 0, 0),
525 F_END
526};
527
528static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
529 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
530 .set_rate = set_rate_mnd,
531 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
532 .current_freq = &rcg_dummy_freq,
533 .base = &virt_bases[GCC_BASE],
534 .c = {
535 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
536 .ops = &clk_ops_rcg_mnd,
537 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
538 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
539 },
540};
541
542static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
543 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
544 .set_rate = set_rate_hid,
545 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
546 .current_freq = &rcg_dummy_freq,
547 .base = &virt_bases[GCC_BASE],
548 .c = {
549 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
550 .ops = &clk_ops_rcg,
551 VDD_DIG_FMAX_MAP1(LOW, 50000000),
552 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
553 },
554};
555
556static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
557 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
558 .set_rate = set_rate_mnd,
559 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
560 .current_freq = &rcg_dummy_freq,
561 .base = &virt_bases[GCC_BASE],
562 .c = {
563 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
564 .ops = &clk_ops_rcg_mnd,
565 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
566 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
567 },
568};
569
570static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
571 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
572 .set_rate = set_rate_hid,
573 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
574 .current_freq = &rcg_dummy_freq,
575 .base = &virt_bases[GCC_BASE],
576 .c = {
577 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
578 .ops = &clk_ops_rcg,
579 VDD_DIG_FMAX_MAP1(LOW, 50000000),
580 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
581 },
582};
583
584static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
585 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
586 .set_rate = set_rate_mnd,
587 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
588 .current_freq = &rcg_dummy_freq,
589 .base = &virt_bases[GCC_BASE],
590 .c = {
591 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
592 .ops = &clk_ops_rcg_mnd,
593 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
594 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
595 },
596};
597
598static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
599 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
600 .set_rate = set_rate_hid,
601 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
602 .current_freq = &rcg_dummy_freq,
603 .base = &virt_bases[GCC_BASE],
604 .c = {
605 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
606 .ops = &clk_ops_rcg,
607 VDD_DIG_FMAX_MAP1(LOW, 50000000),
608 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
609 },
610};
611
612static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
613 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
614 .set_rate = set_rate_mnd,
615 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
616 .current_freq = &rcg_dummy_freq,
617 .base = &virt_bases[GCC_BASE],
618 .c = {
619 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
620 .ops = &clk_ops_rcg_mnd,
621 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
622 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
623 },
624};
625
626static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
627 .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR,
628 .set_rate = set_rate_hid,
629 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
630 .current_freq = &rcg_dummy_freq,
631 .base = &virt_bases[GCC_BASE],
632 .c = {
633 .dbg_name = "blsp1_qup5_i2c_apps_clk_src",
634 .ops = &clk_ops_rcg,
635 VDD_DIG_FMAX_MAP1(LOW, 50000000),
636 CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
637 },
638};
639
640static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
641 .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR,
642 .set_rate = set_rate_mnd,
643 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
644 .current_freq = &rcg_dummy_freq,
645 .base = &virt_bases[GCC_BASE],
646 .c = {
647 .dbg_name = "blsp1_qup5_spi_apps_clk_src",
648 .ops = &clk_ops_rcg_mnd,
649 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
650 CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
651 },
652};
653
654static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
655 .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR,
656 .set_rate = set_rate_hid,
657 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
658 .current_freq = &rcg_dummy_freq,
659 .base = &virt_bases[GCC_BASE],
660 .c = {
661 .dbg_name = "blsp1_qup6_i2c_apps_clk_src",
662 .ops = &clk_ops_rcg,
663 VDD_DIG_FMAX_MAP1(LOW, 50000000),
664 CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
665 },
666};
667
668static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
669 .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR,
670 .set_rate = set_rate_mnd,
671 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
672 .current_freq = &rcg_dummy_freq,
673 .base = &virt_bases[GCC_BASE],
674 .c = {
675 .dbg_name = "blsp1_qup6_spi_apps_clk_src",
676 .ops = &clk_ops_rcg_mnd,
677 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
678 CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
679 },
680};
681
682static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
683 F_GCC( 3686400, gpll0, 1, 96, 15625),
684 F_GCC( 7372800, gpll0, 1, 192, 15625),
685 F_GCC( 14745600, gpll0, 1, 384, 15625),
686 F_GCC( 16000000, gpll0, 5, 2, 15),
687 F_GCC( 19200000, xo, 1, 0, 0),
688 F_GCC( 24000000, gpll0, 5, 1, 5),
689 F_GCC( 32000000, gpll0, 1, 4, 75),
690 F_GCC( 40000000, gpll0, 15, 0, 0),
691 F_GCC( 46400000, gpll0, 1, 29, 375),
692 F_GCC( 48000000, gpll0, 12.5, 0, 0),
693 F_GCC( 51200000, gpll0, 1, 32, 375),
694 F_GCC( 56000000, gpll0, 1, 7, 75),
695 F_GCC( 58982400, gpll0, 1, 1536, 15625),
696 F_GCC( 60000000, gpll0, 10, 0, 0),
697 F_END
698};
699
700static struct rcg_clk blsp1_uart1_apps_clk_src = {
701 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
702 .set_rate = set_rate_mnd,
703 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
704 .current_freq = &rcg_dummy_freq,
705 .base = &virt_bases[GCC_BASE],
706 .c = {
707 .dbg_name = "blsp1_uart1_apps_clk_src",
708 .ops = &clk_ops_rcg_mnd,
709 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
710 CLK_INIT(blsp1_uart1_apps_clk_src.c),
711 },
712};
713
714static struct rcg_clk blsp1_uart2_apps_clk_src = {
715 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
716 .set_rate = set_rate_mnd,
717 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
718 .current_freq = &rcg_dummy_freq,
719 .base = &virt_bases[GCC_BASE],
720 .c = {
721 .dbg_name = "blsp1_uart2_apps_clk_src",
722 .ops = &clk_ops_rcg_mnd,
723 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
724 CLK_INIT(blsp1_uart2_apps_clk_src.c),
725 },
726};
727
728static struct rcg_clk blsp1_uart3_apps_clk_src = {
729 .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR,
730 .set_rate = set_rate_mnd,
731 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
732 .current_freq = &rcg_dummy_freq,
733 .base = &virt_bases[GCC_BASE],
734 .c = {
735 .dbg_name = "blsp1_uart3_apps_clk_src",
736 .ops = &clk_ops_rcg_mnd,
737 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
738 CLK_INIT(blsp1_uart3_apps_clk_src.c),
739 },
740};
741
742static struct rcg_clk blsp1_uart4_apps_clk_src = {
743 .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR,
744 .set_rate = set_rate_mnd,
745 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
746 .current_freq = &rcg_dummy_freq,
747 .base = &virt_bases[GCC_BASE],
748 .c = {
749 .dbg_name = "blsp1_uart4_apps_clk_src",
750 .ops = &clk_ops_rcg_mnd,
751 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
752 CLK_INIT(blsp1_uart4_apps_clk_src.c),
753 },
754};
755
756static struct rcg_clk blsp1_uart5_apps_clk_src = {
757 .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR,
758 .set_rate = set_rate_mnd,
759 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
760 .current_freq = &rcg_dummy_freq,
761 .base = &virt_bases[GCC_BASE],
762 .c = {
763 .dbg_name = "blsp1_uart5_apps_clk_src",
764 .ops = &clk_ops_rcg_mnd,
765 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
766 CLK_INIT(blsp1_uart5_apps_clk_src.c),
767 },
768};
769
770static struct rcg_clk blsp1_uart6_apps_clk_src = {
771 .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR,
772 .set_rate = set_rate_mnd,
773 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
774 .current_freq = &rcg_dummy_freq,
775 .base = &virt_bases[GCC_BASE],
776 .c = {
777 .dbg_name = "blsp1_uart6_apps_clk_src",
778 .ops = &clk_ops_rcg_mnd,
779 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
780 CLK_INIT(blsp1_uart6_apps_clk_src.c),
781 },
782};
783
784static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
785 F_GCC( 50000000, gpll0, 12, 0, 0),
786 F_GCC( 100000000, gpll0, 6, 0, 0),
787 F_END
788};
789
790static struct rcg_clk ce1_clk_src = {
791 .cmd_rcgr_reg = CE1_CMD_RCGR,
792 .set_rate = set_rate_hid,
793 .freq_tbl = ftbl_gcc_ce1_clk,
794 .current_freq = &rcg_dummy_freq,
795 .base = &virt_bases[GCC_BASE],
796 .c = {
797 .dbg_name = "ce1_clk_src",
798 .ops = &clk_ops_rcg,
799 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
800 CLK_INIT(ce1_clk_src.c),
801 },
802};
803
804static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
805 F_GCC( 19200000, xo, 1, 0, 0),
806 F_END
807};
808
809static struct rcg_clk gp1_clk_src = {
810 .cmd_rcgr_reg = GP1_CMD_RCGR,
811 .set_rate = set_rate_mnd,
812 .freq_tbl = ftbl_gcc_gp1_3_clk,
813 .current_freq = &rcg_dummy_freq,
814 .base = &virt_bases[GCC_BASE],
815 .c = {
816 .dbg_name = "gp1_clk_src",
817 .ops = &clk_ops_rcg_mnd,
818 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
819 CLK_INIT(gp1_clk_src.c),
820 },
821};
822
823static struct rcg_clk gp2_clk_src = {
824 .cmd_rcgr_reg = GP2_CMD_RCGR,
825 .set_rate = set_rate_mnd,
826 .freq_tbl = ftbl_gcc_gp1_3_clk,
827 .current_freq = &rcg_dummy_freq,
828 .base = &virt_bases[GCC_BASE],
829 .c = {
830 .dbg_name = "gp2_clk_src",
831 .ops = &clk_ops_rcg_mnd,
832 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
833 CLK_INIT(gp2_clk_src.c),
834 },
835};
836
837static struct rcg_clk gp3_clk_src = {
838 .cmd_rcgr_reg = GP3_CMD_RCGR,
839 .set_rate = set_rate_mnd,
840 .freq_tbl = ftbl_gcc_gp1_3_clk,
841 .current_freq = &rcg_dummy_freq,
842 .base = &virt_bases[GCC_BASE],
843 .c = {
844 .dbg_name = "gp3_clk_src",
845 .ops = &clk_ops_rcg_mnd,
846 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
847 CLK_INIT(gp3_clk_src.c),
848 },
849};
850
851static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
852 F_GCC( 60000000, gpll0, 10, 0, 0),
853 F_END
854};
855
856static struct rcg_clk pdm2_clk_src = {
857 .cmd_rcgr_reg = PDM2_CMD_RCGR,
858 .set_rate = set_rate_hid,
859 .freq_tbl = ftbl_gcc_pdm2_clk,
860 .current_freq = &rcg_dummy_freq,
861 .base = &virt_bases[GCC_BASE],
862 .c = {
863 .dbg_name = "pdm2_clk_src",
864 .ops = &clk_ops_rcg,
865 VDD_DIG_FMAX_MAP1(LOW, 60000000),
866 CLK_INIT(pdm2_clk_src.c),
867 },
868};
869
870static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = {
871 F_GCC( 144000, xo, 16, 3, 25),
872 F_GCC( 400000, xo, 12, 1, 4),
873 F_GCC( 20000000, gpll0, 15, 1, 2),
874 F_GCC( 25000000, gpll0, 12, 1, 2),
875 F_GCC( 50000000, gpll0, 12, 0, 0),
876 F_GCC( 100000000, gpll0, 6, 0, 0),
877 F_GCC( 200000000, gpll0, 3, 0, 0),
878 F_END
879};
880
881static struct rcg_clk sdcc1_apps_clk_src = {
882 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
883 .set_rate = set_rate_mnd,
884 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
885 .current_freq = &rcg_dummy_freq,
886 .base = &virt_bases[GCC_BASE],
887 .c = {
888 .dbg_name = "sdcc1_apps_clk_src",
889 .ops = &clk_ops_rcg_mnd,
890 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
891 CLK_INIT(sdcc1_apps_clk_src.c),
892 },
893};
894
895static struct rcg_clk sdcc2_apps_clk_src = {
896 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
897 .set_rate = set_rate_mnd,
898 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
899 .current_freq = &rcg_dummy_freq,
900 .base = &virt_bases[GCC_BASE],
901 .c = {
902 .dbg_name = "sdcc2_apps_clk_src",
903 .ops = &clk_ops_rcg_mnd,
904 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
905 CLK_INIT(sdcc2_apps_clk_src.c),
906 },
907};
908
909static struct rcg_clk sdcc3_apps_clk_src = {
910 .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,
911 .set_rate = set_rate_mnd,
912 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
913 .current_freq = &rcg_dummy_freq,
914 .base = &virt_bases[GCC_BASE],
915 .c = {
916 .dbg_name = "sdcc3_apps_clk_src",
917 .ops = &clk_ops_rcg_mnd,
918 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
919 CLK_INIT(sdcc3_apps_clk_src.c),
920 },
921};
922
923static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
924 F_GCC( 75000000, gpll0, 8, 0, 0),
925 F_END
926};
927
928static struct rcg_clk usb_hs_system_clk_src = {
929 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
930 .set_rate = set_rate_hid,
931 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
932 .current_freq = &rcg_dummy_freq,
933 .base = &virt_bases[GCC_BASE],
934 .c = {
935 .dbg_name = "usb_hs_system_clk_src",
936 .ops = &clk_ops_rcg,
937 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
938 CLK_INIT(usb_hs_system_clk_src.c),
939 },
940};
941
942static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = {
943 F_HSIC( 480000000, gpll1, 0, 0, 0),
944 F_END
945};
946
947static struct rcg_clk usb_hsic_clk_src = {
948 .cmd_rcgr_reg = USB_HSIC_CMD_RCGR,
949 .set_rate = set_rate_hid,
950 .freq_tbl = ftbl_gcc_usb_hsic_clk,
951 .current_freq = &rcg_dummy_freq,
952 .base = &virt_bases[GCC_BASE],
953 .c = {
954 .dbg_name = "usb_hsic_clk_src",
955 .ops = &clk_ops_rcg,
956 VDD_DIG_FMAX_MAP1(LOW, 480000000),
957 CLK_INIT(usb_hsic_clk_src.c),
958 },
959};
960
961static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
962 F_GCC( 9600000, xo, 2, 0, 0),
963 F_END
964};
965
966static struct rcg_clk usb_hsic_io_cal_clk_src = {
967 .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR,
968 .set_rate = set_rate_hid,
969 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
970 .current_freq = &rcg_dummy_freq,
971 .base = &virt_bases[GCC_BASE],
972 .c = {
973 .dbg_name = "usb_hsic_io_cal_clk_src",
974 .ops = &clk_ops_rcg,
975 VDD_DIG_FMAX_MAP1(LOW, 9600000),
976 CLK_INIT(usb_hsic_io_cal_clk_src.c),
977 },
978};
979
980static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
981 F_GCC( 75000000, gpll0, 8, 0, 0),
982 F_END
983};
984
985static struct rcg_clk usb_hsic_system_clk_src = {
986 .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR,
987 .set_rate = set_rate_hid,
988 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
989 .current_freq = &rcg_dummy_freq,
990 .base = &virt_bases[GCC_BASE],
991 .c = {
992 .dbg_name = "usb_hsic_system_clk_src",
993 .ops = &clk_ops_rcg,
994 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
995 CLK_INIT(usb_hsic_system_clk_src.c),
996 },
997};
998
999static struct local_vote_clk gcc_bam_dma_ahb_clk = {
1000 .cbcr_reg = BAM_DMA_AHB_CBCR,
1001 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1002 .en_mask = BIT(12),
1003 .base = &virt_bases[GCC_BASE],
1004 .c = {
1005 .dbg_name = "gcc_bam_dma_ahb_clk",
1006 .ops = &clk_ops_vote,
1007 CLK_INIT(gcc_bam_dma_ahb_clk.c),
1008 },
1009};
1010
1011static struct local_vote_clk gcc_blsp1_ahb_clk = {
1012 .cbcr_reg = BLSP1_AHB_CBCR,
1013 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1014 .en_mask = BIT(17),
1015 .base = &virt_bases[GCC_BASE],
1016 .c = {
1017 .dbg_name = "gcc_blsp1_ahb_clk",
1018 .ops = &clk_ops_vote,
1019 CLK_INIT(gcc_blsp1_ahb_clk.c),
1020 },
1021};
1022
1023static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1024 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1025 .has_sibling = 0,
1026 .base = &virt_bases[GCC_BASE],
1027 .c = {
1028 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1029 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1030 .ops = &clk_ops_branch,
1031 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1032 },
1033};
1034
1035static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1036 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1037 .has_sibling = 0,
1038 .base = &virt_bases[GCC_BASE],
1039 .c = {
1040 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1041 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1042 .ops = &clk_ops_branch,
1043 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1044 },
1045};
1046
1047static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1048 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1049 .has_sibling = 0,
1050 .base = &virt_bases[GCC_BASE],
1051 .c = {
1052 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1053 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1054 .ops = &clk_ops_branch,
1055 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1056 },
1057};
1058
1059static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1060 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1061 .has_sibling = 0,
1062 .base = &virt_bases[GCC_BASE],
1063 .c = {
1064 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1065 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1066 .ops = &clk_ops_branch,
1067 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1068 },
1069};
1070
1071static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1072 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1073 .has_sibling = 0,
1074 .base = &virt_bases[GCC_BASE],
1075 .c = {
1076 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1077 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1078 .ops = &clk_ops_branch,
1079 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1080 },
1081};
1082
1083static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1084 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1085 .has_sibling = 0,
1086 .base = &virt_bases[GCC_BASE],
1087 .c = {
1088 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1089 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1090 .ops = &clk_ops_branch,
1091 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1092 },
1093};
1094
1095static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
1096 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
1097 .has_sibling = 0,
1098 .base = &virt_bases[GCC_BASE],
1099 .c = {
1100 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
1101 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
1102 .ops = &clk_ops_branch,
1103 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
1104 },
1105};
1106
1107static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
1108 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
1109 .has_sibling = 0,
1110 .base = &virt_bases[GCC_BASE],
1111 .c = {
1112 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
1113 .parent = &blsp1_qup4_spi_apps_clk_src.c,
1114 .ops = &clk_ops_branch,
1115 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
1116 },
1117};
1118
1119static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
1120 .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
1121 .has_sibling = 0,
1122 .base = &virt_bases[GCC_BASE],
1123 .c = {
1124 .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
1125 .parent = &blsp1_qup5_i2c_apps_clk_src.c,
1126 .ops = &clk_ops_branch,
1127 CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
1128 },
1129};
1130
1131static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
1132 .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
1133 .has_sibling = 0,
1134 .base = &virt_bases[GCC_BASE],
1135 .c = {
1136 .dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
1137 .parent = &blsp1_qup5_spi_apps_clk_src.c,
1138 .ops = &clk_ops_branch,
1139 CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
1140 },
1141};
1142
1143static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
1144 .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
1145 .has_sibling = 0,
1146 .base = &virt_bases[GCC_BASE],
1147 .c = {
1148 .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
1149 .parent = &blsp1_qup6_i2c_apps_clk_src.c,
1150 .ops = &clk_ops_branch,
1151 CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
1152 },
1153};
1154
1155static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
1156 .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
1157 .has_sibling = 0,
1158 .base = &virt_bases[GCC_BASE],
1159 .c = {
1160 .dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
1161 .parent = &blsp1_qup6_spi_apps_clk_src.c,
1162 .ops = &clk_ops_branch,
1163 CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
1164 },
1165};
1166
1167static struct branch_clk gcc_blsp1_uart1_apps_clk = {
1168 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
1169 .has_sibling = 0,
1170 .base = &virt_bases[GCC_BASE],
1171 .c = {
1172 .dbg_name = "gcc_blsp1_uart1_apps_clk",
1173 .parent = &blsp1_uart1_apps_clk_src.c,
1174 .ops = &clk_ops_branch,
1175 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
1176 },
1177};
1178
1179static struct branch_clk gcc_blsp1_uart2_apps_clk = {
1180 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
1181 .has_sibling = 0,
1182 .base = &virt_bases[GCC_BASE],
1183 .c = {
1184 .dbg_name = "gcc_blsp1_uart2_apps_clk",
1185 .parent = &blsp1_uart2_apps_clk_src.c,
1186 .ops = &clk_ops_branch,
1187 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
1188 },
1189};
1190
1191static struct branch_clk gcc_blsp1_uart3_apps_clk = {
1192 .cbcr_reg = BLSP1_UART3_APPS_CBCR,
1193 .has_sibling = 0,
1194 .base = &virt_bases[GCC_BASE],
1195 .c = {
1196 .dbg_name = "gcc_blsp1_uart3_apps_clk",
1197 .parent = &blsp1_uart3_apps_clk_src.c,
1198 .ops = &clk_ops_branch,
1199 CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
1200 },
1201};
1202
1203static struct branch_clk gcc_blsp1_uart4_apps_clk = {
1204 .cbcr_reg = BLSP1_UART4_APPS_CBCR,
1205 .has_sibling = 0,
1206 .base = &virt_bases[GCC_BASE],
1207 .c = {
1208 .dbg_name = "gcc_blsp1_uart4_apps_clk",
1209 .parent = &blsp1_uart4_apps_clk_src.c,
1210 .ops = &clk_ops_branch,
1211 CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
1212 },
1213};
1214
1215static struct branch_clk gcc_blsp1_uart5_apps_clk = {
1216 .cbcr_reg = BLSP1_UART5_APPS_CBCR,
1217 .has_sibling = 0,
1218 .base = &virt_bases[GCC_BASE],
1219 .c = {
1220 .dbg_name = "gcc_blsp1_uart5_apps_clk",
1221 .parent = &blsp1_uart5_apps_clk_src.c,
1222 .ops = &clk_ops_branch,
1223 CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
1224 },
1225};
1226
1227static struct branch_clk gcc_blsp1_uart6_apps_clk = {
1228 .cbcr_reg = BLSP1_UART6_APPS_CBCR,
1229 .has_sibling = 0,
1230 .base = &virt_bases[GCC_BASE],
1231 .c = {
1232 .dbg_name = "gcc_blsp1_uart6_apps_clk",
1233 .parent = &blsp1_uart6_apps_clk_src.c,
1234 .ops = &clk_ops_branch,
1235 CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
1236 },
1237};
1238
1239static struct local_vote_clk gcc_boot_rom_ahb_clk = {
1240 .cbcr_reg = BOOT_ROM_AHB_CBCR,
1241 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1242 .en_mask = BIT(10),
1243 .base = &virt_bases[GCC_BASE],
1244 .c = {
1245 .dbg_name = "gcc_boot_rom_ahb_clk",
1246 .ops = &clk_ops_vote,
1247 CLK_INIT(gcc_boot_rom_ahb_clk.c),
1248 },
1249};
1250
1251static struct local_vote_clk gcc_ce1_ahb_clk = {
1252 .cbcr_reg = CE1_AHB_CBCR,
1253 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1254 .en_mask = BIT(3),
1255 .base = &virt_bases[GCC_BASE],
1256 .c = {
1257 .dbg_name = "gcc_ce1_ahb_clk",
1258 .ops = &clk_ops_vote,
1259 CLK_INIT(gcc_ce1_ahb_clk.c),
1260 },
1261};
1262
1263static struct local_vote_clk gcc_ce1_axi_clk = {
1264 .cbcr_reg = CE1_AXI_CBCR,
1265 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1266 .en_mask = BIT(4),
1267 .base = &virt_bases[GCC_BASE],
1268 .c = {
1269 .dbg_name = "gcc_ce1_axi_clk",
1270 .ops = &clk_ops_vote,
1271 CLK_INIT(gcc_ce1_axi_clk.c),
1272 },
1273};
1274
1275static struct local_vote_clk gcc_ce1_clk = {
1276 .cbcr_reg = CE1_CBCR,
1277 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1278 .en_mask = BIT(5),
1279 .base = &virt_bases[GCC_BASE],
1280 .c = {
1281 .dbg_name = "gcc_ce1_clk",
1282 .ops = &clk_ops_vote,
1283 CLK_INIT(gcc_ce1_clk.c),
1284 },
1285};
1286
1287static struct branch_clk gcc_gp1_clk = {
1288 .cbcr_reg = GP1_CBCR,
1289 .has_sibling = 0,
1290 .base = &virt_bases[GCC_BASE],
1291 .c = {
1292 .dbg_name = "gcc_gp1_clk",
1293 .parent = &gp1_clk_src.c,
1294 .ops = &clk_ops_branch,
1295 CLK_INIT(gcc_gp1_clk.c),
1296 },
1297};
1298
1299static struct branch_clk gcc_gp2_clk = {
1300 .cbcr_reg = GP2_CBCR,
1301 .has_sibling = 0,
1302 .base = &virt_bases[GCC_BASE],
1303 .c = {
1304 .dbg_name = "gcc_gp2_clk",
1305 .parent = &gp2_clk_src.c,
1306 .ops = &clk_ops_branch,
1307 CLK_INIT(gcc_gp2_clk.c),
1308 },
1309};
1310
1311static struct branch_clk gcc_gp3_clk = {
1312 .cbcr_reg = GP3_CBCR,
1313 .has_sibling = 0,
1314 .base = &virt_bases[GCC_BASE],
1315 .c = {
1316 .dbg_name = "gcc_gp3_clk",
1317 .parent = &gp3_clk_src.c,
1318 .ops = &clk_ops_branch,
1319 CLK_INIT(gcc_gp3_clk.c),
1320 },
1321};
1322
1323static struct branch_clk gcc_lpass_q6_axi_clk = {
1324 .cbcr_reg = LPASS_Q6_AXI_CBCR,
1325 .has_sibling = 1,
1326 .base = &virt_bases[GCC_BASE],
1327 .c = {
1328 .dbg_name = "gcc_lpass_q6_axi_clk",
1329 .ops = &clk_ops_branch,
1330 CLK_INIT(gcc_lpass_q6_axi_clk.c),
1331 },
1332};
1333
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1334static struct branch_clk gcc_mss_cfg_ahb_clk = {
1335 .cbcr_reg = MSS_CFG_AHB_CBCR,
1336 .has_sibling = 1,
1337 .base = &virt_bases[GCC_BASE],
1338 .c = {
1339 .dbg_name = "gcc_mss_cfg_ahb_clk",
1340 .ops = &clk_ops_branch,
1341 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
1342 },
1343};
1344
1345static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
1346 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
1347 .has_sibling = 1,
1348 .base = &virt_bases[GCC_BASE],
1349 .c = {
1350 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
1351 .ops = &clk_ops_branch,
1352 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
1353 },
1354};
1355
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1356static struct branch_clk gcc_pdm2_clk = {
1357 .cbcr_reg = PDM2_CBCR,
1358 .has_sibling = 0,
1359 .base = &virt_bases[GCC_BASE],
1360 .c = {
1361 .dbg_name = "gcc_pdm2_clk",
1362 .parent = &pdm2_clk_src.c,
1363 .ops = &clk_ops_branch,
1364 CLK_INIT(gcc_pdm2_clk.c),
1365 },
1366};
1367
1368static struct branch_clk gcc_pdm_ahb_clk = {
1369 .cbcr_reg = PDM_AHB_CBCR,
1370 .has_sibling = 1,
1371 .base = &virt_bases[GCC_BASE],
1372 .c = {
1373 .dbg_name = "gcc_pdm_ahb_clk",
1374 .ops = &clk_ops_branch,
1375 CLK_INIT(gcc_pdm_ahb_clk.c),
1376 },
1377};
1378
1379static struct branch_clk gcc_pdm_xo4_clk = {
1380 .cbcr_reg = PDM_XO4_CBCR,
1381 .has_sibling = 1,
1382 .base = &virt_bases[GCC_BASE],
1383 .c = {
1384 .dbg_name = "gcc_pdm_xo4_clk",
1385 .parent = &xo.c,
1386 .ops = &clk_ops_branch,
1387 CLK_INIT(gcc_pdm_xo4_clk.c),
1388 },
1389};
1390
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1391static struct local_vote_clk gcc_prng_ahb_clk = {
1392 .cbcr_reg = PRNG_AHB_CBCR,
1393 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1394 .en_mask = BIT(13),
1395 .base = &virt_bases[GCC_BASE],
1396 .c = {
1397 .dbg_name = "gcc_prng_ahb_clk",
1398 .ops = &clk_ops_vote,
1399 CLK_INIT(gcc_prng_ahb_clk.c),
1400 },
1401};
1402
1403static struct branch_clk gcc_sdcc1_ahb_clk = {
1404 .cbcr_reg = SDCC1_AHB_CBCR,
1405 .has_sibling = 1,
1406 .base = &virt_bases[GCC_BASE],
1407 .c = {
1408 .dbg_name = "gcc_sdcc1_ahb_clk",
1409 .ops = &clk_ops_branch,
1410 CLK_INIT(gcc_sdcc1_ahb_clk.c),
1411 },
1412};
1413
1414static struct branch_clk gcc_sdcc1_apps_clk = {
1415 .cbcr_reg = SDCC1_APPS_CBCR,
1416 .has_sibling = 0,
1417 .base = &virt_bases[GCC_BASE],
1418 .c = {
1419 .dbg_name = "gcc_sdcc1_apps_clk",
1420 .parent = &sdcc1_apps_clk_src.c,
1421 .ops = &clk_ops_branch,
1422 CLK_INIT(gcc_sdcc1_apps_clk.c),
1423 },
1424};
1425
1426static struct branch_clk gcc_sdcc2_ahb_clk = {
1427 .cbcr_reg = SDCC2_AHB_CBCR,
1428 .has_sibling = 1,
1429 .base = &virt_bases[GCC_BASE],
1430 .c = {
1431 .dbg_name = "gcc_sdcc2_ahb_clk",
1432 .ops = &clk_ops_branch,
1433 CLK_INIT(gcc_sdcc2_ahb_clk.c),
1434 },
1435};
1436
1437static struct branch_clk gcc_sdcc2_apps_clk = {
1438 .cbcr_reg = SDCC2_APPS_CBCR,
1439 .has_sibling = 0,
1440 .base = &virt_bases[GCC_BASE],
1441 .c = {
1442 .dbg_name = "gcc_sdcc2_apps_clk",
1443 .parent = &sdcc2_apps_clk_src.c,
1444 .ops = &clk_ops_branch,
1445 CLK_INIT(gcc_sdcc2_apps_clk.c),
1446 },
1447};
1448
1449static struct branch_clk gcc_sdcc3_ahb_clk = {
1450 .cbcr_reg = SDCC3_AHB_CBCR,
1451 .has_sibling = 1,
1452 .base = &virt_bases[GCC_BASE],
1453 .c = {
1454 .dbg_name = "gcc_sdcc3_ahb_clk",
1455 .ops = &clk_ops_branch,
1456 CLK_INIT(gcc_sdcc3_ahb_clk.c),
1457 },
1458};
1459
1460static struct branch_clk gcc_sdcc3_apps_clk = {
1461 .cbcr_reg = SDCC3_APPS_CBCR,
1462 .has_sibling = 0,
1463 .base = &virt_bases[GCC_BASE],
1464 .c = {
1465 .dbg_name = "gcc_sdcc3_apps_clk",
1466 .parent = &sdcc3_apps_clk_src.c,
1467 .ops = &clk_ops_branch,
1468 CLK_INIT(gcc_sdcc3_apps_clk.c),
1469 },
1470};
1471
1472static struct branch_clk gcc_usb2a_phy_sleep_clk = {
1473 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
1474 .has_sibling = 1,
1475 .base = &virt_bases[GCC_BASE],
1476 .c = {
1477 .dbg_name = "gcc_usb2a_phy_sleep_clk",
1478 .ops = &clk_ops_branch,
1479 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
1480 },
1481};
1482
1483static struct branch_clk gcc_usb_hs_ahb_clk = {
1484 .cbcr_reg = USB_HS_AHB_CBCR,
1485 .has_sibling = 1,
1486 .base = &virt_bases[GCC_BASE],
1487 .c = {
1488 .dbg_name = "gcc_usb_hs_ahb_clk",
1489 .ops = &clk_ops_branch,
1490 CLK_INIT(gcc_usb_hs_ahb_clk.c),
1491 },
1492};
1493
1494static struct branch_clk gcc_usb_hs_system_clk = {
1495 .cbcr_reg = USB_HS_SYSTEM_CBCR,
1496 .has_sibling = 0,
1497 .bcr_reg = USB_HS_BCR,
1498 .base = &virt_bases[GCC_BASE],
1499 .c = {
1500 .dbg_name = "gcc_usb_hs_system_clk",
1501 .parent = &usb_hs_system_clk_src.c,
1502 .ops = &clk_ops_branch,
1503 CLK_INIT(gcc_usb_hs_system_clk.c),
1504 },
1505};
1506
1507static struct branch_clk gcc_usb_hsic_ahb_clk = {
1508 .cbcr_reg = USB_HSIC_AHB_CBCR,
1509 .has_sibling = 1,
1510 .base = &virt_bases[GCC_BASE],
1511 .c = {
1512 .dbg_name = "gcc_usb_hsic_ahb_clk",
1513 .ops = &clk_ops_branch,
1514 CLK_INIT(gcc_usb_hsic_ahb_clk.c),
1515 },
1516};
1517
1518static struct branch_clk gcc_usb_hsic_clk = {
1519 .cbcr_reg = USB_HSIC_CBCR,
1520 .has_sibling = 0,
1521 .bcr_reg = USB_HS_HSIC_BCR,
1522 .base = &virt_bases[GCC_BASE],
1523 .c = {
1524 .dbg_name = "gcc_usb_hsic_clk",
1525 .parent = &usb_hsic_clk_src.c,
1526 .ops = &clk_ops_branch,
1527 CLK_INIT(gcc_usb_hsic_clk.c),
1528 },
1529};
1530
1531static struct branch_clk gcc_usb_hsic_io_cal_clk = {
1532 .cbcr_reg = USB_HSIC_IO_CAL_CBCR,
1533 .has_sibling = 0,
1534 .base = &virt_bases[GCC_BASE],
1535 .c = {
1536 .dbg_name = "gcc_usb_hsic_io_cal_clk",
1537 .parent = &usb_hsic_io_cal_clk_src.c,
1538 .ops = &clk_ops_branch,
1539 CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
1540 },
1541};
1542
1543static struct branch_clk gcc_usb_hsic_system_clk = {
1544 .cbcr_reg = USB_HSIC_SYSTEM_CBCR,
1545 .has_sibling = 0,
1546 .bcr_reg = USB_HS_HSIC_BCR,
1547 .base = &virt_bases[GCC_BASE],
1548 .c = {
1549 .dbg_name = "gcc_usb_hsic_system_clk",
1550 .parent = &usb_hsic_system_clk_src.c,
1551 .ops = &clk_ops_branch,
1552 CLK_INIT(gcc_usb_hsic_system_clk.c),
1553 },
1554};
1555
Patrick Daly54a5c2f2013-10-07 17:36:37 -0700[diff] [blame]1556#ifdef CONFIG_DEBUG_FS
1557struct measure_mux_entry {
1558 struct clk *c;
1559 int base;
1560 u32 debug_mux;
1561};
1562
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1563static struct measure_mux_entry measure_mux_GCC[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1564 { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 },
1565 { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 },
1566 { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 },
1567 { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 },
1568 { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a },
1569 { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b },
1570 { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 },
1571 { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 },
1572 { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 },
1573 { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 },
1574 { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 },
1575 { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 },
1576 { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 },
1577 { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 },
1578 { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 },
1579 { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 },
1580 { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a },
1581 { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b },
1582 { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c },
1583 { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e },
1584 { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 },
1585 { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 },
1586 { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 },
1587 { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 },
1588 { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 },
1589 { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 },
1590 { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 },
1591 { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a },
1592 { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c },
1593 { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d },
1594 { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e },
1595 { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 },
1596 { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 },
1597 { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 },
1598 { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 },
1599 { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 },
1600 { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 },
1601 { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 },
1602 { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 },
1603 { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 },
1604 { &gcc_ce1_clk.c, GCC_BASE, 0x0138 },
1605 { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 },
1606 { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a },
1607 { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 },
Patrick Daly2a4ba832013-07-17 12:52:40 -0700[diff] [blame]1608 { &pnoc_clk.c, GCC_BASE, 0x010},
1609 { &snoc_clk.c, GCC_BASE, 0x000},
1610 { &cnoc_clk.c, GCC_BASE, 0x008},
1611 /*
1612 * measure the gcc_bimc_kpss_axi_clk instead to account for the DDR
1613 * rate being gcc_bimc_clk/2.
1614 */
1615 { &bimc_clk.c, GCC_BASE, 0x155},
1616 { &dummy_clk, N_BASES, 0x0000},
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1617};
Patrick Daly54a5c2f2013-10-07 17:36:37 -0700[diff] [blame]1618#endif /* CONFIG_DEBUG_FS */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1619
1620static struct pll_vote_clk mmpll0_pll = {
1621 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1622 .en_mask = BIT(0),
1623 .status_reg = (void __iomem *)MMPLL0_PLL_STATUS,
1624 .status_mask = BIT(17),
1625 .base = &virt_bases[MMSS_BASE],
1626 .c = {
1627 .rate = 800000000,
1628 .parent = &xo.c,
1629 .dbg_name = "mmpll0_pll",
1630 .ops = &clk_ops_pll_vote,
1631 CLK_INIT(mmpll0_pll.c),
1632 },
1633};
1634
1635static struct pll_vote_clk mmpll1_pll = {
1636 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1637 .en_mask = BIT(1),
1638 .status_reg = (void __iomem *)MMPLL1_PLL_STATUS,
1639 .status_mask = BIT(17),
1640 .base = &virt_bases[MMSS_BASE],
1641 .c = {
1642 .rate = 1000000000,
1643 .parent = &xo.c,
1644 .dbg_name = "mmpll1_pll",
1645 .ops = &clk_ops_pll_vote,
1646 CLK_INIT(mmpll1_pll.c),
1647 },
1648};
1649
1650static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = {
1651 F_MMSS( 19200000, xo, 1, 0, 0),
1652 F_MMSS( 37500000, gpll0, 16, 0, 0),
1653 F_MMSS( 50000000, gpll0, 12, 0, 0),
1654 F_MMSS( 75000000, gpll0, 8, 0, 0),
1655 F_MMSS( 100000000, gpll0, 6, 0, 0),
1656 F_MMSS( 150000000, gpll0, 4, 0, 0),
1657 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
pfang948c93e2013-03-20 17:04:18 -0700[diff] [blame]1658 F_MMSS( 266666666, mmpll0_pll, 3, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1659 F_END
1660};
1661
1662static struct rcg_clk axi_clk_src = {
1663 .cmd_rcgr_reg = AXI_CMD_RCGR,
1664 .set_rate = set_rate_hid,
1665 .freq_tbl = ftbl_mmss_mmssnoc_axi_clk,
1666 .current_freq = &rcg_dummy_freq,
1667 .base = &virt_bases[MMSS_BASE],
1668 .c = {
1669 .dbg_name = "axi_clk_src",
1670 .ops = &clk_ops_rcg,
1671 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1672 266670000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1673 CLK_INIT(axi_clk_src.c),
1674 },
1675};
1676
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1677static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = {
1678 F_MMSS( 100000000, gpll0, 6, 0, 0),
1679 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1680 F_END
1681};
1682
1683static struct rcg_clk csi0_clk_src = {
1684 .cmd_rcgr_reg = CSI0_CMD_RCGR,
1685 .set_rate = set_rate_hid,
1686 .freq_tbl = ftbl_camss_csi0_1_clk,
1687 .current_freq = &rcg_dummy_freq,
1688 .base = &virt_bases[MMSS_BASE],
1689 .c = {
1690 .dbg_name = "csi0_clk_src",
1691 .ops = &clk_ops_rcg,
1692 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1693 CLK_INIT(csi0_clk_src.c),
1694 },
1695};
1696
1697static struct rcg_clk csi1_clk_src = {
1698 .cmd_rcgr_reg = CSI1_CMD_RCGR,
1699 .set_rate = set_rate_hid,
1700 .freq_tbl = ftbl_camss_csi0_1_clk,
1701 .current_freq = &rcg_dummy_freq,
1702 .base = &virt_bases[MMSS_BASE],
1703 .c = {
1704 .dbg_name = "csi1_clk_src",
1705 .ops = &clk_ops_rcg,
1706 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1707 CLK_INIT(csi1_clk_src.c),
1708 },
1709};
1710
1711static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = {
1712 F_MMSS( 37500000, gpll0, 16, 0, 0),
1713 F_MMSS( 50000000, gpll0, 12, 0, 0),
1714 F_MMSS( 60000000, gpll0, 10, 0, 0),
1715 F_MMSS( 80000000, gpll0, 7.5, 0, 0),
1716 F_MMSS( 100000000, gpll0, 6, 0, 0),
1717 F_MMSS( 109090000, gpll0, 5.5, 0, 0),
1718 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1719 F_MMSS( 150000000, gpll0, 4, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1720 F_MMSS( 200000000, gpll0, 3, 0, 0),
1721 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1722 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1723 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1724 F_MMSS( 400000000, mmpll0_pll, 2, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1725 F_END
1726};
1727
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1728static unsigned long camss_vfe_vfe0_fmax_v2[VDD_DIG_NUM] = {
1729 150000000, 320000000, 400000000,
1730};
1731
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1732static struct rcg_clk vfe0_clk_src = {
1733 .cmd_rcgr_reg = VFE0_CMD_RCGR,
1734 .set_rate = set_rate_hid,
1735 .freq_tbl = ftbl_camss_vfe_vfe0_clk,
1736 .current_freq = &rcg_dummy_freq,
1737 .base = &virt_bases[MMSS_BASE],
1738 .c = {
1739 .dbg_name = "vfe0_clk_src",
1740 .ops = &clk_ops_rcg,
1741 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1742 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1743 CLK_INIT(vfe0_clk_src.c),
1744 },
1745};
1746
1747static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = {
1748 F_MMSS( 37500000, gpll0, 16, 0, 0),
1749 F_MMSS( 60000000, gpll0, 10, 0, 0),
1750 F_MMSS( 75000000, gpll0, 8, 0, 0),
1751 F_MMSS( 92310000, gpll0, 6.5, 0, 0),
1752 F_MMSS( 100000000, gpll0, 6, 0, 0),
1753 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
1754 F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0),
1755 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1756 F_END
1757};
1758
1759static struct rcg_clk mdp_clk_src = {
1760 .cmd_rcgr_reg = MDP_CMD_RCGR,
1761 .set_rate = set_rate_hid,
1762 .freq_tbl = ftbl_mdss_mdp_clk,
1763 .current_freq = &rcg_dummy_freq,
1764 .base = &virt_bases[MMSS_BASE],
1765 .c = {
1766 .dbg_name = "mdp_clk_src",
1767 .ops = &clk_ops_rcg,
1768 VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1769 200000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1770 CLK_INIT(mdp_clk_src.c),
1771 },
1772};
1773
1774static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = {
1775 F_MMSS( 75000000, gpll0, 8, 0, 0),
1776 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1777 F_MMSS( 200000000, gpll0, 3, 0, 0),
1778 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1779 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1780 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1781 F_END
1782};
1783
1784static struct rcg_clk jpeg0_clk_src = {
1785 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1786 .set_rate = set_rate_hid,
1787 .freq_tbl = ftbl_camss_jpeg_jpeg0_clk,
1788 .current_freq = &rcg_dummy_freq,
1789 .base = &virt_bases[MMSS_BASE],
1790 .c = {
1791 .dbg_name = "jpeg0_clk_src",
1792 .ops = &clk_ops_rcg,
1793 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1794 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1795 CLK_INIT(jpeg0_clk_src.c),
1796 },
1797};
1798
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1799struct clk_ops clk_ops_pixel_clock;
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1800
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1801static long round_rate_pixel(struct clk *clk, unsigned long rate)
1802{
1803 int frac_num[] = {3, 2, 4, 1};
1804 int frac_den[] = {8, 9, 9, 1};
1805 int delta = 100000;
1806 int i;
1807
1808 for (i = 0; i < ARRAY_SIZE(frac_num); i++) {
1809 unsigned long request = (rate * frac_den[i]) / frac_num[i];
1810 unsigned long src_rate;
1811
1812 src_rate = clk_round_rate(clk->parent, request);
1813 if ((src_rate < (request - delta)) ||
1814 (src_rate > (request + delta)))
1815 continue;
1816
1817 return (src_rate * frac_num[i]) / frac_den[i];
1818 }
1819
1820 return -EINVAL;
1821}
1822
1823
1824static int set_rate_pixel(struct clk *clk, unsigned long rate)
1825{
1826 struct rcg_clk *rcg = to_rcg_clk(clk);
1827 struct clk_freq_tbl *pixel_freq = rcg->current_freq;
1828 int frac_num[] = {3, 2, 4, 1};
1829 int frac_den[] = {8, 9, 9, 1};
1830 int delta = 100000;
1831 int i, rc;
1832
1833 for (i = 0; i < ARRAY_SIZE(frac_num); i++) {
1834 unsigned long request = (rate * frac_den[i]) / frac_num[i];
1835 unsigned long src_rate;
1836
1837 src_rate = clk_round_rate(clk->parent, request);
1838 if ((src_rate < (request - delta)) ||
1839 (src_rate > (request + delta)))
1840 continue;
1841
1842 rc = clk_set_rate(clk->parent, src_rate);
1843 if (rc)
1844 return rc;
1845
1846 pixel_freq->div_src_val &= ~BM(4, 0);
1847 if (frac_den[i] == frac_num[i]) {
1848 pixel_freq->m_val = 0;
1849 pixel_freq->n_val = 0;
1850 } else {
1851 pixel_freq->m_val = frac_num[i];
1852 pixel_freq->n_val = ~(frac_den[i] - frac_num[i]);
1853 pixel_freq->d_val = ~frac_den[i];
1854 }
1855 set_rate_mnd(rcg, pixel_freq);
1856 return 0;
1857 }
1858 return -EINVAL;
1859}
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1860
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1861static struct clk_freq_tbl pixel_freq_tbl[] = {
1862 {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1863 .src_clk = &pixel_clk_src_8226.c,
1864 .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val)
1865 | BVAL(4, 0, 0),
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1866 },
1867 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1868};
1869
1870static struct rcg_clk pclk0_clk_src = {
1871 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1872 .current_freq = pixel_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1873 .base = &virt_bases[MMSS_BASE],
1874 .c = {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1875 .parent = &pixel_clk_src_8226.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1876 .dbg_name = "pclk0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1877 .ops = &clk_ops_pixel,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1878 VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000),
1879 CLK_INIT(pclk0_clk_src.c),
1880 },
1881};
1882
1883static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = {
1884 F_MMSS( 66700000, gpll0, 9, 0, 0),
1885 F_MMSS( 100000000, gpll0, 6, 0, 0),
1886 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]1887 F_MMSS( 160000000, mmpll0_pll, 5, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1888 F_END
1889};
1890
1891static struct rcg_clk vcodec0_clk_src = {
1892 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
1893 .set_rate = set_rate_mnd,
1894 .freq_tbl = ftbl_venus0_vcodec0_clk,
1895 .current_freq = &rcg_dummy_freq,
1896 .base = &virt_bases[MMSS_BASE],
1897 .c = {
1898 .dbg_name = "vcodec0_clk_src",
1899 .ops = &clk_ops_rcg_mnd,
Patrick Daly59c74322013-06-07 12:00:42 -0700[diff] [blame]1900 VDD_DIG_FMAX_MAP3(LOW, 66700000, NOMINAL, 133330000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1901 160000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1902 CLK_INIT(vcodec0_clk_src.c),
1903 },
1904};
1905
1906static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = {
1907 F_MMSS( 19200000, xo, 1, 0, 0),
1908 F_END
1909};
1910
1911static struct rcg_clk cci_clk_src = {
1912 .cmd_rcgr_reg = CCI_CMD_RCGR,
1913 .set_rate = set_rate_mnd,
1914 .freq_tbl = ftbl_camss_cci_cci_clk,
1915 .current_freq = &rcg_dummy_freq,
1916 .base = &virt_bases[MMSS_BASE],
1917 .c = {
1918 .dbg_name = "cci_clk_src",
1919 .ops = &clk_ops_rcg_mnd,
1920 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
1921 CLK_INIT(cci_clk_src.c),
1922 },
1923};
1924
1925static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = {
1926 F_MMSS( 10000, xo, 16, 1, 120),
1927 F_MMSS( 24000, xo, 16, 1, 50),
1928 F_MMSS( 6000000, gpll0, 10, 1, 10),
1929 F_MMSS( 12000000, gpll0, 10, 1, 5),
1930 F_MMSS( 13000000, gpll0, 4, 13, 150),
1931 F_MMSS( 24000000, gpll0, 5, 1, 5),
1932 F_END
1933};
1934
1935static struct rcg_clk mmss_gp0_clk_src = {
1936 .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR,
1937 .set_rate = set_rate_mnd,
1938 .freq_tbl = ftbl_camss_gp0_1_clk,
1939 .current_freq = &rcg_dummy_freq,
1940 .base = &virt_bases[MMSS_BASE],
1941 .c = {
1942 .dbg_name = "mmss_gp0_clk_src",
1943 .ops = &clk_ops_rcg_mnd,
1944 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1945 CLK_INIT(mmss_gp0_clk_src.c),
1946 },
1947};
1948
1949static struct rcg_clk mmss_gp1_clk_src = {
1950 .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR,
1951 .set_rate = set_rate_mnd,
1952 .freq_tbl = ftbl_camss_gp0_1_clk,
1953 .current_freq = &rcg_dummy_freq,
1954 .base = &virt_bases[MMSS_BASE],
1955 .c = {
1956 .dbg_name = "mmss_gp1_clk_src",
1957 .ops = &clk_ops_rcg_mnd,
1958 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1959 CLK_INIT(mmss_gp1_clk_src.c),
1960 },
1961};
1962
1963static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = {
Patrick Daly42d2b7a2013-03-07 17:12:33 -0800[diff] [blame]1964 F_MMSS( 19200000, xo, 1, 0, 0),
1965 F_MMSS( 24000000, gpll0, 5, 1, 5),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1966 F_MMSS( 66670000, gpll0, 9, 0, 0),
1967 F_END
1968};
1969
1970static struct rcg_clk mclk0_clk_src = {
1971 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1972 .set_rate = set_rate_mnd,
1973 .freq_tbl = ftbl_camss_mclk0_1_clk,
1974 .current_freq = &rcg_dummy_freq,
1975 .base = &virt_bases[MMSS_BASE],
1976 .c = {
1977 .dbg_name = "mclk0_clk_src",
1978 .ops = &clk_ops_rcg_mnd,
1979 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1980 CLK_INIT(mclk0_clk_src.c),
1981 },
1982};
1983
1984static struct rcg_clk mclk1_clk_src = {
1985 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1986 .set_rate = set_rate_mnd,
1987 .freq_tbl = ftbl_camss_mclk0_1_clk,
1988 .current_freq = &rcg_dummy_freq,
1989 .base = &virt_bases[MMSS_BASE],
1990 .c = {
1991 .dbg_name = "mclk1_clk_src",
1992 .ops = &clk_ops_rcg_mnd,
1993 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1994 CLK_INIT(mclk1_clk_src.c),
1995 },
1996};
1997
1998static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = {
1999 F_MMSS( 100000000, gpll0, 6, 0, 0),
2000 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
2001 F_END
2002};
2003
2004static struct rcg_clk csi0phytimer_clk_src = {
2005 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
2006 .set_rate = set_rate_hid,
2007 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
2008 .current_freq = &rcg_dummy_freq,
2009 .base = &virt_bases[MMSS_BASE],
2010 .c = {
2011 .dbg_name = "csi0phytimer_clk_src",
2012 .ops = &clk_ops_rcg,
2013 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
2014 CLK_INIT(csi0phytimer_clk_src.c),
2015 },
2016};
2017
2018static struct rcg_clk csi1phytimer_clk_src = {
2019 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
2020 .set_rate = set_rate_hid,
2021 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
2022 .current_freq = &rcg_dummy_freq,
2023 .base = &virt_bases[MMSS_BASE],
2024 .c = {
2025 .dbg_name = "csi1phytimer_clk_src",
2026 .ops = &clk_ops_rcg,
2027 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
2028 CLK_INIT(csi1phytimer_clk_src.c),
2029 },
2030};
2031
2032static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = {
2033 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2034 F_MMSS( 150000000, gpll0, 4, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2035 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
2036 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2037 F_MMSS( 400000000, mmpll0_pll, 2, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2038 F_END
2039};
2040
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2041static unsigned long camss_vfe_cpp_fmax_v2[VDD_DIG_NUM] = {
2042 150000000, 320000000, 400000000,
2043};
2044
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2045static struct rcg_clk cpp_clk_src = {
2046 .cmd_rcgr_reg = CPP_CMD_RCGR,
2047 .set_rate = set_rate_hid,
2048 .freq_tbl = ftbl_camss_vfe_cpp_clk,
2049 .current_freq = &rcg_dummy_freq,
2050 .base = &virt_bases[MMSS_BASE],
2051 .c = {
2052 .dbg_name = "cpp_clk_src",
2053 .ops = &clk_ops_rcg,
2054 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]2055 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2056 CLK_INIT(cpp_clk_src.c),
2057 },
2058};
2059
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2060static struct clk_freq_tbl byte_freq_tbl[] = {
2061 {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]2062 .src_clk = &byte_clk_src_8226.c,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2063 .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
2064 },
2065 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2066};
2067
2068static struct rcg_clk byte0_clk_src = {
2069 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2070 .current_freq = byte_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2071 .base = &virt_bases[MMSS_BASE],
2072 .c = {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]2073 .parent = &byte_clk_src_8226.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2074 .dbg_name = "byte0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2075 .ops = &clk_ops_byte,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2076 VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000),
2077 CLK_INIT(byte0_clk_src.c),
2078 },
2079};
2080
2081static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = {
2082 F_MDSS( 19200000, xo, 1, 0, 0),
2083 F_END
2084};
2085
2086static struct rcg_clk esc0_clk_src = {
2087 .cmd_rcgr_reg = ESC0_CMD_RCGR,
2088 .set_rate = set_rate_hid,
2089 .freq_tbl = ftbl_mdss_esc0_clk,
2090 .current_freq = &rcg_dummy_freq,
2091 .base = &virt_bases[MMSS_BASE],
2092 .c = {
2093 .dbg_name = "esc0_clk_src",
2094 .ops = &clk_ops_rcg,
2095 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2096 CLK_INIT(esc0_clk_src.c),
2097 },
2098};
2099
2100static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
2101 F_MDSS( 19200000, xo, 1, 0, 0),
2102 F_END
2103};
2104
2105static struct rcg_clk vsync_clk_src = {
2106 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
2107 .set_rate = set_rate_hid,
2108 .freq_tbl = ftbl_mdss_vsync_clk,
2109 .current_freq = &rcg_dummy_freq,
2110 .base = &virt_bases[MMSS_BASE],
2111 .c = {
2112 .dbg_name = "vsync_clk_src",
2113 .ops = &clk_ops_rcg,
2114 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2115 CLK_INIT(vsync_clk_src.c),
2116 },
2117};
2118
2119static struct branch_clk camss_cci_cci_ahb_clk = {
2120 .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
2121 .has_sibling = 1,
2122 .base = &virt_bases[MMSS_BASE],
2123 .c = {
2124 .dbg_name = "camss_cci_cci_ahb_clk",
2125 .ops = &clk_ops_branch,
2126 CLK_INIT(camss_cci_cci_ahb_clk.c),
2127 },
2128};
2129
2130static struct branch_clk camss_cci_cci_clk = {
2131 .cbcr_reg = CAMSS_CCI_CCI_CBCR,
2132 .has_sibling = 0,
2133 .base = &virt_bases[MMSS_BASE],
2134 .c = {
2135 .dbg_name = "camss_cci_cci_clk",
2136 .parent = &cci_clk_src.c,
2137 .ops = &clk_ops_branch,
2138 CLK_INIT(camss_cci_cci_clk.c),
2139 },
2140};
2141
2142static struct branch_clk camss_csi0_ahb_clk = {
2143 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2144 .has_sibling = 1,
2145 .base = &virt_bases[MMSS_BASE],
2146 .c = {
2147 .dbg_name = "camss_csi0_ahb_clk",
2148 .ops = &clk_ops_branch,
2149 CLK_INIT(camss_csi0_ahb_clk.c),
2150 },
2151};
2152
2153static struct branch_clk camss_csi0_clk = {
2154 .cbcr_reg = CAMSS_CSI0_CBCR,
2155 .has_sibling = 1,
2156 .base = &virt_bases[MMSS_BASE],
2157 .c = {
2158 .dbg_name = "camss_csi0_clk",
2159 .parent = &csi0_clk_src.c,
2160 .ops = &clk_ops_branch,
2161 CLK_INIT(camss_csi0_clk.c),
2162 },
2163};
2164
2165static struct branch_clk camss_csi0phy_clk = {
2166 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2167 .has_sibling = 1,
2168 .base = &virt_bases[MMSS_BASE],
2169 .c = {
2170 .dbg_name = "camss_csi0phy_clk",
2171 .parent = &csi0_clk_src.c,
2172 .ops = &clk_ops_branch,
2173 CLK_INIT(camss_csi0phy_clk.c),
2174 },
2175};
2176
2177static struct branch_clk camss_csi0pix_clk = {
2178 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2179 .has_sibling = 1,
2180 .base = &virt_bases[MMSS_BASE],
2181 .c = {
2182 .dbg_name = "camss_csi0pix_clk",
2183 .parent = &csi0_clk_src.c,
2184 .ops = &clk_ops_branch,
2185 CLK_INIT(camss_csi0pix_clk.c),
2186 },
2187};
2188
2189static struct branch_clk camss_csi0rdi_clk = {
2190 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2191 .has_sibling = 1,
2192 .base = &virt_bases[MMSS_BASE],
2193 .c = {
2194 .dbg_name = "camss_csi0rdi_clk",
2195 .parent = &csi0_clk_src.c,
2196 .ops = &clk_ops_branch,
2197 CLK_INIT(camss_csi0rdi_clk.c),
2198 },
2199};
2200
2201static struct branch_clk camss_csi1_ahb_clk = {
2202 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2203 .has_sibling = 1,
2204 .base = &virt_bases[MMSS_BASE],
2205 .c = {
2206 .dbg_name = "camss_csi1_ahb_clk",
2207 .ops = &clk_ops_branch,
2208 CLK_INIT(camss_csi1_ahb_clk.c),
2209 },
2210};
2211
2212static struct branch_clk camss_csi1_clk = {
2213 .cbcr_reg = CAMSS_CSI1_CBCR,
2214 .has_sibling = 1,
2215 .base = &virt_bases[MMSS_BASE],
2216 .c = {
2217 .dbg_name = "camss_csi1_clk",
2218 .parent = &csi1_clk_src.c,
2219 .ops = &clk_ops_branch,
2220 CLK_INIT(camss_csi1_clk.c),
2221 },
2222};
2223
2224static struct branch_clk camss_csi1phy_clk = {
2225 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2226 .has_sibling = 1,
2227 .base = &virt_bases[MMSS_BASE],
2228 .c = {
2229 .dbg_name = "camss_csi1phy_clk",
2230 .parent = &csi1_clk_src.c,
2231 .ops = &clk_ops_branch,
2232 CLK_INIT(camss_csi1phy_clk.c),
2233 },
2234};
2235
2236static struct branch_clk camss_csi1pix_clk = {
2237 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2238 .has_sibling = 1,
2239 .base = &virt_bases[MMSS_BASE],
2240 .c = {
2241 .dbg_name = "camss_csi1pix_clk",
2242 .parent = &csi1_clk_src.c,
2243 .ops = &clk_ops_branch,
2244 CLK_INIT(camss_csi1pix_clk.c),
2245 },
2246};
2247
2248static struct branch_clk camss_csi1rdi_clk = {
2249 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2250 .has_sibling = 1,
2251 .base = &virt_bases[MMSS_BASE],
2252 .c = {
2253 .dbg_name = "camss_csi1rdi_clk",
2254 .parent = &csi1_clk_src.c,
2255 .ops = &clk_ops_branch,
2256 CLK_INIT(camss_csi1rdi_clk.c),
2257 },
2258};
2259
2260static struct branch_clk camss_csi_vfe0_clk = {
2261 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2262 .bcr_reg = CAMSS_CSI_VFE0_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2263 .has_sibling = 1,
2264 .base = &virt_bases[MMSS_BASE],
2265 .c = {
2266 .dbg_name = "camss_csi_vfe0_clk",
2267 .parent = &vfe0_clk_src.c,
2268 .ops = &clk_ops_branch,
2269 CLK_INIT(camss_csi_vfe0_clk.c),
2270 },
2271};
2272
2273static struct branch_clk camss_gp0_clk = {
2274 .cbcr_reg = CAMSS_GP0_CBCR,
2275 .has_sibling = 0,
2276 .base = &virt_bases[MMSS_BASE],
2277 .c = {
2278 .dbg_name = "camss_gp0_clk",
2279 .parent = &mmss_gp0_clk_src.c,
2280 .ops = &clk_ops_branch,
2281 CLK_INIT(camss_gp0_clk.c),
2282 },
2283};
2284
2285static struct branch_clk camss_gp1_clk = {
2286 .cbcr_reg = CAMSS_GP1_CBCR,
2287 .has_sibling = 0,
2288 .base = &virt_bases[MMSS_BASE],
2289 .c = {
2290 .dbg_name = "camss_gp1_clk",
2291 .parent = &mmss_gp1_clk_src.c,
2292 .ops = &clk_ops_branch,
2293 CLK_INIT(camss_gp1_clk.c),
2294 },
2295};
2296
2297static struct branch_clk camss_ispif_ahb_clk = {
2298 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2299 .has_sibling = 1,
2300 .base = &virt_bases[MMSS_BASE],
2301 .c = {
2302 .dbg_name = "camss_ispif_ahb_clk",
2303 .ops = &clk_ops_branch,
2304 CLK_INIT(camss_ispif_ahb_clk.c),
2305 },
2306};
2307
2308static struct branch_clk camss_jpeg_jpeg0_clk = {
2309 .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2310 .bcr_reg = CAMSS_JPEG_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2311 .has_sibling = 0,
2312 .base = &virt_bases[MMSS_BASE],
2313 .c = {
2314 .dbg_name = "camss_jpeg_jpeg0_clk",
2315 .parent = &jpeg0_clk_src.c,
2316 .ops = &clk_ops_branch,
2317 CLK_INIT(camss_jpeg_jpeg0_clk.c),
2318 },
2319};
2320
2321static struct branch_clk camss_jpeg_jpeg_ahb_clk = {
2322 .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
2323 .has_sibling = 1,
2324 .base = &virt_bases[MMSS_BASE],
2325 .c = {
2326 .dbg_name = "camss_jpeg_jpeg_ahb_clk",
2327 .ops = &clk_ops_branch,
2328 CLK_INIT(camss_jpeg_jpeg_ahb_clk.c),
2329 },
2330};
2331
2332static struct branch_clk camss_jpeg_jpeg_axi_clk = {
2333 .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
2334 .has_sibling = 1,
2335 .base = &virt_bases[MMSS_BASE],
2336 .c = {
2337 .dbg_name = "camss_jpeg_jpeg_axi_clk",
2338 .parent = &axi_clk_src.c,
2339 .ops = &clk_ops_branch,
2340 CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
2341 },
2342};
2343
2344static struct branch_clk camss_mclk0_clk = {
2345 .cbcr_reg = CAMSS_MCLK0_CBCR,
2346 .has_sibling = 0,
2347 .base = &virt_bases[MMSS_BASE],
2348 .c = {
2349 .dbg_name = "camss_mclk0_clk",
2350 .parent = &mclk0_clk_src.c,
2351 .ops = &clk_ops_branch,
2352 CLK_INIT(camss_mclk0_clk.c),
2353 },
2354};
2355
2356static struct branch_clk camss_mclk1_clk = {
2357 .cbcr_reg = CAMSS_MCLK1_CBCR,
2358 .has_sibling = 0,
2359 .base = &virt_bases[MMSS_BASE],
2360 .c = {
2361 .dbg_name = "camss_mclk1_clk",
2362 .parent = &mclk1_clk_src.c,
2363 .ops = &clk_ops_branch,
2364 CLK_INIT(camss_mclk1_clk.c),
2365 },
2366};
2367
2368static struct branch_clk camss_micro_ahb_clk = {
2369 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2370 .has_sibling = 1,
Rajakumar Govindaram4c2482b2013-09-05 19:45:01 -0700[diff] [blame]2371 .bcr_reg = CAMSS_MICRO_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2372 .base = &virt_bases[MMSS_BASE],
2373 .c = {
2374 .dbg_name = "camss_micro_ahb_clk",
2375 .ops = &clk_ops_branch,
2376 CLK_INIT(camss_micro_ahb_clk.c),
2377 },
2378};
2379
2380static struct branch_clk camss_phy0_csi0phytimer_clk = {
2381 .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
2382 .has_sibling = 0,
2383 .base = &virt_bases[MMSS_BASE],
2384 .c = {
2385 .dbg_name = "camss_phy0_csi0phytimer_clk",
2386 .parent = &csi0phytimer_clk_src.c,
2387 .ops = &clk_ops_branch,
2388 CLK_INIT(camss_phy0_csi0phytimer_clk.c),
2389 },
2390};
2391
2392static struct branch_clk camss_phy1_csi1phytimer_clk = {
2393 .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
2394 .has_sibling = 0,
2395 .base = &virt_bases[MMSS_BASE],
2396 .c = {
2397 .dbg_name = "camss_phy1_csi1phytimer_clk",
2398 .parent = &csi1phytimer_clk_src.c,
2399 .ops = &clk_ops_branch,
2400 CLK_INIT(camss_phy1_csi1phytimer_clk.c),
2401 },
2402};
2403
2404static struct branch_clk camss_top_ahb_clk = {
2405 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2406 .has_sibling = 1,
2407 .base = &virt_bases[MMSS_BASE],
2408 .c = {
2409 .dbg_name = "camss_top_ahb_clk",
2410 .ops = &clk_ops_branch,
2411 CLK_INIT(camss_top_ahb_clk.c),
2412 },
2413};
2414
2415static struct branch_clk camss_vfe_cpp_ahb_clk = {
2416 .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
2417 .has_sibling = 1,
2418 .base = &virt_bases[MMSS_BASE],
2419 .c = {
2420 .dbg_name = "camss_vfe_cpp_ahb_clk",
2421 .ops = &clk_ops_branch,
2422 CLK_INIT(camss_vfe_cpp_ahb_clk.c),
2423 },
2424};
2425
2426static struct branch_clk camss_vfe_cpp_clk = {
2427 .cbcr_reg = CAMSS_VFE_CPP_CBCR,
2428 .has_sibling = 0,
2429 .base = &virt_bases[MMSS_BASE],
2430 .c = {
2431 .dbg_name = "camss_vfe_cpp_clk",
2432 .parent = &cpp_clk_src.c,
2433 .ops = &clk_ops_branch,
2434 CLK_INIT(camss_vfe_cpp_clk.c),
2435 },
2436};
2437
2438static struct branch_clk camss_vfe_vfe0_clk = {
2439 .cbcr_reg = CAMSS_VFE_VFE0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2440 .bcr_reg = CAMSS_VFE_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2441 .has_sibling = 1,
2442 .base = &virt_bases[MMSS_BASE],
2443 .c = {
2444 .dbg_name = "camss_vfe_vfe0_clk",
2445 .parent = &vfe0_clk_src.c,
2446 .ops = &clk_ops_branch,
2447 CLK_INIT(camss_vfe_vfe0_clk.c),
2448 },
2449};
2450
2451static struct branch_clk camss_vfe_vfe_ahb_clk = {
2452 .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
2453 .has_sibling = 1,
2454 .base = &virt_bases[MMSS_BASE],
2455 .c = {
2456 .dbg_name = "camss_vfe_vfe_ahb_clk",
2457 .ops = &clk_ops_branch,
2458 CLK_INIT(camss_vfe_vfe_ahb_clk.c),
2459 },
2460};
2461
2462static struct branch_clk camss_vfe_vfe_axi_clk = {
2463 .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
2464 .has_sibling = 1,
2465 .base = &virt_bases[MMSS_BASE],
2466 .c = {
2467 .dbg_name = "camss_vfe_vfe_axi_clk",
2468 .parent = &axi_clk_src.c,
2469 .ops = &clk_ops_branch,
2470 CLK_INIT(camss_vfe_vfe_axi_clk.c),
2471 },
2472};
2473
2474static struct branch_clk mdss_ahb_clk = {
2475 .cbcr_reg = MDSS_AHB_CBCR,
2476 .has_sibling = 1,
2477 .base = &virt_bases[MMSS_BASE],
2478 .c = {
2479 .dbg_name = "mdss_ahb_clk",
2480 .ops = &clk_ops_branch,
2481 CLK_INIT(mdss_ahb_clk.c),
2482 },
2483};
2484
2485static struct branch_clk mdss_axi_clk = {
2486 .cbcr_reg = MDSS_AXI_CBCR,
2487 .has_sibling = 1,
2488 .base = &virt_bases[MMSS_BASE],
2489 .c = {
2490 .dbg_name = "mdss_axi_clk",
2491 .parent = &axi_clk_src.c,
2492 .ops = &clk_ops_branch,
2493 CLK_INIT(mdss_axi_clk.c),
2494 },
2495};
2496
2497static struct branch_clk mdss_byte0_clk = {
2498 .cbcr_reg = MDSS_BYTE0_CBCR,
2499 .has_sibling = 0,
2500 .base = &virt_bases[MMSS_BASE],
2501 .c = {
2502 .dbg_name = "mdss_byte0_clk",
2503 .parent = &byte0_clk_src.c,
2504 .ops = &clk_ops_branch,
2505 CLK_INIT(mdss_byte0_clk.c),
2506 },
2507};
2508
2509static struct branch_clk mdss_esc0_clk = {
2510 .cbcr_reg = MDSS_ESC0_CBCR,
2511 .has_sibling = 0,
2512 .base = &virt_bases[MMSS_BASE],
2513 .c = {
2514 .dbg_name = "mdss_esc0_clk",
2515 .parent = &esc0_clk_src.c,
2516 .ops = &clk_ops_branch,
2517 CLK_INIT(mdss_esc0_clk.c),
2518 },
2519};
2520
2521static struct branch_clk mdss_mdp_clk = {
2522 .cbcr_reg = MDSS_MDP_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2523 .bcr_reg = MDSS_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2524 .has_sibling = 1,
2525 .base = &virt_bases[MMSS_BASE],
2526 .c = {
2527 .dbg_name = "mdss_mdp_clk",
2528 .parent = &mdp_clk_src.c,
2529 .ops = &clk_ops_branch,
2530 CLK_INIT(mdss_mdp_clk.c),
2531 },
2532};
2533
2534static struct branch_clk mdss_mdp_lut_clk = {
2535 .cbcr_reg = MDSS_MDP_LUT_CBCR,
2536 .has_sibling = 1,
2537 .base = &virt_bases[MMSS_BASE],
2538 .c = {
2539 .dbg_name = "mdss_mdp_lut_clk",
2540 .parent = &mdp_clk_src.c,
2541 .ops = &clk_ops_branch,
2542 CLK_INIT(mdss_mdp_lut_clk.c),
2543 },
2544};
2545
2546static struct branch_clk mdss_pclk0_clk = {
2547 .cbcr_reg = MDSS_PCLK0_CBCR,
2548 .has_sibling = 0,
2549 .base = &virt_bases[MMSS_BASE],
2550 .c = {
2551 .dbg_name = "mdss_pclk0_clk",
2552 .parent = &pclk0_clk_src.c,
2553 .ops = &clk_ops_branch,
2554 CLK_INIT(mdss_pclk0_clk.c),
2555 },
2556};
2557
2558static struct branch_clk mdss_vsync_clk = {
2559 .cbcr_reg = MDSS_VSYNC_CBCR,
2560 .has_sibling = 0,
2561 .base = &virt_bases[MMSS_BASE],
2562 .c = {
2563 .dbg_name = "mdss_vsync_clk",
2564 .parent = &vsync_clk_src.c,
2565 .ops = &clk_ops_branch,
2566 CLK_INIT(mdss_vsync_clk.c),
2567 },
2568};
2569
2570static struct branch_clk mmss_misc_ahb_clk = {
2571 .cbcr_reg = MMSS_MISC_AHB_CBCR,
2572 .has_sibling = 1,
2573 .base = &virt_bases[MMSS_BASE],
2574 .c = {
2575 .dbg_name = "mmss_misc_ahb_clk",
2576 .ops = &clk_ops_branch,
2577 CLK_INIT(mmss_misc_ahb_clk.c),
2578 },
2579};
2580
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2581static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
2582 .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
2583 .has_sibling = 1,
2584 .base = &virt_bases[MMSS_BASE],
2585 .c = {
2586 .dbg_name = "mmss_mmssnoc_bto_ahb_clk",
2587 .ops = &clk_ops_branch,
2588 CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c),
2589 },
2590};
2591
2592static struct branch_clk mmss_mmssnoc_axi_clk = {
2593 .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
2594 .has_sibling = 1,
2595 .base = &virt_bases[MMSS_BASE],
2596 .c = {
2597 .dbg_name = "mmss_mmssnoc_axi_clk",
2598 .parent = &axi_clk_src.c,
2599 .ops = &clk_ops_branch,
2600 CLK_INIT(mmss_mmssnoc_axi_clk.c),
2601 },
2602};
2603
2604static struct branch_clk mmss_s0_axi_clk = {
2605 .cbcr_reg = MMSS_S0_AXI_CBCR,
2606 .has_sibling = 0,
2607 .max_div = 0,
2608 .base = &virt_bases[MMSS_BASE],
2609 .c = {
2610 .dbg_name = "mmss_s0_axi_clk",
2611 .parent = &axi_clk_src.c,
2612 .ops = &clk_ops_branch,
2613 CLK_INIT(mmss_s0_axi_clk.c),
2614 .depends = &mmss_mmssnoc_axi_clk.c,
2615 },
2616};
2617
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2618static struct branch_clk oxili_gfx3d_clk = {
2619 .cbcr_reg = OXILI_GFX3D_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2620 .bcr_reg = OXILICX_BCR,
Patrick Daly295173b2013-03-11 13:35:40 -0700[diff] [blame]2621 .has_sibling = 0,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2622 .max_div = 0,
2623 .base = &virt_bases[MMSS_BASE],
2624 .c = {
2625 .dbg_name = "oxili_gfx3d_clk",
2626 .parent = &gfx3d_clk_src.c,
2627 .ops = &clk_ops_branch,
2628 CLK_INIT(oxili_gfx3d_clk.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2629 },
2630};
2631
2632static struct branch_clk oxilicx_ahb_clk = {
2633 .cbcr_reg = OXILICX_AHB_CBCR,
2634 .has_sibling = 1,
2635 .base = &virt_bases[MMSS_BASE],
2636 .c = {
2637 .dbg_name = "oxilicx_ahb_clk",
2638 .ops = &clk_ops_branch,
2639 CLK_INIT(oxilicx_ahb_clk.c),
2640 },
2641};
2642
2643static struct branch_clk oxilicx_axi_clk = {
2644 .cbcr_reg = OXILICX_AXI_CBCR,
2645 .has_sibling = 1,
2646 .base = &virt_bases[MMSS_BASE],
2647 .c = {
2648 .dbg_name = "oxilicx_axi_clk",
2649 .parent = &axi_clk_src.c,
2650 .ops = &clk_ops_branch,
2651 CLK_INIT(oxilicx_axi_clk.c),
2652 },
2653};
2654
2655static struct branch_clk venus0_ahb_clk = {
2656 .cbcr_reg = VENUS0_AHB_CBCR,
2657 .has_sibling = 1,
2658 .base = &virt_bases[MMSS_BASE],
2659 .c = {
2660 .dbg_name = "venus0_ahb_clk",
2661 .ops = &clk_ops_branch,
2662 CLK_INIT(venus0_ahb_clk.c),
2663 },
2664};
2665
2666static struct branch_clk venus0_axi_clk = {
2667 .cbcr_reg = VENUS0_AXI_CBCR,
2668 .has_sibling = 1,
2669 .base = &virt_bases[MMSS_BASE],
2670 .c = {
2671 .dbg_name = "venus0_axi_clk",
2672 .parent = &axi_clk_src.c,
2673 .ops = &clk_ops_branch,
2674 CLK_INIT(venus0_axi_clk.c),
2675 },
2676};
2677
2678static struct branch_clk venus0_vcodec0_clk = {
2679 .cbcr_reg = VENUS0_VCODEC0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2680 .bcr_reg = VENUS0_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2681 .has_sibling = 0,
2682 .base = &virt_bases[MMSS_BASE],
2683 .c = {
2684 .dbg_name = "venus0_vcodec0_clk",
2685 .parent = &vcodec0_clk_src.c,
2686 .ops = &clk_ops_branch,
2687 CLK_INIT(venus0_vcodec0_clk.c),
2688 },
2689};
2690
Patrick Daly54a5c2f2013-10-07 17:36:37 -0700[diff] [blame]2691#ifdef CONFIG_DEBUG_FS
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2692static struct measure_mux_entry measure_mux_MMSS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2693 { &mmss_mmssnoc_bto_ahb_clk.c, MMSS_BASE, 0x0002 },
2694 { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 },
2695 { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 },
2696 { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2697 { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b },
2698 { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c },
2699 { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d },
2700 { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e },
2701 { &venus0_axi_clk.c, MMSS_BASE, 0x000f },
2702 { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 },
2703 { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 },
2704 { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 },
2705 { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 },
2706 { &mdss_vsync_clk.c, MMSS_BASE, 0x001c },
2707 { &mdss_byte0_clk.c, MMSS_BASE, 0x001e },
2708 { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 },
2709 { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 },
2710 { &mdss_axi_clk.c, MMSS_BASE, 0x0024 },
2711 { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 },
2712 { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 },
2713 { &camss_gp0_clk.c, MMSS_BASE, 0x0027 },
2714 { &camss_gp1_clk.c, MMSS_BASE, 0x0028 },
2715 { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 },
2716 { &camss_mclk1_clk.c, MMSS_BASE, 0x002a },
2717 { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d },
2718 { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e },
2719 { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f },
2720 { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 },
2721 { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 },
2722 { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 },
2723 { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 },
2724 { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 },
2725 { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a },
2726 { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b },
2727 { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c },
2728 { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d },
2729 { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f },
2730 { &camss_csi0_clk.c, MMSS_BASE, 0x0041 },
2731 { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 },
2732 { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 },
2733 { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 },
2734 { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 },
2735 { &camss_csi1_clk.c, MMSS_BASE, 0x0046 },
2736 { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 },
2737 { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 },
2738 { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 },
2739 { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a },
2740 { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 },
Patrick Daly2a4ba832013-07-17 12:52:40 -0700[diff] [blame]2741 { &mmssnoc_ahb_clk.c, MMSS_BASE, 0x0001 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2742 {&dummy_clk, N_BASES, 0x0000},
2743};
Patrick Daly54a5c2f2013-10-07 17:36:37 -0700[diff] [blame]2744#endif /* CONFIG_DEBUG_FS */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2745
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2746static struct branch_clk q6ss_ahb_lfabif_clk = {
2747 .cbcr_reg = Q6SS_AHB_LFABIF_CBCR,
2748 .has_sibling = 1,
2749 .base = &virt_bases[LPASS_BASE],
2750 .c = {
2751 .dbg_name = "q6ss_ahb_lfabif_clk",
2752 .ops = &clk_ops_branch,
2753 CLK_INIT(q6ss_ahb_lfabif_clk.c),
2754 },
2755};
2756
2757static struct branch_clk q6ss_ahbm_clk = {
2758 .cbcr_reg = Q6SS_AHBM_CBCR,
2759 .has_sibling = 1,
2760 .base = &virt_bases[LPASS_BASE],
2761 .c = {
2762 .dbg_name = "q6ss_ahbm_clk",
2763 .ops = &clk_ops_branch,
2764 CLK_INIT(q6ss_ahbm_clk.c),
2765 },
2766};
2767
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2768static struct branch_clk q6ss_xo_clk = {
2769 .cbcr_reg = Q6SS_XO_CBCR,
2770 .has_sibling = 1,
2771 .bcr_reg = Q6SS_BCR,
2772 .base = &virt_bases[LPASS_BASE],
2773 .c = {
2774 .dbg_name = "q6ss_xo_clk",
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2775 .ops = &clk_ops_branch,
2776 CLK_INIT(q6ss_xo_clk.c),
2777 },
2778};
2779
Patrick Daly54a5c2f2013-10-07 17:36:37 -0700[diff] [blame]2780#ifdef CONFIG_DEBUG_FS
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2781static struct measure_mux_entry measure_mux_LPASS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2782 { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d },
2783 { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2784 { &q6ss_xo_clk.c, LPASS_BASE, 0x002b },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2785 {&dummy_clk, N_BASES, 0x0000},
2786};
Patrick Daly54a5c2f2013-10-07 17:36:37 -0700[diff] [blame]2787#endif /* CONFIG_DEBUG_FS */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2788
2789
2790static DEFINE_CLK_MEASURE(apc0_m_clk);
2791static DEFINE_CLK_MEASURE(apc1_m_clk);
2792static DEFINE_CLK_MEASURE(apc2_m_clk);
2793static DEFINE_CLK_MEASURE(apc3_m_clk);
2794static DEFINE_CLK_MEASURE(l2_m_clk);
2795
Patrick Daly54a5c2f2013-10-07 17:36:37 -0700[diff] [blame]2796#ifdef CONFIG_DEBUG_FS
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2797static struct measure_mux_entry measure_mux_APSS[] = {
2798 {&apc0_m_clk, APCS_BASE, 0x00010},
2799 {&apc1_m_clk, APCS_BASE, 0x00114},
2800 {&apc2_m_clk, APCS_BASE, 0x00220},
2801 {&apc3_m_clk, APCS_BASE, 0x00324},
2802 {&l2_m_clk, APCS_BASE, 0x01000},
2803 {&dummy_clk, N_BASES, 0x0000}
2804};
Patrick Daly54a5c2f2013-10-07 17:36:37 -0700[diff] [blame]2805#endif /* CONFIG_DEBUG_FS */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2806
2807#define APCS_SH_PLL_MODE (0x000)
2808#define APCS_SH_PLL_L_VAL (0x004)
2809#define APCS_SH_PLL_M_VAL (0x008)
2810#define APCS_SH_PLL_N_VAL (0x00C)
2811#define APCS_SH_PLL_USER_CTL (0x010)
2812#define APCS_SH_PLL_CONFIG_CTL (0x014)
2813#define APCS_SH_PLL_STATUS (0x01C)
2814
2815enum vdd_sr2_pll_levels {
2816 VDD_SR2_PLL_OFF,
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2817 VDD_SR2_PLL_SVS,
2818 VDD_SR2_PLL_NOM,
2819 VDD_SR2_PLL_TUR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2820 VDD_SR2_PLL_NUM
2821};
2822
Junjie Wubb5a79e2013-05-15 13:12:39 -0700[diff] [blame]2823static int vdd_sr2_levels[] = {
2824 0, RPM_REGULATOR_CORNER_NONE, /* VDD_SR2_PLL_OFF */
2825 1800000, RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_SR2_PLL_SVS */
2826 1800000, RPM_REGULATOR_CORNER_NORMAL, /* VDD_SR2_PLL_NOM */
2827 1800000, RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_SR2_PLL_TUR */
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]2828};
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2829
Patrick Daly653c0b52013-04-16 17:18:28 -0700[diff] [blame]2830static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
2831 vdd_sr2_levels, NULL);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2832
2833static struct pll_freq_tbl apcs_pll_freq[] = {
Patrick Daly83806032013-03-25 15:18:24 -0700[diff] [blame]2834 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2835 F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0),
2836 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyf363c252013-03-21 12:08:37 -0700[diff] [blame]2837 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2838 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Daly66e32aa2013-05-30 15:11:52 -0700[diff] [blame]2839 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
2840 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
2841 F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Daly5a66c082013-08-02 10:58:56 -0700[diff] [blame]2842 F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
2843 F_APCS_PLL(1593600000, 83, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2844 PLL_F_END
2845};
2846
2847static struct pll_clk a7sspll = {
2848 .mode_reg = (void __iomem *)APCS_SH_PLL_MODE,
2849 .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL,
2850 .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL,
2851 .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL,
2852 .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL,
2853 .status_reg = (void __iomem *)APCS_SH_PLL_STATUS,
2854 .freq_tbl = apcs_pll_freq,
2855 .masks = {
2856 .vco_mask = BM(29, 28),
2857 .pre_div_mask = BIT(12),
2858 .post_div_mask = BM(9, 8),
2859 .mn_en_mask = BIT(24),
2860 .main_output_mask = BIT(0),
2861 },
2862 .base = &virt_bases[APCS_PLL_BASE],
2863 .c = {
Patrick Daly9bdc8a52013-03-21 19:12:40 -0700[diff] [blame]2864 .parent = &xo_a_clk.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2865 .dbg_name = "a7sspll",
2866 .ops = &clk_ops_sr2_pll,
2867 .vdd_class = &vdd_sr2_pll,
2868 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2869 [VDD_SR2_PLL_SVS] = 1000000000,
2870 [VDD_SR2_PLL_NOM] = 1900000000,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2871 },
2872 .num_fmax = VDD_SR2_PLL_NUM,
2873 CLK_INIT(a7sspll.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2874 },
2875};
2876
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2877static struct clk_freq_tbl ftbl_kpss_ahb_clk[] = {
2878 F_GCC(19200000, xo_a_clk, 0, 0, 0),
2879 F_GCC(37500000, gpll0, 16, 0, 0),
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2880 F_END
2881};
2882
2883static struct rcg_clk kpss_ahb_clk_src = {
2884 .cmd_rcgr_reg = KPSS_AHB_CMD_RCGR,
2885 .set_rate = set_rate_hid,
2886 .freq_tbl = ftbl_kpss_ahb_clk,
2887 .current_freq = &rcg_dummy_freq,
2888 .base = &virt_bases[GCC_BASE],
2889 .c = {
2890 .dbg_name = "kpss_ahb_clk_src",
2891 .ops = &clk_ops_rcg,
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2892 CLK_INIT(kpss_ahb_clk_src.c),
2893 },
2894};
2895
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2896static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
2897static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
2898static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
2899static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
2900static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
2901static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX);
2902
2903static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
2904static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
2905static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX);
2906static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX);
2907static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX);
2908static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
2909static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
2910
2911static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX);
2912
Patrick Daly4aef16c2013-04-17 15:44:12 -0700[diff] [blame]2913static DEFINE_CLK_VOTER(qseecom_ce1_clk_src, &ce1_clk_src.c, 100000000);
2914static DEFINE_CLK_VOTER(scm_ce1_clk_src, &ce1_clk_src.c, 100000000);
Hariprasad Dhalinarasimhae898bb12013-06-07 14:12:14 -0700[diff] [blame]2915static DEFINE_CLK_VOTER(gud_ce1_clk_src, &ce1_clk_src.c, 100000000);
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]2916
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]2917static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, &xo.c);
2918static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, &xo.c);
2919static DEFINE_CLK_BRANCH_VOTER(cxo_pil_mss_clk, &xo.c);
2920static DEFINE_CLK_BRANCH_VOTER(cxo_wlan_clk, &xo.c);
2921static DEFINE_CLK_BRANCH_VOTER(cxo_pil_pronto_clk, &xo.c);
Vikram Mulukutlaae4ae302013-04-24 12:00:28 -0700[diff] [blame]2922static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, &xo.c);
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]2923
2924
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2925#ifdef CONFIG_DEBUG_FS
2926static int measure_clk_set_parent(struct clk *c, struct clk *parent)
2927{
2928 struct measure_clk *clk = to_measure_clk(c);
2929 unsigned long flags;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2930 u32 regval, clk_sel, found = 0;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2931 int i;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2932 static const struct measure_mux_entry *array[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2933 measure_mux_GCC,
2934 measure_mux_MMSS,
2935 measure_mux_LPASS,
2936 measure_mux_APSS,
2937 NULL
2938 };
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2939 const struct measure_mux_entry *mux = array[0];
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2940
2941 if (!parent)
2942 return -EINVAL;
2943
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2944 for (i = 0; array[i] && !found; i++) {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2945 for (mux = array[i]; mux->c != &dummy_clk; mux++)
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2946 if (mux->c == parent) {
2947 found = 1;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2948 break;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2949 }
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2950 }
2951
2952 if (mux->c == &dummy_clk)
2953 return -EINVAL;
2954
2955 spin_lock_irqsave(&local_clock_reg_lock, flags);
2956 /*
2957 * Program the test vector, measurement period (sample_ticks)
2958 * and scaling multiplier.
2959 */
2960 clk->sample_ticks = 0x10000;
2961 clk->multiplier = 1;
2962
2963 switch (mux->base) {
2964
2965 case GCC_BASE:
2966 writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2967 clk_sel = mux->debug_mux;
2968 break;
2969
2970 case MMSS_BASE:
2971 writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2972 clk_sel = 0x02C;
2973 regval = BVAL(11, 0, mux->debug_mux);
2974 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2975
2976 /* Activate debug clock output */
2977 regval |= BIT(16);
2978 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2979 break;
2980
2981 case LPASS_BASE:
2982 writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2983 clk_sel = 0x161;
2984 regval = BVAL(11, 0, mux->debug_mux);
2985 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2986
2987 /* Activate debug clock output */
2988 regval |= BIT(20);
2989 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2990 break;
2991
2992 case APCS_BASE:
2993 clk->multiplier = 4;
2994 clk_sel = 362;
2995 regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG));
2996 regval &= ~0xC0037335;
2997 /* configure a divider of 4 */
2998 regval = BVAL(31, 30, 0x3) | mux->debug_mux;
2999 writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG));
3000 break;
3001
3002 default:
3003 return -EINVAL;
3004 }
3005
3006 /* Set debug mux clock index */
3007 regval = BVAL(8, 0, clk_sel);
3008 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
3009
3010 /* Activate debug clock output */
3011 regval |= BIT(16);
3012 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
3013
3014 /* Make sure test vector is set before starting measurements. */
3015 mb();
3016 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3017
3018 return 0;
3019}
3020
3021/* Sample clock for 'ticks' reference clock ticks. */
3022static u32 run_measurement(unsigned ticks)
3023{
3024 /* Stop counters and set the XO4 counter start value. */
3025 writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
3026
3027 /* Wait for timer to become ready. */
3028 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3029 BIT(25)) != 0)
3030 cpu_relax();
3031
3032 /* Run measurement and wait for completion. */
3033 writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
3034 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3035 BIT(25)) == 0)
3036 cpu_relax();
3037
3038 /* Return measured ticks. */
3039 return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3040 BM(24, 0);
3041}
3042
3043/*
3044 * Perform a hardware rate measurement for a given clock.
3045 * FOR DEBUG USE ONLY: Measurements take ~15 ms!
3046 */
3047static unsigned long measure_clk_get_rate(struct clk *c)
3048{
3049 unsigned long flags;
3050 u32 gcc_xo4_reg_backup;
3051 u64 raw_count_short, raw_count_full;
3052 struct measure_clk *clk = to_measure_clk(c);
3053 unsigned ret;
3054
3055 ret = clk_prepare_enable(&xo.c);
3056 if (ret) {
3057 pr_warn("CXO clock failed to enable. Can't measure\n");
3058 return 0;
3059 }
3060
3061 spin_lock_irqsave(&local_clock_reg_lock, flags);
3062
3063 /* Enable CXO/4 and RINGOSC branch. */
3064 gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3065 writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3066
3067 /*
3068 * The ring oscillator counter will not reset if the measured clock
3069 * is not running. To detect this, run a short measurement before
3070 * the full measurement. If the raw results of the two are the same
3071 * then the clock must be off.
3072 */
3073
3074 /* Run a short measurement. (~1 ms) */
3075 raw_count_short = run_measurement(0x1000);
3076 /* Run a full measurement. (~14 ms) */
3077 raw_count_full = run_measurement(clk->sample_ticks);
3078
3079 writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3080
3081 /* Return 0 if the clock is off. */
3082 if (raw_count_full == raw_count_short) {
3083 ret = 0;
3084 } else {
3085 /* Compute rate in Hz. */
3086 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
3087 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
3088 ret = (raw_count_full * clk->multiplier);
3089 }
3090
Patrick Dalye095edb2013-05-23 14:13:09 -0700[diff] [blame]3091 /* Set pin to gcc_debug_clock, enable output mode, disable input mode */
3092 writel_relaxed(0x51200, GCC_REG_BASE(PLLTEST_PAD_CFG));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3093 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3094
3095 clk_disable_unprepare(&xo.c);
3096
3097 return ret;
3098}
3099
3100#else /* !CONFIG_DEBUG_FS */
3101static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
3102{
3103 return -EINVAL;
3104}
3105
3106static unsigned long measure_clk_get_rate(struct clk *clk)
3107{
3108 return 0;
3109}
3110#endif /* CONFIG_DEBUG_FS */
3111
3112static struct clk_ops clk_ops_measure = {
3113 .set_parent = measure_clk_set_parent,
3114 .get_rate = measure_clk_get_rate,
3115};
3116
3117static struct measure_clk measure_clk = {
3118 .c = {
3119 .dbg_name = "measure_clk",
3120 .ops = &clk_ops_measure,
3121 CLK_INIT(measure_clk.c),
3122 },
3123 .multiplier = 1,
3124};
3125
3126static struct clk_lookup msm_clocks_8226[] = {
3127 /* Debug Clocks */
3128 CLK_LOOKUP("measure", measure_clk.c, "debug"),
3129 CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""),
3130 CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""),
3131 CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""),
3132 CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""),
3133 CLK_LOOKUP("l2_m_clk", l2_m_clk, ""),
3134
Vikram Mulukutlaae4ae302013-04-24 12:00:28 -0700[diff] [blame]3135 /* LPM Resources */
3136 CLK_LOOKUP("xo", cxo_lpm_clk.c, "fc4281d0.qcom,mpm"),
3137
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3138 /* PIL-LPASS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3139 CLK_LOOKUP("xo", cxo_pil_lpass_clk.c, "fe200000.qcom,lpass"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3140 CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"),
3141 CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"),
3142 CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"),
3143 CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"),
3144
3145 /* PIL-MODEM */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3146 CLK_LOOKUP("xo", cxo_pil_mss_clk.c, "fc880000.qcom,mss"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3147 CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"),
3148 CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
3149 CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
Madan Mohan Koyyalamudi497b7002013-06-19 17:32:39 -0700[diff] [blame]3150 /* NFC */
3151 CLK_LOOKUP("ref_clk", cxo_d1_a_pin.c, "2-000e"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3152 /* PIL-PRONTO */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3153 CLK_LOOKUP("xo", cxo_pil_pronto_clk.c, "fb21b000.qcom,pronto"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3154
3155 /* PIL-VENUS */
3156 CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"),
3157 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"),
3158 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3159 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"),
3160 CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3161
3162 /* ACPUCLOCK */
3163 CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
3164 CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
3165 CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]3166 CLK_LOOKUP("kpss_ahb", kpss_ahb_clk_src.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3167
3168 /* WCNSS CLOCKS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3169 CLK_LOOKUP("xo", cxo_wlan_clk.c, "fb000000.qcom,wcnss-wlan"),
Vikram Mulukutla7e5b3112013-04-15 16:32:40 -0700[diff] [blame]3170 CLK_LOOKUP("rf_clk", cxo_a1.c, "fb000000.qcom,wcnss-wlan"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3171
3172 /* BUS DRIVER */
3173 CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"),
3174 CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"),
3175 CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"),
3176 CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"),
3177 CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"),
3178 CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"),
3179 CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"),
3180 CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"),
3181 CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""),
3182 CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"),
3183 CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"),
3184 CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3185 CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3186
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3187 /* CoreSight clocks */
3188 CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"),
3189 CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"),
3190 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"),
3191 CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"),
3192 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"),
3193 CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"),
3194 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"),
3195 CLK_LOOKUP("core_clk", qdss_clk.c, "fc345000.funnel"),
3196 CLK_LOOKUP("core_clk", qdss_clk.c, "fc364000.funnel"),
3197 CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"),
3198 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.etm"),
3199 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.etm"),
3200 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.etm"),
3201 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3202 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.jtagmm"),
3203 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.jtagmm"),
3204 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.jtagmm"),
3205 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3206 CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"),
3207 CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"),
3208 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"),
3209 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"),
3210 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"),
3211 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"),
3212 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"),
3213 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"),
3214 CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"),
3215 CLK_LOOKUP("core_clk", qdss_clk.c, "fc340000.cti"),
3216 CLK_LOOKUP("core_clk", qdss_clk.c, "fc341000.cti"),
3217 CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"),
3218 CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"),
3219 CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"),
Aparna Dasca6aa3a2013-04-02 16:25:27 -0700[diff] [blame]3220 CLK_LOOKUP("core_clk", qdss_clk.c, "fd828018.hwevent"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3221
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3222 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
3223 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
3224 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"),
3225 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"),
3226 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"),
3227 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"),
3228 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"),
3229 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc345000.funnel"),
3230 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc364000.funnel"),
3231 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"),
3232 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.etm"),
3233 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.etm"),
3234 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.etm"),
3235 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.etm"),
Aparna Das664239c2013-05-03 20:13:50 -0700[diff] [blame]3236 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.jtagmm"),
3237 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.jtagmm"),
3238 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.jtagmm"),
3239 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3240 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"),
3241 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"),
3242 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"),
3243 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"),
3244 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"),
3245 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"),
3246 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"),
3247 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"),
3248 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"),
3249 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc340000.cti"),
3250 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc341000.cti"),
3251 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"),
3252 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"),
3253 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"),
Aparna Dasca6aa3a2013-04-02 16:25:27 -0700[diff] [blame]3254 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fd828018.hwevent"),
3255
3256 CLK_LOOKUP("core_mmss_clk", mmss_misc_ahb_clk.c, "fd828018.hwevent"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3257
3258 /* HSUSB-OTG Clocks */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3259 CLK_LOOKUP("xo", cxo_otg_clk.c, "f9a55000.usb"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3260 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
3261 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
Mayank Ranaf14cb8d2013-07-24 17:09:17 +0530[diff] [blame]3262 CLK_LOOKUP("sleep_clk", gcc_usb2a_phy_sleep_clk.c, "f9a55000.usb"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3263
3264 /* SPS CLOCKS */
3265 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"),
3266 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"),
3267 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
3268 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
3269
3270 /* I2C Clocks */
3271 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"),
3272 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"),
3273
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]3274 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"),
3275 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, "f9927000.i2c"),
3276
Madan Mohan Koyyalamudi497b7002013-06-19 17:32:39 -0700[diff] [blame]3277 /* I2C Clocks nfc */
3278 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9925000.i2c"),
3279 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, "f9925000.i2c"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3280 /* lsuart-v14 Clocks */
3281 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"),
3282 CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),
3283
3284 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"),
3285 CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"),
3286
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]3287 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"),
3288 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3289
3290 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"),
3291 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"),
3292 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3293 CLK_LOOKUP("core_clk_src", qseecom_ce1_clk_src.c, "qseecom"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3294
Hariprasad Dhalinarasimhae898bb12013-06-07 14:12:14 -0700[diff] [blame]3295 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "mcd"),
3296 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "mcd"),
3297 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "mcd"),
3298 CLK_LOOKUP("core_clk_src", gud_ce1_clk_src.c, "mcd"),
3299
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3300 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "scm"),
3301 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "scm"),
3302 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "scm"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3303 CLK_LOOKUP("core_clk_src", scm_ce1_clk_src.c, "scm"),
3304
3305 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, ""),
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3306
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3307 /* SDCC */
3308 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"),
3309 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"),
3310 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
3311 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
3312
3313 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
3314 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
3315 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
3316 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
3317
3318 CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
3319 CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
3320
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3321 CLK_LOOKUP("bus_clk", pnoc_clk.c, ""),
3322 CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""),
3323 CLK_LOOKUP("bus_clk", snoc_clk.c, ""),
3324 CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""),
3325 CLK_LOOKUP("bus_clk", cnoc_clk.c, ""),
3326 CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""),
3327 CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""),
3328 CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""),
3329 CLK_LOOKUP("bus_clk", bimc_clk.c, ""),
3330 CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""),
3331 CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
3332
3333 CLK_LOOKUP("gpll0", gpll0.c, ""),
3334 CLK_LOOKUP("gpll1", gpll1.c, ""),
3335 CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""),
3336 CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3337
3338 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
3339 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
3340 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3341 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
3342 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
3343 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
3344 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
3345 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
3346 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
3347 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
3348 CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
3349 CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""),
3350 CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""),
3351 CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""),
3352 CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
3353 CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
3354 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""),
3355 CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""),
3356 CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
3357 CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
3358
3359 CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"),
3360 CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"),
3361 CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"),
3362 CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"),
3363 CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"),
3364 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"),
3365 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"),
3366 CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"),
3367
3368 /* Multimedia clocks */
3369 CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"),
3370 CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"),
3371 CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
Aravind Venkateswaran6b6d9c42013-05-06 16:10:03 -0700[diff] [blame]3372 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd922800.qcom,mdss_dsi"),
3373 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd922800.qcom,mdss_dsi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3374
Adrian Salido-Morenof840a032013-03-01 23:10:03 -0800[diff] [blame]3375 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"),
3376 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"),
3377 CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"),
3378 CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "fd900000.qcom,mdss_mdp"),
3379 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"),
3380 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3381
3382 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"),
3383 CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"),
3384
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]3385 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fd8c1024.qcom,gdsc"),
3386 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd8c2304.qcom,gdsc"),
3387 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd8c2304.qcom,gdsc"),
3388 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fd8c35a4.qcom,gdsc"),
3389 CLK_LOOKUP("core_clk", camss_vfe_vfe0_clk.c, "fd8c36a4.qcom,gdsc"),
3390 CLK_LOOKUP("csi_clk", camss_csi_vfe0_clk.c, "fd8c36a4.qcom,gdsc"),
3391 CLK_LOOKUP("cpp_clk", camss_vfe_cpp_clk.c, "fd8c36a4.qcom,gdsc"),
3392 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fd8c4034.qcom,gdsc"),
3393
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3394 /* MM sensor clocks */
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3395 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6f.qcom,camera"),
Ju He0dd84ad2013-06-18 09:59:13 +0800[diff] [blame]3396 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3397 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6d.qcom,camera"),
Liu Su1e4c0ba2013-06-08 23:30:01 +0800[diff] [blame]3398 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6a.qcom,camera"),
feim0aaee482013-06-08 15:26:20 +0800[diff] [blame]3399 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6c.qcom,camera"),
Ju Hebbe039e2013-07-29 04:45:26 -0700[diff] [blame]3400 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "20.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3401 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6f.qcom,camera"),
Ju He0dd84ad2013-06-18 09:59:13 +0800[diff] [blame]3402 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3403 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6d.qcom,camera"),
Liu Su1e4c0ba2013-06-08 23:30:01 +0800[diff] [blame]3404 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6a.qcom,camera"),
feim0aaee482013-06-08 15:26:20 +0800[diff] [blame]3405 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6c.qcom,camera"),
Ju Hebbe039e2013-07-29 04:45:26 -0700[diff] [blame]3406 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "20.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3407
Ju Hef80f40b2013-07-18 17:06:32 +0800[diff] [blame]3408 /* eeprom clocks */
3409 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6c.qcom,eeprom"),
3410 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6c.qcom,eeprom"),
Wang Wenbinadb94482013-08-07 14:26:09 +0800[diff] [blame]3411 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "18.qcom,eeprom"),
3412 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "18.qcom,eeprom"),
Su Liu56664932013-08-14 10:20:06 +0800[diff] [blame]3413 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6b.qcom,eeprom"),
3414 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6b.qcom,eeprom"),
Ju Hef80f40b2013-07-18 17:06:32 +0800[diff] [blame]3415
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3416 /* CCI clocks */
3417 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3418 "fda0c000.qcom,cci"),
3419 CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c,
3420 "fda0c000.qcom,cci"),
3421 CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"),
3422 CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"),
3423
3424 /* CSIPHY clocks */
3425 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3426 "fda0ac00.qcom,csiphy"),
3427 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3428 "fda0ac00.qcom,csiphy"),
3429 CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c,
3430 "fda0ac00.qcom,csiphy"),
3431 CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c,
3432 "fda0ac00.qcom,csiphy"),
3433 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3434 "fda0b000.qcom,csiphy"),
3435 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3436 "fda0b000.qcom,csiphy"),
3437 CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c,
3438 "fda0b000.qcom,csiphy"),
3439 CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c,
3440 "fda0b000.qcom,csiphy"),
3441
3442 /* CSID clocks */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3443 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3444 "fda08000.qcom,csid"),
3445 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3446 "fda08000.qcom,csid"),
3447 CLK_LOOKUP("csi_ahb_clk", camss_csi0_ahb_clk.c,
3448 "fda08000.qcom,csid"),
3449 CLK_LOOKUP("csi_src_clk", csi0_clk_src.c,
3450 "fda08000.qcom,csid"),
3451 CLK_LOOKUP("csi_phy_clk", camss_csi0phy_clk.c,
3452 "fda08000.qcom,csid"),
3453 CLK_LOOKUP("csi_clk", camss_csi0_clk.c,
3454 "fda08000.qcom,csid"),
3455 CLK_LOOKUP("csi_pix_clk", camss_csi0pix_clk.c,
3456 "fda08000.qcom,csid"),
3457 CLK_LOOKUP("csi_rdi_clk", camss_csi0rdi_clk.c,
3458 "fda08000.qcom,csid"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3459
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3460
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3461 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3462 "fda08400.qcom,csid"),
3463 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3464 "fda08400.qcom,csid"),
3465 CLK_LOOKUP("csi_ahb_clk", camss_csi1_ahb_clk.c,
3466 "fda08400.qcom,csid"),
3467 CLK_LOOKUP("csi_src_clk", csi1_clk_src.c,
3468 "fda08400.qcom,csid"),
3469 CLK_LOOKUP("csi_phy_clk", camss_csi1phy_clk.c,
3470 "fda08400.qcom,csid"),
3471 CLK_LOOKUP("csi_clk", camss_csi1_clk.c,
3472 "fda08400.qcom,csid"),
3473 CLK_LOOKUP("csi_pix_clk", camss_csi1pix_clk.c,
3474 "fda08400.qcom,csid"),
3475 CLK_LOOKUP("csi_rdi_clk", camss_csi1rdi_clk.c,
3476 "fda08400.qcom,csid"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3477
3478 /* ISPIF clocks */
Sreesudhan Ramakrish Ramkumarecdcfce2013-04-17 12:58:26 -0700[diff] [blame]3479 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3480 "fda0a000.qcom,ispif"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3481 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3482 "fda0a000.qcom,ispif"),
3483 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3484 "fda0a000.qcom,ispif"),
3485
3486 /* VFE clocks */
3487 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3488 "fda10000.qcom,vfe"),
3489 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"),
3490 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3491 "fda10000.qcom,vfe"),
3492 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3493 "fda10000.qcom,vfe"),
3494 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"),
3495 CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"),
3496
3497 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c,
3498 "fda44000.qcom,iommu"),
3499 CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"),
3500 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"),
3501
3502 /* Jpeg Clocks */
3503 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"),
3504 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3505 "fda1c000.qcom,jpeg"),
3506 CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c,
3507 "fda1c000.qcom,jpeg"),
3508 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3509 "fda1c000.qcom,jpeg"),
3510
3511 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"),
3512 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3513 "fda64000.qcom,iommu"),
3514 CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c,
3515 "fda64000.qcom,iommu"),
3516
Su Liudb7b2062013-03-14 20:57:15 -0700[diff] [blame]3517 CLK_LOOKUP("micro_iface_clk", camss_micro_ahb_clk.c,
3518 "fda04000.qcom,cpp"),
3519 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3520 "fda04000.qcom,cpp"),
3521 CLK_LOOKUP("cpp_iface_clk", camss_vfe_cpp_ahb_clk.c,
3522 "fda04000.qcom,cpp"),
3523 CLK_LOOKUP("cpp_core_clk", camss_vfe_cpp_clk.c, "fda04000.qcom,cpp"),
3524 CLK_LOOKUP("cpp_bus_clk", camss_vfe_vfe_axi_clk.c, "fda04000.qcom,cpp"),
3525 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda04000.qcom,cpp"),
3526 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3527 "fda04000.qcom,cpp"),
3528 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda04000.qcom,cpp"),
3529
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3530 /* KGSL Clocks */
3531 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"),
3532 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"),
liu zhongc45eb8b2013-02-21 11:50:24 -0800[diff] [blame]3533 CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c,
3534 "fdb00000.qcom,kgsl-3d0"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3535
3536 CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"),
3537 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"),
3538 CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"),
3539
3540 CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3541
3542 /* Venus Clocks */
3543 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"),
3544 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"),
3545 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"),
3546
3547 CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c,
3548 "fdc84000.qcom,iommu"),
3549 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"),
3550 CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"),
Hariprasad Dhalinarasimha92a13222013-03-12 11:59:28 -0700[diff] [blame]3551 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3552 CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""),
3553 CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""),
3554 CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""),
3555
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3556 CLK_LOOKUP("", mmss_mmssnoc_bto_ahb_clk.c, ""),
3557 CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""),
3558 CLK_LOOKUP("", mmss_s0_axi_clk.c, ""),
Bhalchandra Gajared5a4ba72013-03-11 16:15:13 -0700[diff] [blame]3559
3560 /* Audio clocks */
3561 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.224"),
3562 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.4106"),
3563 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16384"),
3564 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16386"),
3565 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16390"),
3566 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16391"),
3567
Hariprasad Dhalinarasimha1fa54392013-03-21 15:57:51 -0700[diff] [blame]3568 /* Add QCEDEV clocks */
3569 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd400000.qcom,qcedev"),
3570 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd400000.qcom,qcedev"),
3571 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd400000.qcom,qcedev"),
3572 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd400000.qcom,qcedev"),
3573
3574 /* Add QCRYPTO clocks */
3575 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd404000.qcom,qcrypto"),
3576 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd404000.qcom,qcrypto"),
3577 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd404000.qcom,qcrypto"),
3578 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd404000.qcom,qcrypto"),
3579
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]3580 /* DSI PLL clocks */
3581 CLK_LOOKUP("", dsi_vco_clk_8226.c, ""),
3582 CLK_LOOKUP("", analog_postdiv_clk_8226.c, ""),
3583 CLK_LOOKUP("", indirect_path_div2_clk_8226.c, ""),
3584 CLK_LOOKUP("", pixel_clk_src_8226.c, ""),
3585 CLK_LOOKUP("", byte_mux_8226.c, ""),
3586 CLK_LOOKUP("", byte_clk_src_8226.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3587};
3588
3589static struct clk_lookup msm_clocks_8226_rumi[] = {
3590 CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3591 CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3592 CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
3593 CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
3594 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
3595 CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
3596 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
3597 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
3598 CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
3599 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
3600};
3601
3602struct clock_init_data msm8226_rumi_clock_init_data __initdata = {
3603 .table = msm_clocks_8226_rumi,
3604 .size = ARRAY_SIZE(msm_clocks_8226_rumi),
3605};
3606
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3607static void __init reg_init(void)
3608{
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3609 u32 regval;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3610
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3611 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
3612 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3613 regval |= BIT(0);
3614 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3615
3616 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3617 * No clocks need to be enabled during sleep.
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3618 */
3619 writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3620}
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3621
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3622static void __init msm8226_clock_post_init(void)
3623{
Vikram Mulukutla441db7a2013-03-15 13:56:33 -0700[diff] [blame]3624 /*
3625 * Hold an active set vote for CXO; this is because CXO is expected
3626 * to remain on whenever CPUs aren't power collapsed.
3627 */
3628 clk_prepare_enable(&xo_a_clk.c);
3629
Patrick Daly856c2fe2013-07-18 12:59:40 -0700[diff] [blame]3630 /*
3631 * Handoff will override the prepare enable count as well as the rate
3632 * Set them again.
3633 */
3634 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
3635 clk_prepare_enable(&mmssnoc_ahb_a_clk.c);
3636
Patrick Dalyfd3df102013-05-28 18:08:22 -0700[diff] [blame]3637 /* Set an initial rate (fmax at nominal) on the MMSSNOC AXI clock */
3638 clk_set_rate(&axi_clk_src.c, 200000000);
3639
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3640 /* Set rates for single-rate clocks. */
3641 clk_set_rate(&usb_hs_system_clk_src.c,
3642 usb_hs_system_clk_src.freq_tbl[0].freq_hz);
3643 clk_set_rate(&usb_hsic_clk_src.c,
3644 usb_hsic_clk_src.freq_tbl[0].freq_hz);
3645 clk_set_rate(&usb_hsic_io_cal_clk_src.c,
3646 usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz);
3647 clk_set_rate(&usb_hsic_system_clk_src.c,
3648 usb_hsic_system_clk_src.freq_tbl[0].freq_hz);
3649 clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz);
3650 clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz);
3651 clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz);
3652 clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz);
3653 clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz);
3654 clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz);
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]3655
3656 clk_set_rate(&kpss_ahb_clk_src.c, 19200000);
3657 clk_prepare_enable(&kpss_ahb_clk_src.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3658}
3659
3660#define GCC_CC_PHYS 0xFC400000
3661#define GCC_CC_SIZE SZ_16K
3662
3663#define MMSS_CC_PHYS 0xFD8C0000
3664#define MMSS_CC_SIZE SZ_256K
3665
3666#define LPASS_CC_PHYS 0xFE000000
3667#define LPASS_CC_SIZE SZ_256K
3668
3669#define APCS_KPSS_SH_PLL_PHYS 0xF9016000
3670#define APCS_KPSS_SH_PLL_SIZE SZ_64
3671
3672#define APCS_KPSS_GLB_PHYS 0xF9011000
3673#define APCS_KPSS_GLB_SIZE SZ_4K
3674
3675
3676static void __init msm8226_clock_pre_init(void)
3677{
3678 virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE);
3679 if (!virt_bases[GCC_BASE])
3680 panic("clock-8226: Unable to ioremap GCC memory!");
3681
3682 virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE);
3683 if (!virt_bases[MMSS_BASE])
3684 panic("clock-8226: Unable to ioremap MMSS_CC memory!");
3685
3686 virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE);
3687 if (!virt_bases[LPASS_BASE])
3688 panic("clock-8226: Unable to ioremap LPASS_CC memory!");
3689
3690 virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS,
3691 APCS_KPSS_GLB_SIZE);
3692 if (!virt_bases[APCS_BASE])
3693 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3694
3695 virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS,
3696 APCS_KPSS_SH_PLL_SIZE);
3697 if (!virt_bases[APCS_PLL_BASE])
3698 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3699
3700 clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
3701
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3702 vdd_dig.regulator[0] = regulator_get(NULL, "vdd_dig");
3703 if (IS_ERR(vdd_dig.regulator[0]))
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3704 panic("clock-8226: Unable to get the vdd_dig regulator!");
3705
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3706 vdd_sr2_pll.regulator[0] = regulator_get(NULL, "vdd_sr2_pll");
3707 if (IS_ERR(vdd_sr2_pll.regulator[0]))
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3708 panic("clock-8226: Unable to get the sr2_pll regulator!");
3709
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]3710 vdd_sr2_pll.regulator[1] = regulator_get(NULL, "vdd_sr2_dig");
3711 if (IS_ERR(vdd_sr2_pll.regulator[1]))
3712 panic("clock-8226: Unable to get the vdd_sr2_dig regulator!");
3713
Patrick Daly856c2fe2013-07-18 12:59:40 -0700[diff] [blame]3714
3715 enable_rpm_scaling();
3716
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3717 /*
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3718 * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB
3719 * source. Sleep set vote is 0.
3720 * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to
3721 * access mmss clock controller registers.
3722 */
3723 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
Patrick Daly856c2fe2013-07-18 12:59:40 -0700[diff] [blame]3724 clk_prepare_enable(&mmssnoc_ahb_a_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3725
3726 reg_init();
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3727
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]3728 /* v2 specific changes */
3729 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
3730 cpp_clk_src.c.fmax = camss_vfe_cpp_fmax_v2;
3731 vfe0_clk_src.c.fmax = camss_vfe_vfe0_fmax_v2;
3732 }
3733
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]3734 clk_ops_pixel_clock = clk_ops_pixel;
3735 clk_ops_pixel_clock.set_rate = set_rate_pixel;
3736 clk_ops_pixel_clock.round_rate = round_rate_pixel;
3737
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3738 /*
3739 * MDSS needs the ahb clock and needs to init before we register the
3740 * lookup table.
3741 */
3742 mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3743}
3744
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3745struct clock_init_data msm8226_clock_init_data __initdata = {
3746 .table = msm_clocks_8226,
3747 .size = ARRAY_SIZE(msm_clocks_8226),
3748 .pre_init = msm8226_clock_pre_init,
3749 .post_init = msm8226_clock_post_init,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3750};