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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2003-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * Copyright 2003 Benjamin Herrenschmidt
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 *
Jeff Garzik953d1132005-08-26 19:46:24 -040030 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
46#include <linux/libata.h>
Alexander Beregalov1737ef72009-01-29 02:30:56 +030047#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "sata_sil"
Robert Hancockc7e324f2008-12-24 19:06:06 -060050#define DRV_VERSION "2.4"
51
52#define SIL_DMA_BOUNDARY 0x7fffffffUL
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090055 SIL_MMIO_BAR = 5,
56
Tejun Heoe653a1e2006-03-05 16:03:52 +090057 /*
58 * host flags
59 */
Tejun Heo201ce852006-06-26 21:23:52 +090060 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
Tejun Heoe4e10e32006-02-25 13:52:30 +090061 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
Tejun Heoe4deec62005-08-23 07:27:25 +090062 SIL_FLAG_MOD15WRITE = (1 << 30),
Tejun Heo20888d82006-05-31 18:27:53 +090063
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +030064 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA,
Tejun Heoe4deec62005-08-23 07:27:25 +090065
Tejun Heoe653a1e2006-03-05 16:03:52 +090066 /*
67 * Controller IDs
68 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 sil_3112 = 0,
Tejun Heo201ce852006-06-26 21:23:52 +090070 sil_3112_no_sata_irq = 1,
71 sil_3512 = 2,
72 sil_3114 = 3,
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
Tejun Heoe653a1e2006-03-05 16:03:52 +090074 /*
75 * Register offsets
76 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070077 SIL_SYSCFG = 0x48,
Tejun Heoe653a1e2006-03-05 16:03:52 +090078
79 /*
80 * Register bits
81 */
82 /* SYSCFG */
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 SIL_MASK_IDE0_INT = (1 << 22),
84 SIL_MASK_IDE1_INT = (1 << 23),
85 SIL_MASK_IDE2_INT = (1 << 24),
86 SIL_MASK_IDE3_INT = (1 << 25),
87 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
88 SIL_MASK_4PORT = SIL_MASK_2PORT |
89 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
90
Tejun Heoe653a1e2006-03-05 16:03:52 +090091 /* BMDMA/BMDMA2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070092 SIL_INTR_STEERING = (1 << 1),
Tejun Heoe653a1e2006-03-05 16:03:52 +090093
Tejun Heo20888d82006-05-31 18:27:53 +090094 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
95 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
96 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
97 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
98 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
99 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
100 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
101 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
102 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
103 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
104
105 /* SIEN */
106 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
107
Tejun Heoe653a1e2006-03-05 16:03:52 +0900108 /*
109 * Others
110 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 SIL_QUIRK_MOD15WRITE = (1 << 0),
112 SIL_QUIRK_UDMA5MAX = (1 << 1),
113};
114
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400115static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700116#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900117static int sil_pci_device_resume(struct pci_dev *pdev);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700118#endif
Alancd0d3bb2007-03-02 00:56:15 +0000119static void sil_dev_config(struct ata_device *dev);
Tejun Heo82ef04f2008-07-31 17:02:40 +0900120static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
121static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Tejun Heo02607312007-08-06 18:36:23 +0900122static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
Robert Hancockc7e324f2008-12-24 19:06:06 -0600123static void sil_qc_prep(struct ata_queued_cmd *qc);
124static void sil_bmdma_setup(struct ata_queued_cmd *qc);
125static void sil_bmdma_start(struct ata_queued_cmd *qc);
126static void sil_bmdma_stop(struct ata_queued_cmd *qc);
Tejun Heof6aae272006-05-15 20:58:27 +0900127static void sil_freeze(struct ata_port *ap);
128static void sil_thaw(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129
Jeff Garzik374b1872005-08-30 05:42:52 -0400130
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500131static const struct pci_device_id sil_pci_tbl[] = {
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400132 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
133 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
134 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
135 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
136 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
137 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
138 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
139
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 { } /* terminate list */
141};
142
143
144/* TODO firmware versions should be added - eric */
145static const struct sil_drivelist {
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400146 const char *product;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 unsigned int quirk;
148} sil_blacklist [] = {
149 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
150 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
151 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
152 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
154 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
156 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
157 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
158 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
159 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
160 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
161 { }
162};
163
164static struct pci_driver sil_pci_driver = {
165 .name = DRV_NAME,
166 .id_table = sil_pci_tbl,
167 .probe = sil_init_one,
168 .remove = ata_pci_remove_one,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700169#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900170 .suspend = ata_pci_device_suspend,
171 .resume = sil_pci_device_resume,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700172#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173};
174
Jeff Garzik193515d2005-11-07 00:59:37 -0500175static struct scsi_host_template sil_sht = {
Robert Hancockc7e324f2008-12-24 19:06:06 -0600176 ATA_BASE_SHT(DRV_NAME),
177 /** These controllers support Large Block Transfer which allows
178 transfer chunks up to 2GB and which cross 64KB boundaries,
179 therefore the DMA limits are more relaxed than standard ATA SFF. */
180 .dma_boundary = SIL_DMA_BOUNDARY,
181 .sg_tablesize = ATA_MAX_PRD
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182};
183
Tejun Heo029cfd62008-03-25 12:22:49 +0900184static struct ata_port_operations sil_ops = {
Robert Hancock31f80112009-04-13 22:57:28 -0600185 .inherits = &ata_bmdma32_port_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186 .dev_config = sil_dev_config,
Alan Cox9d2c7c72007-03-08 23:09:12 +0000187 .set_mode = sil_set_mode,
Robert Hancockc7e324f2008-12-24 19:06:06 -0600188 .bmdma_setup = sil_bmdma_setup,
189 .bmdma_start = sil_bmdma_start,
190 .bmdma_stop = sil_bmdma_stop,
191 .qc_prep = sil_qc_prep,
Tejun Heof6aae272006-05-15 20:58:27 +0900192 .freeze = sil_freeze,
193 .thaw = sil_thaw,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 .scr_read = sil_scr_read,
195 .scr_write = sil_scr_write,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196};
197
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100198static const struct ata_port_info sil_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 /* sil_3112 */
200 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400201 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100202 .pio_mask = ATA_PIO4,
203 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400204 .udma_mask = ATA_UDMA5,
Tejun Heoe4deec62005-08-23 07:27:25 +0900205 .port_ops = &sil_ops,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900206 },
Tejun Heo201ce852006-06-26 21:23:52 +0900207 /* sil_3112_no_sata_irq */
208 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400209 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
Tejun Heo201ce852006-06-26 21:23:52 +0900210 SIL_FLAG_NO_SATA_IRQ,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100211 .pio_mask = ATA_PIO4,
212 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400213 .udma_mask = ATA_UDMA5,
Tejun Heo201ce852006-06-26 21:23:52 +0900214 .port_ops = &sil_ops,
215 },
Tejun Heo0ee304d2006-02-25 13:52:30 +0900216 /* sil_3512 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400218 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100219 .pio_mask = ATA_PIO4,
220 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400221 .udma_mask = ATA_UDMA5,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900222 .port_ops = &sil_ops,
223 },
224 /* sil_3114 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400226 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100227 .pio_mask = ATA_PIO4,
228 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400229 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230 .port_ops = &sil_ops,
231 },
232};
233
234/* per-port register offsets */
235/* TODO: we can probably calculate rather than use a table */
236static const struct {
237 unsigned long tf; /* ATA taskfile register block */
238 unsigned long ctl; /* ATA control/altstatus register block */
239 unsigned long bmdma; /* DMA register block */
Tejun Heo20888d82006-05-31 18:27:53 +0900240 unsigned long bmdma2; /* DMA register block #2 */
Tejun Heo48d4ef22006-03-05 16:03:52 +0900241 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 unsigned long scr; /* SATA control register block */
243 unsigned long sien; /* SATA Interrupt Enable register */
244 unsigned long xfer_mode;/* data transfer mode register */
Tejun Heoe4e10e32006-02-25 13:52:30 +0900245 unsigned long sfis_cfg; /* SATA FIS reception config register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246} sil_port[] = {
247 /* port 0 ... */
Jeff Garzik5bcd7a002007-05-26 16:35:42 -0400248 /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
249 { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
250 { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
Tejun Heo20888d82006-05-31 18:27:53 +0900251 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
252 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 /* ... port 3 */
254};
255
256MODULE_AUTHOR("Jeff Garzik");
257MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
258MODULE_LICENSE("GPL");
259MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
260MODULE_VERSION(DRV_VERSION);
261
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400262static int slow_down;
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500263module_param(slow_down, int, 0444);
264MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
265
Jeff Garzik374b1872005-08-30 05:42:52 -0400266
Robert Hancockc7e324f2008-12-24 19:06:06 -0600267static void sil_bmdma_stop(struct ata_queued_cmd *qc)
268{
269 struct ata_port *ap = qc->ap;
270 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
271 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
272
273 /* clear start/stop bit - can safely always write 0 */
274 iowrite8(0, bmdma2);
275
276 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
277 ata_sff_dma_pause(ap);
278}
279
280static void sil_bmdma_setup(struct ata_queued_cmd *qc)
281{
282 struct ata_port *ap = qc->ap;
283 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
284
285 /* load PRD table addr. */
Tejun Heof60d7012010-05-10 21:41:41 +0200286 iowrite32(ap->bmdma_prd_dma, bmdma + ATA_DMA_TABLE_OFS);
Robert Hancockc7e324f2008-12-24 19:06:06 -0600287
288 /* issue r/w command */
289 ap->ops->sff_exec_command(ap, &qc->tf);
290}
291
292static void sil_bmdma_start(struct ata_queued_cmd *qc)
293{
294 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
295 struct ata_port *ap = qc->ap;
296 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
297 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
298 u8 dmactl = ATA_DMA_START;
299
300 /* set transfer direction, start host DMA transaction
301 Note: For Large Block Transfer to work, the DMA must be started
302 using the bmdma2 register. */
303 if (!rw)
304 dmactl |= ATA_DMA_WR;
305 iowrite8(dmactl, bmdma2);
306}
307
308/* The way God intended PCI IDE scatter/gather lists to look and behave... */
309static void sil_fill_sg(struct ata_queued_cmd *qc)
310{
311 struct scatterlist *sg;
312 struct ata_port *ap = qc->ap;
Tejun Heof60d7012010-05-10 21:41:41 +0200313 struct ata_bmdma_prd *prd, *last_prd = NULL;
Robert Hancockc7e324f2008-12-24 19:06:06 -0600314 unsigned int si;
315
Tejun Heof60d7012010-05-10 21:41:41 +0200316 prd = &ap->bmdma_prd[0];
Robert Hancockc7e324f2008-12-24 19:06:06 -0600317 for_each_sg(qc->sg, sg, qc->n_elem, si) {
318 /* Note h/w doesn't support 64-bit, so we unconditionally
319 * truncate dma_addr_t to u32.
320 */
321 u32 addr = (u32) sg_dma_address(sg);
322 u32 sg_len = sg_dma_len(sg);
323
324 prd->addr = cpu_to_le32(addr);
325 prd->flags_len = cpu_to_le32(sg_len);
Pasi Kärkkäinen41137aa2009-02-02 21:47:14 +0200326 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
Robert Hancockc7e324f2008-12-24 19:06:06 -0600327
328 last_prd = prd;
329 prd++;
330 }
331
332 if (likely(last_prd))
333 last_prd->flags_len |= cpu_to_le32(ATA_PRD_EOT);
334}
335
336static void sil_qc_prep(struct ata_queued_cmd *qc)
337{
338 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
339 return;
340
341 sil_fill_sg(qc);
342}
343
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
345{
346 u8 cache_line = 0;
347 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
348 return cache_line;
349}
350
Alan Cox9d2c7c72007-03-08 23:09:12 +0000351/**
352 * sil_set_mode - wrap set_mode functions
Tejun Heo02607312007-08-06 18:36:23 +0900353 * @link: link to set up
Alan Cox9d2c7c72007-03-08 23:09:12 +0000354 * @r_failed: returned device when we fail
355 *
356 * Wrap the libata method for device setup as after the setup we need
357 * to inspect the results and do some configuration work
358 */
359
Tejun Heo02607312007-08-06 18:36:23 +0900360static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361{
Tejun Heo02607312007-08-06 18:36:23 +0900362 struct ata_port *ap = link->ap;
363 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heo0d5ff562007-02-01 15:06:36 +0900364 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
Tejun Heo02607312007-08-06 18:36:23 +0900365 struct ata_device *dev;
Tejun Heof58229f2007-08-06 18:36:23 +0900366 u32 tmp, dev_mode[2] = { };
Alan Cox9d2c7c72007-03-08 23:09:12 +0000367 int rc;
Jeff Garzika617c092007-05-21 20:14:23 -0400368
Tejun Heo02607312007-08-06 18:36:23 +0900369 rc = ata_do_set_mode(link, r_failed);
Alan Cox9d2c7c72007-03-08 23:09:12 +0000370 if (rc)
371 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372
Tejun Heo1eca4362008-11-03 20:03:17 +0900373 ata_for_each_dev(dev, link, ALL) {
Tejun Heoe1211e32006-04-01 01:38:18 +0900374 if (!ata_dev_enabled(dev))
Tejun Heof58229f2007-08-06 18:36:23 +0900375 dev_mode[dev->devno] = 0; /* PIO0/1/2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 else if (dev->flags & ATA_DFLAG_PIO)
Tejun Heof58229f2007-08-06 18:36:23 +0900377 dev_mode[dev->devno] = 1; /* PIO3/4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 else
Tejun Heof58229f2007-08-06 18:36:23 +0900379 dev_mode[dev->devno] = 3; /* UDMA */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 /* value 2 indicates MDMA */
381 }
382
383 tmp = readl(addr);
384 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
385 tmp |= dev_mode[0];
386 tmp |= (dev_mode[1] << 4);
387 writel(tmp, addr);
388 readl(addr); /* flush */
Alan Cox9d2c7c72007-03-08 23:09:12 +0000389 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390}
391
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400392static inline void __iomem *sil_scr_addr(struct ata_port *ap,
393 unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900395 void __iomem *offset = ap->ioaddr.scr_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396
397 switch (sc_reg) {
398 case SCR_STATUS:
399 return offset + 4;
400 case SCR_ERROR:
401 return offset + 8;
402 case SCR_CONTROL:
403 return offset;
404 default:
405 /* do nothing */
406 break;
407 }
408
Randy Dunlap8d9db2d2007-02-16 01:40:06 -0800409 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410}
411
Tejun Heo82ef04f2008-07-31 17:02:40 +0900412static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900414 void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900415
416 if (mmio) {
417 *val = readl(mmio);
418 return 0;
419 }
420 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421}
422
Tejun Heo82ef04f2008-07-31 17:02:40 +0900423static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900425 void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900426
427 if (mmio) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 writel(val, mmio);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900429 return 0;
430 }
431 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432}
433
Tejun Heocbe88fb2006-05-31 18:27:55 +0900434static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
435{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900436 struct ata_eh_info *ehi = &ap->link.eh_info;
437 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900438 u8 status;
439
Tejun Heoe5738902006-05-31 18:28:16 +0900440 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
Jeff Garzikebd16992011-08-18 23:52:36 -0400441 u32 serror = 0xffffffff;
Tejun Heod4c85322006-06-12 18:45:55 +0900442
443 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
444 * controllers continue to assert IRQ as long as
445 * SError bits are pending. Clear SError immediately.
446 */
Tejun Heo82ef04f2008-07-31 17:02:40 +0900447 sil_scr_read(&ap->link, SCR_ERROR, &serror);
448 sil_scr_write(&ap->link, SCR_ERROR, serror);
Tejun Heod4c85322006-06-12 18:45:55 +0900449
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900450 /* Sometimes spurious interrupts occur, double check
451 * it's PHYRDY CHG.
Tejun Heod4c85322006-06-12 18:45:55 +0900452 */
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900453 if (serror & SERR_PHYRDY_CHG) {
Tejun Heof7fe7ad2007-12-08 08:47:01 +0900454 ap->link.eh_info.serror |= serror;
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900455 goto freeze;
Tejun Heod4c85322006-06-12 18:45:55 +0900456 }
457
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900458 if (!(bmdma2 & SIL_DMA_COMPLETE))
459 return;
Tejun Heoe5738902006-05-31 18:28:16 +0900460 }
461
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900462 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900463 /* this sometimes happens, just clear IRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900464 ap->ops->sff_check_status(ap);
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900465 return;
466 }
467
Tejun Heocbe88fb2006-05-31 18:27:55 +0900468 /* Check whether we are expecting interrupt in this state */
469 switch (ap->hsm_task_state) {
470 case HSM_ST_FIRST:
471 /* Some pre-ATAPI-4 devices assert INTRQ
472 * at this state when ready to receive CDB.
473 */
474
475 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
Tejun Heo405e66b2007-11-27 19:28:53 +0900476 * The flag was turned on only for atapi devices. No
477 * need to check ata_is_atapi(qc->tf.protocol) again.
Tejun Heocbe88fb2006-05-31 18:27:55 +0900478 */
479 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
480 goto err_hsm;
481 break;
482 case HSM_ST_LAST:
Tejun Heo405e66b2007-11-27 19:28:53 +0900483 if (ata_is_dma(qc->tf.protocol)) {
Tejun Heocbe88fb2006-05-31 18:27:55 +0900484 /* clear DMA-Start bit */
485 ap->ops->bmdma_stop(qc);
486
487 if (bmdma2 & SIL_DMA_ERROR) {
488 qc->err_mask |= AC_ERR_HOST_BUS;
489 ap->hsm_task_state = HSM_ST_ERR;
490 }
491 }
492 break;
493 case HSM_ST:
494 break;
495 default:
496 goto err_hsm;
497 }
498
499 /* check main status, clearing INTRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900500 status = ap->ops->sff_check_status(ap);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900501 if (unlikely(status & ATA_BUSY))
502 goto err_hsm;
503
504 /* ack bmdma irq events */
Tejun Heo37f65b82010-05-19 22:10:20 +0200505 ata_bmdma_irq_clear(ap);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900506
507 /* kick HSM in the ass */
Tejun Heo9363c382008-04-07 22:47:16 +0900508 ata_sff_hsm_move(ap, qc, status, 0);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900509
Tejun Heo405e66b2007-11-27 19:28:53 +0900510 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
Tejun Heoea547632006-11-17 12:06:21 +0900511 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
512
Tejun Heocbe88fb2006-05-31 18:27:55 +0900513 return;
514
515 err_hsm:
516 qc->err_mask |= AC_ERR_HSM;
517 freeze:
518 ata_port_freeze(ap);
519}
520
David Howells7d12e782006-10-05 14:55:46 +0100521static irqreturn_t sil_interrupt(int irq, void *dev_instance)
Tejun Heocbe88fb2006-05-31 18:27:55 +0900522{
Jeff Garzikcca39742006-08-24 03:19:22 -0400523 struct ata_host *host = dev_instance;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900524 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900525 int handled = 0;
526 int i;
527
Jeff Garzikcca39742006-08-24 03:19:22 -0400528 spin_lock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900529
Jeff Garzikcca39742006-08-24 03:19:22 -0400530 for (i = 0; i < host->n_ports; i++) {
531 struct ata_port *ap = host->ports[i];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900532 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
533
Tejun Heo201ce852006-06-26 21:23:52 +0900534 /* turn off SATA_IRQ if not supported */
535 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
536 bmdma2 &= ~SIL_DMA_SATA_IRQ;
537
Tejun Heo23fa9612006-06-12 14:18:51 +0900538 if (bmdma2 == 0xffffffff ||
539 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900540 continue;
541
542 sil_host_intr(ap, bmdma2);
543 handled = 1;
544 }
545
Jeff Garzikcca39742006-08-24 03:19:22 -0400546 spin_unlock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900547
548 return IRQ_RETVAL(handled);
549}
550
Tejun Heof6aae272006-05-15 20:58:27 +0900551static void sil_freeze(struct ata_port *ap)
552{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900553 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900554 u32 tmp;
555
Tejun Heoe5738902006-05-31 18:28:16 +0900556 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
557 writel(0, mmio_base + sil_port[ap->port_no].sien);
558
Tejun Heof6aae272006-05-15 20:58:27 +0900559 /* plug IRQ */
560 tmp = readl(mmio_base + SIL_SYSCFG);
561 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
562 writel(tmp, mmio_base + SIL_SYSCFG);
563 readl(mmio_base + SIL_SYSCFG); /* flush */
Jeff Garzik2fc37ad2009-04-07 19:18:32 -0400564
565 /* Ensure DMA_ENABLE is off.
566 *
567 * This is because the controller will not give us access to the
568 * taskfile registers while a DMA is in progress
569 */
570 iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE,
571 ap->ioaddr.bmdma_addr);
572
573 /* According to ata_bmdma_stop, an HDMA transition requires
574 * on PIO cycle. But we can't read a taskfile register.
575 */
576 ioread8(ap->ioaddr.bmdma_addr);
Tejun Heof6aae272006-05-15 20:58:27 +0900577}
578
579static void sil_thaw(struct ata_port *ap)
580{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900581 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900582 u32 tmp;
583
584 /* clear IRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900585 ap->ops->sff_check_status(ap);
Tejun Heo37f65b82010-05-19 22:10:20 +0200586 ata_bmdma_irq_clear(ap);
Tejun Heof6aae272006-05-15 20:58:27 +0900587
Tejun Heo201ce852006-06-26 21:23:52 +0900588 /* turn on SATA IRQ if supported */
589 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
590 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
Tejun Heoe5738902006-05-31 18:28:16 +0900591
Tejun Heof6aae272006-05-15 20:58:27 +0900592 /* turn on IRQ */
593 tmp = readl(mmio_base + SIL_SYSCFG);
594 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
595 writel(tmp, mmio_base + SIL_SYSCFG);
596}
597
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598/**
599 * sil_dev_config - Apply device/host-specific errata fixups
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600 * @dev: Device to be examined
601 *
602 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
603 * device is known to be present, this function is called.
604 * We apply two errata fixups which are specific to Silicon Image,
605 * a Seagate and a Maxtor fixup.
606 *
607 * For certain Seagate devices, we must limit the maximum sectors
608 * to under 8K.
609 *
610 * For certain Maxtor devices, we must not program the drive
611 * beyond udma5.
612 *
613 * Both fixups are unfairly pessimistic. As soon as I get more
614 * information on these errata, I will create a more exhaustive
615 * list, and apply the fixups to only the specific
616 * devices/hosts/firmwares that need it.
617 *
618 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
619 * The Maxtor quirk is in the blacklist, but I'm keeping the original
620 * pessimistic fix for the following reasons...
621 * - There seems to be less info on it, only one device gleaned off the
622 * Windows driver, maybe only one is affected. More info would be greatly
623 * appreciated.
624 * - But then again UDMA5 is hardly anything to complain about
625 */
Alancd0d3bb2007-03-02 00:56:15 +0000626static void sil_dev_config(struct ata_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900628 struct ata_port *ap = dev->link->ap;
629 int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630 unsigned int n, quirks = 0;
Tejun Heoa0cf7332007-01-02 20:18:49 +0900631 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632
Tejun Heoa0cf7332007-01-02 20:18:49 +0900633 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634
Jeff Garzik8a60a072005-07-31 13:13:24 -0400635 for (n = 0; sil_blacklist[n].product; n++)
Tejun Heo2e026712006-02-12 22:47:04 +0900636 if (!strcmp(sil_blacklist[n].product, model_num)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 quirks = sil_blacklist[n].quirk;
638 break;
639 }
Jeff Garzik8a60a072005-07-31 13:13:24 -0400640
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 /* limit requests to 15 sectors */
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500642 if (slow_down ||
643 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
644 (quirks & SIL_QUIRK_MOD15WRITE))) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900645 if (print_info)
Joe Perchesa9a79df2011-04-15 15:51:59 -0700646 ata_dev_info(dev,
647 "applying Seagate errata fix (mod15write workaround)\n");
Tejun Heob00eec12006-02-12 23:32:59 +0900648 dev->max_sectors = 15;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 return;
650 }
651
652 /* limit to udma5 */
653 if (quirks & SIL_QUIRK_UDMA5MAX) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900654 if (print_info)
Joe Perchesa9a79df2011-04-15 15:51:59 -0700655 ata_dev_info(dev, "applying Maxtor errata fix %s\n",
656 model_num);
Tejun Heo5a529132006-03-24 14:07:50 +0900657 dev->udma_mask &= ATA_UDMA5;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658 return;
659 }
660}
661
Tejun Heo4447d352007-04-17 23:44:08 +0900662static void sil_init_controller(struct ata_host *host)
Tejun Heo3d8ec912006-07-03 16:07:27 +0900663{
Tejun Heo4447d352007-04-17 23:44:08 +0900664 struct pci_dev *pdev = to_pci_dev(host->dev);
665 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heo3d8ec912006-07-03 16:07:27 +0900666 u8 cls;
667 u32 tmp;
668 int i;
669
670 /* Initialize FIFO PCI bus arbitration */
671 cls = sil_get_device_cache_line(pdev);
672 if (cls) {
673 cls >>= 3;
674 cls++; /* cls = (line_size/8)+1 */
Tejun Heo4447d352007-04-17 23:44:08 +0900675 for (i = 0; i < host->n_ports; i++)
Tejun Heo3d8ec912006-07-03 16:07:27 +0900676 writew(cls << 8 | cls,
677 mmio_base + sil_port[i].fifo_cfg);
678 } else
Joe Perchesa44fec12011-04-15 15:51:58 -0700679 dev_warn(&pdev->dev,
680 "cache line size not set. Driver may not function\n");
Tejun Heo3d8ec912006-07-03 16:07:27 +0900681
682 /* Apply R_ERR on DMA activate FIS errata workaround */
Tejun Heo4447d352007-04-17 23:44:08 +0900683 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900684 int cnt;
685
Tejun Heo4447d352007-04-17 23:44:08 +0900686 for (i = 0, cnt = 0; i < host->n_ports; i++) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900687 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
688 if ((tmp & 0x3) != 0x01)
689 continue;
690 if (!cnt)
Joe Perchesa44fec12011-04-15 15:51:58 -0700691 dev_info(&pdev->dev,
692 "Applying R_ERR on DMA activate FIS errata fix\n");
Tejun Heo3d8ec912006-07-03 16:07:27 +0900693 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
694 cnt++;
695 }
696 }
697
Tejun Heo4447d352007-04-17 23:44:08 +0900698 if (host->n_ports == 4) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900699 /* flip the magic "make 4 ports work" bit */
700 tmp = readl(mmio_base + sil_port[2].bmdma);
701 if ((tmp & SIL_INTR_STEERING) == 0)
702 writel(tmp | SIL_INTR_STEERING,
703 mmio_base + sil_port[2].bmdma);
704 }
705}
706
Rafael J. Wysockie57db7b2009-01-19 20:58:29 +0100707static bool sil_broken_system_poweroff(struct pci_dev *pdev)
708{
709 static const struct dmi_system_id broken_systems[] = {
710 {
711 .ident = "HP Compaq nx6325",
712 .matches = {
713 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
714 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
715 },
716 /* PCI slot number of the controller */
717 .driver_data = (void *)0x12UL,
718 },
719
720 { } /* terminate list */
721 };
722 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
723
724 if (dmi) {
725 unsigned long slot = (unsigned long)dmi->driver_data;
726 /* apply the quirk only to on-board controllers */
727 return slot == PCI_SLOT(pdev->devfn);
728 }
729
730 return false;
731}
732
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400733static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734{
Tejun Heo4447d352007-04-17 23:44:08 +0900735 int board_id = ent->driver_data;
Rafael J. Wysockie57db7b2009-01-19 20:58:29 +0100736 struct ata_port_info pi = sil_port_info[board_id];
737 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo4447d352007-04-17 23:44:08 +0900738 struct ata_host *host;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400739 void __iomem *mmio_base;
Tejun Heo4447d352007-04-17 23:44:08 +0900740 int n_ports, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742
Joe Perches06296a12011-04-15 15:52:00 -0700743 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744
Tejun Heo4447d352007-04-17 23:44:08 +0900745 /* allocate host */
746 n_ports = 2;
747 if (board_id == sil_3114)
748 n_ports = 4;
749
Rafael J. Wysockie57db7b2009-01-19 20:58:29 +0100750 if (sil_broken_system_poweroff(pdev)) {
751 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN |
752 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
753 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
754 "on poweroff and hibernation\n");
755 }
756
Tejun Heo4447d352007-04-17 23:44:08 +0900757 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
758 if (!host)
759 return -ENOMEM;
760
761 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900762 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763 if (rc)
764 return rc;
765
Tejun Heo0d5ff562007-02-01 15:06:36 +0900766 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
767 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900768 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900769 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900770 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +0900771 host->iomap = pcim_iomap_table(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772
773 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
774 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900775 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
777 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900778 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779
Tejun Heo4447d352007-04-17 23:44:08 +0900780 mmio_base = host->iomap[SIL_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
Tejun Heo4447d352007-04-17 23:44:08 +0900782 for (i = 0; i < host->n_ports; i++) {
Tejun Heocbcdd872007-08-18 13:14:55 +0900783 struct ata_port *ap = host->ports[i];
784 struct ata_ioports *ioaddr = &ap->ioaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785
Tejun Heo4447d352007-04-17 23:44:08 +0900786 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
787 ioaddr->altstatus_addr =
788 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
789 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
790 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
Tejun Heo9363c382008-04-07 22:47:16 +0900791 ata_sff_std_ports(ioaddr);
Tejun Heocbcdd872007-08-18 13:14:55 +0900792
793 ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
794 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 }
796
Tejun Heo4447d352007-04-17 23:44:08 +0900797 /* initialize and activate */
798 sil_init_controller(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 pci_set_master(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +0900801 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
802 &sil_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803}
804
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700805#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900806static int sil_pci_device_resume(struct pci_dev *pdev)
807{
Jeff Garzikcca39742006-08-24 03:19:22 -0400808 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo553c4aa2006-12-26 19:39:50 +0900809 int rc;
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900810
Tejun Heo553c4aa2006-12-26 19:39:50 +0900811 rc = ata_pci_device_do_resume(pdev);
812 if (rc)
813 return rc;
814
Tejun Heo4447d352007-04-17 23:44:08 +0900815 sil_init_controller(host);
Jeff Garzikcca39742006-08-24 03:19:22 -0400816 ata_host_resume(host);
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900817
818 return 0;
819}
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700820#endif
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900821
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822static int __init sil_init(void)
823{
Pavel Roskinb7887192006-08-10 18:13:18 +0900824 return pci_register_driver(&sil_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825}
826
827static void __exit sil_exit(void)
828{
829 pci_unregister_driver(&sil_pci_driver);
830}
831
832
833module_init(sil_init);
834module_exit(sil_exit);