Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 SMP source file. It contains platform specific fucntions |
| 3 | * needed for the linux smp kernel. |
| 4 | * |
| 5 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 6 | * |
| 7 | * Author: |
| 8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 9 | * |
| 10 | * Platform file needed for the OMAP4 SMP. This file is based on arm |
| 11 | * realview smp platform. |
| 12 | * * Copyright (c) 2002 ARM Limited. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | */ |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/device.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 20 | #include <linux/smp.h> |
| 21 | #include <linux/io.h> |
| 22 | |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 23 | #include <asm/cacheflush.h> |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 24 | #include <asm/hardware/gic.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 25 | #include <asm/smp_scu.h> |
| 26 | #include <mach/hardware.h> |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 27 | #include <mach/omap-secure.h> |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 28 | |
| 29 | #include "common.h" |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 30 | |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame^] | 31 | #include "clockdomain.h" |
| 32 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 33 | /* SCU base address */ |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 34 | static void __iomem *scu_base; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 35 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 36 | static DEFINE_SPINLOCK(boot_lock); |
| 37 | |
Santosh Shilimkar | 02afe8a | 2011-03-03 18:03:25 +0530 | [diff] [blame] | 38 | void __iomem *omap4_get_scu_base(void) |
| 39 | { |
| 40 | return scu_base; |
| 41 | } |
| 42 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 43 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 44 | { |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 45 | /* |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 46 | * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. |
| 47 | * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA |
| 48 | * init and for CPU1, a secure PPA API provided. CPU0 must be ON |
| 49 | * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. |
| 50 | * OMAP443X GP devices- SMP bit isn't accessible. |
| 51 | * OMAP446X GP devices - SMP bit access is enabled on both CPUs. |
| 52 | */ |
| 53 | if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) |
| 54 | omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, |
| 55 | 4, 0, 0, 0, 0, 0); |
| 56 | |
| 57 | /* |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 58 | * If any interrupts are already enabled for the primary |
| 59 | * core (e.g. timer irq), then they will not have been enabled |
| 60 | * for us: do so |
| 61 | */ |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 62 | gic_secondary_init(0); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * Synchronise with the boot thread. |
| 66 | */ |
| 67 | spin_lock(&boot_lock); |
| 68 | spin_unlock(&boot_lock); |
| 69 | } |
| 70 | |
| 71 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 72 | { |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame^] | 73 | static struct clockdomain *cpu1_clkdm; |
| 74 | static bool booted; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 75 | /* |
| 76 | * Set synchronisation state between this boot processor |
| 77 | * and the secondary one |
| 78 | */ |
| 79 | spin_lock(&boot_lock); |
| 80 | |
| 81 | /* |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 82 | * Update the AuxCoreBoot0 with boot state for secondary core. |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 83 | * omap_secondary_startup() routine will hold the secondary core till |
| 84 | * the AuxCoreBoot1 register is updated with cpu state |
| 85 | * A barrier is added to ensure that write buffer is drained |
| 86 | */ |
Santosh Shilimkar | 7d35b8d | 2010-08-02 13:18:19 +0300 | [diff] [blame] | 87 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 88 | flush_cache_all(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 89 | smp_wmb(); |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame^] | 90 | |
| 91 | if (!cpu1_clkdm) |
| 92 | cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); |
| 93 | |
| 94 | /* |
| 95 | * The SGI(Software Generated Interrupts) are not wakeup capable |
| 96 | * from low power states. This is known limitation on OMAP4 and |
| 97 | * needs to be worked around by using software forced clockdomain |
| 98 | * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to |
| 99 | * software force wakeup. The clockdomain is then put back to |
| 100 | * hardware supervised mode. |
| 101 | * More details can be found in OMAP4430 TRM - Version J |
| 102 | * Section : |
| 103 | * 4.3.4.2 Power States of CPU0 and CPU1 |
| 104 | */ |
| 105 | if (booted) { |
| 106 | clkdm_wakeup(cpu1_clkdm); |
| 107 | clkdm_allow_idle(cpu1_clkdm); |
| 108 | } else { |
| 109 | dsb_sev(); |
| 110 | booted = true; |
| 111 | } |
| 112 | |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 113 | gic_raise_softirq(cpumask_of(cpu), 1); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 114 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 115 | /* |
| 116 | * Now the secondary core is starting up let it run its |
| 117 | * calibrations, then wait for it to finish |
| 118 | */ |
| 119 | spin_unlock(&boot_lock); |
| 120 | |
| 121 | return 0; |
| 122 | } |
| 123 | |
| 124 | static void __init wakeup_secondary(void) |
| 125 | { |
| 126 | /* |
| 127 | * Write the address of secondary startup routine into the |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 128 | * AuxCoreBoot1 where ROM code will jump and start executing |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 129 | * on secondary core once out of WFE |
| 130 | * A barrier is added to ensure that write buffer is drained |
| 131 | */ |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 132 | omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 133 | smp_wmb(); |
| 134 | |
| 135 | /* |
| 136 | * Send a 'sev' to wake the secondary core from WFE. |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 137 | * Drain the outstanding writes to memory |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 138 | */ |
Tony Lindgren | a4192d3 | 2010-08-16 09:21:20 +0300 | [diff] [blame] | 139 | dsb_sev(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 140 | mb(); |
| 141 | } |
| 142 | |
| 143 | /* |
| 144 | * Initialise the CPU possible map early - this describes the CPUs |
| 145 | * which may be present or become present in the system. |
| 146 | */ |
| 147 | void __init smp_init_cpus(void) |
| 148 | { |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 149 | unsigned int i, ncores; |
| 150 | |
Tony Lindgren | 4c3cf90 | 2011-10-04 18:17:41 -0700 | [diff] [blame] | 151 | /* |
| 152 | * Currently we can't call ioremap here because |
| 153 | * SoC detection won't work until after init_early. |
| 154 | */ |
| 155 | scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 156 | BUG_ON(!scu_base); |
| 157 | |
Russell King | fd778f0 | 2010-12-02 18:09:37 +0000 | [diff] [blame] | 158 | ncores = scu_get_core_count(scu_base); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 159 | |
| 160 | /* sanity check */ |
Russell King | a06f916 | 2011-10-20 22:04:18 +0100 | [diff] [blame] | 161 | if (ncores > nr_cpu_ids) { |
| 162 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
| 163 | ncores, nr_cpu_ids); |
| 164 | ncores = nr_cpu_ids; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 165 | } |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 166 | |
Russell King | bbc3d14 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 167 | for (i = 0; i < ncores; i++) |
| 168 | set_cpu_possible(i, true); |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 169 | |
| 170 | set_smp_cross_call(gic_raise_softirq); |
Russell King | bbc3d14 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 171 | } |
| 172 | |
Russell King | 05c74a6 | 2010-12-03 11:09:48 +0000 | [diff] [blame] | 173 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
Russell King | bbc3d14 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 174 | { |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 175 | |
Russell King | 05c74a6 | 2010-12-03 11:09:48 +0000 | [diff] [blame] | 176 | /* |
| 177 | * Initialise the SCU and wake up the secondary core using |
| 178 | * wakeup_secondary(). |
| 179 | */ |
| 180 | scu_enable(scu_base); |
| 181 | wakeup_secondary(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 182 | } |