blob: 91720291b95bf5d65f5d670ab7e6e94afdb29323 [file] [log] [blame]
Pushkar Joshi70210812012-12-15 19:01:39 -08001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Rohit Vaswani3fc60342012-04-23 18:55:15 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Rohit Vaswani3fc60342012-04-23 18:55:15 -070013/include/ "skeleton.dtsi"
Mitchel Humpherysb3f40d12012-10-05 16:26:58 -070014/include/ "msm9625-ion.dtsi"
Girish Mahadevanfc5f5c32012-10-23 16:27:28 -070015/include/ "msm9625-pm.dtsi"
Pushkar Joshifaf92a72012-10-29 17:45:27 -070016/include/ "msm9625-coresight.dtsi"
Seemanta Dutta519dfd12013-01-22 17:34:36 -080017/include/ "msm9625-smp2p.dtsi"
Rohit Vaswani3fc60342012-04-23 18:55:15 -070018
19/ {
20 model = "Qualcomm MSM 9625";
21 compatible = "qcom,msm9625";
22 interrupt-parent = <&intc>;
23
Gilad Avidov0697ea62013-02-11 16:46:38 -070024 aliases {
25 spi0 = &spi_0;
26 };
27
Rohit Vaswani3fc60342012-04-23 18:55:15 -070028 intc: interrupt-controller@F9000000 {
29 compatible = "qcom,msm-qgic2";
30 interrupt-controller;
31 #interrupt-cells = <3>;
32 reg = <0xF9000000 0x1000>,
33 <0xF9002000 0x1000>;
34 };
35
Abhimanyu Kapur490d20c2012-06-22 17:34:20 -070036 l2: cache-controller@f9040000 {
37 compatible = "arm,pl310-cache";
38 reg = <0xf9040000 0x1000>;
Abhimanyu Kapur490d20c2012-06-22 17:34:20 -070039 cache-unified;
40 cache-level = <2>;
41 };
42
Rohit Vaswani3fc60342012-04-23 18:55:15 -070043 msmgpio: gpio@fd510000 {
44 compatible = "qcom,msm-gpio";
Rohit Vaswanib1cc4932012-07-23 21:30:11 -070045 gpio-controller;
46 #gpio-cells = <2>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070047 interrupt-controller;
48 #interrupt-cells = <2>;
49 reg = <0xfd510000 0x4000>;
Rohit Vaswani341c2032012-11-08 18:49:29 -080050 ngpio = <76>;
Rohit Vaswanid2001522012-12-05 19:23:44 -080051 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -080052 qcom,direct-connect-irqs = <8>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070053 };
54
Abhimanyu Kapur28d0e102013-03-08 19:52:14 -080055 qcom,mpm2-sleep-counter@fc4a3000 {
56 compatible = "qcom,mpm2-sleep-counter";
57 reg = <0xfc4a3000 0x1000>;
58 clock-frequency = <32768>;
59 };
60
Rohit Vaswania5129562012-06-12 20:11:23 -070061 timer: msm-qtimer@f9021000 {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -080062 compatible = "arm,armv7-timer";
Rohit Vaswania5129562012-06-12 20:11:23 -070063 reg = <0xF9021000 0x1000>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070064 interrupts = <0 7 0>;
Rohit Vaswania5129562012-06-12 20:11:23 -070065 irq-is-not-percpu;
Abhimanyu Kapuraf4c4d52012-10-01 14:15:10 -070066 clock-frequency = <19200000>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070067 };
Jin Hong8d328582012-05-01 15:45:29 -070068
Yan He3cb97ba2012-05-13 16:45:24 -070069 qcom,sps@f9980000 {
70 compatible = "qcom,msm_sps";
71 reg = <0xf9984000 0x15000>,
72 <0xf9999000 0xb000>,
Yan He6f9ae712012-09-20 12:55:47 -070073 <0xfe803000 0x4800>;
Yan He3cb97ba2012-05-13 16:45:24 -070074 interrupts = <0 94 0>;
75 qcom,device-type = <2>;
76 };
77
Jin Hong8d328582012-05-01 15:45:29 -070078 serial@f991f000 {
79 compatible = "qcom,msm-lsuart-v14";
80 reg = <0xf991f000 0x1000>;
81 interrupts = <0 109 0>;
82 };
Sahitya Tummala9ba4b282012-06-19 11:41:51 +053083
Jack Phama01e9c12012-09-25 21:37:03 -070084 usb@f9a55000 {
85 compatible = "qcom,hsusb-otg";
86 reg = <0xf9a55000 0x400>;
87 interrupts = <0 134 0 0 140 0>;
88 interrupt-names = "core_irq", "async_irq";
89 HSUSB_VDDCX-supply = <&pm8019_l12>;
90 HSUSB_1p8-supply = <&pm8019_l2>;
91 HSUSB_3p3-supply = <&pm8019_l4>;
David Collins84d39b22012-11-01 14:40:08 -070092 vbus_otg-supply = <&usb_vbus>;
Jack Phama01e9c12012-09-25 21:37:03 -070093
94 qcom,hsusb-otg-phy-type = <2>;
Amit Blay0d353532013-01-22 18:09:51 +020095 qcom,hsusb-otg-mode = <3>;
Jack Phama01e9c12012-09-25 21:37:03 -070096 qcom,hsusb-otg-otg-control = <1>;
97 qcom,hsusb-otg-disable-reset;
Ido Shayevitz9f953c12013-01-13 13:36:30 +020098 qcom,hsusb-otg-lpm-on-dev-suspend;
Ido Shayevitz0f2942d2013-01-13 13:59:48 +020099 qcom,hsusb-otg-clk-always-on-workaround;
Shimrit Malichi3043c0c2013-03-10 11:26:41 +0200100 qcom,hsusb-otg-delay-lpm;
Ido Shayevitz57101762013-01-18 10:06:24 +0200101
102 qcom,msm-bus,name = "usb2";
103 qcom,msm-bus,num-cases = <2>;
104 qcom,msm-bus,active-only = <0>;
105 qcom,msm-bus,num-paths = <1>;
106 qcom,msm-bus,vectors-KBps =
107 <87 512 0 0>,
108 <87 512 40000 640000>;
Jack Phama01e9c12012-09-25 21:37:03 -0700109 };
110
Ofir Cohenb1d52612012-11-14 09:37:38 +0200111 hsic@f9a15000 {
112 compatible = "qcom,hsic-host";
113 reg = <0xf9a15000 0x400>;
Ido Shayevitzfafb1b12013-02-18 18:10:05 +0200114 interrupts = <0 136 0>, <0 148 0>;
115 interrupt-names = "core_irq", "async_irq";
Ofir Cohenb1d52612012-11-14 09:37:38 +0200116 HSIC_VDDCX-supply = <&pm8019_l12>;
117 HSIC_GDSC-supply = <&gdsc_usb_hsic>;
Ido Shayevitz57101762013-01-18 10:06:24 +0200118
119 qcom,msm-bus,name = "hsic";
120 qcom,msm-bus,num-cases = <2>;
121 qcom,msm-bus,active-only = <0>;
122 qcom,msm-bus,num-paths = <1>;
123 qcom,msm-bus,vectors-KBps =
124 <85 512 0 0>,
125 <85 512 40000 640000>;
Shimrit Malichi9e840e32013-03-14 20:45:16 +0200126 qcom,pool-64-bit-align;
127 qcom,enable-hbm;
Ofir Cohenb1d52612012-11-14 09:37:38 +0200128 };
129
Jack Phamd61ff562012-11-21 19:25:53 +0200130 qcom,usbbam@f9a44000 {
131 compatible = "qcom,usb-bam-msm";
Shimrit Malichi9e840e32013-03-14 20:45:16 +0200132 reg = <0xf9a44000 0x11000>,
133 <0xf9a04000 0x11000>;
134 reg-names = "hsusb", "hsic";
135 interrupts = <0 135 0 0 255 0>;
136 interrupt-names = "hsusb", "hsic";
Jack Phamd61ff562012-11-21 19:25:53 +0200137 qcom,usb-bam-num-pipes = <16>;
138 qcom,ignore-core-reset-ack;
repo syncb0ca7512013-01-16 19:37:44 +0200139 qcom,disable-clk-gating;
Jack Phamd61ff562012-11-21 19:25:53 +0200140
141 qcom,pipe0 {
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200142 label = "hsusb-ipa-out-0";
Shimrit Malichi4c74d3b2013-01-29 11:32:23 +0200143 qcom,usb-bam-mem-type = <0>;
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200144 qcom,bam-type = <1>;
145 qcom,dir = <0>;
146 qcom,pipe-num = <0>;
147 qcom,peer-bam = <2>;
Jack Phamd61ff562012-11-21 19:25:53 +0200148 qcom,src-bam-physical-address = <0xf9a44000>;
149 qcom,src-bam-pipe-index = <1>;
Shimrit Malichi4c74d3b2013-01-29 11:32:23 +0200150 qcom,data-fifo-offset = <0x2200>;
151 qcom,data-fifo-size = <0x1e00>;
152 qcom,descriptor-fifo-offset = <0x2100>;
153 qcom,descriptor-fifo-size = <0x100>;
Jack Phamd61ff562012-11-21 19:25:53 +0200154 };
Jack Phamd61ff562012-11-21 19:25:53 +0200155 qcom,pipe1 {
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200156 label = "hsusb-ipa-in-0";
Shimrit Malichi4c74d3b2013-01-29 11:32:23 +0200157 qcom,usb-bam-mem-type = <0>;
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200158 qcom,bam-type = <1>;
159 qcom,dir = <1>;
160 qcom,pipe-num = <0>;
161 qcom,peer-bam = <2>;
Jack Phamd61ff562012-11-21 19:25:53 +0200162 qcom,dst-bam-physical-address = <0xf9a44000>;
163 qcom,dst-bam-pipe-index = <0>;
Shimrit Malichi4c74d3b2013-01-29 11:32:23 +0200164 qcom,data-fifo-offset = <0x300>;
165 qcom,data-fifo-size = <0x1e00>;
166 qcom,descriptor-fifo-offset = <0>;
167 qcom,descriptor-fifo-size = <0x300>;
Jack Phamd61ff562012-11-21 19:25:53 +0200168 };
Anna Perel6ac1fa92013-01-24 22:08:06 +0200169 qcom,pipe2 {
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200170 label = "hsusb-qdss-in-0";
Anna Perel6ac1fa92013-01-24 22:08:06 +0200171 qcom,usb-bam-mem-type = <0>;
Shimrit Malichidbf43d72013-03-16 03:32:27 +0200172 qcom,bam-type = <1>;
173 qcom,dir = <1>;
174 qcom,pipe-num = <0>;
175 qcom,peer-bam = <1>;
Anna Perel6ac1fa92013-01-24 22:08:06 +0200176 qcom,src-bam-physical-address = <0xfc37c000>;
177 qcom,src-bam-pipe-index = <0>;
178 qcom,dst-bam-physical-address = <0xf9a44000>;
179 qcom,dst-bam-pipe-index = <2>;
180 qcom,data-fifo-offset = <0x4100>;
181 qcom,data-fifo-size = <0x400>;
182 qcom,descriptor-fifo-offset = <0x4000>;
183 qcom,descriptor-fifo-size = <0x400>;
184 };
Shimrit Malichi9e840e32013-03-14 20:45:16 +0200185 qcom,pipe3 {
186 label = "hsic-ipa-in-0";
187 qcom,usb-bam-mem-type = <2>;
188 qcom,bam-type = <2>;
189 qcom,dir = <1>;
190 qcom,pipe-num = <0>;
191 qcom,peer-bam = <2>;
192 qcom,dst-bam-physical-address = <0xf9a04000>;
193 qcom,dst-bam-pipe-index = <3>;
194 qcom,data-fifo-size = <0xD480>;
195 qcom,descriptor-fifo-size = <0x1A80>;
196 };
197 qcom,pipe4 {
198 label = "hsic-ipa-in-1";
199 qcom,bam-type = <2>;
200 qcom,dir = <1>;
201 qcom,pipe-num = <1>;
202 qcom,peer-bam = <2>;
203 qcom,usb-bam-mem-type = <2>;
204 qcom,dst-bam-physical-address = <0xf9a04000>;
205 qcom,dst-bam-pipe-index = <4>;
206 qcom,data-fifo-size = <0xD480>;
207 qcom,descriptor-fifo-size = <0x1A80>;
208 };
209 qcom,pipe5 {
210 label = "hsic-ipa-in-2";
211 qcom,usb-bam-mem-type = <2>;
212 qcom,bam-type = <2>;
213 qcom,dir = <1>;
214 qcom,pipe-num = <2>;
215 qcom,peer-bam = <2>;
216 qcom,dst-bam-physical-address = <0xf9a04000>;
217 qcom,dst-bam-pipe-index = <5>;
218 qcom,data-fifo-size = <0xD480>;
219 qcom,descriptor-fifo-size = <0x1A80>;
220 };
221 qcom,pipe6 {
222 label = "hsic-ipa-in-3";
223 qcom,usb-bam-mem-type = <2>;
224 qcom,bam-type = <2>;
225 qcom,dir = <1>;
226 qcom,pipe-num = <3>;
227 qcom,peer-bam = <2>;
228 qcom,dst-bam-physical-address = <0xf9a04000>;
229 qcom,dst-bam-pipe-index = <6>;
230 qcom,data-fifo-size = <0xD480>;
231 qcom,descriptor-fifo-size = <0x1A80>;
232 };
233 qcom,pipe7 {
234 label = "hsic-ipa-out-0";
235 qcom,usb-bam-mem-type = <2>;
236 qcom,bam-type = <2>;
237 qcom,dir = <0>;
238 qcom,pipe-num = <0>;
239 qcom,peer-bam = <2>;
240 qcom,src-bam-physical-address = <0xf9a04000>;
241 qcom,src-bam-pipe-index = <7>;
242 qcom,data-fifo-size = <0xD480>;
243 qcom,descriptor-fifo-size = <0x1A80>;
244 };
Jack Phamd61ff562012-11-21 19:25:53 +0200245 };
246
Sahitya Tummala9ba4b282012-06-19 11:41:51 +0530247 qcom,nand@f9ac0000 {
248 compatible = "qcom,msm-nand";
249 reg = <0xf9ac0000 0x1000>,
250 <0xf9ac4000 0x8000>;
251 reg-names = "nand_phys",
252 "bam_phys";
253 interrupts = <0 247 0>;
254 interrupt-names = "bam_irq";
255 };
Rohit Vaswani0045df42012-06-29 16:21:48 -0700256
Gilad Avidov0697ea62013-02-11 16:46:38 -0700257 spi_0: spi@f9924000 {
Rohit Vaswani0045df42012-06-29 16:21:48 -0700258 compatible = "qcom,spi-qup-v2";
Gilad Avidov09c78ec2012-10-18 09:34:35 -0600259 reg = <0xf9924000 0x1000>;
260 interrupts = <0 96 0>;
261 spi-max-frequency = <25000000>;
Rohit Vaswani0045df42012-06-29 16:21:48 -0700262 #address-cells = <1>;
263 #size-cells = <0>;
Gilad Avidov09c78ec2012-10-18 09:34:35 -0600264 gpios = <&msmgpio 7 0>, /* CLK */
265 <&msmgpio 5 0>, /* MISO */
266 <&msmgpio 4 0>; /* MOSI */
Rohit Vaswani0045df42012-06-29 16:21:48 -0700267
Gilad Avidov09c78ec2012-10-18 09:34:35 -0600268 cs-gpios = <&msmgpio 6 0>;
Rohit Vaswani0045df42012-06-29 16:21:48 -0700269
270 ethernet-switch@0 {
271 compatible = "simtec,ks8851";
272 reg = <0>;
273 interrupt-parent = <&msmgpio>;
274 interrupts = <75 0>;
Gilad Avidov09c78ec2012-10-18 09:34:35 -0600275 spi-max-frequency = <4800000>;
Rohit Vaswani0045df42012-06-29 16:21:48 -0700276 };
277 };
Hanumant Singh6c4bf062012-09-06 15:51:10 -0700278
279 qcom,wdt@f9017000 {
280 compatible = "qcom,msm-watchdog";
281 reg = <0xf9017000 0x1000>;
282 interrupts = <1 2 0>, <1 1 0>;
283 qcom,bark-time = <11000>;
284 qcom,pet-time = <10000>;
Hanumant Singh6c4bf062012-09-06 15:51:10 -0700285 };
Kenneth Heitkec2642402012-09-18 18:56:47 -0600286
Girish Mahadevanc65a7112012-09-19 11:15:56 -0600287 rpm_bus: qcom,rpm-smd {
288 compatible = "qcom,rpm-smd";
289 rpm-channel-name = "rpm_requests";
290 rpm-channel-type = <15>; /* SMD_APPS_RPM */
291 };
292
Kenneth Heitkec2642402012-09-18 18:56:47 -0600293 spmi_bus: qcom,spmi@fc4c0000 {
294 cell-index = <0>;
295 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700296 reg-names = "core", "intr", "cnfg";
Kenneth Heitkec2642402012-09-18 18:56:47 -0600297 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700298 <0Xfc4cb000 0x1000>,
299 <0Xfc4ca000 0x1000>;
Kenneth Heitkec2642402012-09-18 18:56:47 -0600300 /* 190,ee0_krait_hlos_spmi_periph_irq */
301 /* 187,channel_0_krait_hlos_trans_done_irq */
302 interrupts = <0 190 0 0 187 0>;
303 qcom,pmic-arb-ee = <0>;
304 qcom,pmic-arb-channel = <0>;
Kenneth Heitkec2642402012-09-18 18:56:47 -0600305 };
Kenneth Heitkef92a8c72012-10-10 17:15:05 -0600306
307 i2c@f9925000 {
308 cell-index = <3>;
309 compatible = "qcom,i2c-qup";
310 reg = <0xf9925000 0x1000>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg-names = "qup_phys_addr";
314 interrupts = <0 97 0>;
315 interrupt-names = "qup_err_intr";
316 qcom,i2c-bus-freq = <100000>;
317 qcom,i2c-src-freq = <24000000>;
318 };
Oluwafemi Adeyemibbbcc6e2012-09-14 17:24:26 -0700319
320 sdcc2: qcom,sdcc@f98a4000 {
321 cell-index = <2>; /* SDC2 SD card slot */
322 compatible = "qcom,msm-sdcc";
323 reg = <0xf98a4000 0x800>,
324 <0xf98a4800 0x100>,
325 <0xf9884000 0x7000>;
326 reg-names = "core_mem", "dml_mem", "bam_mem";
327
328 vdd-supply = <&ext_2p95v>;
329
330 vdd-io-supply = <&pm8019_l13>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700331 qcom,vdd-io-always-on;
332 qcom,vdd-io-lpm-sup;
333 qcom,vdd-io-voltage-level = <1800000 2950000>;
334 qcom,vdd-io-current-level = <6 22000>;
Oluwafemi Adeyemibbbcc6e2012-09-14 17:24:26 -0700335
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700336 qcom,pad-pull-on = <0x0 0x3 0x3>;
337 qcom,pad-pull-off = <0x0 0x3 0x3>;
338 qcom,pad-drv-on = <0x7 0x4 0x4>;
339 qcom,pad-drv-off = <0x0 0x0 0x0>;
Oluwafemi Adeyemibbbcc6e2012-09-14 17:24:26 -0700340
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700341 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
342 qcom,sup-voltages = <2950 2950>;
343 qcom,bus-width = <4>;
344 qcom,xpc;
345 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
346 qcom,current-limit = <800>;
Oluwafemi Adeyemibbbcc6e2012-09-14 17:24:26 -0700347
348 interrupt-parent = <&sdcc2>;
349 #address-cells = <0>;
350 interrupts = <0 1 2>;
351 #interrupt-cells = <1>;
352 interrupt-map-mask = <0xffffffff>;
353 interrupt-map = <0 &intc 0 125 0
354 1 &intc 0 220 0
355 2 &msmgpio 66 0x3>;
356 interrupt-names = "core_irq", "bam_irq", "status_irq";
357 cd-gpios = <&msmgpio 66 0>;
358 };
Oluwafemi Adeyemi4926a9e2012-09-14 17:39:59 -0700359
360 sdcc3: qcom,sdcc@f9864000 {
361 cell-index = <3>; /* SDC3 SDIO slot */
362 compatible = "qcom,msm-sdcc";
363 reg = <0xf9864000 0x800>,
364 <0xf9864800 0x100>,
365 <0xf9844000 0x7000>;
366 reg-names = "core_mem", "dml_mem", "bam_mem";
367 interrupts = <0 127 0>, <0 223 0>;
368 interrupt-names = "core_irq", "bam_irq";
369
370 gpios = <&msmgpio 25 0>,
371 <&msmgpio 24 0>,
372 <&msmgpio 16 0>,
373 <&msmgpio 17 0>,
374 <&msmgpio 18 0>,
375 <&msmgpio 19 0>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700376 qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
Oluwafemi Adeyemi4926a9e2012-09-14 17:39:59 -0700377
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700378 qcom,clk-rates = <400000 25000000 50000000 100000000>;
379 qcom,sup-voltages = <2950 2950>;
380 qcom,bus-width = <4>;
381 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Oluwafemi Adeyemi4926a9e2012-09-14 17:39:59 -0700382 };
Jeff Hugocdcb8aa2012-10-16 13:41:20 -0600383
Ravi Gummadidalaedae2002013-02-06 12:13:59 -0800384 ipa_hw: qcom,ipa@fd4c0000 {
Talel Atias49196392012-11-20 19:20:14 +0200385 compatible = "qcom,ipa";
386 reg = <0xfd4c0000 0x26000>,
Vladislav Mordohovich4028f802013-03-04 15:16:31 +0200387 <0xfd4c4000 0x14818>,
388 <0xfc834000 0x7000>;
389 reg-names = "ipa-base", "bam-base", "a2-bam-base";
Talel Atias49196392012-11-20 19:20:14 +0200390 interrupts = <0 252 0>,
Vladislav Mordohovich4028f802013-03-04 15:16:31 +0200391 <0 253 0>,
392 <0 29 1>;
393 interrupt-names = "ipa-irq", "bam-irq", "a2-bam-irq";
Talel Atias49196392012-11-20 19:20:14 +0200394
395 qcom,pipe1 {
396 label = "a2-to-ipa";
397 qcom,src-bam-physical-address = <0xfc834000>;
398 qcom,ipa-bam-mem-type = <0>;
399 qcom,src-bam-pipe-index = <1>;
400 qcom,dst-bam-physical-address = <0xfd4c0000>;
401 qcom,dst-bam-pipe-index = <6>;
402 qcom,data-fifo-offset = <0x1000>;
403 qcom,data-fifo-size = <0xd00>;
404 qcom,descriptor-fifo-offset = <0x1d00>;
405 qcom,descriptor-fifo-size = <0x300>;
406 };
407
408 qcom,pipe2 {
409 label = "ipa-to-a2";
410 qcom,src-bam-physical-address = <0xfd4c0000>;
411 qcom,ipa-bam-mem-type = <0>;
412 qcom,src-bam-pipe-index = <7>;
413 qcom,dst-bam-physical-address = <0xfc834000>;
414 qcom,dst-bam-pipe-index = <0>;
415 qcom,data-fifo-offset = <0x00>;
416 qcom,data-fifo-size = <0xd00>;
417 qcom,descriptor-fifo-offset = <0xd00>;
418 qcom,descriptor-fifo-size = <0x300>;
419 };
420 };
421
Tianyi Gouf6ffa872012-10-22 14:22:58 -0700422 qcom,acpuclk@f9010000 {
423 compatible = "qcom,acpuclk-9625";
424 reg = <0xf9010008 0x10>,
425 <0xf9008004 0x4>;
426 reg-names = "rcg_base", "pwr_base";
427 a5_cpu-supply = <&pm8019_l10_corner_ao>;
428 a5_mem-supply = <&pm8019_l12_ao>;
429 };
Tianyi Gou343bd932012-10-29 11:03:03 -0700430
431 gdsc_usb_hsic: qcom,gdsc@fc400404 {
432 compatible = "qcom,gdsc";
433 reg = <0xfc400404 0x4>;
434 regulator-name = "gdsc_usb_hsic";
435 };
Siddartha Mohanadoss650af6b2012-10-25 20:09:11 -0700436
437 tsens@fc4a8000 {
438 compatible = "qcom,msm-tsens";
439 reg = <0xfc4a8000 0x2000>,
440 <0xfc4b8000 0x1000>;
441 reg-names = "tsens_physical", "tsens_eeprom_physical";
442 interrupts = <0 184 0>;
443 qcom,sensors = <5>;
444 qcom,slope = <3200 3200 3200 3200 3200>;
Siddartha Mohanadoss3f8cd142013-02-06 17:24:33 -0800445 qcom,calib-mode = "fuse_map1";
Siddartha Mohanadoss650af6b2012-10-25 20:09:11 -0700446 };
Hariprasad Dhalinarasimhae9ad1da2012-11-14 18:21:56 -0800447
448 qcom,msm-rng@f9bff000 {
449 compatible = "qcom,msm-rng";
450 reg = <0xf9bff000 0x200>;
451 qcom,msm-rng-iface-clk;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700452 };
453
454 wcd9xxx_intc: wcd9xxx-irq {
455 compatible = "qcom,wcd9xxx-irq";
456 interrupt-controller;
457 #interrupt-cells = <1>;
458 interrupt-parent = <&msmgpio>;
459 interrupts = <20 0>;
460 interrupt-names = "cdc-int";
461 };
462
463 i2c@f9925000 {
464 cell-index = <3>;
465 compatible = "qcom,i2c-qup";
466 reg = <0xf9925000 0x1000>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 reg-names = "qup_phys_addr";
470 interrupts = <0 97 0>;
471 interrupt-names = "qup_err_intr";
472 qcom,i2c-bus-freq = <100000>;
473 qcom,i2c-src-freq = <24000000>;
474
475 wcd9xxx_codec@0d{
476 compatible = "qcom,wcd9xxx-i2c";
477 reg = <0x0d>;
478 qcom,cdc-reset-gpio = <&msmgpio 22 0>;
479 interrupt-parent = <&wcd9xxx_intc>;
480 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28>;
481 cdc-vdd-buck-supply = <&pm8019_l11>;
482 qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
483 qcom,cdc-vdd-buck-current = <25000>;
484
485 cdc-vdd-tx-h-supply = <&pm8019_l11>;
486 qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
487 qcom,cdc-vdd-tx-h-current = <25000>;
488
489 cdc-vdd-rx-h-supply = <&pm8019_l11>;
490 qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
491 qcom,cdc-vdd-rx-h-current = <25000>;
492
493 cdc-vddpx-1-supply = <&pm8019_l11>;
494 qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
495 qcom,cdc-vddpx-1-current = <10000>;
496
497 cdc-vdd-a-1p2v-supply = <&pm8019_l9>;
498 qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
499 qcom,cdc-vdd-a-1p2v-current = <10000>;
500
501 cdc-vddcx-1-supply = <&pm8019_l9>;
502 qcom,cdc-vddcx-1-voltage = <1200000 1200000>;
503 qcom,cdc-vddcx-1-current = <10000>;
504
505 cdc-vddcx-2-supply = <&pm8019_l9>;
506 qcom,cdc-vddcx-2-voltage = <1200000 1200000>;
507 qcom,cdc-vddcx-2-current = <10000>;
508
509 qcom,cdc-micbias-ldoh-v = <0x3>;
510 qcom,cdc-micbias-cfilt1-mv = <1800>;
511 qcom,cdc-micbias-cfilt2-mv = <2700>;
512 qcom,cdc-micbias-cfilt3-mv = <1800>;
513 qcom,cdc-micbias1-cfilt-sel = <0x0>;
514 qcom,cdc-micbias2-cfilt-sel = <0x1>;
515 qcom,cdc-micbias3-cfilt-sel = <0x2>;
516 qcom,cdc-micbias4-cfilt-sel = <0x2>;
Venkat Sudhira50a3762012-11-26 12:12:15 -0800517 qcom,cdc-mclk-clk-rate = <12288000>;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700518 };
519
520 wcd9xxx_codec@77{
521 compatible = "qcom,wcd9xxx-i2c";
522 reg = <0x77>;
523 };
524
525 wcd9xxx_codec@66{
526 compatible = "qcom,wcd9xxx-i2c";
527 reg = <0x66>;
528 };
529
530 wcd9xxx_codec@55{
531 compatible = "qcom,wcd9xxx-i2c";
532 reg = <0x55>;
533 };
534 };
535
536 sound {
537 compatible = "qcom,mdm9625-audio-taiko";
538 qcom,model = "mdm9625-taiko-i2s-snd-card";
539
540 qcom,audio-routing =
541 "RX_BIAS", "MCLK",
542 "LDO_H", "MCLK",
543 "Ext Spk Bottom Pos", "LINEOUT1",
544 "Ext Spk Bottom Neg", "LINEOUT3",
545 "Ext Spk Top Pos", "LINEOUT2",
546 "Ext Spk Top Neg", "LINEOUT4",
547 "AMIC1", "MIC BIAS1 External",
548 "MIC BIAS1 External", "Handset Mic",
549 "AMIC2", "MIC BIAS2 External",
550 "MIC BIAS2 External", "Headset Mic",
551 "AMIC3", "MIC BIAS3 Internal1",
552 "MIC BIAS3 Internal1", "ANCRight Headset Mic",
553 "AMIC4", "MIC BIAS1 Internal2",
554 "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
555 "DMIC1", "MIC BIAS1 External",
556 "MIC BIAS1 External", "Digital Mic1",
557 "DMIC2", "MIC BIAS1 External",
558 "MIC BIAS1 External", "Digital Mic2",
559 "DMIC3", "MIC BIAS3 External",
560 "MIC BIAS3 External", "Digital Mic3",
561 "DMIC4", "MIC BIAS3 External",
562 "MIC BIAS3 External", "Digital Mic4",
563 "DMIC5", "MIC BIAS4 External",
564 "MIC BIAS4 External", "Digital Mic5",
565 "DMIC6", "MIC BIAS4 External",
566 "MIC BIAS4 External", "Digital Mic6";
567 qcom,taiko-mclk-clk-freq = <12288000>;
Venkat Sudhir459d6f52012-12-04 12:00:13 -0800568 prim-i2s-gpio-ws = <&msmgpio 12 0>;
569 prim-i2s-gpio-din = <&msmgpio 13 0>;
570 prim-i2s-gpio-dout = <&msmgpio 14 0>;
571 prim-i2s-gpio-sclk = <&msmgpio 15 0>;
572 prim-i2s-gpio-mclk = <&msmgpio 71 0>;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700573 };
574
575 qcom,msm-adsp-loader {
576 compatible = "qcom,adsp-loader";
Venkat Sudhir480db8a2012-11-09 15:31:50 -0800577 qcom,adsp-state = <2>;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700578 };
579
580 qcom,msm-pcm {
581 compatible = "qcom,msm-pcm-dsp";
Venkat Sudhir3f88b092013-02-28 16:28:37 -0800582 qcom,msm-pcm-dsp-id = <0>;
Venkat Sudhir49965c72012-10-23 14:06:10 -0700583 };
584
585 qcom,msm-pcm-routing {
586 compatible = "qcom,msm-pcm-routing";
587 };
588
589 qcom,msm-compr-dsp {
590 compatible = "qcom,msm-compr-dsp";
591 };
592
593 qcom,msm-voip-dsp {
594 compatible = "qcom,msm-voip-dsp";
595 };
596
597 qcom,msm-pcm-voice {
598 compatible = "qcom,msm-pcm-voice";
599 };
600
Venkat Sudhire26f8c42013-01-14 16:53:35 -0800601 qcom,msm-stub-codec {
602 compatible = "qcom,msm-stub-codec";
603 };
604
Venkat Sudhir49965c72012-10-23 14:06:10 -0700605 qcom,msm-dai-fe {
606 compatible = "qcom,msm-dai-fe";
607 };
608
609 qcom,msm-pcm-afe {
610 compatible = "qcom,msm-pcm-afe";
611 };
612
613 qcom,msm-pcm-hostless {
614 compatible = "qcom,msm-pcm-hostless";
615 };
616
Venkat Sudhire26f8c42013-01-14 16:53:35 -0800617 qcom,msm-dai-q6 {
618 compatible = "qcom,msm-dai-q6";
619 qcom,msm-dai-q6-be-afe-pcm-rx {
620 compatible = "qcom,msm-dai-q6-dev";
621 qcom,msm-dai-q6-dev-id = <224>;
622 };
623
624 qcom,msm-dai-q6-be-afe-pcm-tx {
625 compatible = "qcom,msm-dai-q6-dev";
626 qcom,msm-dai-q6-dev-id = <225>;
627 };
628
629 qcom,msm-dai-q6-afe-proxy-rx {
630 compatible = "qcom,msm-dai-q6-dev";
631 qcom,msm-dai-q6-dev-id = <241>;
632 };
633
634 qcom,msm-dai-q6-afe-proxy-tx {
635 compatible = "qcom,msm-dai-q6-dev";
636 qcom,msm-dai-q6-dev-id = <240>;
637 };
638 };
Venkat Sudhire8320292013-01-17 13:45:15 -0800639 qcom,msm-pcm-dtmf {
640 compatible = "qcom,msm-pcm-dtmf";
641 };
642
643 qcom,msm-dai-stub {
644 compatible = "qcom,msm-dai-stub";
645 };
646
647 qcom,msm-stub-codec {
648 compatible = "qcom,msm-stub-codec";
649 };
Venkat Sudhire26f8c42013-01-14 16:53:35 -0800650
Prashanth Reddyf9536572013-02-13 12:17:08 -0800651 qcom,msm-auxpcm {
652 compatible = "qcom,msm-auxpcm-resource";
653 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
654 qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
655 qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
656 qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
657 qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
658 qcom,msm-cpudai-auxpcm-slot = <1>, <1>;
659 qcom,msm-cpudai-auxpcm-data = <0>, <0>;
660 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
661
662 qcom,msm-auxpcm-rx {
663 qcom,msm-auxpcm-dev-id = <4106>;
664 compatible = "qcom,msm-auxpcm-dev";
665 };
666
667 qcom,msm-auxpcm-tx {
668 qcom,msm-auxpcm-dev-id = <4107>;
669 compatible = "qcom,msm-auxpcm-dev";
670 };
671 };
672
Venkat Sudhir49965c72012-10-23 14:06:10 -0700673 qcom,msm-dai-mi2s {
674 compatible = "qcom,msm-dai-mi2s";
675 qcom,msm-dai-q6-mi2s-prim {
676 compatible = "qcom,msm-dai-q6-mi2s";
677 qcom,msm-dai-q6-mi2s-dev-id = <0>;
678 qcom,msm-mi2s-rx-lines = <2>;
679 qcom,msm-mi2s-tx-lines = <1>;
680 };
681 };
682
683 qcom,msm-dai-q6 {
684 compatible = "qcom,msm-dai-q6";
685 };
Vikram Mulukutla7f4ed0d2012-11-05 15:26:51 -0800686
687 qcom,mss {
688 compatible = "qcom,pil-q6v5-mss";
689 interrupts = <0 24 1>;
Seemanta Dutta519dfd12013-01-22 17:34:36 -0800690
691 /* GPIO input from mss */
692 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
693
694 /* GPIO output to mss */
695 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Vikram Mulukutla7f4ed0d2012-11-05 15:26:51 -0800696 };
Jeff Hugo27a6cf02012-11-29 15:46:50 -0700697
698 qcom,smem@fa00000 {
699 compatible = "qcom,smem";
700 reg = <0xfa00000 0x200000>,
Stepan Moskovchenkod6ee8262013-02-06 11:26:05 -0800701 <0xf9011000 0x1000>,
Jeff Hugo27a6cf02012-11-29 15:46:50 -0700702 <0xfc428000 0x4000>;
703 reg-names = "smem", "irq-reg-base", "aux-mem1";
704
705 qcom,smd-modem {
706 compatible = "qcom,smd";
707 qcom,smd-edge = <0>;
708 qcom,smd-irq-offset = <0x8>;
709 qcom,smd-irq-bitmask = <0x1000>;
710 qcom,pil-string = "modem";
711 interrupts = <0 25 1>;
712 };
713
714 qcom,smsm-modem {
715 compatible = "qcom,smsm";
716 qcom,smsm-edge = <0>;
717 qcom,smsm-irq-offset = <0x8>;
718 qcom,smsm-irq-bitmask = <0x2000>;
719 interrupts = <0 26 1>;
720 };
721
722 qcom,smd-adsp {
723 compatible = "qcom,smd";
724 qcom,smd-edge = <1>;
725 qcom,smd-irq-offset = <0x8>;
726 qcom,smd-irq-bitmask = <0x100>;
727 qcom,pil-string = "adsp";
728 interrupts = <0 156 1>;
729 };
730
731 qcom,smsm-adsp {
732 compatible = "qcom,smsm";
733 qcom,smsm-edge = <1>;
734 qcom,smsm-irq-offset = <0x8>;
735 qcom,smsm-irq-bitmask = <0x200>;
736 interrupts = <0 157 1>;
737 };
738
739 qcom,smd-rpm {
740 compatible = "qcom,smd";
741 qcom,smd-edge = <15>;
742 qcom,smd-irq-offset = <0x8>;
743 qcom,smd-irq-bitmask = <0x1>;
744 interrupts = <0 168 1>;
745 qcom,irq-no-suspend;
746 };
747 };
Hariprasad Dhalinarasimhaf4a5b0c2012-11-21 17:49:19 -0800748
749 qcom,qcedev@fd400000 {
750 compatible = "qcom,qcedev";
751 reg = <0xfd400000 0x20000>,
752 <0xfd404000 0x8000>;
753 reg-names = "crypto-base","crypto-bam-base";
754 interrupts = <0 207 0>;
755 qcom,bam-pipe-pair = <1>;
756 };
757
758 qcom,qcrypto@fd440000 {
759 compatible = "qcom,qcrypto";
760 reg = <0xfd400000 0x20000>,
761 <0xfd404000 0x8000>;
762 reg-names = "crypto-base","crypto-bam-base";
763 interrupts = <0 207 0>;
764 qcom,bam-pipe-pair = <2>;
765 };
766
Pushkar Joshi70210812012-12-15 19:01:39 -0800767 jtag_mm: jtagmm@fc332000 {
768 compatible = "qcom,jtag-mm";
769 reg = <0xfc332000 0x1000>,
770 <0xfc330000 0x1000>;
771 reg-names = "etm-base","debug-base";
772 };
Pushkar Joshi30306d32013-01-16 17:00:26 -0800773
774 qcom,msm-rtb {
775 compatible = "qcom,msm-rtb";
776 qcom,memory-reservation-type = "EBI1";
777 qcom,memory-reservation-size = <0x1000>; /* 4K EBI1 buffer */
778 };
Neeti Desai2036e122012-11-30 14:24:13 -0800779
780 qcom,msm-mem-hole {
781 compatible = "qcom,msm-mem-hole";
782 qcom,memblock-remove = <0x1f00000 0x5700000>; /* Address and Size of Hole */
783 };
784
Jeff Hugo96766e22013-03-06 13:52:37 -0700785 sfpb_spinlock: qcom,ipc-spinlock@fd484000 {
786 compatible = "qcom,ipc-spinlock-sfpb";
Jeff Hugo86a55b22013-03-14 14:51:30 -0600787 reg = <0xfd484000 0x400>;
788 qcom,num-locks = <8>;
Jeff Hugo96766e22013-03-06 13:52:37 -0700789 };
790
791 ldrex_spinlock: qcom,ipc-spinlock@fa00000 {
792 compatible = "qcom,ipc-spinlock-ldrex";
793 reg = <0xfa00000 0x200000>;
794 status = "disable";
795 };
796
Ashwin Chaugule50d59892013-03-12 12:58:51 -0400797 cpu-pmu {
798 compatible = "arm,cortex-a5-pmu";
799 qcom,irq-is-percpu;
800 interrupts = <1 7 0x00>;
801 };
802
803 l2-pmu {
804 compatible = "qcom,l2-pmu";
805 interrupts = <0 1 0>;
806 };
807
Rohit Vaswani3fc60342012-04-23 18:55:15 -0700808};
David Collinsa2b73f22012-09-13 17:32:16 -0700809
David Collins722a6512012-09-14 11:09:18 -0700810/include/ "msm-pm8019-rpm-regulator.dtsi"
David Collinsa2b73f22012-09-13 17:32:16 -0700811/include/ "msm-pm8019.dtsi"
David Collins56b41122012-09-24 17:09:23 -0700812/include/ "msm9625-regulator.dtsi"
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700813
814&pm8019_vadc {
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800815 chan@31 {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700816 label = "batt_id_therm";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800817 reg = <0x31>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700818 qcom,decimation = <0>;
819 qcom,pre-div-channel-scaling = <0>;
820 qcom,calibration-type = "ratiometric";
821 qcom,scale-function = <0>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800822 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700823 qcom,fast-avg-setup = <0>;
824 };
825
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800826 chan@33 {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700827 label = "pa_therm1";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800828 reg = <0x33>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700829 qcom,decimation = <0>;
830 qcom,pre-div-channel-scaling = <0>;
831 qcom,calibration-type = "ratiometric";
832 qcom,scale-function = <2>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800833 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700834 qcom,fast-avg-setup = <0>;
835 };
836
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800837 chan@34 {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700838 label = "pa_therm2";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800839 reg = <0x34>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700840 qcom,decimation = <0>;
841 qcom,pre-div-channel-scaling = <0>;
842 qcom,calibration-type = "ratiometric";
843 qcom,scale-function = <2>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800844 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700845 qcom,fast-avg-setup = <0>;
846 };
847
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800848 chan@32 {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700849 label = "xo_therm";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800850 reg = <0x32>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700851 qcom,decimation = <0>;
852 qcom,pre-div-channel-scaling = <0>;
853 qcom,calibration-type = "ratiometric";
854 qcom,scale-function = <4>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800855 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700856 qcom,fast-avg-setup = <0>;
857 };
858
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800859 chan@3c {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700860 label = "xo_therm_amux";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800861 reg = <0x3c>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700862 qcom,decimation = <0>;
863 qcom,pre-div-channel-scaling = <0>;
864 qcom,calibration-type = "ratiometric";
865 qcom,scale-function = <4>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800866 qcom,hw-settle-time = <2>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700867 qcom,fast-avg-setup = <0>;
868 };
869};