blob: e16cac5c77ca177c96d6ee4206f6d8ae3ffc411b [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
29#include <mach/msm_xo.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070030#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "clock-local.h"
33#include "clock-rpm.h"
34#include "clock-voter.h"
35#include "clock-dss-8960.h"
36#include "devices.h"
37
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
Stephen Boyda52d7e32011-11-10 11:59:00 -080044#define ADM0_PBUS_CLK_CTL_REG REG(0x2208)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070045#define CE1_HCLK_CTL_REG REG(0x2720)
46#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou41515e22011-09-01 19:37:43 -070047#define CE3_HCLK_CTL_REG REG(0x36C4)
48#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
49#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070050#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou41515e22011-09-01 19:37:43 -070051#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070052#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
53#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
54#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
55#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070056/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070057#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
58#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070059#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070060#define CLK_TEST_REG REG(0x2FA0)
Matt Wagantall7625a4c2011-11-01 16:17:53 -070061#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
62#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070063#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
64#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
65#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
66#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
67#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
68#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070069#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070070/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070071#define BB_PLL_ENA_SC0_REG REG(0x34C0)
72#define BB_PLL0_STATUS_REG REG(0x30D8)
73#define BB_PLL5_STATUS_REG REG(0x30F8)
74#define BB_PLL6_STATUS_REG REG(0x3118)
75#define BB_PLL7_STATUS_REG REG(0x3138)
76#define BB_PLL8_L_VAL_REG REG(0x3144)
77#define BB_PLL8_M_VAL_REG REG(0x3148)
78#define BB_PLL8_MODE_REG REG(0x3140)
79#define BB_PLL8_N_VAL_REG REG(0x314C)
80#define BB_PLL8_STATUS_REG REG(0x3158)
81#define BB_PLL8_CONFIG_REG REG(0x3154)
82#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070083#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
84#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070085#define BB_PLL14_MODE_REG REG(0x31C0)
86#define BB_PLL14_L_VAL_REG REG(0x31C4)
87#define BB_PLL14_M_VAL_REG REG(0x31C8)
88#define BB_PLL14_N_VAL_REG REG(0x31CC)
89#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
90#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070091#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070092#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
93#define PMEM_ACLK_CTL_REG REG(0x25A0)
94#define RINGOSC_NS_REG REG(0x2DC0)
95#define RINGOSC_STATUS_REG REG(0x2DCC)
96#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
Stephen Boyda52d7e32011-11-10 11:59:00 -080097#define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070098#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
99#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
100#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
101#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
102#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
103#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
104#define TSIF_HCLK_CTL_REG REG(0x2700)
105#define TSIF_REF_CLK_MD_REG REG(0x270C)
106#define TSIF_REF_CLK_NS_REG REG(0x2710)
107#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700108#define SATA_CLK_SRC_NS_REG REG(0x2C08)
109#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
110#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
111#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
112#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700113#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
114#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
115#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
116#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
117#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
118#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700119#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700120#define USB_HS1_RESET_REG REG(0x2910)
121#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
122#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700123#define USB_HS3_HCLK_CTL_REG REG(0x3700)
124#define USB_HS3_HCLK_FS_REG REG(0x3704)
125#define USB_HS3_RESET_REG REG(0x3710)
126#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
127#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
128#define USB_HS4_HCLK_CTL_REG REG(0x3720)
129#define USB_HS4_HCLK_FS_REG REG(0x3724)
130#define USB_HS4_RESET_REG REG(0x3730)
131#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
132#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700133#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
134#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
135#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
136#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
137#define USB_HSIC_RESET_REG REG(0x2934)
138#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
139#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
140#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700141#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700142#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
143#define PCIE_HCLK_CTL_REG REG(0x22CC)
144#define GPLL1_MODE_REG REG(0x3160)
145#define GPLL1_L_VAL_REG REG(0x3164)
146#define GPLL1_M_VAL_REG REG(0x3168)
147#define GPLL1_N_VAL_REG REG(0x316C)
148#define GPLL1_CONFIG_REG REG(0x3174)
149#define GPLL1_STATUS_REG REG(0x3178)
150#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700151
152/* Multimedia clock registers. */
153#define AHB_EN_REG REG_MM(0x0008)
154#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700155#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700156#define AHB_NS_REG REG_MM(0x0004)
157#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700158#define CAMCLK0_NS_REG REG_MM(0x0148)
159#define CAMCLK0_CC_REG REG_MM(0x0140)
160#define CAMCLK0_MD_REG REG_MM(0x0144)
161#define CAMCLK1_NS_REG REG_MM(0x015C)
162#define CAMCLK1_CC_REG REG_MM(0x0154)
163#define CAMCLK1_MD_REG REG_MM(0x0158)
164#define CAMCLK2_NS_REG REG_MM(0x0228)
165#define CAMCLK2_CC_REG REG_MM(0x0220)
166#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700167#define CSI0_NS_REG REG_MM(0x0048)
168#define CSI0_CC_REG REG_MM(0x0040)
169#define CSI0_MD_REG REG_MM(0x0044)
170#define CSI1_NS_REG REG_MM(0x0010)
171#define CSI1_CC_REG REG_MM(0x0024)
172#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700173#define CSI2_NS_REG REG_MM(0x0234)
174#define CSI2_CC_REG REG_MM(0x022C)
175#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700176#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
177#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
178#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
179#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
180#define DSI1_BYTE_CC_REG REG_MM(0x0090)
181#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
182#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
183#define DSI1_ESC_NS_REG REG_MM(0x011C)
184#define DSI1_ESC_CC_REG REG_MM(0x00CC)
185#define DSI2_ESC_NS_REG REG_MM(0x0150)
186#define DSI2_ESC_CC_REG REG_MM(0x013C)
187#define DSI_PIXEL_CC_REG REG_MM(0x0130)
188#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
189#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
190#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
191#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
192#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
193#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
194#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
195#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
196#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
197#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700198#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700199#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
200#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
201#define GFX2D0_CC_REG REG_MM(0x0060)
202#define GFX2D0_MD0_REG REG_MM(0x0064)
203#define GFX2D0_MD1_REG REG_MM(0x0068)
204#define GFX2D0_NS_REG REG_MM(0x0070)
205#define GFX2D1_CC_REG REG_MM(0x0074)
206#define GFX2D1_MD0_REG REG_MM(0x0078)
207#define GFX2D1_MD1_REG REG_MM(0x006C)
208#define GFX2D1_NS_REG REG_MM(0x007C)
209#define GFX3D_CC_REG REG_MM(0x0080)
210#define GFX3D_MD0_REG REG_MM(0x0084)
211#define GFX3D_MD1_REG REG_MM(0x0088)
212#define GFX3D_NS_REG REG_MM(0x008C)
213#define IJPEG_CC_REG REG_MM(0x0098)
214#define IJPEG_MD_REG REG_MM(0x009C)
215#define IJPEG_NS_REG REG_MM(0x00A0)
216#define JPEGD_CC_REG REG_MM(0x00A4)
217#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700218#define VCAP_CC_REG REG_MM(0x0178)
219#define VCAP_NS_REG REG_MM(0x021C)
220#define VCAP_MD0_REG REG_MM(0x01EC)
221#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700222#define MAXI_EN_REG REG_MM(0x0018)
223#define MAXI_EN2_REG REG_MM(0x0020)
224#define MAXI_EN3_REG REG_MM(0x002C)
225#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700226#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700227#define MDP_CC_REG REG_MM(0x00C0)
228#define MDP_LUT_CC_REG REG_MM(0x016C)
229#define MDP_MD0_REG REG_MM(0x00C4)
230#define MDP_MD1_REG REG_MM(0x00C8)
231#define MDP_NS_REG REG_MM(0x00D0)
232#define MISC_CC_REG REG_MM(0x0058)
233#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700234#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700235#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700236#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
237#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
238#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
239#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
240#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
241#define MM_PLL1_STATUS_REG REG_MM(0x0334)
242#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700243#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
244#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
245#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
246#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
247#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
248#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700249#define ROT_CC_REG REG_MM(0x00E0)
250#define ROT_NS_REG REG_MM(0x00E8)
251#define SAXI_EN_REG REG_MM(0x0030)
252#define SW_RESET_AHB_REG REG_MM(0x020C)
253#define SW_RESET_AHB2_REG REG_MM(0x0200)
254#define SW_RESET_ALL_REG REG_MM(0x0204)
255#define SW_RESET_AXI_REG REG_MM(0x0208)
256#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700257#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700258#define TV_CC_REG REG_MM(0x00EC)
259#define TV_CC2_REG REG_MM(0x0124)
260#define TV_MD_REG REG_MM(0x00F0)
261#define TV_NS_REG REG_MM(0x00F4)
262#define VCODEC_CC_REG REG_MM(0x00F8)
263#define VCODEC_MD0_REG REG_MM(0x00FC)
264#define VCODEC_MD1_REG REG_MM(0x0128)
265#define VCODEC_NS_REG REG_MM(0x0100)
266#define VFE_CC_REG REG_MM(0x0104)
267#define VFE_MD_REG REG_MM(0x0108)
268#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700269#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700270#define VPE_CC_REG REG_MM(0x0110)
271#define VPE_NS_REG REG_MM(0x0118)
272
273/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700274#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700275#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
276#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
277#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
278#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
279#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
280#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
281#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
282#define LCC_MI2S_MD_REG REG_LPA(0x004C)
283#define LCC_MI2S_NS_REG REG_LPA(0x0048)
284#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
285#define LCC_PCM_MD_REG REG_LPA(0x0058)
286#define LCC_PCM_NS_REG REG_LPA(0x0054)
287#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700288#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
289#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
290#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
291#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
292#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700293#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700294#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
295#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
296#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
297#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
298#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
299#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
300#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
301#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
302#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
303#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700304#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700305
Matt Wagantall8b38f942011-08-02 18:23:18 -0700306#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
307
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700308/* MUX source input identifiers. */
309#define pxo_to_bb_mux 0
Matt Wagantall7625a4c2011-11-01 16:17:53 -0700310#define cxo_to_bb_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700311#define pll0_to_bb_mux 2
312#define pll8_to_bb_mux 3
313#define pll6_to_bb_mux 4
314#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700315#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700316#define pxo_to_mm_mux 0
317#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700318#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
319#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700320#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700321#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700322#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700323#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700324#define hdmi_pll_to_mm_mux 3
325#define cxo_to_xo_mux 0
326#define pxo_to_xo_mux 1
327#define gnd_to_xo_mux 3
328#define pxo_to_lpa_mux 0
329#define cxo_to_lpa_mux 1
330#define pll4_to_lpa_mux 2
331#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700332#define pxo_to_pcie_mux 0
333#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700334
335/* Test Vector Macros */
336#define TEST_TYPE_PER_LS 1
337#define TEST_TYPE_PER_HS 2
338#define TEST_TYPE_MM_LS 3
339#define TEST_TYPE_MM_HS 4
340#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700341#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700342#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700343#define TEST_TYPE_SHIFT 24
344#define TEST_CLK_SEL_MASK BM(23, 0)
345#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
346#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
347#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
348#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
349#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
350#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700351#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700352#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700353
354#define MN_MODE_DUAL_EDGE 0x2
355
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700356struct pll_rate {
357 const uint32_t l_val;
358 const uint32_t m_val;
359 const uint32_t n_val;
360 const uint32_t vco;
361 const uint32_t post_div;
362 const uint32_t i_bits;
363};
364#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
365
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800366static int rpm_vreg_id_vdd_dig;
367
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700368enum vdd_dig_levels {
369 VDD_DIG_NONE,
370 VDD_DIG_LOW,
371 VDD_DIG_NOMINAL,
372 VDD_DIG_HIGH
373};
374
375static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
376{
377 static const int vdd_uv[] = {
378 [VDD_DIG_NONE] = 0,
379 [VDD_DIG_LOW] = 945000,
380 [VDD_DIG_NOMINAL] = 1050000,
381 [VDD_DIG_HIGH] = 1150000
382 };
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800383 return rpm_vreg_set_voltage(rpm_vreg_id_vdd_dig, RPM_VREG_VOTER3,
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700384 vdd_uv[level], 1150000, 1);
385}
386
387static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
388
389#define VDD_DIG_FMAX_MAP1(l1, f1) \
390 .vdd_class = &vdd_dig, \
391 .fmax[VDD_DIG_##l1] = (f1)
392#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
393 .vdd_class = &vdd_dig, \
394 .fmax[VDD_DIG_##l1] = (f1), \
395 .fmax[VDD_DIG_##l2] = (f2)
396#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
397 .vdd_class = &vdd_dig, \
398 .fmax[VDD_DIG_##l1] = (f1), \
399 .fmax[VDD_DIG_##l2] = (f2), \
400 .fmax[VDD_DIG_##l3] = (f3)
401
Matt Wagantallc57577d2011-10-06 17:06:53 -0700402enum vdd_l23_levels {
403 VDD_L23_OFF,
404 VDD_L23_ON
405};
406
407static int set_vdd_l23(struct clk_vdd_class *vdd_class, int level)
408{
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800409 int rc = 0;
410 if (cpu_is_msm8960()) {
411 if (level == VDD_L23_OFF) {
412 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
413 RPM_VREG_VOTER3, 0, 0, 1);
414 if (rc)
415 return rc;
416 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
417 RPM_VREG_VOTER3, 0, 0, 1);
418 if (rc)
419 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
420 RPM_VREG_VOTER3, 1800000, 1800000, 1);
421 } else {
422 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
423 RPM_VREG_VOTER3, 2200000, 2200000, 1);
424 if (rc)
425 return rc;
426 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
427 RPM_VREG_VOTER3, 1800000, 1800000, 1);
428 if (rc)
429 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
430 RPM_VREG_VOTER3, 0, 0, 1);
431 }
432 } else if (cpu_is_msm8930() || cpu_is_msm8627()) {
433 if (level == VDD_L23_OFF) {
434 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23,
435 RPM_VREG_VOTER3, 0, 0, 1);
436 if (rc)
437 return rc;
438 } else {
439 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23,
440 RPM_VREG_VOTER3, 1800000, 1800000, 1);
441 if (rc)
442 return rc;
443 }
Matt Wagantallc57577d2011-10-06 17:06:53 -0700444 }
445
446 return rc;
447}
448
449static DEFINE_VDD_CLASS(vdd_l23, set_vdd_l23);
450
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700451/*
452 * Clock Descriptions
453 */
454
455static struct msm_xo_voter *xo_pxo, *xo_cxo;
456
457static int pxo_clk_enable(struct clk *clk)
458{
459 return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON);
460}
461
462static void pxo_clk_disable(struct clk *clk)
463{
Tianyi Gou41515e22011-09-01 19:37:43 -0700464 msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700465}
466
467static struct clk_ops clk_ops_pxo = {
468 .enable = pxo_clk_enable,
469 .disable = pxo_clk_disable,
470 .get_rate = fixed_clk_get_rate,
471 .is_local = local_clk_is_local,
472};
473
474static struct fixed_clk pxo_clk = {
475 .rate = 27000000,
476 .c = {
477 .dbg_name = "pxo_clk",
478 .ops = &clk_ops_pxo,
479 CLK_INIT(pxo_clk.c),
480 },
481};
482
483static int cxo_clk_enable(struct clk *clk)
484{
485 return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON);
486}
487
488static void cxo_clk_disable(struct clk *clk)
489{
490 msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF);
491}
492
493static struct clk_ops clk_ops_cxo = {
494 .enable = cxo_clk_enable,
495 .disable = cxo_clk_disable,
496 .get_rate = fixed_clk_get_rate,
497 .is_local = local_clk_is_local,
498};
499
500static struct fixed_clk cxo_clk = {
501 .rate = 19200000,
502 .c = {
503 .dbg_name = "cxo_clk",
504 .ops = &clk_ops_cxo,
505 CLK_INIT(cxo_clk.c),
506 },
507};
508
509static struct pll_clk pll2_clk = {
510 .rate = 800000000,
511 .mode_reg = MM_PLL1_MODE_REG,
512 .parent = &pxo_clk.c,
513 .c = {
514 .dbg_name = "pll2_clk",
515 .ops = &clk_ops_pll,
516 CLK_INIT(pll2_clk.c),
517 },
518};
519
Stephen Boyd94625ef2011-07-12 17:06:01 -0700520static struct pll_clk pll3_clk = {
521 .rate = 1200000000,
522 .mode_reg = BB_MMCC_PLL2_MODE_REG,
523 .parent = &pxo_clk.c,
524 .c = {
525 .dbg_name = "pll3_clk",
526 .ops = &clk_ops_pll,
Matt Wagantallc57577d2011-10-06 17:06:53 -0700527 .vdd_class = &vdd_l23,
528 .fmax[VDD_L23_ON] = ULONG_MAX,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700529 CLK_INIT(pll3_clk.c),
530 },
531};
532
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700533static struct pll_vote_clk pll4_clk = {
534 .rate = 393216000,
535 .en_reg = BB_PLL_ENA_SC0_REG,
536 .en_mask = BIT(4),
537 .status_reg = LCC_PLL0_STATUS_REG,
538 .parent = &pxo_clk.c,
539 .c = {
540 .dbg_name = "pll4_clk",
541 .ops = &clk_ops_pll_vote,
542 CLK_INIT(pll4_clk.c),
543 },
544};
545
546static struct pll_vote_clk pll8_clk = {
547 .rate = 384000000,
548 .en_reg = BB_PLL_ENA_SC0_REG,
549 .en_mask = BIT(8),
550 .status_reg = BB_PLL8_STATUS_REG,
551 .parent = &pxo_clk.c,
552 .c = {
553 .dbg_name = "pll8_clk",
554 .ops = &clk_ops_pll_vote,
555 CLK_INIT(pll8_clk.c),
556 },
557};
558
Stephen Boyd94625ef2011-07-12 17:06:01 -0700559static struct pll_vote_clk pll14_clk = {
560 .rate = 480000000,
561 .en_reg = BB_PLL_ENA_SC0_REG,
562 .en_mask = BIT(14),
563 .status_reg = BB_PLL14_STATUS_REG,
564 .parent = &pxo_clk.c,
565 .c = {
566 .dbg_name = "pll14_clk",
567 .ops = &clk_ops_pll_vote,
568 CLK_INIT(pll14_clk.c),
569 },
570};
571
Tianyi Gou41515e22011-09-01 19:37:43 -0700572static struct pll_clk pll15_clk = {
573 .rate = 975000000,
574 .mode_reg = MM_PLL3_MODE_REG,
575 .parent = &pxo_clk.c,
576 .c = {
577 .dbg_name = "pll15_clk",
578 .ops = &clk_ops_pll,
579 CLK_INIT(pll15_clk.c),
580 },
581};
582
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700583static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700584 .enable = rcg_clk_enable,
585 .disable = rcg_clk_disable,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800586 .enable_hwcg = rcg_clk_enable_hwcg,
587 .disable_hwcg = rcg_clk_disable_hwcg,
588 .in_hwcg_mode = rcg_clk_in_hwcg_mode,
Matt Wagantall41af0772011-09-17 12:21:39 -0700589 .auto_off = rcg_clk_disable,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700590 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700591 .set_rate = rcg_clk_set_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700592 .get_rate = rcg_clk_get_rate,
593 .list_rate = rcg_clk_list_rate,
594 .is_enabled = rcg_clk_is_enabled,
595 .round_rate = rcg_clk_round_rate,
Stephen Boyd7bf28142011-12-07 00:30:52 -0800596 .reset = rcg_clk_reset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700597 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700598 .get_parent = rcg_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700599};
600
601static struct clk_ops clk_ops_branch = {
602 .enable = branch_clk_enable,
603 .disable = branch_clk_disable,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800604 .enable_hwcg = branch_clk_enable_hwcg,
605 .disable_hwcg = branch_clk_disable_hwcg,
606 .in_hwcg_mode = branch_clk_in_hwcg_mode,
Matt Wagantall41af0772011-09-17 12:21:39 -0700607 .auto_off = branch_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700608 .is_enabled = branch_clk_is_enabled,
609 .reset = branch_clk_reset,
610 .is_local = local_clk_is_local,
611 .get_parent = branch_clk_get_parent,
612 .set_parent = branch_clk_set_parent,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800613 .handoff = branch_clk_handoff,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700614};
615
616static struct clk_ops clk_ops_reset = {
617 .reset = branch_clk_reset,
618 .is_local = local_clk_is_local,
619};
620
621/* AXI Interfaces */
622static struct branch_clk gmem_axi_clk = {
623 .b = {
624 .ctl_reg = MAXI_EN_REG,
625 .en_mask = BIT(24),
626 .halt_reg = DBG_BUS_VEC_E_REG,
627 .halt_bit = 6,
628 },
629 .c = {
630 .dbg_name = "gmem_axi_clk",
631 .ops = &clk_ops_branch,
632 CLK_INIT(gmem_axi_clk.c),
633 },
634};
635
636static struct branch_clk ijpeg_axi_clk = {
637 .b = {
638 .ctl_reg = MAXI_EN_REG,
639 .en_mask = BIT(21),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800640 .hwcg_reg = MAXI_EN_REG,
641 .hwcg_mask = BIT(11),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700642 .reset_reg = SW_RESET_AXI_REG,
643 .reset_mask = BIT(14),
644 .halt_reg = DBG_BUS_VEC_E_REG,
645 .halt_bit = 4,
646 },
647 .c = {
648 .dbg_name = "ijpeg_axi_clk",
649 .ops = &clk_ops_branch,
650 CLK_INIT(ijpeg_axi_clk.c),
651 },
652};
653
654static struct branch_clk imem_axi_clk = {
655 .b = {
656 .ctl_reg = MAXI_EN_REG,
657 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800658 .hwcg_reg = MAXI_EN_REG,
659 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700660 .reset_reg = SW_RESET_CORE_REG,
661 .reset_mask = BIT(10),
662 .halt_reg = DBG_BUS_VEC_E_REG,
663 .halt_bit = 7,
664 },
665 .c = {
666 .dbg_name = "imem_axi_clk",
667 .ops = &clk_ops_branch,
668 CLK_INIT(imem_axi_clk.c),
669 },
670};
671
672static struct branch_clk jpegd_axi_clk = {
673 .b = {
674 .ctl_reg = MAXI_EN_REG,
675 .en_mask = BIT(25),
676 .halt_reg = DBG_BUS_VEC_E_REG,
677 .halt_bit = 5,
678 },
679 .c = {
680 .dbg_name = "jpegd_axi_clk",
681 .ops = &clk_ops_branch,
682 CLK_INIT(jpegd_axi_clk.c),
683 },
684};
685
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700686static struct branch_clk vcodec_axi_b_clk = {
687 .b = {
688 .ctl_reg = MAXI_EN4_REG,
689 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800690 .hwcg_reg = MAXI_EN4_REG,
691 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700692 .halt_reg = DBG_BUS_VEC_I_REG,
693 .halt_bit = 25,
694 },
695 .c = {
696 .dbg_name = "vcodec_axi_b_clk",
697 .ops = &clk_ops_branch,
698 CLK_INIT(vcodec_axi_b_clk.c),
699 },
700};
701
Matt Wagantall91f42702011-07-14 12:01:15 -0700702static struct branch_clk vcodec_axi_a_clk = {
703 .b = {
704 .ctl_reg = MAXI_EN4_REG,
705 .en_mask = BIT(25),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800706 .hwcg_reg = MAXI_EN4_REG,
707 .hwcg_mask = BIT(24),
Matt Wagantall91f42702011-07-14 12:01:15 -0700708 .halt_reg = DBG_BUS_VEC_I_REG,
709 .halt_bit = 26,
710 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700711 .c = {
712 .dbg_name = "vcodec_axi_a_clk",
713 .ops = &clk_ops_branch,
714 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700715 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700716 },
717};
718
719static struct branch_clk vcodec_axi_clk = {
720 .b = {
721 .ctl_reg = MAXI_EN_REG,
722 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800723 .hwcg_reg = MAXI_EN_REG,
724 .hwcg_mask = BIT(13),
Matt Wagantall91f42702011-07-14 12:01:15 -0700725 .reset_reg = SW_RESET_AXI_REG,
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -0800726 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700727 .halt_reg = DBG_BUS_VEC_E_REG,
728 .halt_bit = 3,
729 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700730 .c = {
731 .dbg_name = "vcodec_axi_clk",
732 .ops = &clk_ops_branch,
733 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700734 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700735 },
736};
737
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700738static struct branch_clk vfe_axi_clk = {
739 .b = {
740 .ctl_reg = MAXI_EN_REG,
741 .en_mask = BIT(18),
742 .reset_reg = SW_RESET_AXI_REG,
743 .reset_mask = BIT(9),
744 .halt_reg = DBG_BUS_VEC_E_REG,
745 .halt_bit = 0,
746 },
747 .c = {
748 .dbg_name = "vfe_axi_clk",
749 .ops = &clk_ops_branch,
750 CLK_INIT(vfe_axi_clk.c),
751 },
752};
753
754static struct branch_clk mdp_axi_clk = {
755 .b = {
756 .ctl_reg = MAXI_EN_REG,
757 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800758 .hwcg_reg = MAXI_EN_REG,
759 .hwcg_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700760 .reset_reg = SW_RESET_AXI_REG,
761 .reset_mask = BIT(13),
762 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700763 .halt_bit = 8,
764 },
765 .c = {
766 .dbg_name = "mdp_axi_clk",
767 .ops = &clk_ops_branch,
768 CLK_INIT(mdp_axi_clk.c),
769 },
770};
771
772static struct branch_clk rot_axi_clk = {
773 .b = {
774 .ctl_reg = MAXI_EN2_REG,
775 .en_mask = BIT(24),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800776 .hwcg_reg = MAXI_EN2_REG,
777 .hwcg_mask = BIT(25),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700778 .reset_reg = SW_RESET_AXI_REG,
779 .reset_mask = BIT(6),
780 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700781 .halt_bit = 2,
782 },
783 .c = {
784 .dbg_name = "rot_axi_clk",
785 .ops = &clk_ops_branch,
786 CLK_INIT(rot_axi_clk.c),
787 },
788};
789
790static struct branch_clk vpe_axi_clk = {
791 .b = {
792 .ctl_reg = MAXI_EN2_REG,
793 .en_mask = BIT(26),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800794 .hwcg_reg = MAXI_EN2_REG,
795 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700796 .reset_reg = SW_RESET_AXI_REG,
797 .reset_mask = BIT(15),
798 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700799 .halt_bit = 1,
800 },
801 .c = {
802 .dbg_name = "vpe_axi_clk",
803 .ops = &clk_ops_branch,
804 CLK_INIT(vpe_axi_clk.c),
805 },
806};
807
Tianyi Gou41515e22011-09-01 19:37:43 -0700808static struct branch_clk vcap_axi_clk = {
809 .b = {
810 .ctl_reg = MAXI_EN5_REG,
811 .en_mask = BIT(12),
812 .reset_reg = SW_RESET_AXI_REG,
813 .reset_mask = BIT(16),
814 .halt_reg = DBG_BUS_VEC_J_REG,
815 .halt_bit = 20,
816 },
817 .c = {
818 .dbg_name = "vcap_axi_clk",
819 .ops = &clk_ops_branch,
820 CLK_INIT(vcap_axi_clk.c),
821 },
822};
823
Tianyi Gou621f8742011-09-01 21:45:01 -0700824/* For 8064, gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
825static struct branch_clk gfx3d_axi_clk = {
826 .b = {
827 .ctl_reg = MAXI_EN5_REG,
828 .en_mask = BIT(25),
829 .reset_reg = SW_RESET_AXI_REG,
830 .reset_mask = BIT(17),
831 .halt_reg = DBG_BUS_VEC_J_REG,
832 .halt_bit = 30,
833 },
834 .c = {
835 .dbg_name = "gfx3d_axi_clk",
836 .ops = &clk_ops_branch,
837 CLK_INIT(gfx3d_axi_clk.c),
838 },
839};
840
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700841/* AHB Interfaces */
842static struct branch_clk amp_p_clk = {
843 .b = {
844 .ctl_reg = AHB_EN_REG,
845 .en_mask = BIT(24),
846 .halt_reg = DBG_BUS_VEC_F_REG,
847 .halt_bit = 18,
848 },
849 .c = {
850 .dbg_name = "amp_p_clk",
851 .ops = &clk_ops_branch,
852 CLK_INIT(amp_p_clk.c),
853 },
854};
855
Matt Wagantallc23eee92011-08-16 23:06:52 -0700856static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700857 .b = {
858 .ctl_reg = AHB_EN_REG,
859 .en_mask = BIT(7),
860 .reset_reg = SW_RESET_AHB_REG,
861 .reset_mask = BIT(17),
862 .halt_reg = DBG_BUS_VEC_F_REG,
863 .halt_bit = 16,
864 },
865 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700866 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700867 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700868 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700869 },
870};
871
872static struct branch_clk dsi1_m_p_clk = {
873 .b = {
874 .ctl_reg = AHB_EN_REG,
875 .en_mask = BIT(9),
876 .reset_reg = SW_RESET_AHB_REG,
877 .reset_mask = BIT(6),
878 .halt_reg = DBG_BUS_VEC_F_REG,
879 .halt_bit = 19,
880 },
881 .c = {
882 .dbg_name = "dsi1_m_p_clk",
883 .ops = &clk_ops_branch,
884 CLK_INIT(dsi1_m_p_clk.c),
885 },
886};
887
888static struct branch_clk dsi1_s_p_clk = {
889 .b = {
890 .ctl_reg = AHB_EN_REG,
891 .en_mask = BIT(18),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800892 .hwcg_reg = AHB_EN2_REG,
893 .hwcg_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700894 .reset_reg = SW_RESET_AHB_REG,
895 .reset_mask = BIT(5),
896 .halt_reg = DBG_BUS_VEC_F_REG,
897 .halt_bit = 21,
898 },
899 .c = {
900 .dbg_name = "dsi1_s_p_clk",
901 .ops = &clk_ops_branch,
902 CLK_INIT(dsi1_s_p_clk.c),
903 },
904};
905
906static struct branch_clk dsi2_m_p_clk = {
907 .b = {
908 .ctl_reg = AHB_EN_REG,
909 .en_mask = BIT(17),
910 .reset_reg = SW_RESET_AHB2_REG,
911 .reset_mask = BIT(1),
912 .halt_reg = DBG_BUS_VEC_E_REG,
913 .halt_bit = 18,
914 },
915 .c = {
916 .dbg_name = "dsi2_m_p_clk",
917 .ops = &clk_ops_branch,
918 CLK_INIT(dsi2_m_p_clk.c),
919 },
920};
921
922static struct branch_clk dsi2_s_p_clk = {
923 .b = {
924 .ctl_reg = AHB_EN_REG,
925 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800926 .hwcg_reg = AHB_EN2_REG,
927 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700928 .reset_reg = SW_RESET_AHB2_REG,
929 .reset_mask = BIT(0),
930 .halt_reg = DBG_BUS_VEC_F_REG,
931 .halt_bit = 20,
932 },
933 .c = {
934 .dbg_name = "dsi2_s_p_clk",
935 .ops = &clk_ops_branch,
936 CLK_INIT(dsi2_s_p_clk.c),
937 },
938};
939
940static struct branch_clk gfx2d0_p_clk = {
941 .b = {
942 .ctl_reg = AHB_EN_REG,
943 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800944 .hwcg_reg = AHB_EN2_REG,
945 .hwcg_mask = BIT(28),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700946 .reset_reg = SW_RESET_AHB_REG,
947 .reset_mask = BIT(12),
948 .halt_reg = DBG_BUS_VEC_F_REG,
949 .halt_bit = 2,
950 },
951 .c = {
952 .dbg_name = "gfx2d0_p_clk",
953 .ops = &clk_ops_branch,
954 CLK_INIT(gfx2d0_p_clk.c),
955 },
956};
957
958static struct branch_clk gfx2d1_p_clk = {
959 .b = {
960 .ctl_reg = AHB_EN_REG,
961 .en_mask = BIT(2),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800962 .hwcg_reg = AHB_EN2_REG,
963 .hwcg_mask = BIT(29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700964 .reset_reg = SW_RESET_AHB_REG,
965 .reset_mask = BIT(11),
966 .halt_reg = DBG_BUS_VEC_F_REG,
967 .halt_bit = 3,
968 },
969 .c = {
970 .dbg_name = "gfx2d1_p_clk",
971 .ops = &clk_ops_branch,
972 CLK_INIT(gfx2d1_p_clk.c),
973 },
974};
975
976static struct branch_clk gfx3d_p_clk = {
977 .b = {
978 .ctl_reg = AHB_EN_REG,
979 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800980 .hwcg_reg = AHB_EN2_REG,
981 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700982 .reset_reg = SW_RESET_AHB_REG,
983 .reset_mask = BIT(10),
984 .halt_reg = DBG_BUS_VEC_F_REG,
985 .halt_bit = 4,
986 },
987 .c = {
988 .dbg_name = "gfx3d_p_clk",
989 .ops = &clk_ops_branch,
990 CLK_INIT(gfx3d_p_clk.c),
991 },
992};
993
994static struct branch_clk hdmi_m_p_clk = {
995 .b = {
996 .ctl_reg = AHB_EN_REG,
997 .en_mask = BIT(14),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800998 .hwcg_reg = AHB_EN2_REG,
999 .hwcg_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001000 .reset_reg = SW_RESET_AHB_REG,
1001 .reset_mask = BIT(9),
1002 .halt_reg = DBG_BUS_VEC_F_REG,
1003 .halt_bit = 5,
1004 },
1005 .c = {
1006 .dbg_name = "hdmi_m_p_clk",
1007 .ops = &clk_ops_branch,
1008 CLK_INIT(hdmi_m_p_clk.c),
1009 },
1010};
1011
1012static struct branch_clk hdmi_s_p_clk = {
1013 .b = {
1014 .ctl_reg = AHB_EN_REG,
1015 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001016 .hwcg_reg = AHB_EN2_REG,
1017 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001018 .reset_reg = SW_RESET_AHB_REG,
1019 .reset_mask = BIT(9),
1020 .halt_reg = DBG_BUS_VEC_F_REG,
1021 .halt_bit = 6,
1022 },
1023 .c = {
1024 .dbg_name = "hdmi_s_p_clk",
1025 .ops = &clk_ops_branch,
1026 CLK_INIT(hdmi_s_p_clk.c),
1027 },
1028};
1029
1030static struct branch_clk ijpeg_p_clk = {
1031 .b = {
1032 .ctl_reg = AHB_EN_REG,
1033 .en_mask = BIT(5),
1034 .reset_reg = SW_RESET_AHB_REG,
1035 .reset_mask = BIT(7),
1036 .halt_reg = DBG_BUS_VEC_F_REG,
1037 .halt_bit = 9,
1038 },
1039 .c = {
1040 .dbg_name = "ijpeg_p_clk",
1041 .ops = &clk_ops_branch,
1042 CLK_INIT(ijpeg_p_clk.c),
1043 },
1044};
1045
1046static struct branch_clk imem_p_clk = {
1047 .b = {
1048 .ctl_reg = AHB_EN_REG,
1049 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001050 .hwcg_reg = AHB_EN2_REG,
1051 .hwcg_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001052 .reset_reg = SW_RESET_AHB_REG,
1053 .reset_mask = BIT(8),
1054 .halt_reg = DBG_BUS_VEC_F_REG,
1055 .halt_bit = 10,
1056 },
1057 .c = {
1058 .dbg_name = "imem_p_clk",
1059 .ops = &clk_ops_branch,
1060 CLK_INIT(imem_p_clk.c),
1061 },
1062};
1063
1064static struct branch_clk jpegd_p_clk = {
1065 .b = {
1066 .ctl_reg = AHB_EN_REG,
1067 .en_mask = BIT(21),
1068 .reset_reg = SW_RESET_AHB_REG,
1069 .reset_mask = BIT(4),
1070 .halt_reg = DBG_BUS_VEC_F_REG,
1071 .halt_bit = 7,
1072 },
1073 .c = {
1074 .dbg_name = "jpegd_p_clk",
1075 .ops = &clk_ops_branch,
1076 CLK_INIT(jpegd_p_clk.c),
1077 },
1078};
1079
1080static struct branch_clk mdp_p_clk = {
1081 .b = {
1082 .ctl_reg = AHB_EN_REG,
1083 .en_mask = BIT(10),
1084 .reset_reg = SW_RESET_AHB_REG,
1085 .reset_mask = BIT(3),
1086 .halt_reg = DBG_BUS_VEC_F_REG,
1087 .halt_bit = 11,
1088 },
1089 .c = {
1090 .dbg_name = "mdp_p_clk",
1091 .ops = &clk_ops_branch,
1092 CLK_INIT(mdp_p_clk.c),
1093 },
1094};
1095
1096static struct branch_clk rot_p_clk = {
1097 .b = {
1098 .ctl_reg = AHB_EN_REG,
1099 .en_mask = BIT(12),
1100 .reset_reg = SW_RESET_AHB_REG,
1101 .reset_mask = BIT(2),
1102 .halt_reg = DBG_BUS_VEC_F_REG,
1103 .halt_bit = 13,
1104 },
1105 .c = {
1106 .dbg_name = "rot_p_clk",
1107 .ops = &clk_ops_branch,
1108 CLK_INIT(rot_p_clk.c),
1109 },
1110};
1111
1112static struct branch_clk smmu_p_clk = {
1113 .b = {
1114 .ctl_reg = AHB_EN_REG,
1115 .en_mask = BIT(15),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001116 .hwcg_reg = AHB_EN_REG,
1117 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001118 .halt_reg = DBG_BUS_VEC_F_REG,
1119 .halt_bit = 22,
1120 },
1121 .c = {
1122 .dbg_name = "smmu_p_clk",
1123 .ops = &clk_ops_branch,
1124 CLK_INIT(smmu_p_clk.c),
1125 },
1126};
1127
1128static struct branch_clk tv_enc_p_clk = {
1129 .b = {
1130 .ctl_reg = AHB_EN_REG,
1131 .en_mask = BIT(25),
1132 .reset_reg = SW_RESET_AHB_REG,
1133 .reset_mask = BIT(15),
1134 .halt_reg = DBG_BUS_VEC_F_REG,
1135 .halt_bit = 23,
1136 },
1137 .c = {
1138 .dbg_name = "tv_enc_p_clk",
1139 .ops = &clk_ops_branch,
1140 CLK_INIT(tv_enc_p_clk.c),
1141 },
1142};
1143
1144static struct branch_clk vcodec_p_clk = {
1145 .b = {
1146 .ctl_reg = AHB_EN_REG,
1147 .en_mask = BIT(11),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001148 .hwcg_reg = AHB_EN2_REG,
1149 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001150 .reset_reg = SW_RESET_AHB_REG,
1151 .reset_mask = BIT(1),
1152 .halt_reg = DBG_BUS_VEC_F_REG,
1153 .halt_bit = 12,
1154 },
1155 .c = {
1156 .dbg_name = "vcodec_p_clk",
1157 .ops = &clk_ops_branch,
1158 CLK_INIT(vcodec_p_clk.c),
1159 },
1160};
1161
1162static struct branch_clk vfe_p_clk = {
1163 .b = {
1164 .ctl_reg = AHB_EN_REG,
1165 .en_mask = BIT(13),
1166 .reset_reg = SW_RESET_AHB_REG,
1167 .reset_mask = BIT(0),
1168 .halt_reg = DBG_BUS_VEC_F_REG,
1169 .halt_bit = 14,
1170 },
1171 .c = {
1172 .dbg_name = "vfe_p_clk",
1173 .ops = &clk_ops_branch,
1174 CLK_INIT(vfe_p_clk.c),
1175 },
1176};
1177
1178static struct branch_clk vpe_p_clk = {
1179 .b = {
1180 .ctl_reg = AHB_EN_REG,
1181 .en_mask = BIT(16),
1182 .reset_reg = SW_RESET_AHB_REG,
1183 .reset_mask = BIT(14),
1184 .halt_reg = DBG_BUS_VEC_F_REG,
1185 .halt_bit = 15,
1186 },
1187 .c = {
1188 .dbg_name = "vpe_p_clk",
1189 .ops = &clk_ops_branch,
1190 CLK_INIT(vpe_p_clk.c),
1191 },
1192};
1193
Tianyi Gou41515e22011-09-01 19:37:43 -07001194static struct branch_clk vcap_p_clk = {
1195 .b = {
1196 .ctl_reg = AHB_EN3_REG,
1197 .en_mask = BIT(1),
1198 .reset_reg = SW_RESET_AHB2_REG,
1199 .reset_mask = BIT(2),
1200 .halt_reg = DBG_BUS_VEC_J_REG,
1201 .halt_bit = 23,
1202 },
1203 .c = {
1204 .dbg_name = "vcap_p_clk",
1205 .ops = &clk_ops_branch,
1206 CLK_INIT(vcap_p_clk.c),
1207 },
1208};
1209
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001210/*
1211 * Peripheral Clocks
1212 */
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001213#define CLK_GP(i, n, h_r, h_b) \
1214 struct rcg_clk i##_clk = { \
1215 .b = { \
1216 .ctl_reg = GPn_NS_REG(n), \
1217 .en_mask = BIT(9), \
1218 .halt_reg = h_r, \
1219 .halt_bit = h_b, \
1220 }, \
1221 .ns_reg = GPn_NS_REG(n), \
1222 .md_reg = GPn_MD_REG(n), \
1223 .root_en_mask = BIT(11), \
1224 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1225 .set_rate = set_rate_mnd, \
1226 .freq_tbl = clk_tbl_gp, \
1227 .current_freq = &rcg_dummy_freq, \
1228 .c = { \
1229 .dbg_name = #i "_clk", \
1230 .ops = &clk_ops_rcg_8960, \
1231 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
1232 CLK_INIT(i##_clk.c), \
1233 }, \
1234 }
1235#define F_GP(f, s, d, m, n) \
1236 { \
1237 .freq_hz = f, \
1238 .src_clk = &s##_clk.c, \
1239 .md_val = MD8(16, m, 0, n), \
1240 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1241 .mnd_en_mask = BIT(8) * !!(n), \
1242 }
1243static struct clk_freq_tbl clk_tbl_gp[] = {
1244 F_GP( 0, gnd, 1, 0, 0),
1245 F_GP( 9600000, cxo, 2, 0, 0),
1246 F_GP( 13500000, pxo, 2, 0, 0),
1247 F_GP( 19200000, cxo, 1, 0, 0),
1248 F_GP( 27000000, pxo, 1, 0, 0),
1249 F_GP( 64000000, pll8, 2, 1, 3),
1250 F_GP( 76800000, pll8, 1, 1, 5),
1251 F_GP( 96000000, pll8, 4, 0, 0),
1252 F_GP(128000000, pll8, 3, 0, 0),
1253 F_GP(192000000, pll8, 2, 0, 0),
1254 F_GP(384000000, pll8, 1, 0, 0),
1255 F_END
1256};
1257
1258static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
1259static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
1260static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
1261
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001262#define CLK_GSBI_UART(i, n, h_r, h_b) \
1263 struct rcg_clk i##_clk = { \
1264 .b = { \
1265 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1266 .en_mask = BIT(9), \
1267 .reset_reg = GSBIn_RESET_REG(n), \
1268 .reset_mask = BIT(0), \
1269 .halt_reg = h_r, \
1270 .halt_bit = h_b, \
1271 }, \
1272 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1273 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1274 .root_en_mask = BIT(11), \
1275 .ns_mask = (BM(31, 16) | BM(6, 0)), \
1276 .set_rate = set_rate_mnd, \
1277 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001278 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001279 .c = { \
1280 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001281 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001282 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001283 CLK_INIT(i##_clk.c), \
1284 }, \
1285 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001286#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001287 { \
1288 .freq_hz = f, \
1289 .src_clk = &s##_clk.c, \
1290 .md_val = MD16(m, n), \
1291 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1292 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001293 }
1294static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001295 F_GSBI_UART( 0, gnd, 1, 0, 0),
Matt Wagantall9a561f72012-01-19 16:13:12 -08001296 F_GSBI_UART( 1843200, pll8, 2, 6, 625),
1297 F_GSBI_UART( 3686400, pll8, 2, 12, 625),
1298 F_GSBI_UART( 7372800, pll8, 2, 24, 625),
1299 F_GSBI_UART(14745600, pll8, 2, 48, 625),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001300 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1301 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1302 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1303 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1304 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1305 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1306 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1307 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1308 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1309 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001310 F_END
1311};
1312
1313static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1314static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1315static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1316static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1317static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1318static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1319static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1320static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1321static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1322static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1323static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1324static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1325
1326#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1327 struct rcg_clk i##_clk = { \
1328 .b = { \
1329 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1330 .en_mask = BIT(9), \
1331 .reset_reg = GSBIn_RESET_REG(n), \
1332 .reset_mask = BIT(0), \
1333 .halt_reg = h_r, \
1334 .halt_bit = h_b, \
1335 }, \
1336 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1337 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1338 .root_en_mask = BIT(11), \
1339 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1340 .set_rate = set_rate_mnd, \
1341 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001342 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001343 .c = { \
1344 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001345 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001346 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001347 CLK_INIT(i##_clk.c), \
1348 }, \
1349 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001350#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001351 { \
1352 .freq_hz = f, \
1353 .src_clk = &s##_clk.c, \
1354 .md_val = MD8(16, m, 0, n), \
1355 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1356 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001357 }
1358static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001359 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1360 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1361 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1362 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1363 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1364 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1365 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1366 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1367 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1368 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001369 F_END
1370};
1371
1372static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1373static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1374static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1375static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1376static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1377static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1378static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1379static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1380static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1381static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1382static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1383static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1384
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001385#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001386 { \
1387 .freq_hz = f, \
1388 .src_clk = &s##_clk.c, \
1389 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001390 }
1391static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001392 F_PDM( 0, gnd, 1),
1393 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001394 F_END
1395};
1396
1397static struct rcg_clk pdm_clk = {
1398 .b = {
1399 .ctl_reg = PDM_CLK_NS_REG,
1400 .en_mask = BIT(9),
1401 .reset_reg = PDM_CLK_NS_REG,
1402 .reset_mask = BIT(12),
1403 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1404 .halt_bit = 3,
1405 },
1406 .ns_reg = PDM_CLK_NS_REG,
1407 .root_en_mask = BIT(11),
1408 .ns_mask = BM(1, 0),
1409 .set_rate = set_rate_nop,
1410 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001411 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001412 .c = {
1413 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001414 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001415 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001416 CLK_INIT(pdm_clk.c),
1417 },
1418};
1419
1420static struct branch_clk pmem_clk = {
1421 .b = {
1422 .ctl_reg = PMEM_ACLK_CTL_REG,
1423 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001424 .hwcg_reg = PMEM_ACLK_CTL_REG,
1425 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001426 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1427 .halt_bit = 20,
1428 },
1429 .c = {
1430 .dbg_name = "pmem_clk",
1431 .ops = &clk_ops_branch,
1432 CLK_INIT(pmem_clk.c),
1433 },
1434};
1435
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001436#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001437 { \
1438 .freq_hz = f, \
1439 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001440 }
1441static struct clk_freq_tbl clk_tbl_prng[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001442 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001443 F_END
1444};
1445
1446static struct rcg_clk prng_clk = {
1447 .b = {
1448 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1449 .en_mask = BIT(10),
1450 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1451 .halt_check = HALT_VOTED,
1452 .halt_bit = 10,
1453 },
1454 .set_rate = set_rate_nop,
1455 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001456 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001457 .c = {
1458 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001459 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001460 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001461 CLK_INIT(prng_clk.c),
1462 },
1463};
1464
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001465#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001466 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001467 .b = { \
1468 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1469 .en_mask = BIT(9), \
1470 .reset_reg = SDCn_RESET_REG(n), \
1471 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001472 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001473 .halt_bit = h_b, \
1474 }, \
1475 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1476 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1477 .root_en_mask = BIT(11), \
1478 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1479 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001480 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001481 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001482 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001483 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001484 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001485 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001486 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001487 }, \
1488 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001489#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001490 { \
1491 .freq_hz = f, \
1492 .src_clk = &s##_clk.c, \
1493 .md_val = MD8(16, m, 0, n), \
1494 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1495 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001496 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001497static struct clk_freq_tbl clk_tbl_sdc[] = {
1498 F_SDC( 0, gnd, 1, 0, 0),
1499 F_SDC( 144000, pxo, 3, 2, 125),
1500 F_SDC( 400000, pll8, 4, 1, 240),
1501 F_SDC( 16000000, pll8, 4, 1, 6),
1502 F_SDC( 17070000, pll8, 1, 2, 45),
1503 F_SDC( 20210000, pll8, 1, 1, 19),
1504 F_SDC( 24000000, pll8, 4, 1, 4),
1505 F_SDC( 48000000, pll8, 4, 1, 2),
1506 F_SDC( 64000000, pll8, 3, 1, 2),
1507 F_SDC( 96000000, pll8, 4, 0, 0),
Subhash Jadavanibd238ba2011-11-24 15:12:39 +05301508 F_SDC(192000000, pll8, 2, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001509 F_END
1510};
1511
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001512static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1513static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1514static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1515static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1516static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001517
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001518#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001519 { \
1520 .freq_hz = f, \
1521 .src_clk = &s##_clk.c, \
1522 .md_val = MD16(m, n), \
1523 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1524 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001525 }
1526static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001527 F_TSIF_REF( 0, gnd, 1, 0, 0),
1528 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001529 F_END
1530};
1531
1532static struct rcg_clk tsif_ref_clk = {
1533 .b = {
1534 .ctl_reg = TSIF_REF_CLK_NS_REG,
1535 .en_mask = BIT(9),
1536 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1537 .halt_bit = 5,
1538 },
1539 .ns_reg = TSIF_REF_CLK_NS_REG,
1540 .md_reg = TSIF_REF_CLK_MD_REG,
1541 .root_en_mask = BIT(11),
1542 .ns_mask = (BM(31, 16) | BM(6, 0)),
1543 .set_rate = set_rate_mnd,
1544 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001545 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001546 .c = {
1547 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001548 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001549 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001550 CLK_INIT(tsif_ref_clk.c),
1551 },
1552};
1553
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001554#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001555 { \
1556 .freq_hz = f, \
1557 .src_clk = &s##_clk.c, \
1558 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001559 }
1560static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001561 F_TSSC( 0, gnd),
1562 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001563 F_END
1564};
1565
1566static struct rcg_clk tssc_clk = {
1567 .b = {
1568 .ctl_reg = TSSC_CLK_CTL_REG,
1569 .en_mask = BIT(4),
1570 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1571 .halt_bit = 4,
1572 },
1573 .ns_reg = TSSC_CLK_CTL_REG,
1574 .ns_mask = BM(1, 0),
1575 .set_rate = set_rate_nop,
1576 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001577 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001578 .c = {
1579 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001580 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001581 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001582 CLK_INIT(tssc_clk.c),
1583 },
1584};
1585
Tianyi Gou41515e22011-09-01 19:37:43 -07001586#define CLK_USB_HS(name, n, h_b) \
1587 static struct rcg_clk name = { \
1588 .b = { \
1589 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1590 .en_mask = BIT(9), \
1591 .reset_reg = USB_HS##n##_RESET_REG, \
1592 .reset_mask = BIT(0), \
1593 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1594 .halt_bit = h_b, \
1595 }, \
1596 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1597 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1598 .root_en_mask = BIT(11), \
1599 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1600 .set_rate = set_rate_mnd, \
1601 .freq_tbl = clk_tbl_usb, \
1602 .current_freq = &rcg_dummy_freq, \
1603 .c = { \
1604 .dbg_name = #name, \
1605 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001606 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001607 CLK_INIT(name.c), \
1608 }, \
1609}
1610
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001611#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001612 { \
1613 .freq_hz = f, \
1614 .src_clk = &s##_clk.c, \
1615 .md_val = MD8(16, m, 0, n), \
1616 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1617 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001618 }
1619static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001620 F_USB( 0, gnd, 1, 0, 0),
1621 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001622 F_END
1623};
1624
Tianyi Gou41515e22011-09-01 19:37:43 -07001625CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1626CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1627CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001628
Stephen Boyd94625ef2011-07-12 17:06:01 -07001629static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001630 F_USB( 0, gnd, 1, 0, 0),
1631 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001632 F_END
1633};
1634
1635static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1636 .b = {
1637 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1638 .en_mask = BIT(9),
1639 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1640 .halt_bit = 26,
1641 },
1642 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1643 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1644 .root_en_mask = BIT(11),
1645 .ns_mask = (BM(23, 16) | BM(6, 0)),
1646 .set_rate = set_rate_mnd,
1647 .freq_tbl = clk_tbl_usb_hsic,
1648 .current_freq = &rcg_dummy_freq,
1649 .c = {
1650 .dbg_name = "usb_hsic_xcvr_fs_clk",
1651 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001652 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001653 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1654 },
1655};
1656
1657static struct branch_clk usb_hsic_system_clk = {
1658 .b = {
1659 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1660 .en_mask = BIT(4),
1661 .reset_reg = USB_HSIC_RESET_REG,
1662 .reset_mask = BIT(0),
1663 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1664 .halt_bit = 24,
1665 },
1666 .parent = &usb_hsic_xcvr_fs_clk.c,
1667 .c = {
1668 .dbg_name = "usb_hsic_system_clk",
1669 .ops = &clk_ops_branch,
1670 CLK_INIT(usb_hsic_system_clk.c),
1671 },
1672};
1673
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001674#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001675 { \
1676 .freq_hz = f, \
1677 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001678 }
1679static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001680 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001681 F_END
1682};
1683
1684static struct rcg_clk usb_hsic_hsic_src_clk = {
1685 .b = {
1686 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1687 .halt_check = NOCHECK,
1688 },
1689 .root_en_mask = BIT(0),
1690 .set_rate = set_rate_nop,
1691 .freq_tbl = clk_tbl_usb2_hsic,
1692 .current_freq = &rcg_dummy_freq,
1693 .c = {
1694 .dbg_name = "usb_hsic_hsic_src_clk",
1695 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001696 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001697 CLK_INIT(usb_hsic_hsic_src_clk.c),
1698 },
1699};
1700
1701static struct branch_clk usb_hsic_hsic_clk = {
1702 .b = {
1703 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1704 .en_mask = BIT(0),
1705 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1706 .halt_bit = 19,
1707 },
1708 .parent = &usb_hsic_hsic_src_clk.c,
1709 .c = {
1710 .dbg_name = "usb_hsic_hsic_clk",
1711 .ops = &clk_ops_branch,
1712 CLK_INIT(usb_hsic_hsic_clk.c),
1713 },
1714};
1715
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001716#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001717 { \
1718 .freq_hz = f, \
1719 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001720 }
1721static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001722 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001723 F_END
1724};
1725
1726static struct rcg_clk usb_hsic_hsio_cal_clk = {
1727 .b = {
1728 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1729 .en_mask = BIT(0),
1730 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1731 .halt_bit = 23,
1732 },
1733 .set_rate = set_rate_nop,
1734 .freq_tbl = clk_tbl_usb_hsio_cal,
1735 .current_freq = &rcg_dummy_freq,
1736 .c = {
1737 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyda0e82ec2011-09-19 12:18:45 -07001738 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001739 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001740 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1741 },
1742};
1743
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001744static struct branch_clk usb_phy0_clk = {
1745 .b = {
1746 .reset_reg = USB_PHY0_RESET_REG,
1747 .reset_mask = BIT(0),
1748 },
1749 .c = {
1750 .dbg_name = "usb_phy0_clk",
1751 .ops = &clk_ops_reset,
1752 CLK_INIT(usb_phy0_clk.c),
1753 },
1754};
1755
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001756#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001757 struct rcg_clk i##_clk = { \
1758 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1759 .b = { \
1760 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1761 .halt_check = NOCHECK, \
1762 }, \
1763 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1764 .root_en_mask = BIT(11), \
1765 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1766 .set_rate = set_rate_mnd, \
1767 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001768 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001769 .c = { \
1770 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001771 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001772 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001773 CLK_INIT(i##_clk.c), \
1774 }, \
1775 }
1776
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001777static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001778static struct branch_clk usb_fs1_xcvr_clk = {
1779 .b = {
1780 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1781 .en_mask = BIT(9),
1782 .reset_reg = USB_FSn_RESET_REG(1),
1783 .reset_mask = BIT(1),
1784 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1785 .halt_bit = 15,
1786 },
1787 .parent = &usb_fs1_src_clk.c,
1788 .c = {
1789 .dbg_name = "usb_fs1_xcvr_clk",
1790 .ops = &clk_ops_branch,
1791 CLK_INIT(usb_fs1_xcvr_clk.c),
1792 },
1793};
1794
1795static struct branch_clk usb_fs1_sys_clk = {
1796 .b = {
1797 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1798 .en_mask = BIT(4),
1799 .reset_reg = USB_FSn_RESET_REG(1),
1800 .reset_mask = BIT(0),
1801 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1802 .halt_bit = 16,
1803 },
1804 .parent = &usb_fs1_src_clk.c,
1805 .c = {
1806 .dbg_name = "usb_fs1_sys_clk",
1807 .ops = &clk_ops_branch,
1808 CLK_INIT(usb_fs1_sys_clk.c),
1809 },
1810};
1811
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001812static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001813static struct branch_clk usb_fs2_xcvr_clk = {
1814 .b = {
1815 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1816 .en_mask = BIT(9),
1817 .reset_reg = USB_FSn_RESET_REG(2),
1818 .reset_mask = BIT(1),
1819 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1820 .halt_bit = 12,
1821 },
1822 .parent = &usb_fs2_src_clk.c,
1823 .c = {
1824 .dbg_name = "usb_fs2_xcvr_clk",
1825 .ops = &clk_ops_branch,
1826 CLK_INIT(usb_fs2_xcvr_clk.c),
1827 },
1828};
1829
1830static struct branch_clk usb_fs2_sys_clk = {
1831 .b = {
1832 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1833 .en_mask = BIT(4),
1834 .reset_reg = USB_FSn_RESET_REG(2),
1835 .reset_mask = BIT(0),
1836 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1837 .halt_bit = 13,
1838 },
1839 .parent = &usb_fs2_src_clk.c,
1840 .c = {
1841 .dbg_name = "usb_fs2_sys_clk",
1842 .ops = &clk_ops_branch,
1843 CLK_INIT(usb_fs2_sys_clk.c),
1844 },
1845};
1846
1847/* Fast Peripheral Bus Clocks */
1848static struct branch_clk ce1_core_clk = {
1849 .b = {
1850 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1851 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001852 .hwcg_reg = CE1_CORE_CLK_CTL_REG,
1853 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001854 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1855 .halt_bit = 27,
1856 },
1857 .c = {
1858 .dbg_name = "ce1_core_clk",
1859 .ops = &clk_ops_branch,
1860 CLK_INIT(ce1_core_clk.c),
1861 },
1862};
Tianyi Gou41515e22011-09-01 19:37:43 -07001863
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001864static struct branch_clk ce1_p_clk = {
1865 .b = {
1866 .ctl_reg = CE1_HCLK_CTL_REG,
1867 .en_mask = BIT(4),
1868 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1869 .halt_bit = 1,
1870 },
1871 .c = {
1872 .dbg_name = "ce1_p_clk",
1873 .ops = &clk_ops_branch,
1874 CLK_INIT(ce1_p_clk.c),
1875 },
1876};
1877
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001878#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07001879 { \
1880 .freq_hz = f, \
1881 .src_clk = &s##_clk.c, \
1882 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001883 }
1884
1885static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001886 F_CE3( 0, gnd, 1),
1887 F_CE3( 48000000, pll8, 8),
1888 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07001889 F_END
1890};
1891
1892static struct rcg_clk ce3_src_clk = {
1893 .b = {
1894 .ctl_reg = CE3_CLK_SRC_NS_REG,
1895 .halt_check = NOCHECK,
1896 },
1897 .ns_reg = CE3_CLK_SRC_NS_REG,
1898 .root_en_mask = BIT(7),
1899 .ns_mask = BM(6, 0),
1900 .set_rate = set_rate_nop,
1901 .freq_tbl = clk_tbl_ce3,
1902 .current_freq = &rcg_dummy_freq,
1903 .c = {
1904 .dbg_name = "ce3_src_clk",
1905 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001906 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07001907 CLK_INIT(ce3_src_clk.c),
1908 },
1909};
1910
1911static struct branch_clk ce3_core_clk = {
1912 .b = {
1913 .ctl_reg = CE3_CORE_CLK_CTL_REG,
1914 .en_mask = BIT(4),
1915 .reset_reg = CE3_CORE_CLK_CTL_REG,
1916 .reset_mask = BIT(7),
1917 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1918 .halt_bit = 5,
1919 },
1920 .parent = &ce3_src_clk.c,
1921 .c = {
1922 .dbg_name = "ce3_core_clk",
1923 .ops = &clk_ops_branch,
1924 CLK_INIT(ce3_core_clk.c),
1925 }
1926};
1927
1928static struct branch_clk ce3_p_clk = {
1929 .b = {
1930 .ctl_reg = CE3_HCLK_CTL_REG,
1931 .en_mask = BIT(4),
1932 .reset_reg = CE3_HCLK_CTL_REG,
1933 .reset_mask = BIT(7),
1934 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1935 .halt_bit = 16,
1936 },
1937 .parent = &ce3_src_clk.c,
1938 .c = {
1939 .dbg_name = "ce3_p_clk",
1940 .ops = &clk_ops_branch,
1941 CLK_INIT(ce3_p_clk.c),
1942 }
1943};
1944
1945static struct branch_clk sata_phy_ref_clk = {
1946 .b = {
1947 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
1948 .en_mask = BIT(4),
1949 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1950 .halt_bit = 24,
1951 },
1952 .parent = &pxo_clk.c,
1953 .c = {
1954 .dbg_name = "sata_phy_ref_clk",
1955 .ops = &clk_ops_branch,
1956 CLK_INIT(sata_phy_ref_clk.c),
1957 },
1958};
1959
1960static struct branch_clk pcie_p_clk = {
1961 .b = {
1962 .ctl_reg = PCIE_HCLK_CTL_REG,
1963 .en_mask = BIT(4),
1964 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1965 .halt_bit = 8,
1966 },
1967 .c = {
1968 .dbg_name = "pcie_p_clk",
1969 .ops = &clk_ops_branch,
1970 CLK_INIT(pcie_p_clk.c),
1971 },
1972};
1973
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001974static struct branch_clk dma_bam_p_clk = {
1975 .b = {
1976 .ctl_reg = DMA_BAM_HCLK_CTL,
1977 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001978 .hwcg_reg = DMA_BAM_HCLK_CTL,
1979 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001980 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1981 .halt_bit = 12,
1982 },
1983 .c = {
1984 .dbg_name = "dma_bam_p_clk",
1985 .ops = &clk_ops_branch,
1986 CLK_INIT(dma_bam_p_clk.c),
1987 },
1988};
1989
1990static struct branch_clk gsbi1_p_clk = {
1991 .b = {
1992 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
1993 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001994 .hwcg_reg = GSBIn_HCLK_CTL_REG(1),
1995 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001996 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1997 .halt_bit = 11,
1998 },
1999 .c = {
2000 .dbg_name = "gsbi1_p_clk",
2001 .ops = &clk_ops_branch,
2002 CLK_INIT(gsbi1_p_clk.c),
2003 },
2004};
2005
2006static struct branch_clk gsbi2_p_clk = {
2007 .b = {
2008 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2009 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002010 .hwcg_reg = GSBIn_HCLK_CTL_REG(2),
2011 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002012 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2013 .halt_bit = 7,
2014 },
2015 .c = {
2016 .dbg_name = "gsbi2_p_clk",
2017 .ops = &clk_ops_branch,
2018 CLK_INIT(gsbi2_p_clk.c),
2019 },
2020};
2021
2022static struct branch_clk gsbi3_p_clk = {
2023 .b = {
2024 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2025 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002026 .hwcg_reg = GSBIn_HCLK_CTL_REG(3),
2027 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002028 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2029 .halt_bit = 3,
2030 },
2031 .c = {
2032 .dbg_name = "gsbi3_p_clk",
2033 .ops = &clk_ops_branch,
2034 CLK_INIT(gsbi3_p_clk.c),
2035 },
2036};
2037
2038static struct branch_clk gsbi4_p_clk = {
2039 .b = {
2040 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2041 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002042 .hwcg_reg = GSBIn_HCLK_CTL_REG(4),
2043 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002044 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2045 .halt_bit = 27,
2046 },
2047 .c = {
2048 .dbg_name = "gsbi4_p_clk",
2049 .ops = &clk_ops_branch,
2050 CLK_INIT(gsbi4_p_clk.c),
2051 },
2052};
2053
2054static struct branch_clk gsbi5_p_clk = {
2055 .b = {
2056 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2057 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002058 .hwcg_reg = GSBIn_HCLK_CTL_REG(5),
2059 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002060 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2061 .halt_bit = 23,
2062 },
2063 .c = {
2064 .dbg_name = "gsbi5_p_clk",
2065 .ops = &clk_ops_branch,
2066 CLK_INIT(gsbi5_p_clk.c),
2067 },
2068};
2069
2070static struct branch_clk gsbi6_p_clk = {
2071 .b = {
2072 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2073 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002074 .hwcg_reg = GSBIn_HCLK_CTL_REG(6),
2075 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002076 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2077 .halt_bit = 19,
2078 },
2079 .c = {
2080 .dbg_name = "gsbi6_p_clk",
2081 .ops = &clk_ops_branch,
2082 CLK_INIT(gsbi6_p_clk.c),
2083 },
2084};
2085
2086static struct branch_clk gsbi7_p_clk = {
2087 .b = {
2088 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2089 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002090 .hwcg_reg = GSBIn_HCLK_CTL_REG(7),
2091 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002092 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2093 .halt_bit = 15,
2094 },
2095 .c = {
2096 .dbg_name = "gsbi7_p_clk",
2097 .ops = &clk_ops_branch,
2098 CLK_INIT(gsbi7_p_clk.c),
2099 },
2100};
2101
2102static struct branch_clk gsbi8_p_clk = {
2103 .b = {
2104 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2105 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002106 .hwcg_reg = GSBIn_HCLK_CTL_REG(8),
2107 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002108 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2109 .halt_bit = 11,
2110 },
2111 .c = {
2112 .dbg_name = "gsbi8_p_clk",
2113 .ops = &clk_ops_branch,
2114 CLK_INIT(gsbi8_p_clk.c),
2115 },
2116};
2117
2118static struct branch_clk gsbi9_p_clk = {
2119 .b = {
2120 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2121 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002122 .hwcg_reg = GSBIn_HCLK_CTL_REG(9),
2123 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002124 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2125 .halt_bit = 7,
2126 },
2127 .c = {
2128 .dbg_name = "gsbi9_p_clk",
2129 .ops = &clk_ops_branch,
2130 CLK_INIT(gsbi9_p_clk.c),
2131 },
2132};
2133
2134static struct branch_clk gsbi10_p_clk = {
2135 .b = {
2136 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2137 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002138 .hwcg_reg = GSBIn_HCLK_CTL_REG(10),
2139 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002140 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2141 .halt_bit = 3,
2142 },
2143 .c = {
2144 .dbg_name = "gsbi10_p_clk",
2145 .ops = &clk_ops_branch,
2146 CLK_INIT(gsbi10_p_clk.c),
2147 },
2148};
2149
2150static struct branch_clk gsbi11_p_clk = {
2151 .b = {
2152 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2153 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002154 .hwcg_reg = GSBIn_HCLK_CTL_REG(11),
2155 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002156 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2157 .halt_bit = 18,
2158 },
2159 .c = {
2160 .dbg_name = "gsbi11_p_clk",
2161 .ops = &clk_ops_branch,
2162 CLK_INIT(gsbi11_p_clk.c),
2163 },
2164};
2165
2166static struct branch_clk gsbi12_p_clk = {
2167 .b = {
2168 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2169 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002170 .hwcg_reg = GSBIn_HCLK_CTL_REG(12),
2171 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002172 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2173 .halt_bit = 14,
2174 },
2175 .c = {
2176 .dbg_name = "gsbi12_p_clk",
2177 .ops = &clk_ops_branch,
2178 CLK_INIT(gsbi12_p_clk.c),
2179 },
2180};
2181
Tianyi Gou41515e22011-09-01 19:37:43 -07002182static struct branch_clk sata_phy_cfg_clk = {
2183 .b = {
2184 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2185 .en_mask = BIT(4),
2186 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2187 .halt_bit = 12,
2188 },
2189 .c = {
2190 .dbg_name = "sata_phy_cfg_clk",
2191 .ops = &clk_ops_branch,
2192 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002193 },
2194};
2195
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002196static struct branch_clk tsif_p_clk = {
2197 .b = {
2198 .ctl_reg = TSIF_HCLK_CTL_REG,
2199 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002200 .hwcg_reg = TSIF_HCLK_CTL_REG,
2201 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002202 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2203 .halt_bit = 7,
2204 },
2205 .c = {
2206 .dbg_name = "tsif_p_clk",
2207 .ops = &clk_ops_branch,
2208 CLK_INIT(tsif_p_clk.c),
2209 },
2210};
2211
2212static struct branch_clk usb_fs1_p_clk = {
2213 .b = {
2214 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2215 .en_mask = BIT(4),
2216 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2217 .halt_bit = 17,
2218 },
2219 .c = {
2220 .dbg_name = "usb_fs1_p_clk",
2221 .ops = &clk_ops_branch,
2222 CLK_INIT(usb_fs1_p_clk.c),
2223 },
2224};
2225
2226static struct branch_clk usb_fs2_p_clk = {
2227 .b = {
2228 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2229 .en_mask = BIT(4),
2230 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2231 .halt_bit = 14,
2232 },
2233 .c = {
2234 .dbg_name = "usb_fs2_p_clk",
2235 .ops = &clk_ops_branch,
2236 CLK_INIT(usb_fs2_p_clk.c),
2237 },
2238};
2239
2240static struct branch_clk usb_hs1_p_clk = {
2241 .b = {
2242 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2243 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002244 .hwcg_reg = USB_HS1_HCLK_CTL_REG,
2245 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002246 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2247 .halt_bit = 1,
2248 },
2249 .c = {
2250 .dbg_name = "usb_hs1_p_clk",
2251 .ops = &clk_ops_branch,
2252 CLK_INIT(usb_hs1_p_clk.c),
2253 },
2254};
2255
Tianyi Gou41515e22011-09-01 19:37:43 -07002256static struct branch_clk usb_hs3_p_clk = {
2257 .b = {
2258 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2259 .en_mask = BIT(4),
2260 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2261 .halt_bit = 31,
2262 },
2263 .c = {
2264 .dbg_name = "usb_hs3_p_clk",
2265 .ops = &clk_ops_branch,
2266 CLK_INIT(usb_hs3_p_clk.c),
2267 },
2268};
2269
2270static struct branch_clk usb_hs4_p_clk = {
2271 .b = {
2272 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2273 .en_mask = BIT(4),
2274 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2275 .halt_bit = 7,
2276 },
2277 .c = {
2278 .dbg_name = "usb_hs4_p_clk",
2279 .ops = &clk_ops_branch,
2280 CLK_INIT(usb_hs4_p_clk.c),
2281 },
2282};
2283
Stephen Boyd94625ef2011-07-12 17:06:01 -07002284static struct branch_clk usb_hsic_p_clk = {
2285 .b = {
2286 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2287 .en_mask = BIT(4),
2288 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2289 .halt_bit = 28,
2290 },
2291 .c = {
2292 .dbg_name = "usb_hsic_p_clk",
2293 .ops = &clk_ops_branch,
2294 CLK_INIT(usb_hsic_p_clk.c),
2295 },
2296};
2297
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002298static struct branch_clk sdc1_p_clk = {
2299 .b = {
2300 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2301 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002302 .hwcg_reg = SDCn_HCLK_CTL_REG(1),
2303 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002304 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2305 .halt_bit = 11,
2306 },
2307 .c = {
2308 .dbg_name = "sdc1_p_clk",
2309 .ops = &clk_ops_branch,
2310 CLK_INIT(sdc1_p_clk.c),
2311 },
2312};
2313
2314static struct branch_clk sdc2_p_clk = {
2315 .b = {
2316 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2317 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002318 .hwcg_reg = SDCn_HCLK_CTL_REG(2),
2319 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002320 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2321 .halt_bit = 10,
2322 },
2323 .c = {
2324 .dbg_name = "sdc2_p_clk",
2325 .ops = &clk_ops_branch,
2326 CLK_INIT(sdc2_p_clk.c),
2327 },
2328};
2329
2330static struct branch_clk sdc3_p_clk = {
2331 .b = {
2332 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2333 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002334 .hwcg_reg = SDCn_HCLK_CTL_REG(3),
2335 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002336 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2337 .halt_bit = 9,
2338 },
2339 .c = {
2340 .dbg_name = "sdc3_p_clk",
2341 .ops = &clk_ops_branch,
2342 CLK_INIT(sdc3_p_clk.c),
2343 },
2344};
2345
2346static struct branch_clk sdc4_p_clk = {
2347 .b = {
2348 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2349 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002350 .hwcg_reg = SDCn_HCLK_CTL_REG(4),
2351 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002352 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2353 .halt_bit = 8,
2354 },
2355 .c = {
2356 .dbg_name = "sdc4_p_clk",
2357 .ops = &clk_ops_branch,
2358 CLK_INIT(sdc4_p_clk.c),
2359 },
2360};
2361
2362static struct branch_clk sdc5_p_clk = {
2363 .b = {
2364 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2365 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002366 .hwcg_reg = SDCn_HCLK_CTL_REG(5),
2367 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002368 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2369 .halt_bit = 7,
2370 },
2371 .c = {
2372 .dbg_name = "sdc5_p_clk",
2373 .ops = &clk_ops_branch,
2374 CLK_INIT(sdc5_p_clk.c),
2375 },
2376};
2377
2378/* HW-Voteable Clocks */
2379static struct branch_clk adm0_clk = {
2380 .b = {
2381 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2382 .en_mask = BIT(2),
2383 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2384 .halt_check = HALT_VOTED,
2385 .halt_bit = 14,
2386 },
2387 .c = {
2388 .dbg_name = "adm0_clk",
2389 .ops = &clk_ops_branch,
2390 CLK_INIT(adm0_clk.c),
2391 },
2392};
2393
2394static struct branch_clk adm0_p_clk = {
2395 .b = {
2396 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2397 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002398 .hwcg_reg = ADM0_PBUS_CLK_CTL_REG,
2399 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002400 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2401 .halt_check = HALT_VOTED,
2402 .halt_bit = 13,
2403 },
2404 .c = {
2405 .dbg_name = "adm0_p_clk",
2406 .ops = &clk_ops_branch,
2407 CLK_INIT(adm0_p_clk.c),
2408 },
2409};
2410
2411static struct branch_clk pmic_arb0_p_clk = {
2412 .b = {
2413 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2414 .en_mask = BIT(8),
2415 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2416 .halt_check = HALT_VOTED,
2417 .halt_bit = 22,
2418 },
2419 .c = {
2420 .dbg_name = "pmic_arb0_p_clk",
2421 .ops = &clk_ops_branch,
2422 CLK_INIT(pmic_arb0_p_clk.c),
2423 },
2424};
2425
2426static struct branch_clk pmic_arb1_p_clk = {
2427 .b = {
2428 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2429 .en_mask = BIT(9),
2430 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2431 .halt_check = HALT_VOTED,
2432 .halt_bit = 21,
2433 },
2434 .c = {
2435 .dbg_name = "pmic_arb1_p_clk",
2436 .ops = &clk_ops_branch,
2437 CLK_INIT(pmic_arb1_p_clk.c),
2438 },
2439};
2440
2441static struct branch_clk pmic_ssbi2_clk = {
2442 .b = {
2443 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2444 .en_mask = BIT(7),
2445 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2446 .halt_check = HALT_VOTED,
2447 .halt_bit = 23,
2448 },
2449 .c = {
2450 .dbg_name = "pmic_ssbi2_clk",
2451 .ops = &clk_ops_branch,
2452 CLK_INIT(pmic_ssbi2_clk.c),
2453 },
2454};
2455
2456static struct branch_clk rpm_msg_ram_p_clk = {
2457 .b = {
2458 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2459 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002460 .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG,
2461 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002462 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2463 .halt_check = HALT_VOTED,
2464 .halt_bit = 12,
2465 },
2466 .c = {
2467 .dbg_name = "rpm_msg_ram_p_clk",
2468 .ops = &clk_ops_branch,
2469 CLK_INIT(rpm_msg_ram_p_clk.c),
2470 },
2471};
2472
2473/*
2474 * Multimedia Clocks
2475 */
2476
2477static struct branch_clk amp_clk = {
2478 .b = {
2479 .reset_reg = SW_RESET_CORE_REG,
2480 .reset_mask = BIT(20),
2481 },
2482 .c = {
2483 .dbg_name = "amp_clk",
2484 .ops = &clk_ops_reset,
2485 CLK_INIT(amp_clk.c),
2486 },
2487};
2488
Stephen Boyd94625ef2011-07-12 17:06:01 -07002489#define CLK_CAM(name, n, hb) \
2490 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002491 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002492 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002493 .en_mask = BIT(0), \
2494 .halt_reg = DBG_BUS_VEC_I_REG, \
2495 .halt_bit = hb, \
2496 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002497 .ns_reg = CAMCLK##n##_NS_REG, \
2498 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002499 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002500 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002501 .ctl_mask = BM(7, 6), \
2502 .set_rate = set_rate_mnd_8, \
2503 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002504 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002505 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002506 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002507 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002508 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002509 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002510 }, \
2511 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002512#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002513 { \
2514 .freq_hz = f, \
2515 .src_clk = &s##_clk.c, \
2516 .md_val = MD8(8, m, 0, n), \
2517 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2518 .ctl_val = CC(6, n), \
2519 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002520 }
2521static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002522 F_CAM( 0, gnd, 1, 0, 0),
2523 F_CAM( 6000000, pll8, 4, 1, 16),
2524 F_CAM( 8000000, pll8, 4, 1, 12),
2525 F_CAM( 12000000, pll8, 4, 1, 8),
2526 F_CAM( 16000000, pll8, 4, 1, 6),
2527 F_CAM( 19200000, pll8, 4, 1, 5),
2528 F_CAM( 24000000, pll8, 4, 1, 4),
2529 F_CAM( 32000000, pll8, 4, 1, 3),
2530 F_CAM( 48000000, pll8, 4, 1, 2),
2531 F_CAM( 64000000, pll8, 3, 1, 2),
2532 F_CAM( 96000000, pll8, 4, 0, 0),
2533 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002534 F_END
2535};
2536
Stephen Boyd94625ef2011-07-12 17:06:01 -07002537static CLK_CAM(cam0_clk, 0, 15);
2538static CLK_CAM(cam1_clk, 1, 16);
2539static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002540
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002541#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002542 { \
2543 .freq_hz = f, \
2544 .src_clk = &s##_clk.c, \
2545 .md_val = MD8(8, m, 0, n), \
2546 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2547 .ctl_val = CC(6, n), \
2548 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002549 }
2550static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002551 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002552 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002553 F_CSI( 85330000, pll8, 1, 2, 9),
2554 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002555 F_END
2556};
2557
2558static struct rcg_clk csi0_src_clk = {
2559 .ns_reg = CSI0_NS_REG,
2560 .b = {
2561 .ctl_reg = CSI0_CC_REG,
2562 .halt_check = NOCHECK,
2563 },
2564 .md_reg = CSI0_MD_REG,
2565 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002566 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002567 .ctl_mask = BM(7, 6),
2568 .set_rate = set_rate_mnd,
2569 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002570 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002571 .c = {
2572 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002573 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002574 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002575 CLK_INIT(csi0_src_clk.c),
2576 },
2577};
2578
2579static struct branch_clk csi0_clk = {
2580 .b = {
2581 .ctl_reg = CSI0_CC_REG,
2582 .en_mask = BIT(0),
2583 .reset_reg = SW_RESET_CORE_REG,
2584 .reset_mask = BIT(8),
2585 .halt_reg = DBG_BUS_VEC_B_REG,
2586 .halt_bit = 13,
2587 },
2588 .parent = &csi0_src_clk.c,
2589 .c = {
2590 .dbg_name = "csi0_clk",
2591 .ops = &clk_ops_branch,
2592 CLK_INIT(csi0_clk.c),
2593 },
2594};
2595
2596static struct branch_clk csi0_phy_clk = {
2597 .b = {
2598 .ctl_reg = CSI0_CC_REG,
2599 .en_mask = BIT(8),
2600 .reset_reg = SW_RESET_CORE_REG,
2601 .reset_mask = BIT(29),
2602 .halt_reg = DBG_BUS_VEC_I_REG,
2603 .halt_bit = 9,
2604 },
2605 .parent = &csi0_src_clk.c,
2606 .c = {
2607 .dbg_name = "csi0_phy_clk",
2608 .ops = &clk_ops_branch,
2609 CLK_INIT(csi0_phy_clk.c),
2610 },
2611};
2612
2613static struct rcg_clk csi1_src_clk = {
2614 .ns_reg = CSI1_NS_REG,
2615 .b = {
2616 .ctl_reg = CSI1_CC_REG,
2617 .halt_check = NOCHECK,
2618 },
2619 .md_reg = CSI1_MD_REG,
2620 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002621 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002622 .ctl_mask = BM(7, 6),
2623 .set_rate = set_rate_mnd,
2624 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002625 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002626 .c = {
2627 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002628 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002629 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002630 CLK_INIT(csi1_src_clk.c),
2631 },
2632};
2633
2634static struct branch_clk csi1_clk = {
2635 .b = {
2636 .ctl_reg = CSI1_CC_REG,
2637 .en_mask = BIT(0),
2638 .reset_reg = SW_RESET_CORE_REG,
2639 .reset_mask = BIT(18),
2640 .halt_reg = DBG_BUS_VEC_B_REG,
2641 .halt_bit = 14,
2642 },
2643 .parent = &csi1_src_clk.c,
2644 .c = {
2645 .dbg_name = "csi1_clk",
2646 .ops = &clk_ops_branch,
2647 CLK_INIT(csi1_clk.c),
2648 },
2649};
2650
2651static struct branch_clk csi1_phy_clk = {
2652 .b = {
2653 .ctl_reg = CSI1_CC_REG,
2654 .en_mask = BIT(8),
2655 .reset_reg = SW_RESET_CORE_REG,
2656 .reset_mask = BIT(28),
2657 .halt_reg = DBG_BUS_VEC_I_REG,
2658 .halt_bit = 10,
2659 },
2660 .parent = &csi1_src_clk.c,
2661 .c = {
2662 .dbg_name = "csi1_phy_clk",
2663 .ops = &clk_ops_branch,
2664 CLK_INIT(csi1_phy_clk.c),
2665 },
2666};
2667
Stephen Boyd94625ef2011-07-12 17:06:01 -07002668static struct rcg_clk csi2_src_clk = {
2669 .ns_reg = CSI2_NS_REG,
2670 .b = {
2671 .ctl_reg = CSI2_CC_REG,
2672 .halt_check = NOCHECK,
2673 },
2674 .md_reg = CSI2_MD_REG,
2675 .root_en_mask = BIT(2),
2676 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
2677 .ctl_mask = BM(7, 6),
2678 .set_rate = set_rate_mnd,
2679 .freq_tbl = clk_tbl_csi,
2680 .current_freq = &rcg_dummy_freq,
2681 .c = {
2682 .dbg_name = "csi2_src_clk",
2683 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002684 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002685 CLK_INIT(csi2_src_clk.c),
2686 },
2687};
2688
2689static struct branch_clk csi2_clk = {
2690 .b = {
2691 .ctl_reg = CSI2_CC_REG,
2692 .en_mask = BIT(0),
2693 .reset_reg = SW_RESET_CORE2_REG,
2694 .reset_mask = BIT(2),
2695 .halt_reg = DBG_BUS_VEC_B_REG,
2696 .halt_bit = 29,
2697 },
2698 .parent = &csi2_src_clk.c,
2699 .c = {
2700 .dbg_name = "csi2_clk",
2701 .ops = &clk_ops_branch,
2702 CLK_INIT(csi2_clk.c),
2703 },
2704};
2705
2706static struct branch_clk csi2_phy_clk = {
2707 .b = {
2708 .ctl_reg = CSI2_CC_REG,
2709 .en_mask = BIT(8),
2710 .reset_reg = SW_RESET_CORE_REG,
2711 .reset_mask = BIT(31),
2712 .halt_reg = DBG_BUS_VEC_I_REG,
2713 .halt_bit = 29,
2714 },
2715 .parent = &csi2_src_clk.c,
2716 .c = {
2717 .dbg_name = "csi2_phy_clk",
2718 .ops = &clk_ops_branch,
2719 CLK_INIT(csi2_phy_clk.c),
2720 },
2721};
2722
Stephen Boyd092fd182011-10-21 15:56:30 -07002723static struct clk *pix_rdi_mux_map[] = {
2724 [0] = &csi0_clk.c,
2725 [1] = &csi1_clk.c,
2726 [2] = &csi2_clk.c,
2727 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002728};
2729
Stephen Boyd092fd182011-10-21 15:56:30 -07002730struct pix_rdi_clk {
2731 bool enabled;
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002732 unsigned long cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002733
2734 void __iomem *const s_reg;
2735 u32 s_mask;
2736
2737 void __iomem *const s2_reg;
2738 u32 s2_mask;
2739
2740 struct branch b;
2741 struct clk c;
2742};
2743
2744static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk)
2745{
2746 return container_of(clk, struct pix_rdi_clk, c);
2747}
2748
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002749static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate)
Stephen Boyd092fd182011-10-21 15:56:30 -07002750{
2751 int ret, i;
2752 u32 reg;
2753 unsigned long flags;
2754 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2755 struct clk **mux_map = pix_rdi_mux_map;
2756
2757 /*
2758 * These clocks select three inputs via two muxes. One mux selects
2759 * between csi0 and csi1 and the second mux selects between that mux's
2760 * output and csi2. The source and destination selections for each
2761 * mux must be clocking for the switch to succeed so just turn on
2762 * all three sources because it's easier than figuring out what source
2763 * needs to be on at what time.
2764 */
2765 for (i = 0; mux_map[i]; i++) {
2766 ret = clk_enable(mux_map[i]);
2767 if (ret)
2768 goto err;
2769 }
2770 if (rate >= i) {
2771 ret = -EINVAL;
2772 goto err;
2773 }
2774 /* Keep the new source on when switching inputs of an enabled clock */
2775 if (clk->enabled) {
2776 clk_disable(mux_map[clk->cur_rate]);
2777 clk_enable(mux_map[rate]);
2778 }
2779 spin_lock_irqsave(&local_clock_reg_lock, flags);
2780 reg = readl_relaxed(clk->s2_reg);
2781 reg &= ~clk->s2_mask;
2782 reg |= rate == 2 ? clk->s2_mask : 0;
2783 writel_relaxed(reg, clk->s2_reg);
2784 /*
2785 * Wait at least 6 cycles of slowest clock
2786 * for the glitch-free MUX to fully switch sources.
2787 */
2788 mb();
2789 udelay(1);
2790 reg = readl_relaxed(clk->s_reg);
2791 reg &= ~clk->s_mask;
2792 reg |= rate == 1 ? clk->s_mask : 0;
2793 writel_relaxed(reg, clk->s_reg);
2794 /*
2795 * Wait at least 6 cycles of slowest clock
2796 * for the glitch-free MUX to fully switch sources.
2797 */
2798 mb();
2799 udelay(1);
2800 clk->cur_rate = rate;
2801 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2802err:
2803 for (i--; i >= 0; i--)
2804 clk_disable(mux_map[i]);
2805
2806 return 0;
2807}
2808
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002809static unsigned long pix_rdi_clk_get_rate(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002810{
2811 return to_pix_rdi_clk(c)->cur_rate;
2812}
2813
2814static int pix_rdi_clk_enable(struct clk *c)
2815{
2816 unsigned long flags;
2817 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2818
2819 spin_lock_irqsave(&local_clock_reg_lock, flags);
2820 __branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
2821 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2822 clk->enabled = true;
2823
2824 return 0;
2825}
2826
2827static void pix_rdi_clk_disable(struct clk *c)
2828{
2829 unsigned long flags;
2830 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2831
2832 spin_lock_irqsave(&local_clock_reg_lock, flags);
2833 __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
2834 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2835 clk->enabled = false;
2836}
2837
2838static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action)
2839{
2840 return branch_reset(&to_pix_rdi_clk(clk)->b, action);
2841}
2842
2843static struct clk *pix_rdi_clk_get_parent(struct clk *c)
2844{
2845 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2846
2847 return pix_rdi_mux_map[clk->cur_rate];
2848}
2849
2850static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
2851{
2852 if (pix_rdi_mux_map[n])
2853 return n;
2854 return -ENXIO;
2855}
2856
2857static int pix_rdi_clk_handoff(struct clk *c)
2858{
2859 u32 reg;
2860 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2861
2862 reg = readl_relaxed(clk->s_reg);
2863 clk->cur_rate = reg & clk->s_mask ? 1 : 0;
2864 reg = readl_relaxed(clk->s2_reg);
2865 clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate;
2866 return 0;
2867}
2868
2869static struct clk_ops clk_ops_pix_rdi_8960 = {
2870 .enable = pix_rdi_clk_enable,
2871 .disable = pix_rdi_clk_disable,
2872 .auto_off = pix_rdi_clk_disable,
2873 .handoff = pix_rdi_clk_handoff,
2874 .set_rate = pix_rdi_clk_set_rate,
2875 .get_rate = pix_rdi_clk_get_rate,
2876 .list_rate = pix_rdi_clk_list_rate,
2877 .reset = pix_rdi_clk_reset,
2878 .is_local = local_clk_is_local,
2879 .get_parent = pix_rdi_clk_get_parent,
2880};
2881
2882static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002883 .b = {
2884 .ctl_reg = MISC_CC_REG,
2885 .en_mask = BIT(26),
2886 .halt_check = DELAY,
2887 .reset_reg = SW_RESET_CORE_REG,
2888 .reset_mask = BIT(26),
2889 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002890 .s_reg = MISC_CC_REG,
2891 .s_mask = BIT(25),
2892 .s2_reg = MISC_CC3_REG,
2893 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002894 .c = {
2895 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002896 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002897 CLK_INIT(csi_pix_clk.c),
2898 },
2899};
2900
Stephen Boyd092fd182011-10-21 15:56:30 -07002901static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002902 .b = {
2903 .ctl_reg = MISC_CC3_REG,
2904 .en_mask = BIT(10),
2905 .halt_check = DELAY,
2906 .reset_reg = SW_RESET_CORE_REG,
2907 .reset_mask = BIT(30),
2908 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002909 .s_reg = MISC_CC3_REG,
2910 .s_mask = BIT(8),
2911 .s2_reg = MISC_CC3_REG,
2912 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002913 .c = {
2914 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002915 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002916 CLK_INIT(csi_pix1_clk.c),
2917 },
2918};
2919
Stephen Boyd092fd182011-10-21 15:56:30 -07002920static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002921 .b = {
2922 .ctl_reg = MISC_CC_REG,
2923 .en_mask = BIT(13),
2924 .halt_check = DELAY,
2925 .reset_reg = SW_RESET_CORE_REG,
2926 .reset_mask = BIT(27),
2927 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002928 .s_reg = MISC_CC_REG,
2929 .s_mask = BIT(12),
2930 .s2_reg = MISC_CC3_REG,
2931 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002932 .c = {
2933 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002934 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002935 CLK_INIT(csi_rdi_clk.c),
2936 },
2937};
2938
Stephen Boyd092fd182011-10-21 15:56:30 -07002939static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002940 .b = {
2941 .ctl_reg = MISC_CC3_REG,
2942 .en_mask = BIT(2),
2943 .halt_check = DELAY,
2944 .reset_reg = SW_RESET_CORE2_REG,
2945 .reset_mask = BIT(1),
2946 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002947 .s_reg = MISC_CC3_REG,
2948 .s_mask = BIT(0),
2949 .s2_reg = MISC_CC3_REG,
2950 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002951 .c = {
2952 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002953 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002954 CLK_INIT(csi_rdi1_clk.c),
2955 },
2956};
2957
Stephen Boyd092fd182011-10-21 15:56:30 -07002958static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002959 .b = {
2960 .ctl_reg = MISC_CC3_REG,
2961 .en_mask = BIT(6),
2962 .halt_check = DELAY,
2963 .reset_reg = SW_RESET_CORE2_REG,
2964 .reset_mask = BIT(0),
2965 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002966 .s_reg = MISC_CC3_REG,
2967 .s_mask = BIT(4),
2968 .s2_reg = MISC_CC3_REG,
2969 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002970 .c = {
2971 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002972 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002973 CLK_INIT(csi_rdi2_clk.c),
2974 },
2975};
2976
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002977#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002978 { \
2979 .freq_hz = f, \
2980 .src_clk = &s##_clk.c, \
2981 .md_val = MD8(8, m, 0, n), \
2982 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2983 .ctl_val = CC(6, n), \
2984 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002985 }
2986static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002987 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
2988 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
2989 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002990 F_END
2991};
2992
2993static struct rcg_clk csiphy_timer_src_clk = {
2994 .ns_reg = CSIPHYTIMER_NS_REG,
2995 .b = {
2996 .ctl_reg = CSIPHYTIMER_CC_REG,
2997 .halt_check = NOCHECK,
2998 },
2999 .md_reg = CSIPHYTIMER_MD_REG,
3000 .root_en_mask = BIT(2),
3001 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
3002 .ctl_mask = BM(7, 6),
3003 .set_rate = set_rate_mnd_8,
3004 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003005 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003006 .c = {
3007 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003008 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003009 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003010 CLK_INIT(csiphy_timer_src_clk.c),
3011 },
3012};
3013
3014static struct branch_clk csi0phy_timer_clk = {
3015 .b = {
3016 .ctl_reg = CSIPHYTIMER_CC_REG,
3017 .en_mask = BIT(0),
3018 .halt_reg = DBG_BUS_VEC_I_REG,
3019 .halt_bit = 17,
3020 },
3021 .parent = &csiphy_timer_src_clk.c,
3022 .c = {
3023 .dbg_name = "csi0phy_timer_clk",
3024 .ops = &clk_ops_branch,
3025 CLK_INIT(csi0phy_timer_clk.c),
3026 },
3027};
3028
3029static struct branch_clk csi1phy_timer_clk = {
3030 .b = {
3031 .ctl_reg = CSIPHYTIMER_CC_REG,
3032 .en_mask = BIT(9),
3033 .halt_reg = DBG_BUS_VEC_I_REG,
3034 .halt_bit = 18,
3035 },
3036 .parent = &csiphy_timer_src_clk.c,
3037 .c = {
3038 .dbg_name = "csi1phy_timer_clk",
3039 .ops = &clk_ops_branch,
3040 CLK_INIT(csi1phy_timer_clk.c),
3041 },
3042};
3043
Stephen Boyd94625ef2011-07-12 17:06:01 -07003044static struct branch_clk csi2phy_timer_clk = {
3045 .b = {
3046 .ctl_reg = CSIPHYTIMER_CC_REG,
3047 .en_mask = BIT(11),
3048 .halt_reg = DBG_BUS_VEC_I_REG,
3049 .halt_bit = 30,
3050 },
3051 .parent = &csiphy_timer_src_clk.c,
3052 .c = {
3053 .dbg_name = "csi2phy_timer_clk",
3054 .ops = &clk_ops_branch,
3055 CLK_INIT(csi2phy_timer_clk.c),
3056 },
3057};
3058
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003059#define F_DSI(d) \
3060 { \
3061 .freq_hz = d, \
3062 .ns_val = BVAL(15, 12, (d-1)), \
3063 }
3064/*
3065 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3066 * without this clock driver knowing. So, overload the clk_set_rate() to set
3067 * the divider (1 to 16) of the clock with respect to the PLL rate.
3068 */
3069static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3070 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3071 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3072 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3073 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3074 F_END
3075};
3076
3077static struct rcg_clk dsi1_byte_clk = {
3078 .b = {
3079 .ctl_reg = DSI1_BYTE_CC_REG,
3080 .en_mask = BIT(0),
3081 .reset_reg = SW_RESET_CORE_REG,
3082 .reset_mask = BIT(7),
3083 .halt_reg = DBG_BUS_VEC_B_REG,
3084 .halt_bit = 21,
3085 },
3086 .ns_reg = DSI1_BYTE_NS_REG,
3087 .root_en_mask = BIT(2),
3088 .ns_mask = BM(15, 12),
3089 .set_rate = set_rate_nop,
3090 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003091 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003092 .c = {
3093 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003094 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003095 CLK_INIT(dsi1_byte_clk.c),
3096 },
3097};
3098
3099static struct rcg_clk dsi2_byte_clk = {
3100 .b = {
3101 .ctl_reg = DSI2_BYTE_CC_REG,
3102 .en_mask = BIT(0),
3103 .reset_reg = SW_RESET_CORE_REG,
3104 .reset_mask = BIT(25),
3105 .halt_reg = DBG_BUS_VEC_B_REG,
3106 .halt_bit = 20,
3107 },
3108 .ns_reg = DSI2_BYTE_NS_REG,
3109 .root_en_mask = BIT(2),
3110 .ns_mask = BM(15, 12),
3111 .set_rate = set_rate_nop,
3112 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003113 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003114 .c = {
3115 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003116 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003117 CLK_INIT(dsi2_byte_clk.c),
3118 },
3119};
3120
3121static struct rcg_clk dsi1_esc_clk = {
3122 .b = {
3123 .ctl_reg = DSI1_ESC_CC_REG,
3124 .en_mask = BIT(0),
3125 .reset_reg = SW_RESET_CORE_REG,
3126 .halt_reg = DBG_BUS_VEC_I_REG,
3127 .halt_bit = 1,
3128 },
3129 .ns_reg = DSI1_ESC_NS_REG,
3130 .root_en_mask = BIT(2),
3131 .ns_mask = BM(15, 12),
3132 .set_rate = set_rate_nop,
3133 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003134 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003135 .c = {
3136 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003137 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003138 CLK_INIT(dsi1_esc_clk.c),
3139 },
3140};
3141
3142static struct rcg_clk dsi2_esc_clk = {
3143 .b = {
3144 .ctl_reg = DSI2_ESC_CC_REG,
3145 .en_mask = BIT(0),
3146 .halt_reg = DBG_BUS_VEC_I_REG,
3147 .halt_bit = 3,
3148 },
3149 .ns_reg = DSI2_ESC_NS_REG,
3150 .root_en_mask = BIT(2),
3151 .ns_mask = BM(15, 12),
3152 .set_rate = set_rate_nop,
3153 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003154 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003155 .c = {
3156 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003157 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003158 CLK_INIT(dsi2_esc_clk.c),
3159 },
3160};
3161
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003162#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003163 { \
3164 .freq_hz = f, \
3165 .src_clk = &s##_clk.c, \
3166 .md_val = MD4(4, m, 0, n), \
3167 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3168 .ctl_val = CC_BANKED(9, 6, n), \
3169 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003170 }
3171static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003172 F_GFX2D( 0, gnd, 0, 0),
3173 F_GFX2D( 27000000, pxo, 0, 0),
3174 F_GFX2D( 48000000, pll8, 1, 8),
3175 F_GFX2D( 54857000, pll8, 1, 7),
3176 F_GFX2D( 64000000, pll8, 1, 6),
3177 F_GFX2D( 76800000, pll8, 1, 5),
3178 F_GFX2D( 96000000, pll8, 1, 4),
3179 F_GFX2D(128000000, pll8, 1, 3),
3180 F_GFX2D(145455000, pll2, 2, 11),
3181 F_GFX2D(160000000, pll2, 1, 5),
3182 F_GFX2D(177778000, pll2, 2, 9),
3183 F_GFX2D(200000000, pll2, 1, 4),
3184 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003185 F_END
3186};
3187
3188static struct bank_masks bmnd_info_gfx2d0 = {
3189 .bank_sel_mask = BIT(11),
3190 .bank0_mask = {
3191 .md_reg = GFX2D0_MD0_REG,
3192 .ns_mask = BM(23, 20) | BM(5, 3),
3193 .rst_mask = BIT(25),
3194 .mnd_en_mask = BIT(8),
3195 .mode_mask = BM(10, 9),
3196 },
3197 .bank1_mask = {
3198 .md_reg = GFX2D0_MD1_REG,
3199 .ns_mask = BM(19, 16) | BM(2, 0),
3200 .rst_mask = BIT(24),
3201 .mnd_en_mask = BIT(5),
3202 .mode_mask = BM(7, 6),
3203 },
3204};
3205
3206static struct rcg_clk gfx2d0_clk = {
3207 .b = {
3208 .ctl_reg = GFX2D0_CC_REG,
3209 .en_mask = BIT(0),
3210 .reset_reg = SW_RESET_CORE_REG,
3211 .reset_mask = BIT(14),
3212 .halt_reg = DBG_BUS_VEC_A_REG,
3213 .halt_bit = 9,
3214 },
3215 .ns_reg = GFX2D0_NS_REG,
3216 .root_en_mask = BIT(2),
3217 .set_rate = set_rate_mnd_banked,
3218 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003219 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003220 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003221 .c = {
3222 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003223 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003224 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3225 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003226 CLK_INIT(gfx2d0_clk.c),
3227 },
3228};
3229
3230static struct bank_masks bmnd_info_gfx2d1 = {
3231 .bank_sel_mask = BIT(11),
3232 .bank0_mask = {
3233 .md_reg = GFX2D1_MD0_REG,
3234 .ns_mask = BM(23, 20) | BM(5, 3),
3235 .rst_mask = BIT(25),
3236 .mnd_en_mask = BIT(8),
3237 .mode_mask = BM(10, 9),
3238 },
3239 .bank1_mask = {
3240 .md_reg = GFX2D1_MD1_REG,
3241 .ns_mask = BM(19, 16) | BM(2, 0),
3242 .rst_mask = BIT(24),
3243 .mnd_en_mask = BIT(5),
3244 .mode_mask = BM(7, 6),
3245 },
3246};
3247
3248static struct rcg_clk gfx2d1_clk = {
3249 .b = {
3250 .ctl_reg = GFX2D1_CC_REG,
3251 .en_mask = BIT(0),
3252 .reset_reg = SW_RESET_CORE_REG,
3253 .reset_mask = BIT(13),
3254 .halt_reg = DBG_BUS_VEC_A_REG,
3255 .halt_bit = 14,
3256 },
3257 .ns_reg = GFX2D1_NS_REG,
3258 .root_en_mask = BIT(2),
3259 .set_rate = set_rate_mnd_banked,
3260 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003261 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003262 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003263 .c = {
3264 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003265 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003266 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3267 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003268 CLK_INIT(gfx2d1_clk.c),
3269 },
3270};
3271
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003272#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003273 { \
3274 .freq_hz = f, \
3275 .src_clk = &s##_clk.c, \
3276 .md_val = MD4(4, m, 0, n), \
3277 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3278 .ctl_val = CC_BANKED(9, 6, n), \
3279 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003280 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003281
3282static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003283 F_GFX3D( 0, gnd, 0, 0),
3284 F_GFX3D( 27000000, pxo, 0, 0),
3285 F_GFX3D( 48000000, pll8, 1, 8),
3286 F_GFX3D( 54857000, pll8, 1, 7),
3287 F_GFX3D( 64000000, pll8, 1, 6),
3288 F_GFX3D( 76800000, pll8, 1, 5),
3289 F_GFX3D( 96000000, pll8, 1, 4),
3290 F_GFX3D(128000000, pll8, 1, 3),
3291 F_GFX3D(145455000, pll2, 2, 11),
3292 F_GFX3D(160000000, pll2, 1, 5),
3293 F_GFX3D(177778000, pll2, 2, 9),
3294 F_GFX3D(200000000, pll2, 1, 4),
3295 F_GFX3D(228571000, pll2, 2, 7),
3296 F_GFX3D(266667000, pll2, 1, 3),
3297 F_GFX3D(320000000, pll2, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003298 F_END
3299};
3300
Tianyi Gou41515e22011-09-01 19:37:43 -07003301static struct clk_freq_tbl clk_tbl_gfx3d_8960_v2[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003302 F_GFX3D( 0, gnd, 0, 0),
3303 F_GFX3D( 27000000, pxo, 0, 0),
3304 F_GFX3D( 48000000, pll8, 1, 8),
3305 F_GFX3D( 54857000, pll8, 1, 7),
3306 F_GFX3D( 64000000, pll8, 1, 6),
3307 F_GFX3D( 76800000, pll8, 1, 5),
3308 F_GFX3D( 96000000, pll8, 1, 4),
3309 F_GFX3D(128000000, pll8, 1, 3),
3310 F_GFX3D(145455000, pll2, 2, 11),
3311 F_GFX3D(160000000, pll2, 1, 5),
3312 F_GFX3D(177778000, pll2, 2, 9),
3313 F_GFX3D(200000000, pll2, 1, 4),
3314 F_GFX3D(228571000, pll2, 2, 7),
3315 F_GFX3D(266667000, pll2, 1, 3),
3316 F_GFX3D(300000000, pll3, 1, 4),
3317 F_GFX3D(320000000, pll2, 2, 5),
3318 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003319 F_END
3320};
3321
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003322static unsigned long fmax_gfx3d_8960_v2[MAX_VDD_LEVELS] __initdata = {
3323 [VDD_DIG_LOW] = 128000000,
3324 [VDD_DIG_NOMINAL] = 300000000,
3325 [VDD_DIG_HIGH] = 400000000
3326};
3327
Tianyi Gou41515e22011-09-01 19:37:43 -07003328static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003329 F_GFX3D( 0, gnd, 0, 0),
3330 F_GFX3D( 27000000, pxo, 0, 0),
3331 F_GFX3D( 48000000, pll8, 1, 8),
3332 F_GFX3D( 54857000, pll8, 1, 7),
3333 F_GFX3D( 64000000, pll8, 1, 6),
3334 F_GFX3D( 76800000, pll8, 1, 5),
3335 F_GFX3D( 96000000, pll8, 1, 4),
3336 F_GFX3D(128000000, pll8, 1, 3),
3337 F_GFX3D(145455000, pll2, 2, 11),
3338 F_GFX3D(160000000, pll2, 1, 5),
3339 F_GFX3D(177778000, pll2, 2, 9),
3340 F_GFX3D(200000000, pll2, 1, 4),
3341 F_GFX3D(228571000, pll2, 2, 7),
3342 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07003343 F_GFX3D(325000000, pll15, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003344 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003345 F_END
3346};
3347
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003348static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3349 [VDD_DIG_LOW] = 128000000,
3350 [VDD_DIG_NOMINAL] = 325000000,
3351 [VDD_DIG_HIGH] = 400000000
3352};
3353
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003354static struct bank_masks bmnd_info_gfx3d = {
3355 .bank_sel_mask = BIT(11),
3356 .bank0_mask = {
3357 .md_reg = GFX3D_MD0_REG,
3358 .ns_mask = BM(21, 18) | BM(5, 3),
3359 .rst_mask = BIT(23),
3360 .mnd_en_mask = BIT(8),
3361 .mode_mask = BM(10, 9),
3362 },
3363 .bank1_mask = {
3364 .md_reg = GFX3D_MD1_REG,
3365 .ns_mask = BM(17, 14) | BM(2, 0),
3366 .rst_mask = BIT(22),
3367 .mnd_en_mask = BIT(5),
3368 .mode_mask = BM(7, 6),
3369 },
3370};
3371
3372static struct rcg_clk gfx3d_clk = {
3373 .b = {
3374 .ctl_reg = GFX3D_CC_REG,
3375 .en_mask = BIT(0),
3376 .reset_reg = SW_RESET_CORE_REG,
3377 .reset_mask = BIT(12),
3378 .halt_reg = DBG_BUS_VEC_A_REG,
3379 .halt_bit = 4,
3380 },
3381 .ns_reg = GFX3D_NS_REG,
3382 .root_en_mask = BIT(2),
3383 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003384 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003385 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003386 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003387 .c = {
3388 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003389 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003390 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 266667000,
3391 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003392 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003393 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003394 },
3395};
3396
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003397#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003398 { \
3399 .freq_hz = f, \
3400 .src_clk = &s##_clk.c, \
3401 .md_val = MD4(4, m, 0, n), \
3402 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3403 .ctl_val = CC_BANKED(9, 6, n), \
3404 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003405 }
3406
3407static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003408 F_VCAP( 0, gnd, 0, 0),
3409 F_VCAP( 27000000, pxo, 0, 0),
3410 F_VCAP( 54860000, pll8, 1, 7),
3411 F_VCAP( 64000000, pll8, 1, 6),
3412 F_VCAP( 76800000, pll8, 1, 5),
3413 F_VCAP(128000000, pll8, 1, 3),
3414 F_VCAP(160000000, pll2, 1, 5),
3415 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003416 F_END
3417};
3418
3419static struct bank_masks bmnd_info_vcap = {
3420 .bank_sel_mask = BIT(11),
3421 .bank0_mask = {
3422 .md_reg = VCAP_MD0_REG,
3423 .ns_mask = BM(21, 18) | BM(5, 3),
3424 .rst_mask = BIT(23),
3425 .mnd_en_mask = BIT(8),
3426 .mode_mask = BM(10, 9),
3427 },
3428 .bank1_mask = {
3429 .md_reg = VCAP_MD1_REG,
3430 .ns_mask = BM(17, 14) | BM(2, 0),
3431 .rst_mask = BIT(22),
3432 .mnd_en_mask = BIT(5),
3433 .mode_mask = BM(7, 6),
3434 },
3435};
3436
3437static struct rcg_clk vcap_clk = {
3438 .b = {
3439 .ctl_reg = VCAP_CC_REG,
3440 .en_mask = BIT(0),
3441 .halt_reg = DBG_BUS_VEC_J_REG,
3442 .halt_bit = 15,
3443 },
3444 .ns_reg = VCAP_NS_REG,
3445 .root_en_mask = BIT(2),
3446 .set_rate = set_rate_mnd_banked,
3447 .freq_tbl = clk_tbl_vcap,
3448 .bank_info = &bmnd_info_vcap,
3449 .current_freq = &rcg_dummy_freq,
3450 .c = {
3451 .dbg_name = "vcap_clk",
3452 .ops = &clk_ops_rcg_8960,
3453 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003454 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003455 CLK_INIT(vcap_clk.c),
3456 },
3457};
3458
3459static struct branch_clk vcap_npl_clk = {
3460 .b = {
3461 .ctl_reg = VCAP_CC_REG,
3462 .en_mask = BIT(13),
3463 .halt_reg = DBG_BUS_VEC_J_REG,
3464 .halt_bit = 25,
3465 },
3466 .parent = &vcap_clk.c,
3467 .c = {
3468 .dbg_name = "vcap_npl_clk",
3469 .ops = &clk_ops_branch,
3470 CLK_INIT(vcap_npl_clk.c),
3471 },
3472};
3473
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003474#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003475 { \
3476 .freq_hz = f, \
3477 .src_clk = &s##_clk.c, \
3478 .md_val = MD8(8, m, 0, n), \
3479 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3480 .ctl_val = CC(6, n), \
3481 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003482 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003483
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003484static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3485 F_IJPEG( 0, gnd, 1, 0, 0),
3486 F_IJPEG( 27000000, pxo, 1, 0, 0),
3487 F_IJPEG( 36570000, pll8, 1, 2, 21),
3488 F_IJPEG( 54860000, pll8, 7, 0, 0),
3489 F_IJPEG( 96000000, pll8, 4, 0, 0),
3490 F_IJPEG(109710000, pll8, 1, 2, 7),
3491 F_IJPEG(128000000, pll8, 3, 0, 0),
3492 F_IJPEG(153600000, pll8, 1, 2, 5),
3493 F_IJPEG(200000000, pll2, 4, 0, 0),
3494 F_IJPEG(228571000, pll2, 1, 2, 7),
3495 F_IJPEG(266667000, pll2, 1, 1, 3),
3496 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003497 F_END
3498};
3499
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003500static unsigned long fmax_ijpeg_8960_v2[MAX_VDD_LEVELS] __initdata = {
3501 [VDD_DIG_LOW] = 110000000,
3502 [VDD_DIG_NOMINAL] = 266667000,
3503 [VDD_DIG_HIGH] = 320000000
3504};
3505
3506static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3507 [VDD_DIG_LOW] = 128000000,
3508 [VDD_DIG_NOMINAL] = 266667000,
3509 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003510};
3511
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003512static struct rcg_clk ijpeg_clk = {
3513 .b = {
3514 .ctl_reg = IJPEG_CC_REG,
3515 .en_mask = BIT(0),
3516 .reset_reg = SW_RESET_CORE_REG,
3517 .reset_mask = BIT(9),
3518 .halt_reg = DBG_BUS_VEC_A_REG,
3519 .halt_bit = 24,
3520 },
3521 .ns_reg = IJPEG_NS_REG,
3522 .md_reg = IJPEG_MD_REG,
3523 .root_en_mask = BIT(2),
3524 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
3525 .ctl_mask = BM(7, 6),
3526 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003527 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003528 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003529 .c = {
3530 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003531 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003532 VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003533 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003534 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003535 },
3536};
3537
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003538#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003539 { \
3540 .freq_hz = f, \
3541 .src_clk = &s##_clk.c, \
3542 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003543 }
3544static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003545 F_JPEGD( 0, gnd, 1),
3546 F_JPEGD( 64000000, pll8, 6),
3547 F_JPEGD( 76800000, pll8, 5),
3548 F_JPEGD( 96000000, pll8, 4),
3549 F_JPEGD(160000000, pll2, 5),
3550 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003551 F_END
3552};
3553
3554static struct rcg_clk jpegd_clk = {
3555 .b = {
3556 .ctl_reg = JPEGD_CC_REG,
3557 .en_mask = BIT(0),
3558 .reset_reg = SW_RESET_CORE_REG,
3559 .reset_mask = BIT(19),
3560 .halt_reg = DBG_BUS_VEC_A_REG,
3561 .halt_bit = 19,
3562 },
3563 .ns_reg = JPEGD_NS_REG,
3564 .root_en_mask = BIT(2),
3565 .ns_mask = (BM(15, 12) | BM(2, 0)),
3566 .set_rate = set_rate_nop,
3567 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003568 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003569 .c = {
3570 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003571 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003572 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003573 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003574 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003575 },
3576};
3577
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003578#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003579 { \
3580 .freq_hz = f, \
3581 .src_clk = &s##_clk.c, \
3582 .md_val = MD8(8, m, 0, n), \
3583 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3584 .ctl_val = CC_BANKED(9, 6, n), \
3585 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003586 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003587static struct clk_freq_tbl clk_tbl_mdp[] = {
3588 F_MDP( 0, gnd, 0, 0),
3589 F_MDP( 9600000, pll8, 1, 40),
3590 F_MDP( 13710000, pll8, 1, 28),
3591 F_MDP( 27000000, pxo, 0, 0),
3592 F_MDP( 29540000, pll8, 1, 13),
3593 F_MDP( 34910000, pll8, 1, 11),
3594 F_MDP( 38400000, pll8, 1, 10),
3595 F_MDP( 59080000, pll8, 2, 13),
3596 F_MDP( 76800000, pll8, 1, 5),
3597 F_MDP( 85330000, pll8, 2, 9),
3598 F_MDP( 96000000, pll8, 1, 4),
3599 F_MDP(128000000, pll8, 1, 3),
3600 F_MDP(160000000, pll2, 1, 5),
3601 F_MDP(177780000, pll2, 2, 9),
3602 F_MDP(200000000, pll2, 1, 4),
3603 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003604 F_END
3605};
3606
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003607static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3608 [VDD_DIG_LOW] = 128000000,
3609 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003610};
3611
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003612static struct bank_masks bmnd_info_mdp = {
3613 .bank_sel_mask = BIT(11),
3614 .bank0_mask = {
3615 .md_reg = MDP_MD0_REG,
3616 .ns_mask = BM(29, 22) | BM(5, 3),
3617 .rst_mask = BIT(31),
3618 .mnd_en_mask = BIT(8),
3619 .mode_mask = BM(10, 9),
3620 },
3621 .bank1_mask = {
3622 .md_reg = MDP_MD1_REG,
3623 .ns_mask = BM(21, 14) | BM(2, 0),
3624 .rst_mask = BIT(30),
3625 .mnd_en_mask = BIT(5),
3626 .mode_mask = BM(7, 6),
3627 },
3628};
3629
3630static struct rcg_clk mdp_clk = {
3631 .b = {
3632 .ctl_reg = MDP_CC_REG,
3633 .en_mask = BIT(0),
3634 .reset_reg = SW_RESET_CORE_REG,
3635 .reset_mask = BIT(21),
3636 .halt_reg = DBG_BUS_VEC_C_REG,
3637 .halt_bit = 10,
3638 },
3639 .ns_reg = MDP_NS_REG,
3640 .root_en_mask = BIT(2),
3641 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003642 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003643 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003644 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003645 .c = {
3646 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003647 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003648 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003649 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003650 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003651 },
3652};
3653
3654static struct branch_clk lut_mdp_clk = {
3655 .b = {
3656 .ctl_reg = MDP_LUT_CC_REG,
3657 .en_mask = BIT(0),
3658 .halt_reg = DBG_BUS_VEC_I_REG,
3659 .halt_bit = 13,
3660 },
3661 .parent = &mdp_clk.c,
3662 .c = {
3663 .dbg_name = "lut_mdp_clk",
3664 .ops = &clk_ops_branch,
3665 CLK_INIT(lut_mdp_clk.c),
3666 },
3667};
3668
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003669#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003670 { \
3671 .freq_hz = f, \
3672 .src_clk = &s##_clk.c, \
3673 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003674 }
3675static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003676 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003677 F_END
3678};
3679
3680static struct rcg_clk mdp_vsync_clk = {
3681 .b = {
3682 .ctl_reg = MISC_CC_REG,
3683 .en_mask = BIT(6),
3684 .reset_reg = SW_RESET_CORE_REG,
3685 .reset_mask = BIT(3),
3686 .halt_reg = DBG_BUS_VEC_B_REG,
3687 .halt_bit = 22,
3688 },
3689 .ns_reg = MISC_CC2_REG,
3690 .ns_mask = BIT(13),
3691 .set_rate = set_rate_nop,
3692 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003693 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003694 .c = {
3695 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003696 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003697 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003698 CLK_INIT(mdp_vsync_clk.c),
3699 },
3700};
3701
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003702#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003703 { \
3704 .freq_hz = f, \
3705 .src_clk = &s##_clk.c, \
3706 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3707 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003708 }
3709static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003710 F_ROT( 0, gnd, 1),
3711 F_ROT( 27000000, pxo, 1),
3712 F_ROT( 29540000, pll8, 13),
3713 F_ROT( 32000000, pll8, 12),
3714 F_ROT( 38400000, pll8, 10),
3715 F_ROT( 48000000, pll8, 8),
3716 F_ROT( 54860000, pll8, 7),
3717 F_ROT( 64000000, pll8, 6),
3718 F_ROT( 76800000, pll8, 5),
3719 F_ROT( 96000000, pll8, 4),
3720 F_ROT(100000000, pll2, 8),
3721 F_ROT(114290000, pll2, 7),
3722 F_ROT(133330000, pll2, 6),
3723 F_ROT(160000000, pll2, 5),
3724 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003725 F_END
3726};
3727
3728static struct bank_masks bdiv_info_rot = {
3729 .bank_sel_mask = BIT(30),
3730 .bank0_mask = {
3731 .ns_mask = BM(25, 22) | BM(18, 16),
3732 },
3733 .bank1_mask = {
3734 .ns_mask = BM(29, 26) | BM(21, 19),
3735 },
3736};
3737
3738static struct rcg_clk rot_clk = {
3739 .b = {
3740 .ctl_reg = ROT_CC_REG,
3741 .en_mask = BIT(0),
3742 .reset_reg = SW_RESET_CORE_REG,
3743 .reset_mask = BIT(2),
3744 .halt_reg = DBG_BUS_VEC_C_REG,
3745 .halt_bit = 15,
3746 },
3747 .ns_reg = ROT_NS_REG,
3748 .root_en_mask = BIT(2),
3749 .set_rate = set_rate_div_banked,
3750 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003751 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003752 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003753 .c = {
3754 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003755 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003756 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003757 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003758 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003759 },
3760};
3761
3762static int hdmi_pll_clk_enable(struct clk *clk)
3763{
3764 int ret;
3765 unsigned long flags;
3766 spin_lock_irqsave(&local_clock_reg_lock, flags);
3767 ret = hdmi_pll_enable();
3768 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3769 return ret;
3770}
3771
3772static void hdmi_pll_clk_disable(struct clk *clk)
3773{
3774 unsigned long flags;
3775 spin_lock_irqsave(&local_clock_reg_lock, flags);
3776 hdmi_pll_disable();
3777 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3778}
3779
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07003780static unsigned long hdmi_pll_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003781{
3782 return hdmi_pll_get_rate();
3783}
3784
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003785static struct clk *hdmi_pll_clk_get_parent(struct clk *clk)
3786{
3787 return &pxo_clk.c;
3788}
3789
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003790static struct clk_ops clk_ops_hdmi_pll = {
3791 .enable = hdmi_pll_clk_enable,
3792 .disable = hdmi_pll_clk_disable,
3793 .get_rate = hdmi_pll_clk_get_rate,
3794 .is_local = local_clk_is_local,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003795 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003796};
3797
3798static struct clk hdmi_pll_clk = {
3799 .dbg_name = "hdmi_pll_clk",
3800 .ops = &clk_ops_hdmi_pll,
3801 CLK_INIT(hdmi_pll_clk),
3802};
3803
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003804#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003805 { \
3806 .freq_hz = f, \
3807 .src_clk = &s##_clk.c, \
3808 .md_val = MD8(8, m, 0, n), \
3809 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3810 .ctl_val = CC(6, n), \
3811 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003812 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003813#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003814 { \
3815 .freq_hz = f, \
3816 .src_clk = &s##_clk, \
3817 .md_val = MD8(8, m, 0, n), \
3818 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3819 .ctl_val = CC(6, n), \
3820 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003821 .extra_freq_data = (void *)p_r, \
3822 }
3823/* Switching TV freqs requires PLL reconfiguration. */
3824static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003825 F_TV_GND( 0, gnd, 0, 1, 0, 0),
3826 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
3827 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
3828 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
3829 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
3830 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003831 F_END
3832};
3833
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003834static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
3835 [VDD_DIG_LOW] = 74250000,
3836 [VDD_DIG_NOMINAL] = 149000000
3837};
3838
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003839/*
3840 * Unlike other clocks, the TV rate is adjusted through PLL
3841 * re-programming. It is also routed through an MND divider.
3842 */
3843void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3844{
3845 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3846 if (pll_rate)
3847 hdmi_pll_set_rate(pll_rate);
3848 set_rate_mnd(clk, nf);
3849}
3850
3851static struct rcg_clk tv_src_clk = {
3852 .ns_reg = TV_NS_REG,
3853 .b = {
3854 .ctl_reg = TV_CC_REG,
3855 .halt_check = NOCHECK,
3856 },
3857 .md_reg = TV_MD_REG,
3858 .root_en_mask = BIT(2),
3859 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
3860 .ctl_mask = BM(7, 6),
3861 .set_rate = set_rate_tv,
3862 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003863 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003864 .c = {
3865 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003866 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003867 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003868 CLK_INIT(tv_src_clk.c),
3869 },
3870};
3871
3872static struct branch_clk tv_enc_clk = {
3873 .b = {
3874 .ctl_reg = TV_CC_REG,
3875 .en_mask = BIT(8),
3876 .reset_reg = SW_RESET_CORE_REG,
3877 .reset_mask = BIT(0),
3878 .halt_reg = DBG_BUS_VEC_D_REG,
3879 .halt_bit = 9,
3880 },
3881 .parent = &tv_src_clk.c,
3882 .c = {
3883 .dbg_name = "tv_enc_clk",
3884 .ops = &clk_ops_branch,
3885 CLK_INIT(tv_enc_clk.c),
3886 },
3887};
3888
3889static struct branch_clk tv_dac_clk = {
3890 .b = {
3891 .ctl_reg = TV_CC_REG,
3892 .en_mask = BIT(10),
3893 .halt_reg = DBG_BUS_VEC_D_REG,
3894 .halt_bit = 10,
3895 },
3896 .parent = &tv_src_clk.c,
3897 .c = {
3898 .dbg_name = "tv_dac_clk",
3899 .ops = &clk_ops_branch,
3900 CLK_INIT(tv_dac_clk.c),
3901 },
3902};
3903
3904static struct branch_clk mdp_tv_clk = {
3905 .b = {
3906 .ctl_reg = TV_CC_REG,
3907 .en_mask = BIT(0),
3908 .reset_reg = SW_RESET_CORE_REG,
3909 .reset_mask = BIT(4),
3910 .halt_reg = DBG_BUS_VEC_D_REG,
3911 .halt_bit = 12,
3912 },
3913 .parent = &tv_src_clk.c,
3914 .c = {
3915 .dbg_name = "mdp_tv_clk",
3916 .ops = &clk_ops_branch,
3917 CLK_INIT(mdp_tv_clk.c),
3918 },
3919};
3920
3921static struct branch_clk hdmi_tv_clk = {
3922 .b = {
3923 .ctl_reg = TV_CC_REG,
3924 .en_mask = BIT(12),
3925 .reset_reg = SW_RESET_CORE_REG,
3926 .reset_mask = BIT(1),
3927 .halt_reg = DBG_BUS_VEC_D_REG,
3928 .halt_bit = 11,
3929 },
3930 .parent = &tv_src_clk.c,
3931 .c = {
3932 .dbg_name = "hdmi_tv_clk",
3933 .ops = &clk_ops_branch,
3934 CLK_INIT(hdmi_tv_clk.c),
3935 },
3936};
3937
3938static struct branch_clk hdmi_app_clk = {
3939 .b = {
3940 .ctl_reg = MISC_CC2_REG,
3941 .en_mask = BIT(11),
3942 .reset_reg = SW_RESET_CORE_REG,
3943 .reset_mask = BIT(11),
3944 .halt_reg = DBG_BUS_VEC_B_REG,
3945 .halt_bit = 25,
3946 },
3947 .c = {
3948 .dbg_name = "hdmi_app_clk",
3949 .ops = &clk_ops_branch,
3950 CLK_INIT(hdmi_app_clk.c),
3951 },
3952};
3953
3954static struct bank_masks bmnd_info_vcodec = {
3955 .bank_sel_mask = BIT(13),
3956 .bank0_mask = {
3957 .md_reg = VCODEC_MD0_REG,
3958 .ns_mask = BM(18, 11) | BM(2, 0),
3959 .rst_mask = BIT(31),
3960 .mnd_en_mask = BIT(5),
3961 .mode_mask = BM(7, 6),
3962 },
3963 .bank1_mask = {
3964 .md_reg = VCODEC_MD1_REG,
3965 .ns_mask = BM(26, 19) | BM(29, 27),
3966 .rst_mask = BIT(30),
3967 .mnd_en_mask = BIT(10),
3968 .mode_mask = BM(12, 11),
3969 },
3970};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003971#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003972 { \
3973 .freq_hz = f, \
3974 .src_clk = &s##_clk.c, \
3975 .md_val = MD8(8, m, 0, n), \
3976 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
3977 .ctl_val = CC_BANKED(6, 11, n), \
3978 .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003979 }
3980static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003981 F_VCODEC( 0, gnd, 0, 0),
3982 F_VCODEC( 27000000, pxo, 0, 0),
3983 F_VCODEC( 32000000, pll8, 1, 12),
3984 F_VCODEC( 48000000, pll8, 1, 8),
3985 F_VCODEC( 54860000, pll8, 1, 7),
3986 F_VCODEC( 96000000, pll8, 1, 4),
3987 F_VCODEC(133330000, pll2, 1, 6),
3988 F_VCODEC(200000000, pll2, 1, 4),
3989 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003990 F_END
3991};
3992
3993static struct rcg_clk vcodec_clk = {
3994 .b = {
3995 .ctl_reg = VCODEC_CC_REG,
3996 .en_mask = BIT(0),
3997 .reset_reg = SW_RESET_CORE_REG,
3998 .reset_mask = BIT(6),
3999 .halt_reg = DBG_BUS_VEC_C_REG,
4000 .halt_bit = 29,
4001 },
4002 .ns_reg = VCODEC_NS_REG,
4003 .root_en_mask = BIT(2),
4004 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004005 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004006 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004007 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004008 .c = {
4009 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004010 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004011 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4012 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004013 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004014 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004015 },
4016};
4017
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004018#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004019 { \
4020 .freq_hz = f, \
4021 .src_clk = &s##_clk.c, \
4022 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004023 }
4024static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004025 F_VPE( 0, gnd, 1),
4026 F_VPE( 27000000, pxo, 1),
4027 F_VPE( 34909000, pll8, 11),
4028 F_VPE( 38400000, pll8, 10),
4029 F_VPE( 64000000, pll8, 6),
4030 F_VPE( 76800000, pll8, 5),
4031 F_VPE( 96000000, pll8, 4),
4032 F_VPE(100000000, pll2, 8),
4033 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004034 F_END
4035};
4036
4037static struct rcg_clk vpe_clk = {
4038 .b = {
4039 .ctl_reg = VPE_CC_REG,
4040 .en_mask = BIT(0),
4041 .reset_reg = SW_RESET_CORE_REG,
4042 .reset_mask = BIT(17),
4043 .halt_reg = DBG_BUS_VEC_A_REG,
4044 .halt_bit = 28,
4045 },
4046 .ns_reg = VPE_NS_REG,
4047 .root_en_mask = BIT(2),
4048 .ns_mask = (BM(15, 12) | BM(2, 0)),
4049 .set_rate = set_rate_nop,
4050 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004051 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004052 .c = {
4053 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004054 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004055 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004056 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004057 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004058 },
4059};
4060
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004061#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004062 { \
4063 .freq_hz = f, \
4064 .src_clk = &s##_clk.c, \
4065 .md_val = MD8(8, m, 0, n), \
4066 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4067 .ctl_val = CC(6, n), \
4068 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004069 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004070
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004071static struct clk_freq_tbl clk_tbl_vfe[] = {
4072 F_VFE( 0, gnd, 1, 0, 0),
4073 F_VFE( 13960000, pll8, 1, 2, 55),
4074 F_VFE( 27000000, pxo, 1, 0, 0),
4075 F_VFE( 36570000, pll8, 1, 2, 21),
4076 F_VFE( 38400000, pll8, 2, 1, 5),
4077 F_VFE( 45180000, pll8, 1, 2, 17),
4078 F_VFE( 48000000, pll8, 2, 1, 4),
4079 F_VFE( 54860000, pll8, 1, 1, 7),
4080 F_VFE( 64000000, pll8, 2, 1, 3),
4081 F_VFE( 76800000, pll8, 1, 1, 5),
4082 F_VFE( 96000000, pll8, 2, 1, 2),
4083 F_VFE(109710000, pll8, 1, 2, 7),
4084 F_VFE(128000000, pll8, 1, 1, 3),
4085 F_VFE(153600000, pll8, 1, 2, 5),
4086 F_VFE(200000000, pll2, 2, 1, 2),
4087 F_VFE(228570000, pll2, 1, 2, 7),
4088 F_VFE(266667000, pll2, 1, 1, 3),
4089 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004090 F_END
4091};
4092
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004093static unsigned long fmax_vfe_8960_v2[MAX_VDD_LEVELS] __initdata = {
4094 [VDD_DIG_LOW] = 110000000,
4095 [VDD_DIG_NOMINAL] = 266667000,
4096 [VDD_DIG_HIGH] = 320000000
4097};
4098
4099static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4100 [VDD_DIG_LOW] = 128000000,
4101 [VDD_DIG_NOMINAL] = 266667000,
4102 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004103};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004104
4105static struct rcg_clk vfe_clk = {
4106 .b = {
4107 .ctl_reg = VFE_CC_REG,
4108 .reset_reg = SW_RESET_CORE_REG,
4109 .reset_mask = BIT(15),
4110 .halt_reg = DBG_BUS_VEC_B_REG,
4111 .halt_bit = 6,
4112 .en_mask = BIT(0),
4113 },
4114 .ns_reg = VFE_NS_REG,
4115 .md_reg = VFE_MD_REG,
4116 .root_en_mask = BIT(2),
4117 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
4118 .ctl_mask = BM(7, 6),
4119 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004120 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004121 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004122 .c = {
4123 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004124 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004125 VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004126 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004127 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004128 },
4129};
4130
Matt Wagantallc23eee92011-08-16 23:06:52 -07004131static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004132 .b = {
4133 .ctl_reg = VFE_CC_REG,
4134 .en_mask = BIT(12),
4135 .reset_reg = SW_RESET_CORE_REG,
4136 .reset_mask = BIT(24),
4137 .halt_reg = DBG_BUS_VEC_B_REG,
4138 .halt_bit = 8,
4139 },
4140 .parent = &vfe_clk.c,
4141 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004142 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004143 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004144 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004145 },
4146};
4147
4148/*
4149 * Low Power Audio Clocks
4150 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004151#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004152 { \
4153 .freq_hz = f, \
4154 .src_clk = &s##_clk.c, \
4155 .md_val = MD8(8, m, 0, n), \
4156 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4157 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004158 }
4159static struct clk_freq_tbl clk_tbl_aif_osr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004160 F_AIF_OSR( 0, gnd, 1, 0, 0),
4161 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4162 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4163 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4164 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4165 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4166 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4167 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4168 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4169 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4170 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4171 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004172 F_END
4173};
4174
4175#define CLK_AIF_OSR(i, ns, md, h_r) \
4176 struct rcg_clk i##_clk = { \
4177 .b = { \
4178 .ctl_reg = ns, \
4179 .en_mask = BIT(17), \
4180 .reset_reg = ns, \
4181 .reset_mask = BIT(19), \
4182 .halt_reg = h_r, \
4183 .halt_check = ENABLE, \
4184 .halt_bit = 1, \
4185 }, \
4186 .ns_reg = ns, \
4187 .md_reg = md, \
4188 .root_en_mask = BIT(9), \
4189 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4190 .set_rate = set_rate_mnd, \
4191 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004192 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004193 .c = { \
4194 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004195 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004196 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004197 CLK_INIT(i##_clk.c), \
4198 }, \
4199 }
4200#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4201 struct rcg_clk i##_clk = { \
4202 .b = { \
4203 .ctl_reg = ns, \
4204 .en_mask = BIT(21), \
4205 .reset_reg = ns, \
4206 .reset_mask = BIT(23), \
4207 .halt_reg = h_r, \
4208 .halt_check = ENABLE, \
4209 .halt_bit = 1, \
4210 }, \
4211 .ns_reg = ns, \
4212 .md_reg = md, \
4213 .root_en_mask = BIT(9), \
4214 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4215 .set_rate = set_rate_mnd, \
4216 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004217 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004218 .c = { \
4219 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004220 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004221 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004222 CLK_INIT(i##_clk.c), \
4223 }, \
4224 }
4225
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004226#define CLK_AIF_BIT(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004227 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004228 .b = { \
4229 .ctl_reg = ns, \
4230 .en_mask = BIT(15), \
4231 .halt_reg = h_r, \
4232 .halt_check = DELAY, \
4233 }, \
4234 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004235 .ext_mask = BIT(14), \
4236 .div_offset = 10, \
4237 .max_div = 16, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004238 .c = { \
4239 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004240 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004241 CLK_INIT(i##_clk.c), \
4242 }, \
4243 }
4244
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004245#define CLK_AIF_BIT_DIV(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004246 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004247 .b = { \
4248 .ctl_reg = ns, \
4249 .en_mask = BIT(19), \
4250 .halt_reg = h_r, \
4251 .halt_check = ENABLE, \
4252 }, \
4253 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004254 .ext_mask = BIT(18), \
4255 .div_offset = 10, \
4256 .max_div = 256, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004257 .c = { \
4258 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004259 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004260 CLK_INIT(i##_clk.c), \
4261 }, \
4262 }
4263
4264static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4265 LCC_MI2S_STATUS_REG);
4266static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4267
4268static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4269 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4270static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4271 LCC_CODEC_I2S_MIC_STATUS_REG);
4272
4273static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4274 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4275static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4276 LCC_SPARE_I2S_MIC_STATUS_REG);
4277
4278static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4279 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4280static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4281 LCC_CODEC_I2S_SPKR_STATUS_REG);
4282
4283static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4284 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4285static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4286 LCC_SPARE_I2S_SPKR_STATUS_REG);
4287
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004288#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004289 { \
4290 .freq_hz = f, \
4291 .src_clk = &s##_clk.c, \
4292 .md_val = MD16(m, n), \
4293 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4294 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004295 }
4296static struct clk_freq_tbl clk_tbl_pcm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004297 F_PCM( 0, gnd, 1, 0, 0),
4298 F_PCM( 512000, pll4, 4, 1, 192),
4299 F_PCM( 768000, pll4, 4, 1, 128),
4300 F_PCM( 1024000, pll4, 4, 1, 96),
4301 F_PCM( 1536000, pll4, 4, 1, 64),
4302 F_PCM( 2048000, pll4, 4, 1, 48),
4303 F_PCM( 3072000, pll4, 4, 1, 32),
4304 F_PCM( 4096000, pll4, 4, 1, 24),
4305 F_PCM( 6144000, pll4, 4, 1, 16),
4306 F_PCM( 8192000, pll4, 4, 1, 12),
4307 F_PCM(12288000, pll4, 4, 1, 8),
4308 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004309 F_END
4310};
4311
4312static struct rcg_clk pcm_clk = {
4313 .b = {
4314 .ctl_reg = LCC_PCM_NS_REG,
4315 .en_mask = BIT(11),
4316 .reset_reg = LCC_PCM_NS_REG,
4317 .reset_mask = BIT(13),
4318 .halt_reg = LCC_PCM_STATUS_REG,
4319 .halt_check = ENABLE,
4320 .halt_bit = 0,
4321 },
4322 .ns_reg = LCC_PCM_NS_REG,
4323 .md_reg = LCC_PCM_MD_REG,
4324 .root_en_mask = BIT(9),
4325 .ns_mask = (BM(31, 16) | BM(6, 0)),
4326 .set_rate = set_rate_mnd,
4327 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004328 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004329 .c = {
4330 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004331 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004332 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004333 CLK_INIT(pcm_clk.c),
4334 },
4335};
4336
4337static struct rcg_clk audio_slimbus_clk = {
4338 .b = {
4339 .ctl_reg = LCC_SLIMBUS_NS_REG,
4340 .en_mask = BIT(10),
4341 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4342 .reset_mask = BIT(5),
4343 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4344 .halt_check = ENABLE,
4345 .halt_bit = 0,
4346 },
4347 .ns_reg = LCC_SLIMBUS_NS_REG,
4348 .md_reg = LCC_SLIMBUS_MD_REG,
4349 .root_en_mask = BIT(9),
4350 .ns_mask = (BM(31, 24) | BM(6, 0)),
4351 .set_rate = set_rate_mnd,
4352 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004353 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004354 .c = {
4355 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004356 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004357 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004358 CLK_INIT(audio_slimbus_clk.c),
4359 },
4360};
4361
4362static struct branch_clk sps_slimbus_clk = {
4363 .b = {
4364 .ctl_reg = LCC_SLIMBUS_NS_REG,
4365 .en_mask = BIT(12),
4366 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4367 .halt_check = ENABLE,
4368 .halt_bit = 1,
4369 },
4370 .parent = &audio_slimbus_clk.c,
4371 .c = {
4372 .dbg_name = "sps_slimbus_clk",
4373 .ops = &clk_ops_branch,
4374 CLK_INIT(sps_slimbus_clk.c),
4375 },
4376};
4377
4378static struct branch_clk slimbus_xo_src_clk = {
4379 .b = {
4380 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4381 .en_mask = BIT(2),
4382 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004383 .halt_bit = 28,
4384 },
4385 .parent = &sps_slimbus_clk.c,
4386 .c = {
4387 .dbg_name = "slimbus_xo_src_clk",
4388 .ops = &clk_ops_branch,
4389 CLK_INIT(slimbus_xo_src_clk.c),
4390 },
4391};
4392
Matt Wagantall735f01a2011-08-12 12:40:28 -07004393DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4394DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4395DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4396DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4397DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4398DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4399DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4400DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004401
4402static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4403static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
Manu Gautam7483f172011-11-08 15:22:26 +05304404static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c);
4405static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004406static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4407static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4408static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4409static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4410static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4411static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
Stephen Boyd1c51a492011-10-26 12:11:47 -07004412static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c);
Stephen Boydef5d1c42011-12-15 20:47:14 -08004413static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004414
4415static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
Stephen Boyd36466ae2012-01-18 20:58:27 -08004416static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004417
4418#ifdef CONFIG_DEBUG_FS
4419struct measure_sel {
4420 u32 test_vector;
4421 struct clk *clk;
4422};
4423
Matt Wagantall8b38f942011-08-02 18:23:18 -07004424static DEFINE_CLK_MEASURE(l2_m_clk);
4425static DEFINE_CLK_MEASURE(krait0_m_clk);
4426static DEFINE_CLK_MEASURE(krait1_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004427static DEFINE_CLK_MEASURE(q6sw_clk);
4428static DEFINE_CLK_MEASURE(q6fw_clk);
4429static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004430
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004431static struct measure_sel measure_mux[] = {
4432 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4433 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4434 { TEST_PER_LS(0x13), &sdc1_clk.c },
4435 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4436 { TEST_PER_LS(0x15), &sdc2_clk.c },
4437 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4438 { TEST_PER_LS(0x17), &sdc3_clk.c },
4439 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4440 { TEST_PER_LS(0x19), &sdc4_clk.c },
4441 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4442 { TEST_PER_LS(0x1B), &sdc5_clk.c },
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004443 { TEST_PER_LS(0x1F), &gp0_clk.c },
4444 { TEST_PER_LS(0x20), &gp1_clk.c },
4445 { TEST_PER_LS(0x21), &gp2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004446 { TEST_PER_LS(0x25), &dfab_clk.c },
4447 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4448 { TEST_PER_LS(0x26), &pmem_clk.c },
4449 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4450 { TEST_PER_LS(0x33), &cfpb_clk.c },
4451 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4452 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4453 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4454 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4455 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4456 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4457 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4458 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4459 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4460 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4461 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4462 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4463 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4464 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4465 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4466 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4467 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4468 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4469 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4470 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4471 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4472 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4473 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4474 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4475 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4476 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4477 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4478 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4479 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4480 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4481 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4482 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4483 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4484 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4485 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4486 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4487 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004488 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4489 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4490 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4491 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4492 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4493 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4494 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4495 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4496 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004497 { TEST_PER_LS(0x78), &sfpb_clk.c },
4498 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4499 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4500 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4501 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4502 { TEST_PER_LS(0x7D), &prng_clk.c },
4503 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4504 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4505 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4506 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004507 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4508 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4509 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004510 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4511 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4512 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4513 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4514 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4515 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4516 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4517 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4518 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4519 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004520 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004521 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4522
4523 { TEST_PER_HS(0x07), &afab_clk.c },
4524 { TEST_PER_HS(0x07), &afab_a_clk.c },
4525 { TEST_PER_HS(0x18), &sfab_clk.c },
4526 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004527 { TEST_PER_HS(0x26), &q6sw_clk },
4528 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004529 { TEST_PER_HS(0x2A), &adm0_clk.c },
4530 { TEST_PER_HS(0x34), &ebi1_clk.c },
4531 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004532 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004533
4534 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4535 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4536 { TEST_MM_LS(0x02), &cam1_clk.c },
4537 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004538 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004539 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4540 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4541 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4542 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4543 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4544 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4545 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4546 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4547 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4548 { TEST_MM_LS(0x12), &imem_p_clk.c },
4549 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4550 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4551 { TEST_MM_LS(0x16), &rot_p_clk.c },
4552 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4553 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4554 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4555 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4556 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4557 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4558 { TEST_MM_LS(0x1D), &cam0_clk.c },
4559 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4560 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4561 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4562 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4563 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4564 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4565 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4566 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004567 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004568 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004569
4570 { TEST_MM_HS(0x00), &csi0_clk.c },
4571 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004572 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004573 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4574 { TEST_MM_HS(0x06), &vfe_clk.c },
4575 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4576 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4577 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4578 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4579 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4580 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4581 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4582 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4583 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4584 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4585 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4586 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4587 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4588 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4589 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4590 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4591 { TEST_MM_HS(0x1A), &mdp_clk.c },
4592 { TEST_MM_HS(0x1B), &rot_clk.c },
4593 { TEST_MM_HS(0x1C), &vpe_clk.c },
4594 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4595 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4596 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4597 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4598 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4599 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4600 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4601 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4602 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4603 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4604 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004605 { TEST_MM_HS(0x2D), &csi2_clk.c },
4606 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4607 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4608 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4609 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4610 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004611 { TEST_MM_HS(0x33), &vcap_clk.c },
4612 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004613 { TEST_MM_HS(0x36), &vcap_axi_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004614 { TEST_MM_HS(0x39), &gfx3d_axi_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004615
4616 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4617 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4618 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4619 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4620 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4621 { TEST_LPA(0x14), &pcm_clk.c },
4622 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004623
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004624 { TEST_LPA_HS(0x00), &q6_func_clk },
4625
Stephen Boyd46fdf0d2011-11-22 12:25:09 -08004626 { TEST_CPUL2(0x2), &l2_m_clk },
4627 { TEST_CPUL2(0x0), &krait0_m_clk },
4628 { TEST_CPUL2(0x1), &krait1_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004629};
4630
4631static struct measure_sel *find_measure_sel(struct clk *clk)
4632{
4633 int i;
4634
4635 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4636 if (measure_mux[i].clk == clk)
4637 return &measure_mux[i];
4638 return NULL;
4639}
4640
Matt Wagantall8b38f942011-08-02 18:23:18 -07004641static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004642{
4643 int ret = 0;
4644 u32 clk_sel;
4645 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004646 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004647 unsigned long flags;
4648
4649 if (!parent)
4650 return -EINVAL;
4651
4652 p = find_measure_sel(parent);
4653 if (!p)
4654 return -EINVAL;
4655
4656 spin_lock_irqsave(&local_clock_reg_lock, flags);
4657
Matt Wagantall8b38f942011-08-02 18:23:18 -07004658 /*
4659 * Program the test vector, measurement period (sample_ticks)
4660 * and scaling multiplier.
4661 */
4662 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004663 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004664 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004665 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4666 case TEST_TYPE_PER_LS:
4667 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4668 break;
4669 case TEST_TYPE_PER_HS:
4670 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4671 break;
4672 case TEST_TYPE_MM_LS:
4673 writel_relaxed(0x4030D97, CLK_TEST_REG);
4674 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4675 break;
4676 case TEST_TYPE_MM_HS:
4677 writel_relaxed(0x402B800, CLK_TEST_REG);
4678 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4679 break;
4680 case TEST_TYPE_LPA:
4681 writel_relaxed(0x4030D98, CLK_TEST_REG);
4682 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4683 LCC_CLK_LS_DEBUG_CFG_REG);
4684 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004685 case TEST_TYPE_LPA_HS:
4686 writel_relaxed(0x402BC00, CLK_TEST_REG);
4687 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4688 LCC_CLK_HS_DEBUG_CFG_REG);
4689 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004690 case TEST_TYPE_CPUL2:
4691 writel_relaxed(0x4030400, CLK_TEST_REG);
4692 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4693 clk->sample_ticks = 0x4000;
4694 clk->multiplier = 2;
4695 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004696 default:
4697 ret = -EPERM;
4698 }
4699 /* Make sure test vector is set before starting measurements. */
4700 mb();
4701
4702 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4703
4704 return ret;
4705}
4706
4707/* Sample clock for 'ticks' reference clock ticks. */
4708static u32 run_measurement(unsigned ticks)
4709{
4710 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004711 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4712
4713 /* Wait for timer to become ready. */
4714 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4715 cpu_relax();
4716
4717 /* Run measurement and wait for completion. */
4718 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4719 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4720 cpu_relax();
4721
4722 /* Stop counters. */
4723 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4724
4725 /* Return measured ticks. */
4726 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4727}
4728
4729
4730/* Perform a hardware rate measurement for a given clock.
4731 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004732static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004733{
4734 unsigned long flags;
4735 u32 pdm_reg_backup, ringosc_reg_backup;
4736 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004737 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004738 unsigned ret;
4739
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004740 ret = clk_enable(&cxo_clk.c);
4741 if (ret) {
4742 pr_warning("CXO clock failed to enable. Can't measure\n");
4743 return 0;
4744 }
4745
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004746 spin_lock_irqsave(&local_clock_reg_lock, flags);
4747
4748 /* Enable CXO/4 and RINGOSC branch and root. */
4749 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4750 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4751 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4752 writel_relaxed(0xA00, RINGOSC_NS_REG);
4753
4754 /*
4755 * The ring oscillator counter will not reset if the measured clock
4756 * is not running. To detect this, run a short measurement before
4757 * the full measurement. If the raw results of the two are the same
4758 * then the clock must be off.
4759 */
4760
4761 /* Run a short measurement. (~1 ms) */
4762 raw_count_short = run_measurement(0x1000);
4763 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004764 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004765
4766 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4767 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4768
4769 /* Return 0 if the clock is off. */
4770 if (raw_count_full == raw_count_short)
4771 ret = 0;
4772 else {
4773 /* Compute rate in Hz. */
4774 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004775 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4776 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004777 }
4778
4779 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004780 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004781 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4782
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004783 clk_disable(&cxo_clk.c);
4784
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004785 return ret;
4786}
4787#else /* !CONFIG_DEBUG_FS */
4788static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4789{
4790 return -EINVAL;
4791}
4792
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004793static unsigned long measure_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004794{
4795 return 0;
4796}
4797#endif /* CONFIG_DEBUG_FS */
4798
4799static struct clk_ops measure_clk_ops = {
4800 .set_parent = measure_clk_set_parent,
4801 .get_rate = measure_clk_get_rate,
4802 .is_local = local_clk_is_local,
4803};
4804
Matt Wagantall8b38f942011-08-02 18:23:18 -07004805static struct measure_clk measure_clk = {
4806 .c = {
4807 .dbg_name = "measure_clk",
4808 .ops = &measure_clk_ops,
4809 CLK_INIT(measure_clk.c),
4810 },
4811 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004812};
4813
Tianyi Goua8b3cce2011-11-08 14:37:26 -08004814static struct clk_lookup msm_clocks_8064[] = {
Tianyi Gou41515e22011-09-01 19:37:43 -07004815 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
Stephen Boyd98a82ed2012-01-11 18:31:54 -08004816 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
Stephen Boyd86f2e652012-01-11 18:25:44 -08004817 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004818 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07004819 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
Tianyi Gouc29c3242011-10-12 21:02:15 -07004820 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07004821 CLK_LOOKUP("measure", measure_clk.c, "debug"),
4822
Matt Wagantallb2710b82011-11-16 19:55:17 -08004823 CLK_DUMMY("bus_clk", AFAB_CLK, "msm_apps_fab", 0),
4824 CLK_DUMMY("bus_a_clk", AFAB_A_CLK, "msm_apps_fab", 0),
4825 CLK_DUMMY("bus_clk", SFAB_CLK, "msm_sys_fab", 0),
4826 CLK_DUMMY("bus_a_clk", SFAB_A_CLK, "msm_sys_fab", 0),
4827 CLK_DUMMY("bus_clk", SFPB_CLK, "msm_sys_fpb", 0),
4828 CLK_DUMMY("bus_a_clk", SFPB_A_CLK, "msm_sys_fpb", 0),
4829 CLK_DUMMY("bus_clk", MMFAB_CLK, "msm_mm_fab", 0),
4830 CLK_DUMMY("bus_a_clk", MMFAB_A_CLK, "msm_mm_fab", 0),
4831 CLK_DUMMY("bus_clk", CFPB_CLK, "msm_cpss_fpb", 0),
4832 CLK_DUMMY("bus_a_clk", CFPB_A_CLK, "msm_cpss_fpb", 0),
4833 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
4834 CLK_DUMMY("mem_a_clk", EBI1_A_CLK, "msm_bus", 0),
4835
4836 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
Tianyi Gou41515e22011-09-01 19:37:43 -07004837 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
4838 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
Matt Wagantallb2710b82011-11-16 19:55:17 -08004839 CLK_DUMMY("bus_clk", MMFPB_CLK, NULL, 0),
4840 CLK_DUMMY("bus_a_clk", MMFPB_A_CLK, NULL, 0),
Tianyi Gou41515e22011-09-01 19:37:43 -07004841
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004842 CLK_LOOKUP("core_clk", gp0_clk.c, NULL),
4843 CLK_LOOKUP("core_clk", gp1_clk.c, NULL),
4844 CLK_LOOKUP("core_clk", gp2_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07004845 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
4846 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
4847 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
4848 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
4849 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, NULL),
4850 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, NULL),
4851 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
4852 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, NULL),
4853 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
4854 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, NULL),
4855 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, NULL),
4856 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
4857 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
4858 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07004859 CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07004860 CLK_LOOKUP("pmem_clk", pmem_clk.c, NULL),
Ramesh Masavarapuf46be1b2011-11-03 11:13:41 -07004861 CLK_DUMMY("core_clk", PRNG_CLK, "msm_rng.0", OFF),
Tianyi Gou43208a02011-09-27 15:35:13 -07004862 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
4863 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
4864 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
4865 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07004866 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
4867 CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08004868 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
4869 CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"),
4870 CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"),
4871 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, NULL),
4872 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, NULL),
4873 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07004874 CLK_LOOKUP("iface_clk", ce1_p_clk.c, NULL),
4875 CLK_LOOKUP("core_clk", ce1_core_clk.c, NULL),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07004876 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07004877 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, NULL),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07004878 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
4879 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
4880 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
4881 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
4882 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
4883 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004884 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
4885 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
4886 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
4887 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, NULL),
4888 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, NULL),
4889 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, NULL),
4890 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
4891 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07004892 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08004893 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, NULL),
4894 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Manu Gautam7483f172011-11-08 15:22:26 +05304895 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"),
4896 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004897 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
4898 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
4899 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
4900 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004901 CLK_LOOKUP("iface_clk", pcie_p_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07004902 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
4903 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07004904 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
4905 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
4906 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
4907 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
4908 CLK_LOOKUP("core_clk", amp_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07004909 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
4910 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
4911 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
4912 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
4913 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07004914 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07004915 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
4916 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
4917 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07004918 CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07004919 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
4920 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
4921 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07004922 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07004923 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
4924 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
4925 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07004926 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, NULL),
4927 CLK_LOOKUP("csi_pix_clk", csi_pix1_clk.c, NULL),
4928 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, NULL),
4929 CLK_LOOKUP("csi_rdi_clk", csi_rdi1_clk.c, NULL),
4930 CLK_LOOKUP("csi_rdi_clk", csi_rdi2_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07004931 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
4932 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, NULL),
4933 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, NULL),
4934 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, NULL),
4935 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
4936 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
4937 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
4938 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
4939 CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
4940 CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
Pu Chen86b4be92011-11-03 17:27:57 -07004941 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004942 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
4943 CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004944 CLK_LOOKUP("iface_clk", vcap_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004945 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
4946 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004947 CLK_LOOKUP("core_clk", vcap_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004948 CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004949 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004950 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004951 CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
4952 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004953 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07004954 CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07004955 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004956 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004957 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08004958 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004959 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08004960 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07004961 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004962 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004963 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
Greg Griscofa47b532011-11-11 10:32:06 -08004964 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004965 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004966 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
Matt Wagantallb82a5132011-12-12 22:26:41 -08004967 CLK_DUMMY("tv_clk", MDP_TV_CLK, "footswitch-8x60.4", OFF),
Tianyi Gou41515e22011-09-01 19:37:43 -07004968 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07004969 CLK_LOOKUP("core_clk", hdmi_app_clk.c, NULL),
4970 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004971 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004972 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004973 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004974 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004975 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
4976 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
4977 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
4978 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
4979 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
4980 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
4981 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004982 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
4983 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
4984 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
4985 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
4986 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
4987 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Pu Chen86b4be92011-11-03 17:27:57 -07004988 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004989 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004990 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, NULL),
4991 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, NULL),
4992 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004993 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07004994 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
4995 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07004996 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07004997 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Tianyi Gou621f8742011-09-01 21:45:01 -07004998 CLK_LOOKUP("iface_clk", smmu_p_clk.c, NULL),
Matt Wagantallbb90da92011-10-25 15:07:52 -07004999 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005000 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Greg Griscofa47b532011-11-11 10:32:06 -08005001 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005002 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005003 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005004 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Tianyi Gou621f8742011-09-01 21:45:01 -07005005 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005006 CLK_LOOKUP("iface_pclk", vpe_p_clk.c, "footswitch-8x60.9"),
Tianyi Gouc29c3242011-10-12 21:02:15 -07005007 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
5008 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
5009 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
5010 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
5011 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
5012 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
5013 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
5014 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
5015 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
5016 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
5017 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
Tianyi Goudd8138a2011-10-20 15:46:00 -07005018 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5019 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005020 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, NULL),
5021 CLK_LOOKUP("core_clk", vpe_axi_clk.c, NULL),
5022 CLK_LOOKUP("core_clk", mdp_axi_clk.c, NULL),
5023 CLK_LOOKUP("core_clk", vcap_axi_clk.c, NULL),
5024 CLK_LOOKUP("core_clk", rot_axi_clk.c, NULL),
5025 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, NULL),
5026 CLK_LOOKUP("core_clk", vfe_axi_clk.c, NULL),
5027 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, NULL),
5028 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, NULL),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07005029 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005030 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
Manu Gautam5143b252012-01-05 19:25:23 -08005031 CLK_DUMMY("core_clk", DFAB_USB_HS_CLK, "msm_otg", 0),
5032 CLK_DUMMY("core_clk", DFAB_USB_HS3_CLK, "msm_ehci_host.0", 0),
5033 CLK_DUMMY("core_clk", DFAB_USB_HS4_CLK, "msm_ehci_host.1", 0),
Tianyi Gou41515e22011-09-01 19:37:43 -07005034 CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, NULL, 0),
5035 CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, NULL, 0),
5036 CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, NULL, 0),
5037 CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, NULL, 0),
5038 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
Stephen Boydef5d1c42011-12-15 20:47:14 -08005039 CLK_DUMMY("bus_clk", DFAB_SCM_CLK, "scm", 0),
Manu Gautam5143b252012-01-05 19:25:23 -08005040 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5041 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5042 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5043 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5044 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005045
Jeff Ohlstein8c116c72011-10-27 17:34:48 -07005046 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005047
5048 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
5049 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
5050 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
5051};
5052
Stephen Boyd94625ef2011-07-12 17:06:01 -07005053static struct clk_lookup msm_clocks_8960_v1[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005054 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
Stephen Boyd98a82ed2012-01-11 18:31:54 -08005055 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
Stephen Boyd86f2e652012-01-11 18:25:44 -08005056 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005057 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5058 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5059 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005060 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005061
Matt Wagantallb2710b82011-11-16 19:55:17 -08005062 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
5063 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
5064 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5065 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5066 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
5067 CLK_LOOKUP("bus_a_clk", sfab_a_clk.c, "msm_sys_fab"),
5068 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5069 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5070 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5071 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5072 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
5073 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
5074
5075 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
5076 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
5077 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
5078 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5079 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5080 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005081
Matt Wagantall7625a4c2011-11-01 16:17:53 -07005082 CLK_LOOKUP("core_clk", gp0_clk.c, NULL),
5083 CLK_LOOKUP("core_clk", gp1_clk.c, NULL),
5084 CLK_LOOKUP("core_clk", gp2_clk.c, NULL),
Matt Wagantalle2522372011-08-17 14:52:21 -07005085 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
5086 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
5087 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
5088 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
5089 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5090 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
5091 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
5092 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, NULL),
5093 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, NULL),
5094 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, NULL),
5095 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, NULL),
5096 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005097 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005098 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005099 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5100 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005101 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
5102 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
5103 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
5104 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, NULL),
5105 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005106 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005107 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005108 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005109 CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005110 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005111 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005112 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5113 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5114 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5115 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5116 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005117 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07005118 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005119 CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005120 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5121 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
5122 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, NULL),
5123 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, NULL),
5124 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, NULL),
5125 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, NULL),
5126 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, NULL),
5127 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, NULL),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005128 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005129 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005130 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005131 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005132 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005133 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005134 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005135 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5136 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005137 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5138 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005139 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
5140 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, NULL),
5141 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005142 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005143 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005144 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07005145 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005146 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, NULL),
5147 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, NULL),
5148 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005149 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5150 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5151 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5152 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5153 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005154 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5155 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005156 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
5157 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
5158 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
5159 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
5160 CLK_LOOKUP("core_clk", amp_clk.c, NULL),
Kevin Chan09f4e662011-12-16 08:17:02 -08005161 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
5162 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
5163 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005164 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5165 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5166 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5167 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5168 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5169 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
Kevin Chane12c6672011-10-26 11:55:26 -07005170 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5171 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
Kevin Chanf6216f22011-10-25 18:40:11 -07005172 CLK_LOOKUP("csiphy_timer_src_clk",
5173 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5174 CLK_LOOKUP("csiphy_timer_src_clk",
5175 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5176 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5177 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005178 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5179 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5180 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5181 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005182 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005183 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005184 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005185 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005186 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005187 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5188 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005189 CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005190 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005191 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005192 CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005193 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005194 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005195 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005196 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005197 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005198 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005199 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005200 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005201 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005202 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005203 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
5204 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005205 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005206 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005207 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005208 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005209 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005210 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Kevin Chana0853122011-11-07 19:48:44 -08005211 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005212 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chan5827c552011-10-28 18:36:32 -07005213 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005214 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chan5827c552011-10-28 18:36:32 -07005215 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005216 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5217 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5218 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5219 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5220 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5221 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5222 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005223 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005224 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5225 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005226 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5227 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5228 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5229 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005230 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005231 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005232 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005233 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005234 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005235 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005236 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5237 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005238 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005239 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005240 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005241 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005242 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005243 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005244 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005245 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005246 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005247 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005248 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005249 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chan5827c552011-10-28 18:36:32 -07005250 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005251 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chana0853122011-11-07 19:48:44 -08005252 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005253 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005254 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
5255 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
5256 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
5257 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
5258 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
5259 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
5260 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
5261 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
5262 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
5263 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
5264 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
5265 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5266 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
Matt Wagantalle604d712011-10-21 15:38:18 -07005267 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5268 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5269 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5270 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5271 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5272 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5273 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5274 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5275 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5276 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
5277 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5278 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005279
5280 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5281 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5282 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5283 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5284 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
5285
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005286 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005287 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005288 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5289 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5290 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5291 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5292 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005293 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005294 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Stephen Boydef5d1c42011-12-15 20:47:14 -08005295 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005296
Matt Wagantalle1a86062011-08-18 17:46:10 -07005297 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005298
5299 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
5300 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
5301 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
Stephen Boyd3939c8d2011-08-29 17:36:22 -07005302 CLK_LOOKUP("q6sw_clk", q6sw_clk, NULL),
5303 CLK_LOOKUP("q6fw_clk", q6fw_clk, NULL),
5304 CLK_LOOKUP("q6_func_clk", q6_func_clk, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005305};
5306
Stephen Boyd94625ef2011-07-12 17:06:01 -07005307static struct clk_lookup msm_clocks_8960_v2[] __initdata = {
5308 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
5309 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5310 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
Kevin Chane12c6672011-10-26 11:55:26 -07005311 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5312 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5313 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
Stephen Boyd94625ef2011-07-12 17:06:01 -07005314 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5315 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005316 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5317 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5318 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5319 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5320 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Stephen Boyd94625ef2011-07-12 17:06:01 -07005321};
5322
5323/* Add v2 clocks dynamically at runtime */
5324static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_v1) +
5325 ARRAY_SIZE(msm_clocks_8960_v2)];
5326
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005327/*
5328 * Miscellaneous clock register initializations
5329 */
5330
5331/* Read, modify, then write-back a register. */
5332static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5333{
5334 uint32_t regval = readl_relaxed(reg);
5335 regval &= ~mask;
5336 regval |= val;
5337 writel_relaxed(regval, reg);
5338}
5339
Tianyi Gou41515e22011-09-01 19:37:43 -07005340static void __init set_fsm_mode(void __iomem *mode_reg)
5341{
5342 u32 regval = readl_relaxed(mode_reg);
5343
5344 /*De-assert reset to FSM */
5345 regval &= ~BIT(21);
5346 writel_relaxed(regval, mode_reg);
5347
5348 /* Program bias count */
Tianyi Gou358c3862011-10-18 17:03:41 -07005349 regval &= ~BM(19, 14);
5350 regval |= BVAL(19, 14, 0x1);
5351 writel_relaxed(regval, mode_reg);
5352
5353 /* Program lock count */
Tianyi Gou41515e22011-09-01 19:37:43 -07005354 regval &= ~BM(13, 8);
5355 regval |= BVAL(13, 8, 0x8);
5356 writel_relaxed(regval, mode_reg);
5357
5358 /*Enable PLL FSM voting */
5359 regval |= BIT(20);
5360 writel_relaxed(regval, mode_reg);
5361}
5362
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005363static void __init reg_init(void)
5364{
Stephen Boydd471e7a2011-11-19 01:37:39 -08005365 void __iomem *imem_reg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005366 /* Deassert MM SW_RESET_ALL signal. */
5367 writel_relaxed(0, SW_RESET_ALL_REG);
5368
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005369 /*
5370 * Some bits are only used on either 8960 or 8064 and are marked as
5371 * reserved bits on the other SoC. Writing to these reserved bits
5372 * should have no effect.
5373 */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005374 /*
5375 * Initialize MM AHB registers: Enable the FPB clock and disable HW
5376 * gating on 8960v1/8064 for all clocks. Also set VFE_AHB's
5377 * FORCE_CORE_ON bit to prevent its memory from being collapsed when
5378 * the clock is halted. The sleep and wake-up delays are set to safe
5379 * values.
5380 */
5381 if (cpu_is_msm8960() &&
5382 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
5383 rmwreg(0x44000000, AHB_EN_REG, 0x6C000103);
5384 writel_relaxed(0x3C7097F9, AHB_EN2_REG);
5385 } else {
5386 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
5387 writel_relaxed(0x000007F9, AHB_EN2_REG);
5388 }
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005389 if (cpu_is_apq8064())
5390 rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005391
5392 /* Deassert all locally-owned MM AHB resets. */
5393 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07005394 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005395
5396 /* Initialize MM AXI registers: Enable HW gating for all clocks that
5397 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
5398 * delays to safe values. */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005399 if (cpu_is_msm8960() &&
5400 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) {
5401 rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF);
5402 rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -08005403 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08005404 } else {
5405 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
5406 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
5407 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
5408 }
Matt Wagantall53d968f2011-07-19 13:22:53 -07005409 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005410 if (cpu_is_apq8064())
5411 rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08005412 if (cpu_is_msm8960() &&
5413 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2)
5414 rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF);
5415 else
5416 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
5417
5418 /* Enable IMEM's clk_on signal */
5419 imem_reg = ioremap(0x04b00040, 4);
5420 if (imem_reg) {
5421 writel_relaxed(0x3, imem_reg);
5422 iounmap(imem_reg);
5423 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005424
5425 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
5426 * memories retain state even when not clocked. Also, set sleep and
5427 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005428 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
5429 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
5430 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
5431 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
5432 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
5433 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
Tarun Karra6fbc00a2011-12-13 09:23:47 -07005434 rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005435 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
5436 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
5437 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
5438 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
5439 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005440 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
5441 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
5442 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005443 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005444 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005445 if (cpu_is_msm8960() || cpu_is_msm8930()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005446 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
5447 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
5448 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
5449 }
5450 if (cpu_is_apq8064()) {
5451 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07005452 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005453 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005454
Tianyi Gou41515e22011-09-01 19:37:43 -07005455 /*
5456 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
5457 * core remain active during halt state of the clk. Also, set sleep
5458 * and wake-up value to max.
5459 */
5460 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005461 if (cpu_is_apq8064()) {
5462 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
5463 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
5464 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005465
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005466 /* De-assert MM AXI resets to all hardware blocks. */
5467 writel_relaxed(0, SW_RESET_AXI_REG);
5468
5469 /* Deassert all MM core resets. */
5470 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005471 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005472
5473 /* Reset 3D core once more, with its clock enabled. This can
5474 * eventually be done as part of the GDFS footswitch driver. */
5475 clk_set_rate(&gfx3d_clk.c, 27000000);
5476 clk_enable(&gfx3d_clk.c);
5477 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
5478 mb();
5479 udelay(5);
5480 writel_relaxed(0, SW_RESET_CORE_REG);
5481 /* Make sure reset is de-asserted before clock is disabled. */
5482 mb();
5483 clk_disable(&gfx3d_clk.c);
5484
5485 /* Enable TSSC and PDM PXO sources. */
5486 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
5487 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
5488
5489 /* Source SLIMBus xo src from slimbus reference clock */
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005490 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005491 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005492
5493 /* Source the dsi_byte_clks from the DSI PHY PLLs */
5494 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
5495 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07005496
5497 /* Source the sata_phy_ref_clk from PXO */
5498 if (cpu_is_apq8064())
5499 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
5500
5501 /*
5502 * TODO: Programming below PLLs is temporary and needs to be removed
5503 * after bootloaders program them.
5504 */
5505 if (cpu_is_apq8064()) {
5506 u32 regval, is_pll_enabled;
5507
5508 /* Program pxo_src_clk to source from PXO */
5509 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
5510
5511 /* Check if PLL8 is active */
5512 is_pll_enabled = readl_relaxed(BB_PLL8_STATUS_REG) & BIT(16);
5513 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005514 /* Ref clk = 27MHz and program pll8 to 384MHz */
5515 writel_relaxed(0xE, BB_PLL8_L_VAL_REG);
5516 writel_relaxed(0x2, BB_PLL8_M_VAL_REG);
5517 writel_relaxed(0x9, BB_PLL8_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005518
5519 regval = readl_relaxed(BB_PLL8_CONFIG_REG);
5520
5521 /* Enable the main output and the MN accumulator */
5522 regval |= BIT(23) | BIT(22);
5523
5524 /* Set pre-divider and post-divider values to 1 and 1 */
5525 regval &= ~BIT(19);
5526 regval &= ~BM(21, 20);
5527
5528 writel_relaxed(regval, BB_PLL8_CONFIG_REG);
5529
5530 /* Set VCO frequency */
5531 rmwreg(0x10000, BB_PLL8_CONFIG_REG, 0x30000);
5532
5533 /* Enable AUX output */
5534 regval = readl_relaxed(BB_PLL8_TEST_CTL_REG);
5535 regval |= BIT(12);
5536 writel_relaxed(regval, BB_PLL8_TEST_CTL_REG);
5537
5538 set_fsm_mode(BB_PLL8_MODE_REG);
5539 }
5540 /* Check if PLL3 is active */
5541 is_pll_enabled = readl_relaxed(GPLL1_STATUS_REG) & BIT(16);
5542 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005543 /* Ref clk = 27MHz and program pll3 to 1200MHz */
5544 writel_relaxed(0x2C, GPLL1_L_VAL_REG);
5545 writel_relaxed(0x4, GPLL1_M_VAL_REG);
5546 writel_relaxed(0x9, GPLL1_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005547
5548 regval = readl_relaxed(GPLL1_CONFIG_REG);
5549
5550 /* Set pre-divider and post-divider values to 1 and 1 */
5551 regval &= ~BIT(15);
5552 regval |= BIT(16);
5553
5554 writel_relaxed(regval, GPLL1_CONFIG_REG);
5555
5556 /* Set VCO frequency */
5557 rmwreg(0x180, GPLL1_CONFIG_REG, 0x180);
5558 }
5559 /* Check if PLL14 is active */
5560 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
5561 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005562 /* Ref clk = 27MHz and program pll14 to 480MHz */
5563 writel_relaxed(0x11, BB_PLL14_L_VAL_REG);
5564 writel_relaxed(0x7, BB_PLL14_M_VAL_REG);
5565 writel_relaxed(0x9, BB_PLL14_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005566
5567 regval = readl_relaxed(BB_PLL14_CONFIG_REG);
5568
5569 /* Enable the main output and the MN accumulator */
5570 regval |= BIT(23) | BIT(22);
5571
5572 /* Set pre-divider and post-divider values to 1 and 1 */
5573 regval &= ~BIT(19);
5574 regval &= ~BM(21, 20);
5575
5576 writel_relaxed(regval, BB_PLL14_CONFIG_REG);
5577
5578 /* Set VCO frequency */
5579 rmwreg(0x10000, BB_PLL14_CONFIG_REG, 0x30000);
5580
Tianyi Gou41515e22011-09-01 19:37:43 -07005581 set_fsm_mode(BB_PLL14_MODE_REG);
5582 }
Tianyi Gou621f8742011-09-01 21:45:01 -07005583 /* Program PLL2 to 800MHz with ref clk = 27MHz */
5584 writel_relaxed(0x1D, MM_PLL1_L_VAL_REG);
5585 writel_relaxed(0x11, MM_PLL1_M_VAL_REG);
5586 writel_relaxed(0x1B, MM_PLL1_N_VAL_REG);
5587
5588 regval = readl_relaxed(MM_PLL1_CONFIG_REG);
5589
5590 /* Enable the main output and the MN accumulator */
5591 regval |= BIT(23) | BIT(22);
5592
5593 /* Set pre-divider and post-divider values to 1 and 1 */
5594 regval &= ~BIT(19);
5595 regval &= ~BM(21, 20);
5596
5597 writel_relaxed(regval, MM_PLL1_CONFIG_REG);
5598
5599 /* Set VCO frequency */
5600 rmwreg(0x20000, MM_PLL1_CONFIG_REG, 0x30000);
5601
Tianyi Gou621f8742011-09-01 21:45:01 -07005602 /* Program PLL15 to 975MHz with ref clk = 27MHz */
5603 writel_relaxed(0x24, MM_PLL3_L_VAL_REG);
5604 writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
5605 writel_relaxed(0x9, MM_PLL3_N_VAL_REG);
5606
5607 regval = readl_relaxed(MM_PLL3_CONFIG_REG);
5608
5609 /* Enable the main output and the MN accumulator */
5610 regval |= BIT(23) | BIT(22);
5611
5612 /* Set pre-divider and post-divider values to 1 and 1 */
5613 regval &= ~BIT(19);
5614 regval &= ~BM(21, 20);
5615
5616 writel_relaxed(regval, MM_PLL3_CONFIG_REG);
5617
5618 /* Set VCO frequency */
5619 rmwreg(0x20000, MM_PLL3_CONFIG_REG, 0x30000);
5620
5621 /* Enable AUX output */
5622 regval = readl_relaxed(MM_PLL3_TEST_CTL_REG);
5623 regval |= BIT(12);
5624 writel_relaxed(regval, MM_PLL3_TEST_CTL_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005625
5626 /* Check if PLL4 is active */
5627 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
5628 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005629 /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
5630 writel_relaxed(0xE, LCC_PLL0_L_VAL_REG);
5631 writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG);
5632 writel_relaxed(0x465, LCC_PLL0_N_VAL_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005633
5634 regval = readl_relaxed(LCC_PLL0_CONFIG_REG);
5635
5636 /* Enable the main output and the MN accumulator */
5637 regval |= BIT(23) | BIT(22);
5638
5639 /* Set pre-divider and post-divider values to 1 and 1 */
5640 regval &= ~BIT(19);
5641 regval &= ~BM(21, 20);
5642
5643 /* Set VCO frequency */
5644 regval &= ~BM(17, 16);
5645 writel_relaxed(regval, LCC_PLL0_CONFIG_REG);
5646
5647 set_fsm_mode(LCC_PLL0_MODE_REG);
5648 }
5649
5650 /* Enable PLL4 source on the LPASS Primary PLL Mux */
5651 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005652 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005653}
5654
Stephen Boyd94625ef2011-07-12 17:06:01 -07005655struct clock_init_data msm8960_clock_init_data __initdata;
5656
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005657/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07005658static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005659{
Stephen Boyd94625ef2011-07-12 17:06:01 -07005660 size_t num_lookups = ARRAY_SIZE(msm_clocks_8960_v1);
Tianyi Gou41515e22011-09-01 19:37:43 -07005661
Tianyi Goubf3d0b12012-01-23 14:37:28 -08005662 if (cpu_is_msm8960() || cpu_is_apq8064())
5663 rpm_vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3;
5664 else if (cpu_is_msm8930() || cpu_is_msm8627())
5665 rpm_vreg_id_vdd_dig = RPM_VREG_ID_PM8038_S1;
5666 else
5667 BUG();
5668
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005669 xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960");
5670 if (IS_ERR(xo_pxo)) {
5671 pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
5672 BUG();
5673 }
Matt Wagantalled90b002011-12-12 21:22:43 -08005674 xo_cxo = msm_xo_get(MSM_XO_CXO, "clock-8960");
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005675 if (IS_ERR(xo_cxo)) {
5676 pr_err("%s: msm_xo_get(CXO) failed.\n", __func__);
5677 BUG();
5678 }
5679
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005680 if (cpu_is_msm8960() || cpu_is_msm8930()) {
Tianyi Gou41515e22011-09-01 19:37:43 -07005681 memcpy(msm_clocks_8960, msm_clocks_8960_v1,
5682 sizeof(msm_clocks_8960_v1));
5683 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
5684 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960_v2;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005685
5686 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8960_v2,
5687 sizeof(gfx3d_clk.c.fmax));
5688 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8960_v2,
5689 sizeof(ijpeg_clk.c.fmax));
5690 memcpy(vfe_clk.c.fmax, fmax_vfe_8960_v2,
5691 sizeof(vfe_clk.c.fmax));
5692
Tianyi Gou41515e22011-09-01 19:37:43 -07005693 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07005694 msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
Tianyi Gou41515e22011-09-01 19:37:43 -07005695 num_lookups = ARRAY_SIZE(msm_clocks_8960);
5696 }
5697 msm8960_clock_init_data.size = num_lookups;
Stephen Boyd94625ef2011-07-12 17:06:01 -07005698 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005699
5700 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005701 * Change the freq tables for and voltage requirements for
5702 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07005703 */
5704 if (cpu_is_apq8064()) {
5705 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005706
5707 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
5708 sizeof(gfx3d_clk.c.fmax));
5709 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
5710 sizeof(ijpeg_clk.c.fmax));
5711 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
5712 sizeof(ijpeg_clk.c.fmax));
5713 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
5714 sizeof(tv_src_clk.c.fmax));
5715 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
5716 sizeof(vfe_clk.c.fmax));
5717
Tianyi Gou621f8742011-09-01 21:45:01 -07005718 gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07005719 }
Stephen Boyd94625ef2011-07-12 17:06:01 -07005720
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005721 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005722
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07005723 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005724
5725 /* Initialize clock registers. */
5726 reg_init();
5727
5728 /* Initialize rates for clocks that only support one. */
5729 clk_set_rate(&pdm_clk.c, 27000000);
5730 clk_set_rate(&prng_clk.c, 64000000);
5731 clk_set_rate(&mdp_vsync_clk.c, 27000000);
5732 clk_set_rate(&tsif_ref_clk.c, 105000);
5733 clk_set_rate(&tssc_clk.c, 27000000);
5734 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07005735 if (cpu_is_apq8064()) {
5736 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
5737 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
5738 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005739 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005740 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou41515e22011-09-01 19:37:43 -07005741 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005742 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
5743 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
5744 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07005745 /*
5746 * Set the CSI rates to a safe default to avoid warnings when
5747 * switching csi pix and rdi clocks.
5748 */
5749 clk_set_rate(&csi0_src_clk.c, 27000000);
5750 clk_set_rate(&csi1_src_clk.c, 27000000);
5751 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005752
5753 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07005754 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005755 * Toggle these clocks on and off to refresh them.
5756 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07005757 rcg_clk_enable(&pdm_clk.c);
5758 rcg_clk_disable(&pdm_clk.c);
5759 rcg_clk_enable(&tssc_clk.c);
5760 rcg_clk_disable(&tssc_clk.c);
Stephen Boyd60496bb2011-10-17 13:51:37 -07005761 if (cpu_is_msm8960() &&
5762 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
5763 clk_enable(&usb_hsic_hsic_clk.c);
5764 clk_disable(&usb_hsic_hsic_clk.c);
Stephen Boyd092fd182011-10-21 15:56:30 -07005765 } else
5766 /* CSI2 hardware not present on 8960v1 devices */
5767 pix_rdi_mux_map[2] = NULL;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005768
5769 if (machine_is_msm8960_sim()) {
5770 clk_set_rate(&sdc1_clk.c, 48000000);
5771 clk_enable(&sdc1_clk.c);
5772 clk_enable(&sdc1_p_clk.c);
5773 clk_set_rate(&sdc3_clk.c, 48000000);
5774 clk_enable(&sdc3_clk.c);
5775 clk_enable(&sdc3_p_clk.c);
5776 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005777}
5778
Stephen Boydbb600ae2011-08-02 20:11:40 -07005779static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005780{
Stephen Boyda3787f32011-09-16 18:55:13 -07005781 int rc;
5782 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07005783 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07005784
5785 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
5786 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
5787 PTR_ERR(mmfpb_a_clk)))
5788 return PTR_ERR(mmfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08005789 rc = clk_set_rate(mmfpb_a_clk, 76800000);
Stephen Boyda3787f32011-09-16 18:55:13 -07005790 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
5791 return rc;
5792 rc = clk_enable(mmfpb_a_clk);
5793 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
5794 return rc;
5795
Stephen Boyd85436132011-09-16 18:55:13 -07005796 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
5797 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
5798 PTR_ERR(cfpb_a_clk)))
5799 return PTR_ERR(cfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08005800 rc = clk_set_rate(cfpb_a_clk, 64000000);
Stephen Boyd85436132011-09-16 18:55:13 -07005801 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
5802 return rc;
5803 rc = clk_enable(cfpb_a_clk);
5804 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
5805 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005806
5807 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005808}
Stephen Boydbb600ae2011-08-02 20:11:40 -07005809
5810struct clock_init_data msm8960_clock_init_data __initdata = {
5811 .table = msm_clocks_8960,
5812 .size = ARRAY_SIZE(msm_clocks_8960),
5813 .init = msm8960_clock_init,
5814 .late_init = msm8960_clock_late_init,
5815};
Tianyi Gou41515e22011-09-01 19:37:43 -07005816
5817struct clock_init_data apq8064_clock_init_data __initdata = {
5818 .table = msm_clocks_8064,
5819 .size = ARRAY_SIZE(msm_clocks_8064),
5820 .init = msm8960_clock_init,
5821 .late_init = msm8960_clock_late_init,
5822};