Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_x86.h" |
| 18 | #include "dex/quick/mir_to_lir-inl.h" |
| 19 | #include "x86_lir.h" |
| 20 | |
| 21 | namespace art { |
| 22 | |
| 23 | #define MAX_ASSEMBLER_RETRIES 50 |
| 24 | |
| 25 | const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 26 | { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4, false }, "data", "0x!0d" }, |
| 27 | { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0, false }, "int 3", "" }, |
| 28 | { kX86Nop, kNop, NO_OPERAND, { 0, 0, 0x90, 0, 0, 0, 0, 0, false }, "nop", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | |
| 30 | #define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ |
| 31 | rm8_r8, rm32_r32, \ |
| 32 | r8_rm8, r32_rm32, \ |
| 33 | ax8_i8, ax32_i32, \ |
| 34 | rm8_i8, rm8_i8_modrm, \ |
| 35 | rm32_i32, rm32_i32_modrm, \ |
| 36 | rm32_i8, rm32_i8_modrm) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 37 | { kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8MR", "[!0r+!1d],!2r" }, \ |
| 38 | { kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true}, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 39 | { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \ |
| 40 | { kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RR", "!0r,!1r" }, \ |
| 41 | { kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RM", "!0r,[!1r+!2d]" }, \ |
| 42 | { kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 43 | { kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RT", "!0r,fs:[!1d]" }, \ |
| 44 | { kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1, true }, #opname "8RI", "!0r,!1d" }, \ |
| 45 | { kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \ |
| 46 | { kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 47 | { kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8TI", "fs:[!0d],!1d" }, \ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 48 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 49 | { kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16MR", "[!0r+!1d],!2r" }, \ |
| 50 | { kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 51 | { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \ |
| 52 | { kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RR", "!0r,!1r" }, \ |
| 53 | { kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RM", "!0r,[!1r+!2d]" }, \ |
| 54 | { kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 55 | { kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RT", "!0r,fs:[!1d]" }, \ |
| 56 | { kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2, false }, #opname "16RI", "!0r,!1d" }, \ |
| 57 | { kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ |
| 58 | { kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 59 | { kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16TI", "fs:[!0d],!1d" }, \ |
| 60 | { kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16RI8", "!0r,!1d" }, \ |
| 61 | { kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16MI8", "[!0r+!1d],!2d" }, \ |
| 62 | { kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 63 | { kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16TI8", "fs:[!0d],!1d" }, \ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 64 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 65 | { kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32MR", "[!0r+!1d],!2r" }, \ |
| 66 | { kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 67 | { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \ |
| 68 | { kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RR", "!0r,!1r" }, \ |
| 69 | { kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RM", "!0r,[!1r+!2d]" }, \ |
| 70 | { kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 71 | { kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RT", "!0r,fs:[!1d]" }, \ |
| 72 | { kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "32RI", "!0r,!1d" }, \ |
| 73 | { kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ |
| 74 | { kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 75 | { kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32TI", "fs:[!0d],!1d" }, \ |
| 76 | { kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32RI8", "!0r,!1d" }, \ |
| 77 | { kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32MI8", "[!0r+!1d],!2d" }, \ |
| 78 | { kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 79 | { kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32TI8", "fs:[!0d],!1d" }, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 80 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 81 | { kX86 ## opname ## 64MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64MR", "[!0r+!1d],!2r" }, \ |
| 82 | { kX86 ## opname ## 64AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 83 | { kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \ |
| 84 | { kX86 ## opname ## 64RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RR", "!0r,!1r" }, \ |
| 85 | { kX86 ## opname ## 64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RM", "!0r,[!1r+!2d]" }, \ |
| 86 | { kX86 ## opname ## 64RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 87 | { kX86 ## opname ## 64RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RT", "!0r,fs:[!1d]" }, \ |
| 88 | { kX86 ## opname ## 64RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "64RI", "!0r,!1d" }, \ |
| 89 | { kX86 ## opname ## 64MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ |
| 90 | { kX86 ## opname ## 64AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 91 | { kX86 ## opname ## 64TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64TI", "fs:[!0d],!1d" }, \ |
| 92 | { kX86 ## opname ## 64RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64RI8", "!0r,!1d" }, \ |
| 93 | { kX86 ## opname ## 64MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64MI8", "[!0r+!1d],!2d" }, \ |
| 94 | { kX86 ## opname ## 64AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 95 | { kX86 ## opname ## 64TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64TI8", "fs:[!0d],!1d" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 96 | |
| 97 | ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 98 | 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, |
| 99 | 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, |
| 100 | 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, |
| 101 | 0x80, 0x0 /* RegMem8/imm8 */, |
| 102 | 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), |
| 103 | ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 104 | 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, |
| 105 | 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, |
| 106 | 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, |
| 107 | 0x80, 0x1 /* RegMem8/imm8 */, |
| 108 | 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), |
| 109 | ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, |
| 110 | 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, |
| 111 | 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, |
| 112 | 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, |
| 113 | 0x80, 0x2 /* RegMem8/imm8 */, |
| 114 | 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), |
| 115 | ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, |
| 116 | 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, |
| 117 | 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, |
| 118 | 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, |
| 119 | 0x80, 0x3 /* RegMem8/imm8 */, |
| 120 | 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), |
| 121 | ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 122 | 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, |
| 123 | 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, |
| 124 | 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, |
| 125 | 0x80, 0x4 /* RegMem8/imm8 */, |
| 126 | 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), |
| 127 | ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 128 | 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, |
| 129 | 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, |
| 130 | 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, |
| 131 | 0x80, 0x5 /* RegMem8/imm8 */, |
| 132 | 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), |
| 133 | ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 134 | 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, |
| 135 | 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, |
| 136 | 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, |
| 137 | 0x80, 0x6 /* RegMem8/imm8 */, |
| 138 | 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), |
| 139 | ENCODING_MAP(Cmp, IS_LOAD, 0, 0, |
| 140 | 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, |
| 141 | 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, |
| 142 | 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, |
| 143 | 0x80, 0x7 /* RegMem8/imm8 */, |
| 144 | 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), |
| 145 | #undef ENCODING_MAP |
| 146 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 147 | { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RRI", "!0r,!1r,!2d" }, |
| 148 | { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, |
| 149 | { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 150 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 151 | { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RRI", "!0r,!1r,!2d" }, |
| 152 | { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, |
| 153 | { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 154 | { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RRI8", "!0r,!1r,!2d" }, |
| 155 | { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, |
| 156 | { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 157 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 158 | { kX86Imul64RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RRI", "!0r,!1r,!2d" }, |
| 159 | { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RMI", "!0r,[!1r+!2d],!3d" }, |
| 160 | { kX86Imul64RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 161 | { kX86Imul64RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RRI8", "!0r,!1r,!2d" }, |
| 162 | { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" }, |
| 163 | { kX86Imul64RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 164 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 165 | { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8MR", "[!0r+!1d],!2r" }, |
| 166 | { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 167 | { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8TR", "fs:[!0d],!1r" }, |
| 168 | { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RR", "!0r,!1r" }, |
| 169 | { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RM", "!0r,[!1r+!2d]" }, |
| 170 | { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 171 | { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RT", "!0r,fs:[!1d]" }, |
| 172 | { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1, true }, "Mov8RI", "!0r,!1d" }, |
| 173 | { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8MI", "[!0r+!1d],!2d" }, |
| 174 | { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 175 | { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8TI", "fs:[!0d],!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 176 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 177 | { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16MR", "[!0r+!1d],!2r" }, |
| 178 | { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 179 | { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0, false }, "Mov16TR", "fs:[!0d],!1r" }, |
| 180 | { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RR", "!0r,!1r" }, |
| 181 | { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RM", "!0r,[!1r+!2d]" }, |
| 182 | { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 183 | { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RT", "!0r,fs:[!1d]" }, |
| 184 | { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2, false }, "Mov16RI", "!0r,!1d" }, |
| 185 | { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16MI", "[!0r+!1d],!2d" }, |
| 186 | { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 187 | { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16TI", "fs:[!0d],!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 188 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 189 | { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32MR", "[!0r+!1d],!2r" }, |
| 190 | { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 191 | { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32TR", "fs:[!0d],!1r" }, |
| 192 | { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RR", "!0r,!1r" }, |
| 193 | { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RM", "!0r,[!1r+!2d]" }, |
| 194 | { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 195 | { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RT", "!0r,fs:[!1d]" }, |
| 196 | { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "Mov32RI", "!0r,!1d" }, |
| 197 | { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32MI", "[!0r+!1d],!2d" }, |
| 198 | { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 199 | { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32TI", "fs:[!0d],!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 200 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 201 | { kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RM", "!0r,[!1r+!2d]" }, |
| 202 | { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 203 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 204 | { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64MR", "[!0r+!1d],!2r" }, |
| 205 | { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 206 | { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0, false }, "Mov64TR", "fs:[!0d],!1r" }, |
| 207 | { kX86Mov64RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RR", "!0r,!1r" }, |
| 208 | { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" }, |
| 209 | { kX86Mov64RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 210 | { kX86Mov64RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RT", "!0r,fs:[!1d]" }, |
| 211 | { kX86Mov64RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { REX_W, 0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI", "!0r,!1d" }, |
| 212 | { kX86Mov64MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64MI", "[!0r+!1d],!2d" }, |
| 213 | { kX86Mov64AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 214 | { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64TI", "fs:[!0d],!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 215 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 216 | { kX86Lea64RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RM", "!0r,[!1r+!2d]" }, |
| 217 | { kX86Lea64RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 218 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 219 | { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RR", "!2c !0r,!1r" }, |
| 220 | { kX86Cmov64RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RR", "!2c !0r,!1r" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 221 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 222 | { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" }, |
| 223 | { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" }, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 224 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 225 | #define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 226 | { kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8RI", "!0r,!1d" }, \ |
| 227 | { kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \ |
| 228 | { kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 229 | { kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8RC", "!0r,cl" }, \ |
| 230 | { kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8MC", "[!0r+!1d],cl" }, \ |
| 231 | { kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 232 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 233 | { kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16RI", "!0r,!1d" }, \ |
| 234 | { kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ |
| 235 | { kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 236 | { kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16RC", "!0r,cl" }, \ |
| 237 | { kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16MC", "[!0r+!1d],cl" }, \ |
| 238 | { kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 239 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 240 | { kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32RI", "!0r,!1d" }, \ |
| 241 | { kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ |
| 242 | { kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 243 | { kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32RC", "!0r,cl" }, \ |
| 244 | { kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32MC", "[!0r+!1d],cl" }, \ |
| 245 | { kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 246 | \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 247 | { kX86 ## opname ## 64RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64RI", "!0r,!1d" }, \ |
| 248 | { kX86 ## opname ## 64MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ |
| 249 | { kX86 ## opname ## 64AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 250 | { kX86 ## opname ## 64RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64RC", "!0r,cl" }, \ |
| 251 | { kX86 ## opname ## 64MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64MC", "[!0r+!1d],cl" }, \ |
| 252 | { kX86 ## opname ## 64AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64AC", "[!0r+!1r<<!2d+!3d],cl" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 253 | |
| 254 | SHIFT_ENCODING_MAP(Rol, 0x0), |
| 255 | SHIFT_ENCODING_MAP(Ror, 0x1), |
| 256 | SHIFT_ENCODING_MAP(Rcl, 0x2), |
| 257 | SHIFT_ENCODING_MAP(Rcr, 0x3), |
| 258 | SHIFT_ENCODING_MAP(Sal, 0x4), |
| 259 | SHIFT_ENCODING_MAP(Shr, 0x5), |
| 260 | SHIFT_ENCODING_MAP(Sar, 0x7), |
| 261 | #undef SHIFT_ENCODING_MAP |
| 262 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 263 | { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0, false }, "Cmc", "" }, |
| 264 | { kX86Shld32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32RRI", "!0r,!1r,!2d" }, |
| 265 | { kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32MRI", "[!0r+!1d],!2r,!3d" }, |
| 266 | { kX86Shrd32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32RRI", "!0r,!1r,!2d" }, |
| 267 | { kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32MRI", "[!0r+!1d],!2r,!3d" }, |
| 268 | { kX86Shld64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64RRI", "!0r,!1r,!2d" }, |
| 269 | { kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64MRI", "[!0r+!1d],!2r,!3d" }, |
| 270 | { kX86Shrd64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64RRI", "!0r,!1r,!2d" }, |
| 271 | { kX86Shrd64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64MRI", "[!0r+!1d],!2r,!3d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 272 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 273 | { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8RI", "!0r,!1d" }, |
| 274 | { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8MI", "[!0r+!1d],!2d" }, |
| 275 | { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 276 | { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16RI", "!0r,!1d" }, |
| 277 | { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16MI", "[!0r+!1d],!2d" }, |
| 278 | { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 279 | { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32RI", "!0r,!1d" }, |
| 280 | { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32MI", "[!0r+!1d],!2d" }, |
| 281 | { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 282 | { kX86Test64RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64RI", "!0r,!1d" }, |
| 283 | { kX86Test64MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64MI", "[!0r+!1d],!2d" }, |
| 284 | { kX86Test64AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 285 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 286 | { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RR", "!0r,!1r" }, |
| 287 | { kX86Test64RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test64RR", "!0r,!1r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 288 | |
| 289 | #define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ |
| 290 | reg, reg_kind, reg_flags, \ |
| 291 | mem, mem_kind, mem_flags, \ |
| 292 | arr, arr_kind, arr_flags, imm, \ |
| 293 | b_flags, hw_flags, w_flags, \ |
| 294 | b_format, hw_format, w_format) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 295 | { kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \ |
| 296 | { kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \ |
| 297 | { kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 298 | { kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \ |
| 299 | { kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \ |
| 300 | { kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 301 | { kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \ |
| 302 | { kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \ |
| 303 | { kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 304 | { kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #reg, w_format "!0r" }, \ |
| 305 | { kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #mem, w_format "[!0r+!1d]" }, \ |
| 306 | { kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 307 | |
| 308 | UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), |
| 309 | UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), |
| 310 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 311 | UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), |
| 312 | UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), |
| 313 | UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), |
| 314 | UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 315 | #undef UNARY_ENCODING_MAP |
| 316 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 317 | { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cdq", "" }, |
| 318 | { kx86Cqo64Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { REX_W, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cqo", "" }, |
| 319 | { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap32R", "!0r" }, |
| 320 | { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0, false }, "Push32R", "!0r" }, |
| 321 | { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0, false }, "Pop32R", "!0r" }, |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 322 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 323 | #define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 324 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ |
| 325 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 326 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 327 | |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 328 | #define EXT_0F_REX_W_ENCODING_MAP(opname, prefix, opcode, reg_def) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 329 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ |
| 330 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 331 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 332 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 333 | #define EXT_0F_ENCODING2_MAP(opname, prefix, opcode, opcode2, reg_def) \ |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 334 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ |
| 335 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 336 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 337 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 338 | EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 339 | { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdMR", "[!0r+!1d],!2r" }, |
| 340 | { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 341 | |
| 342 | EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 343 | { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssMR", "[!0r+!1d],!2r" }, |
| 344 | { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 345 | |
| 346 | EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), |
| 347 | EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 348 | EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2sd, 0xF2, 0x2A, REG_DEF0), |
| 349 | EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2ss, 0xF3, 0x2A, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 350 | EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), |
| 351 | EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 352 | EXT_0F_REX_W_ENCODING_MAP(Cvttsd2sqi, 0xF2, 0x2C, REG_DEF0), |
| 353 | EXT_0F_REX_W_ENCODING_MAP(Cvttss2sqi, 0xF3, 0x2C, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 354 | EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), |
| 355 | EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 356 | EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0), |
| 357 | EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0), |
| 358 | EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0), |
| 359 | EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0), |
| 360 | EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0), |
| 361 | EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0), |
| 362 | EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0), |
| 363 | EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0), |
| 364 | EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0), |
| 365 | EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 366 | EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), |
| 367 | EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 368 | EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0), |
| 369 | EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0), |
| 370 | EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0), |
| 371 | EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0), |
| 372 | EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0), |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 373 | EXT_0F_ENCODING_MAP(Sqrtsd, 0xF2, 0x51, REG_DEF0_USE0), |
| 374 | EXT_0F_ENCODING2_MAP(Pmulld, 0x66, 0x38, 0x40, REG_DEF0_USE0), |
| 375 | EXT_0F_ENCODING_MAP(Pmullw, 0x66, 0xD5, REG_DEF0_USE0), |
| 376 | EXT_0F_ENCODING_MAP(Mulps, 0x00, 0x59, REG_DEF0_USE0), |
| 377 | EXT_0F_ENCODING_MAP(Mulpd, 0x66, 0x59, REG_DEF0_USE0), |
| 378 | EXT_0F_ENCODING_MAP(Paddb, 0x66, 0xFC, REG_DEF0_USE0), |
| 379 | EXT_0F_ENCODING_MAP(Paddw, 0x66, 0xFD, REG_DEF0_USE0), |
| 380 | EXT_0F_ENCODING_MAP(Paddd, 0x66, 0xFE, REG_DEF0_USE0), |
| 381 | EXT_0F_ENCODING_MAP(Addps, 0x00, 0x58, REG_DEF0_USE0), |
| 382 | EXT_0F_ENCODING_MAP(Addpd, 0xF2, 0x58, REG_DEF0_USE0), |
| 383 | EXT_0F_ENCODING_MAP(Psubb, 0x66, 0xF8, REG_DEF0_USE0), |
| 384 | EXT_0F_ENCODING_MAP(Psubw, 0x66, 0xF9, REG_DEF0_USE0), |
| 385 | EXT_0F_ENCODING_MAP(Psubd, 0x66, 0xFA, REG_DEF0_USE0), |
| 386 | EXT_0F_ENCODING_MAP(Subps, 0x00, 0x5C, REG_DEF0_USE0), |
| 387 | EXT_0F_ENCODING_MAP(Subpd, 0x66, 0x5C, REG_DEF0_USE0), |
| 388 | EXT_0F_ENCODING_MAP(Pand, 0x66, 0xDB, REG_DEF0_USE0), |
| 389 | EXT_0F_ENCODING_MAP(Por, 0x66, 0xEB, REG_DEF0_USE0), |
| 390 | EXT_0F_ENCODING_MAP(Pxor, 0x66, 0xEF, REG_DEF0_USE0), |
| 391 | EXT_0F_ENCODING2_MAP(Phaddw, 0x66, 0x38, 0x01, REG_DEF0_USE0), |
| 392 | EXT_0F_ENCODING2_MAP(Phaddd, 0x66, 0x38, 0x02, REG_DEF0_USE0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 393 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 394 | { kX86PextrbRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x14, 0, 0, 1, false }, "PextbRRI", "!0r,!1r,!2d" }, |
| 395 | { kX86PextrwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC5, 0x00, 0, 0, 1, false }, "PextwRRI", "!0r,!1r,!2d" }, |
| 396 | { kX86PextrdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextdRRI", "!0r,!1r,!2d" }, |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 397 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 398 | { kX86PshuflwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0xF2, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuflwRRI", "!0r,!1r,!2d" }, |
| 399 | { kX86PshufdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuffRRI", "!0r,!1r,!2d" }, |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 400 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 401 | { kX86PsrawRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 4, 0, 1, false }, "PsrawRI", "!0r,!1d" }, |
| 402 | { kX86PsradRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 4, 0, 1, false }, "PsradRI", "!0r,!1d" }, |
| 403 | { kX86PsrlwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 2, 0, 1, false }, "PsrlwRI", "!0r,!1d" }, |
| 404 | { kX86PsrldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 2, 0, 1, false }, "PsrldRI", "!0r,!1d" }, |
| 405 | { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1, false }, "PsrlqRI", "!0r,!1d" }, |
| 406 | { kX86PsllwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 6, 0, 1, false }, "PsllwRI", "!0r,!1d" }, |
| 407 | { kX86PslldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 6, 0, 1, false }, "PslldRI", "!0r,!1d" }, |
| 408 | { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1, false }, "PsllqRI", "!0r,!1d" }, |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 409 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 410 | { kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0, false }, "Fild32M", "[!0r,!1d]" }, |
| 411 | { kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0, false }, "Fild64M", "[!0r,!1d]" }, |
| 412 | { kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0, false }, "FstpsM", "[!0r,!1d]" }, |
| 413 | { kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0, false }, "FstpdM", "[!0r,!1d]" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 414 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 415 | EXT_0F_ENCODING_MAP(Mova128, 0x66, 0x6F, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 416 | { kX86Mova128MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128MR", "[!0r+!1d],!2r" }, |
| 417 | { kX86Mova128AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 418 | |
| 419 | |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 420 | EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 421 | { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsMR", "[!0r+!1d],!2r" }, |
| 422 | { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 423 | |
| 424 | EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 425 | { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsMR", "[!0r+!1d],!2r" }, |
| 426 | { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 427 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 428 | { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRM", "!0r,[!1r+!2d]" }, |
| 429 | { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 430 | { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsMR", "[!0r+!1d],!2r" }, |
| 431 | { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 432 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 433 | { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRM", "!0r,[!1r+!2d]" }, |
| 434 | { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 435 | { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsMR", "[!0r+!1d],!2r" }, |
| 436 | { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 437 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 438 | EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 439 | EXT_0F_REX_W_ENCODING_MAP(Movqxr, 0x66, 0x6E, REG_DEF0), |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 440 | { kX86MovqrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxRR", "!0r,!1r" }, |
| 441 | { kX86MovqrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxMR", "[!0r+!1d],!2r" }, |
| 442 | { kX86MovqrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 443 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 444 | { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxRR", "!0r,!1r" }, |
| 445 | { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxMR", "[!0r+!1d],!2r" }, |
| 446 | { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 447 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 448 | { kX86MovsxdRR, kRegReg, IS_BINARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRR", "!0r,!1r" }, |
| 449 | { kX86MovsxdRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRM", "!0r,[!1r+!2d]" }, |
| 450 | { kX86MovsxdRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE12, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 451 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 452 | { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, true }, "Set8R", "!1c !0r" }, |
| 453 | { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8M", "!2c [!0r+!1d]" }, |
| 454 | { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 455 | |
| 456 | // TODO: load/store? |
| 457 | // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 458 | { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0, false }, "Mfence", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 459 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 460 | EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
| 461 | EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 462 | EXT_0F_ENCODING_MAP(Imul64, REX_W, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 463 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 464 | { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "!0r,!1r" }, |
| 465 | { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1d],!2r" }, |
| 466 | { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 467 | { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, |
| 468 | { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 469 | { kX86LockCmpxchg64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1d]" }, |
| 470 | { kX86LockCmpxchg64A, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" }, |
| 471 | { kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0, false }, "Xchg", "[!0r+!1d],!2r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 472 | |
| 473 | EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), |
| 474 | EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), |
| 475 | EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), |
| 476 | EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), |
| 477 | #undef EXT_0F_ENCODING_MAP |
| 478 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 479 | { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0, false }, "Jcc8", "!1c !0t" }, |
| 480 | { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0, false }, "Jcc32", "!1c !0t" }, |
| 481 | { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0, false }, "Jmp8", "!0t" }, |
| 482 | { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Jmp32", "!0t" }, |
| 483 | { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpR", "!0r" }, |
| 484 | { kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0, false }, "Jecxz", "!0t" }, |
| 485 | { kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpT", "fs:[!0d]" }, |
| 486 | { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0, false }, "CallR", "!0r" }, |
| 487 | { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallM", "[!0r+!1d]" }, |
| 488 | { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallA", "[!0r+!1r<<!2d+!3d]" }, |
| 489 | { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallT", "fs:[!0d]" }, |
| 490 | { kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4, false }, "CallI", "!0d" }, |
| 491 | { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Ret", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 492 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 493 | { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0, false }, "StartOfMethod", "!0r" }, |
| 494 | { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, |
| 495 | { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "PcRelAdr", "!0r,!1d" }, |
| 496 | { kX86RepneScasw, kNullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0, false }, "RepNE ScasW", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 497 | }; |
| 498 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 499 | static bool NeedsRex(int32_t raw_reg) { |
| 500 | return RegStorage::RegNum(raw_reg) > 7; |
| 501 | } |
| 502 | |
| 503 | static uint8_t LowRegisterBits(int32_t raw_reg) { |
| 504 | uint8_t low_reg = RegStorage::RegNum(raw_reg) & kRegNumMask32; // 3 bits |
| 505 | DCHECK_LT(low_reg, 8); |
| 506 | return low_reg; |
| 507 | } |
| 508 | |
| 509 | size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, |
| 510 | int32_t raw_base, bool has_sib, bool r8_form, bool r8_reg_reg_form, |
| 511 | int32_t displacement) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 512 | size_t size = 0; |
| 513 | if (entry->skeleton.prefix1 > 0) { |
| 514 | ++size; |
| 515 | if (entry->skeleton.prefix2 > 0) { |
| 516 | ++size; |
| 517 | } |
| 518 | } |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 519 | if (Gen64Bit() || kIsDebugBuild) { |
| 520 | bool registers_need_rex_prefix = |
| 521 | NeedsRex(raw_reg) || NeedsRex(raw_index) || NeedsRex(raw_base) || |
| 522 | (r8_form && RegStorage::RegNum(raw_reg) > 4) || |
| 523 | (r8_reg_reg_form && RegStorage::RegNum(raw_base) > 4); |
| 524 | if (registers_need_rex_prefix && |
| 525 | entry->skeleton.prefix1 != REX_W && entry->skeleton.prefix2 != REX_W) { |
| 526 | DCHECK(Gen64Bit()) << "Attempt to use " << entry->name << " on a non-byte register " |
| 527 | << RegStorage::RegNum(raw_reg); |
| 528 | ++size; // rex |
| 529 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 530 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 531 | ++size; // opcode |
| 532 | if (entry->skeleton.opcode == 0x0F) { |
| 533 | ++size; |
| 534 | if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { |
| 535 | ++size; |
| 536 | } |
| 537 | } |
| 538 | ++size; // modrm |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 539 | if (has_sib || LowRegisterBits(raw_base) == rs_rX86_SP.GetRegNum() |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 540 | || (Gen64Bit() && entry->skeleton.prefix1 == THREAD_PREFIX)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 541 | // SP requires a SIB byte. |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 542 | // GS access also needs a SIB byte for absolute adressing in 64-bit mode. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 543 | ++size; |
| 544 | } |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 545 | if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 546 | // BP requires an explicit displacement, even when it's 0. |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 547 | if (entry->opcode != kX86Lea32RA && entry->opcode != kX86Lea64RA) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 548 | DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), UINT64_C(0)) << entry->name; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 549 | } |
| 550 | size += IS_SIMM8(displacement) ? 1 : 4; |
| 551 | } |
| 552 | size += entry->skeleton.immediate_bytes; |
| 553 | return size; |
| 554 | } |
| 555 | |
| 556 | int X86Mir2Lir::GetInsnSize(LIR* lir) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 557 | DCHECK(!IsPseudoLirOp(lir->opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 558 | const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 559 | DCHECK_EQ(entry->opcode, lir->opcode) << entry->name; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 560 | switch (entry->kind) { |
| 561 | case kData: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 562 | return 4; // 4 bytes of data. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 563 | case kNop: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 564 | return lir->operands[0]; // Length of nop is sole operand. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 565 | case kNullary: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 566 | // Substract 1 for modrm which isn't used. |
| 567 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 568 | return ComputeSize(entry, NO_REG, NO_REG, NO_REG, false, false, false, 0) - 1; |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 569 | case kRegOpcode: // lir operands - 0: reg |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 570 | // Substract 1 for modrm which isn't used. |
| 571 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 572 | // Note: RegOpcode form passes reg as REX_R but encodes it as REX_B. |
| 573 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, false, false, false, 0) - 1; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 574 | case kReg: // lir operands - 0: reg |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 575 | // Note: Reg form passes reg as REX_R but encodes it as REX_B. |
| 576 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, |
| 577 | false, entry->skeleton.r8_form, false, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 578 | case kMem: // lir operands - 0: base, 1: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 579 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 580 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], false, false, false, |
| 581 | lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 582 | case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 583 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], true, false, false, |
| 584 | lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 585 | case kMemReg: // lir operands - 0: base, 1: disp, 2: reg |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 586 | return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], |
| 587 | false, entry->skeleton.r8_form, false, lir->operands[1]); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 588 | case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 589 | return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], |
| 590 | false, entry->skeleton.r8_form, false, lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 591 | case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 592 | return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], |
| 593 | true, entry->skeleton.r8_form, false, lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 594 | case kThreadReg: // lir operands - 0: disp, 1: reg |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 595 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 596 | // Thread displacement size is always 32bit. |
| 597 | return ComputeSize(entry, lir->operands[1], NO_REG, NO_REG, false, false, false, |
| 598 | 0x12345678); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 599 | case kRegReg: // lir operands - 0: reg1, 1: reg2 |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 600 | // Note: RegReg form passes reg2 as index but encodes it using base. |
| 601 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, |
| 602 | false, entry->skeleton.r8_form, entry->skeleton.r8_form, 0); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 603 | case kRegRegStore: // lir operands - 0: reg2, 1: reg1 |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 604 | // Note: RegRegStore form passes reg1 as index but encodes it using base. |
| 605 | return ComputeSize(entry, lir->operands[1], lir->operands[0], NO_REG, |
| 606 | false, entry->skeleton.r8_form, entry->skeleton.r8_form, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 607 | case kRegMem: // lir operands - 0: reg, 1: base, 2: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 608 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], |
| 609 | false, entry->skeleton.r8_form, false, lir->operands[2]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 610 | case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 611 | return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], |
| 612 | true, entry->skeleton.r8_form, false, lir->operands[4]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 613 | case kRegThread: // lir operands - 0: reg, 1: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 614 | // Thread displacement size is always 32bit. |
| 615 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 616 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, false, false, false, |
| 617 | 0x12345678); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 618 | case kRegImm: { // lir operands - 0: reg, 1: immediate |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 619 | size_t size = ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, |
| 620 | false, entry->skeleton.r8_form, false, 0); |
| 621 | // AX opcodes don't require the modrm byte. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 622 | if (entry->skeleton.ax_opcode == 0) { |
| 623 | return size; |
| 624 | } else { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 625 | return size - (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 626 | } |
| 627 | } |
| 628 | case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 629 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 630 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], |
| 631 | false, false, false, lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 632 | case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 633 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 634 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], |
| 635 | true, false, false, lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 636 | case kThreadImm: // lir operands - 0: disp, 1: imm |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 637 | // Thread displacement size is always 32bit. |
| 638 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 639 | return ComputeSize(entry, NO_REG, NO_REG, NO_REG, false, false, false, 0x12345678); |
| 640 | case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm |
| 641 | // Note: RegRegImm form passes reg2 as index but encodes it using base. |
| 642 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, |
| 643 | false, entry->skeleton.r8_form, entry->skeleton.r8_form, 0); |
| 644 | case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm |
| 645 | // Note: RegRegImmStore form passes reg1 as index but encodes it using base. |
| 646 | return ComputeSize(entry, lir->operands[1], lir->operands[0], NO_REG, |
| 647 | false, entry->skeleton.r8_form, entry->skeleton.r8_form, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 648 | case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 649 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], |
| 650 | false, entry->skeleton.r8_form, false, lir->operands[2]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 651 | case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 652 | return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], |
| 653 | true, entry->skeleton.r8_form, false, lir->operands[4]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 654 | case kMovRegImm: // lir operands - 0: reg, 1: immediate |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 655 | return ((entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])) ? 1 : 0) + 1 + |
| 656 | entry->skeleton.immediate_bytes; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 657 | case kShiftRegImm: // lir operands - 0: reg, 1: immediate |
| 658 | // Shift by immediate one has a shorter opcode. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 659 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, |
| 660 | false, entry->skeleton.r8_form, false, 0) - |
| 661 | (lir->operands[1] == 1 ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 662 | case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
| 663 | // Shift by immediate one has a shorter opcode. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 664 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], |
| 665 | false, entry->skeleton.r8_form, false, lir->operands[1]) - |
| 666 | (lir->operands[2] == 1 ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 667 | case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate |
| 668 | // Shift by immediate one has a shorter opcode. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 669 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], |
| 670 | true, entry->skeleton.r8_form, false, lir->operands[3]) - |
| 671 | (lir->operands[4] == 1 ? 1 : 0); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 672 | case kShiftRegCl: // lir operands - 0: reg, 1: cl |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 673 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[1])); |
| 674 | // Note: ShiftRegCl form passes reg as reg but encodes it using base. |
| 675 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, |
| 676 | false, entry->skeleton.r8_form, false, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 677 | case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 678 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 679 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2])); |
| 680 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], |
| 681 | false, false, false, lir->operands[1]); |
| 682 | case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cl |
| 683 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 684 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[4])); |
| 685 | return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], |
| 686 | true, false, false, lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 687 | case kRegCond: // lir operands - 0: reg, 1: cond |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 688 | return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, |
| 689 | false, entry->skeleton.r8_form, false, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 690 | case kMemCond: // lir operands - 0: base, 1: disp, 2: cond |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 691 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 692 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], false, false, false, |
| 693 | lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 694 | case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 695 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 696 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], true, false, false, |
| 697 | lir->operands[3]); |
| 698 | case kRegRegCond: // lir operands - 0: reg1, 1: reg2, 2: cond |
| 699 | // Note: RegRegCond form passes reg2 as index but encodes it using base. |
| 700 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 701 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, false, false, false, 0); |
| 702 | case kRegMemCond: // lir operands - 0: reg, 1: base, 2: disp, 3:cond |
| 703 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 704 | return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], false, false, false, |
| 705 | lir->operands[2]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 706 | case kJcc: |
| 707 | if (lir->opcode == kX86Jcc8) { |
| 708 | return 2; // opcode + rel8 |
| 709 | } else { |
| 710 | DCHECK(lir->opcode == kX86Jcc32); |
| 711 | return 6; // 2 byte opcode + rel32 |
| 712 | } |
| 713 | case kJmp: |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 714 | if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 715 | return 2; // opcode + rel8 |
| 716 | } else if (lir->opcode == kX86Jmp32) { |
| 717 | return 5; // opcode + rel32 |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 718 | } else if (lir->opcode == kX86JmpT) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 719 | // Thread displacement size is always 32bit. |
| 720 | return ComputeSize(entry, NO_REG, NO_REG, NO_REG, false, false, false, 0x12345678); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 721 | } else { |
| 722 | DCHECK(lir->opcode == kX86JmpR); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 723 | if (NeedsRex(lir->operands[0])) { |
| 724 | return 3; // REX.B + opcode + modrm |
| 725 | } else { |
| 726 | return 2; // opcode + modrm |
| 727 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 728 | } |
| 729 | case kCall: |
| 730 | switch (lir->opcode) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 731 | case kX86CallI: return 5; // opcode 0:disp |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 732 | case kX86CallR: return 2; // opcode modrm |
| 733 | case kX86CallM: // lir operands - 0: base, 1: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 734 | return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], false, false, false, |
| 735 | lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 736 | case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 737 | return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], true, false, false, |
| 738 | lir->operands[3]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 739 | case kX86CallT: // lir operands - 0: disp |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 740 | // Thread displacement size is always 32bit. |
| 741 | return ComputeSize(entry, NO_REG, NO_REG, NO_REG, false, false, false, 0x12345678); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 742 | default: |
| 743 | break; |
| 744 | } |
| 745 | break; |
| 746 | case kPcRel: |
| 747 | if (entry->opcode == kX86PcRelLoadRA) { |
| 748 | // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 749 | // Force the displacement size to 32bit, it will hold a computed offset later. |
| 750 | return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], |
| 751 | true, false, false, 0x12345678); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 752 | } else { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 753 | DCHECK_EQ(entry->opcode, kX86PcRelAdr); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 754 | return 5; // opcode with reg + 4 byte immediate |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 755 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 756 | case kMacro: // lir operands - 0: reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 757 | DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); |
| 758 | return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 759 | ComputeSize(&X86Mir2Lir::EncodingMap[Gen64Bit() ? kX86Sub64RI : kX86Sub32RI], |
| 760 | lir->operands[0], NO_REG, NO_REG, false, false, false, 0) - |
| 761 | // Shorter ax encoding. |
| 762 | (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); |
| 763 | case kUnimplemented: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 764 | break; |
| 765 | } |
| 766 | UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; |
| 767 | return 0; |
| 768 | } |
| 769 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 770 | static uint8_t ModrmForDisp(int base, int disp) { |
| 771 | // BP requires an explicit disp, so do not omit it in the 0 case |
| 772 | if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { |
| 773 | return 0; |
| 774 | } else if (IS_SIMM8(disp)) { |
| 775 | return 1; |
| 776 | } else { |
| 777 | return 2; |
| 778 | } |
| 779 | } |
| 780 | |
| 781 | void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) { |
| 782 | if (kIsDebugBuild) { |
| 783 | // Sanity check r8_form is correctly specified. |
| 784 | if (entry->skeleton.r8_form) { |
| 785 | CHECK(strchr(entry->name, '8') != nullptr) << entry->name; |
| 786 | } else { |
| 787 | if (entry->skeleton.immediate_bytes != 1) { // Ignore ...I8 instructions. |
| 788 | if (!StartsWith(entry->name, "Movzx8") && !StartsWith(entry->name, "Movsx8")) { |
| 789 | CHECK(strchr(entry->name, '8') == nullptr) << entry->name; |
| 790 | } |
| 791 | } |
| 792 | } |
| 793 | if (RegStorage::RegNum(raw_reg) >= 4) { |
| 794 | // ah, bh, ch and dh are not valid registers in 32-bit. |
| 795 | CHECK(Gen64Bit() || !entry->skeleton.r8_form) |
| 796 | << "Invalid register " << static_cast<int>(RegStorage::RegNum(raw_reg)) |
| 797 | << " for instruction " << entry->name << " in " |
| 798 | << PrettyMethod(cu_->method_idx, *cu_->dex_file); |
| 799 | } |
| 800 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 801 | } |
| 802 | |
| 803 | void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 804 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b, |
| 805 | bool r8_form) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 806 | // REX.WRXB |
| 807 | // W - 64-bit operand |
| 808 | // R - MODRM.reg |
| 809 | // X - SIB.index |
| 810 | // B - MODRM.rm/SIB.base |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 811 | bool w = (entry->skeleton.prefix1 == REX_W) || (entry->skeleton.prefix2 == REX_W); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 812 | bool r = NeedsRex(raw_reg_r); |
| 813 | bool x = NeedsRex(raw_reg_x); |
| 814 | bool b = NeedsRex(raw_reg_b); |
| 815 | uint8_t rex = 0; |
| 816 | if (r8_form && RegStorage::RegNum(raw_reg_r) > 4) { |
| 817 | rex |= 0x40; // REX.0000 |
| 818 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 819 | if (w) { |
| 820 | rex |= 0x48; // REX.W000 |
| 821 | } |
| 822 | if (r) { |
| 823 | rex |= 0x44; // REX.0R00 |
| 824 | } |
| 825 | if (x) { |
| 826 | rex |= 0x42; // REX.00X0 |
| 827 | } |
| 828 | if (b) { |
| 829 | rex |= 0x41; // REX.000B |
| 830 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 831 | if (entry->skeleton.prefix1 != 0) { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 832 | if (Gen64Bit() && entry->skeleton.prefix1 == THREAD_PREFIX) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 833 | // 64 bit addresses by GS, not FS. |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 834 | code_buffer_.push_back(THREAD_PREFIX_GS); |
| 835 | } else { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 836 | if (entry->skeleton.prefix1 == REX_W) { |
| 837 | rex |= entry->skeleton.prefix1; |
| 838 | code_buffer_.push_back(rex); |
| 839 | rex = 0; |
| 840 | } else { |
| 841 | code_buffer_.push_back(entry->skeleton.prefix1); |
| 842 | } |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 843 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 844 | if (entry->skeleton.prefix2 != 0) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 845 | if (entry->skeleton.prefix2 == REX_W) { |
| 846 | rex |= entry->skeleton.prefix2; |
| 847 | code_buffer_.push_back(rex); |
| 848 | rex = 0; |
| 849 | } else { |
| 850 | code_buffer_.push_back(entry->skeleton.prefix2); |
| 851 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 852 | } |
| 853 | } else { |
| 854 | DCHECK_EQ(0, entry->skeleton.prefix2); |
| 855 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 856 | if (rex != 0) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 857 | DCHECK(Gen64Bit()); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 858 | code_buffer_.push_back(rex); |
| 859 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 860 | } |
| 861 | |
| 862 | void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { |
| 863 | code_buffer_.push_back(entry->skeleton.opcode); |
| 864 | if (entry->skeleton.opcode == 0x0F) { |
| 865 | code_buffer_.push_back(entry->skeleton.extra_opcode1); |
| 866 | if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { |
| 867 | code_buffer_.push_back(entry->skeleton.extra_opcode2); |
| 868 | } else { |
| 869 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
| 870 | } |
| 871 | } else { |
| 872 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 873 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
| 874 | } |
| 875 | } |
| 876 | |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 877 | void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 878 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b, |
| 879 | bool r8_form) { |
| 880 | EmitPrefix(entry, raw_reg_r, raw_reg_x, raw_reg_b, r8_form); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 881 | EmitOpcode(entry); |
| 882 | } |
| 883 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 884 | void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 885 | // BP requires an explicit disp, so do not omit it in the 0 case |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 886 | if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 887 | return; |
| 888 | } else if (IS_SIMM8(disp)) { |
| 889 | code_buffer_.push_back(disp & 0xFF); |
| 890 | } else { |
| 891 | code_buffer_.push_back(disp & 0xFF); |
| 892 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 893 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 894 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 895 | } |
| 896 | } |
| 897 | |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 898 | void X86Mir2Lir::EmitModrmThread(uint8_t reg_or_opcode) { |
| 899 | if (Gen64Bit()) { |
| 900 | // Absolute adressing for GS access. |
| 901 | uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rX86_SP.GetRegNum(); |
| 902 | code_buffer_.push_back(modrm); |
| 903 | uint8_t sib = (0/*TIMES_1*/ << 6) | (rs_rX86_SP.GetRegNum() << 3) | rs_rBP.GetRegNum(); |
| 904 | code_buffer_.push_back(sib); |
| 905 | } else { |
| 906 | uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rBP.GetRegNum(); |
| 907 | code_buffer_.push_back(modrm); |
| 908 | } |
| 909 | } |
| 910 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 911 | void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) { |
| 912 | DCHECK_LT(reg_or_opcode, 8); |
| 913 | DCHECK_LT(base, 8); |
| 914 | uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 915 | code_buffer_.push_back(modrm); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 916 | if (base == rs_rX86_SP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 917 | // Special SIB for SP base |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 918 | code_buffer_.push_back(0 << 6 | rs_rX86_SP.GetRegNum() << 3 | rs_rX86_SP.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 919 | } |
| 920 | EmitDisp(base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 921 | } |
| 922 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 923 | void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 924 | int scale, int32_t disp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 925 | DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8); |
| 926 | uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 | |
| 927 | rs_rX86_SP.GetRegNum(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 928 | code_buffer_.push_back(modrm); |
| 929 | DCHECK_LT(scale, 4); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 930 | DCHECK_LT(RegStorage::RegNum(index), 8); |
| 931 | DCHECK_LT(RegStorage::RegNum(base), 8); |
| 932 | uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 933 | code_buffer_.push_back(sib); |
| 934 | EmitDisp(base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 935 | } |
| 936 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 937 | void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 938 | switch (entry->skeleton.immediate_bytes) { |
| 939 | case 1: |
| 940 | DCHECK(IS_SIMM8(imm)); |
| 941 | code_buffer_.push_back(imm & 0xFF); |
| 942 | break; |
| 943 | case 2: |
| 944 | DCHECK(IS_SIMM16(imm)); |
| 945 | code_buffer_.push_back(imm & 0xFF); |
| 946 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 947 | break; |
| 948 | case 4: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 949 | DCHECK(IS_SIMM32(imm)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 950 | code_buffer_.push_back(imm & 0xFF); |
| 951 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 952 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 953 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 954 | break; |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 955 | case 8: |
| 956 | code_buffer_.push_back(imm & 0xFF); |
| 957 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 958 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 959 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 960 | code_buffer_.push_back((imm >> 32) & 0xFF); |
| 961 | code_buffer_.push_back((imm >> 40) & 0xFF); |
| 962 | code_buffer_.push_back((imm >> 48) & 0xFF); |
| 963 | code_buffer_.push_back((imm >> 56) & 0xFF); |
| 964 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 965 | default: |
| 966 | LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes |
| 967 | << ") for instruction: " << entry->name; |
| 968 | break; |
| 969 | } |
| 970 | } |
| 971 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 972 | void X86Mir2Lir::EmitNullary(const X86EncodingMap* entry) { |
| 973 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 974 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG, false); |
| 975 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 976 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 977 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 978 | } |
| 979 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 980 | void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg) { |
| 981 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 982 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg, false); |
| 983 | // There's no 3-byte instruction with +rd |
| 984 | DCHECK(entry->skeleton.opcode != 0x0F || |
| 985 | (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A)); |
| 986 | DCHECK(!RegStorage::IsFloat(raw_reg)); |
| 987 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 988 | code_buffer_.back() += low_reg; |
| 989 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 990 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 991 | } |
| 992 | |
| 993 | void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg) { |
| 994 | CheckValidByteRegister(entry, raw_reg); |
| 995 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg, entry->skeleton.r8_form); |
| 996 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 997 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 998 | code_buffer_.push_back(modrm); |
| 999 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1000 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1001 | } |
| 1002 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1003 | void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { |
| 1004 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1005 | EmitPrefix(entry, NO_REG, NO_REG, raw_base, false); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1006 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1007 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1008 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1009 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1010 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1011 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1012 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1013 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1014 | } |
| 1015 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1016 | void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, |
| 1017 | int scale, int32_t disp) { |
| 1018 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1019 | EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base, false); |
| 1020 | uint8_t low_index = LowRegisterBits(raw_index); |
| 1021 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1022 | EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1023 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1024 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1025 | } |
| 1026 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1027 | void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, |
| 1028 | int32_t raw_reg) { |
| 1029 | CheckValidByteRegister(entry, raw_reg); |
| 1030 | EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base, entry->skeleton.r8_form); |
| 1031 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1032 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1033 | EmitModrmDisp(low_reg, low_base, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1034 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1035 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1036 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1037 | } |
| 1038 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1039 | void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 1040 | int32_t disp) { |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1041 | // Opcode will flip operands. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1042 | EmitMemReg(entry, raw_base, disp, raw_reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1043 | } |
| 1044 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1045 | void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 1046 | int32_t raw_index, int scale, int32_t disp) { |
| 1047 | CheckValidByteRegister(entry, raw_reg); |
| 1048 | EmitPrefixAndOpcode(entry, raw_reg, raw_index, raw_base, entry->skeleton.r8_form); |
| 1049 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1050 | uint8_t low_index = LowRegisterBits(raw_index); |
| 1051 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1052 | EmitModrmSibDisp(low_reg, low_base, low_index, scale, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1053 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1054 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1055 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1056 | } |
| 1057 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1058 | void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, |
| 1059 | int scale, int32_t disp, int32_t raw_reg) { |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1060 | // Opcode will flip operands. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1061 | EmitRegArray(entry, raw_reg, raw_base, raw_index, scale, disp); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1062 | } |
| 1063 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1064 | void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, |
| 1065 | int32_t imm) { |
| 1066 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1067 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base, false); |
| 1068 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1069 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1070 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
Mark Mendell | 9ed4277 | 2014-05-07 17:26:12 -0400 | [diff] [blame] | 1071 | EmitImm(entry, imm); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1072 | } |
| 1073 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1074 | void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry, |
| 1075 | int32_t raw_base, int32_t raw_index, int scale, int32_t disp, |
| 1076 | int32_t imm) { |
| 1077 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1078 | EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base, false); |
| 1079 | uint8_t low_index = LowRegisterBits(raw_index); |
| 1080 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1081 | EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); |
| 1082 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1083 | EmitImm(entry, imm); |
| 1084 | } |
| 1085 | |
| 1086 | void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) { |
| 1087 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1088 | DCHECK_NE(entry->skeleton.prefix1, 0); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1089 | EmitPrefixAndOpcode(entry, raw_reg, NO_REG, NO_REG, false); |
| 1090 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1091 | EmitModrmThread(low_reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1092 | code_buffer_.push_back(disp & 0xFF); |
| 1093 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1094 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1095 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1096 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1097 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1098 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1099 | } |
| 1100 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1101 | void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2) { |
| 1102 | CheckValidByteRegister(entry, raw_reg1); |
| 1103 | CheckValidByteRegister(entry, raw_reg2); |
| 1104 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2, entry->skeleton.r8_form); |
| 1105 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1106 | uint8_t low_reg2 = LowRegisterBits(raw_reg2); |
| 1107 | uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1108 | code_buffer_.push_back(modrm); |
| 1109 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1110 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1111 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1112 | } |
| 1113 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1114 | void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, |
| 1115 | int32_t imm) { |
| 1116 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1117 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2, false); |
| 1118 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1119 | uint8_t low_reg2 = LowRegisterBits(raw_reg2); |
| 1120 | uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1121 | code_buffer_.push_back(modrm); |
| 1122 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1123 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1124 | EmitImm(entry, imm); |
| 1125 | } |
| 1126 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1127 | void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1128 | int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) { |
| 1129 | DCHECK(!RegStorage::IsFloat(raw_reg)); |
| 1130 | CheckValidByteRegister(entry, raw_reg); |
| 1131 | EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base, entry->skeleton.r8_form); |
| 1132 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1133 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1134 | EmitModrmDisp(low_reg, low_base, disp); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1135 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1136 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1137 | EmitImm(entry, imm); |
| 1138 | } |
| 1139 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1140 | void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry, |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1141 | int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) { |
| 1142 | // Opcode will flip operands. |
| 1143 | EmitRegMemImm(entry, raw_reg, raw_base, disp, imm); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1144 | } |
| 1145 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1146 | void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { |
| 1147 | CheckValidByteRegister(entry, raw_reg); |
| 1148 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg, entry->skeleton.r8_form); |
| 1149 | if (RegStorage::RegNum(raw_reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1150 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1151 | } else { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1152 | uint8_t low_reg = LowRegisterBits(raw_reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1153 | EmitOpcode(entry); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1154 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1155 | code_buffer_.push_back(modrm); |
| 1156 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1157 | EmitImm(entry, imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1158 | } |
| 1159 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1160 | void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) { |
| 1161 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG, false); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 1162 | EmitModrmThread(entry->skeleton.modrm_opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1163 | code_buffer_.push_back(disp & 0xFF); |
| 1164 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1165 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1166 | code_buffer_.push_back((disp >> 24) & 0xFF); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1167 | EmitImm(entry, imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1168 | DCHECK_EQ(entry->skeleton.ax_opcode, 0); |
| 1169 | } |
| 1170 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1171 | void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) { |
| 1172 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1173 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg, false); |
| 1174 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1175 | code_buffer_.push_back(0xB8 + low_reg); |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1176 | switch (entry->skeleton.immediate_bytes) { |
| 1177 | case 4: |
| 1178 | code_buffer_.push_back(imm & 0xFF); |
| 1179 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1180 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 1181 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 1182 | break; |
| 1183 | case 8: |
| 1184 | code_buffer_.push_back(imm & 0xFF); |
| 1185 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1186 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 1187 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 1188 | code_buffer_.push_back((imm >> 32) & 0xFF); |
| 1189 | code_buffer_.push_back((imm >> 40) & 0xFF); |
| 1190 | code_buffer_.push_back((imm >> 48) & 0xFF); |
| 1191 | code_buffer_.push_back((imm >> 56) & 0xFF); |
| 1192 | break; |
| 1193 | default: |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1194 | LOG(FATAL) << "Unsupported immediate size for EmitMovRegImm: " |
| 1195 | << static_cast<uint32_t>(entry->skeleton.immediate_bytes); |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1196 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1197 | } |
| 1198 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1199 | void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { |
| 1200 | CheckValidByteRegister(entry, raw_reg); |
| 1201 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg, entry->skeleton.r8_form); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1202 | if (imm != 1) { |
| 1203 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1204 | } else { |
| 1205 | // Shorter encoding for 1 bit shift |
| 1206 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1207 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1208 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1209 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1210 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1211 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1212 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1213 | code_buffer_.push_back(modrm); |
| 1214 | if (imm != 1) { |
| 1215 | DCHECK_EQ(entry->skeleton.immediate_bytes, 1); |
| 1216 | DCHECK(IS_SIMM8(imm)); |
| 1217 | code_buffer_.push_back(imm & 0xFF); |
| 1218 | } |
| 1219 | } |
| 1220 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1221 | void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl) { |
| 1222 | CheckValidByteRegister(entry, raw_reg); |
| 1223 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); |
| 1224 | EmitPrefix(entry, NO_REG, NO_REG, raw_reg, entry->skeleton.r8_form); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1225 | code_buffer_.push_back(entry->skeleton.opcode); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1226 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1227 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1228 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1229 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1230 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1231 | code_buffer_.push_back(modrm); |
| 1232 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1233 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1234 | } |
| 1235 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1236 | void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, |
| 1237 | int32_t displacement, int32_t raw_cl) { |
| 1238 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1239 | DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); |
| 1240 | EmitPrefix(entry, NO_REG, NO_REG, raw_base, false); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1241 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1242 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1243 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1244 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1245 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1246 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, displacement); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1247 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1248 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1249 | } |
| 1250 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1251 | void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, |
| 1252 | int32_t imm) { |
| 1253 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1254 | EmitPrefix(entry, NO_REG, NO_REG, raw_base, false); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1255 | if (imm != 1) { |
| 1256 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1257 | } else { |
| 1258 | // Shorter encoding for 1 bit shift |
| 1259 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1260 | } |
| 1261 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1262 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1263 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1264 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1265 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1266 | if (imm != 1) { |
| 1267 | DCHECK_EQ(entry->skeleton.immediate_bytes, 1); |
| 1268 | DCHECK(IS_SIMM8(imm)); |
| 1269 | code_buffer_.push_back(imm & 0xFF); |
| 1270 | } |
| 1271 | } |
| 1272 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1273 | void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc) { |
| 1274 | CheckValidByteRegister(entry, raw_reg); |
| 1275 | EmitPrefix(entry, raw_reg, NO_REG, NO_REG, entry->skeleton.r8_form); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1276 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1277 | DCHECK_EQ(0x0F, entry->skeleton.opcode); |
| 1278 | code_buffer_.push_back(0x0F); |
| 1279 | DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1280 | DCHECK_GE(cc, 0); |
| 1281 | DCHECK_LT(cc, 16); |
| 1282 | code_buffer_.push_back(0x90 | cc); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1283 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1284 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1285 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1286 | code_buffer_.push_back(modrm); |
| 1287 | DCHECK_EQ(entry->skeleton.immediate_bytes, 0); |
| 1288 | } |
| 1289 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1290 | void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, |
| 1291 | int32_t cc) { |
| 1292 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1293 | if (entry->skeleton.prefix1 != 0) { |
| 1294 | code_buffer_.push_back(entry->skeleton.prefix1); |
| 1295 | if (entry->skeleton.prefix2 != 0) { |
| 1296 | code_buffer_.push_back(entry->skeleton.prefix2); |
| 1297 | } |
| 1298 | } else { |
| 1299 | DCHECK_EQ(0, entry->skeleton.prefix2); |
| 1300 | } |
| 1301 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1302 | DCHECK_EQ(0x0F, entry->skeleton.opcode); |
| 1303 | code_buffer_.push_back(0x0F); |
| 1304 | DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1305 | DCHECK_GE(cc, 0); |
| 1306 | DCHECK_LT(cc, 16); |
| 1307 | code_buffer_.push_back(0x90 | cc); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1308 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1309 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1310 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1311 | DCHECK_EQ(entry->skeleton.immediate_bytes, 0); |
| 1312 | } |
| 1313 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1314 | void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, |
| 1315 | int32_t cc) { |
| 1316 | // Generate prefix and opcode without the condition. |
| 1317 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1318 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2, false); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1319 | |
| 1320 | // Now add the condition. The last byte of opcode is the one that receives it. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1321 | DCHECK_GE(cc, 0); |
| 1322 | DCHECK_LT(cc, 16); |
| 1323 | code_buffer_.back() += cc; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1324 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1325 | // Not expecting to have to encode immediate or do anything special for ModR/M since there are |
| 1326 | // two registers. |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1327 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1328 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1329 | |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1330 | // For register to register encoding, the mod is 3. |
| 1331 | const uint8_t mod = (3 << 6); |
| 1332 | |
| 1333 | // Encode the ModR/M byte now. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1334 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1335 | uint8_t low_reg2 = LowRegisterBits(raw_reg2); |
| 1336 | const uint8_t modrm = mod | (low_reg1 << 3) | low_reg2; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1337 | code_buffer_.push_back(modrm); |
| 1338 | } |
| 1339 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1340 | void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, |
| 1341 | int32_t disp, int32_t cc) { |
| 1342 | // Generate prefix and opcode without the condition. |
| 1343 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1344 | EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_base, false); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1345 | |
| 1346 | // Now add the condition. The last byte of opcode is the one that receives it. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1347 | DCHECK_GE(cc, 0); |
| 1348 | DCHECK_LT(cc, 16); |
| 1349 | code_buffer_.back() += cc; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1350 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1351 | // Not expecting to have to encode immediate or do anything special for ModR/M since there are |
| 1352 | // two registers. |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1353 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1354 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1355 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1356 | uint8_t low_reg1 = LowRegisterBits(raw_reg1); |
| 1357 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1358 | EmitModrmDisp(low_reg1, low_base, disp); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1359 | } |
| 1360 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1361 | void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int32_t rel) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1362 | if (entry->opcode == kX86Jmp8) { |
| 1363 | DCHECK(IS_SIMM8(rel)); |
| 1364 | code_buffer_.push_back(0xEB); |
| 1365 | code_buffer_.push_back(rel & 0xFF); |
| 1366 | } else if (entry->opcode == kX86Jmp32) { |
| 1367 | code_buffer_.push_back(0xE9); |
| 1368 | code_buffer_.push_back(rel & 0xFF); |
| 1369 | code_buffer_.push_back((rel >> 8) & 0xFF); |
| 1370 | code_buffer_.push_back((rel >> 16) & 0xFF); |
| 1371 | code_buffer_.push_back((rel >> 24) & 0xFF); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1372 | } else if (entry->opcode == kX86Jecxz8) { |
| 1373 | DCHECK(IS_SIMM8(rel)); |
| 1374 | code_buffer_.push_back(0xE3); |
| 1375 | code_buffer_.push_back(rel & 0xFF); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1376 | } else { |
| 1377 | DCHECK(entry->opcode == kX86JmpR); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1378 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1379 | EmitPrefix(entry, NO_REG, NO_REG, rel, false); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1380 | code_buffer_.push_back(entry->skeleton.opcode); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1381 | uint8_t low_reg = LowRegisterBits(rel); |
| 1382 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1383 | code_buffer_.push_back(modrm); |
| 1384 | } |
| 1385 | } |
| 1386 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1387 | void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc) { |
| 1388 | DCHECK_GE(cc, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1389 | DCHECK_LT(cc, 16); |
| 1390 | if (entry->opcode == kX86Jcc8) { |
| 1391 | DCHECK(IS_SIMM8(rel)); |
| 1392 | code_buffer_.push_back(0x70 | cc); |
| 1393 | code_buffer_.push_back(rel & 0xFF); |
| 1394 | } else { |
| 1395 | DCHECK(entry->opcode == kX86Jcc32); |
| 1396 | code_buffer_.push_back(0x0F); |
| 1397 | code_buffer_.push_back(0x80 | cc); |
| 1398 | code_buffer_.push_back(rel & 0xFF); |
| 1399 | code_buffer_.push_back((rel >> 8) & 0xFF); |
| 1400 | code_buffer_.push_back((rel >> 16) & 0xFF); |
| 1401 | code_buffer_.push_back((rel >> 24) & 0xFF); |
| 1402 | } |
| 1403 | } |
| 1404 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1405 | void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { |
| 1406 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1407 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base, false); |
| 1408 | uint8_t low_base = LowRegisterBits(raw_base); |
| 1409 | EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1410 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1411 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1412 | } |
| 1413 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1414 | void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) { |
| 1415 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1416 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG, false); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1417 | DCHECK_EQ(4, entry->skeleton.immediate_bytes); |
| 1418 | code_buffer_.push_back(disp & 0xFF); |
| 1419 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1420 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1421 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1422 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1423 | } |
| 1424 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1425 | void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int32_t disp) { |
| 1426 | DCHECK_EQ(false, entry->skeleton.r8_form); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1427 | DCHECK_NE(entry->skeleton.prefix1, 0); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1428 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG, false); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 1429 | EmitModrmThread(entry->skeleton.modrm_opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1430 | code_buffer_.push_back(disp & 0xFF); |
| 1431 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1432 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1433 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1434 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1435 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1436 | } |
| 1437 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1438 | void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, |
| 1439 | int32_t raw_index, int scale, int32_t table_or_disp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1440 | int disp; |
| 1441 | if (entry->opcode == kX86PcRelLoadRA) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1442 | Mir2Lir::EmbeddedData *tab_rec = |
| 1443 | reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1444 | disp = tab_rec->offset; |
| 1445 | } else { |
| 1446 | DCHECK(entry->opcode == kX86PcRelAdr); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1447 | Mir2Lir::EmbeddedData *tab_rec = |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1448 | reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(raw_base_or_table)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1449 | disp = tab_rec->offset; |
| 1450 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1451 | if (entry->opcode == kX86PcRelLoadRA) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1452 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1453 | EmitPrefix(entry, raw_reg, raw_index, raw_base_or_table, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1454 | code_buffer_.push_back(entry->skeleton.opcode); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1455 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1456 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1457 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1458 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1459 | uint8_t modrm = (2 << 6) | (low_reg << 3) | rs_rX86_SP.GetRegNum(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1460 | code_buffer_.push_back(modrm); |
| 1461 | DCHECK_LT(scale, 4); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1462 | uint8_t low_base_or_table = LowRegisterBits(raw_base_or_table); |
| 1463 | uint8_t low_index = LowRegisterBits(raw_index); |
| 1464 | uint8_t sib = (scale << 6) | (low_index << 3) | low_base_or_table; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1465 | code_buffer_.push_back(sib); |
| 1466 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1467 | } else { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1468 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1469 | code_buffer_.push_back(entry->skeleton.opcode + low_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1470 | } |
| 1471 | code_buffer_.push_back(disp & 0xFF); |
| 1472 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1473 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1474 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1475 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1476 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1477 | } |
| 1478 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1479 | void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset) { |
| 1480 | DCHECK_EQ(entry->opcode, kX86StartOfMethod) << entry->name; |
| 1481 | DCHECK_EQ(false, entry->skeleton.r8_form); |
| 1482 | EmitPrefix(entry, raw_reg, NO_REG, NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1483 | code_buffer_.push_back(0xE8); // call +0 |
| 1484 | code_buffer_.push_back(0); |
| 1485 | code_buffer_.push_back(0); |
| 1486 | code_buffer_.push_back(0); |
| 1487 | code_buffer_.push_back(0); |
| 1488 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1489 | uint8_t low_reg = LowRegisterBits(raw_reg); |
| 1490 | code_buffer_.push_back(0x58 + low_reg); // pop reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1491 | |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 1492 | EmitRegImm(&X86Mir2Lir::EncodingMap[Gen64Bit() ? kX86Sub64RI : kX86Sub32RI], |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1493 | raw_reg, offset + 5 /* size of call +0 */); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1494 | } |
| 1495 | |
| 1496 | void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { |
| 1497 | UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " |
| 1498 | << BuildInsnString(entry->fmt, lir, 0); |
| 1499 | for (int i = 0; i < GetInsnSize(lir); ++i) { |
| 1500 | code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 |
| 1501 | } |
| 1502 | } |
| 1503 | |
| 1504 | /* |
| 1505 | * Assemble the LIR into binary instruction format. Note that we may |
| 1506 | * discover that pc-relative displacements may not fit the selected |
| 1507 | * instruction. In those cases we will try to substitute a new code |
| 1508 | * sequence or request that the trace be shortened and retried. |
| 1509 | */ |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1510 | AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1511 | LIR *lir; |
| 1512 | AssemblerStatus res = kSuccess; // Assume success |
| 1513 | |
| 1514 | const bool kVerbosePcFixup = false; |
| 1515 | for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 1516 | if (IsPseudoLirOp(lir->opcode)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1517 | continue; |
| 1518 | } |
| 1519 | |
| 1520 | if (lir->flags.is_nop) { |
| 1521 | continue; |
| 1522 | } |
| 1523 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1524 | if (lir->flags.fixup != kFixupNone) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1525 | switch (lir->opcode) { |
| 1526 | case kX86Jcc8: { |
| 1527 | LIR *target_lir = lir->target; |
| 1528 | DCHECK(target_lir != NULL); |
| 1529 | int delta = 0; |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1530 | CodeOffset pc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1531 | if (IS_SIMM8(lir->operands[0])) { |
| 1532 | pc = lir->offset + 2 /* opcode + rel8 */; |
| 1533 | } else { |
| 1534 | pc = lir->offset + 6 /* 2 byte opcode + rel32 */; |
| 1535 | } |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1536 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1537 | delta = target - pc; |
| 1538 | if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { |
| 1539 | if (kVerbosePcFixup) { |
| 1540 | LOG(INFO) << "Retry for JCC growth at " << lir->offset |
| 1541 | << " delta: " << delta << " old delta: " << lir->operands[0]; |
| 1542 | } |
| 1543 | lir->opcode = kX86Jcc32; |
| 1544 | SetupResourceMasks(lir); |
| 1545 | res = kRetryAll; |
| 1546 | } |
| 1547 | if (kVerbosePcFixup) { |
| 1548 | LOG(INFO) << "Source:"; |
| 1549 | DumpLIRInsn(lir, 0); |
| 1550 | LOG(INFO) << "Target:"; |
| 1551 | DumpLIRInsn(target_lir, 0); |
| 1552 | LOG(INFO) << "Delta " << delta; |
| 1553 | } |
| 1554 | lir->operands[0] = delta; |
| 1555 | break; |
| 1556 | } |
| 1557 | case kX86Jcc32: { |
| 1558 | LIR *target_lir = lir->target; |
| 1559 | DCHECK(target_lir != NULL); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1560 | CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; |
| 1561 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1562 | int delta = target - pc; |
| 1563 | if (kVerbosePcFixup) { |
| 1564 | LOG(INFO) << "Source:"; |
| 1565 | DumpLIRInsn(lir, 0); |
| 1566 | LOG(INFO) << "Target:"; |
| 1567 | DumpLIRInsn(target_lir, 0); |
| 1568 | LOG(INFO) << "Delta " << delta; |
| 1569 | } |
| 1570 | lir->operands[0] = delta; |
| 1571 | break; |
| 1572 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1573 | case kX86Jecxz8: { |
| 1574 | LIR *target_lir = lir->target; |
| 1575 | DCHECK(target_lir != NULL); |
| 1576 | CodeOffset pc; |
| 1577 | pc = lir->offset + 2; // opcode + rel8 |
| 1578 | CodeOffset target = target_lir->offset; |
| 1579 | int delta = target - pc; |
| 1580 | lir->operands[0] = delta; |
| 1581 | DCHECK(IS_SIMM8(delta)); |
| 1582 | break; |
| 1583 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1584 | case kX86Jmp8: { |
| 1585 | LIR *target_lir = lir->target; |
| 1586 | DCHECK(target_lir != NULL); |
| 1587 | int delta = 0; |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1588 | CodeOffset pc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1589 | if (IS_SIMM8(lir->operands[0])) { |
| 1590 | pc = lir->offset + 2 /* opcode + rel8 */; |
| 1591 | } else { |
| 1592 | pc = lir->offset + 5 /* opcode + rel32 */; |
| 1593 | } |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1594 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1595 | delta = target - pc; |
| 1596 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { |
| 1597 | // Useless branch |
buzbee | 252254b | 2013-09-08 16:20:53 -0700 | [diff] [blame] | 1598 | NopLIR(lir); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1599 | if (kVerbosePcFixup) { |
| 1600 | LOG(INFO) << "Retry for useless branch at " << lir->offset; |
| 1601 | } |
| 1602 | res = kRetryAll; |
| 1603 | } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { |
| 1604 | if (kVerbosePcFixup) { |
| 1605 | LOG(INFO) << "Retry for JMP growth at " << lir->offset; |
| 1606 | } |
| 1607 | lir->opcode = kX86Jmp32; |
| 1608 | SetupResourceMasks(lir); |
| 1609 | res = kRetryAll; |
| 1610 | } |
| 1611 | lir->operands[0] = delta; |
| 1612 | break; |
| 1613 | } |
| 1614 | case kX86Jmp32: { |
| 1615 | LIR *target_lir = lir->target; |
| 1616 | DCHECK(target_lir != NULL); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1617 | CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; |
| 1618 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1619 | int delta = target - pc; |
| 1620 | lir->operands[0] = delta; |
| 1621 | break; |
| 1622 | } |
| 1623 | default: |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 1624 | if (lir->flags.fixup == kFixupLoad) { |
| 1625 | LIR *target_lir = lir->target; |
| 1626 | DCHECK(target_lir != NULL); |
| 1627 | CodeOffset target = target_lir->offset; |
| 1628 | lir->operands[2] = target; |
| 1629 | int newSize = GetInsnSize(lir); |
| 1630 | if (newSize != lir->flags.size) { |
| 1631 | lir->flags.size = newSize; |
| 1632 | res = kRetryAll; |
| 1633 | } |
| 1634 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1635 | break; |
| 1636 | } |
| 1637 | } |
| 1638 | |
| 1639 | /* |
| 1640 | * If one of the pc-relative instructions expanded we'll have |
| 1641 | * to make another pass. Don't bother to fully assemble the |
| 1642 | * instruction. |
| 1643 | */ |
| 1644 | if (res != kSuccess) { |
| 1645 | continue; |
| 1646 | } |
| 1647 | CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); |
| 1648 | const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; |
| 1649 | size_t starting_cbuf_size = code_buffer_.size(); |
| 1650 | switch (entry->kind) { |
| 1651 | case kData: // 4 bytes of data |
| 1652 | code_buffer_.push_back(lir->operands[0]); |
| 1653 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1654 | case kNullary: // 1 byte of opcode and possible prefixes. |
| 1655 | EmitNullary(entry); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1656 | break; |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 1657 | case kRegOpcode: // lir operands - 0: reg |
| 1658 | EmitOpRegOpcode(entry, lir->operands[0]); |
| 1659 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1660 | case kReg: // lir operands - 0: reg |
| 1661 | EmitOpReg(entry, lir->operands[0]); |
| 1662 | break; |
| 1663 | case kMem: // lir operands - 0: base, 1: disp |
| 1664 | EmitOpMem(entry, lir->operands[0], lir->operands[1]); |
| 1665 | break; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1666 | case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
| 1667 | EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]); |
| 1668 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1669 | case kMemReg: // lir operands - 0: base, 1: disp, 2: reg |
| 1670 | EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1671 | break; |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1672 | case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
| 1673 | EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1674 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1675 | case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate |
| 1676 | EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1677 | lir->operands[3], lir->operands[4]); |
| 1678 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1679 | case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg |
| 1680 | EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1681 | lir->operands[3], lir->operands[4]); |
| 1682 | break; |
| 1683 | case kRegMem: // lir operands - 0: reg, 1: base, 2: disp |
| 1684 | EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1685 | break; |
| 1686 | case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp |
| 1687 | EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1688 | lir->operands[3], lir->operands[4]); |
| 1689 | break; |
| 1690 | case kRegThread: // lir operands - 0: reg, 1: disp |
| 1691 | EmitRegThread(entry, lir->operands[0], lir->operands[1]); |
| 1692 | break; |
| 1693 | case kRegReg: // lir operands - 0: reg1, 1: reg2 |
| 1694 | EmitRegReg(entry, lir->operands[0], lir->operands[1]); |
| 1695 | break; |
| 1696 | case kRegRegStore: // lir operands - 0: reg2, 1: reg1 |
| 1697 | EmitRegReg(entry, lir->operands[1], lir->operands[0]); |
| 1698 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1699 | case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1700 | EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1701 | lir->operands[3]); |
| 1702 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1703 | case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1704 | EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1705 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1706 | case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm |
| 1707 | EmitRegRegImm(entry, lir->operands[1], lir->operands[0], lir->operands[2]); |
| 1708 | break; |
| 1709 | case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1710 | EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1711 | lir->operands[3]); |
| 1712 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1713 | case kRegImm: // lir operands - 0: reg, 1: immediate |
| 1714 | EmitRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1715 | break; |
| 1716 | case kThreadImm: // lir operands - 0: disp, 1: immediate |
| 1717 | EmitThreadImm(entry, lir->operands[0], lir->operands[1]); |
| 1718 | break; |
| 1719 | case kMovRegImm: // lir operands - 0: reg, 1: immediate |
| 1720 | EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1721 | break; |
| 1722 | case kShiftRegImm: // lir operands - 0: reg, 1: immediate |
| 1723 | EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1724 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1725 | case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate |
| 1726 | EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1727 | break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1728 | case kShiftRegCl: // lir operands - 0: reg, 1: cl |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1729 | EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); |
| 1730 | break; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1731 | case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl |
| 1732 | EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1733 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1734 | case kRegCond: // lir operands - 0: reg, 1: condition |
| 1735 | EmitRegCond(entry, lir->operands[0], lir->operands[1]); |
| 1736 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1737 | case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition |
| 1738 | EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1739 | break; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1740 | case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition |
| 1741 | EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1742 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1743 | case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1744 | EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1745 | lir->operands[3]); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1746 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1747 | case kJmp: // lir operands - 0: rel |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 1748 | if (entry->opcode == kX86JmpT) { |
| 1749 | // This works since the instruction format for jmp and call is basically the same and |
| 1750 | // EmitCallThread loads opcode info. |
| 1751 | EmitCallThread(entry, lir->operands[0]); |
| 1752 | } else { |
| 1753 | EmitJmp(entry, lir->operands[0]); |
| 1754 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1755 | break; |
| 1756 | case kJcc: // lir operands - 0: rel, 1: CC, target assigned |
| 1757 | EmitJcc(entry, lir->operands[0], lir->operands[1]); |
| 1758 | break; |
| 1759 | case kCall: |
| 1760 | switch (entry->opcode) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1761 | case kX86CallI: // lir operands - 0: disp |
| 1762 | EmitCallImmediate(entry, lir->operands[0]); |
| 1763 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1764 | case kX86CallM: // lir operands - 0: base, 1: disp |
| 1765 | EmitCallMem(entry, lir->operands[0], lir->operands[1]); |
| 1766 | break; |
| 1767 | case kX86CallT: // lir operands - 0: disp |
| 1768 | EmitCallThread(entry, lir->operands[0]); |
| 1769 | break; |
| 1770 | default: |
| 1771 | EmitUnimplemented(entry, lir); |
| 1772 | break; |
| 1773 | } |
| 1774 | break; |
| 1775 | case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table |
| 1776 | EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1777 | lir->operands[3], lir->operands[4]); |
| 1778 | break; |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1779 | case kMacro: // lir operands - 0: reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1780 | EmitMacro(entry, lir->operands[0], lir->offset); |
| 1781 | break; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 1782 | case kNop: // TODO: these instruction kinds are missing implementations. |
| 1783 | case kThreadReg: |
| 1784 | case kRegArrayImm: |
| 1785 | case kShiftArrayImm: |
| 1786 | case kShiftArrayCl: |
| 1787 | case kArrayCond: |
| 1788 | case kUnimplemented: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1789 | EmitUnimplemented(entry, lir); |
| 1790 | break; |
| 1791 | } |
| 1792 | CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)), |
| 1793 | code_buffer_.size() - starting_cbuf_size) |
| 1794 | << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; |
| 1795 | } |
| 1796 | return res; |
| 1797 | } |
| 1798 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1799 | // LIR offset assignment. |
| 1800 | // TODO: consolidate w/ Arm assembly mechanism. |
| 1801 | int X86Mir2Lir::AssignInsnOffsets() { |
| 1802 | LIR* lir; |
| 1803 | int offset = 0; |
| 1804 | |
| 1805 | for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { |
| 1806 | lir->offset = offset; |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 1807 | if (LIKELY(!IsPseudoLirOp(lir->opcode))) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1808 | if (!lir->flags.is_nop) { |
| 1809 | offset += lir->flags.size; |
| 1810 | } |
| 1811 | } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { |
| 1812 | if (offset & 0x2) { |
| 1813 | offset += 2; |
| 1814 | lir->operands[0] = 1; |
| 1815 | } else { |
| 1816 | lir->operands[0] = 0; |
| 1817 | } |
| 1818 | } |
| 1819 | /* Pseudo opcodes don't consume space */ |
| 1820 | } |
| 1821 | return offset; |
| 1822 | } |
| 1823 | |
| 1824 | /* |
| 1825 | * Walk the compilation unit and assign offsets to instructions |
| 1826 | * and literals and compute the total size of the compiled unit. |
| 1827 | * TODO: consolidate w/ Arm assembly mechanism. |
| 1828 | */ |
| 1829 | void X86Mir2Lir::AssignOffsets() { |
| 1830 | int offset = AssignInsnOffsets(); |
| 1831 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1832 | if (const_vectors_ != nullptr) { |
| 1833 | /* assign offsets to vector literals */ |
| 1834 | |
| 1835 | // First, get offset to 12 mod 16 to align to 16 byte boundary. |
| 1836 | // This will ensure that the vector is 16 byte aligned, as the procedure is |
| 1837 | // always aligned at at 4 mod 16. |
| 1838 | int align_size = (16-4) - (offset & 0xF); |
| 1839 | if (align_size < 0) { |
| 1840 | align_size += 16; |
| 1841 | } |
| 1842 | |
| 1843 | offset += align_size; |
| 1844 | |
| 1845 | // Now assign each literal the right offset. |
| 1846 | for (LIR *p = const_vectors_; p != nullptr; p = p->next) { |
| 1847 | p->offset = offset; |
| 1848 | offset += 16; |
| 1849 | } |
| 1850 | } |
| 1851 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1852 | /* Const values have to be word aligned */ |
Andreas Gampe | 6601882 | 2014-05-05 20:47:19 -0700 | [diff] [blame] | 1853 | offset = RoundUp(offset, 4); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1854 | |
| 1855 | /* Set up offsets for literals */ |
| 1856 | data_offset_ = offset; |
| 1857 | |
| 1858 | offset = AssignLiteralOffset(offset); |
| 1859 | |
| 1860 | offset = AssignSwitchTablesOffset(offset); |
| 1861 | |
| 1862 | offset = AssignFillArrayDataOffset(offset); |
| 1863 | |
| 1864 | total_size_ = offset; |
| 1865 | } |
| 1866 | |
| 1867 | /* |
| 1868 | * Go over each instruction in the list and calculate the offset from the top |
| 1869 | * before sending them off to the assembler. If out-of-range branch distance is |
| 1870 | * seen rearrange the instructions a bit to correct it. |
| 1871 | * TODO: consolidate w/ Arm assembly mechanism. |
| 1872 | */ |
| 1873 | void X86Mir2Lir::AssembleLIR() { |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 1874 | cu_->NewTimingSplit("Assemble"); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1875 | |
| 1876 | // We will remove the method address if we never ended up using it |
| 1877 | if (store_method_addr_ && !store_method_addr_used_) { |
| 1878 | setup_method_address_[0]->flags.is_nop = true; |
| 1879 | setup_method_address_[1]->flags.is_nop = true; |
| 1880 | } |
| 1881 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1882 | AssignOffsets(); |
| 1883 | int assembler_retries = 0; |
| 1884 | /* |
| 1885 | * Assemble here. Note that we generate code with optimistic assumptions |
| 1886 | * and if found now to work, we'll have to redo the sequence and retry. |
| 1887 | */ |
| 1888 | |
| 1889 | while (true) { |
| 1890 | AssemblerStatus res = AssembleInstructions(0); |
| 1891 | if (res == kSuccess) { |
| 1892 | break; |
| 1893 | } else { |
| 1894 | assembler_retries++; |
| 1895 | if (assembler_retries > MAX_ASSEMBLER_RETRIES) { |
| 1896 | CodegenDump(); |
| 1897 | LOG(FATAL) << "Assembler error - too many retries"; |
| 1898 | } |
| 1899 | // Redo offsets and try again |
| 1900 | AssignOffsets(); |
| 1901 | code_buffer_.clear(); |
| 1902 | } |
| 1903 | } |
| 1904 | |
| 1905 | // Install literals |
| 1906 | InstallLiteralPools(); |
| 1907 | |
| 1908 | // Install switch tables |
| 1909 | InstallSwitchTables(); |
| 1910 | |
| 1911 | // Install fill array data |
| 1912 | InstallFillArrayData(); |
| 1913 | |
| 1914 | // Create the mapping table and native offset to reference map. |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 1915 | cu_->NewTimingSplit("PcMappingTable"); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1916 | CreateMappingTables(); |
| 1917 | |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 1918 | cu_->NewTimingSplit("GcMap"); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1919 | CreateNativeGcMap(); |
| 1920 | } |
| 1921 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1922 | } // namespace art |