Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains register alloction support. */ |
| 18 | |
| 19 | #include "dex/compiler_ir.h" |
| 20 | #include "dex/compiler_internals.h" |
| 21 | #include "mir_to_lir-inl.h" |
| 22 | |
| 23 | namespace art { |
| 24 | |
| 25 | /* |
| 26 | * Free all allocated temps in the temp pools. Note that this does |
| 27 | * not affect the "liveness" of a temp register, which will stay |
| 28 | * live until it is either explicitly killed or reallocated. |
| 29 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 30 | void Mir2Lir::ResetRegPool() { |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 31 | GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); |
| 32 | for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 33 | info->MarkFree(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 34 | } |
| 35 | // Reset temp tracking sanity check. |
| 36 | if (kIsDebugBuild) { |
| 37 | live_sreg_ = INVALID_SREG; |
| 38 | } |
| 39 | } |
| 40 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 41 | Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, uint64_t mask) |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 42 | : reg_(r), is_temp_(false), wide_value_(false), dirty_(false), aliased_(false), partner_(r), |
| 43 | s_reg_(INVALID_SREG), def_use_mask_(mask), master_(this) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 44 | switch (r.StorageSize()) { |
| 45 | case 0: storage_mask_ = 0xffffffff; break; |
| 46 | case 4: storage_mask_ = 0x00000001; break; |
| 47 | case 8: storage_mask_ = 0x00000003; break; |
| 48 | case 16: storage_mask_ = 0x0000000f; break; |
| 49 | case 32: storage_mask_ = 0x000000ff; break; |
| 50 | case 64: storage_mask_ = 0x0000ffff; break; |
| 51 | case 128: storage_mask_ = 0xffffffff; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 52 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 53 | used_storage_ = r.Valid() ? ~storage_mask_ : storage_mask_; |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 54 | liveness_ = used_storage_; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 55 | } |
| 56 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 57 | Mir2Lir::RegisterPool::RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, |
| 58 | const std::vector<RegStorage>& core_regs, |
| 59 | const std::vector<RegStorage>& sp_regs, |
| 60 | const std::vector<RegStorage>& dp_regs, |
| 61 | const std::vector<RegStorage>& reserved_regs, |
| 62 | const std::vector<RegStorage>& core_temps, |
| 63 | const std::vector<RegStorage>& sp_temps, |
| 64 | const std::vector<RegStorage>& dp_temps) : |
| 65 | core_regs_(arena, core_regs.size()), next_core_reg_(0), sp_regs_(arena, sp_regs.size()), |
| 66 | next_sp_reg_(0), dp_regs_(arena, dp_regs.size()), next_dp_reg_(0), m2l_(m2l) { |
| 67 | // Initialize the fast lookup map. |
| 68 | m2l_->reginfo_map_.Reset(); |
| 69 | m2l_->reginfo_map_.Resize(RegStorage::kMaxRegs); |
| 70 | for (unsigned i = 0; i < RegStorage::kMaxRegs; i++) { |
| 71 | m2l_->reginfo_map_.Insert(nullptr); |
| 72 | } |
| 73 | |
| 74 | // Construct the register pool. |
| 75 | for (RegStorage reg : core_regs) { |
| 76 | RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); |
| 77 | m2l_->reginfo_map_.Put(reg.GetReg(), info); |
| 78 | core_regs_.Insert(info); |
| 79 | } |
| 80 | for (RegStorage reg : sp_regs) { |
| 81 | RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); |
| 82 | m2l_->reginfo_map_.Put(reg.GetReg(), info); |
| 83 | sp_regs_.Insert(info); |
| 84 | } |
| 85 | for (RegStorage reg : dp_regs) { |
| 86 | RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); |
| 87 | m2l_->reginfo_map_.Put(reg.GetReg(), info); |
| 88 | dp_regs_.Insert(info); |
| 89 | } |
| 90 | |
| 91 | // Keep special registers from being allocated. |
| 92 | for (RegStorage reg : reserved_regs) { |
| 93 | m2l_->MarkInUse(reg); |
| 94 | } |
| 95 | |
| 96 | // Mark temp regs - all others not in use can be used for promotion |
| 97 | for (RegStorage reg : core_temps) { |
| 98 | m2l_->MarkTemp(reg); |
| 99 | } |
| 100 | for (RegStorage reg : sp_temps) { |
| 101 | m2l_->MarkTemp(reg); |
| 102 | } |
| 103 | for (RegStorage reg : dp_temps) { |
| 104 | m2l_->MarkTemp(reg); |
| 105 | } |
| 106 | |
| 107 | // Add an entry for InvalidReg with zero'd mask. |
| 108 | RegisterInfo* invalid_reg = new (arena) RegisterInfo(RegStorage::InvalidReg(), 0); |
| 109 | m2l_->reginfo_map_.Put(RegStorage::InvalidReg().GetReg(), invalid_reg); |
| 110 | } |
| 111 | |
| 112 | void Mir2Lir::DumpRegPool(GrowableArray<RegisterInfo*>* regs) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 113 | LOG(INFO) << "================================================"; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 114 | GrowableArray<RegisterInfo*>::Iterator it(regs); |
| 115 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 116 | LOG(INFO) << StringPrintf( |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 117 | "R[%d:%d:%c]: T:%d, U:%d, W:%d, p:%d, LV:%d, D:%d, SR:%d, DEF:%d", |
| 118 | info->GetReg().GetReg(), info->GetReg().GetRegNum(), info->GetReg().IsFloat() ? 'f' : 'c', |
| 119 | info->IsTemp(), info->InUse(), info->IsWide(), info->Partner().GetReg(), info->IsLive(), |
| 120 | info->IsDirty(), info->SReg(), info->DefStart() != nullptr); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 121 | } |
| 122 | LOG(INFO) << "================================================"; |
| 123 | } |
| 124 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 125 | void Mir2Lir::DumpCoreRegPool() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 126 | DumpRegPool(®_pool_->core_regs_); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 127 | } |
| 128 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 129 | void Mir2Lir::DumpFpRegPool() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 130 | DumpRegPool(®_pool_->sp_regs_); |
| 131 | DumpRegPool(®_pool_->dp_regs_); |
| 132 | } |
| 133 | |
| 134 | void Mir2Lir::DumpRegPools() { |
| 135 | LOG(INFO) << "Core registers"; |
| 136 | DumpCoreRegPool(); |
| 137 | LOG(INFO) << "FP registers"; |
| 138 | DumpFpRegPool(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 139 | } |
| 140 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 141 | void Mir2Lir::Clobber(RegStorage reg) { |
| 142 | if (reg.IsPair()) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 143 | DCHECK(!GetRegInfo(reg.GetLow())->IsAliased()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 144 | ClobberBody(GetRegInfo(reg.GetLow())); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 145 | DCHECK(!GetRegInfo(reg.GetHigh())->IsAliased()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 146 | ClobberBody(GetRegInfo(reg.GetHigh())); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 147 | } else { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 148 | RegisterInfo* info = GetRegInfo(reg); |
| 149 | if (info->IsAliased()) { |
| 150 | ClobberAliases(info); |
| 151 | } else if (info != info->Master() && info->Master()->SReg() != INVALID_SREG) { |
| 152 | ClobberBody(info->Master()); |
| 153 | } |
| 154 | ClobberBody(info); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 155 | } |
| 156 | } |
| 157 | |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 158 | void Mir2Lir::ClobberAliases(RegisterInfo* info) { |
| 159 | DCHECK(info->IsAliased()); |
| 160 | GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); |
| 161 | for (RegisterInfo* tmpreg_info = iter.Next(); tmpreg_info != NULL; tmpreg_info = iter.Next()) { |
| 162 | if (tmpreg_info->Master() == info) { |
| 163 | // tmpreg_info is an alias of info. |
| 164 | ClobberBody(tmpreg_info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 165 | } |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | /* |
| 170 | * Break the association between a Dalvik vreg and a physical temp register of either register |
| 171 | * class. |
| 172 | * TODO: Ideally, the public version of this code should not exist. Besides its local usage |
| 173 | * in the register utilities, is is also used by code gen routines to work around a deficiency in |
| 174 | * local register allocation, which fails to distinguish between the "in" and "out" identities |
| 175 | * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg |
| 176 | * is used both as the source and destination register of an operation in which the type |
| 177 | * changes (for example: INT_TO_FLOAT v1, v1). Revisit when improved register allocation is |
| 178 | * addressed. |
| 179 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 180 | void Mir2Lir::ClobberSReg(int s_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 181 | if (s_reg != INVALID_SREG) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 182 | if (kIsDebugBuild && s_reg == live_sreg_) { |
| 183 | live_sreg_ = INVALID_SREG; |
| 184 | } |
| 185 | GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); |
| 186 | for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { |
| 187 | if (info->SReg() == s_reg) { |
| 188 | if (info->IsAliased()) { |
| 189 | // TUNING: if this gets hot, we could add links to follow - aliasing is static. |
| 190 | ClobberAliases(info); |
| 191 | } |
| 192 | ClobberBody(info); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 193 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 194 | } |
| 195 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | /* |
| 199 | * SSA names associated with the initial definitions of Dalvik |
| 200 | * registers are the same as the Dalvik register number (and |
| 201 | * thus take the same position in the promotion_map. However, |
| 202 | * the special Method* and compiler temp resisters use negative |
| 203 | * v_reg numbers to distinguish them and can have an arbitrary |
| 204 | * ssa name (above the last original Dalvik register). This function |
| 205 | * maps SSA names to positions in the promotion_map array. |
| 206 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 207 | int Mir2Lir::SRegToPMap(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 208 | DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs()); |
| 209 | DCHECK_GE(s_reg, 0); |
| 210 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 211 | if (v_reg >= 0) { |
| 212 | DCHECK_LT(v_reg, cu_->num_dalvik_registers); |
| 213 | return v_reg; |
| 214 | } else { |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 215 | /* |
| 216 | * It must be the case that the v_reg for temporary is less than or equal to the |
| 217 | * base reg for temps. For that reason, "position" must be zero or positive. |
| 218 | */ |
| 219 | unsigned int position = std::abs(v_reg) - std::abs(static_cast<int>(kVRegTempBaseReg)); |
| 220 | |
| 221 | // The temporaries are placed after dalvik registers in the promotion map |
| 222 | DCHECK_LT(position, mir_graph_->GetNumUsedCompilerTemps()); |
| 223 | return cu_->num_dalvik_registers + position; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 224 | } |
| 225 | } |
| 226 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 227 | // TODO: refactor following Alloc/Record routines - much commonality. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 228 | void Mir2Lir::RecordCorePromotion(RegStorage reg, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 229 | int p_map_idx = SRegToPMap(s_reg); |
| 230 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 231 | int reg_num = reg.GetRegNum(); |
| 232 | GetRegInfo(reg)->MarkInUse(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 233 | core_spill_mask_ |= (1 << reg_num); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 234 | // Include reg for later sort |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 235 | core_vmap_table_.push_back(reg_num << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 236 | num_core_spills_++; |
| 237 | promotion_map_[p_map_idx].core_location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 238 | promotion_map_[p_map_idx].core_reg = reg_num; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 239 | } |
| 240 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 241 | /* Reserve a callee-save register. Return InvalidReg if none available */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 242 | RegStorage Mir2Lir::AllocPreservedCoreReg(int s_reg) { |
| 243 | RegStorage res; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 244 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->core_regs_); |
| 245 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 246 | if (!info->IsTemp() && !info->InUse()) { |
| 247 | res = info->GetReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 248 | RecordCorePromotion(res, s_reg); |
| 249 | break; |
| 250 | } |
| 251 | } |
| 252 | return res; |
| 253 | } |
| 254 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 255 | void Mir2Lir::RecordSinglePromotion(RegStorage reg, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 256 | int p_map_idx = SRegToPMap(s_reg); |
| 257 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 258 | GetRegInfo(reg)->MarkInUse(); |
| 259 | MarkPreservedSingle(v_reg, reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 260 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 261 | promotion_map_[p_map_idx].FpReg = reg.GetReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 262 | } |
| 263 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 264 | // Reserve a callee-save sp single register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 265 | RegStorage Mir2Lir::AllocPreservedSingle(int s_reg) { |
| 266 | RegStorage res; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 267 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); |
| 268 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 269 | if (!info->IsTemp() && !info->InUse()) { |
| 270 | res = info->GetReg(); |
| 271 | RecordSinglePromotion(res, s_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 272 | break; |
| 273 | } |
| 274 | } |
| 275 | return res; |
| 276 | } |
| 277 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 278 | void Mir2Lir::RecordDoublePromotion(RegStorage reg, int s_reg) { |
| 279 | int p_map_idx = SRegToPMap(s_reg); |
| 280 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 281 | GetRegInfo(reg)->MarkInUse(); |
| 282 | MarkPreservedDouble(v_reg, reg); |
| 283 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
| 284 | promotion_map_[p_map_idx].FpReg = reg.GetReg(); |
| 285 | } |
| 286 | |
| 287 | // Reserve a callee-save dp solo register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 288 | RegStorage Mir2Lir::AllocPreservedDouble(int s_reg) { |
| 289 | RegStorage res; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 290 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->dp_regs_); |
| 291 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 292 | if (!info->IsTemp() && !info->InUse()) { |
| 293 | res = info->GetReg(); |
| 294 | RecordDoublePromotion(res, s_reg); |
| 295 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 296 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 297 | } |
| 298 | return res; |
| 299 | } |
| 300 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 301 | |
| 302 | RegStorage Mir2Lir::AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required) { |
| 303 | int num_regs = regs.Size(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 304 | int next = *next_temp; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 305 | for (int i = 0; i< num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 306 | if (next >= num_regs) |
| 307 | next = 0; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 308 | RegisterInfo* info = regs.Get(next); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 309 | // Try to allocate a register that doesn't hold a live value. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 310 | if (info->IsTemp() && !info->InUse() && !info->IsLive()) { |
| 311 | Clobber(info->GetReg()); |
| 312 | info->MarkInUse(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 313 | /* |
| 314 | * NOTE: "wideness" is an attribute of how the container is used, not its physical size. |
| 315 | * The caller will set wideness as appropriate. |
| 316 | */ |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 317 | info->SetIsWide(false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 318 | *next_temp = next + 1; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 319 | return info->GetReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 320 | } |
| 321 | next++; |
| 322 | } |
| 323 | next = *next_temp; |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 324 | // No free non-live regs. Anything we can kill? |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 325 | for (int i = 0; i< num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 326 | if (next >= num_regs) |
| 327 | next = 0; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 328 | RegisterInfo* info = regs.Get(next); |
| 329 | if (info->IsTemp() && !info->InUse()) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 330 | // Got one. Kill it. |
| 331 | ClobberSReg(info->SReg()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 332 | Clobber(info->GetReg()); |
| 333 | info->MarkInUse(); |
| 334 | info->SetIsWide(false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 335 | *next_temp = next + 1; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 336 | return info->GetReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 337 | } |
| 338 | next++; |
| 339 | } |
| 340 | if (required) { |
| 341 | CodegenDump(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 342 | DumpRegPools(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 343 | LOG(FATAL) << "No free temp registers"; |
| 344 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 345 | return RegStorage::InvalidReg(); // No register available |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 346 | } |
| 347 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 348 | /* Return a temp if one is available, -1 otherwise */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 349 | RegStorage Mir2Lir::AllocFreeTemp() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 350 | return AllocTempBody(reg_pool_->core_regs_, ®_pool_->next_core_reg_, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 351 | } |
| 352 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 353 | RegStorage Mir2Lir::AllocTemp() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 354 | return AllocTempBody(reg_pool_->core_regs_, ®_pool_->next_core_reg_, true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 355 | } |
| 356 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 357 | RegStorage Mir2Lir::AllocTempSingle() { |
| 358 | RegStorage res = AllocTempBody(reg_pool_->sp_regs_, ®_pool_->next_sp_reg_, true); |
| 359 | DCHECK(res.IsSingle()) << "Reg: 0x" << std::hex << res.GetRawBits(); |
| 360 | return res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 361 | } |
| 362 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 363 | RegStorage Mir2Lir::AllocTempDouble() { |
| 364 | RegStorage res = AllocTempBody(reg_pool_->dp_regs_, ®_pool_->next_dp_reg_, true); |
| 365 | DCHECK(res.IsDouble()) << "Reg: 0x" << std::hex << res.GetRawBits(); |
| 366 | return res; |
| 367 | } |
| 368 | |
| 369 | RegStorage Mir2Lir::FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg) { |
| 370 | RegStorage res; |
| 371 | GrowableArray<RegisterInfo*>::Iterator it(®s); |
| 372 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 373 | if ((info->SReg() == s_reg) && info->IsLive()) { |
| 374 | res = info->GetReg(); |
| 375 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 376 | } |
| 377 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 378 | return res; |
| 379 | } |
| 380 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 381 | RegStorage Mir2Lir::AllocLiveReg(int s_reg, int reg_class, bool wide) { |
| 382 | RegStorage reg; |
| 383 | // TODO: might be worth a sanity check here to verify at most 1 live reg per s_reg. |
| 384 | if ((reg_class == kAnyReg) || (reg_class == kFPReg)) { |
| 385 | reg = FindLiveReg(wide ? reg_pool_->dp_regs_ : reg_pool_->sp_regs_, s_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 386 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 387 | if (!reg.Valid() && (reg_class != kFPReg)) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 388 | // TODO: add 64-bit core pool similar to above. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 389 | reg = FindLiveReg(reg_pool_->core_regs_, s_reg); |
| 390 | } |
| 391 | if (reg.Valid()) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 392 | if (wide && !reg.IsFloat() && !Is64BitInstructionSet(cu_->instruction_set)) { |
| 393 | // Only allow reg pairs for core regs on 32-bit targets. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 394 | RegStorage high_reg = FindLiveReg(reg_pool_->core_regs_, s_reg + 1); |
| 395 | if (high_reg.Valid()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 396 | reg = RegStorage::MakeRegPair(reg, high_reg); |
| 397 | MarkWide(reg); |
| 398 | } else { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 399 | // Only half available. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 400 | reg = RegStorage::InvalidReg(); |
| 401 | } |
| 402 | } |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 403 | if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) { |
| 404 | // Width mismatch - don't try to reuse. |
| 405 | reg = RegStorage::InvalidReg(); |
| 406 | } |
| 407 | } |
| 408 | if (reg.Valid()) { |
| 409 | if (reg.IsPair()) { |
| 410 | RegisterInfo* info_low = GetRegInfo(reg.GetLow()); |
| 411 | RegisterInfo* info_high = GetRegInfo(reg.GetHigh()); |
| 412 | if (info_low->IsTemp()) { |
| 413 | info_low->MarkInUse(); |
| 414 | } |
| 415 | if (info_high->IsTemp()) { |
| 416 | info_high->MarkInUse(); |
| 417 | } |
| 418 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 419 | RegisterInfo* info = GetRegInfo(reg); |
| 420 | if (info->IsTemp()) { |
| 421 | info->MarkInUse(); |
| 422 | } |
| 423 | } |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 424 | } else { |
| 425 | // Either not found, or something didn't match up. Clobber to prevent any stale instances. |
| 426 | ClobberSReg(s_reg); |
| 427 | if (wide) { |
| 428 | ClobberSReg(s_reg + 1); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 429 | } |
| 430 | } |
| 431 | return reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 432 | } |
| 433 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 434 | void Mir2Lir::FreeTemp(RegStorage reg) { |
| 435 | if (reg.IsPair()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 436 | FreeTemp(reg.GetLow()); |
| 437 | FreeTemp(reg.GetHigh()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 438 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 439 | RegisterInfo* p = GetRegInfo(reg); |
| 440 | if (p->IsTemp()) { |
| 441 | p->MarkFree(); |
| 442 | p->SetIsWide(false); |
| 443 | p->SetPartner(reg); |
| 444 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 445 | } |
| 446 | } |
| 447 | |
buzbee | 262b299 | 2014-03-27 11:22:43 -0700 | [diff] [blame] | 448 | bool Mir2Lir::IsLive(RegStorage reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 449 | bool res; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 450 | if (reg.IsPair()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 451 | RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); |
| 452 | RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 453 | DCHECK_EQ(p_lo->IsLive(), p_hi->IsLive()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 454 | res = p_lo->IsLive() || p_hi->IsLive(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 455 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 456 | RegisterInfo* p = GetRegInfo(reg); |
| 457 | res = p->IsLive(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 458 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 459 | return res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 460 | } |
| 461 | |
buzbee | 262b299 | 2014-03-27 11:22:43 -0700 | [diff] [blame] | 462 | bool Mir2Lir::IsTemp(RegStorage reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 463 | bool res; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 464 | if (reg.IsPair()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 465 | RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); |
| 466 | RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); |
| 467 | res = p_lo->IsTemp() || p_hi->IsTemp(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 468 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 469 | RegisterInfo* p = GetRegInfo(reg); |
| 470 | res = p->IsTemp(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 471 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 472 | return res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 473 | } |
| 474 | |
buzbee | 262b299 | 2014-03-27 11:22:43 -0700 | [diff] [blame] | 475 | bool Mir2Lir::IsPromoted(RegStorage reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 476 | bool res; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 477 | if (reg.IsPair()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 478 | RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); |
| 479 | RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); |
| 480 | res = !p_lo->IsTemp() || !p_hi->IsTemp(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 481 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 482 | RegisterInfo* p = GetRegInfo(reg); |
| 483 | res = !p->IsTemp(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 484 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 485 | return res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 486 | } |
| 487 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 488 | bool Mir2Lir::IsDirty(RegStorage reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 489 | bool res; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 490 | if (reg.IsPair()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 491 | RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); |
| 492 | RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); |
| 493 | res = p_lo->IsDirty() || p_hi->IsDirty(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 494 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 495 | RegisterInfo* p = GetRegInfo(reg); |
| 496 | res = p->IsDirty(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 497 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 498 | return res; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 499 | } |
| 500 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 501 | /* |
| 502 | * Similar to AllocTemp(), but forces the allocation of a specific |
| 503 | * register. No check is made to see if the register was previously |
| 504 | * allocated. Use with caution. |
| 505 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 506 | void Mir2Lir::LockTemp(RegStorage reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 507 | DCHECK(IsTemp(reg)); |
| 508 | if (reg.IsPair()) { |
| 509 | RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); |
| 510 | RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); |
| 511 | p_lo->MarkInUse(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 512 | p_lo->MarkDead(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 513 | p_hi->MarkInUse(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 514 | p_hi->MarkDead(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 515 | } else { |
| 516 | RegisterInfo* p = GetRegInfo(reg); |
| 517 | p->MarkInUse(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 518 | p->MarkDead(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 519 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 520 | } |
| 521 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 522 | void Mir2Lir::ResetDef(RegStorage reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 523 | if (reg.IsPair()) { |
| 524 | GetRegInfo(reg.GetLow())->ResetDefBody(); |
| 525 | GetRegInfo(reg.GetHigh())->ResetDefBody(); |
| 526 | } else { |
| 527 | GetRegInfo(reg)->ResetDefBody(); |
| 528 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 529 | } |
| 530 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 531 | void Mir2Lir::NullifyRange(RegStorage reg, int s_reg) { |
| 532 | RegisterInfo* info = nullptr; |
| 533 | RegStorage rs = reg.IsPair() ? reg.GetLow() : reg; |
| 534 | if (IsTemp(rs)) { |
| 535 | info = GetRegInfo(reg); |
| 536 | } |
| 537 | if ((info != nullptr) && (info->DefStart() != nullptr) && (info->DefEnd() != nullptr)) { |
| 538 | DCHECK_EQ(info->SReg(), s_reg); // Make sure we're on the same page. |
| 539 | for (LIR* p = info->DefStart();; p = p->next) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 540 | NopLIR(p); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 541 | if (p == info->DefEnd()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 542 | break; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 543 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 544 | } |
| 545 | } |
| 546 | } |
| 547 | |
| 548 | /* |
| 549 | * Mark the beginning and end LIR of a def sequence. Note that |
| 550 | * on entry start points to the LIR prior to the beginning of the |
| 551 | * sequence. |
| 552 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 553 | void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 554 | DCHECK(!rl.wide); |
| 555 | DCHECK(start && start->next); |
| 556 | DCHECK(finish); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 557 | RegisterInfo* p = GetRegInfo(rl.reg); |
| 558 | p->SetDefStart(start->next); |
| 559 | p->SetDefEnd(finish); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | /* |
| 563 | * Mark the beginning and end LIR of a def sequence. Note that |
| 564 | * on entry start points to the LIR prior to the beginning of the |
| 565 | * sequence. |
| 566 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 567 | void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 568 | DCHECK(rl.wide); |
| 569 | DCHECK(start && start->next); |
| 570 | DCHECK(finish); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 571 | RegisterInfo* p; |
| 572 | if (rl.reg.IsPair()) { |
| 573 | p = GetRegInfo(rl.reg.GetLow()); |
| 574 | ResetDef(rl.reg.GetHigh()); // Only track low of pair |
| 575 | } else { |
| 576 | p = GetRegInfo(rl.reg); |
| 577 | } |
| 578 | p->SetDefStart(start->next); |
| 579 | p->SetDefEnd(finish); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 580 | } |
| 581 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 582 | RegLocation Mir2Lir::WideToNarrow(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 583 | DCHECK(rl.wide); |
| 584 | if (rl.location == kLocPhysReg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 585 | if (rl.reg.IsPair()) { |
| 586 | RegisterInfo* info_lo = GetRegInfo(rl.reg.GetLow()); |
| 587 | RegisterInfo* info_hi = GetRegInfo(rl.reg.GetHigh()); |
| 588 | if (info_lo->IsTemp()) { |
| 589 | info_lo->SetIsWide(false); |
| 590 | info_lo->ResetDefBody(); |
| 591 | } |
| 592 | if (info_hi->IsTemp()) { |
| 593 | info_hi->SetIsWide(false); |
| 594 | info_hi->ResetDefBody(); |
| 595 | } |
| 596 | rl.reg = rl.reg.GetLow(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 597 | } else { |
| 598 | /* |
| 599 | * TODO: If not a pair, we can't just drop the high register. On some targets, we may be |
| 600 | * able to re-cast the 64-bit register as 32 bits, so it might be worthwhile to revisit |
| 601 | * this code. Will probably want to make this a virtual function. |
| 602 | */ |
| 603 | // Can't narrow 64-bit register. Clobber. |
| 604 | if (GetRegInfo(rl.reg)->IsTemp()) { |
| 605 | Clobber(rl.reg); |
| 606 | FreeTemp(rl.reg); |
| 607 | } |
| 608 | rl.location = kLocDalvikFrame; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 609 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 610 | } |
| 611 | rl.wide = false; |
| 612 | return rl; |
| 613 | } |
| 614 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 615 | void Mir2Lir::ResetDefLoc(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 616 | DCHECK(!rl.wide); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 617 | if (IsTemp(rl.reg) && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 618 | NullifyRange(rl.reg, rl.s_reg_low); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 619 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 620 | ResetDef(rl.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 621 | } |
| 622 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 623 | void Mir2Lir::ResetDefLocWide(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 624 | DCHECK(rl.wide); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 625 | // If pair, only track low reg of pair. |
| 626 | RegStorage rs = rl.reg.IsPair() ? rl.reg.GetLow() : rl.reg; |
| 627 | if (IsTemp(rs) && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 628 | NullifyRange(rs, rl.s_reg_low); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 629 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 630 | ResetDef(rs); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 631 | } |
| 632 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 633 | void Mir2Lir::ResetDefTracking() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 634 | GrowableArray<RegisterInfo*>::Iterator core_it(®_pool_->core_regs_); |
| 635 | for (RegisterInfo* info = core_it.Next(); info != nullptr; info = core_it.Next()) { |
| 636 | info->ResetDefBody(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 637 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 638 | GrowableArray<RegisterInfo*>::Iterator sp_it(®_pool_->core_regs_); |
| 639 | for (RegisterInfo* info = sp_it.Next(); info != nullptr; info = sp_it.Next()) { |
| 640 | info->ResetDefBody(); |
| 641 | } |
| 642 | GrowableArray<RegisterInfo*>::Iterator dp_it(®_pool_->core_regs_); |
| 643 | for (RegisterInfo* info = dp_it.Next(); info != nullptr; info = dp_it.Next()) { |
| 644 | info->ResetDefBody(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 645 | } |
| 646 | } |
| 647 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 648 | void Mir2Lir::ClobberAllRegs() { |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 649 | GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); |
| 650 | for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 651 | ClobberBody(info); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 652 | } |
| 653 | } |
| 654 | |
| 655 | void Mir2Lir::FlushRegWide(RegStorage reg) { |
| 656 | if (reg.IsPair()) { |
| 657 | RegisterInfo* info1 = GetRegInfo(reg.GetLow()); |
| 658 | RegisterInfo* info2 = GetRegInfo(reg.GetHigh()); |
| 659 | DCHECK(info1 && info2 && info1->IsWide() && info2->IsWide() && |
| 660 | (info1->Partner() == info2->GetReg()) && (info2->Partner() == info1->GetReg())); |
| 661 | if ((info1->IsLive() && info1->IsDirty()) || (info2->IsLive() && info2->IsDirty())) { |
| 662 | if (!(info1->IsTemp() && info2->IsTemp())) { |
| 663 | /* Should not happen. If it does, there's a problem in eval_loc */ |
| 664 | LOG(FATAL) << "Long half-temp, half-promoted"; |
| 665 | } |
| 666 | |
| 667 | info1->SetIsDirty(false); |
| 668 | info2->SetIsDirty(false); |
| 669 | if (mir_graph_->SRegToVReg(info2->SReg()) < mir_graph_->SRegToVReg(info1->SReg())) { |
| 670 | info1 = info2; |
| 671 | } |
| 672 | int v_reg = mir_graph_->SRegToVReg(info1->SReg()); |
Vladimir Marko | 455759b | 2014-05-06 20:49:36 +0100 | [diff] [blame] | 673 | StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 674 | } |
| 675 | } else { |
| 676 | RegisterInfo* info = GetRegInfo(reg); |
| 677 | if (info->IsLive() && info->IsDirty()) { |
| 678 | info->SetIsDirty(false); |
| 679 | int v_reg = mir_graph_->SRegToVReg(info->SReg()); |
Vladimir Marko | 455759b | 2014-05-06 20:49:36 +0100 | [diff] [blame] | 680 | StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 681 | } |
| 682 | } |
| 683 | } |
| 684 | |
| 685 | void Mir2Lir::FlushReg(RegStorage reg) { |
| 686 | DCHECK(!reg.IsPair()); |
| 687 | RegisterInfo* info = GetRegInfo(reg); |
| 688 | if (info->IsLive() && info->IsDirty()) { |
| 689 | info->SetIsDirty(false); |
| 690 | int v_reg = mir_graph_->SRegToVReg(info->SReg()); |
| 691 | StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, kWord); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 692 | } |
| 693 | } |
| 694 | |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 695 | void Mir2Lir::FlushSpecificReg(RegisterInfo* info) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 696 | if (info->IsWide()) { |
| 697 | FlushRegWide(info->GetReg()); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 698 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 699 | FlushReg(info->GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 700 | } |
| 701 | } |
| 702 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 703 | void Mir2Lir::FlushAllRegs() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 704 | GrowableArray<RegisterInfo*>::Iterator it(&tempreg_info_); |
| 705 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 706 | if (info->IsLive() && info->IsDirty()) { |
| 707 | FlushSpecificReg(info); |
| 708 | } |
| 709 | DCHECK(info->IsTemp()); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 710 | info->MarkDead(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 711 | info->SetSReg(INVALID_SREG); |
| 712 | info->ResetDefBody(); |
| 713 | info->SetIsWide(false); |
| 714 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 715 | } |
| 716 | |
| 717 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 718 | bool Mir2Lir::RegClassMatches(int reg_class, RegStorage reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 719 | if (reg_class == kAnyReg) { |
| 720 | return true; |
| 721 | } else if (reg_class == kCoreReg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 722 | return !reg.IsFloat(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 723 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 724 | return reg.IsFloat(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 725 | } |
| 726 | } |
| 727 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 728 | void Mir2Lir::MarkLiveReg(RegStorage reg, int s_reg) { |
| 729 | RegisterInfo* info = GetRegInfo(reg); |
| 730 | if ((info->SReg() == s_reg) && info->IsLive()) { |
| 731 | return; // Already live. |
| 732 | } |
| 733 | if (s_reg != INVALID_SREG) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 734 | ClobberSReg(s_reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 735 | if (info->IsTemp()) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 736 | info->MarkLive(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 737 | } |
| 738 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 739 | // Can't be live if no associated s_reg. |
| 740 | DCHECK(info->IsTemp()); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame^] | 741 | info->MarkDead(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 742 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 743 | info->SetSReg(s_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 744 | } |
| 745 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 746 | void Mir2Lir::MarkLive(RegLocation loc) { |
| 747 | RegStorage reg = loc.reg; |
| 748 | int s_reg = loc.s_reg_low; |
| 749 | if (reg.IsPair()) { |
| 750 | MarkLiveReg(reg.GetLow(), s_reg); |
| 751 | MarkLiveReg(reg.GetHigh(), s_reg+1); |
| 752 | } else { |
| 753 | if (loc.wide) { |
| 754 | ClobberSReg(s_reg + 1); |
| 755 | } |
| 756 | MarkLiveReg(reg, s_reg); |
| 757 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 758 | } |
| 759 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 760 | void Mir2Lir::MarkTemp(RegStorage reg) { |
| 761 | DCHECK(!reg.IsPair()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 762 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 763 | tempreg_info_.Insert(info); |
| 764 | info->SetIsTemp(true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 765 | } |
| 766 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 767 | void Mir2Lir::UnmarkTemp(RegStorage reg) { |
| 768 | DCHECK(!reg.IsPair()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 769 | RegisterInfo* info = GetRegInfo(reg); |
| 770 | tempreg_info_.Delete(info); |
| 771 | info->SetIsTemp(false); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 772 | } |
| 773 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 774 | void Mir2Lir::MarkWide(RegStorage reg) { |
| 775 | if (reg.IsPair()) { |
| 776 | RegisterInfo* info_lo = GetRegInfo(reg.GetLow()); |
| 777 | RegisterInfo* info_hi = GetRegInfo(reg.GetHigh()); |
| 778 | info_lo->SetIsWide(true); |
| 779 | info_hi->SetIsWide(true); |
| 780 | info_lo->SetPartner(reg.GetHigh()); |
| 781 | info_hi->SetPartner(reg.GetLow()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 782 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 783 | RegisterInfo* info = GetRegInfo(reg); |
| 784 | info->SetIsWide(true); |
| 785 | info->SetPartner(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 786 | } |
| 787 | } |
| 788 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 789 | void Mir2Lir::MarkClean(RegLocation loc) { |
| 790 | if (loc.reg.IsPair()) { |
| 791 | RegisterInfo* info = GetRegInfo(loc.reg.GetLow()); |
| 792 | info->SetIsDirty(false); |
| 793 | info = GetRegInfo(loc.reg.GetHigh()); |
| 794 | info->SetIsDirty(false); |
| 795 | } else { |
| 796 | RegisterInfo* info = GetRegInfo(loc.reg); |
| 797 | info->SetIsDirty(false); |
| 798 | } |
| 799 | } |
| 800 | |
| 801 | // FIXME: need to verify rules/assumptions about how wide values are treated in 64BitSolos. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 802 | void Mir2Lir::MarkDirty(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 803 | if (loc.home) { |
| 804 | // If already home, can't be dirty |
| 805 | return; |
| 806 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 807 | if (loc.reg.IsPair()) { |
| 808 | RegisterInfo* info = GetRegInfo(loc.reg.GetLow()); |
| 809 | info->SetIsDirty(true); |
| 810 | info = GetRegInfo(loc.reg.GetHigh()); |
| 811 | info->SetIsDirty(true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 812 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 813 | RegisterInfo* info = GetRegInfo(loc.reg); |
| 814 | info->SetIsDirty(true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 815 | } |
| 816 | } |
| 817 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 818 | void Mir2Lir::MarkInUse(RegStorage reg) { |
| 819 | if (reg.IsPair()) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 820 | GetRegInfo(reg.GetLow())->MarkInUse(); |
| 821 | GetRegInfo(reg.GetHigh())->MarkInUse(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 822 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 823 | GetRegInfo(reg)->MarkInUse(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 824 | } |
| 825 | } |
| 826 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 827 | bool Mir2Lir::CheckCorePoolSanity() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 828 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->core_regs_); |
| 829 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 830 | RegStorage my_reg = info->GetReg(); |
| 831 | if (info->IsWide() && my_reg.IsPair()) { |
| 832 | int my_sreg = info->SReg(); |
| 833 | RegStorage partner_reg = info->Partner(); |
| 834 | RegisterInfo* partner = GetRegInfo(partner_reg); |
Brian Carlstrom | 6f485c6 | 2013-07-18 15:35:35 -0700 | [diff] [blame] | 835 | DCHECK(partner != NULL); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 836 | DCHECK(partner->IsWide()); |
| 837 | DCHECK_EQ(my_reg.GetReg(), partner->Partner().GetReg()); |
| 838 | int partner_sreg = partner->SReg(); |
Brian Carlstrom | 6f485c6 | 2013-07-18 15:35:35 -0700 | [diff] [blame] | 839 | if (my_sreg == INVALID_SREG) { |
| 840 | DCHECK_EQ(partner_sreg, INVALID_SREG); |
| 841 | } else { |
| 842 | int diff = my_sreg - partner_sreg; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 843 | DCHECK((diff == 0) || (diff == -1) || (diff == 1)); |
Brian Carlstrom | 6f485c6 | 2013-07-18 15:35:35 -0700 | [diff] [blame] | 844 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 845 | } else { |
| 846 | // TODO: add whatever sanity checks might be useful for 64BitSolo regs here. |
| 847 | // TODO: sanity checks for floating point pools? |
Brian Carlstrom | 6f485c6 | 2013-07-18 15:35:35 -0700 | [diff] [blame] | 848 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 849 | if (!info->IsLive()) { |
| 850 | DCHECK(info->DefStart() == NULL); |
| 851 | DCHECK(info->DefEnd() == NULL); |
Brian Carlstrom | 6f485c6 | 2013-07-18 15:35:35 -0700 | [diff] [blame] | 852 | } |
| 853 | } |
| 854 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 855 | } |
| 856 | |
| 857 | /* |
| 858 | * Return an updated location record with current in-register status. |
| 859 | * If the value lives in live temps, reflect that fact. No code |
| 860 | * is generated. If the live value is part of an older pair, |
| 861 | * clobber both low and high. |
| 862 | * TUNING: clobbering both is a bit heavy-handed, but the alternative |
| 863 | * is a bit complex when dealing with FP regs. Examine code to see |
| 864 | * if it's worthwhile trying to be more clever here. |
| 865 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 866 | RegLocation Mir2Lir::UpdateLoc(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 867 | DCHECK(!loc.wide); |
| 868 | DCHECK(CheckCorePoolSanity()); |
| 869 | if (loc.location != kLocPhysReg) { |
| 870 | DCHECK((loc.location == kLocDalvikFrame) || |
| 871 | (loc.location == kLocCompilerTemp)); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 872 | RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, false); |
| 873 | if (reg.Valid()) { |
| 874 | bool match = true; |
| 875 | RegisterInfo* info = GetRegInfo(reg); |
| 876 | match &= !reg.IsPair(); |
| 877 | match &= !info->IsWide(); |
| 878 | if (match) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 879 | loc.location = kLocPhysReg; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 880 | loc.reg = reg; |
| 881 | } else { |
| 882 | Clobber(reg); |
| 883 | FreeTemp(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 884 | } |
| 885 | } |
| 886 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 887 | return loc; |
| 888 | } |
| 889 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 890 | RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 891 | DCHECK(loc.wide); |
| 892 | DCHECK(CheckCorePoolSanity()); |
| 893 | if (loc.location != kLocPhysReg) { |
| 894 | DCHECK((loc.location == kLocDalvikFrame) || |
| 895 | (loc.location == kLocCompilerTemp)); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 896 | RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, true); |
| 897 | if (reg.Valid()) { |
| 898 | bool match = true; |
| 899 | if (reg.IsPair()) { |
| 900 | // If we've got a register pair, make sure that it was last used as the same pair. |
| 901 | RegisterInfo* info_lo = GetRegInfo(reg.GetLow()); |
| 902 | RegisterInfo* info_hi = GetRegInfo(reg.GetHigh()); |
| 903 | match &= info_lo->IsWide(); |
| 904 | match &= info_hi->IsWide(); |
| 905 | match &= (info_lo->Partner() == info_hi->GetReg()); |
| 906 | match &= (info_hi->Partner() == info_lo->GetReg()); |
| 907 | } else { |
| 908 | RegisterInfo* info = GetRegInfo(reg); |
| 909 | match &= info->IsWide(); |
| 910 | match &= (info->GetReg() == info->Partner()); |
| 911 | } |
| 912 | if (match) { |
| 913 | loc.location = kLocPhysReg; |
| 914 | loc.reg = reg; |
| 915 | } else { |
| 916 | Clobber(reg); |
| 917 | FreeTemp(reg); |
| 918 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 919 | } |
| 920 | } |
| 921 | return loc; |
| 922 | } |
| 923 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 924 | /* For use in cases we don't know (or care) width */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 925 | RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 926 | if (loc.wide) |
| 927 | return UpdateLocWide(loc); |
| 928 | else |
| 929 | return UpdateLoc(loc); |
| 930 | } |
| 931 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 932 | RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 933 | DCHECK(loc.wide); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 934 | |
| 935 | loc = UpdateLocWide(loc); |
| 936 | |
| 937 | /* If already in registers, we can assume proper form. Right reg class? */ |
| 938 | if (loc.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 939 | if (!RegClassMatches(reg_class, loc.reg)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 940 | /* Wrong register class. Reallocate and copy */ |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 941 | RegStorage new_regs = AllocTypedTempWide(loc.fp, reg_class); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 942 | OpRegCopyWide(new_regs, loc.reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 943 | // Associate the old sreg with the new register and clobber the old register. |
| 944 | GetRegInfo(new_regs)->SetSReg(GetRegInfo(loc.reg)->SReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 945 | Clobber(loc.reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 946 | loc.reg = new_regs; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 947 | MarkWide(loc.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 948 | } |
| 949 | return loc; |
| 950 | } |
| 951 | |
| 952 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 953 | DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); |
| 954 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 955 | loc.reg = AllocTypedTempWide(loc.fp, reg_class); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 956 | MarkWide(loc.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 957 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 958 | if (update) { |
| 959 | loc.location = kLocPhysReg; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 960 | MarkLive(loc); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 961 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 962 | return loc; |
| 963 | } |
| 964 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 965 | RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 966 | if (loc.wide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 967 | return EvalLocWide(loc, reg_class, update); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 968 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 969 | |
| 970 | loc = UpdateLoc(loc); |
| 971 | |
| 972 | if (loc.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 973 | if (!RegClassMatches(reg_class, loc.reg)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 974 | /* Wrong register class. Realloc, copy and transfer ownership */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 975 | RegStorage new_reg = AllocTypedTemp(loc.fp, reg_class); |
| 976 | OpRegCopy(new_reg, loc.reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 977 | // Associate the old sreg with the new register and clobber the old register. |
| 978 | GetRegInfo(new_reg)->SetSReg(GetRegInfo(loc.reg)->SReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 979 | Clobber(loc.reg); |
| 980 | loc.reg = new_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 981 | } |
| 982 | return loc; |
| 983 | } |
| 984 | |
| 985 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 986 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 987 | loc.reg = AllocTypedTemp(loc.fp, reg_class); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 988 | |
| 989 | if (update) { |
| 990 | loc.location = kLocPhysReg; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 991 | MarkLive(loc); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 992 | } |
| 993 | return loc; |
| 994 | } |
| 995 | |
| 996 | /* USE SSA names to count references of base Dalvik v_regs. */ |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 997 | void Mir2Lir::CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 998 | for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { |
| 999 | RegLocation loc = mir_graph_->reg_location_[i]; |
| 1000 | RefCounts* counts = loc.fp ? fp_counts : core_counts; |
| 1001 | int p_map_idx = SRegToPMap(loc.s_reg_low); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1002 | if (loc.fp) { |
| 1003 | if (loc.wide) { |
| 1004 | // Treat doubles as a unit, using upper half of fp_counts array. |
| 1005 | counts[p_map_idx + num_regs].count += mir_graph_->GetUseCount(i); |
| 1006 | i++; |
| 1007 | } else { |
| 1008 | counts[p_map_idx].count += mir_graph_->GetUseCount(i); |
| 1009 | } |
| 1010 | } else if (!IsInexpensiveConstant(loc)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1011 | counts[p_map_idx].count += mir_graph_->GetUseCount(i); |
| 1012 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | /* qsort callback function, sort descending */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1017 | static int SortCounts(const void *val1, const void *val2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1018 | const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1); |
| 1019 | const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2); |
Brian Carlstrom | 4b8c13e | 2013-08-23 18:10:32 -0700 | [diff] [blame] | 1020 | // Note that we fall back to sorting on reg so we get stable output |
| 1021 | // on differing qsort implementations (such as on host and target or |
| 1022 | // between local host and build servers). |
| 1023 | return (op1->count == op2->count) |
| 1024 | ? (op1->s_reg - op2->s_reg) |
| 1025 | : (op1->count < op2->count ? 1 : -1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1026 | } |
| 1027 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1028 | void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1029 | LOG(INFO) << msg; |
| 1030 | for (int i = 0; i < size; i++) { |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1031 | if ((arr[i].s_reg & STARTING_DOUBLE_SREG) != 0) { |
| 1032 | LOG(INFO) << "s_reg[D" << (arr[i].s_reg & ~STARTING_DOUBLE_SREG) << "]: " << arr[i].count; |
| 1033 | } else { |
| 1034 | LOG(INFO) << "s_reg[" << arr[i].s_reg << "]: " << arr[i].count; |
| 1035 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1036 | } |
| 1037 | } |
| 1038 | |
| 1039 | /* |
| 1040 | * Note: some portions of this code required even if the kPromoteRegs |
| 1041 | * optimization is disabled. |
| 1042 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1043 | void Mir2Lir::DoPromotion() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1044 | int dalvik_regs = cu_->num_dalvik_registers; |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 1045 | int num_regs = dalvik_regs + mir_graph_->GetNumUsedCompilerTemps(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1046 | const int promotion_threshold = 1; |
buzbee | d69835d | 2014-02-03 14:40:27 -0800 | [diff] [blame] | 1047 | // Allocate the promotion map - one entry for each Dalvik vReg or compiler temp |
| 1048 | promotion_map_ = static_cast<PromotionMap*> |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 1049 | (arena_->Alloc(num_regs * sizeof(promotion_map_[0]), kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1050 | |
| 1051 | // Allow target code to add any special registers |
| 1052 | AdjustSpillMask(); |
| 1053 | |
| 1054 | /* |
| 1055 | * Simple register promotion. Just do a static count of the uses |
| 1056 | * of Dalvik registers. Note that we examine the SSA names, but |
| 1057 | * count based on original Dalvik register name. Count refs |
| 1058 | * separately based on type in order to give allocation |
| 1059 | * preference to fp doubles - which must be allocated sequential |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1060 | * physical single fp registers starting with an even-numbered |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1061 | * reg. |
| 1062 | * TUNING: replace with linear scan once we have the ability |
| 1063 | * to describe register live ranges for GC. |
| 1064 | */ |
| 1065 | RefCounts *core_regs = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 1066 | static_cast<RefCounts*>(arena_->Alloc(sizeof(RefCounts) * num_regs, |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 1067 | kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1068 | RefCounts *FpRegs = |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1069 | static_cast<RefCounts *>(arena_->Alloc(sizeof(RefCounts) * num_regs * 2, |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 1070 | kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1071 | // Set ssa names for original Dalvik registers |
| 1072 | for (int i = 0; i < dalvik_regs; i++) { |
| 1073 | core_regs[i].s_reg = FpRegs[i].s_reg = i; |
| 1074 | } |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 1075 | |
| 1076 | // Set ssa names for compiler temporaries |
| 1077 | for (unsigned int ct_idx = 0; ct_idx < mir_graph_->GetNumUsedCompilerTemps(); ct_idx++) { |
| 1078 | CompilerTemp* ct = mir_graph_->GetCompilerTemp(ct_idx); |
| 1079 | core_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
| 1080 | FpRegs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
| 1081 | FpRegs[num_regs + dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1082 | } |
| 1083 | |
| 1084 | // Duplicate in upper half to represent possible fp double starting sregs. |
| 1085 | for (int i = 0; i < num_regs; i++) { |
| 1086 | FpRegs[num_regs + i].s_reg = FpRegs[i].s_reg | STARTING_DOUBLE_SREG; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1087 | } |
| 1088 | |
| 1089 | // Sum use counts of SSA regs by original Dalvik vreg. |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1090 | CountRefs(core_regs, FpRegs, num_regs); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1091 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1092 | |
| 1093 | // Sort the count arrays |
| 1094 | qsort(core_regs, num_regs, sizeof(RefCounts), SortCounts); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1095 | qsort(FpRegs, num_regs * 2, sizeof(RefCounts), SortCounts); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1096 | |
| 1097 | if (cu_->verbose) { |
| 1098 | DumpCounts(core_regs, num_regs, "Core regs after sort"); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1099 | DumpCounts(FpRegs, num_regs * 2, "Fp regs after sort"); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1100 | } |
| 1101 | |
| 1102 | if (!(cu_->disable_opt & (1 << kPromoteRegs))) { |
| 1103 | // Promote FpRegs |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1104 | for (int i = 0; (i < (num_regs * 2)) && (FpRegs[i].count >= promotion_threshold); i++) { |
| 1105 | int p_map_idx = SRegToPMap(FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG); |
| 1106 | if ((FpRegs[i].s_reg & STARTING_DOUBLE_SREG) != 0) { |
| 1107 | if ((promotion_map_[p_map_idx].fp_location != kLocPhysReg) && |
| 1108 | (promotion_map_[p_map_idx + 1].fp_location != kLocPhysReg)) { |
| 1109 | int low_sreg = FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG; |
| 1110 | // Ignore result - if can't alloc double may still be able to alloc singles. |
| 1111 | AllocPreservedDouble(low_sreg); |
| 1112 | } |
| 1113 | } else if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1114 | RegStorage reg = AllocPreservedSingle(FpRegs[i].s_reg); |
| 1115 | if (!reg.Valid()) { |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1116 | break; // No more left. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1117 | } |
| 1118 | } |
| 1119 | } |
| 1120 | |
| 1121 | // Promote core regs |
| 1122 | for (int i = 0; (i < num_regs) && |
| 1123 | (core_regs[i].count >= promotion_threshold); i++) { |
| 1124 | int p_map_idx = SRegToPMap(core_regs[i].s_reg); |
| 1125 | if (promotion_map_[p_map_idx].core_location != |
| 1126 | kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1127 | RegStorage reg = AllocPreservedCoreReg(core_regs[i].s_reg); |
| 1128 | if (!reg.Valid()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1129 | break; // No more left |
| 1130 | } |
| 1131 | } |
| 1132 | } |
| 1133 | } |
| 1134 | |
| 1135 | // Now, update SSA names to new home locations |
| 1136 | for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { |
| 1137 | RegLocation *curr = &mir_graph_->reg_location_[i]; |
| 1138 | int p_map_idx = SRegToPMap(curr->s_reg_low); |
| 1139 | if (!curr->wide) { |
| 1140 | if (curr->fp) { |
| 1141 | if (promotion_map_[p_map_idx].fp_location == kLocPhysReg) { |
| 1142 | curr->location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1143 | curr->reg = RegStorage::Solo32(promotion_map_[p_map_idx].FpReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1144 | curr->home = true; |
| 1145 | } |
| 1146 | } else { |
| 1147 | if (promotion_map_[p_map_idx].core_location == kLocPhysReg) { |
| 1148 | curr->location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1149 | curr->reg = RegStorage::Solo32(promotion_map_[p_map_idx].core_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1150 | curr->home = true; |
| 1151 | } |
| 1152 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1153 | } else { |
| 1154 | if (curr->high_word) { |
| 1155 | continue; |
| 1156 | } |
| 1157 | if (curr->fp) { |
| 1158 | if ((promotion_map_[p_map_idx].fp_location == kLocPhysReg) && |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1159 | (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1160 | int low_reg = promotion_map_[p_map_idx].FpReg; |
| 1161 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
| 1162 | // Doubles require pair of singles starting at even reg |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1163 | // TODO: move target-specific restrictions out of here. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1164 | if (((low_reg & 0x1) == 0) && ((low_reg + 1) == high_reg)) { |
| 1165 | curr->location = kLocPhysReg; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1166 | if (cu_->instruction_set == kThumb2) { |
| 1167 | curr->reg = RegStorage::FloatSolo64(RegStorage::RegNum(low_reg) >> 1); |
| 1168 | } else { |
| 1169 | curr->reg = RegStorage(RegStorage::k64BitPair, low_reg, high_reg); |
| 1170 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1171 | curr->home = true; |
| 1172 | } |
| 1173 | } |
| 1174 | } else { |
| 1175 | if ((promotion_map_[p_map_idx].core_location == kLocPhysReg) |
| 1176 | && (promotion_map_[p_map_idx+1].core_location == |
| 1177 | kLocPhysReg)) { |
| 1178 | curr->location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1179 | curr->reg = RegStorage(RegStorage::k64BitPair, promotion_map_[p_map_idx].core_reg, |
| 1180 | promotion_map_[p_map_idx+1].core_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1181 | curr->home = true; |
| 1182 | } |
| 1183 | } |
| 1184 | } |
| 1185 | } |
| 1186 | if (cu_->verbose) { |
| 1187 | DumpPromotionMap(); |
| 1188 | } |
| 1189 | } |
| 1190 | |
| 1191 | /* Returns sp-relative offset in bytes for a VReg */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1192 | int Mir2Lir::VRegOffset(int v_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1193 | return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_, |
Nicolas Geoffray | 42fcd98 | 2014-04-22 11:03:52 +0000 | [diff] [blame] | 1194 | fp_spill_mask_, frame_size_, v_reg, |
| 1195 | cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1196 | } |
| 1197 | |
| 1198 | /* Returns sp-relative offset in bytes for a SReg */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1199 | int Mir2Lir::SRegOffset(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1200 | return VRegOffset(mir_graph_->SRegToVReg(s_reg)); |
| 1201 | } |
| 1202 | |
| 1203 | /* Mark register usage state and return long retloc */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1204 | RegLocation Mir2Lir::GetReturnWide(bool is_double) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1205 | RegLocation gpr_res = LocCReturnWide(); |
| 1206 | RegLocation fpr_res = LocCReturnDouble(); |
| 1207 | RegLocation res = is_double ? fpr_res : gpr_res; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1208 | if (res.reg.IsPair()) { |
| 1209 | Clobber(res.reg); |
| 1210 | LockTemp(res.reg); |
| 1211 | // Does this wide value live in two registers or one vector register? |
| 1212 | if (res.reg.GetLowReg() != res.reg.GetHighReg()) { |
| 1213 | // FIXME: I think we want to mark these as wide as well. |
| 1214 | MarkWide(res.reg); |
| 1215 | } |
| 1216 | } else { |
| 1217 | Clobber(res.reg); |
| 1218 | LockTemp(res.reg); |
| 1219 | MarkWide(res.reg); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 1220 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1221 | return res; |
| 1222 | } |
| 1223 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1224 | RegLocation Mir2Lir::GetReturn(bool is_float) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1225 | RegLocation gpr_res = LocCReturn(); |
| 1226 | RegLocation fpr_res = LocCReturnFloat(); |
| 1227 | RegLocation res = is_float ? fpr_res : gpr_res; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1228 | Clobber(res.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1229 | if (cu_->instruction_set == kMips) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1230 | MarkInUse(res.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1231 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1232 | LockTemp(res.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1233 | } |
| 1234 | return res; |
| 1235 | } |
| 1236 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1237 | void Mir2Lir::SimpleRegAlloc() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1238 | DoPromotion(); |
| 1239 | |
| 1240 | if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) { |
| 1241 | LOG(INFO) << "After Promotion"; |
| 1242 | mir_graph_->DumpRegLocTable(mir_graph_->reg_location_, mir_graph_->GetNumSSARegs()); |
| 1243 | } |
| 1244 | |
| 1245 | /* Set the frame size */ |
| 1246 | frame_size_ = ComputeFrameSize(); |
| 1247 | } |
| 1248 | |
| 1249 | /* |
| 1250 | * Get the "real" sreg number associated with an s_reg slot. In general, |
| 1251 | * s_reg values passed through codegen are the SSA names created by |
| 1252 | * dataflow analysis and refer to slot numbers in the mir_graph_->reg_location |
| 1253 | * array. However, renaming is accomplished by simply replacing RegLocation |
| 1254 | * entries in the reglocation[] array. Therefore, when location |
| 1255 | * records for operands are first created, we need to ask the locRecord |
| 1256 | * identified by the dataflow pass what it's new name is. |
| 1257 | */ |
| 1258 | int Mir2Lir::GetSRegHi(int lowSreg) { |
| 1259 | return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1; |
| 1260 | } |
| 1261 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1262 | bool Mir2Lir::LiveOut(int s_reg) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1263 | // For now. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1264 | return true; |
| 1265 | } |
| 1266 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1267 | } // namespace art |