Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the X86 ISA */ |
| 18 | |
| 19 | #include "codegen_x86.h" |
| 20 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 21 | #include "dex/reg_storage_eq.h" |
Mingyao Yang | 98d1cc8 | 2014-05-15 17:02:16 -0700 | [diff] [blame] | 22 | #include "mirror/art_method.h" |
Ian Rogers | 7e70b00 | 2014-10-08 11:47:24 -0700 | [diff] [blame] | 23 | #include "mirror/array-inl.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 24 | #include "x86_lir.h" |
| 25 | |
| 26 | namespace art { |
| 27 | |
| 28 | /* |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | * Compare two 64-bit values |
| 30 | * x = y return 0 |
| 31 | * x < y return -1 |
| 32 | * x > y return 1 |
| 33 | */ |
| 34 | void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 35 | RegLocation rl_src2) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 36 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 37 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 38 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 39 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 40 | RegStorage temp_reg = AllocTemp(); |
Serguei Katkov | 1c55703 | 2014-06-23 13:23:38 +0700 | [diff] [blame] | 41 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
| 42 | NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0 |
| 43 | NewLIR2(kX86Set8R, temp_reg.GetReg(), kX86CondL); // temp = (src1 >= src2) ? 0 : 1 |
| 44 | NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg()); |
| 45 | NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
Serguei Katkov | 0498223 | 2014-06-20 18:17:16 +0700 | [diff] [blame] | 46 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 47 | StoreValue(rl_dest, rl_result); |
| 48 | FreeTemp(temp_reg); |
| 49 | return; |
| 50 | } |
| 51 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 52 | // Prepare for explicit register usage |
| 53 | ExplicitTempRegisterLock(this, 4, &rs_r0, &rs_r1, &rs_r2, &rs_r3); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 54 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 55 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 56 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 57 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 58 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 59 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 60 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 61 | NewLIR2(kX86Set8R, rs_r2.GetReg(), kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 |
| 62 | NewLIR2(kX86Movzx8RR, rs_r2.GetReg(), rs_r2.GetReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 63 | OpReg(kOpNeg, rs_r2); // r2 = -r2 |
| 64 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 65 | NewLIR2(kX86Set8R, rs_r0.GetReg(), kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | NewLIR2(kX86Movzx8RR, r0, r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 67 | OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 68 | RegLocation rl_result = LocCReturn(); |
| 69 | StoreValue(rl_dest, rl_result); |
| 70 | } |
| 71 | |
| 72 | X86ConditionCode X86ConditionEncoding(ConditionCode cond) { |
| 73 | switch (cond) { |
| 74 | case kCondEq: return kX86CondEq; |
| 75 | case kCondNe: return kX86CondNe; |
| 76 | case kCondCs: return kX86CondC; |
| 77 | case kCondCc: return kX86CondNc; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 78 | case kCondUlt: return kX86CondC; |
| 79 | case kCondUge: return kX86CondNc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 80 | case kCondMi: return kX86CondS; |
| 81 | case kCondPl: return kX86CondNs; |
| 82 | case kCondVs: return kX86CondO; |
| 83 | case kCondVc: return kX86CondNo; |
| 84 | case kCondHi: return kX86CondA; |
| 85 | case kCondLs: return kX86CondBe; |
| 86 | case kCondGe: return kX86CondGe; |
| 87 | case kCondLt: return kX86CondL; |
| 88 | case kCondGt: return kX86CondG; |
| 89 | case kCondLe: return kX86CondLe; |
| 90 | case kCondAl: |
| 91 | case kCondNv: LOG(FATAL) << "Should not reach here"; |
| 92 | } |
| 93 | return kX86CondO; |
| 94 | } |
| 95 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 96 | LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 97 | NewLIR2(src1.Is64Bit() ? kX86Cmp64RR : kX86Cmp32RR, src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 98 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 99 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , |
| 100 | cc); |
| 101 | branch->target = target; |
| 102 | return branch; |
| 103 | } |
| 104 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 105 | LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 106 | int check_value, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 107 | if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { |
| 108 | // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 109 | NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg.GetReg(), reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 110 | } else { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 111 | if (reg.Is64Bit()) { |
| 112 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp64RI8 : kX86Cmp64RI, reg.GetReg(), check_value); |
| 113 | } else { |
| 114 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); |
| 115 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 116 | } |
| 117 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 118 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); |
| 119 | branch->target = target; |
| 120 | return branch; |
| 121 | } |
| 122 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 123 | LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { |
| 124 | // If src or dest is a pair, we'll be using low reg. |
| 125 | if (r_dest.IsPair()) { |
| 126 | r_dest = r_dest.GetLow(); |
| 127 | } |
| 128 | if (r_src.IsPair()) { |
| 129 | r_src = r_src.GetLow(); |
| 130 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 131 | if (r_dest.IsFloat() || r_src.IsFloat()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 132 | return OpFpRegCopy(r_dest, r_src); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 133 | LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 134 | r_dest.GetReg(), r_src.GetReg()); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 135 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 136 | res->flags.is_nop = true; |
| 137 | } |
| 138 | return res; |
| 139 | } |
| 140 | |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 141 | void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { |
| 142 | if (r_dest != r_src) { |
| 143 | LIR *res = OpRegCopyNoInsert(r_dest, r_src); |
| 144 | AppendLIR(res); |
| 145 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 146 | } |
| 147 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 148 | void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 149 | if (r_dest != r_src) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 150 | bool dest_fp = r_dest.IsFloat(); |
| 151 | bool src_fp = r_src.IsFloat(); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 152 | if (dest_fp) { |
| 153 | if (src_fp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 154 | OpRegCopy(r_dest, r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 155 | } else { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 156 | // TODO: Prevent this from happening in the code. The result is often |
| 157 | // unused or could have been loaded more easily from memory. |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 158 | if (!r_src.IsPair()) { |
| 159 | DCHECK(!r_dest.IsPair()); |
| 160 | NewLIR2(kX86MovqxrRR, r_dest.GetReg(), r_src.GetReg()); |
| 161 | } else { |
| 162 | NewLIR2(kX86MovdxrRR, r_dest.GetReg(), r_src.GetLowReg()); |
| 163 | RegStorage r_tmp = AllocTempDouble(); |
| 164 | NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), r_src.GetHighReg()); |
| 165 | NewLIR2(kX86PunpckldqRR, r_dest.GetReg(), r_tmp.GetReg()); |
| 166 | FreeTemp(r_tmp); |
| 167 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 168 | } |
| 169 | } else { |
| 170 | if (src_fp) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 171 | if (!r_dest.IsPair()) { |
| 172 | DCHECK(!r_src.IsPair()); |
| 173 | NewLIR2(kX86MovqrxRR, r_dest.GetReg(), r_src.GetReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 174 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 175 | NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetReg()); |
| 176 | RegStorage temp_reg = AllocTempDouble(); |
| 177 | NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); |
| 178 | NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); |
| 179 | NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); |
| 180 | } |
| 181 | } else { |
| 182 | DCHECK_EQ(r_dest.IsPair(), r_src.IsPair()); |
| 183 | if (!r_src.IsPair()) { |
| 184 | // Just copy the register directly. |
| 185 | OpRegCopy(r_dest, r_src); |
| 186 | } else { |
| 187 | // Handle overlap |
| 188 | if (r_src.GetHighReg() == r_dest.GetLowReg() && |
| 189 | r_src.GetLowReg() == r_dest.GetHighReg()) { |
| 190 | // Deal with cycles. |
| 191 | RegStorage temp_reg = AllocTemp(); |
| 192 | OpRegCopy(temp_reg, r_dest.GetHigh()); |
| 193 | OpRegCopy(r_dest.GetHigh(), r_dest.GetLow()); |
| 194 | OpRegCopy(r_dest.GetLow(), temp_reg); |
| 195 | FreeTemp(temp_reg); |
| 196 | } else if (r_src.GetHighReg() == r_dest.GetLowReg()) { |
| 197 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 198 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 199 | } else { |
| 200 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 201 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 202 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 203 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 204 | } |
| 205 | } |
| 206 | } |
| 207 | } |
| 208 | |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 209 | void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 210 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
| 211 | int dest_reg_class) { |
Serguei Katkov | 9ee4519 | 2014-07-17 14:39:03 +0700 | [diff] [blame] | 212 | DCHECK(!left_op.IsPair() && !right_op.IsPair() && !rs_dest.IsPair()); |
| 213 | DCHECK(!left_op.IsFloat() && !right_op.IsFloat() && !rs_dest.IsFloat()); |
| 214 | |
| 215 | // We really need this check for correctness, otherwise we will need to do more checks in |
| 216 | // non zero/one case |
| 217 | if (true_val == false_val) { |
| 218 | LoadConstantNoClobber(rs_dest, true_val); |
| 219 | return; |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 220 | } |
| 221 | |
Serguei Katkov | 9ee4519 | 2014-07-17 14:39:03 +0700 | [diff] [blame] | 222 | const bool dest_intersect = IsSameReg(rs_dest, left_op) || IsSameReg(rs_dest, right_op); |
| 223 | |
| 224 | const bool zero_one_case = (true_val == 0 && false_val == 1) || (true_val == 1 && false_val == 0); |
| 225 | if (zero_one_case && IsByteRegister(rs_dest)) { |
| 226 | if (!dest_intersect) { |
| 227 | LoadConstantNoClobber(rs_dest, 0); |
| 228 | } |
| 229 | OpRegReg(kOpCmp, left_op, right_op); |
| 230 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
| 231 | NewLIR2(kX86Set8R, rs_dest.GetReg(), |
| 232 | X86ConditionEncoding(true_val == 1 ? code : FlipComparisonOrder(code))); |
| 233 | if (dest_intersect) { |
| 234 | NewLIR2(rs_dest.Is64Bit() ? kX86Movzx8qRR : kX86Movzx8RR, rs_dest.GetReg(), rs_dest.GetReg()); |
| 235 | } |
| 236 | } else { |
| 237 | // Be careful rs_dest can be changed only after cmp because it can be the same as one of ops |
| 238 | // and it cannot use xor because it makes cc flags to be dirty |
| 239 | RegStorage temp_reg = AllocTypedTemp(false, dest_reg_class, false); |
| 240 | if (temp_reg.Valid()) { |
| 241 | if (false_val == 0 && dest_intersect) { |
| 242 | code = FlipComparisonOrder(code); |
| 243 | std::swap(true_val, false_val); |
| 244 | } |
| 245 | if (!dest_intersect) { |
| 246 | LoadConstantNoClobber(rs_dest, false_val); |
| 247 | } |
| 248 | LoadConstantNoClobber(temp_reg, true_val); |
| 249 | OpRegReg(kOpCmp, left_op, right_op); |
| 250 | if (dest_intersect) { |
| 251 | LoadConstantNoClobber(rs_dest, false_val); |
| 252 | DCHECK(!last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
| 253 | } |
| 254 | OpCondRegReg(kOpCmov, code, rs_dest, temp_reg); |
| 255 | FreeTemp(temp_reg); |
| 256 | } else { |
| 257 | // slow path |
| 258 | LIR* cmp_branch = OpCmpBranch(code, left_op, right_op, nullptr); |
| 259 | LoadConstantNoClobber(rs_dest, false_val); |
| 260 | LIR* that_is_it = NewLIR1(kX86Jmp8, 0); |
| 261 | LIR* true_case = NewLIR0(kPseudoTargetLabel); |
| 262 | cmp_branch->target = true_case; |
| 263 | LoadConstantNoClobber(rs_dest, true_val); |
| 264 | LIR* end = NewLIR0(kPseudoTargetLabel); |
| 265 | that_is_it->target = end; |
| 266 | } |
| 267 | } |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 268 | } |
| 269 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 270 | void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 271 | RegLocation rl_result; |
| 272 | RegLocation rl_src = mir_graph_->GetSrc(mir, 0); |
| 273 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 274 | // Avoid using float regs here. |
| 275 | RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; |
| 276 | RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 277 | ConditionCode ccode = mir->meta.ccode; |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 278 | |
| 279 | // The kMirOpSelect has two variants, one for constants and one for moves. |
| 280 | const bool is_constant_case = (mir->ssa_rep->num_uses == 1); |
| 281 | |
| 282 | if (is_constant_case) { |
| 283 | int true_val = mir->dalvikInsn.vB; |
| 284 | int false_val = mir->dalvikInsn.vC; |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 285 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 286 | // simplest strange case |
| 287 | if (true_val == false_val) { |
| 288 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
| 289 | LoadConstantNoClobber(rl_result.reg, true_val); |
| 290 | } else { |
| 291 | // TODO: use GenSelectConst32 and handle additional opcode patterns such as |
| 292 | // "cmp; setcc; movzx" or "cmp; sbb r0,r0; and r0,$mask; add r0,$literal". |
| 293 | rl_src = LoadValue(rl_src, src_reg_class); |
| 294 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
| 295 | /* |
| 296 | * For ccode == kCondEq: |
| 297 | * |
| 298 | * 1) When the true case is zero and result_reg is not same as src_reg: |
| 299 | * xor result_reg, result_reg |
| 300 | * cmp $0, src_reg |
| 301 | * mov t1, $false_case |
| 302 | * cmovnz result_reg, t1 |
| 303 | * 2) When the false case is zero and result_reg is not same as src_reg: |
| 304 | * xor result_reg, result_reg |
| 305 | * cmp $0, src_reg |
| 306 | * mov t1, $true_case |
| 307 | * cmovz result_reg, t1 |
| 308 | * 3) All other cases (we do compare first to set eflags): |
| 309 | * cmp $0, src_reg |
| 310 | * mov result_reg, $false_case |
| 311 | * mov t1, $true_case |
| 312 | * cmovz result_reg, t1 |
| 313 | */ |
| 314 | // FIXME: depending on how you use registers you could get a false != mismatch when dealing |
| 315 | // with different views of the same underlying physical resource (i.e. solo32 vs. solo64). |
| 316 | const bool result_reg_same_as_src = |
| 317 | (rl_src.location == kLocPhysReg && rl_src.reg.GetRegNum() == rl_result.reg.GetRegNum()); |
| 318 | const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src); |
| 319 | const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src); |
| 320 | const bool catch_all_case = !(true_zero_case || false_zero_case); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 321 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 322 | if (true_zero_case || false_zero_case) { |
| 323 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
| 324 | } |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 325 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 326 | if (true_zero_case || false_zero_case || catch_all_case) { |
| 327 | OpRegImm(kOpCmp, rl_src.reg, 0); |
| 328 | } |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 329 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 330 | if (catch_all_case) { |
| 331 | OpRegImm(kOpMov, rl_result.reg, false_val); |
| 332 | } |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 333 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 334 | if (true_zero_case || false_zero_case || catch_all_case) { |
| 335 | ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; |
| 336 | int immediateForTemp = true_zero_case ? false_val : true_val; |
| 337 | RegStorage temp1_reg = AllocTypedTemp(false, result_reg_class); |
| 338 | OpRegImm(kOpMov, temp1_reg, immediateForTemp); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 339 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 340 | OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 341 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 342 | FreeTemp(temp1_reg); |
| 343 | } |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 344 | } |
| 345 | } else { |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 346 | rl_src = LoadValue(rl_src, src_reg_class); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 347 | RegLocation rl_true = mir_graph_->GetSrc(mir, 1); |
| 348 | RegLocation rl_false = mir_graph_->GetSrc(mir, 2); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 349 | rl_true = LoadValue(rl_true, result_reg_class); |
| 350 | rl_false = LoadValue(rl_false, result_reg_class); |
| 351 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 352 | |
| 353 | /* |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 354 | * For ccode == kCondEq: |
| 355 | * |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 356 | * 1) When true case is already in place: |
| 357 | * cmp $0, src_reg |
| 358 | * cmovnz result_reg, false_reg |
| 359 | * 2) When false case is already in place: |
| 360 | * cmp $0, src_reg |
| 361 | * cmovz result_reg, true_reg |
| 362 | * 3) When neither cases are in place: |
| 363 | * cmp $0, src_reg |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 364 | * mov result_reg, false_reg |
| 365 | * cmovz result_reg, true_reg |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 366 | */ |
| 367 | |
| 368 | // kMirOpSelect is generated just for conditional cases when comparison is done with zero. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 369 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 370 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 371 | if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 372 | OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 373 | } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 374 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 375 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 376 | OpRegCopy(rl_result.reg, rl_false.reg); |
| 377 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 378 | } |
| 379 | } |
| 380 | |
| 381 | StoreValue(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 382 | } |
| 383 | |
| 384 | void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 385 | LIR* taken = &block_label_list_[bb->taken]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 386 | RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); |
| 387 | RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); |
Vladimir Marko | a894607 | 2014-01-22 10:30:44 +0000 | [diff] [blame] | 388 | ConditionCode ccode = mir->meta.ccode; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 389 | |
| 390 | if (rl_src1.is_const) { |
| 391 | std::swap(rl_src1, rl_src2); |
| 392 | ccode = FlipComparisonOrder(ccode); |
| 393 | } |
| 394 | if (rl_src2.is_const) { |
| 395 | // Do special compare/branch against simple const operand |
| 396 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 397 | GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); |
| 398 | return; |
| 399 | } |
| 400 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 401 | if (cu_->target64) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 402 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 403 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 404 | |
| 405 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
| 406 | OpCondBranch(ccode, taken); |
| 407 | return; |
| 408 | } |
| 409 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 410 | // Prepare for explicit register usage |
| 411 | ExplicitTempRegisterLock(this, 4, &rs_r0, &rs_r1, &rs_r2, &rs_r3); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 412 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 413 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 414 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 415 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 416 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 417 | // Swap operands and condition code to prevent use of zero flag. |
| 418 | if (ccode == kCondLe || ccode == kCondGt) { |
| 419 | // Compute (r3:r2) = (r3:r2) - (r1:r0) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 420 | OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0 |
| 421 | OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 422 | } else { |
| 423 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 424 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 425 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 426 | } |
| 427 | switch (ccode) { |
| 428 | case kCondEq: |
| 429 | case kCondNe: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 430 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 431 | break; |
| 432 | case kCondLe: |
| 433 | ccode = kCondGe; |
| 434 | break; |
| 435 | case kCondGt: |
| 436 | ccode = kCondLt; |
| 437 | break; |
| 438 | case kCondLt: |
| 439 | case kCondGe: |
| 440 | break; |
| 441 | default: |
| 442 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 443 | } |
| 444 | OpCondBranch(ccode, taken); |
| 445 | } |
| 446 | |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 447 | void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 448 | int64_t val, ConditionCode ccode) { |
| 449 | int32_t val_lo = Low32Bits(val); |
| 450 | int32_t val_hi = High32Bits(val); |
| 451 | LIR* taken = &block_label_list_[bb->taken]; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 452 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 453 | bool is_equality_test = ccode == kCondEq || ccode == kCondNe; |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 454 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 455 | if (cu_->target64) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 456 | if (is_equality_test && val == 0) { |
| 457 | // We can simplify of comparing for ==, != to 0. |
| 458 | NewLIR2(kX86Test64RR, rl_src1.reg.GetReg(), rl_src1.reg.GetReg()); |
| 459 | } else if (is_equality_test && val_hi == 0 && val_lo > 0) { |
| 460 | OpRegImm(kOpCmp, rl_src1.reg, val_lo); |
| 461 | } else { |
| 462 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 463 | LoadConstantWide(tmp, val); |
| 464 | OpRegReg(kOpCmp, rl_src1.reg, tmp); |
| 465 | FreeTemp(tmp); |
| 466 | } |
| 467 | OpCondBranch(ccode, taken); |
| 468 | return; |
| 469 | } |
| 470 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 471 | if (is_equality_test && val != 0) { |
| 472 | rl_src1 = ForceTempWide(rl_src1); |
| 473 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 474 | RegStorage low_reg = rl_src1.reg.GetLow(); |
| 475 | RegStorage high_reg = rl_src1.reg.GetHigh(); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 476 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 477 | if (is_equality_test) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 478 | // We can simplify of comparing for ==, != to 0. |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 479 | if (val == 0) { |
| 480 | if (IsTemp(low_reg)) { |
| 481 | OpRegReg(kOpOr, low_reg, high_reg); |
| 482 | // We have now changed it; ignore the old values. |
| 483 | Clobber(rl_src1.reg); |
| 484 | } else { |
| 485 | RegStorage t_reg = AllocTemp(); |
| 486 | OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); |
| 487 | FreeTemp(t_reg); |
| 488 | } |
| 489 | OpCondBranch(ccode, taken); |
| 490 | return; |
| 491 | } |
| 492 | |
| 493 | // Need to compute the actual value for ==, !=. |
| 494 | OpRegImm(kOpSub, low_reg, val_lo); |
| 495 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 496 | OpRegReg(kOpOr, high_reg, low_reg); |
| 497 | Clobber(rl_src1.reg); |
| 498 | } else if (ccode == kCondLe || ccode == kCondGt) { |
| 499 | // Swap operands and condition code to prevent use of zero flag. |
| 500 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 501 | LoadConstantWide(tmp, val); |
| 502 | OpRegReg(kOpSub, tmp.GetLow(), low_reg); |
| 503 | OpRegReg(kOpSbc, tmp.GetHigh(), high_reg); |
| 504 | ccode = (ccode == kCondLe) ? kCondGe : kCondLt; |
| 505 | FreeTemp(tmp); |
| 506 | } else { |
| 507 | // We can use a compare for the low word to set CF. |
| 508 | OpRegImm(kOpCmp, low_reg, val_lo); |
| 509 | if (IsTemp(high_reg)) { |
| 510 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 511 | // We have now changed it; ignore the old values. |
| 512 | Clobber(rl_src1.reg); |
| 513 | } else { |
| 514 | // mov temp_reg, high_reg; sbb temp_reg, high_constant |
| 515 | RegStorage t_reg = AllocTemp(); |
| 516 | OpRegCopy(t_reg, high_reg); |
| 517 | NewLIR2(kX86Sbb32RI, t_reg.GetReg(), val_hi); |
| 518 | FreeTemp(t_reg); |
| 519 | } |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 520 | } |
| 521 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 522 | OpCondBranch(ccode, taken); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 523 | } |
| 524 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 525 | void X86Mir2Lir::CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 526 | // It does not make sense to calculate magic and shift for zero divisor. |
| 527 | DCHECK_NE(divisor, 0); |
| 528 | |
| 529 | /* According to H.S.Warren's Hacker's Delight Chapter 10 and |
| 530 | * T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 531 | * The magic number M and shift S can be calculated in the following way: |
| 532 | * Let nc be the most positive value of numerator(n) such that nc = kd - 1, |
| 533 | * where divisor(d) >=2. |
| 534 | * Let nc be the most negative value of numerator(n) such that nc = kd + 1, |
| 535 | * where divisor(d) <= -2. |
| 536 | * Thus nc can be calculated like: |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 537 | * nc = exp + exp % d - 1, where d >= 2 and exp = 2^31 for int or 2^63 for long |
| 538 | * nc = -exp + (exp + 1) % d, where d >= 2 and exp = 2^31 for int or 2^63 for long |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 539 | * |
| 540 | * So the shift p is the smallest p satisfying |
| 541 | * 2^p > nc * (d - 2^p % d), where d >= 2 |
| 542 | * 2^p > nc * (d + 2^p % d), where d <= -2. |
| 543 | * |
| 544 | * the magic number M is calcuated by |
| 545 | * M = (2^p + d - 2^p % d) / d, where d >= 2 |
| 546 | * M = (2^p - d - 2^p % d) / d, where d <= -2. |
| 547 | * |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 548 | * Notice that p is always bigger than or equal to 32/64, so we just return 32-p/64-p as |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 549 | * the shift number S. |
| 550 | */ |
| 551 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 552 | int64_t p = (is_long) ? 63 : 31; |
| 553 | const uint64_t exp = (is_long) ? 0x8000000000000000ULL : 0x80000000U; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 554 | |
| 555 | // Initialize the computations. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 556 | uint64_t abs_d = (divisor >= 0) ? divisor : -divisor; |
| 557 | uint64_t tmp = exp + ((is_long) ? static_cast<uint64_t>(divisor) >> 63 : |
| 558 | static_cast<uint32_t>(divisor) >> 31); |
| 559 | uint64_t abs_nc = tmp - 1 - tmp % abs_d; |
| 560 | uint64_t quotient1 = exp / abs_nc; |
| 561 | uint64_t remainder1 = exp % abs_nc; |
| 562 | uint64_t quotient2 = exp / abs_d; |
| 563 | uint64_t remainder2 = exp % abs_d; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 564 | |
| 565 | /* |
| 566 | * To avoid handling both positive and negative divisor, Hacker's Delight |
| 567 | * introduces a method to handle these 2 cases together to avoid duplication. |
| 568 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 569 | uint64_t delta; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 570 | do { |
| 571 | p++; |
| 572 | quotient1 = 2 * quotient1; |
| 573 | remainder1 = 2 * remainder1; |
| 574 | if (remainder1 >= abs_nc) { |
| 575 | quotient1++; |
| 576 | remainder1 = remainder1 - abs_nc; |
| 577 | } |
| 578 | quotient2 = 2 * quotient2; |
| 579 | remainder2 = 2 * remainder2; |
| 580 | if (remainder2 >= abs_d) { |
| 581 | quotient2++; |
| 582 | remainder2 = remainder2 - abs_d; |
| 583 | } |
| 584 | delta = abs_d - remainder2; |
| 585 | } while (quotient1 < delta || (quotient1 == delta && remainder1 == 0)); |
| 586 | |
| 587 | magic = (divisor > 0) ? (quotient2 + 1) : (-quotient2 - 1); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 588 | |
| 589 | if (!is_long) { |
| 590 | magic = static_cast<int>(magic); |
| 591 | } |
| 592 | |
| 593 | shift = (is_long) ? p - 64 : p - 32; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 594 | } |
| 595 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 596 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 597 | LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; |
| 598 | return rl_dest; |
| 599 | } |
| 600 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 601 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, |
| 602 | int imm, bool is_div) { |
| 603 | // Use a multiply (and fixup) to perform an int div/rem by a constant. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 604 | RegLocation rl_result; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 605 | |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 606 | if (imm == 1) { |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 607 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 608 | if (is_div) { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 609 | // x / 1 == x. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 610 | LoadValueDirectFixed(rl_src, rl_result.reg); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 611 | } else { |
| 612 | // x % 1 == 0. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 613 | LoadConstantNoClobber(rl_result.reg, 0); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 614 | } |
| 615 | } else if (imm == -1) { // handle 0x80000000 / -1 special case. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 616 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 617 | if (is_div) { |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 618 | LoadValueDirectFixed(rl_src, rl_result.reg); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 619 | |
| 620 | // Check if numerator is 0 |
| 621 | OpRegImm(kOpCmp, rl_result.reg, 0); |
| 622 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 623 | |
| 624 | // handle 0x80000000 / -1 |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 625 | OpRegImm(kOpCmp, rl_result.reg, 0x80000000); |
| 626 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 627 | |
| 628 | // for x != MIN_INT, x / -1 == -x. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 629 | NewLIR1(kX86Neg32R, rl_result.reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 630 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 631 | // EAX already contains the right value (0x80000000), |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 632 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 633 | branch->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 634 | } else { |
| 635 | // x % -1 == 0. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 636 | LoadConstantNoClobber(rl_result.reg, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 637 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 638 | } else if (is_div && IsPowerOfTwo(std::abs(imm))) { |
| 639 | // Division using shifting. |
| 640 | rl_src = LoadValue(rl_src, kCoreReg); |
| 641 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 642 | if (IsSameReg(rl_result.reg, rl_src.reg)) { |
| 643 | RegStorage rs_temp = AllocTypedTemp(false, kCoreReg); |
| 644 | rl_result.reg.SetReg(rs_temp.GetReg()); |
| 645 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 646 | |
| 647 | // Check if numerator is 0 |
| 648 | OpRegImm(kOpCmp, rl_src.reg, 0); |
| 649 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 650 | LoadConstantNoClobber(rl_result.reg, 0); |
| 651 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 652 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 653 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 654 | NewLIR3(kX86Lea32RM, rl_result.reg.GetReg(), rl_src.reg.GetReg(), std::abs(imm) - 1); |
| 655 | NewLIR2(kX86Test32RR, rl_src.reg.GetReg(), rl_src.reg.GetReg()); |
| 656 | OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg); |
| 657 | int shift_amount = LowestSetBit(imm); |
| 658 | OpRegImm(kOpAsr, rl_result.reg, shift_amount); |
| 659 | if (imm < 0) { |
| 660 | OpReg(kOpNeg, rl_result.reg); |
| 661 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 662 | done->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 663 | } else { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 664 | CHECK(imm <= -2 || imm >= 2); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 665 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 666 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 667 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 668 | int64_t magic; |
| 669 | int shift; |
| 670 | CalculateMagicAndShift((int64_t)imm, magic, shift, false /* is_long */); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 671 | |
| 672 | /* |
| 673 | * For imm >= 2, |
| 674 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 675 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 676 | * For imm <= -2, |
| 677 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 678 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 679 | * We implement this algorithm in the following way: |
| 680 | * 1. multiply magic number m and numerator n, get the higher 32bit result in EDX |
| 681 | * 2. if imm > 0 and magic < 0, add numerator to EDX |
| 682 | * if imm < 0 and magic > 0, sub numerator from EDX |
| 683 | * 3. if S !=0, SAR S bits for EDX |
| 684 | * 4. add 1 to EDX if EDX < 0 |
| 685 | * 5. Thus, EDX is the quotient |
| 686 | */ |
| 687 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 688 | FlushReg(rs_r0); |
| 689 | Clobber(rs_r0); |
| 690 | LockTemp(rs_r0); |
| 691 | FlushReg(rs_r2); |
| 692 | Clobber(rs_r2); |
| 693 | LockTemp(rs_r2); |
| 694 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 695 | // Assume that the result will be in EDX for divide, and EAX for remainder. |
| 696 | rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, is_div ? rs_r2 : rs_r0, |
| 697 | INVALID_SREG, INVALID_SREG}; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 698 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 699 | // We need the value at least twice. Load into a temp. |
| 700 | rl_src = LoadValue(rl_src, kCoreReg); |
| 701 | RegStorage numerator_reg = rl_src.reg; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 702 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 703 | // Check if numerator is 0. |
| 704 | OpRegImm(kOpCmp, numerator_reg, 0); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 705 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 706 | // Return result 0 if numerator was 0. |
| 707 | LoadConstantNoClobber(rl_result.reg, 0); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 708 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 709 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 710 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 711 | // EAX = magic. |
| 712 | LoadConstant(rs_r0, magic); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 713 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 714 | // EDX:EAX = magic * numerator. |
| 715 | NewLIR1(kX86Imul32DaR, numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 716 | |
| 717 | if (imm > 0 && magic < 0) { |
| 718 | // Add numerator to EDX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 719 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 720 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 721 | } else if (imm < 0 && magic > 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 722 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 723 | NewLIR2(kX86Sub32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 724 | } |
| 725 | |
| 726 | // Do we need the shift? |
| 727 | if (shift != 0) { |
| 728 | // Shift EDX by 'shift' bits. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 729 | NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 730 | } |
| 731 | |
| 732 | // Add 1 to EDX if EDX < 0. |
| 733 | |
| 734 | // Move EDX to EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 735 | OpRegCopy(rs_r0, rs_r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 736 | |
| 737 | // Move sign bit to bit 0, zeroing the rest. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 738 | NewLIR2(kX86Shr32RI, rs_r2.GetReg(), 31); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 739 | |
| 740 | // EDX = EDX + EAX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 741 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 742 | |
| 743 | // Quotient is in EDX. |
| 744 | if (!is_div) { |
| 745 | // We need to compute the remainder. |
| 746 | // Remainder is divisor - (quotient * imm). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 747 | DCHECK(numerator_reg.Valid()); |
| 748 | OpRegCopy(rs_r0, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 749 | |
| 750 | // EAX = numerator * imm. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 751 | OpRegRegImm(kOpMul, rs_r2, rs_r2, imm); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 752 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 753 | // EAX -= EDX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 754 | NewLIR2(kX86Sub32RR, rs_r0.GetReg(), rs_r2.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 755 | |
| 756 | // For this case, return the result in EAX. |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 757 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 758 | done->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | return rl_result; |
| 762 | } |
| 763 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 764 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, |
| 765 | bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 766 | LOG(FATAL) << "Unexpected use of GenDivRem for x86"; |
| 767 | return rl_dest; |
| 768 | } |
| 769 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 770 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 771 | RegLocation rl_src2, bool is_div, int flags) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 772 | // We have to use fixed registers, so flush all the temps. |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 773 | |
| 774 | // Prepare for explicit register usage. |
| 775 | ExplicitTempRegisterLock(this, 3, &rs_r0, &rs_r1, &rs_r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 776 | |
| 777 | // Load LHS into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 778 | LoadValueDirectFixed(rl_src1, rs_r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 779 | |
| 780 | // Load RHS into EBX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 781 | LoadValueDirectFixed(rl_src2, rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 782 | |
| 783 | // Copy LHS sign bit into EDX. |
| 784 | NewLIR0(kx86Cdq32Da); |
| 785 | |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 786 | if ((flags & MIR_IGNORE_DIV_ZERO_CHECK) == 0) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 787 | // Handle division by zero case. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 788 | GenDivZeroCheck(rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 789 | } |
| 790 | |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 791 | // Check if numerator is 0 |
| 792 | OpRegImm(kOpCmp, rs_r0, 0); |
| 793 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 794 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 795 | // Have to catch 0x80000000/-1 case, or we will get an exception! |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 796 | OpRegImm(kOpCmp, rs_r1, -1); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 797 | LIR* minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 798 | |
| 799 | // RHS is -1. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 800 | OpRegImm(kOpCmp, rs_r0, 0x80000000); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 801 | LIR* minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 802 | |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 803 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 804 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 805 | // In 0x80000000/-1 case. |
| 806 | if (!is_div) { |
| 807 | // For DIV, EAX is already right. For REM, we need EDX 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 808 | LoadConstantNoClobber(rs_r2, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 809 | } |
| 810 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 811 | |
| 812 | // Expected case. |
| 813 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 814 | minint_branch->target = minus_one_branch->target; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 815 | NewLIR1(kX86Idivmod32DaR, rs_r1.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 816 | done->target = NewLIR0(kPseudoTargetLabel); |
| 817 | |
| 818 | // Result is in EAX for div and EDX for rem. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 819 | RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 820 | if (!is_div) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 821 | rl_result.reg.SetReg(r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 822 | } |
| 823 | return rl_result; |
| 824 | } |
| 825 | |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 826 | bool X86Mir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 827 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 828 | |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 829 | if (is_long && !cu_->target64) { |
| 830 | /* |
| 831 | * We want to implement the following algorithm |
| 832 | * mov eax, low part of arg1 |
| 833 | * mov edx, high part of arg1 |
| 834 | * mov ebx, low part of arg2 |
| 835 | * mov ecx, high part of arg2 |
| 836 | * mov edi, eax |
| 837 | * sub edi, ebx |
| 838 | * mov edi, edx |
| 839 | * sbb edi, ecx |
| 840 | * is_min ? "cmovgel eax, ebx" : "cmovll eax, ebx" |
| 841 | * is_min ? "cmovgel edx, ecx" : "cmovll edx, ecx" |
| 842 | * |
| 843 | * The algorithm above needs 5 registers: a pair for the first operand |
| 844 | * (which later will be used as result), a pair for the second operand |
| 845 | * and a temp register (e.g. 'edi') for intermediate calculations. |
| 846 | * Ideally we have 6 GP caller-save registers in 32-bit mode. They are: |
| 847 | * 'eax', 'ebx', 'ecx', 'edx', 'esi' and 'edi'. So there should be |
| 848 | * always enough registers to operate on. Practically, there is a pair |
| 849 | * of registers 'edi' and 'esi' which holds promoted values and |
| 850 | * sometimes should be treated as 'callee save'. If one of the operands |
| 851 | * is in the promoted registers then we have enough register to |
| 852 | * operate on. Otherwise there is lack of resources and we have to |
| 853 | * save 'edi' before calculations and restore after. |
| 854 | */ |
| 855 | |
| 856 | RegLocation rl_src1 = info->args[0]; |
| 857 | RegLocation rl_src2 = info->args[2]; |
| 858 | RegLocation rl_dest = InlineTargetWide(info); |
| 859 | int res_vreg, src1_vreg, src2_vreg; |
| 860 | |
| 861 | /* |
| 862 | * If the result register is the same as the second element, then we |
| 863 | * need to be careful. The reason is that the first copy will |
| 864 | * inadvertently clobber the second element with the first one thus |
| 865 | * yielding the wrong result. Thus we do a swap in that case. |
| 866 | */ |
| 867 | res_vreg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); |
| 868 | src2_vreg = mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 869 | if (res_vreg == src2_vreg) { |
| 870 | std::swap(rl_src1, rl_src2); |
| 871 | } |
| 872 | |
| 873 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 874 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 875 | |
| 876 | // Pick the first integer as min/max. |
| 877 | OpRegCopyWide(rl_result.reg, rl_src1.reg); |
| 878 | |
| 879 | /* |
| 880 | * If the integers are both in the same register, then there is |
| 881 | * nothing else to do because they are equal and we have already |
| 882 | * moved one into the result. |
| 883 | */ |
| 884 | src1_vreg = mir_graph_->SRegToVReg(rl_src1.s_reg_low); |
| 885 | src2_vreg = mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 886 | if (src1_vreg == src2_vreg) { |
| 887 | StoreValueWide(rl_dest, rl_result); |
| 888 | return true; |
| 889 | } |
| 890 | |
| 891 | // Free registers to make some room for the second operand. |
| 892 | // But don't try to free ourselves or promoted registers. |
| 893 | if (res_vreg != src1_vreg && |
| 894 | IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { |
| 895 | FreeTemp(rl_src1.reg); |
| 896 | } |
| 897 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 898 | |
| 899 | // Do we have a free register for intermediate calculations? |
| 900 | RegStorage tmp = AllocTemp(false); |
| 901 | if (tmp == RegStorage::InvalidReg()) { |
| 902 | /* |
| 903 | * No, will use 'edi'. |
| 904 | * |
| 905 | * As mentioned above we have 4 temporary and 2 promotable |
| 906 | * caller-save registers. Therefore, we assume that a free |
| 907 | * register can be allocated only if 'esi' and 'edi' are |
| 908 | * already used as operands. If number of promotable registers |
| 909 | * increases from 2 to 4 then our assumption fails and operand |
| 910 | * data is corrupted. |
| 911 | * Let's DCHECK it. |
| 912 | */ |
| 913 | DCHECK(IsTemp(rl_src2.reg.GetLow()) && |
| 914 | IsTemp(rl_src2.reg.GetHigh()) && |
| 915 | IsTemp(rl_result.reg.GetLow()) && |
| 916 | IsTemp(rl_result.reg.GetHigh())); |
| 917 | tmp = rs_rDI; |
| 918 | NewLIR1(kX86Push32R, tmp.GetReg()); |
| 919 | } |
| 920 | |
| 921 | // Now we are ready to do calculations. |
| 922 | OpRegReg(kOpMov, tmp, rl_result.reg.GetLow()); |
| 923 | OpRegReg(kOpSub, tmp, rl_src2.reg.GetLow()); |
| 924 | OpRegReg(kOpMov, tmp, rl_result.reg.GetHigh()); |
| 925 | OpRegReg(kOpSbc, tmp, rl_src2.reg.GetHigh()); |
| 926 | |
| 927 | // Let's put pop 'edi' here to break a bit the dependency chain. |
| 928 | if (tmp == rs_rDI) { |
| 929 | NewLIR1(kX86Pop32R, tmp.GetReg()); |
| 930 | } |
| 931 | |
| 932 | // Conditionally move the other integer into the destination register. |
| 933 | ConditionCode cc = is_min ? kCondGe : kCondLt; |
| 934 | OpCondRegReg(kOpCmov, cc, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); |
| 935 | OpCondRegReg(kOpCmov, cc, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); |
| 936 | StoreValueWide(rl_dest, rl_result); |
| 937 | return true; |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 938 | } |
| 939 | |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 940 | // Get the two arguments to the invoke and place them in GP registers. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 941 | RegLocation rl_src1 = info->args[0]; |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 942 | RegLocation rl_src2 = (is_long) ? info->args[2] : info->args[1]; |
| 943 | rl_src1 = (is_long) ? LoadValueWide(rl_src1, kCoreReg) : LoadValue(rl_src1, kCoreReg); |
| 944 | rl_src2 = (is_long) ? LoadValueWide(rl_src2, kCoreReg) : LoadValue(rl_src2, kCoreReg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 945 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 946 | RegLocation rl_dest = (is_long) ? InlineTargetWide(info) : InlineTarget(info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 947 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 948 | |
| 949 | /* |
| 950 | * If the result register is the same as the second element, then we need to be careful. |
| 951 | * The reason is that the first copy will inadvertently clobber the second element with |
| 952 | * the first one thus yielding the wrong result. Thus we do a swap in that case. |
| 953 | */ |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 954 | if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 955 | std::swap(rl_src1, rl_src2); |
| 956 | } |
| 957 | |
| 958 | // Pick the first integer as min/max. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 959 | OpRegCopy(rl_result.reg, rl_src1.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 960 | |
| 961 | // If the integers are both in the same register, then there is nothing else to do |
| 962 | // because they are equal and we have already moved one into the result. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 963 | if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 964 | // It is possible we didn't pick correctly so do the actual comparison now. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 965 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 966 | |
| 967 | // Conditionally move the other integer into the destination register. |
| 968 | ConditionCode condition_code = is_min ? kCondGt : kCondLt; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 969 | OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 970 | } |
| 971 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 972 | if (is_long) { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 973 | StoreValueWide(rl_dest, rl_result); |
| 974 | } else { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 975 | StoreValue(rl_dest, rl_result); |
| 976 | } |
| 977 | return true; |
| 978 | } |
| 979 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 980 | bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 981 | RegLocation rl_src_address = info->args[0]; // long address |
| 982 | RegLocation rl_address; |
| 983 | if (!cu_->target64) { |
| 984 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[0] |
| 985 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 986 | } else { |
| 987 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 988 | } |
| 989 | RegLocation rl_dest = size == k64 ? InlineTargetWide(info) : InlineTarget(info); |
| 990 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 991 | // Unaligned access is allowed on x86. |
| 992 | LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, kNotVolatile); |
| 993 | if (size == k64) { |
| 994 | StoreValueWide(rl_dest, rl_result); |
| 995 | } else { |
| 996 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
| 997 | StoreValue(rl_dest, rl_result); |
| 998 | } |
| 999 | return true; |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1000 | } |
| 1001 | |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 1002 | bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 1003 | RegLocation rl_src_address = info->args[0]; // long address |
| 1004 | RegLocation rl_address; |
| 1005 | if (!cu_->target64) { |
| 1006 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[0] |
| 1007 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 1008 | } else { |
| 1009 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 1010 | } |
| 1011 | RegLocation rl_src_value = info->args[2]; // [size] value |
| 1012 | RegLocation rl_value; |
| 1013 | if (size == k64) { |
| 1014 | // Unaligned access is allowed on x86. |
| 1015 | rl_value = LoadValueWide(rl_src_value, kCoreReg); |
| 1016 | } else { |
| 1017 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
| 1018 | // In 32-bit mode the only EAX..EDX registers can be used with Mov8MR. |
| 1019 | if (!cu_->target64 && size == kSignedByte) { |
| 1020 | rl_src_value = UpdateLocTyped(rl_src_value, kCoreReg); |
| 1021 | if (rl_src_value.location == kLocPhysReg && !IsByteRegister(rl_src_value.reg)) { |
| 1022 | RegStorage temp = AllocateByteRegister(); |
| 1023 | OpRegCopy(temp, rl_src_value.reg); |
| 1024 | rl_value.reg = temp; |
| 1025 | } else { |
| 1026 | rl_value = LoadValue(rl_src_value, kCoreReg); |
| 1027 | } |
| 1028 | } else { |
| 1029 | rl_value = LoadValue(rl_src_value, kCoreReg); |
| 1030 | } |
| 1031 | } |
| 1032 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile); |
| 1033 | return true; |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 1034 | } |
| 1035 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1036 | void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { |
| 1037 | NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1038 | } |
| 1039 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1040 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1041 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 1042 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
| 1043 | } |
| 1044 | |
| 1045 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { |
| 1046 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 1047 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1048 | } |
| 1049 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1050 | static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) { |
| 1051 | return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 1052 | } |
| 1053 | |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 1054 | bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 1055 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1056 | // Unused - RegLocation rl_src_unsafe = info->args[0]; |
| 1057 | RegLocation rl_src_obj = info->args[1]; // Object - known non-null |
| 1058 | RegLocation rl_src_offset = info->args[2]; // long low |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1059 | if (!cu_->target64) { |
| 1060 | rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] |
| 1061 | } |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1062 | RegLocation rl_src_expected = info->args[4]; // int, long or Object |
| 1063 | // If is_long, high half is in info->args[5] |
| 1064 | RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object |
| 1065 | // If is_long, high half is in info->args[7] |
| 1066 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1067 | if (is_long && cu_->target64) { |
| 1068 | // RAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in RAX. |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1069 | FlushReg(rs_r0q); |
| 1070 | Clobber(rs_r0q); |
| 1071 | LockTemp(rs_r0q); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1072 | |
| 1073 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
| 1074 | RegLocation rl_new_value = LoadValueWide(rl_src_new_value, kCoreReg); |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1075 | RegLocation rl_offset = LoadValueWide(rl_src_offset, kCoreReg); |
| 1076 | LoadValueDirectWide(rl_src_expected, rs_r0q); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1077 | NewLIR5(kX86LockCmpxchg64AR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, |
| 1078 | rl_new_value.reg.GetReg()); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1079 | |
| 1080 | // After a store we need to insert barrier in case of potential load. Since the |
| 1081 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1082 | GenMemBarrier(kAnyAny); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1083 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1084 | FreeTemp(rs_r0q); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1085 | } else if (is_long) { |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 1086 | // TODO: avoid unnecessary loads of SI and DI when the values are in registers. |
| 1087 | // TODO: CFI support. |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 1088 | FlushAllRegs(); |
| 1089 | LockCallTemps(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1090 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 1091 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_rBX, rs_rCX); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1092 | LoadValueDirectWideFixed(rl_src_expected, r_tmp1); |
| 1093 | LoadValueDirectWideFixed(rl_src_new_value, r_tmp2); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1094 | // FIXME: needs 64-bit update. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1095 | const bool obj_in_di = IsInReg(this, rl_src_obj, rs_rDI); |
| 1096 | const bool obj_in_si = IsInReg(this, rl_src_obj, rs_rSI); |
| 1097 | DCHECK(!obj_in_si || !obj_in_di); |
| 1098 | const bool off_in_di = IsInReg(this, rl_src_offset, rs_rDI); |
| 1099 | const bool off_in_si = IsInReg(this, rl_src_offset, rs_rSI); |
| 1100 | DCHECK(!off_in_si || !off_in_di); |
| 1101 | // If obj/offset is in a reg, use that reg. Otherwise, use the empty reg. |
| 1102 | RegStorage rs_obj = obj_in_di ? rs_rDI : obj_in_si ? rs_rSI : !off_in_di ? rs_rDI : rs_rSI; |
| 1103 | RegStorage rs_off = off_in_si ? rs_rSI : off_in_di ? rs_rDI : !obj_in_si ? rs_rSI : rs_rDI; |
| 1104 | bool push_di = (!obj_in_di && !off_in_di) && (rs_obj == rs_rDI || rs_off == rs_rDI); |
| 1105 | bool push_si = (!obj_in_si && !off_in_si) && (rs_obj == rs_rSI || rs_off == rs_rSI); |
| 1106 | if (push_di) { |
| 1107 | NewLIR1(kX86Push32R, rs_rDI.GetReg()); |
| 1108 | MarkTemp(rs_rDI); |
| 1109 | LockTemp(rs_rDI); |
| 1110 | } |
| 1111 | if (push_si) { |
| 1112 | NewLIR1(kX86Push32R, rs_rSI.GetReg()); |
| 1113 | MarkTemp(rs_rSI); |
| 1114 | LockTemp(rs_rSI); |
| 1115 | } |
| 1116 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1117 | const size_t push_offset = (push_si ? 4u : 0u) + (push_di ? 4u : 0u); |
| 1118 | if (!obj_in_si && !obj_in_di) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1119 | LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_obj.s_reg_low) + push_offset, rs_obj); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1120 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1121 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1122 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; |
| 1123 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
| 1124 | } |
| 1125 | if (!off_in_si && !off_in_di) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1126 | LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1127 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1128 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1129 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; |
| 1130 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
| 1131 | } |
| 1132 | NewLIR4(kX86LockCmpxchg64A, rs_obj.GetReg(), rs_off.GetReg(), 0, 0); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1133 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1134 | // After a store we need to insert barrier to prevent reordering with either |
| 1135 | // earlier or later memory accesses. Since |
| 1136 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated, |
| 1137 | // and it will be associated with the cmpxchg instruction, preventing both. |
| 1138 | GenMemBarrier(kAnyAny); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1139 | |
| 1140 | if (push_si) { |
| 1141 | FreeTemp(rs_rSI); |
| 1142 | UnmarkTemp(rs_rSI); |
| 1143 | NewLIR1(kX86Pop32R, rs_rSI.GetReg()); |
| 1144 | } |
| 1145 | if (push_di) { |
| 1146 | FreeTemp(rs_rDI); |
| 1147 | UnmarkTemp(rs_rDI); |
| 1148 | NewLIR1(kX86Pop32R, rs_rDI.GetReg()); |
| 1149 | } |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 1150 | FreeCallTemps(); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1151 | } else { |
| 1152 | // EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1153 | FlushReg(rs_r0); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1154 | Clobber(rs_r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1155 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1156 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1157 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
buzbee | 7c02e91 | 2014-10-03 13:14:17 -0700 | [diff] [blame] | 1158 | RegLocation rl_new_value = LoadValue(rl_src_new_value, LocToRegClass(rl_src_new_value)); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1159 | |
| 1160 | if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { |
| 1161 | // Mark card for object assuming new value is stored. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1162 | FreeTemp(rs_r0); // Temporarily release EAX for MarkGCCard(). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1163 | MarkGCCard(rl_new_value.reg, rl_object.reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1164 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1165 | } |
| 1166 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1167 | RegLocation rl_offset; |
| 1168 | if (cu_->target64) { |
| 1169 | rl_offset = LoadValueWide(rl_src_offset, kCoreReg); |
| 1170 | } else { |
| 1171 | rl_offset = LoadValue(rl_src_offset, kCoreReg); |
| 1172 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1173 | LoadValueDirect(rl_src_expected, rs_r0); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1174 | NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, |
| 1175 | rl_new_value.reg.GetReg()); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1176 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1177 | // After a store we need to insert barrier to prevent reordering with either |
| 1178 | // earlier or later memory accesses. Since |
| 1179 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated, |
| 1180 | // and it will be associated with the cmpxchg instruction, preventing both. |
| 1181 | GenMemBarrier(kAnyAny); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1182 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1183 | FreeTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1184 | } |
| 1185 | |
| 1186 | // Convert ZF to boolean |
| 1187 | RegLocation rl_dest = InlineTarget(info); // boolean place for result |
| 1188 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1189 | RegStorage result_reg = rl_result.reg; |
| 1190 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1191 | // For 32-bit, SETcc only works with EAX..EDX. |
| 1192 | if (!IsByteRegister(result_reg)) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1193 | result_reg = AllocateByteRegister(); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1194 | } |
| 1195 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondZ); |
| 1196 | NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), result_reg.GetReg()); |
| 1197 | if (IsTemp(result_reg)) { |
| 1198 | FreeTemp(result_reg); |
| 1199 | } |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1200 | StoreValue(rl_dest, rl_result); |
| 1201 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1202 | } |
| 1203 | |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 1204 | void X86Mir2Lir::SwapBits(RegStorage result_reg, int shift, int32_t value) { |
| 1205 | RegStorage r_temp = AllocTemp(); |
| 1206 | OpRegCopy(r_temp, result_reg); |
| 1207 | OpRegImm(kOpLsr, result_reg, shift); |
| 1208 | OpRegImm(kOpAnd, r_temp, value); |
| 1209 | OpRegImm(kOpAnd, result_reg, value); |
| 1210 | OpRegImm(kOpLsl, r_temp, shift); |
| 1211 | OpRegReg(kOpOr, result_reg, r_temp); |
| 1212 | FreeTemp(r_temp); |
| 1213 | } |
| 1214 | |
| 1215 | void X86Mir2Lir::SwapBits64(RegStorage result_reg, int shift, int64_t value) { |
| 1216 | RegStorage r_temp = AllocTempWide(); |
| 1217 | OpRegCopy(r_temp, result_reg); |
| 1218 | OpRegImm(kOpLsr, result_reg, shift); |
| 1219 | RegStorage r_value = AllocTempWide(); |
| 1220 | LoadConstantWide(r_value, value); |
| 1221 | OpRegReg(kOpAnd, r_temp, r_value); |
| 1222 | OpRegReg(kOpAnd, result_reg, r_value); |
| 1223 | OpRegImm(kOpLsl, r_temp, shift); |
| 1224 | OpRegReg(kOpOr, result_reg, r_temp); |
| 1225 | FreeTemp(r_temp); |
| 1226 | FreeTemp(r_value); |
| 1227 | } |
| 1228 | |
| 1229 | bool X86Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { |
| 1230 | RegLocation rl_src_i = info->args[0]; |
| 1231 | RegLocation rl_i = (size == k64) ? LoadValueWide(rl_src_i, kCoreReg) |
| 1232 | : LoadValue(rl_src_i, kCoreReg); |
| 1233 | RegLocation rl_dest = (size == k64) ? InlineTargetWide(info) : InlineTarget(info); |
| 1234 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 1235 | if (size == k64) { |
| 1236 | if (cu_->instruction_set == kX86_64) { |
| 1237 | /* Use one bswap instruction to reverse byte order first and then use 3 rounds of |
| 1238 | swapping bits to reverse bits in a long number x. Using bswap to save instructions |
| 1239 | compared to generic luni implementation which has 5 rounds of swapping bits. |
| 1240 | x = bswap x |
| 1241 | x = (x & 0x5555555555555555) << 1 | (x >> 1) & 0x5555555555555555; |
| 1242 | x = (x & 0x3333333333333333) << 2 | (x >> 2) & 0x3333333333333333; |
| 1243 | x = (x & 0x0F0F0F0F0F0F0F0F) << 4 | (x >> 4) & 0x0F0F0F0F0F0F0F0F; |
| 1244 | */ |
| 1245 | OpRegReg(kOpRev, rl_result.reg, rl_i.reg); |
| 1246 | SwapBits64(rl_result.reg, 1, 0x5555555555555555); |
| 1247 | SwapBits64(rl_result.reg, 2, 0x3333333333333333); |
| 1248 | SwapBits64(rl_result.reg, 4, 0x0f0f0f0f0f0f0f0f); |
| 1249 | StoreValueWide(rl_dest, rl_result); |
| 1250 | return true; |
| 1251 | } |
| 1252 | RegStorage r_i_low = rl_i.reg.GetLow(); |
| 1253 | if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { |
| 1254 | // First REV shall clobber rl_result.reg.GetLowReg(), save the value in a temp for the second |
| 1255 | // REV. |
| 1256 | r_i_low = AllocTemp(); |
| 1257 | OpRegCopy(r_i_low, rl_i.reg); |
| 1258 | } |
| 1259 | OpRegReg(kOpRev, rl_result.reg.GetLow(), rl_i.reg.GetHigh()); |
| 1260 | OpRegReg(kOpRev, rl_result.reg.GetHigh(), r_i_low); |
| 1261 | if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { |
| 1262 | FreeTemp(r_i_low); |
| 1263 | } |
| 1264 | SwapBits(rl_result.reg.GetLow(), 1, 0x55555555); |
| 1265 | SwapBits(rl_result.reg.GetLow(), 2, 0x33333333); |
| 1266 | SwapBits(rl_result.reg.GetLow(), 4, 0x0f0f0f0f); |
| 1267 | SwapBits(rl_result.reg.GetHigh(), 1, 0x55555555); |
| 1268 | SwapBits(rl_result.reg.GetHigh(), 2, 0x33333333); |
| 1269 | SwapBits(rl_result.reg.GetHigh(), 4, 0x0f0f0f0f); |
| 1270 | StoreValueWide(rl_dest, rl_result); |
| 1271 | } else { |
| 1272 | OpRegReg(kOpRev, rl_result.reg, rl_i.reg); |
| 1273 | SwapBits(rl_result.reg, 1, 0x55555555); |
| 1274 | SwapBits(rl_result.reg, 2, 0x33333333); |
| 1275 | SwapBits(rl_result.reg, 4, 0x0f0f0f0f); |
| 1276 | StoreValue(rl_dest, rl_result); |
| 1277 | } |
| 1278 | return true; |
| 1279 | } |
| 1280 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1281 | LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1282 | CHECK(base_of_code_ != nullptr); |
| 1283 | |
| 1284 | // Address the start of the method |
| 1285 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 1286 | if (rl_method.wide) { |
| 1287 | LoadValueDirectWideFixed(rl_method, reg); |
| 1288 | } else { |
| 1289 | LoadValueDirectFixed(rl_method, reg); |
| 1290 | } |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1291 | store_method_addr_used_ = true; |
| 1292 | |
| 1293 | // Load the proper value from the literal area. |
| 1294 | // We don't know the proper offset for the value, so pick one that will force |
| 1295 | // 4 byte offset. We will fix this up in the assembler later to have the right |
| 1296 | // value. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1297 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1298 | LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256, |
| 1299 | 0, 0, target); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1300 | res->target = target; |
| 1301 | res->flags.fixup = kFixupLoad; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1302 | store_method_addr_used_ = true; |
| 1303 | return res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1304 | } |
| 1305 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1306 | LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1307 | LOG(FATAL) << "Unexpected use of OpVldm for x86"; |
| 1308 | return NULL; |
| 1309 | } |
| 1310 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1311 | LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1312 | LOG(FATAL) << "Unexpected use of OpVstm for x86"; |
| 1313 | return NULL; |
| 1314 | } |
| 1315 | |
| 1316 | void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, |
| 1317 | RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1318 | int first_bit, int second_bit) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1319 | RegStorage t_reg = AllocTemp(); |
| 1320 | OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); |
| 1321 | OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1322 | FreeTemp(t_reg); |
| 1323 | if (first_bit != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1324 | OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1325 | } |
| 1326 | } |
| 1327 | |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1328 | void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1329 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1330 | DCHECK(reg.Is64Bit()); |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 1331 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1332 | NewLIR2(kX86Cmp64RI8, reg.GetReg(), 0); |
| 1333 | } else { |
| 1334 | DCHECK(reg.IsPair()); |
| 1335 | |
| 1336 | // We are not supposed to clobber the incoming storage, so allocate a temporary. |
| 1337 | RegStorage t_reg = AllocTemp(); |
| 1338 | // Doing an OR is a quick way to check if both registers are zero. This will set the flags. |
| 1339 | OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); |
| 1340 | // The temp is no longer needed so free it at this time. |
| 1341 | FreeTemp(t_reg); |
| 1342 | } |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 1343 | |
| 1344 | // In case of zero, throw ArithmeticException. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1345 | GenDivZeroCheck(kCondEq); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1346 | } |
| 1347 | |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1348 | void X86Mir2Lir::GenArrayBoundsCheck(RegStorage index, |
| 1349 | RegStorage array_base, |
| 1350 | int len_offset) { |
| 1351 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 1352 | public: |
| 1353 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, |
| 1354 | RegStorage index, RegStorage array_base, int32_t len_offset) |
| 1355 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), |
| 1356 | index_(index), array_base_(array_base), len_offset_(len_offset) { |
| 1357 | } |
| 1358 | |
| 1359 | void Compile() OVERRIDE { |
| 1360 | m2l_->ResetRegPool(); |
| 1361 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 1362 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1363 | |
| 1364 | RegStorage new_index = index_; |
| 1365 | // Move index out of kArg1, either directly to kArg0, or to kArg2. |
Serguei Katkov | 4c7cc15 | 2014-06-24 00:50:02 +0700 | [diff] [blame] | 1366 | // TODO: clean-up to check not a number but with type |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1367 | if (index_ == m2l_->TargetReg(kArg1, kNotWide)) { |
| 1368 | if (array_base_ == m2l_->TargetReg(kArg0, kRef)) { |
| 1369 | m2l_->OpRegCopy(m2l_->TargetReg(kArg2, kNotWide), index_); |
| 1370 | new_index = m2l_->TargetReg(kArg2, kNotWide); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1371 | } else { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1372 | m2l_->OpRegCopy(m2l_->TargetReg(kArg0, kNotWide), index_); |
| 1373 | new_index = m2l_->TargetReg(kArg0, kNotWide); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1374 | } |
| 1375 | } |
| 1376 | // Load array length to kArg1. |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1377 | X86Mir2Lir* x86_m2l = static_cast<X86Mir2Lir*>(m2l_); |
| 1378 | x86_m2l->OpRegMem(kOpMov, m2l_->TargetReg(kArg1, kNotWide), array_base_, len_offset_); |
| 1379 | x86_m2l->CallRuntimeHelperRegReg(kQuickThrowArrayBounds, new_index, |
| 1380 | m2l_->TargetReg(kArg1, kNotWide), true); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1381 | } |
| 1382 | |
| 1383 | private: |
| 1384 | const RegStorage index_; |
| 1385 | const RegStorage array_base_; |
| 1386 | const int32_t len_offset_; |
| 1387 | }; |
| 1388 | |
| 1389 | OpRegMem(kOpCmp, index, array_base, len_offset); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1390 | MarkPossibleNullPointerException(0); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1391 | LIR* branch = OpCondBranch(kCondUge, nullptr); |
| 1392 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 1393 | index, array_base, len_offset)); |
| 1394 | } |
| 1395 | |
| 1396 | void X86Mir2Lir::GenArrayBoundsCheck(int32_t index, |
| 1397 | RegStorage array_base, |
| 1398 | int32_t len_offset) { |
| 1399 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 1400 | public: |
| 1401 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, |
| 1402 | int32_t index, RegStorage array_base, int32_t len_offset) |
| 1403 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), |
| 1404 | index_(index), array_base_(array_base), len_offset_(len_offset) { |
| 1405 | } |
| 1406 | |
| 1407 | void Compile() OVERRIDE { |
| 1408 | m2l_->ResetRegPool(); |
| 1409 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 1410 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1411 | |
| 1412 | // Load array length to kArg1. |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1413 | X86Mir2Lir* x86_m2l = static_cast<X86Mir2Lir*>(m2l_); |
| 1414 | x86_m2l->OpRegMem(kOpMov, m2l_->TargetReg(kArg1, kNotWide), array_base_, len_offset_); |
| 1415 | x86_m2l->LoadConstant(m2l_->TargetReg(kArg0, kNotWide), index_); |
| 1416 | x86_m2l->CallRuntimeHelperRegReg(kQuickThrowArrayBounds, m2l_->TargetReg(kArg0, kNotWide), |
| 1417 | m2l_->TargetReg(kArg1, kNotWide), true); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1418 | } |
| 1419 | |
| 1420 | private: |
| 1421 | const int32_t index_; |
| 1422 | const RegStorage array_base_; |
| 1423 | const int32_t len_offset_; |
| 1424 | }; |
| 1425 | |
| 1426 | NewLIR3(IS_SIMM8(index) ? kX86Cmp32MI8 : kX86Cmp32MI, array_base.GetReg(), len_offset, index); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1427 | MarkPossibleNullPointerException(0); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1428 | LIR* branch = OpCondBranch(kCondLs, nullptr); |
| 1429 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 1430 | index, array_base, len_offset)); |
| 1431 | } |
| 1432 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1433 | // Test suspend flag, return target of taken suspend branch |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1434 | LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 1435 | if (cu_->target64) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1436 | OpTlsCmp(Thread::ThreadFlagsOffset<8>(), 0); |
| 1437 | } else { |
| 1438 | OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0); |
| 1439 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1440 | return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); |
| 1441 | } |
| 1442 | |
| 1443 | // Decrement register and branch on condition |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1444 | LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1445 | OpRegImm(kOpSub, reg, 1); |
Yixin Shou | a0dac3e | 2014-01-23 05:01:22 -0800 | [diff] [blame] | 1446 | return OpCondBranch(c_code, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1447 | } |
| 1448 | |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 1449 | bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1450 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1451 | LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; |
| 1452 | return false; |
| 1453 | } |
| 1454 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1455 | bool X86Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { |
| 1456 | LOG(FATAL) << "Unexpected use of easyMultiply in x86"; |
| 1457 | return false; |
| 1458 | } |
| 1459 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1460 | LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1461 | LOG(FATAL) << "Unexpected use of OpIT in x86"; |
| 1462 | return NULL; |
| 1463 | } |
| 1464 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 1465 | void X86Mir2Lir::OpEndIT(LIR* it) { |
| 1466 | LOG(FATAL) << "Unexpected use of OpEndIT in x86"; |
| 1467 | } |
| 1468 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1469 | void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1470 | switch (val) { |
| 1471 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1472 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1473 | break; |
| 1474 | case 1: |
| 1475 | OpRegCopy(dest, src); |
| 1476 | break; |
| 1477 | default: |
| 1478 | OpRegRegImm(kOpMul, dest, src, val); |
| 1479 | break; |
| 1480 | } |
| 1481 | } |
| 1482 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1483 | void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1484 | // All memory accesses below reference dalvik regs. |
| 1485 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1486 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1487 | LIR *m; |
| 1488 | switch (val) { |
| 1489 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1490 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1491 | break; |
| 1492 | case 1: |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1493 | LoadBaseDisp(rs_rX86_SP, displacement, dest, k32, kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1494 | break; |
| 1495 | default: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1496 | m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), |
| 1497 | rs_rX86_SP.GetReg(), displacement, val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1498 | AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); |
| 1499 | break; |
| 1500 | } |
| 1501 | } |
| 1502 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1503 | void X86Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1504 | RegLocation rl_src2, int flags) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1505 | if (!cu_->target64) { |
| 1506 | // Some x86 32b ops are fallback. |
| 1507 | switch (opcode) { |
| 1508 | case Instruction::NOT_LONG: |
| 1509 | case Instruction::DIV_LONG: |
| 1510 | case Instruction::DIV_LONG_2ADDR: |
| 1511 | case Instruction::REM_LONG: |
| 1512 | case Instruction::REM_LONG_2ADDR: |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1513 | Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1514 | return; |
| 1515 | |
| 1516 | default: |
| 1517 | // Everything else we can handle. |
| 1518 | break; |
| 1519 | } |
| 1520 | } |
| 1521 | |
| 1522 | switch (opcode) { |
| 1523 | case Instruction::NOT_LONG: |
| 1524 | GenNotLong(rl_dest, rl_src2); |
| 1525 | return; |
| 1526 | |
| 1527 | case Instruction::ADD_LONG: |
| 1528 | case Instruction::ADD_LONG_2ADDR: |
| 1529 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1530 | return; |
| 1531 | |
| 1532 | case Instruction::SUB_LONG: |
| 1533 | case Instruction::SUB_LONG_2ADDR: |
| 1534 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); |
| 1535 | return; |
| 1536 | |
| 1537 | case Instruction::MUL_LONG: |
| 1538 | case Instruction::MUL_LONG_2ADDR: |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1539 | GenMulLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1540 | return; |
| 1541 | |
| 1542 | case Instruction::DIV_LONG: |
| 1543 | case Instruction::DIV_LONG_2ADDR: |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1544 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1545 | return; |
| 1546 | |
| 1547 | case Instruction::REM_LONG: |
| 1548 | case Instruction::REM_LONG_2ADDR: |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1549 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1550 | return; |
| 1551 | |
| 1552 | case Instruction::AND_LONG_2ADDR: |
| 1553 | case Instruction::AND_LONG: |
| 1554 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1555 | return; |
| 1556 | |
| 1557 | case Instruction::OR_LONG: |
| 1558 | case Instruction::OR_LONG_2ADDR: |
| 1559 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1560 | return; |
| 1561 | |
| 1562 | case Instruction::XOR_LONG: |
| 1563 | case Instruction::XOR_LONG_2ADDR: |
| 1564 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1565 | return; |
| 1566 | |
| 1567 | case Instruction::NEG_LONG: |
| 1568 | GenNegLong(rl_dest, rl_src2); |
| 1569 | return; |
| 1570 | |
| 1571 | default: |
| 1572 | LOG(FATAL) << "Invalid long arith op"; |
| 1573 | return; |
| 1574 | } |
| 1575 | } |
| 1576 | |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1577 | bool X86Mir2Lir::GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val, int flags) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1578 | // All memory accesses below reference dalvik regs. |
| 1579 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1580 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1581 | if (val == 0) { |
Alexei Zavjalov | d8191d0 | 2014-06-11 18:26:40 +0700 | [diff] [blame] | 1582 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1583 | if (cu_->target64) { |
| 1584 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
Alexei Zavjalov | d8191d0 | 2014-06-11 18:26:40 +0700 | [diff] [blame] | 1585 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1586 | OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow()); |
| 1587 | OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1588 | } |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1589 | StoreValueWide(rl_dest, rl_result); |
| 1590 | return true; |
| 1591 | } else if (val == 1) { |
| 1592 | StoreValueWide(rl_dest, rl_src1); |
| 1593 | return true; |
| 1594 | } else if (val == 2) { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1595 | GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1596 | return true; |
| 1597 | } else if (IsPowerOfTwo(val)) { |
| 1598 | int shift_amount = LowestSetBit(val); |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 1599 | if (!PartiallyIntersects(rl_src1, rl_dest)) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1600 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1601 | RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1602 | shift_amount, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1603 | StoreValueWide(rl_dest, rl_result); |
| 1604 | return true; |
| 1605 | } |
| 1606 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1607 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1608 | // Okay, on 32b just bite the bullet and do it, still better than the general case. |
| 1609 | if (!cu_->target64) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1610 | int32_t val_lo = Low32Bits(val); |
| 1611 | int32_t val_hi = High32Bits(val); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 1612 | // Prepare for explicit register usage. |
| 1613 | ExplicitTempRegisterLock(this, 3, &rs_r0, &rs_r1, &rs_r2); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1614 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1615 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1616 | int displacement = SRegOffset(rl_src1.s_reg_low); |
| 1617 | |
| 1618 | // ECX <- 1H * 2L |
| 1619 | // EAX <- 1L * 2H |
| 1620 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1621 | GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo); |
| 1622 | GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1623 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1624 | GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); |
| 1625 | GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1626 | } |
| 1627 | |
| 1628 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1629 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1630 | |
| 1631 | // EAX <- 2L |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1632 | LoadConstantNoClobber(rs_r0, val_lo); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1633 | |
| 1634 | // EDX:EAX <- 2L * 1L (double precision) |
| 1635 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1636 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1637 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1638 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1639 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1640 | true /* is_load */, true /* is_64bit */); |
| 1641 | } |
| 1642 | |
| 1643 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1644 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1645 | |
| 1646 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1647 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
| 1648 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1649 | StoreValueWide(rl_dest, rl_result); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1650 | return true; |
| 1651 | } |
| 1652 | return false; |
| 1653 | } |
| 1654 | |
| 1655 | void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1656 | RegLocation rl_src2, int flags) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1657 | if (rl_src1.is_const) { |
| 1658 | std::swap(rl_src1, rl_src2); |
| 1659 | } |
| 1660 | |
| 1661 | if (rl_src2.is_const) { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1662 | if (GenMulLongConst(rl_dest, rl_src1, mir_graph_->ConstantValueWide(rl_src2), flags)) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1663 | return; |
| 1664 | } |
| 1665 | } |
| 1666 | |
| 1667 | // All memory accesses below reference dalvik regs. |
| 1668 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1669 | |
| 1670 | if (cu_->target64) { |
| 1671 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1672 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1673 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1674 | if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && |
| 1675 | rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
| 1676 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
| 1677 | } else if (rl_result.reg.GetReg() != rl_src1.reg.GetReg() && |
| 1678 | rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
| 1679 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); |
| 1680 | } else if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && |
| 1681 | rl_result.reg.GetReg() != rl_src2.reg.GetReg()) { |
| 1682 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); |
| 1683 | } else { |
| 1684 | OpRegCopy(rl_result.reg, rl_src1.reg); |
| 1685 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); |
| 1686 | } |
| 1687 | StoreValueWide(rl_dest, rl_result); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1688 | return; |
| 1689 | } |
| 1690 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1691 | // Not multiplying by a constant. Do it the hard way |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1692 | // Check for V*V. We can eliminate a multiply in that case, as 2L*1H == 2H*1L. |
| 1693 | bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == |
| 1694 | mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 1695 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 1696 | // Prepare for explicit register usage. |
| 1697 | ExplicitTempRegisterLock(this, 3, &rs_r0, &rs_r1, &rs_r2); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1698 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
| 1699 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1700 | |
| 1701 | // At this point, the VRs are in their home locations. |
| 1702 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1703 | bool src2_in_reg = rl_src2.location == kLocPhysReg; |
| 1704 | |
| 1705 | // ECX <- 1H |
| 1706 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1707 | NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1708 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1709 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32, |
| 1710 | kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1711 | } |
| 1712 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1713 | if (is_square) { |
| 1714 | // Take advantage of the fact that the values are the same. |
| 1715 | // ECX <- ECX * 2L (1H * 2L) |
| 1716 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1717 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1718 | } else { |
| 1719 | int displacement = SRegOffset(rl_src2.s_reg_low); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 1720 | LIR* m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1721 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1722 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1723 | true /* is_load */, true /* is_64bit */); |
| 1724 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1725 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1726 | // ECX <- 2*ECX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1727 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1728 | } else { |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1729 | // EAX <- 2H |
| 1730 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1731 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1732 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1733 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0, k32, |
| 1734 | kNotVolatile); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1735 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1736 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1737 | // EAX <- EAX * 1L (2H * 1L) |
| 1738 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1739 | NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1740 | } else { |
| 1741 | int displacement = SRegOffset(rl_src1.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1742 | LIR *m = NewLIR3(kX86Imul32RM, rs_r0.GetReg(), rs_rX86_SP.GetReg(), |
| 1743 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1744 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1745 | true /* is_load */, true /* is_64bit */); |
| 1746 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1747 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1748 | // ECX <- ECX * 2L (1H * 2L) |
| 1749 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1750 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1751 | } else { |
| 1752 | int displacement = SRegOffset(rl_src2.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1753 | LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), |
| 1754 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1755 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1756 | true /* is_load */, true /* is_64bit */); |
| 1757 | } |
| 1758 | |
| 1759 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1760 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1761 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1762 | |
| 1763 | // EAX <- 2L |
| 1764 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1765 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1766 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1767 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32, |
| 1768 | kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1769 | } |
| 1770 | |
| 1771 | // EDX:EAX <- 2L * 1L (double precision) |
| 1772 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1773 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1774 | } else { |
| 1775 | int displacement = SRegOffset(rl_src1.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1776 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1777 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1778 | true /* is_load */, true /* is_64bit */); |
| 1779 | } |
| 1780 | |
| 1781 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1782 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1783 | |
| 1784 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1785 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1786 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1787 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1788 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1789 | |
| 1790 | void X86Mir2Lir::GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, |
| 1791 | Instruction::Code op) { |
| 1792 | DCHECK_EQ(rl_dest.location, kLocPhysReg); |
| 1793 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
| 1794 | if (rl_src.location == kLocPhysReg) { |
| 1795 | // Both operands are in registers. |
Serguei Katkov | ab5545f | 2014-03-25 10:51:15 +0700 | [diff] [blame] | 1796 | // But we must ensure that rl_src is in pair |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1797 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1798 | NewLIR2(x86op, rl_dest.reg.GetReg(), rl_src.reg.GetReg()); |
| 1799 | } else { |
| 1800 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1801 | if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) { |
| 1802 | // The registers are the same, so we would clobber it before the use. |
| 1803 | RegStorage temp_reg = AllocTemp(); |
| 1804 | OpRegCopy(temp_reg, rl_dest.reg); |
| 1805 | rl_src.reg.SetHighReg(temp_reg.GetReg()); |
| 1806 | } |
| 1807 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1808 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1809 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1810 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1811 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1812 | return; |
| 1813 | } |
| 1814 | |
| 1815 | // RHS is in memory. |
| 1816 | DCHECK((rl_src.location == kLocDalvikFrame) || |
| 1817 | (rl_src.location == kLocCompilerTemp)); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1818 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1819 | int displacement = SRegOffset(rl_src.s_reg_low); |
| 1820 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1821 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1822 | LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), |
| 1823 | r_base, displacement + LOWORD_OFFSET); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1824 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 1825 | true /* is_load */, true /* is64bit */); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1826 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1827 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1828 | lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1829 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1830 | true /* is_load */, true /* is64bit */); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1831 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1832 | } |
| 1833 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1834 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1835 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1836 | if (rl_dest.location == kLocPhysReg) { |
| 1837 | // Ensure we are in a register pair |
| 1838 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1839 | |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1840 | rl_src = UpdateLocWideTyped(rl_src, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1841 | GenLongRegOrMemOp(rl_result, rl_src, op); |
| 1842 | StoreFinalValueWide(rl_dest, rl_result); |
| 1843 | return; |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 1844 | } else if (!cu_->target64 && Intersects(rl_src, rl_dest)) { |
| 1845 | // Handle the case when src and dest are intersect. |
| 1846 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1847 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1848 | rl_src = UpdateLocWideTyped(rl_src, kCoreReg); |
| 1849 | GenLongRegOrMemOp(rl_result, rl_src, op); |
| 1850 | StoreFinalValueWide(rl_dest, rl_result); |
| 1851 | return; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1852 | } |
| 1853 | |
| 1854 | // It wasn't in registers, so it better be in memory. |
| 1855 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1856 | (rl_dest.location == kLocCompilerTemp)); |
| 1857 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1858 | |
| 1859 | // Operate directly into memory. |
| 1860 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1861 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1862 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 1863 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1864 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1865 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1866 | cu_->target64 ? rl_src.reg.GetReg() : rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1867 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 1868 | true /* is_load */, true /* is64bit */); |
| 1869 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1870 | false /* is_load */, true /* is64bit */); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1871 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1872 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1873 | lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1874 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1875 | true /* is_load */, true /* is64bit */); |
| 1876 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1877 | false /* is_load */, true /* is64bit */); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1878 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1879 | } |
| 1880 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1881 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1, |
| 1882 | RegLocation rl_src2, Instruction::Code op, |
| 1883 | bool is_commutative) { |
| 1884 | // Is this really a 2 operand operation? |
| 1885 | switch (op) { |
| 1886 | case Instruction::ADD_LONG_2ADDR: |
| 1887 | case Instruction::SUB_LONG_2ADDR: |
| 1888 | case Instruction::AND_LONG_2ADDR: |
| 1889 | case Instruction::OR_LONG_2ADDR: |
| 1890 | case Instruction::XOR_LONG_2ADDR: |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 1891 | if (GenerateTwoOperandInstructions()) { |
| 1892 | GenLongArith(rl_dest, rl_src2, op); |
| 1893 | return; |
| 1894 | } |
| 1895 | break; |
| 1896 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1897 | default: |
| 1898 | break; |
| 1899 | } |
| 1900 | |
| 1901 | if (rl_dest.location == kLocPhysReg) { |
| 1902 | RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg); |
| 1903 | |
| 1904 | // We are about to clobber the LHS, so it needs to be a temp. |
| 1905 | rl_result = ForceTempWide(rl_result); |
| 1906 | |
| 1907 | // Perform the operation using the RHS. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1908 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1909 | GenLongRegOrMemOp(rl_result, rl_src2, op); |
| 1910 | |
| 1911 | // And now record that the result is in the temp. |
| 1912 | StoreFinalValueWide(rl_dest, rl_result); |
| 1913 | return; |
| 1914 | } |
| 1915 | |
| 1916 | // It wasn't in registers, so it better be in memory. |
| 1917 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1918 | (rl_dest.location == kLocCompilerTemp)); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1919 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
| 1920 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1921 | |
| 1922 | // Get one of the source operands into temporary register. |
| 1923 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1924 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1925 | if (IsTemp(rl_src1.reg)) { |
| 1926 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1927 | } else if (is_commutative) { |
| 1928 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1929 | // We need at least one of them to be a temporary. |
| 1930 | if (!IsTemp(rl_src2.reg)) { |
| 1931 | rl_src1 = ForceTempWide(rl_src1); |
| 1932 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1933 | } else { |
| 1934 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 1935 | StoreFinalValueWide(rl_dest, rl_src2); |
| 1936 | return; |
| 1937 | } |
| 1938 | } else { |
| 1939 | // Need LHS to be the temp. |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1940 | rl_src1 = ForceTempWide(rl_src1); |
Yevgeny Rouban | 91b6ffa | 2014-03-07 14:35:44 +0700 | [diff] [blame] | 1941 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1942 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1943 | } else { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1944 | if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { |
| 1945 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1946 | } else if (is_commutative) { |
| 1947 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1948 | // We need at least one of them to be a temporary. |
| 1949 | if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) { |
| 1950 | rl_src1 = ForceTempWide(rl_src1); |
| 1951 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1952 | } else { |
| 1953 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 1954 | StoreFinalValueWide(rl_dest, rl_src2); |
| 1955 | return; |
| 1956 | } |
| 1957 | } else { |
| 1958 | // Need LHS to be the temp. |
| 1959 | rl_src1 = ForceTempWide(rl_src1); |
| 1960 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1961 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1962 | } |
| 1963 | |
| 1964 | StoreFinalValueWide(rl_dest, rl_src1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1965 | } |
| 1966 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 1967 | void X86Mir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1968 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1969 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1970 | RegLocation rl_result; |
| 1971 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1972 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 1973 | OpReg(kOpNot, rl_result.reg); |
| 1974 | StoreValueWide(rl_dest, rl_result); |
| 1975 | } else { |
| 1976 | LOG(FATAL) << "Unexpected use GenNotLong()"; |
| 1977 | } |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 1978 | } |
| 1979 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 1980 | void X86Mir2Lir::GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, |
| 1981 | int64_t imm, bool is_div) { |
| 1982 | if (imm == 0) { |
| 1983 | GenDivZeroException(); |
| 1984 | } else if (imm == 1) { |
| 1985 | if (is_div) { |
| 1986 | // x / 1 == x. |
| 1987 | StoreValueWide(rl_dest, rl_src); |
| 1988 | } else { |
| 1989 | // x % 1 == 0. |
| 1990 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1991 | LoadConstantWide(rl_result.reg, 0); |
| 1992 | StoreValueWide(rl_dest, rl_result); |
| 1993 | } |
| 1994 | } else if (imm == -1) { // handle 0x8000000000000000 / -1 special case. |
| 1995 | if (is_div) { |
| 1996 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1997 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1998 | RegStorage rs_temp = AllocTempWide(); |
| 1999 | |
| 2000 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 2001 | LoadConstantWide(rs_temp, 0x8000000000000000); |
| 2002 | |
| 2003 | // If x == MIN_LONG, return MIN_LONG. |
| 2004 | OpRegReg(kOpCmp, rl_src.reg, rs_temp); |
| 2005 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 2006 | |
| 2007 | // For x != MIN_LONG, x / -1 == -x. |
| 2008 | OpReg(kOpNeg, rl_result.reg); |
| 2009 | |
| 2010 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
| 2011 | FreeTemp(rs_temp); |
| 2012 | StoreValueWide(rl_dest, rl_result); |
| 2013 | } else { |
| 2014 | // x % -1 == 0. |
| 2015 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2016 | LoadConstantWide(rl_result.reg, 0); |
| 2017 | StoreValueWide(rl_dest, rl_result); |
| 2018 | } |
| 2019 | } else if (is_div && IsPowerOfTwo(std::abs(imm))) { |
| 2020 | // Division using shifting. |
| 2021 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2022 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2023 | if (IsSameReg(rl_result.reg, rl_src.reg)) { |
| 2024 | RegStorage rs_temp = AllocTypedTempWide(false, kCoreReg); |
| 2025 | rl_result.reg.SetReg(rs_temp.GetReg()); |
| 2026 | } |
| 2027 | LoadConstantWide(rl_result.reg, std::abs(imm) - 1); |
| 2028 | OpRegReg(kOpAdd, rl_result.reg, rl_src.reg); |
| 2029 | NewLIR2(kX86Test64RR, rl_src.reg.GetReg(), rl_src.reg.GetReg()); |
| 2030 | OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg); |
| 2031 | int shift_amount = LowestSetBit(imm); |
| 2032 | OpRegImm(kOpAsr, rl_result.reg, shift_amount); |
| 2033 | if (imm < 0) { |
| 2034 | OpReg(kOpNeg, rl_result.reg); |
| 2035 | } |
| 2036 | StoreValueWide(rl_dest, rl_result); |
| 2037 | } else { |
| 2038 | CHECK(imm <= -2 || imm >= 2); |
| 2039 | |
| 2040 | FlushReg(rs_r0q); |
| 2041 | Clobber(rs_r0q); |
| 2042 | LockTemp(rs_r0q); |
| 2043 | FlushReg(rs_r2q); |
| 2044 | Clobber(rs_r2q); |
| 2045 | LockTemp(rs_r2q); |
| 2046 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2047 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
| 2048 | is_div ? rs_r2q : rs_r0q, INVALID_SREG, INVALID_SREG}; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2049 | |
| 2050 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 2051 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 2052 | int64_t magic; |
| 2053 | int shift; |
| 2054 | CalculateMagicAndShift(imm, magic, shift, true /* is_long */); |
| 2055 | |
| 2056 | /* |
| 2057 | * For imm >= 2, |
| 2058 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 2059 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 2060 | * For imm <= -2, |
| 2061 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 2062 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 2063 | * We implement this algorithm in the following way: |
| 2064 | * 1. multiply magic number m and numerator n, get the higher 64bit result in RDX |
| 2065 | * 2. if imm > 0 and magic < 0, add numerator to RDX |
| 2066 | * if imm < 0 and magic > 0, sub numerator from RDX |
| 2067 | * 3. if S !=0, SAR S bits for RDX |
| 2068 | * 4. add 1 to RDX if RDX < 0 |
| 2069 | * 5. Thus, RDX is the quotient |
| 2070 | */ |
| 2071 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2072 | // RAX = magic. |
| 2073 | LoadConstantWide(rs_r0q, magic); |
| 2074 | |
| 2075 | // Multiply by numerator. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2076 | RegStorage numerator_reg; |
| 2077 | if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { |
| 2078 | // We will need the value later. |
| 2079 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2080 | numerator_reg = rl_src.reg; |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2081 | |
| 2082 | // RDX:RAX = magic * numerator. |
| 2083 | NewLIR1(kX86Imul64DaR, numerator_reg.GetReg()); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2084 | } else { |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2085 | // Only need this once. Multiply directly from the value. |
| 2086 | rl_src = UpdateLocWideTyped(rl_src, kCoreReg); |
| 2087 | if (rl_src.location != kLocPhysReg) { |
| 2088 | // Okay, we can do this from memory. |
| 2089 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 2090 | int displacement = SRegOffset(rl_src.s_reg_low); |
| 2091 | // RDX:RAX = magic * numerator. |
| 2092 | LIR *m = NewLIR2(kX86Imul64DaM, rs_rX86_SP.GetReg(), displacement); |
| 2093 | AnnotateDalvikRegAccess(m, displacement >> 2, |
| 2094 | true /* is_load */, true /* is_64bit */); |
| 2095 | } else { |
| 2096 | // RDX:RAX = magic * numerator. |
| 2097 | NewLIR1(kX86Imul64DaR, rl_src.reg.GetReg()); |
| 2098 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2099 | } |
| 2100 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2101 | if (imm > 0 && magic < 0) { |
| 2102 | // Add numerator to RDX. |
| 2103 | DCHECK(numerator_reg.Valid()); |
| 2104 | OpRegReg(kOpAdd, rs_r2q, numerator_reg); |
| 2105 | } else if (imm < 0 && magic > 0) { |
| 2106 | DCHECK(numerator_reg.Valid()); |
| 2107 | OpRegReg(kOpSub, rs_r2q, numerator_reg); |
| 2108 | } |
| 2109 | |
| 2110 | // Do we need the shift? |
| 2111 | if (shift != 0) { |
| 2112 | // Shift RDX by 'shift' bits. |
| 2113 | OpRegImm(kOpAsr, rs_r2q, shift); |
| 2114 | } |
| 2115 | |
| 2116 | // Move RDX to RAX. |
| 2117 | OpRegCopyWide(rs_r0q, rs_r2q); |
| 2118 | |
| 2119 | // Move sign bit to bit 0, zeroing the rest. |
| 2120 | OpRegImm(kOpLsr, rs_r2q, 63); |
| 2121 | |
| 2122 | // RDX = RDX + RAX. |
| 2123 | OpRegReg(kOpAdd, rs_r2q, rs_r0q); |
| 2124 | |
| 2125 | // Quotient is in RDX. |
| 2126 | if (!is_div) { |
| 2127 | // We need to compute the remainder. |
| 2128 | // Remainder is divisor - (quotient * imm). |
| 2129 | DCHECK(numerator_reg.Valid()); |
| 2130 | OpRegCopyWide(rs_r0q, numerator_reg); |
| 2131 | |
| 2132 | // Imul doesn't support 64-bit imms. |
| 2133 | if (imm > std::numeric_limits<int32_t>::max() || |
| 2134 | imm < std::numeric_limits<int32_t>::min()) { |
| 2135 | RegStorage rs_temp = AllocTempWide(); |
| 2136 | LoadConstantWide(rs_temp, imm); |
| 2137 | |
| 2138 | // RAX = numerator * imm. |
| 2139 | NewLIR2(kX86Imul64RR, rs_r2q.GetReg(), rs_temp.GetReg()); |
| 2140 | |
| 2141 | FreeTemp(rs_temp); |
| 2142 | } else { |
| 2143 | // RAX = numerator * imm. |
| 2144 | int short_imm = static_cast<int>(imm); |
| 2145 | NewLIR3(kX86Imul64RRI, rs_r2q.GetReg(), rs_r2q.GetReg(), short_imm); |
| 2146 | } |
| 2147 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2148 | // RAX -= RDX. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2149 | OpRegReg(kOpSub, rs_r0q, rs_r2q); |
| 2150 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2151 | // Result in RAX. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2152 | } else { |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2153 | // Result in RDX. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2154 | } |
| 2155 | StoreValueWide(rl_dest, rl_result); |
| 2156 | FreeTemp(rs_r0q); |
| 2157 | FreeTemp(rs_r2q); |
| 2158 | } |
| 2159 | } |
| 2160 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2161 | void X86Mir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2162 | RegLocation rl_src2, bool is_div, int flags) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2163 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2164 | LOG(FATAL) << "Unexpected use GenDivRemLong()"; |
| 2165 | return; |
| 2166 | } |
| 2167 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2168 | if (rl_src2.is_const) { |
| 2169 | DCHECK(rl_src2.wide); |
| 2170 | int64_t imm = mir_graph_->ConstantValueWide(rl_src2); |
| 2171 | GenDivRemLongLit(rl_dest, rl_src1, imm, is_div); |
| 2172 | return; |
| 2173 | } |
| 2174 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2175 | // We have to use fixed registers, so flush all the temps. |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 2176 | // Prepare for explicit register usage. |
| 2177 | ExplicitTempRegisterLock(this, 4, &rs_r0q, &rs_r1q, &rs_r2q, &rs_r6q); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2178 | |
| 2179 | // Load LHS into RAX. |
| 2180 | LoadValueDirectWideFixed(rl_src1, rs_r0q); |
| 2181 | |
| 2182 | // Load RHS into RCX. |
| 2183 | LoadValueDirectWideFixed(rl_src2, rs_r1q); |
| 2184 | |
| 2185 | // Copy LHS sign bit into RDX. |
| 2186 | NewLIR0(kx86Cqo64Da); |
| 2187 | |
| 2188 | // Handle division by zero case. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2189 | if ((flags & MIR_IGNORE_DIV_ZERO_CHECK) == 0) { |
| 2190 | GenDivZeroCheckWide(rs_r1q); |
| 2191 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2192 | |
| 2193 | // Have to catch 0x8000000000000000/-1 case, or we will get an exception! |
| 2194 | NewLIR2(kX86Cmp64RI8, rs_r1q.GetReg(), -1); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 2195 | LIR* minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2196 | |
| 2197 | // RHS is -1. |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 2198 | LoadConstantWide(rs_r6q, 0x8000000000000000); |
| 2199 | NewLIR2(kX86Cmp64RR, rs_r0q.GetReg(), rs_r6q.GetReg()); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2200 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2201 | |
| 2202 | // In 0x8000000000000000/-1 case. |
| 2203 | if (!is_div) { |
| 2204 | // For DIV, RAX is already right. For REM, we need RDX 0. |
| 2205 | NewLIR2(kX86Xor64RR, rs_r2q.GetReg(), rs_r2q.GetReg()); |
| 2206 | } |
| 2207 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 2208 | |
| 2209 | // Expected case. |
| 2210 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 2211 | minint_branch->target = minus_one_branch->target; |
| 2212 | NewLIR1(kX86Idivmod64DaR, rs_r1q.GetReg()); |
| 2213 | done->target = NewLIR0(kPseudoTargetLabel); |
| 2214 | |
| 2215 | // Result is in RAX for div and RDX for rem. |
| 2216 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r0q, INVALID_SREG, INVALID_SREG}; |
| 2217 | if (!is_div) { |
| 2218 | rl_result.reg.SetReg(r2q); |
| 2219 | } |
| 2220 | |
| 2221 | StoreValueWide(rl_dest, rl_result); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2222 | } |
| 2223 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 2224 | void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2225 | rl_src = LoadValueWide(rl_src, kCoreReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2226 | RegLocation rl_result; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2227 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2228 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2229 | OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); |
| 2230 | } else { |
| 2231 | rl_result = ForceTempWide(rl_src); |
| 2232 | if (((rl_dest.location == kLocPhysReg) && (rl_src.location == kLocPhysReg)) && |
| 2233 | ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) { |
| 2234 | // The registers are the same, so we would clobber it before the use. |
| 2235 | RegStorage temp_reg = AllocTemp(); |
| 2236 | OpRegCopy(temp_reg, rl_result.reg); |
| 2237 | rl_result.reg.SetHighReg(temp_reg.GetReg()); |
| 2238 | } |
| 2239 | OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow |
| 2240 | OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF |
| 2241 | OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2242 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2243 | StoreValueWide(rl_dest, rl_result); |
| 2244 | } |
| 2245 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2246 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 2247 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 2248 | X86OpCode opcode = kX86Bkpt; |
| 2249 | switch (op) { |
| 2250 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 2251 | case kOpMov: opcode = kX86Mov32RT; break; |
| 2252 | default: |
| 2253 | LOG(FATAL) << "Bad opcode: " << op; |
| 2254 | break; |
| 2255 | } |
| 2256 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
| 2257 | } |
| 2258 | |
| 2259 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) { |
| 2260 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2261 | X86OpCode opcode = kX86Bkpt; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2262 | if (cu_->target64 && r_dest.Is64BitSolo()) { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 2263 | switch (op) { |
| 2264 | case kOpCmp: opcode = kX86Cmp64RT; break; |
| 2265 | case kOpMov: opcode = kX86Mov64RT; break; |
| 2266 | default: |
| 2267 | LOG(FATAL) << "Bad opcode(OpRegThreadMem 64): " << op; |
| 2268 | break; |
| 2269 | } |
| 2270 | } else { |
| 2271 | switch (op) { |
| 2272 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 2273 | case kOpMov: opcode = kX86Mov32RT; break; |
| 2274 | default: |
| 2275 | LOG(FATAL) << "Bad opcode: " << op; |
| 2276 | break; |
| 2277 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2278 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2279 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2280 | } |
| 2281 | |
| 2282 | /* |
| 2283 | * Generate array load |
| 2284 | */ |
| 2285 | void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2286 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2287 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2288 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2289 | RegLocation rl_result; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2290 | rl_array = LoadValue(rl_array, kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2291 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2292 | int data_offset; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2293 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2294 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 2295 | } else { |
| 2296 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 2297 | } |
| 2298 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2299 | bool constant_index = rl_index.is_const; |
| 2300 | int32_t constant_index_value = 0; |
| 2301 | if (!constant_index) { |
| 2302 | rl_index = LoadValue(rl_index, kCoreReg); |
| 2303 | } else { |
| 2304 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 2305 | // If index is constant, just fold it into the data offset |
| 2306 | data_offset += constant_index_value << scale; |
| 2307 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2308 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2309 | } |
| 2310 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2311 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2312 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2313 | |
| 2314 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2315 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2316 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2317 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2318 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2319 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2320 | } |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2321 | rl_result = EvalLoc(rl_dest, reg_class, true); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 2322 | LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2323 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2324 | StoreValueWide(rl_dest, rl_result); |
| 2325 | } else { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2326 | StoreValue(rl_dest, rl_result); |
| 2327 | } |
| 2328 | } |
| 2329 | |
| 2330 | /* |
| 2331 | * Generate array store |
| 2332 | * |
| 2333 | */ |
| 2334 | void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2335 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2336 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2337 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 2338 | int data_offset; |
| 2339 | |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2340 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2341 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 2342 | } else { |
| 2343 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 2344 | } |
| 2345 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2346 | rl_array = LoadValue(rl_array, kRefReg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2347 | bool constant_index = rl_index.is_const; |
| 2348 | int32_t constant_index_value = 0; |
| 2349 | if (!constant_index) { |
| 2350 | rl_index = LoadValue(rl_index, kCoreReg); |
| 2351 | } else { |
| 2352 | // If index is constant, just fold it into the data offset |
| 2353 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 2354 | data_offset += constant_index_value << scale; |
| 2355 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2356 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2357 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2358 | |
| 2359 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2360 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2361 | |
| 2362 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2363 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2364 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2365 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2366 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2367 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2368 | } |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2369 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2370 | rl_src = LoadValueWide(rl_src, reg_class); |
| 2371 | } else { |
| 2372 | rl_src = LoadValue(rl_src, reg_class); |
| 2373 | } |
| 2374 | // If the src reg can't be byte accessed, move it to a temp first. |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 2375 | if ((size == kSignedByte || size == kUnsignedByte) && !IsByteRegister(rl_src.reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2376 | RegStorage temp = AllocTemp(); |
| 2377 | OpRegCopy(temp, rl_src.reg); |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 2378 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2379 | } else { |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 2380 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2381 | } |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2382 | if (card_mark) { |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 2383 | // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2384 | if (!constant_index) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2385 | FreeTemp(rl_index.reg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2386 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2387 | MarkGCCard(rl_src.reg, rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2388 | } |
| 2389 | } |
| 2390 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2391 | RegLocation X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2392 | RegLocation rl_src, int shift_amount, int flags) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2393 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2394 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2395 | OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ |
| 2396 | switch (opcode) { |
| 2397 | case Instruction::SHL_LONG: |
| 2398 | case Instruction::SHL_LONG_2ADDR: |
| 2399 | op = kOpLsl; |
| 2400 | break; |
| 2401 | case Instruction::SHR_LONG: |
| 2402 | case Instruction::SHR_LONG_2ADDR: |
| 2403 | op = kOpAsr; |
| 2404 | break; |
| 2405 | case Instruction::USHR_LONG: |
| 2406 | case Instruction::USHR_LONG_2ADDR: |
| 2407 | op = kOpLsr; |
| 2408 | break; |
| 2409 | default: |
| 2410 | LOG(FATAL) << "Unexpected case"; |
| 2411 | } |
| 2412 | OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount); |
| 2413 | } else { |
| 2414 | switch (opcode) { |
| 2415 | case Instruction::SHL_LONG: |
| 2416 | case Instruction::SHL_LONG_2ADDR: |
| 2417 | DCHECK_NE(shift_amount, 1); // Prevent a double store from happening. |
| 2418 | if (shift_amount == 32) { |
| 2419 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 2420 | LoadConstant(rl_result.reg.GetLow(), 0); |
| 2421 | } else if (shift_amount > 31) { |
| 2422 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 2423 | NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32); |
| 2424 | LoadConstant(rl_result.reg.GetLow(), 0); |
| 2425 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2426 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2427 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2428 | NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), |
| 2429 | shift_amount); |
| 2430 | NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount); |
| 2431 | } |
| 2432 | break; |
| 2433 | case Instruction::SHR_LONG: |
| 2434 | case Instruction::SHR_LONG_2ADDR: |
| 2435 | if (shift_amount == 32) { |
| 2436 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2437 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2438 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
| 2439 | } else if (shift_amount > 31) { |
| 2440 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2441 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2442 | NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 2443 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
| 2444 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2445 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2446 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2447 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), |
| 2448 | shift_amount); |
| 2449 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount); |
| 2450 | } |
| 2451 | break; |
| 2452 | case Instruction::USHR_LONG: |
| 2453 | case Instruction::USHR_LONG_2ADDR: |
| 2454 | if (shift_amount == 32) { |
| 2455 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2456 | LoadConstant(rl_result.reg.GetHigh(), 0); |
| 2457 | } else if (shift_amount > 31) { |
| 2458 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2459 | NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 2460 | LoadConstant(rl_result.reg.GetHigh(), 0); |
| 2461 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2462 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2463 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2464 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), |
| 2465 | shift_amount); |
| 2466 | NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount); |
| 2467 | } |
| 2468 | break; |
| 2469 | default: |
| 2470 | LOG(FATAL) << "Unexpected case"; |
| 2471 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2472 | } |
| 2473 | return rl_result; |
| 2474 | } |
| 2475 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2476 | void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2477 | RegLocation rl_src, RegLocation rl_shift, int flags) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2478 | // Per spec, we only care about low 6 bits of shift amount. |
| 2479 | int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; |
| 2480 | if (shift_amount == 0) { |
| 2481 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2482 | StoreValueWide(rl_dest, rl_src); |
| 2483 | return; |
| 2484 | } else if (shift_amount == 1 && |
| 2485 | (opcode == Instruction::SHL_LONG || opcode == Instruction::SHL_LONG_2ADDR)) { |
| 2486 | // Need to handle this here to avoid calling StoreValueWide twice. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2487 | GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src, rl_src, flags); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2488 | return; |
| 2489 | } |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 2490 | if (PartiallyIntersects(rl_src, rl_dest)) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2491 | GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); |
| 2492 | return; |
| 2493 | } |
| 2494 | rl_src = LoadValueWide(rl_src, kCoreReg); |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2495 | RegLocation rl_result = GenShiftImmOpLong(opcode, rl_dest, rl_src, shift_amount, flags); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2496 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2497 | } |
| 2498 | |
| 2499 | void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2500 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 2501 | int flags) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2502 | bool isConstSuccess = false; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2503 | switch (opcode) { |
| 2504 | case Instruction::ADD_LONG: |
| 2505 | case Instruction::AND_LONG: |
| 2506 | case Instruction::OR_LONG: |
| 2507 | case Instruction::XOR_LONG: |
| 2508 | if (rl_src2.is_const) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2509 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2510 | } else { |
| 2511 | DCHECK(rl_src1.is_const); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2512 | isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2513 | } |
| 2514 | break; |
| 2515 | case Instruction::SUB_LONG: |
| 2516 | case Instruction::SUB_LONG_2ADDR: |
| 2517 | if (rl_src2.is_const) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2518 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2519 | } else { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2520 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2521 | isConstSuccess = true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2522 | } |
| 2523 | break; |
| 2524 | case Instruction::ADD_LONG_2ADDR: |
| 2525 | case Instruction::OR_LONG_2ADDR: |
| 2526 | case Instruction::XOR_LONG_2ADDR: |
| 2527 | case Instruction::AND_LONG_2ADDR: |
| 2528 | if (rl_src2.is_const) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2529 | if (GenerateTwoOperandInstructions()) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2530 | isConstSuccess = GenLongImm(rl_dest, rl_src2, opcode); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2531 | } else { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2532 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2533 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2534 | } else { |
| 2535 | DCHECK(rl_src1.is_const); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2536 | isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2537 | } |
| 2538 | break; |
| 2539 | default: |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2540 | isConstSuccess = false; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2541 | break; |
| 2542 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2543 | |
| 2544 | if (!isConstSuccess) { |
| 2545 | // Default - bail to non-const handler. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2546 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2547 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2548 | } |
| 2549 | |
| 2550 | bool X86Mir2Lir::IsNoOp(Instruction::Code op, int32_t value) { |
| 2551 | switch (op) { |
| 2552 | case Instruction::AND_LONG_2ADDR: |
| 2553 | case Instruction::AND_LONG: |
| 2554 | return value == -1; |
| 2555 | case Instruction::OR_LONG: |
| 2556 | case Instruction::OR_LONG_2ADDR: |
| 2557 | case Instruction::XOR_LONG: |
| 2558 | case Instruction::XOR_LONG_2ADDR: |
| 2559 | return value == 0; |
| 2560 | default: |
| 2561 | return false; |
| 2562 | } |
| 2563 | } |
| 2564 | |
| 2565 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 2566 | bool is_high_op) { |
| 2567 | bool rhs_in_mem = rhs.location != kLocPhysReg; |
| 2568 | bool dest_in_mem = dest.location != kLocPhysReg; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2569 | bool is64Bit = cu_->target64; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2570 | DCHECK(!rhs_in_mem || !dest_in_mem); |
| 2571 | switch (op) { |
| 2572 | case Instruction::ADD_LONG: |
| 2573 | case Instruction::ADD_LONG_2ADDR: |
| 2574 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2575 | return is64Bit ? kX86Add64MR : is_high_op ? kX86Adc32MR : kX86Add32MR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2576 | } else if (rhs_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2577 | return is64Bit ? kX86Add64RM : is_high_op ? kX86Adc32RM : kX86Add32RM; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2578 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2579 | return is64Bit ? kX86Add64RR : is_high_op ? kX86Adc32RR : kX86Add32RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2580 | case Instruction::SUB_LONG: |
| 2581 | case Instruction::SUB_LONG_2ADDR: |
| 2582 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2583 | return is64Bit ? kX86Sub64MR : is_high_op ? kX86Sbb32MR : kX86Sub32MR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2584 | } else if (rhs_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2585 | return is64Bit ? kX86Sub64RM : is_high_op ? kX86Sbb32RM : kX86Sub32RM; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2586 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2587 | return is64Bit ? kX86Sub64RR : is_high_op ? kX86Sbb32RR : kX86Sub32RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2588 | case Instruction::AND_LONG_2ADDR: |
| 2589 | case Instruction::AND_LONG: |
| 2590 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2591 | return is64Bit ? kX86And64MR : kX86And32MR; |
| 2592 | } |
| 2593 | if (is64Bit) { |
| 2594 | return rhs_in_mem ? kX86And64RM : kX86And64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2595 | } |
| 2596 | return rhs_in_mem ? kX86And32RM : kX86And32RR; |
| 2597 | case Instruction::OR_LONG: |
| 2598 | case Instruction::OR_LONG_2ADDR: |
| 2599 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2600 | return is64Bit ? kX86Or64MR : kX86Or32MR; |
| 2601 | } |
| 2602 | if (is64Bit) { |
| 2603 | return rhs_in_mem ? kX86Or64RM : kX86Or64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2604 | } |
| 2605 | return rhs_in_mem ? kX86Or32RM : kX86Or32RR; |
| 2606 | case Instruction::XOR_LONG: |
| 2607 | case Instruction::XOR_LONG_2ADDR: |
| 2608 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2609 | return is64Bit ? kX86Xor64MR : kX86Xor32MR; |
| 2610 | } |
| 2611 | if (is64Bit) { |
| 2612 | return rhs_in_mem ? kX86Xor64RM : kX86Xor64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2613 | } |
| 2614 | return rhs_in_mem ? kX86Xor32RM : kX86Xor32RR; |
| 2615 | default: |
| 2616 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 2617 | return kX86Add32RR; |
| 2618 | } |
| 2619 | } |
| 2620 | |
| 2621 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, |
| 2622 | int32_t value) { |
| 2623 | bool in_mem = loc.location != kLocPhysReg; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2624 | bool is64Bit = cu_->target64; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2625 | bool byte_imm = IS_SIMM8(value); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2626 | DCHECK(in_mem || !loc.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2627 | switch (op) { |
| 2628 | case Instruction::ADD_LONG: |
| 2629 | case Instruction::ADD_LONG_2ADDR: |
| 2630 | if (byte_imm) { |
| 2631 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2632 | return is64Bit ? kX86Add64MI8 : is_high_op ? kX86Adc32MI8 : kX86Add32MI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2633 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2634 | return is64Bit ? kX86Add64RI8 : is_high_op ? kX86Adc32RI8 : kX86Add32RI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2635 | } |
| 2636 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2637 | return is64Bit ? kX86Add64MI : is_high_op ? kX86Adc32MI : kX86Add32MI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2638 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2639 | return is64Bit ? kX86Add64RI : is_high_op ? kX86Adc32RI : kX86Add32RI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2640 | case Instruction::SUB_LONG: |
| 2641 | case Instruction::SUB_LONG_2ADDR: |
| 2642 | if (byte_imm) { |
| 2643 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2644 | return is64Bit ? kX86Sub64MI8 : is_high_op ? kX86Sbb32MI8 : kX86Sub32MI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2645 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2646 | return is64Bit ? kX86Sub64RI8 : is_high_op ? kX86Sbb32RI8 : kX86Sub32RI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2647 | } |
| 2648 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2649 | return is64Bit ? kX86Sub64MI : is_high_op ? kX86Sbb32MI : kX86Sub32MI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2650 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2651 | return is64Bit ? kX86Sub64RI : is_high_op ? kX86Sbb32RI : kX86Sub32RI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2652 | case Instruction::AND_LONG_2ADDR: |
| 2653 | case Instruction::AND_LONG: |
| 2654 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2655 | if (is64Bit) { |
| 2656 | return in_mem ? kX86And64MI8 : kX86And64RI8; |
| 2657 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2658 | return in_mem ? kX86And32MI8 : kX86And32RI8; |
| 2659 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2660 | if (is64Bit) { |
| 2661 | return in_mem ? kX86And64MI : kX86And64RI; |
| 2662 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2663 | return in_mem ? kX86And32MI : kX86And32RI; |
| 2664 | case Instruction::OR_LONG: |
| 2665 | case Instruction::OR_LONG_2ADDR: |
| 2666 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2667 | if (is64Bit) { |
| 2668 | return in_mem ? kX86Or64MI8 : kX86Or64RI8; |
| 2669 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2670 | return in_mem ? kX86Or32MI8 : kX86Or32RI8; |
| 2671 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2672 | if (is64Bit) { |
| 2673 | return in_mem ? kX86Or64MI : kX86Or64RI; |
| 2674 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2675 | return in_mem ? kX86Or32MI : kX86Or32RI; |
| 2676 | case Instruction::XOR_LONG: |
| 2677 | case Instruction::XOR_LONG_2ADDR: |
| 2678 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2679 | if (is64Bit) { |
| 2680 | return in_mem ? kX86Xor64MI8 : kX86Xor64RI8; |
| 2681 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2682 | return in_mem ? kX86Xor32MI8 : kX86Xor32RI8; |
| 2683 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2684 | if (is64Bit) { |
| 2685 | return in_mem ? kX86Xor64MI : kX86Xor64RI; |
| 2686 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2687 | return in_mem ? kX86Xor32MI : kX86Xor32RI; |
| 2688 | default: |
| 2689 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 2690 | return kX86Add32MI; |
| 2691 | } |
| 2692 | } |
| 2693 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2694 | bool X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2695 | DCHECK(rl_src.is_const); |
| 2696 | int64_t val = mir_graph_->ConstantValueWide(rl_src); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2697 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2698 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2699 | // We can do with imm only if it fits 32 bit |
| 2700 | if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { |
| 2701 | return false; |
| 2702 | } |
| 2703 | |
| 2704 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 2705 | |
| 2706 | if ((rl_dest.location == kLocDalvikFrame) || |
| 2707 | (rl_dest.location == kLocCompilerTemp)) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2708 | int r_base = rs_rX86_SP.GetReg(); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2709 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 2710 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2711 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2712 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val); |
| 2713 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); |
| 2714 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 2715 | true /* is_load */, true /* is64bit */); |
| 2716 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 2717 | false /* is_load */, true /* is64bit */); |
| 2718 | return true; |
| 2719 | } |
| 2720 | |
| 2721 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2722 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
| 2723 | DCHECK(!rl_result.reg.IsFloat()); |
| 2724 | |
| 2725 | X86OpCode x86op = GetOpcode(op, rl_result, false, val); |
| 2726 | NewLIR2(x86op, rl_result.reg.GetReg(), val); |
| 2727 | |
| 2728 | StoreValueWide(rl_dest, rl_result); |
| 2729 | return true; |
| 2730 | } |
| 2731 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2732 | int32_t val_lo = Low32Bits(val); |
| 2733 | int32_t val_hi = High32Bits(val); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 2734 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2735 | |
| 2736 | // Can we just do this into memory? |
| 2737 | if ((rl_dest.location == kLocDalvikFrame) || |
| 2738 | (rl_dest.location == kLocCompilerTemp)) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2739 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2740 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 2741 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2742 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2743 | if (!IsNoOp(op, val_lo)) { |
| 2744 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2745 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2746 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 2747 | true /* is_load */, true /* is64bit */); |
| 2748 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2749 | false /* is_load */, true /* is64bit */); |
| 2750 | } |
| 2751 | if (!IsNoOp(op, val_hi)) { |
| 2752 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2753 | LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2754 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 2755 | true /* is_load */, true /* is64bit */); |
| 2756 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2757 | false /* is_load */, true /* is64bit */); |
| 2758 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2759 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2760 | } |
| 2761 | |
| 2762 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2763 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2764 | DCHECK(!rl_result.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2765 | |
| 2766 | if (!IsNoOp(op, val_lo)) { |
| 2767 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2768 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2769 | } |
| 2770 | if (!IsNoOp(op, val_hi)) { |
| 2771 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2772 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2773 | } |
| 2774 | StoreValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2775 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2776 | } |
| 2777 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2778 | bool X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2779 | RegLocation rl_src2, Instruction::Code op) { |
| 2780 | DCHECK(rl_src2.is_const); |
| 2781 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2782 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2783 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2784 | // We can do with imm only if it fits 32 bit |
| 2785 | if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { |
| 2786 | return false; |
| 2787 | } |
| 2788 | if (rl_dest.location == kLocPhysReg && |
| 2789 | rl_src1.location == kLocPhysReg && !rl_dest.reg.IsFloat()) { |
| 2790 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val); |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 2791 | OpRegCopy(rl_dest.reg, rl_src1.reg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2792 | NewLIR2(x86op, rl_dest.reg.GetReg(), val); |
| 2793 | StoreFinalValueWide(rl_dest, rl_dest); |
| 2794 | return true; |
| 2795 | } |
| 2796 | |
| 2797 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 2798 | // We need the values to be in a temporary |
| 2799 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 2800 | |
| 2801 | X86OpCode x86op = GetOpcode(op, rl_result, false, val); |
| 2802 | NewLIR2(x86op, rl_result.reg.GetReg(), val); |
| 2803 | |
| 2804 | StoreFinalValueWide(rl_dest, rl_result); |
| 2805 | return true; |
| 2806 | } |
| 2807 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2808 | int32_t val_lo = Low32Bits(val); |
| 2809 | int32_t val_hi = High32Bits(val); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 2810 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 2811 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2812 | |
| 2813 | // Can we do this directly into the destination registers? |
| 2814 | if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg && |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2815 | rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() && |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2816 | rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2817 | if (!IsNoOp(op, val_lo)) { |
| 2818 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2819 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2820 | } |
| 2821 | if (!IsNoOp(op, val_hi)) { |
| 2822 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2823 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2824 | } |
Maxim Kazantsev | 653f2bf | 2014-02-13 15:11:17 +0700 | [diff] [blame] | 2825 | |
| 2826 | StoreFinalValueWide(rl_dest, rl_dest); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2827 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2828 | } |
| 2829 | |
| 2830 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 2831 | DCHECK_EQ(rl_src1.location, kLocPhysReg); |
| 2832 | |
| 2833 | // We need the values to be in a temporary |
| 2834 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 2835 | if (!IsNoOp(op, val_lo)) { |
| 2836 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2837 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2838 | } |
| 2839 | if (!IsNoOp(op, val_hi)) { |
| 2840 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2841 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2842 | } |
| 2843 | |
| 2844 | StoreFinalValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2845 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2846 | } |
| 2847 | |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2848 | // For final classes there are no sub-classes to check and so we can answer the instance-of |
| 2849 | // question with simple comparisons. Use compares to memory and SETEQ to optimize for x86. |
| 2850 | void X86Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, |
| 2851 | RegLocation rl_dest, RegLocation rl_src) { |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2852 | RegLocation object = LoadValue(rl_src, kRefReg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2853 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2854 | RegStorage result_reg = rl_result.reg; |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2855 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 2856 | // For 32-bit, SETcc only works with EAX..EDX. |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2857 | RegStorage object_32reg = object.reg.Is64Bit() ? As32BitReg(object.reg) : object.reg; |
Dmitry Petrochenko | 407f5c1 | 2014-07-01 01:21:38 +0700 | [diff] [blame] | 2858 | if (result_reg.GetRegNum() == object_32reg.GetRegNum() || !IsByteRegister(result_reg)) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2859 | result_reg = AllocateByteRegister(); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2860 | } |
| 2861 | |
| 2862 | // Assume that there is no match. |
| 2863 | LoadConstant(result_reg, 0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2864 | LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2865 | |
Mark Mendell | ade54a2 | 2014-06-09 12:49:55 -0400 | [diff] [blame] | 2866 | // We will use this register to compare to memory below. |
| 2867 | // References are 32 bit in memory, and 64 bit in registers (in 64 bit mode). |
| 2868 | // For this reason, force allocation of a 32 bit register to use, so that the |
| 2869 | // compare to memory will be done using a 32 bit comparision. |
| 2870 | // The LoadRefDisp(s) below will work normally, even in 64 bit mode. |
| 2871 | RegStorage check_class = AllocTemp(); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2872 | |
| 2873 | // If Method* is already in a register, we can save a copy. |
| 2874 | RegLocation rl_method = mir_graph_->GetMethodLoc(); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2875 | int32_t offset_of_type = mirror::Array::DataOffset( |
| 2876 | sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + |
| 2877 | (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2878 | |
| 2879 | if (rl_method.location == kLocPhysReg) { |
| 2880 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2881 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2882 | check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2883 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2884 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2885 | check_class, kNotVolatile); |
| 2886 | LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2887 | } |
| 2888 | } else { |
| 2889 | LoadCurrMethodDirect(check_class); |
| 2890 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2891 | LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2892 | check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2893 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2894 | LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2895 | check_class, kNotVolatile); |
| 2896 | LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2897 | } |
| 2898 | } |
| 2899 | |
| 2900 | // Compare the computed class to the class in the object. |
| 2901 | DCHECK_EQ(object.location, kLocPhysReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2902 | OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value()); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2903 | |
| 2904 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2905 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2906 | |
| 2907 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 2908 | null_branchover->target = target; |
| 2909 | FreeTemp(check_class); |
| 2910 | if (IsTemp(result_reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2911 | OpRegCopy(rl_result.reg, result_reg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2912 | FreeTemp(result_reg); |
| 2913 | } |
| 2914 | StoreValue(rl_dest, rl_result); |
| 2915 | } |
| 2916 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2917 | void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 2918 | RegLocation rl_lhs, RegLocation rl_rhs, int flags) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2919 | OpKind op = kOpBkpt; |
| 2920 | bool is_div_rem = false; |
| 2921 | bool unary = false; |
| 2922 | bool shift_op = false; |
| 2923 | bool is_two_addr = false; |
| 2924 | RegLocation rl_result; |
| 2925 | switch (opcode) { |
| 2926 | case Instruction::NEG_INT: |
| 2927 | op = kOpNeg; |
| 2928 | unary = true; |
| 2929 | break; |
| 2930 | case Instruction::NOT_INT: |
| 2931 | op = kOpMvn; |
| 2932 | unary = true; |
| 2933 | break; |
| 2934 | case Instruction::ADD_INT_2ADDR: |
| 2935 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2936 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2937 | case Instruction::ADD_INT: |
| 2938 | op = kOpAdd; |
| 2939 | break; |
| 2940 | case Instruction::SUB_INT_2ADDR: |
| 2941 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2942 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2943 | case Instruction::SUB_INT: |
| 2944 | op = kOpSub; |
| 2945 | break; |
| 2946 | case Instruction::MUL_INT_2ADDR: |
| 2947 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2948 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2949 | case Instruction::MUL_INT: |
| 2950 | op = kOpMul; |
| 2951 | break; |
| 2952 | case Instruction::DIV_INT_2ADDR: |
| 2953 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2954 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2955 | case Instruction::DIV_INT: |
| 2956 | op = kOpDiv; |
| 2957 | is_div_rem = true; |
| 2958 | break; |
| 2959 | /* NOTE: returns in kArg1 */ |
| 2960 | case Instruction::REM_INT_2ADDR: |
| 2961 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2962 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2963 | case Instruction::REM_INT: |
| 2964 | op = kOpRem; |
| 2965 | is_div_rem = true; |
| 2966 | break; |
| 2967 | case Instruction::AND_INT_2ADDR: |
| 2968 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2969 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2970 | case Instruction::AND_INT: |
| 2971 | op = kOpAnd; |
| 2972 | break; |
| 2973 | case Instruction::OR_INT_2ADDR: |
| 2974 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2975 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2976 | case Instruction::OR_INT: |
| 2977 | op = kOpOr; |
| 2978 | break; |
| 2979 | case Instruction::XOR_INT_2ADDR: |
| 2980 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2981 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2982 | case Instruction::XOR_INT: |
| 2983 | op = kOpXor; |
| 2984 | break; |
| 2985 | case Instruction::SHL_INT_2ADDR: |
| 2986 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2987 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2988 | case Instruction::SHL_INT: |
| 2989 | shift_op = true; |
| 2990 | op = kOpLsl; |
| 2991 | break; |
| 2992 | case Instruction::SHR_INT_2ADDR: |
| 2993 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 2994 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2995 | case Instruction::SHR_INT: |
| 2996 | shift_op = true; |
| 2997 | op = kOpAsr; |
| 2998 | break; |
| 2999 | case Instruction::USHR_INT_2ADDR: |
| 3000 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3001 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3002 | case Instruction::USHR_INT: |
| 3003 | shift_op = true; |
| 3004 | op = kOpLsr; |
| 3005 | break; |
| 3006 | default: |
| 3007 | LOG(FATAL) << "Invalid word arith op: " << opcode; |
| 3008 | } |
| 3009 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 3010 | // Can we convert to a two address instruction? |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3011 | if (!is_two_addr && |
| 3012 | (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 3013 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 3014 | is_two_addr = true; |
| 3015 | } |
| 3016 | |
| 3017 | if (!GenerateTwoOperandInstructions()) { |
| 3018 | is_two_addr = false; |
| 3019 | } |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3020 | |
| 3021 | // Get the div/rem stuff out of the way. |
| 3022 | if (is_div_rem) { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 3023 | rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, flags); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3024 | StoreValue(rl_dest, rl_result); |
| 3025 | return; |
| 3026 | } |
| 3027 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3028 | // If we generate any memory access below, it will reference a dalvik reg. |
| 3029 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 3030 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3031 | if (unary) { |
| 3032 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3033 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3034 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3035 | OpRegReg(op, rl_result.reg, rl_lhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3036 | } else { |
| 3037 | if (shift_op) { |
| 3038 | // X86 doesn't require masking and must use ECX. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 3039 | RegStorage t_reg = TargetReg(kCount, kNotWide); // rCX |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3040 | LoadValueDirectFixed(rl_rhs, t_reg); |
| 3041 | if (is_two_addr) { |
| 3042 | // Can we do this directly into memory? |
Serguei Katkov | a464466 | 2014-09-08 12:42:27 +0700 | [diff] [blame] | 3043 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3044 | if (rl_result.location != kLocPhysReg) { |
| 3045 | // Okay, we can do this into memory |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3046 | OpMemReg(op, rl_result, t_reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3047 | FreeTemp(t_reg); |
| 3048 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3049 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3050 | // Can do this directly into the result register |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3051 | OpRegReg(op, rl_result.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3052 | FreeTemp(t_reg); |
| 3053 | StoreFinalValue(rl_dest, rl_result); |
| 3054 | return; |
| 3055 | } |
| 3056 | } |
| 3057 | // Three address form, or we can't do directly. |
| 3058 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3059 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3060 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3061 | FreeTemp(t_reg); |
| 3062 | } else { |
| 3063 | // Multiply is 3 operand only (sort of). |
| 3064 | if (is_two_addr && op != kOpMul) { |
| 3065 | // Can we do this directly into memory? |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3066 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3067 | if (rl_result.location == kLocPhysReg) { |
Serguei Katkov | 366f8ae | 2014-04-15 16:55:26 +0700 | [diff] [blame] | 3068 | // Ensure res is in a core reg |
| 3069 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3070 | // Can we do this from memory directly? |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3071 | rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3072 | if (rl_rhs.location != kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3073 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3074 | StoreFinalValue(rl_dest, rl_result); |
| 3075 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3076 | } else if (!rl_rhs.reg.IsFloat()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3077 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3078 | StoreFinalValue(rl_dest, rl_result); |
| 3079 | return; |
| 3080 | } |
| 3081 | } |
| 3082 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
Serguei Katkov | d293fb4 | 2014-05-19 15:45:42 +0700 | [diff] [blame] | 3083 | // It might happen rl_rhs and rl_dest are the same VR |
| 3084 | // in this case rl_dest is in reg after LoadValue while |
| 3085 | // rl_result is not updated yet, so do this |
| 3086 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3087 | if (rl_result.location != kLocPhysReg) { |
| 3088 | // Okay, we can do this into memory. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 3089 | OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3090 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3091 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3092 | // Can do this directly into the result register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3093 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3094 | StoreFinalValue(rl_dest, rl_result); |
| 3095 | return; |
| 3096 | } else { |
| 3097 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3098 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3099 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3100 | } |
| 3101 | } else { |
| 3102 | // Try to use reg/memory instructions. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3103 | rl_lhs = UpdateLocTyped(rl_lhs, kCoreReg); |
| 3104 | rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3105 | // We can't optimize with FP registers. |
| 3106 | if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) { |
| 3107 | // Something is difficult, so fall back to the standard case. |
| 3108 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3109 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3110 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3111 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3112 | } else { |
| 3113 | // We can optimize by moving to result and using memory operands. |
| 3114 | if (rl_rhs.location != kLocPhysReg) { |
| 3115 | // Force LHS into result. |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3116 | // We should be careful with order here |
| 3117 | // If rl_dest and rl_lhs points to the same VR we should load first |
| 3118 | // If the are different we should find a register first for dest |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3119 | if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 3120 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3121 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3122 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 3123 | // No-op if these are the same. |
| 3124 | OpRegCopy(rl_result.reg, rl_lhs.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3125 | } else { |
| 3126 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3127 | LoadValueDirect(rl_lhs, rl_result.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3128 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3129 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3130 | } else if (rl_lhs.location != kLocPhysReg) { |
| 3131 | // RHS is in a register; LHS is in memory. |
| 3132 | if (op != kOpSub) { |
| 3133 | // Force RHS into result and operate on memory. |
| 3134 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3135 | OpRegCopy(rl_result.reg, rl_rhs.reg); |
| 3136 | OpRegMem(op, rl_result.reg, rl_lhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3137 | } else { |
| 3138 | // Subtraction isn't commutative. |
| 3139 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3140 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3141 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3142 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3143 | } |
| 3144 | } else { |
| 3145 | // Both are in registers. |
| 3146 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3147 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3148 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3149 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3150 | } |
| 3151 | } |
| 3152 | } |
| 3153 | } |
| 3154 | } |
| 3155 | StoreValue(rl_dest, rl_result); |
| 3156 | } |
| 3157 | |
| 3158 | bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) { |
| 3159 | // If we have non-core registers, then we can't do good things. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3160 | if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3161 | return false; |
| 3162 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3163 | if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3164 | return false; |
| 3165 | } |
| 3166 | |
| 3167 | // Everything will be fine :-). |
| 3168 | return true; |
| 3169 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3170 | |
| 3171 | void X86Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 3172 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3173 | Mir2Lir::GenIntToLong(rl_dest, rl_src); |
| 3174 | return; |
| 3175 | } |
Serguei Katkov | e63d9d4 | 2014-06-25 00:25:35 +0700 | [diff] [blame] | 3176 | rl_src = UpdateLocTyped(rl_src, kCoreReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3177 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 3178 | if (rl_src.location == kLocPhysReg) { |
| 3179 | NewLIR2(kX86MovsxdRR, rl_result.reg.GetReg(), rl_src.reg.GetReg()); |
| 3180 | } else { |
| 3181 | int displacement = SRegOffset(rl_src.s_reg_low); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3182 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3183 | LIR *m = NewLIR3(kX86MovsxdRM, rl_result.reg.GetReg(), rs_rX86_SP.GetReg(), |
| 3184 | displacement + LOWORD_OFFSET); |
| 3185 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 3186 | true /* is_load */, true /* is_64bit */); |
| 3187 | } |
| 3188 | StoreValueWide(rl_dest, rl_result); |
| 3189 | } |
| 3190 | |
| 3191 | void X86Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 3192 | RegLocation rl_src1, RegLocation rl_shift) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 3193 | if (!cu_->target64) { |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 3194 | // Long shift operations in 32-bit. Use shld or shrd to create a 32-bit register filled from |
| 3195 | // the other half, shift the other half, if the shift amount is less than 32 we're done, |
| 3196 | // otherwise move one register to the other and place zero or sign bits in the other. |
| 3197 | LIR* branch; |
| 3198 | FlushAllRegs(); |
| 3199 | LockCallTemps(); |
| 3200 | LoadValueDirectFixed(rl_shift, rs_rCX); |
| 3201 | RegStorage r_tmp = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 3202 | LoadValueDirectWideFixed(rl_src1, r_tmp); |
| 3203 | switch (opcode) { |
| 3204 | case Instruction::SHL_LONG: |
| 3205 | case Instruction::SHL_LONG_2ADDR: |
| 3206 | NewLIR3(kX86Shld32RRC, r_tmp.GetHighReg(), r_tmp.GetLowReg(), rs_rCX.GetReg()); |
| 3207 | NewLIR2(kX86Sal32RC, r_tmp.GetLowReg(), rs_rCX.GetReg()); |
| 3208 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3209 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3210 | OpRegCopy(r_tmp.GetHigh(), r_tmp.GetLow()); |
| 3211 | LoadConstant(r_tmp.GetLow(), 0); |
| 3212 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3213 | break; |
| 3214 | case Instruction::SHR_LONG: |
| 3215 | case Instruction::SHR_LONG_2ADDR: |
| 3216 | NewLIR3(kX86Shrd32RRC, r_tmp.GetLowReg(), r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3217 | NewLIR2(kX86Sar32RC, r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3218 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3219 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3220 | OpRegCopy(r_tmp.GetLow(), r_tmp.GetHigh()); |
| 3221 | NewLIR2(kX86Sar32RI, r_tmp.GetHighReg(), 31); |
| 3222 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3223 | break; |
| 3224 | case Instruction::USHR_LONG: |
| 3225 | case Instruction::USHR_LONG_2ADDR: |
| 3226 | NewLIR3(kX86Shrd32RRC, r_tmp.GetLowReg(), r_tmp.GetHighReg(), |
| 3227 | rs_rCX.GetReg()); |
| 3228 | NewLIR2(kX86Shr32RC, r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3229 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3230 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3231 | OpRegCopy(r_tmp.GetLow(), r_tmp.GetHigh()); |
| 3232 | LoadConstant(r_tmp.GetHigh(), 0); |
| 3233 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3234 | break; |
| 3235 | default: |
| 3236 | LOG(FATAL) << "Unexpected case: " << opcode; |
| 3237 | return; |
| 3238 | } |
| 3239 | RegLocation rl_result = LocCReturnWide(); |
| 3240 | StoreValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3241 | return; |
| 3242 | } |
| 3243 | |
| 3244 | bool is_two_addr = false; |
| 3245 | OpKind op = kOpBkpt; |
| 3246 | RegLocation rl_result; |
| 3247 | |
| 3248 | switch (opcode) { |
| 3249 | case Instruction::SHL_LONG_2ADDR: |
| 3250 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3251 | FALLTHROUGH_INTENDED; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3252 | case Instruction::SHL_LONG: |
| 3253 | op = kOpLsl; |
| 3254 | break; |
| 3255 | case Instruction::SHR_LONG_2ADDR: |
| 3256 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3257 | FALLTHROUGH_INTENDED; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3258 | case Instruction::SHR_LONG: |
| 3259 | op = kOpAsr; |
| 3260 | break; |
| 3261 | case Instruction::USHR_LONG_2ADDR: |
| 3262 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3263 | FALLTHROUGH_INTENDED; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3264 | case Instruction::USHR_LONG: |
| 3265 | op = kOpLsr; |
| 3266 | break; |
| 3267 | default: |
| 3268 | op = kOpBkpt; |
| 3269 | } |
| 3270 | |
| 3271 | // X86 doesn't require masking and must use ECX. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 3272 | RegStorage t_reg = TargetReg(kCount, kNotWide); // rCX |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3273 | LoadValueDirectFixed(rl_shift, t_reg); |
| 3274 | if (is_two_addr) { |
| 3275 | // Can we do this directly into memory? |
| 3276 | rl_result = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 3277 | if (rl_result.location != kLocPhysReg) { |
| 3278 | // Okay, we can do this into memory |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3279 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3280 | OpMemReg(op, rl_result, t_reg.GetReg()); |
| 3281 | } else if (!rl_result.reg.IsFloat()) { |
| 3282 | // Can do this directly into the result register |
| 3283 | OpRegReg(op, rl_result.reg, t_reg); |
| 3284 | StoreFinalValueWide(rl_dest, rl_result); |
| 3285 | } |
| 3286 | } else { |
| 3287 | // Three address form, or we can't do directly. |
| 3288 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 3289 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 3290 | OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); |
| 3291 | StoreFinalValueWide(rl_dest, rl_result); |
| 3292 | } |
| 3293 | |
| 3294 | FreeTemp(t_reg); |
| 3295 | } |
| 3296 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 3297 | } // namespace art |