Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_x86.h" |
| 18 | #include "dex/quick/mir_to_lir-inl.h" |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame^] | 19 | #include "dex/dataflow_iterator-inl.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 20 | #include "x86_lir.h" |
| 21 | |
| 22 | namespace art { |
| 23 | |
| 24 | /* This file contains codegen for the X86 ISA */ |
| 25 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 26 | LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | int opcode; |
| 28 | /* must be both DOUBLE or both not DOUBLE */ |
| 29 | DCHECK_EQ(X86_DOUBLEREG(r_dest), X86_DOUBLEREG(r_src)); |
| 30 | if (X86_DOUBLEREG(r_dest)) { |
| 31 | opcode = kX86MovsdRR; |
| 32 | } else { |
| 33 | if (X86_SINGLEREG(r_dest)) { |
| 34 | if (X86_SINGLEREG(r_src)) { |
| 35 | opcode = kX86MovssRR; |
| 36 | } else { // Fpr <- Gpr |
| 37 | opcode = kX86MovdxrRR; |
| 38 | } |
| 39 | } else { // Gpr <- Fpr |
| 40 | DCHECK(X86_SINGLEREG(r_src)); |
| 41 | opcode = kX86MovdrxRR; |
| 42 | } |
| 43 | } |
| 44 | DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); |
| 45 | LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); |
| 46 | if (r_dest == r_src) { |
| 47 | res->flags.is_nop = true; |
| 48 | } |
| 49 | return res; |
| 50 | } |
| 51 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 52 | bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 53 | return true; |
| 54 | } |
| 55 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 56 | bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 57 | return false; |
| 58 | } |
| 59 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 60 | bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 61 | return true; |
| 62 | } |
| 63 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 64 | bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) { |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame^] | 65 | return value == 0; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | /* |
| 69 | * Load a immediate using a shortcut if possible; otherwise |
| 70 | * grab from the per-translation literal pool. If target is |
| 71 | * a high register, build constant into a low register and copy. |
| 72 | * |
| 73 | * No additional register clobbering operation performed. Use this version when |
| 74 | * 1) r_dest is freshly returned from AllocTemp or |
| 75 | * 2) The codegen is under fixed register usage |
| 76 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 77 | LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 78 | int r_dest_save = r_dest; |
| 79 | if (X86_FPREG(r_dest)) { |
| 80 | if (value == 0) { |
| 81 | return NewLIR2(kX86XorpsRR, r_dest, r_dest); |
| 82 | } |
| 83 | DCHECK(X86_SINGLEREG(r_dest)); |
| 84 | r_dest = AllocTemp(); |
| 85 | } |
| 86 | |
| 87 | LIR *res; |
| 88 | if (value == 0) { |
| 89 | res = NewLIR2(kX86Xor32RR, r_dest, r_dest); |
| 90 | } else { |
| 91 | // Note, there is no byte immediate form of a 32 bit immediate move. |
| 92 | res = NewLIR2(kX86Mov32RI, r_dest, value); |
| 93 | } |
| 94 | |
| 95 | if (X86_FPREG(r_dest_save)) { |
| 96 | NewLIR2(kX86MovdxrRR, r_dest_save, r_dest); |
| 97 | FreeTemp(r_dest); |
| 98 | } |
| 99 | |
| 100 | return res; |
| 101 | } |
| 102 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 103 | LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) { |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 104 | LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 105 | res->target = target; |
| 106 | return res; |
| 107 | } |
| 108 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 109 | LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 110 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */, |
| 111 | X86ConditionEncoding(cc)); |
| 112 | branch->target = target; |
| 113 | return branch; |
| 114 | } |
| 115 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 116 | LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 117 | X86OpCode opcode = kX86Bkpt; |
| 118 | switch (op) { |
| 119 | case kOpNeg: opcode = kX86Neg32R; break; |
| 120 | case kOpNot: opcode = kX86Not32R; break; |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 121 | case kOpRev: opcode = kX86Bswap32R; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 122 | case kOpBlx: opcode = kX86CallR; break; |
| 123 | default: |
| 124 | LOG(FATAL) << "Bad case in OpReg " << op; |
| 125 | } |
| 126 | return NewLIR1(opcode, r_dest_src); |
| 127 | } |
| 128 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 129 | LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 130 | X86OpCode opcode = kX86Bkpt; |
| 131 | bool byte_imm = IS_SIMM8(value); |
| 132 | DCHECK(!X86_FPREG(r_dest_src1)); |
| 133 | switch (op) { |
| 134 | case kOpLsl: opcode = kX86Sal32RI; break; |
| 135 | case kOpLsr: opcode = kX86Shr32RI; break; |
| 136 | case kOpAsr: opcode = kX86Sar32RI; break; |
| 137 | case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break; |
| 138 | case kOpOr: opcode = byte_imm ? kX86Or32RI8 : kX86Or32RI; break; |
| 139 | case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 140 | // case kOpSbb: opcode = kX86Sbb32RI; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 141 | case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break; |
| 142 | case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break; |
| 143 | case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break; |
| 144 | case kOpCmp: opcode = byte_imm ? kX86Cmp32RI8 : kX86Cmp32RI; break; |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 145 | case kOpMov: |
| 146 | /* |
| 147 | * Moving the constant zero into register can be specialized as an xor of the register. |
| 148 | * However, that sets eflags while the move does not. For that reason here, always do |
| 149 | * the move and if caller is flexible, they should be calling LoadConstantNoClobber instead. |
| 150 | */ |
| 151 | opcode = kX86Mov32RI; |
| 152 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 153 | case kOpMul: |
| 154 | opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI; |
| 155 | return NewLIR3(opcode, r_dest_src1, r_dest_src1, value); |
| 156 | default: |
| 157 | LOG(FATAL) << "Bad case in OpRegImm " << op; |
| 158 | } |
| 159 | return NewLIR2(opcode, r_dest_src1, value); |
| 160 | } |
| 161 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 162 | LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 163 | X86OpCode opcode = kX86Nop; |
| 164 | bool src2_must_be_cx = false; |
| 165 | switch (op) { |
| 166 | // X86 unary opcodes |
| 167 | case kOpMvn: |
| 168 | OpRegCopy(r_dest_src1, r_src2); |
| 169 | return OpReg(kOpNot, r_dest_src1); |
| 170 | case kOpNeg: |
| 171 | OpRegCopy(r_dest_src1, r_src2); |
| 172 | return OpReg(kOpNeg, r_dest_src1); |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 173 | case kOpRev: |
| 174 | OpRegCopy(r_dest_src1, r_src2); |
| 175 | return OpReg(kOpRev, r_dest_src1); |
| 176 | case kOpRevsh: |
| 177 | OpRegCopy(r_dest_src1, r_src2); |
| 178 | OpReg(kOpRev, r_dest_src1); |
| 179 | return OpRegImm(kOpAsr, r_dest_src1, 16); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 180 | // X86 binary opcodes |
| 181 | case kOpSub: opcode = kX86Sub32RR; break; |
| 182 | case kOpSbc: opcode = kX86Sbb32RR; break; |
| 183 | case kOpLsl: opcode = kX86Sal32RC; src2_must_be_cx = true; break; |
| 184 | case kOpLsr: opcode = kX86Shr32RC; src2_must_be_cx = true; break; |
| 185 | case kOpAsr: opcode = kX86Sar32RC; src2_must_be_cx = true; break; |
| 186 | case kOpMov: opcode = kX86Mov32RR; break; |
| 187 | case kOpCmp: opcode = kX86Cmp32RR; break; |
| 188 | case kOpAdd: opcode = kX86Add32RR; break; |
| 189 | case kOpAdc: opcode = kX86Adc32RR; break; |
| 190 | case kOpAnd: opcode = kX86And32RR; break; |
| 191 | case kOpOr: opcode = kX86Or32RR; break; |
| 192 | case kOpXor: opcode = kX86Xor32RR; break; |
| 193 | case kOp2Byte: |
| 194 | // Use shifts instead of a byte operand if the source can't be byte accessed. |
| 195 | if (r_src2 >= 4) { |
| 196 | NewLIR2(kX86Mov32RR, r_dest_src1, r_src2); |
| 197 | NewLIR2(kX86Sal32RI, r_dest_src1, 24); |
| 198 | return NewLIR2(kX86Sar32RI, r_dest_src1, 24); |
| 199 | } else { |
| 200 | opcode = kX86Movsx8RR; |
| 201 | } |
| 202 | break; |
| 203 | case kOp2Short: opcode = kX86Movsx16RR; break; |
| 204 | case kOp2Char: opcode = kX86Movzx16RR; break; |
| 205 | case kOpMul: opcode = kX86Imul32RR; break; |
| 206 | default: |
| 207 | LOG(FATAL) << "Bad case in OpRegReg " << op; |
| 208 | break; |
| 209 | } |
| 210 | CHECK(!src2_must_be_cx || r_src2 == rCX); |
| 211 | return NewLIR2(opcode, r_dest_src1, r_src2); |
| 212 | } |
| 213 | |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 214 | LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) { |
| 215 | // The only conditional reg to reg operation supported is Cmov |
| 216 | DCHECK_EQ(op, kOpCmov); |
| 217 | return NewLIR3(kX86Cmov32RRC, r_dest, r_src, X86ConditionEncoding(cc)); |
| 218 | } |
| 219 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 220 | LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 221 | int offset) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 222 | X86OpCode opcode = kX86Nop; |
| 223 | switch (op) { |
| 224 | // X86 binary opcodes |
| 225 | case kOpSub: opcode = kX86Sub32RM; break; |
| 226 | case kOpMov: opcode = kX86Mov32RM; break; |
| 227 | case kOpCmp: opcode = kX86Cmp32RM; break; |
| 228 | case kOpAdd: opcode = kX86Add32RM; break; |
| 229 | case kOpAnd: opcode = kX86And32RM; break; |
| 230 | case kOpOr: opcode = kX86Or32RM; break; |
| 231 | case kOpXor: opcode = kX86Xor32RM; break; |
| 232 | case kOp2Byte: opcode = kX86Movsx8RM; break; |
| 233 | case kOp2Short: opcode = kX86Movsx16RM; break; |
| 234 | case kOp2Char: opcode = kX86Movzx16RM; break; |
| 235 | case kOpMul: |
| 236 | default: |
| 237 | LOG(FATAL) << "Bad case in OpRegMem " << op; |
| 238 | break; |
| 239 | } |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 240 | LIR *l = NewLIR3(opcode, r_dest, rBase, offset); |
| 241 | if (rBase == rX86_SP) { |
| 242 | AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */); |
| 243 | } |
| 244 | return l; |
| 245 | } |
| 246 | |
| 247 | LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) { |
| 248 | DCHECK_NE(rl_dest.location, kLocPhysReg); |
| 249 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 250 | X86OpCode opcode = kX86Nop; |
| 251 | switch (op) { |
| 252 | case kOpSub: opcode = kX86Sub32MR; break; |
| 253 | case kOpMov: opcode = kX86Mov32MR; break; |
| 254 | case kOpCmp: opcode = kX86Cmp32MR; break; |
| 255 | case kOpAdd: opcode = kX86Add32MR; break; |
| 256 | case kOpAnd: opcode = kX86And32MR; break; |
| 257 | case kOpOr: opcode = kX86Or32MR; break; |
| 258 | case kOpXor: opcode = kX86Xor32MR; break; |
| 259 | case kOpLsl: opcode = kX86Sal32MC; break; |
| 260 | case kOpLsr: opcode = kX86Shr32MC; break; |
| 261 | case kOpAsr: opcode = kX86Sar32MC; break; |
| 262 | default: |
| 263 | LOG(FATAL) << "Bad case in OpMemReg " << op; |
| 264 | break; |
| 265 | } |
| 266 | LIR *l = NewLIR3(opcode, rX86_SP, displacement, r_value); |
| 267 | AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, false /* is_64bit */); |
| 268 | return l; |
| 269 | } |
| 270 | |
| 271 | LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, RegLocation rl_value) { |
| 272 | DCHECK_NE(rl_value.location, kLocPhysReg); |
| 273 | int displacement = SRegOffset(rl_value.s_reg_low); |
| 274 | X86OpCode opcode = kX86Nop; |
| 275 | switch (op) { |
| 276 | case kOpSub: opcode = kX86Sub32RM; break; |
| 277 | case kOpMov: opcode = kX86Mov32RM; break; |
| 278 | case kOpCmp: opcode = kX86Cmp32RM; break; |
| 279 | case kOpAdd: opcode = kX86Add32RM; break; |
| 280 | case kOpAnd: opcode = kX86And32RM; break; |
| 281 | case kOpOr: opcode = kX86Or32RM; break; |
| 282 | case kOpXor: opcode = kX86Xor32RM; break; |
| 283 | case kOpMul: opcode = kX86Imul32RM; break; |
| 284 | default: |
| 285 | LOG(FATAL) << "Bad case in OpRegMem " << op; |
| 286 | break; |
| 287 | } |
| 288 | LIR *l = NewLIR3(opcode, r_dest, rX86_SP, displacement); |
| 289 | AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */); |
| 290 | return l; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 294 | int r_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 295 | if (r_dest != r_src1 && r_dest != r_src2) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 296 | if (op == kOpAdd) { // lea special case, except can't encode rbp as base |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 297 | if (r_src1 == r_src2) { |
| 298 | OpRegCopy(r_dest, r_src1); |
| 299 | return OpRegImm(kOpLsl, r_dest, 1); |
| 300 | } else if (r_src1 != rBP) { |
| 301 | return NewLIR5(kX86Lea32RA, r_dest, r_src1 /* base */, |
| 302 | r_src2 /* index */, 0 /* scale */, 0 /* disp */); |
| 303 | } else { |
| 304 | return NewLIR5(kX86Lea32RA, r_dest, r_src2 /* base */, |
| 305 | r_src1 /* index */, 0 /* scale */, 0 /* disp */); |
| 306 | } |
| 307 | } else { |
| 308 | OpRegCopy(r_dest, r_src1); |
| 309 | return OpRegReg(op, r_dest, r_src2); |
| 310 | } |
| 311 | } else if (r_dest == r_src1) { |
| 312 | return OpRegReg(op, r_dest, r_src2); |
| 313 | } else { // r_dest == r_src2 |
| 314 | switch (op) { |
| 315 | case kOpSub: // non-commutative |
| 316 | OpReg(kOpNeg, r_dest); |
| 317 | op = kOpAdd; |
| 318 | break; |
| 319 | case kOpSbc: |
| 320 | case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: { |
| 321 | int t_reg = AllocTemp(); |
| 322 | OpRegCopy(t_reg, r_src1); |
| 323 | OpRegReg(op, t_reg, r_src2); |
| 324 | LIR* res = OpRegCopy(r_dest, t_reg); |
| 325 | FreeTemp(t_reg); |
| 326 | return res; |
| 327 | } |
| 328 | case kOpAdd: // commutative |
| 329 | case kOpOr: |
| 330 | case kOpAdc: |
| 331 | case kOpAnd: |
| 332 | case kOpXor: |
| 333 | break; |
| 334 | default: |
| 335 | LOG(FATAL) << "Bad case in OpRegRegReg " << op; |
| 336 | } |
| 337 | return OpRegReg(op, r_dest, r_src1); |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 342 | int value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 343 | if (op == kOpMul) { |
| 344 | X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; |
| 345 | return NewLIR3(opcode, r_dest, r_src, value); |
| 346 | } else if (op == kOpAnd) { |
| 347 | if (value == 0xFF && r_src < 4) { |
| 348 | return NewLIR2(kX86Movzx8RR, r_dest, r_src); |
| 349 | } else if (value == 0xFFFF) { |
| 350 | return NewLIR2(kX86Movzx16RR, r_dest, r_src); |
| 351 | } |
| 352 | } |
| 353 | if (r_dest != r_src) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 354 | if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 355 | // TODO: fix bug in LEA encoding when disp == 0 |
| 356 | return NewLIR5(kX86Lea32RA, r_dest, r5sib_no_base /* base */, |
| 357 | r_src /* index */, value /* scale */, 0 /* disp */); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 358 | } else if (op == kOpAdd) { // lea add special case |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 359 | return NewLIR5(kX86Lea32RA, r_dest, r_src /* base */, |
| 360 | r4sib_no_index /* index */, 0 /* scale */, value /* disp */); |
| 361 | } |
| 362 | OpRegCopy(r_dest, r_src); |
| 363 | } |
| 364 | return OpRegImm(op, r_dest, value); |
| 365 | } |
| 366 | |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 367 | LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 368 | X86OpCode opcode = kX86Bkpt; |
| 369 | switch (op) { |
| 370 | case kOpBlx: opcode = kX86CallT; break; |
| 371 | default: |
| 372 | LOG(FATAL) << "Bad opcode: " << op; |
| 373 | break; |
| 374 | } |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 375 | return NewLIR1(opcode, thread_offset.Int32Value()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 376 | } |
| 377 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 378 | LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 379 | X86OpCode opcode = kX86Bkpt; |
| 380 | switch (op) { |
| 381 | case kOpBlx: opcode = kX86CallM; break; |
| 382 | default: |
| 383 | LOG(FATAL) << "Bad opcode: " << op; |
| 384 | break; |
| 385 | } |
| 386 | return NewLIR2(opcode, rBase, disp); |
| 387 | } |
| 388 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 389 | LIR* X86Mir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 390 | int32_t val_lo = Low32Bits(value); |
| 391 | int32_t val_hi = High32Bits(value); |
| 392 | LIR *res; |
| 393 | if (X86_FPREG(r_dest_lo)) { |
| 394 | DCHECK(X86_FPREG(r_dest_hi)); // ignore r_dest_hi |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 395 | DCHECK_EQ(r_dest_lo, r_dest_hi); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 396 | if (value == 0) { |
| 397 | return NewLIR2(kX86XorpsRR, r_dest_lo, r_dest_lo); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame^] | 398 | } else if (base_of_code_ != nullptr) { |
| 399 | // We will load the value from the literal area. |
| 400 | LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); |
| 401 | if (data_target == NULL) { |
| 402 | data_target = AddWideData(&literal_list_, val_lo, val_hi); |
| 403 | } |
| 404 | |
| 405 | // Address the start of the method |
| 406 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
| 407 | rl_method = LoadValue(rl_method, kCoreReg); |
| 408 | |
| 409 | // Load the proper value from the literal area. |
| 410 | // We don't know the proper offset for the value, so pick one that will force |
| 411 | // 4 byte offset. We will fix this up in the assembler later to have the right |
| 412 | // value. |
| 413 | res = LoadBaseDisp(rl_method.low_reg, 256 /* bogus */, r_dest_lo, kDouble, INVALID_SREG); |
| 414 | res->target = data_target; |
| 415 | res->flags.fixup = kFixupLoad; |
| 416 | SetMemRefType(res, true, kLiteral); |
| 417 | // Redo after we assign target to ensure size is correct. |
| 418 | SetupResourceMasks(res); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 419 | } else { |
| 420 | if (val_lo == 0) { |
| 421 | res = NewLIR2(kX86XorpsRR, r_dest_lo, r_dest_lo); |
| 422 | } else { |
| 423 | res = LoadConstantNoClobber(r_dest_lo, val_lo); |
| 424 | } |
| 425 | if (val_hi != 0) { |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 426 | r_dest_hi = AllocTempDouble(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 427 | LoadConstantNoClobber(r_dest_hi, val_hi); |
Razvan A Lupusoru | d3266bc | 2014-01-24 12:55:31 -0800 | [diff] [blame] | 428 | NewLIR2(kX86PunpckldqRR, r_dest_lo, r_dest_hi); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 429 | FreeTemp(r_dest_hi); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 430 | } |
| 431 | } |
| 432 | } else { |
| 433 | res = LoadConstantNoClobber(r_dest_lo, val_lo); |
| 434 | LoadConstantNoClobber(r_dest_hi, val_hi); |
| 435 | } |
| 436 | return res; |
| 437 | } |
| 438 | |
| 439 | LIR* X86Mir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, |
| 440 | int displacement, int r_dest, int r_dest_hi, OpSize size, |
| 441 | int s_reg) { |
| 442 | LIR *load = NULL; |
| 443 | LIR *load2 = NULL; |
| 444 | bool is_array = r_index != INVALID_REG; |
| 445 | bool pair = false; |
| 446 | bool is64bit = false; |
| 447 | X86OpCode opcode = kX86Nop; |
| 448 | switch (size) { |
| 449 | case kLong: |
| 450 | case kDouble: |
| 451 | is64bit = true; |
| 452 | if (X86_FPREG(r_dest)) { |
| 453 | opcode = is_array ? kX86MovsdRA : kX86MovsdRM; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 454 | } else { |
| 455 | pair = true; |
| 456 | opcode = is_array ? kX86Mov32RA : kX86Mov32RM; |
| 457 | } |
| 458 | // TODO: double store is to unaligned address |
| 459 | DCHECK_EQ((displacement & 0x3), 0); |
| 460 | break; |
| 461 | case kWord: |
| 462 | case kSingle: |
| 463 | opcode = is_array ? kX86Mov32RA : kX86Mov32RM; |
| 464 | if (X86_FPREG(r_dest)) { |
| 465 | opcode = is_array ? kX86MovssRA : kX86MovssRM; |
| 466 | DCHECK(X86_SINGLEREG(r_dest)); |
| 467 | } |
| 468 | DCHECK_EQ((displacement & 0x3), 0); |
| 469 | break; |
| 470 | case kUnsignedHalf: |
| 471 | opcode = is_array ? kX86Movzx16RA : kX86Movzx16RM; |
| 472 | DCHECK_EQ((displacement & 0x1), 0); |
| 473 | break; |
| 474 | case kSignedHalf: |
| 475 | opcode = is_array ? kX86Movsx16RA : kX86Movsx16RM; |
| 476 | DCHECK_EQ((displacement & 0x1), 0); |
| 477 | break; |
| 478 | case kUnsignedByte: |
| 479 | opcode = is_array ? kX86Movzx8RA : kX86Movzx8RM; |
| 480 | break; |
| 481 | case kSignedByte: |
| 482 | opcode = is_array ? kX86Movsx8RA : kX86Movsx8RM; |
| 483 | break; |
| 484 | default: |
| 485 | LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody"; |
| 486 | } |
| 487 | |
| 488 | if (!is_array) { |
| 489 | if (!pair) { |
| 490 | load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET); |
| 491 | } else { |
| 492 | if (rBase == r_dest) { |
| 493 | load2 = NewLIR3(opcode, r_dest_hi, rBase, |
| 494 | displacement + HIWORD_OFFSET); |
| 495 | load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET); |
| 496 | } else { |
| 497 | load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET); |
| 498 | load2 = NewLIR3(opcode, r_dest_hi, rBase, |
| 499 | displacement + HIWORD_OFFSET); |
| 500 | } |
| 501 | } |
| 502 | if (rBase == rX86_SP) { |
| 503 | AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, |
| 504 | true /* is_load */, is64bit); |
| 505 | if (pair) { |
| 506 | AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, |
| 507 | true /* is_load */, is64bit); |
| 508 | } |
| 509 | } |
| 510 | } else { |
| 511 | if (!pair) { |
| 512 | load = NewLIR5(opcode, r_dest, rBase, r_index, scale, |
| 513 | displacement + LOWORD_OFFSET); |
| 514 | } else { |
| 515 | if (rBase == r_dest) { |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 516 | if (r_dest_hi == r_index) { |
| 517 | // We can't use either register for the first load. |
| 518 | int temp = AllocTemp(); |
| 519 | load2 = NewLIR5(opcode, temp, rBase, r_index, scale, |
| 520 | displacement + HIWORD_OFFSET); |
| 521 | load = NewLIR5(opcode, r_dest, rBase, r_index, scale, |
| 522 | displacement + LOWORD_OFFSET); |
| 523 | OpRegCopy(r_dest_hi, temp); |
| 524 | FreeTemp(temp); |
| 525 | } else { |
| 526 | load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale, |
| 527 | displacement + HIWORD_OFFSET); |
| 528 | load = NewLIR5(opcode, r_dest, rBase, r_index, scale, |
| 529 | displacement + LOWORD_OFFSET); |
| 530 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 531 | } else { |
Mark Mendell | ae427c3 | 2014-01-24 09:17:22 -0800 | [diff] [blame] | 532 | if (r_dest == r_index) { |
| 533 | // We can't use either register for the first load. |
| 534 | int temp = AllocTemp(); |
| 535 | load = NewLIR5(opcode, temp, rBase, r_index, scale, |
| 536 | displacement + LOWORD_OFFSET); |
| 537 | load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale, |
| 538 | displacement + HIWORD_OFFSET); |
| 539 | OpRegCopy(r_dest, temp); |
| 540 | FreeTemp(temp); |
| 541 | } else { |
| 542 | load = NewLIR5(opcode, r_dest, rBase, r_index, scale, |
| 543 | displacement + LOWORD_OFFSET); |
| 544 | load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale, |
| 545 | displacement + HIWORD_OFFSET); |
| 546 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 547 | } |
| 548 | } |
| 549 | } |
| 550 | |
| 551 | return load; |
| 552 | } |
| 553 | |
| 554 | /* Load value from base + scaled index. */ |
| 555 | LIR* X86Mir2Lir::LoadBaseIndexed(int rBase, |
| 556 | int r_index, int r_dest, int scale, OpSize size) { |
| 557 | return LoadBaseIndexedDisp(rBase, r_index, scale, 0, |
| 558 | r_dest, INVALID_REG, size, INVALID_SREG); |
| 559 | } |
| 560 | |
| 561 | LIR* X86Mir2Lir::LoadBaseDisp(int rBase, int displacement, |
| 562 | int r_dest, OpSize size, int s_reg) { |
| 563 | return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement, |
| 564 | r_dest, INVALID_REG, size, s_reg); |
| 565 | } |
| 566 | |
| 567 | LIR* X86Mir2Lir::LoadBaseDispWide(int rBase, int displacement, |
| 568 | int r_dest_lo, int r_dest_hi, int s_reg) { |
| 569 | return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement, |
| 570 | r_dest_lo, r_dest_hi, kLong, s_reg); |
| 571 | } |
| 572 | |
| 573 | LIR* X86Mir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, |
| 574 | int displacement, int r_src, int r_src_hi, OpSize size, |
| 575 | int s_reg) { |
| 576 | LIR *store = NULL; |
| 577 | LIR *store2 = NULL; |
| 578 | bool is_array = r_index != INVALID_REG; |
| 579 | bool pair = false; |
| 580 | bool is64bit = false; |
| 581 | X86OpCode opcode = kX86Nop; |
| 582 | switch (size) { |
| 583 | case kLong: |
| 584 | case kDouble: |
| 585 | is64bit = true; |
| 586 | if (X86_FPREG(r_src)) { |
| 587 | opcode = is_array ? kX86MovsdAR : kX86MovsdMR; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 588 | } else { |
| 589 | pair = true; |
| 590 | opcode = is_array ? kX86Mov32AR : kX86Mov32MR; |
| 591 | } |
| 592 | // TODO: double store is to unaligned address |
| 593 | DCHECK_EQ((displacement & 0x3), 0); |
| 594 | break; |
| 595 | case kWord: |
| 596 | case kSingle: |
| 597 | opcode = is_array ? kX86Mov32AR : kX86Mov32MR; |
| 598 | if (X86_FPREG(r_src)) { |
| 599 | opcode = is_array ? kX86MovssAR : kX86MovssMR; |
| 600 | DCHECK(X86_SINGLEREG(r_src)); |
| 601 | } |
| 602 | DCHECK_EQ((displacement & 0x3), 0); |
| 603 | break; |
| 604 | case kUnsignedHalf: |
| 605 | case kSignedHalf: |
| 606 | opcode = is_array ? kX86Mov16AR : kX86Mov16MR; |
| 607 | DCHECK_EQ((displacement & 0x1), 0); |
| 608 | break; |
| 609 | case kUnsignedByte: |
| 610 | case kSignedByte: |
| 611 | opcode = is_array ? kX86Mov8AR : kX86Mov8MR; |
| 612 | break; |
| 613 | default: |
| 614 | LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody"; |
| 615 | } |
| 616 | |
| 617 | if (!is_array) { |
| 618 | if (!pair) { |
| 619 | store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src); |
| 620 | } else { |
| 621 | store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src); |
| 622 | store2 = NewLIR3(opcode, rBase, displacement + HIWORD_OFFSET, r_src_hi); |
| 623 | } |
| 624 | if (rBase == rX86_SP) { |
| 625 | AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, |
| 626 | false /* is_load */, is64bit); |
| 627 | if (pair) { |
| 628 | AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, |
| 629 | false /* is_load */, is64bit); |
| 630 | } |
| 631 | } |
| 632 | } else { |
| 633 | if (!pair) { |
| 634 | store = NewLIR5(opcode, rBase, r_index, scale, |
| 635 | displacement + LOWORD_OFFSET, r_src); |
| 636 | } else { |
| 637 | store = NewLIR5(opcode, rBase, r_index, scale, |
| 638 | displacement + LOWORD_OFFSET, r_src); |
| 639 | store2 = NewLIR5(opcode, rBase, r_index, scale, |
| 640 | displacement + HIWORD_OFFSET, r_src_hi); |
| 641 | } |
| 642 | } |
| 643 | |
| 644 | return store; |
| 645 | } |
| 646 | |
| 647 | /* store value base base + scaled index. */ |
| 648 | LIR* X86Mir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 649 | int scale, OpSize size) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 650 | return StoreBaseIndexedDisp(rBase, r_index, scale, 0, |
| 651 | r_src, INVALID_REG, size, INVALID_SREG); |
| 652 | } |
| 653 | |
| 654 | LIR* X86Mir2Lir::StoreBaseDisp(int rBase, int displacement, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 655 | int r_src, OpSize size) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 656 | return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, |
| 657 | displacement, r_src, INVALID_REG, size, |
| 658 | INVALID_SREG); |
| 659 | } |
| 660 | |
| 661 | LIR* X86Mir2Lir::StoreBaseDispWide(int rBase, int displacement, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 662 | int r_src_lo, int r_src_hi) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 663 | return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, displacement, |
| 664 | r_src_lo, r_src_hi, kLong, INVALID_SREG); |
| 665 | } |
| 666 | |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 667 | /* |
| 668 | * Copy a long value in Core registers to an XMM register |
| 669 | * |
| 670 | */ |
| 671 | void X86Mir2Lir::OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg) { |
| 672 | NewLIR2(kX86MovdxrRR, fp_reg, low_reg); |
| 673 | int tmp_reg = AllocTempDouble(); |
| 674 | NewLIR2(kX86MovdxrRR, tmp_reg, high_reg); |
Razvan A Lupusoru | d3266bc | 2014-01-24 12:55:31 -0800 | [diff] [blame] | 675 | NewLIR2(kX86PunpckldqRR, fp_reg, tmp_reg); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 676 | FreeTemp(tmp_reg); |
| 677 | } |
| 678 | |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 679 | LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg, |
| 680 | int offset, int check_value, LIR* target) { |
| 681 | NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg, offset, |
| 682 | check_value); |
| 683 | LIR* branch = OpCondBranch(cond, target); |
| 684 | return branch; |
| 685 | } |
| 686 | |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame^] | 687 | void X86Mir2Lir::AnalyzeMIR() { |
| 688 | // Assume we don't need a pointer to the base of the code. |
| 689 | cu_->NewTimingSplit("X86 MIR Analysis"); |
| 690 | store_method_addr_ = false; |
| 691 | |
| 692 | // Walk the MIR looking for interesting items. |
| 693 | PreOrderDfsIterator iter(mir_graph_); |
| 694 | BasicBlock* curr_bb = iter.Next(); |
| 695 | while (curr_bb != NULL) { |
| 696 | AnalyzeBB(curr_bb); |
| 697 | curr_bb = iter.Next(); |
| 698 | } |
| 699 | |
| 700 | // Did we need a pointer to the method code? |
| 701 | if (store_method_addr_) { |
| 702 | base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempVR, false); |
| 703 | } else { |
| 704 | base_of_code_ = nullptr; |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | void X86Mir2Lir::AnalyzeBB(BasicBlock * bb) { |
| 709 | if (bb->block_type == kDead) { |
| 710 | // Ignore dead blocks |
| 711 | return; |
| 712 | } |
| 713 | |
| 714 | for (MIR *mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { |
| 715 | int opcode = mir->dalvikInsn.opcode; |
| 716 | if (opcode >= kMirOpFirst) { |
| 717 | AnalyzeExtendedMIR(opcode, bb, mir); |
| 718 | } else { |
| 719 | AnalyzeMIR(opcode, bb, mir); |
| 720 | } |
| 721 | } |
| 722 | } |
| 723 | |
| 724 | |
| 725 | void X86Mir2Lir::AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) { |
| 726 | switch (opcode) { |
| 727 | // Instructions referencing doubles. |
| 728 | case kMirOpFusedCmplDouble: |
| 729 | case kMirOpFusedCmpgDouble: |
| 730 | AnalyzeFPInstruction(opcode, bb, mir); |
| 731 | break; |
| 732 | default: |
| 733 | // Ignore the rest. |
| 734 | break; |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | void X86Mir2Lir::AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) { |
| 739 | // Looking for |
| 740 | // - Do we need a pointer to the code (used for packed switches and double lits)? |
| 741 | |
| 742 | switch (opcode) { |
| 743 | // Instructions referencing doubles. |
| 744 | case Instruction::CMPL_DOUBLE: |
| 745 | case Instruction::CMPG_DOUBLE: |
| 746 | case Instruction::NEG_DOUBLE: |
| 747 | case Instruction::ADD_DOUBLE: |
| 748 | case Instruction::SUB_DOUBLE: |
| 749 | case Instruction::MUL_DOUBLE: |
| 750 | case Instruction::DIV_DOUBLE: |
| 751 | case Instruction::REM_DOUBLE: |
| 752 | case Instruction::ADD_DOUBLE_2ADDR: |
| 753 | case Instruction::SUB_DOUBLE_2ADDR: |
| 754 | case Instruction::MUL_DOUBLE_2ADDR: |
| 755 | case Instruction::DIV_DOUBLE_2ADDR: |
| 756 | case Instruction::REM_DOUBLE_2ADDR: |
| 757 | AnalyzeFPInstruction(opcode, bb, mir); |
| 758 | break; |
| 759 | // Packed switches and array fills need a pointer to the base of the method. |
| 760 | case Instruction::FILL_ARRAY_DATA: |
| 761 | case Instruction::PACKED_SWITCH: |
| 762 | store_method_addr_ = true; |
| 763 | break; |
| 764 | default: |
| 765 | // Other instructions are not interesting yet. |
| 766 | break; |
| 767 | } |
| 768 | } |
| 769 | |
| 770 | void X86Mir2Lir::AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) { |
| 771 | // Look at all the uses, and see if they are double constants. |
| 772 | uint64_t attrs = mir_graph_->oat_data_flow_attributes_[opcode]; |
| 773 | int next_sreg = 0; |
| 774 | if (attrs & DF_UA) { |
| 775 | if (attrs & DF_A_WIDE) { |
| 776 | AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); |
| 777 | next_sreg += 2; |
| 778 | } else { |
| 779 | next_sreg++; |
| 780 | } |
| 781 | } |
| 782 | if (attrs & DF_UB) { |
| 783 | if (attrs & DF_B_WIDE) { |
| 784 | AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); |
| 785 | next_sreg += 2; |
| 786 | } else { |
| 787 | next_sreg++; |
| 788 | } |
| 789 | } |
| 790 | if (attrs & DF_UC) { |
| 791 | if (attrs & DF_C_WIDE) { |
| 792 | AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); |
| 793 | } |
| 794 | } |
| 795 | } |
| 796 | |
| 797 | void X86Mir2Lir::AnalyzeDoubleUse(RegLocation use) { |
| 798 | // If this is a double literal, we will want it in the literal pool. |
| 799 | if (use.is_const) { |
| 800 | store_method_addr_ = true; |
| 801 | } |
| 802 | } |
| 803 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 804 | } // namespace art |