Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "dex/compiler_internals.h" |
Andreas Gampe | 53c913b | 2014-08-12 23:19:23 -0700 | [diff] [blame] | 21 | #include "dex/quick/mir_to_lir.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 22 | #include "x86_lir.h" |
| 23 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 24 | #include <map> |
| 25 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 26 | namespace art { |
| 27 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 28 | class X86Mir2Lir : public Mir2Lir { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 29 | protected: |
| 30 | class InToRegStorageMapper { |
| 31 | public: |
Serguei Katkov | 407a9d2 | 2014-07-05 03:09:32 +0700 | [diff] [blame] | 32 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 33 | virtual ~InToRegStorageMapper() {} |
| 34 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 35 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 36 | class InToRegStorageX86_64Mapper : public InToRegStorageMapper { |
| 37 | public: |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 38 | explicit InToRegStorageX86_64Mapper(Mir2Lir* ml) : ml_(ml), cur_core_reg_(0), cur_fp_reg_(0) {} |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 39 | virtual ~InToRegStorageX86_64Mapper() {} |
Serguei Katkov | 407a9d2 | 2014-07-05 03:09:32 +0700 | [diff] [blame] | 40 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 41 | protected: |
| 42 | Mir2Lir* ml_; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 43 | private: |
| 44 | int cur_core_reg_; |
| 45 | int cur_fp_reg_; |
| 46 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 47 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 48 | class InToRegStorageMapping { |
| 49 | public: |
| 50 | InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), |
| 51 | initialized_(false) {} |
| 52 | void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); |
| 53 | int GetMaxMappedIn() { return max_mapped_in_; } |
| 54 | bool IsThereStackMapped() { return is_there_stack_mapped_; } |
| 55 | RegStorage Get(int in_position); |
| 56 | bool IsInitialized() { return initialized_; } |
| 57 | private: |
| 58 | std::map<int, RegStorage> mapping_; |
| 59 | int max_mapped_in_; |
| 60 | bool is_there_stack_mapped_; |
| 61 | bool initialized_; |
| 62 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 63 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 64 | public: |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 65 | X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 67 | // Required for target - codegen helpers. |
| 68 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 69 | RegLocation rl_dest, int lit) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 70 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
| 71 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 72 | RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 73 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 74 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 75 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 76 | OpSize size) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 77 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 78 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 79 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 80 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 81 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
| 82 | OpSize size) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 83 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; |
| 84 | void GenImplicitNullCheck(RegStorage reg, int opt_flags) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 85 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 86 | // Required for target - register utilities. |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 87 | RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 88 | RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { |
| 89 | if (wide_kind == kWide) { |
| 90 | if (cu_->target64) { |
| 91 | return As64BitReg(TargetReg32(symbolic_reg)); |
| 92 | } else { |
| 93 | // x86: construct a pair. |
| 94 | DCHECK((kArg0 <= symbolic_reg && symbolic_reg < kArg3) || |
| 95 | (kFArg0 <= symbolic_reg && symbolic_reg < kFArg3) || |
| 96 | (kRet0 == symbolic_reg)); |
| 97 | return RegStorage::MakeRegPair(TargetReg32(symbolic_reg), |
| 98 | TargetReg32(static_cast<SpecialTargetRegister>(symbolic_reg + 1))); |
| 99 | } |
| 100 | } else if (wide_kind == kRef && cu_->target64) { |
| 101 | return As64BitReg(TargetReg32(symbolic_reg)); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 102 | } else { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 103 | return TargetReg32(symbolic_reg); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 104 | } |
| 105 | } |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 106 | RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 107 | return TargetReg(symbolic_reg, cu_->target64 ? kWide : kNotWide); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 108 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 109 | |
| 110 | RegStorage GetArgMappingToPhysicalReg(int arg_num) OVERRIDE; |
| 111 | |
| 112 | RegLocation GetReturnAlt() OVERRIDE; |
| 113 | RegLocation GetReturnWideAlt() OVERRIDE; |
| 114 | RegLocation LocCReturn() OVERRIDE; |
| 115 | RegLocation LocCReturnRef() OVERRIDE; |
| 116 | RegLocation LocCReturnDouble() OVERRIDE; |
| 117 | RegLocation LocCReturnFloat() OVERRIDE; |
| 118 | RegLocation LocCReturnWide() OVERRIDE; |
| 119 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 120 | ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 121 | void AdjustSpillMask() OVERRIDE; |
| 122 | void ClobberCallerSave() OVERRIDE; |
| 123 | void FreeCallTemps() OVERRIDE; |
| 124 | void LockCallTemps() OVERRIDE; |
| 125 | |
| 126 | void CompilerInitializeRegAlloc() OVERRIDE; |
| 127 | int VectorRegisterSize() OVERRIDE; |
| 128 | int NumReservableVectorRegisters(bool fp_used) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 129 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 130 | // Required for target - miscellaneous. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 131 | void AssembleLIR() OVERRIDE; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 132 | void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; |
| 133 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 134 | ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 135 | const char* GetTargetInstFmt(int opcode) OVERRIDE; |
| 136 | const char* GetTargetInstName(int opcode) OVERRIDE; |
| 137 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 138 | ResourceMask GetPCUseDefEncoding() const OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 139 | uint64_t GetTargetInstFlags(int opcode) OVERRIDE; |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 140 | size_t GetInsnSize(LIR* lir) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 141 | bool IsUnconditionalBranch(LIR* lir) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 142 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 143 | // Get the register class for load/store of a field. |
| 144 | RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 145 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 146 | // Required for target - Dalvik-level generators. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 147 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 148 | RegLocation rl_dest, int scale) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 149 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 150 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) OVERRIDE; |
| 151 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 152 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 153 | RegLocation rl_src2) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 154 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 155 | RegLocation rl_src2) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 156 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 157 | RegLocation rl_src2) OVERRIDE; |
| 158 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 159 | |
| 160 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE; |
| 161 | bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE; |
| 162 | bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE; |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 163 | bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 164 | bool GenInlinedSqrt(CallInfo* info) OVERRIDE; |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 165 | bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; |
| 166 | bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 167 | bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE; |
| 168 | bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE; |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 169 | bool GenInlinedCharAt(CallInfo* info) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 170 | |
| 171 | // Long instructions. |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 172 | void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 173 | RegLocation rl_src2) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 174 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 175 | RegLocation rl_src2) OVERRIDE; |
| 176 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 177 | RegLocation rl_src1, RegLocation rl_shift) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 178 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) OVERRIDE; |
| 179 | void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 180 | void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 181 | RegLocation rl_src1, RegLocation rl_shift) OVERRIDE; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 182 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 183 | /* |
| 184 | * @brief Generate a two address long operation with a constant value |
| 185 | * @param rl_dest location of result |
| 186 | * @param rl_src constant source operand |
| 187 | * @param op Opcode to be generated |
| 188 | * @return success or not |
| 189 | */ |
| 190 | bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 191 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 192 | /* |
| 193 | * @brief Generate a three address long operation with a constant value |
| 194 | * @param rl_dest location of result |
| 195 | * @param rl_src1 source operand |
| 196 | * @param rl_src2 constant source operand |
| 197 | * @param op Opcode to be generated |
| 198 | * @return success or not |
| 199 | */ |
| 200 | bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 201 | Instruction::Code op); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 202 | /** |
| 203 | * @brief Generate a long arithmetic operation. |
| 204 | * @param rl_dest The destination. |
| 205 | * @param rl_src1 First operand. |
| 206 | * @param rl_src2 Second operand. |
| 207 | * @param op The DEX opcode for the operation. |
| 208 | * @param is_commutative The sources can be swapped if needed. |
| 209 | */ |
| 210 | virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 211 | Instruction::Code op, bool is_commutative); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 212 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 213 | /** |
| 214 | * @brief Generate a two operand long arithmetic operation. |
| 215 | * @param rl_dest The destination. |
| 216 | * @param rl_src Second operand. |
| 217 | * @param op The DEX opcode for the operation. |
| 218 | */ |
| 219 | void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 220 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 221 | /** |
| 222 | * @brief Generate a long operation. |
| 223 | * @param rl_dest The destination. Must be in a register |
| 224 | * @param rl_src The other operand. May be in a register or in memory. |
| 225 | * @param op The DEX opcode for the operation. |
| 226 | */ |
| 227 | virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 228 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 229 | |
| 230 | // TODO: collapse reg_lo, reg_hi |
| 231 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div) |
| 232 | OVERRIDE; |
| 233 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) OVERRIDE; |
| 234 | void GenDivZeroCheckWide(RegStorage reg) OVERRIDE; |
| 235 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; |
| 236 | void GenExitSequence() OVERRIDE; |
| 237 | void GenSpecialExitSequence() OVERRIDE; |
| 238 | void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
| 239 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; |
| 240 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; |
| 241 | void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; |
| 242 | void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 243 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
| 244 | int dest_reg_class) OVERRIDE; |
| 245 | bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE; |
| 246 | void GenMoveException(RegLocation rl_dest) OVERRIDE; |
| 247 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 248 | int first_bit, int second_bit) OVERRIDE; |
| 249 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 250 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
Andreas Gampe | 48971b3 | 2014-08-06 10:09:01 -0700 | [diff] [blame] | 251 | void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
| 252 | void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 253 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 254 | /** |
| 255 | * @brief Implement instanceof a final class with x86 specific code. |
| 256 | * @param use_declaring_class 'true' if we can use the class itself. |
| 257 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 258 | * @param rl_dest Result to be set to 0 or 1. |
| 259 | * @param rl_src Object to be tested. |
| 260 | */ |
| 261 | void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 262 | RegLocation rl_src) OVERRIDE; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 263 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 264 | // Single operation generators. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 265 | LIR* OpUnconditionalBranch(LIR* target) OVERRIDE; |
| 266 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE; |
| 267 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE; |
| 268 | LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE; |
| 269 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE; |
| 270 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 271 | LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE; |
| 272 | void OpEndIT(LIR* it) OVERRIDE; |
| 273 | LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; |
| 274 | LIR* OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE; |
| 275 | LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE; |
| 276 | void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 277 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 278 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE; |
| 279 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE; |
| 280 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE; |
| 281 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; |
| 282 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 283 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE; |
| 284 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE; |
| 285 | LIR* OpTestSuspend(LIR* target) OVERRIDE; |
| 286 | LIR* OpVldm(RegStorage r_base, int count) OVERRIDE; |
| 287 | LIR* OpVstm(RegStorage r_base, int count) OVERRIDE; |
| 288 | void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE; |
| 289 | bool GenInlinedCurrentThread(CallInfo* info) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 290 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 291 | bool InexpensiveConstantInt(int32_t value) OVERRIDE; |
| 292 | bool InexpensiveConstantFloat(int32_t value) OVERRIDE; |
| 293 | bool InexpensiveConstantLong(int64_t value) OVERRIDE; |
| 294 | bool InexpensiveConstantDouble(int64_t value) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 295 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 296 | /* |
| 297 | * @brief Should try to optimize for two address instructions? |
| 298 | * @return true if we try to avoid generating three operand instructions. |
| 299 | */ |
| 300 | virtual bool GenerateTwoOperandInstructions() const { return true; } |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 301 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 302 | /* |
| 303 | * @brief x86 specific codegen for int operations. |
| 304 | * @param opcode Operation to perform. |
| 305 | * @param rl_dest Destination for the result. |
| 306 | * @param rl_lhs Left hand operand. |
| 307 | * @param rl_rhs Right hand operand. |
| 308 | */ |
| 309 | void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 310 | RegLocation rl_rhs) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 311 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 312 | /* |
| 313 | * @brief Load the Method* of a dex method into the register. |
| 314 | * @param target_method The MethodReference of the method to be invoked. |
| 315 | * @param type How the method will be invoked. |
| 316 | * @param register that will contain the code address. |
| 317 | * @note register will be passed to TargetReg to get physical register. |
| 318 | */ |
| 319 | void LoadMethodAddress(const MethodReference& target_method, InvokeType type, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 320 | SpecialTargetRegister symbolic_reg) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 321 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 322 | /* |
| 323 | * @brief Load the Class* of a Dex Class type into the register. |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 324 | * @param dex DexFile that contains the class type. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 325 | * @param type How the method will be invoked. |
| 326 | * @param register that will contain the code address. |
| 327 | * @note register will be passed to TargetReg to get physical register. |
| 328 | */ |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 329 | void LoadClassType(const DexFile& dex_file, uint32_t type_idx, |
| 330 | SpecialTargetRegister symbolic_reg) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 331 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 332 | void FlushIns(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 333 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 334 | int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 335 | NextCallInsn next_call_insn, |
| 336 | const MethodReference& target_method, |
| 337 | uint32_t vtable_idx, |
| 338 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 339 | bool skip_this) OVERRIDE; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 340 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 341 | int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, |
| 342 | NextCallInsn next_call_insn, |
| 343 | const MethodReference& target_method, |
| 344 | uint32_t vtable_idx, |
| 345 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 346 | bool skip_this) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 347 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 348 | /* |
| 349 | * @brief Generate a relative call to the method that will be patched at link time. |
| 350 | * @param target_method The MethodReference of the method to be invoked. |
| 351 | * @param type How the method will be invoked. |
| 352 | * @returns Call instruction |
| 353 | */ |
| 354 | virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 355 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 356 | /* |
| 357 | * @brief Handle x86 specific literals |
| 358 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 359 | void InstallLiteralPools() OVERRIDE; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 360 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 361 | /* |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 362 | * @brief Generate the debug_frame FDE information. |
| 363 | * @returns pointer to vector containing CFE information |
| 364 | */ |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 365 | std::vector<uint8_t>* ReturnFrameDescriptionEntry() OVERRIDE; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 366 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 367 | LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; |
| 368 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 369 | protected: |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 370 | RegStorage TargetReg32(SpecialTargetRegister reg); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 371 | // Casting of RegStorage |
| 372 | RegStorage As32BitReg(RegStorage reg) { |
| 373 | DCHECK(!reg.IsPair()); |
| 374 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { |
| 375 | if (kFailOnSizeError) { |
| 376 | LOG(FATAL) << "Expected 64b register " << reg.GetReg(); |
| 377 | } else { |
| 378 | LOG(WARNING) << "Expected 64b register " << reg.GetReg(); |
| 379 | return reg; |
| 380 | } |
| 381 | } |
| 382 | RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, |
| 383 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 384 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) |
| 385 | ->GetReg().GetReg(), |
| 386 | ret_val.GetReg()); |
| 387 | return ret_val; |
| 388 | } |
| 389 | |
| 390 | RegStorage As64BitReg(RegStorage reg) { |
| 391 | DCHECK(!reg.IsPair()); |
| 392 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { |
| 393 | if (kFailOnSizeError) { |
| 394 | LOG(FATAL) << "Expected 32b register " << reg.GetReg(); |
| 395 | } else { |
| 396 | LOG(WARNING) << "Expected 32b register " << reg.GetReg(); |
| 397 | return reg; |
| 398 | } |
| 399 | } |
| 400 | RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, |
| 401 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 402 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) |
| 403 | ->GetReg().GetReg(), |
| 404 | ret_val.GetReg()); |
| 405 | return ret_val; |
| 406 | } |
| 407 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 408 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
| 409 | RegStorage r_dest, OpSize size); |
| 410 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame^] | 411 | RegStorage r_src, OpSize size, int opt_flags = 0); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 412 | |
| 413 | RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); |
| 414 | |
| 415 | int AssignInsnOffsets(); |
| 416 | void AssignOffsets(); |
| 417 | AssemblerStatus AssembleInstructions(CodeOffset start_addr); |
| 418 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 419 | size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 420 | int32_t raw_base, int32_t displacement); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 421 | void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); |
| 422 | void EmitPrefix(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 423 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 424 | void EmitOpcode(const X86EncodingMap* entry); |
| 425 | void EmitPrefixAndOpcode(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 426 | int32_t reg_r, int32_t reg_x, int32_t reg_b); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 427 | void EmitDisp(uint8_t base, int32_t disp); |
| 428 | void EmitModrmThread(uint8_t reg_or_opcode); |
| 429 | void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); |
| 430 | void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, |
| 431 | int32_t disp); |
| 432 | void EmitImm(const X86EncodingMap* entry, int64_t imm); |
| 433 | void EmitNullary(const X86EncodingMap* entry); |
| 434 | void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); |
| 435 | void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); |
| 436 | void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 437 | void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 438 | int32_t disp); |
| 439 | void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); |
| 440 | void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); |
| 441 | void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 442 | int32_t raw_index, int scale, int32_t disp); |
| 443 | void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 444 | int32_t disp, int32_t raw_reg); |
| 445 | void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 446 | void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 447 | int32_t raw_disp, int32_t imm); |
| 448 | void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); |
| 449 | void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); |
| 450 | void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); |
| 451 | void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 452 | int32_t imm); |
| 453 | void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, |
| 454 | int32_t imm); |
| 455 | void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 456 | void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); |
| 457 | void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); |
| 458 | void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 459 | void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); |
| 460 | void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 461 | void EmitShiftRegRegCl(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, |
| 462 | int32_t raw_cl); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 463 | void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 464 | void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); |
| 465 | void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); |
| 466 | void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); |
| 467 | void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 468 | int32_t cc); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 469 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 470 | void EmitJmp(const X86EncodingMap* entry, int32_t rel); |
| 471 | void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); |
| 472 | void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 473 | void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); |
| 474 | void EmitCallThread(const X86EncodingMap* entry, int32_t disp); |
| 475 | void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, |
| 476 | int32_t raw_index, int scale, int32_t table_or_disp); |
| 477 | void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); |
| 478 | void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); |
| 479 | void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 480 | int64_t val, ConditionCode ccode); |
| 481 | void GenConstWide(RegLocation rl_dest, int64_t value); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 482 | void GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir); |
| 483 | void GenShiftByteVector(BasicBlock *bb, MIR *mir); |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 484 | void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, |
| 485 | uint32_t m4); |
| 486 | void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, |
| 487 | uint32_t m3, uint32_t m4); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 488 | void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 489 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 490 | static bool ProvidesFullMemoryBarrier(X86OpCode opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 491 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 492 | /* |
| 493 | * @brief Ensure that a temporary register is byte addressable. |
| 494 | * @returns a temporary guarenteed to be byte addressable. |
| 495 | */ |
| 496 | virtual RegStorage AllocateByteRegister(); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 497 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 498 | /* |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 499 | * @brief Use a wide temporary as a 128-bit register |
| 500 | * @returns a 128-bit temporary register. |
| 501 | */ |
| 502 | virtual RegStorage Get128BitRegister(RegStorage reg); |
| 503 | |
| 504 | /* |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 505 | * @brief Check if a register is byte addressable. |
| 506 | * @returns true if a register is byte addressable. |
| 507 | */ |
| 508 | bool IsByteRegister(RegStorage reg); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 509 | |
| 510 | void GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, int64_t imm, bool is_div); |
| 511 | |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 512 | bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 513 | |
| 514 | /* |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 515 | * @brief generate inline code for fast case of Strng.indexOf. |
| 516 | * @param info Call parameters |
| 517 | * @param zero_based 'true' if the index into the string is 0. |
| 518 | * @returns 'true' if the call was inlined, 'false' if a regular call needs to be |
| 519 | * generated. |
| 520 | */ |
| 521 | bool GenInlinedIndexOf(CallInfo* info, bool zero_based); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 522 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 523 | /** |
| 524 | * @brief Reserve a fixed number of vector registers from the register pool |
| 525 | * @details The mir->dalvikInsn.vA specifies an N such that vector registers |
| 526 | * [0..N-1] are removed from the temporary pool. The caller must call |
| 527 | * ReturnVectorRegisters before calling ReserveVectorRegisters again. |
| 528 | * Also sets the num_reserved_vector_regs_ to the specified value |
| 529 | * @param mir whose vA specifies the number of registers to reserve |
| 530 | */ |
| 531 | void ReserveVectorRegisters(MIR* mir); |
| 532 | |
| 533 | /** |
| 534 | * @brief Return all the reserved vector registers to the temp pool |
| 535 | * @details Returns [0..num_reserved_vector_regs_] |
| 536 | */ |
| 537 | void ReturnVectorRegisters(); |
| 538 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 539 | /* |
| 540 | * @brief Load 128 bit constant into vector register. |
| 541 | * @param bb The basic block in which the MIR is from. |
| 542 | * @param mir The MIR whose opcode is kMirConstVector |
| 543 | * @note vA is the TypeSize for the register. |
| 544 | * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. |
| 545 | */ |
| 546 | void GenConst128(BasicBlock* bb, MIR* mir); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 547 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 548 | /* |
| 549 | * @brief MIR to move a vectorized register to another. |
| 550 | * @param bb The basic block in which the MIR is from. |
| 551 | * @param mir The MIR whose opcode is kMirConstVector. |
| 552 | * @note vA: TypeSize |
| 553 | * @note vB: destination |
| 554 | * @note vC: source |
| 555 | */ |
| 556 | void GenMoveVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 557 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 558 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 559 | * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know |
| 560 | * the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 561 | * @param bb The basic block in which the MIR is from. |
| 562 | * @param mir The MIR whose opcode is kMirConstVector. |
| 563 | * @note vA: TypeSize |
| 564 | * @note vB: destination and source |
| 565 | * @note vC: source |
| 566 | */ |
| 567 | void GenMultiplyVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 568 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 569 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 570 | * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the |
| 571 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 572 | * @param bb The basic block in which the MIR is from. |
| 573 | * @param mir The MIR whose opcode is kMirConstVector. |
| 574 | * @note vA: TypeSize |
| 575 | * @note vB: destination and source |
| 576 | * @note vC: source |
| 577 | */ |
| 578 | void GenAddVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 579 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 580 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 581 | * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the |
| 582 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 583 | * @param bb The basic block in which the MIR is from. |
| 584 | * @param mir The MIR whose opcode is kMirConstVector. |
| 585 | * @note vA: TypeSize |
| 586 | * @note vB: destination and source |
| 587 | * @note vC: source |
| 588 | */ |
| 589 | void GenSubtractVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 590 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 591 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 592 | * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the |
| 593 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 594 | * @param bb The basic block in which the MIR is from. |
| 595 | * @param mir The MIR whose opcode is kMirConstVector. |
| 596 | * @note vA: TypeSize |
| 597 | * @note vB: destination and source |
| 598 | * @note vC: immediate |
| 599 | */ |
| 600 | void GenShiftLeftVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 601 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 602 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 603 | * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to |
| 604 | * know the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 605 | * @param bb The basic block in which the MIR is from. |
| 606 | * @param mir The MIR whose opcode is kMirConstVector. |
| 607 | * @note vA: TypeSize |
| 608 | * @note vB: destination and source |
| 609 | * @note vC: immediate |
| 610 | */ |
| 611 | void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 612 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 613 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 614 | * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA |
| 615 | * to know the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 616 | * @param bb The basic block in which the MIR is from.. |
| 617 | * @param mir The MIR whose opcode is kMirConstVector. |
| 618 | * @note vA: TypeSize |
| 619 | * @note vB: destination and source |
| 620 | * @note vC: immediate |
| 621 | */ |
| 622 | void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 623 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 624 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 625 | * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the |
| 626 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 627 | * @note vA: TypeSize |
| 628 | * @note vB: destination and source |
| 629 | * @note vC: source |
| 630 | */ |
| 631 | void GenAndVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 632 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 633 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 634 | * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the |
| 635 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 636 | * @param bb The basic block in which the MIR is from. |
| 637 | * @param mir The MIR whose opcode is kMirConstVector. |
| 638 | * @note vA: TypeSize |
| 639 | * @note vB: destination and source |
| 640 | * @note vC: source |
| 641 | */ |
| 642 | void GenOrVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 643 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 644 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 645 | * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the |
| 646 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 647 | * @param bb The basic block in which the MIR is from. |
| 648 | * @param mir The MIR whose opcode is kMirConstVector. |
| 649 | * @note vA: TypeSize |
| 650 | * @note vB: destination and source |
| 651 | * @note vC: source |
| 652 | */ |
| 653 | void GenXorVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 654 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 655 | /* |
| 656 | * @brief Reduce a 128-bit packed element into a single VR by taking lower bits |
| 657 | * @param bb The basic block in which the MIR is from. |
| 658 | * @param mir The MIR whose opcode is kMirConstVector. |
| 659 | * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. |
| 660 | * @note vA: TypeSize |
| 661 | * @note vB: destination and source VR (not vector register) |
| 662 | * @note vC: source (vector register) |
| 663 | */ |
| 664 | void GenAddReduceVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 665 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 666 | /* |
| 667 | * @brief Extract a packed element into a single VR. |
| 668 | * @param bb The basic block in which the MIR is from. |
| 669 | * @param mir The MIR whose opcode is kMirConstVector. |
| 670 | * @note vA: TypeSize |
| 671 | * @note vB: destination VR (not vector register) |
| 672 | * @note vC: source (vector register) |
| 673 | * @note arg[0]: The index to use for extraction from vector register (which packed element). |
| 674 | */ |
| 675 | void GenReduceVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 676 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 677 | /* |
| 678 | * @brief Create a vector value, with all TypeSize values equal to vC |
| 679 | * @param bb The basic block in which the MIR is from. |
| 680 | * @param mir The MIR whose opcode is kMirConstVector. |
| 681 | * @note vA: TypeSize. |
| 682 | * @note vB: destination vector register. |
| 683 | * @note vC: source VR (not vector register). |
| 684 | */ |
| 685 | void GenSetVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 686 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 687 | /* |
| 688 | * @brief Generate code for a vector opcode. |
| 689 | * @param bb The basic block in which the MIR is from. |
| 690 | * @param mir The MIR whose opcode is a non-standard opcode. |
| 691 | */ |
| 692 | void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 693 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 694 | /* |
| 695 | * @brief Return the correct x86 opcode for the Dex operation |
| 696 | * @param op Dex opcode for the operation |
| 697 | * @param loc Register location of the operand |
| 698 | * @param is_high_op 'true' if this is an operation on the high word |
| 699 | * @param value Immediate value for the operation. Used for byte variants |
| 700 | * @returns the correct x86 opcode to perform the operation |
| 701 | */ |
| 702 | X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 703 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 704 | /* |
| 705 | * @brief Return the correct x86 opcode for the Dex operation |
| 706 | * @param op Dex opcode for the operation |
| 707 | * @param dest location of the destination. May be register or memory. |
| 708 | * @param rhs Location for the rhs of the operation. May be in register or memory. |
| 709 | * @param is_high_op 'true' if this is an operation on the high word |
| 710 | * @returns the correct x86 opcode to perform the operation |
| 711 | * @note at most one location may refer to memory |
| 712 | */ |
| 713 | X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 714 | bool is_high_op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 715 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 716 | /* |
| 717 | * @brief Is this operation a no-op for this opcode and value |
| 718 | * @param op Dex opcode for the operation |
| 719 | * @param value Immediate value for the operation. |
| 720 | * @returns 'true' if the operation will have no effect |
| 721 | */ |
| 722 | bool IsNoOp(Instruction::Code op, int32_t value); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 723 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 724 | /** |
| 725 | * @brief Calculate magic number and shift for a given divisor |
| 726 | * @param divisor divisor number for calculation |
| 727 | * @param magic hold calculated magic number |
| 728 | * @param shift hold calculated shift |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 729 | * @param is_long 'true' if divisor is jlong, 'false' for jint. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 730 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 731 | void CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 732 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 733 | /* |
| 734 | * @brief Generate an integer div or rem operation. |
| 735 | * @param rl_dest Destination Location. |
| 736 | * @param rl_src1 Numerator Location. |
| 737 | * @param rl_src2 Divisor Location. |
| 738 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 739 | * @param check_zero 'true' if an exception should be generated if the divisor is 0. |
| 740 | */ |
| 741 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 742 | bool is_div, bool check_zero); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 743 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 744 | /* |
| 745 | * @brief Generate an integer div or rem operation by a literal. |
| 746 | * @param rl_dest Destination Location. |
| 747 | * @param rl_src Numerator Location. |
| 748 | * @param lit Divisor. |
| 749 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 750 | */ |
| 751 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 752 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 753 | /* |
| 754 | * Generate code to implement long shift operations. |
| 755 | * @param opcode The DEX opcode to specify the shift type. |
| 756 | * @param rl_dest The destination. |
| 757 | * @param rl_src The value to be shifted. |
| 758 | * @param shift_amount How much to shift. |
| 759 | * @returns the RegLocation of the result. |
| 760 | */ |
| 761 | RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 762 | RegLocation rl_src, int shift_amount); |
| 763 | /* |
| 764 | * Generate an imul of a register by a constant or a better sequence. |
| 765 | * @param dest Destination Register. |
| 766 | * @param src Source Register. |
| 767 | * @param val Constant multiplier. |
| 768 | */ |
| 769 | void GenImulRegImm(RegStorage dest, RegStorage src, int val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 770 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 771 | /* |
| 772 | * Generate an imul of a memory location by a constant or a better sequence. |
| 773 | * @param dest Destination Register. |
| 774 | * @param sreg Symbolic register. |
| 775 | * @param displacement Displacement on stack of Symbolic Register. |
| 776 | * @param val Constant multiplier. |
| 777 | */ |
| 778 | void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 779 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 780 | /* |
| 781 | * @brief Compare memory to immediate, and branch if condition true. |
| 782 | * @param cond The condition code that when true will branch to the target. |
| 783 | * @param temp_reg A temporary register that can be used if compare memory is not |
| 784 | * supported by the architecture. |
| 785 | * @param base_reg The register holding the base address. |
| 786 | * @param offset The offset from the base. |
| 787 | * @param check_value The immediate to compare to. |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 788 | * @param target branch target (or nullptr) |
| 789 | * @param compare output for getting LIR for comparison (or nullptr) |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 790 | */ |
| 791 | LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 792 | int offset, int check_value, LIR* target, LIR** compare); |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 793 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 794 | void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); |
| 795 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 796 | /* |
| 797 | * Can this operation be using core registers without temporaries? |
| 798 | * @param rl_lhs Left hand operand. |
| 799 | * @param rl_rhs Right hand operand. |
| 800 | * @returns 'true' if the operation can proceed without needing temporary regs. |
| 801 | */ |
| 802 | bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 803 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 804 | /** |
| 805 | * @brief Generates inline code for conversion of long to FP by using x87/ |
| 806 | * @param rl_dest The destination of the FP. |
| 807 | * @param rl_src The source of the long. |
| 808 | * @param is_double 'true' if dealing with double, 'false' for float. |
| 809 | */ |
| 810 | virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 811 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 812 | void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); |
| 813 | void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); |
| 814 | |
| 815 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 816 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); |
| 817 | LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); |
| 818 | LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); |
| 819 | LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset); |
| 820 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); |
| 821 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); |
| 822 | void OpTlsCmp(ThreadOffset<4> offset, int val); |
| 823 | void OpTlsCmp(ThreadOffset<8> offset, int val); |
| 824 | |
| 825 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 826 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 827 | // Try to do a long multiplication where rl_src2 is a constant. This simplified setup might fail, |
| 828 | // in which case false will be returned. |
| 829 | bool GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val); |
| 830 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 831 | RegLocation rl_src2); |
| 832 | void GenNotLong(RegLocation rl_dest, RegLocation rl_src); |
| 833 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 834 | void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
| 835 | RegLocation rl_src2, bool is_div); |
| 836 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 837 | void SpillCoreRegs(); |
| 838 | void UnSpillCoreRegs(); |
| 839 | void UnSpillFPRegs(); |
| 840 | void SpillFPRegs(); |
| 841 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 842 | /* |
| 843 | * @brief Perform MIR analysis before compiling method. |
| 844 | * @note Invokes Mir2LiR::Materialize after analysis. |
| 845 | */ |
| 846 | void Materialize(); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 847 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 848 | /* |
| 849 | * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register |
| 850 | * without regard to data type. In practice, this can result in UpdateLoc returning a |
| 851 | * location record for a Dalvik float value in a core register, and vis-versa. For targets |
| 852 | * which can inexpensively move data between core and float registers, this can often be a win. |
| 853 | * However, for x86 this is generally not a win. These variants of UpdateLoc() |
| 854 | * take a register class argument - and will return an in-register location record only if |
| 855 | * the value is live in a temp register of the correct class. Additionally, if the value is in |
| 856 | * a temp register of the wrong register class, it will be clobbered. |
| 857 | */ |
| 858 | RegLocation UpdateLocTyped(RegLocation loc, int reg_class); |
| 859 | RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 860 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 861 | /* |
| 862 | * @brief Analyze MIR before generating code, to prepare for the code generation. |
| 863 | */ |
| 864 | void AnalyzeMIR(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 865 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 866 | /* |
| 867 | * @brief Analyze one basic block. |
| 868 | * @param bb Basic block to analyze. |
| 869 | */ |
| 870 | void AnalyzeBB(BasicBlock * bb); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 871 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 872 | /* |
| 873 | * @brief Analyze one extended MIR instruction |
| 874 | * @param opcode MIR instruction opcode. |
| 875 | * @param bb Basic block containing instruction. |
| 876 | * @param mir Extended instruction to analyze. |
| 877 | */ |
| 878 | void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 879 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 880 | /* |
| 881 | * @brief Analyze one MIR instruction |
| 882 | * @param opcode MIR instruction opcode. |
| 883 | * @param bb Basic block containing instruction. |
| 884 | * @param mir Instruction to analyze. |
| 885 | */ |
| 886 | virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 887 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 888 | /* |
| 889 | * @brief Analyze one MIR float/double instruction |
| 890 | * @param opcode MIR instruction opcode. |
| 891 | * @param bb Basic block containing instruction. |
| 892 | * @param mir Instruction to analyze. |
| 893 | */ |
| 894 | void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 895 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 896 | /* |
| 897 | * @brief Analyze one use of a double operand. |
| 898 | * @param rl_use Double RegLocation for the operand. |
| 899 | */ |
| 900 | void AnalyzeDoubleUse(RegLocation rl_use); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 901 | |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 902 | /* |
| 903 | * @brief Analyze one invoke-static MIR instruction |
| 904 | * @param opcode MIR instruction opcode. |
| 905 | * @param bb Basic block containing instruction. |
| 906 | * @param mir Instruction to analyze. |
| 907 | */ |
| 908 | void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); |
| 909 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 910 | // Information derived from analysis of MIR |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 911 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 912 | // The compiler temporary for the code address of the method. |
| 913 | CompilerTemp *base_of_code_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 914 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 915 | // Have we decided to compute a ptr to code and store in temporary VR? |
| 916 | bool store_method_addr_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 917 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 918 | // Have we used the stored method address? |
| 919 | bool store_method_addr_used_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 920 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 921 | // Instructions to remove if we didn't use the stored method address. |
| 922 | LIR* setup_method_address_[2]; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 923 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 924 | // Instructions needing patching with Method* values. |
| 925 | GrowableArray<LIR*> method_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 926 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 927 | // Instructions needing patching with Class Type* values. |
| 928 | GrowableArray<LIR*> class_type_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 929 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 930 | // Instructions needing patching with PC relative code addresses. |
| 931 | GrowableArray<LIR*> call_method_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 932 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 933 | // Prologue decrement of stack pointer. |
| 934 | LIR* stack_decrement_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 935 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 936 | // Epilogue increment of stack pointer. |
| 937 | LIR* stack_increment_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 938 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 939 | // The list of const vector literals. |
| 940 | LIR *const_vectors_; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 941 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 942 | /* |
| 943 | * @brief Search for a matching vector literal |
| 944 | * @param mir A kMirOpConst128b MIR instruction to match. |
| 945 | * @returns pointer to matching LIR constant, or nullptr if not found. |
| 946 | */ |
| 947 | LIR *ScanVectorLiteral(MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 948 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 949 | /* |
| 950 | * @brief Add a constant vector literal |
| 951 | * @param mir A kMirOpConst128b MIR instruction to match. |
| 952 | */ |
| 953 | LIR *AddVectorLiteral(MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 954 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 955 | InToRegStorageMapping in_to_reg_storage_mapping_; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 956 | |
Serguei Katkov | 59a42af | 2014-07-05 00:55:46 +0700 | [diff] [blame] | 957 | bool WideGPRsAreAliases() OVERRIDE { |
| 958 | return cu_->target64; // On 64b, we have 64b GPRs. |
| 959 | } |
| 960 | bool WideFPRsAreAliases() OVERRIDE { |
| 961 | return true; // xmm registers have 64b views even on x86. |
| 962 | } |
| 963 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 964 | /* |
| 965 | * @brief Dump a RegLocation using printf |
| 966 | * @param loc Register location to dump |
| 967 | */ |
| 968 | static void DumpRegLocation(RegLocation loc); |
| 969 | |
| 970 | static const X86EncodingMap EncodingMap[kX86Last]; |
| 971 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 972 | private: |
| 973 | // The number of vector registers [0..N] reserved by a call to ReserveVectorRegisters |
| 974 | int num_reserved_vector_regs_; |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 975 | |
| 976 | void SwapBits(RegStorage result_reg, int shift, int32_t value); |
| 977 | void SwapBits64(RegStorage result_reg, int shift, int64_t value); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 978 | }; |
| 979 | |
| 980 | } // namespace art |
| 981 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 982 | #endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |