Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_arm64.h" |
| 18 | |
| 19 | #include <inttypes.h> |
| 20 | |
| 21 | #include <string> |
| 22 | |
Andreas Gampe | 53c913b | 2014-08-12 23:19:23 -0700 | [diff] [blame] | 23 | #include "backend_arm64.h" |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 24 | #include "dex/compiler_internals.h" |
| 25 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 26 | #include "dex/reg_storage_eq.h" |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 27 | |
| 28 | namespace art { |
| 29 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 30 | static constexpr RegStorage core_regs_arr[] = |
buzbee | b01bf15 | 2014-05-13 15:59:07 -0700 | [diff] [blame] | 31 | {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7, |
| 32 | rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, |
| 33 | rs_w16, rs_w17, rs_w18, rs_w19, rs_w20, rs_w21, rs_w22, rs_w23, |
| 34 | rs_w24, rs_w25, rs_w26, rs_w27, rs_w28, rs_w29, rs_w30, rs_w31, |
| 35 | rs_wzr}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 36 | static constexpr RegStorage core64_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 37 | {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, |
| 38 | rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, |
| 39 | rs_x16, rs_x17, rs_x18, rs_x19, rs_x20, rs_x21, rs_x22, rs_x23, |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 40 | rs_x24, rs_x25, rs_x26, rs_x27, rs_x28, rs_x29, rs_x30, rs_x31, |
| 41 | rs_xzr}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 42 | static constexpr RegStorage sp_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 43 | {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, |
| 44 | rs_f8, rs_f9, rs_f10, rs_f11, rs_f12, rs_f13, rs_f14, rs_f15, |
| 45 | rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, |
| 46 | rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 47 | static constexpr RegStorage dp_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 48 | {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame] | 49 | rs_d8, rs_d9, rs_d10, rs_d11, rs_d12, rs_d13, rs_d14, rs_d15, |
| 50 | rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, |
| 51 | rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; |
Zheng Xu | b551fdc | 2014-07-25 11:49:42 +0800 | [diff] [blame] | 52 | // Note: we are not able to call to C function since rs_xSELF is a special register need to be |
| 53 | // preserved but would be scratched by native functions follow aapcs64. |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 54 | static constexpr RegStorage reserved_regs_arr[] = |
Zheng Xu | baa7c88 | 2014-06-30 14:26:50 +0800 | [diff] [blame] | 55 | {rs_wSUSPEND, rs_wSELF, rs_wsp, rs_wLR, rs_wzr}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 56 | static constexpr RegStorage reserved64_regs_arr[] = |
Zheng Xu | baa7c88 | 2014-06-30 14:26:50 +0800 | [diff] [blame] | 57 | {rs_xSUSPEND, rs_xSELF, rs_sp, rs_xLR, rs_xzr}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 58 | static constexpr RegStorage core_temps_arr[] = |
buzbee | b01bf15 | 2014-05-13 15:59:07 -0700 | [diff] [blame] | 59 | {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7, |
| 60 | rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, rs_w16, |
| 61 | rs_w17}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 62 | static constexpr RegStorage core64_temps_arr[] = |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame] | 63 | {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, |
| 64 | rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, rs_x16, |
| 65 | rs_x17}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 66 | static constexpr RegStorage sp_temps_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 67 | {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame] | 68 | rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, |
| 69 | rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 70 | static constexpr RegStorage dp_temps_arr[] = |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame] | 71 | {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, |
| 72 | rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, |
| 73 | rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 74 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 75 | static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr); |
| 76 | static constexpr ArrayRef<const RegStorage> core64_regs(core64_regs_arr); |
| 77 | static constexpr ArrayRef<const RegStorage> sp_regs(sp_regs_arr); |
| 78 | static constexpr ArrayRef<const RegStorage> dp_regs(dp_regs_arr); |
| 79 | static constexpr ArrayRef<const RegStorage> reserved_regs(reserved_regs_arr); |
| 80 | static constexpr ArrayRef<const RegStorage> reserved64_regs(reserved64_regs_arr); |
| 81 | static constexpr ArrayRef<const RegStorage> core_temps(core_temps_arr); |
| 82 | static constexpr ArrayRef<const RegStorage> core64_temps(core64_temps_arr); |
| 83 | static constexpr ArrayRef<const RegStorage> sp_temps(sp_temps_arr); |
| 84 | static constexpr ArrayRef<const RegStorage> dp_temps(dp_temps_arr); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 85 | |
| 86 | RegLocation Arm64Mir2Lir::LocCReturn() { |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 87 | return a64_loc_c_return; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 88 | } |
| 89 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 90 | RegLocation Arm64Mir2Lir::LocCReturnRef() { |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 91 | return a64_loc_c_return_ref; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 94 | RegLocation Arm64Mir2Lir::LocCReturnWide() { |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 95 | return a64_loc_c_return_wide; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | RegLocation Arm64Mir2Lir::LocCReturnFloat() { |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 99 | return a64_loc_c_return_float; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | RegLocation Arm64Mir2Lir::LocCReturnDouble() { |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 103 | return a64_loc_c_return_double; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | // Return a target-dependent special register. |
| 107 | RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) { |
| 108 | RegStorage res_reg = RegStorage::InvalidReg(); |
| 109 | switch (reg) { |
Matteo Franchin | ed7a0f2 | 2014-06-10 19:23:45 +0100 | [diff] [blame] | 110 | case kSelf: res_reg = rs_wSELF; break; |
| 111 | case kSuspend: res_reg = rs_wSUSPEND; break; |
| 112 | case kLr: res_reg = rs_wLR; break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 113 | case kPc: res_reg = RegStorage::InvalidReg(); break; |
Matteo Franchin | ed7a0f2 | 2014-06-10 19:23:45 +0100 | [diff] [blame] | 114 | case kSp: res_reg = rs_wsp; break; |
| 115 | case kArg0: res_reg = rs_w0; break; |
| 116 | case kArg1: res_reg = rs_w1; break; |
| 117 | case kArg2: res_reg = rs_w2; break; |
| 118 | case kArg3: res_reg = rs_w3; break; |
| 119 | case kArg4: res_reg = rs_w4; break; |
| 120 | case kArg5: res_reg = rs_w5; break; |
| 121 | case kArg6: res_reg = rs_w6; break; |
| 122 | case kArg7: res_reg = rs_w7; break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 123 | case kFArg0: res_reg = rs_f0; break; |
| 124 | case kFArg1: res_reg = rs_f1; break; |
| 125 | case kFArg2: res_reg = rs_f2; break; |
| 126 | case kFArg3: res_reg = rs_f3; break; |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 127 | case kFArg4: res_reg = rs_f4; break; |
| 128 | case kFArg5: res_reg = rs_f5; break; |
| 129 | case kFArg6: res_reg = rs_f6; break; |
| 130 | case kFArg7: res_reg = rs_f7; break; |
Matteo Franchin | ed7a0f2 | 2014-06-10 19:23:45 +0100 | [diff] [blame] | 131 | case kRet0: res_reg = rs_w0; break; |
| 132 | case kRet1: res_reg = rs_w1; break; |
| 133 | case kInvokeTgt: res_reg = rs_wLR; break; |
Zheng Xu | b551fdc | 2014-07-25 11:49:42 +0800 | [diff] [blame] | 134 | case kHiddenArg: res_reg = rs_wIP1; break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 135 | case kHiddenFpArg: res_reg = RegStorage::InvalidReg(); break; |
| 136 | case kCount: res_reg = RegStorage::InvalidReg(); break; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 137 | default: res_reg = RegStorage::InvalidReg(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 138 | } |
| 139 | return res_reg; |
| 140 | } |
| 141 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 142 | /* |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 143 | * Decode the register id. This routine makes assumptions on the encoding made by RegStorage. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 144 | */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 145 | ResourceMask Arm64Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 146 | // TODO(Arm64): this function depends too much on the internal RegStorage encoding. Refactor. |
| 147 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 148 | // Check if the shape mask is zero (i.e. invalid). |
| 149 | if (UNLIKELY(reg == rs_wzr || reg == rs_xzr)) { |
| 150 | // The zero register is not a true register. It is just an immediate zero. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 151 | return kEncodeNone; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 152 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 153 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 154 | return ResourceMask::Bit( |
| 155 | // FP register starts at bit position 32. |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 156 | (reg.IsFloat() ? kA64FPReg0 : 0) + reg.GetRegNum()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 157 | } |
| 158 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 159 | ResourceMask Arm64Mir2Lir::GetPCUseDefEncoding() const { |
Zheng Xu | 421efca | 2014-07-11 17:33:59 +0800 | [diff] [blame] | 160 | // Note: On arm64, we are not able to set pc except branch instructions, which is regarded as a |
| 161 | // kind of barrier. All other instructions only use pc, which has no dependency between any |
| 162 | // of them. So it is fine to just return kEncodeNone here. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 163 | return kEncodeNone; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 164 | } |
| 165 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 166 | // Arm64 specific setup. TODO: inline?: |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 167 | void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 168 | ResourceMask* use_mask, ResourceMask* def_mask) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 169 | DCHECK_EQ(cu_->instruction_set, kArm64); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 170 | DCHECK(!lir->flags.use_def_invalid); |
| 171 | |
Zheng Xu | 421efca | 2014-07-11 17:33:59 +0800 | [diff] [blame] | 172 | // Note: REG_USE_PC is ignored, the reason is the same with what we do in GetPCUseDefEncoding(). |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 173 | // These flags are somewhat uncommon - bypass if we can. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 174 | if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LR)) != 0) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 175 | if (flags & REG_DEF_SP) { |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 176 | def_mask->SetBit(kA64RegSP); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | if (flags & REG_USE_SP) { |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 180 | use_mask->SetBit(kA64RegSP); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 181 | } |
| 182 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 183 | if (flags & REG_DEF_LR) { |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 184 | def_mask->SetBit(kA64RegLR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 185 | } |
| 186 | } |
| 187 | } |
| 188 | |
| 189 | ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { |
| 190 | ArmConditionCode res; |
| 191 | switch (ccode) { |
| 192 | case kCondEq: res = kArmCondEq; break; |
| 193 | case kCondNe: res = kArmCondNe; break; |
| 194 | case kCondCs: res = kArmCondCs; break; |
| 195 | case kCondCc: res = kArmCondCc; break; |
| 196 | case kCondUlt: res = kArmCondCc; break; |
| 197 | case kCondUge: res = kArmCondCs; break; |
| 198 | case kCondMi: res = kArmCondMi; break; |
| 199 | case kCondPl: res = kArmCondPl; break; |
| 200 | case kCondVs: res = kArmCondVs; break; |
| 201 | case kCondVc: res = kArmCondVc; break; |
| 202 | case kCondHi: res = kArmCondHi; break; |
| 203 | case kCondLs: res = kArmCondLs; break; |
| 204 | case kCondGe: res = kArmCondGe; break; |
| 205 | case kCondLt: res = kArmCondLt; break; |
| 206 | case kCondGt: res = kArmCondGt; break; |
| 207 | case kCondLe: res = kArmCondLe; break; |
| 208 | case kCondAl: res = kArmCondAl; break; |
| 209 | case kCondNv: res = kArmCondNv; break; |
| 210 | default: |
| 211 | LOG(FATAL) << "Bad condition code " << ccode; |
| 212 | res = static_cast<ArmConditionCode>(0); // Quiet gcc |
| 213 | } |
| 214 | return res; |
| 215 | } |
| 216 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 217 | static const char *shift_names[4] = { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 218 | "lsl", |
| 219 | "lsr", |
| 220 | "asr", |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 221 | "ror" |
| 222 | }; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 223 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 224 | static const char* extend_names[8] = { |
| 225 | "uxtb", |
| 226 | "uxth", |
| 227 | "uxtw", |
| 228 | "uxtx", |
| 229 | "sxtb", |
| 230 | "sxth", |
| 231 | "sxtw", |
| 232 | "sxtx", |
| 233 | }; |
| 234 | |
| 235 | /* Decode and print a register extension (e.g. ", uxtb #1") */ |
| 236 | static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { |
| 237 | if ((operand & (1 << 6)) == 0) { |
| 238 | const char *shift_name = shift_names[(operand >> 7) & 0x3]; |
| 239 | int amount = operand & 0x3f; |
| 240 | snprintf(buf, buf_size, ", %s #%d", shift_name, amount); |
| 241 | } else { |
| 242 | const char *extend_name = extend_names[(operand >> 3) & 0x7]; |
| 243 | int amount = operand & 0x7; |
| 244 | if (amount == 0) { |
| 245 | snprintf(buf, buf_size, ", %s", extend_name); |
| 246 | } else { |
| 247 | snprintf(buf, buf_size, ", %s #%d", extend_name, amount); |
| 248 | } |
| 249 | } |
| 250 | } |
| 251 | |
buzbee | f77e977 | 2014-09-02 15:39:57 -0700 | [diff] [blame] | 252 | static uint64_t bit_mask(unsigned width) { |
| 253 | DCHECK_LE(width, 64U); |
| 254 | return (width == 64) ? static_cast<uint64_t>(-1) : ((UINT64_C(1) << (width)) - UINT64_C(1)); |
| 255 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 256 | |
| 257 | static uint64_t RotateRight(uint64_t value, unsigned rotate, unsigned width) { |
| 258 | DCHECK_LE(width, 64U); |
| 259 | rotate &= 63; |
buzbee | f77e977 | 2014-09-02 15:39:57 -0700 | [diff] [blame] | 260 | value = value & bit_mask(width); |
| 261 | return ((value & bit_mask(rotate)) << (width - rotate)) | (value >> rotate); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | static uint64_t RepeatBitsAcrossReg(bool is_wide, uint64_t value, unsigned width) { |
| 265 | unsigned i; |
| 266 | unsigned reg_size = (is_wide) ? 64 : 32; |
buzbee | f77e977 | 2014-09-02 15:39:57 -0700 | [diff] [blame] | 267 | uint64_t result = value & bit_mask(width); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 268 | for (i = width; i < reg_size; i *= 2) { |
| 269 | result |= (result << i); |
| 270 | } |
| 271 | DCHECK_EQ(i, reg_size); |
| 272 | return result; |
| 273 | } |
| 274 | |
| 275 | /** |
| 276 | * @brief Decode an immediate in the form required by logical instructions. |
| 277 | * |
| 278 | * @param is_wide Whether @p value encodes a 64-bit (as opposed to 32-bit) immediate. |
| 279 | * @param value The encoded logical immediates that is to be decoded. |
| 280 | * @return The decoded logical immediate. |
| 281 | * @note This is the inverse of Arm64Mir2Lir::EncodeLogicalImmediate(). |
| 282 | */ |
| 283 | uint64_t Arm64Mir2Lir::DecodeLogicalImmediate(bool is_wide, int value) { |
| 284 | unsigned n = (value >> 12) & 0x01; |
| 285 | unsigned imm_r = (value >> 6) & 0x3f; |
| 286 | unsigned imm_s = (value >> 0) & 0x3f; |
| 287 | |
| 288 | // An integer is constructed from the n, imm_s and imm_r bits according to |
| 289 | // the following table: |
| 290 | // |
| 291 | // N imms immr size S R |
| 292 | // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) |
| 293 | // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) |
| 294 | // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) |
| 295 | // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) |
| 296 | // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) |
| 297 | // 0 11110s xxxxxr 2 UInt(s) UInt(r) |
| 298 | // (s bits must not be all set) |
| 299 | // |
| 300 | // A pattern is constructed of size bits, where the least significant S+1 |
| 301 | // bits are set. The pattern is rotated right by R, and repeated across a |
| 302 | // 32 or 64-bit value, depending on destination register width. |
| 303 | |
| 304 | if (n == 1) { |
| 305 | DCHECK_NE(imm_s, 0x3fU); |
buzbee | f77e977 | 2014-09-02 15:39:57 -0700 | [diff] [blame] | 306 | uint64_t bits = bit_mask(imm_s + 1); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 307 | return RotateRight(bits, imm_r, 64); |
| 308 | } else { |
| 309 | DCHECK_NE((imm_s >> 1), 0x1fU); |
| 310 | for (unsigned width = 0x20; width >= 0x2; width >>= 1) { |
| 311 | if ((imm_s & width) == 0) { |
| 312 | unsigned mask = (unsigned)(width - 1); |
| 313 | DCHECK_NE((imm_s & mask), mask); |
buzbee | f77e977 | 2014-09-02 15:39:57 -0700 | [diff] [blame] | 314 | uint64_t bits = bit_mask((imm_s & mask) + 1); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 315 | return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 316 | } |
| 317 | } |
| 318 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 319 | return 0; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 320 | } |
| 321 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 322 | /** |
| 323 | * @brief Decode an 8-bit single point number encoded with EncodeImmSingle(). |
| 324 | */ |
| 325 | static float DecodeImmSingle(uint8_t small_float) { |
| 326 | int mantissa = (small_float & 0x0f) + 0x10; |
| 327 | int sign = ((small_float & 0x80) == 0) ? 1 : -1; |
| 328 | float signed_mantissa = static_cast<float>(sign*mantissa); |
| 329 | int exponent = (((small_float >> 4) & 0x7) + 4) & 0x7; |
| 330 | return signed_mantissa*static_cast<float>(1 << exponent)*0.0078125f; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 331 | } |
| 332 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 333 | static const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", |
| 334 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 335 | /* |
| 336 | * Interpret a format string and build a string no longer than size |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 337 | * See format key in assemble_arm64.cc. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 338 | */ |
| 339 | std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { |
| 340 | std::string buf; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 341 | const char* fmt_end = &fmt[strlen(fmt)]; |
| 342 | char tbuf[256]; |
| 343 | const char* name; |
| 344 | char nc; |
| 345 | while (fmt < fmt_end) { |
| 346 | int operand; |
| 347 | if (*fmt == '!') { |
| 348 | fmt++; |
| 349 | DCHECK_LT(fmt, fmt_end); |
| 350 | nc = *fmt++; |
| 351 | if (nc == '!') { |
| 352 | strcpy(tbuf, "!"); |
| 353 | } else { |
| 354 | DCHECK_LT(fmt, fmt_end); |
| 355 | DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U); |
| 356 | operand = lir->operands[nc-'0']; |
| 357 | switch (*fmt++) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 358 | case 'e': { |
| 359 | // Omit ", uxtw #0" in strings like "add w0, w1, w3, uxtw #0" and |
| 360 | // ", uxtx #0" in strings like "add x0, x1, x3, uxtx #0" |
| 361 | int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : |
| 362 | EncodeExtend(kA64Uxtw, 0)); |
| 363 | if (LIKELY(operand == omittable)) { |
| 364 | strcpy(tbuf, ""); |
| 365 | } else { |
| 366 | DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); |
| 367 | } |
| 368 | } |
| 369 | break; |
| 370 | case 'o': |
| 371 | // Omit ", lsl #0" |
| 372 | if (LIKELY(operand == EncodeShift(kA64Lsl, 0))) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 373 | strcpy(tbuf, ""); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 374 | } else { |
| 375 | DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 376 | } |
| 377 | break; |
| 378 | case 'B': |
| 379 | switch (operand) { |
| 380 | case kSY: |
| 381 | name = "sy"; |
| 382 | break; |
| 383 | case kST: |
| 384 | name = "st"; |
| 385 | break; |
| 386 | case kISH: |
| 387 | name = "ish"; |
| 388 | break; |
| 389 | case kISHST: |
| 390 | name = "ishst"; |
| 391 | break; |
| 392 | case kNSH: |
| 393 | name = "nsh"; |
| 394 | break; |
| 395 | case kNSHST: |
| 396 | name = "shst"; |
| 397 | break; |
| 398 | default: |
| 399 | name = "DecodeError2"; |
| 400 | break; |
| 401 | } |
| 402 | strcpy(tbuf, name); |
| 403 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 404 | case 's': |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 405 | snprintf(tbuf, arraysize(tbuf), "s%d", operand & RegStorage::kRegNumMask); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 406 | break; |
| 407 | case 'S': |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 408 | snprintf(tbuf, arraysize(tbuf), "d%d", operand & RegStorage::kRegNumMask); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 409 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 410 | case 'f': |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 411 | snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_WIDE(lir->opcode)) ? 'd' : 's', |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 412 | operand & RegStorage::kRegNumMask); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 413 | break; |
| 414 | case 'l': { |
| 415 | bool is_wide = IS_WIDE(lir->opcode); |
| 416 | uint64_t imm = DecodeLogicalImmediate(is_wide, operand); |
| 417 | snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm); |
| 418 | } |
| 419 | break; |
| 420 | case 'I': |
| 421 | snprintf(tbuf, arraysize(tbuf), "%f", DecodeImmSingle(operand)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 422 | break; |
| 423 | case 'M': |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 424 | if (LIKELY(operand == 0)) |
| 425 | strcpy(tbuf, ""); |
| 426 | else |
| 427 | snprintf(tbuf, arraysize(tbuf), ", lsl #%d", 16*operand); |
| 428 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 429 | case 'd': |
| 430 | snprintf(tbuf, arraysize(tbuf), "%d", operand); |
| 431 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 432 | case 'w': |
| 433 | if (LIKELY(operand != rwzr)) |
| 434 | snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); |
| 435 | else |
| 436 | strcpy(tbuf, "wzr"); |
| 437 | break; |
| 438 | case 'W': |
| 439 | if (LIKELY(operand != rwsp)) |
| 440 | snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); |
| 441 | else |
| 442 | strcpy(tbuf, "wsp"); |
| 443 | break; |
| 444 | case 'x': |
| 445 | if (LIKELY(operand != rxzr)) |
| 446 | snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); |
| 447 | else |
| 448 | strcpy(tbuf, "xzr"); |
| 449 | break; |
| 450 | case 'X': |
| 451 | if (LIKELY(operand != rsp)) |
| 452 | snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); |
| 453 | else |
| 454 | strcpy(tbuf, "sp"); |
| 455 | break; |
| 456 | case 'D': |
| 457 | snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 458 | break; |
| 459 | case 'E': |
| 460 | snprintf(tbuf, arraysize(tbuf), "%d", operand*4); |
| 461 | break; |
| 462 | case 'F': |
| 463 | snprintf(tbuf, arraysize(tbuf), "%d", operand*2); |
| 464 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 465 | case 'G': |
| 466 | if (LIKELY(operand == 0)) |
| 467 | strcpy(tbuf, ""); |
| 468 | else |
| 469 | strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); |
| 470 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 471 | case 'c': |
| 472 | strcpy(tbuf, cc_names[operand]); |
| 473 | break; |
| 474 | case 't': |
| 475 | snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 476 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + (operand << 2), |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 477 | lir->target); |
| 478 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 479 | case 'r': { |
| 480 | bool is_wide = IS_WIDE(lir->opcode); |
| 481 | if (LIKELY(operand != rwzr && operand != rxzr)) { |
| 482 | snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', |
| 483 | operand & RegStorage::kRegNumMask); |
| 484 | } else { |
| 485 | strcpy(tbuf, (is_wide) ? "xzr" : "wzr"); |
| 486 | } |
| 487 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 488 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 489 | case 'R': { |
| 490 | bool is_wide = IS_WIDE(lir->opcode); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 491 | if (LIKELY(operand != rwsp && operand != rsp)) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 492 | snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', |
| 493 | operand & RegStorage::kRegNumMask); |
| 494 | } else { |
| 495 | strcpy(tbuf, (is_wide) ? "sp" : "wsp"); |
| 496 | } |
| 497 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 498 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 499 | case 'p': |
| 500 | snprintf(tbuf, arraysize(tbuf), ".+%d (addr %#" PRIxPTR ")", 4*operand, |
| 501 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4*operand); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 502 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 503 | case 'T': |
| 504 | if (LIKELY(operand == 0)) |
| 505 | strcpy(tbuf, ""); |
| 506 | else if (operand == 1) |
| 507 | strcpy(tbuf, ", lsl #12"); |
| 508 | else |
| 509 | strcpy(tbuf, ", DecodeError3"); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 510 | break; |
Zheng Xu | 5d7cdec | 2014-08-18 17:28:22 +0800 | [diff] [blame] | 511 | case 'h': |
| 512 | snprintf(tbuf, arraysize(tbuf), "%d", operand); |
| 513 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 514 | default: |
| 515 | strcpy(tbuf, "DecodeError1"); |
| 516 | break; |
| 517 | } |
| 518 | buf += tbuf; |
| 519 | } |
| 520 | } else { |
| 521 | buf += *fmt++; |
| 522 | } |
| 523 | } |
| 524 | return buf; |
| 525 | } |
| 526 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 527 | void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 528 | char buf[256]; |
| 529 | buf[0] = 0; |
| 530 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 531 | if (mask.Equals(kEncodeAll)) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 532 | strcpy(buf, "all"); |
| 533 | } else { |
| 534 | char num[8]; |
| 535 | int i; |
| 536 | |
Matteo Franchin | 4163c53 | 2014-07-15 15:20:27 +0100 | [diff] [blame] | 537 | for (i = 0; i < kA64RegEnd; i++) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 538 | if (mask.HasBit(i)) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 539 | snprintf(num, arraysize(num), "%d ", i); |
| 540 | strcat(buf, num); |
| 541 | } |
| 542 | } |
| 543 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 544 | if (mask.HasBit(ResourceMask::kCCode)) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 545 | strcat(buf, "cc "); |
| 546 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 547 | if (mask.HasBit(ResourceMask::kFPStatus)) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 548 | strcat(buf, "fpcc "); |
| 549 | } |
| 550 | |
| 551 | /* Memory bits */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 552 | if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 553 | snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", |
| 554 | DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info), |
| 555 | DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : ""); |
| 556 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 557 | if (mask.HasBit(ResourceMask::kLiteral)) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 558 | strcat(buf, "lit "); |
| 559 | } |
| 560 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 561 | if (mask.HasBit(ResourceMask::kHeapRef)) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 562 | strcat(buf, "heap "); |
| 563 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 564 | if (mask.HasBit(ResourceMask::kMustNotAlias)) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 565 | strcat(buf, "noalias "); |
| 566 | } |
| 567 | } |
| 568 | if (buf[0]) { |
| 569 | LOG(INFO) << prefix << ": " << buf; |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | bool Arm64Mir2Lir::IsUnconditionalBranch(LIR* lir) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 574 | return (lir->opcode == kA64B1t); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 575 | } |
| 576 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 577 | RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { |
| 578 | if (UNLIKELY(is_volatile)) { |
| 579 | // On arm64, fp register load/store is atomic only for single bytes. |
| 580 | if (size != kSignedByte && size != kUnsignedByte) { |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 581 | return (size == kReference) ? kRefReg : kCoreReg; |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 582 | } |
| 583 | } |
| 584 | return RegClassBySize(size); |
| 585 | } |
| 586 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 587 | Arm64Mir2Lir::Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) |
Vladimir Marko | 7c2ad5a | 2014-09-24 12:42:55 +0100 | [diff] [blame] | 588 | : Mir2Lir(cu, mir_graph, arena), |
| 589 | call_method_insns_(arena->Adapter()) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 590 | // Sanity check - make sure encoding map lines up. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 591 | for (int i = 0; i < kA64Last; i++) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 592 | DCHECK_EQ(UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode), i) |
| 593 | << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name |
| 594 | << " is wrong: expecting " << i << ", seeing " |
| 595 | << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 596 | } |
| 597 | } |
| 598 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 599 | Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, |
| 600 | ArenaAllocator* const arena) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 601 | return new Arm64Mir2Lir(cu, mir_graph, arena); |
| 602 | } |
| 603 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 604 | void Arm64Mir2Lir::CompilerInitializeRegAlloc() { |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 605 | reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs, core64_regs, sp_regs, dp_regs, |
| 606 | reserved_regs, reserved64_regs, |
| 607 | core_temps, core64_temps, sp_temps, dp_temps)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 608 | |
| 609 | // Target-specific adjustments. |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 610 | // Alias single precision float registers to corresponding double registers. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 611 | for (RegisterInfo* info : reg_pool_->sp_regs_) { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 612 | int fp_reg_num = info->GetReg().GetRegNum(); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 613 | RegStorage dp_reg = RegStorage::FloatSolo64(fp_reg_num); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 614 | RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); |
| 615 | // Double precision register's master storage should refer to itself. |
| 616 | DCHECK_EQ(dp_reg_info, dp_reg_info->Master()); |
| 617 | // Redirect single precision's master storage to master. |
| 618 | info->SetMaster(dp_reg_info); |
| 619 | // Singles should show a single 32-bit mask bit, at first referring to the low half. |
| 620 | DCHECK_EQ(info->StorageMask(), 0x1U); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 621 | } |
| 622 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 623 | // Alias 32bit W registers to corresponding 64bit X registers. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 624 | for (RegisterInfo* info : reg_pool_->core_regs_) { |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 625 | int x_reg_num = info->GetReg().GetRegNum(); |
| 626 | RegStorage x_reg = RegStorage::Solo64(x_reg_num); |
| 627 | RegisterInfo* x_reg_info = GetRegInfo(x_reg); |
| 628 | // 64bit X register's master storage should refer to itself. |
| 629 | DCHECK_EQ(x_reg_info, x_reg_info->Master()); |
| 630 | // Redirect 32bit W master storage to 64bit X. |
| 631 | info->SetMaster(x_reg_info); |
| 632 | // 32bit W should show a single 32-bit mask bit, at first referring to the low half. |
| 633 | DCHECK_EQ(info->StorageMask(), 0x1U); |
| 634 | } |
| 635 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 636 | // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. |
| 637 | // TODO: adjust when we roll to hard float calling convention. |
| 638 | reg_pool_->next_core_reg_ = 2; |
| 639 | reg_pool_->next_sp_reg_ = 0; |
| 640 | reg_pool_->next_dp_reg_ = 0; |
| 641 | } |
| 642 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 643 | /* |
| 644 | * TUNING: is true leaf? Can't just use METHOD_IS_LEAF to determine as some |
| 645 | * instructions might call out to C/assembly helper functions. Until |
| 646 | * machinery is in place, always spill lr. |
| 647 | */ |
| 648 | |
| 649 | void Arm64Mir2Lir::AdjustSpillMask() { |
Zheng Xu | baa7c88 | 2014-06-30 14:26:50 +0800 | [diff] [blame] | 650 | core_spill_mask_ |= (1 << rs_xLR.GetRegNum()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 651 | num_core_spills_++; |
| 652 | } |
| 653 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 654 | /* Clobber all regs that might be used by an external C call */ |
| 655 | void Arm64Mir2Lir::ClobberCallerSave() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 656 | Clobber(rs_x0); |
| 657 | Clobber(rs_x1); |
| 658 | Clobber(rs_x2); |
| 659 | Clobber(rs_x3); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 660 | Clobber(rs_x4); |
| 661 | Clobber(rs_x5); |
| 662 | Clobber(rs_x6); |
| 663 | Clobber(rs_x7); |
| 664 | Clobber(rs_x8); |
| 665 | Clobber(rs_x9); |
| 666 | Clobber(rs_x10); |
| 667 | Clobber(rs_x11); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 668 | Clobber(rs_x12); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 669 | Clobber(rs_x13); |
| 670 | Clobber(rs_x14); |
| 671 | Clobber(rs_x15); |
| 672 | Clobber(rs_x16); |
| 673 | Clobber(rs_x17); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 674 | Clobber(rs_x30); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 675 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 676 | Clobber(rs_f0); |
| 677 | Clobber(rs_f1); |
| 678 | Clobber(rs_f2); |
| 679 | Clobber(rs_f3); |
| 680 | Clobber(rs_f4); |
| 681 | Clobber(rs_f5); |
| 682 | Clobber(rs_f6); |
| 683 | Clobber(rs_f7); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 684 | Clobber(rs_f16); |
| 685 | Clobber(rs_f17); |
| 686 | Clobber(rs_f18); |
| 687 | Clobber(rs_f19); |
| 688 | Clobber(rs_f20); |
| 689 | Clobber(rs_f21); |
| 690 | Clobber(rs_f22); |
| 691 | Clobber(rs_f23); |
| 692 | Clobber(rs_f24); |
| 693 | Clobber(rs_f25); |
| 694 | Clobber(rs_f26); |
| 695 | Clobber(rs_f27); |
| 696 | Clobber(rs_f28); |
| 697 | Clobber(rs_f29); |
| 698 | Clobber(rs_f30); |
| 699 | Clobber(rs_f31); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 700 | } |
| 701 | |
| 702 | RegLocation Arm64Mir2Lir::GetReturnWideAlt() { |
| 703 | RegLocation res = LocCReturnWide(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 704 | res.reg.SetReg(rx2); |
| 705 | res.reg.SetHighReg(rx3); |
| 706 | Clobber(rs_x2); |
| 707 | Clobber(rs_x3); |
| 708 | MarkInUse(rs_x2); |
| 709 | MarkInUse(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 710 | MarkWide(res.reg); |
| 711 | return res; |
| 712 | } |
| 713 | |
| 714 | RegLocation Arm64Mir2Lir::GetReturnAlt() { |
| 715 | RegLocation res = LocCReturn(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 716 | res.reg.SetReg(rx1); |
| 717 | Clobber(rs_x1); |
| 718 | MarkInUse(rs_x1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 719 | return res; |
| 720 | } |
| 721 | |
| 722 | /* To be used when explicitly managing register use */ |
| 723 | void Arm64Mir2Lir::LockCallTemps() { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 724 | // TODO: needs cleanup. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 725 | LockTemp(rs_x0); |
| 726 | LockTemp(rs_x1); |
| 727 | LockTemp(rs_x2); |
| 728 | LockTemp(rs_x3); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 729 | LockTemp(rs_x4); |
| 730 | LockTemp(rs_x5); |
| 731 | LockTemp(rs_x6); |
| 732 | LockTemp(rs_x7); |
| 733 | LockTemp(rs_f0); |
| 734 | LockTemp(rs_f1); |
| 735 | LockTemp(rs_f2); |
| 736 | LockTemp(rs_f3); |
| 737 | LockTemp(rs_f4); |
| 738 | LockTemp(rs_f5); |
| 739 | LockTemp(rs_f6); |
| 740 | LockTemp(rs_f7); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 741 | } |
| 742 | |
| 743 | /* To be used when explicitly managing register use */ |
| 744 | void Arm64Mir2Lir::FreeCallTemps() { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 745 | // TODO: needs cleanup. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 746 | FreeTemp(rs_x0); |
| 747 | FreeTemp(rs_x1); |
| 748 | FreeTemp(rs_x2); |
| 749 | FreeTemp(rs_x3); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 750 | FreeTemp(rs_x4); |
| 751 | FreeTemp(rs_x5); |
| 752 | FreeTemp(rs_x6); |
| 753 | FreeTemp(rs_x7); |
| 754 | FreeTemp(rs_f0); |
| 755 | FreeTemp(rs_f1); |
| 756 | FreeTemp(rs_f2); |
| 757 | FreeTemp(rs_f3); |
| 758 | FreeTemp(rs_f4); |
| 759 | FreeTemp(rs_f5); |
| 760 | FreeTemp(rs_f6); |
| 761 | FreeTemp(rs_f7); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 762 | } |
| 763 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 764 | RegStorage Arm64Mir2Lir::LoadHelper(QuickEntrypointEnum trampoline) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 765 | // TODO(Arm64): use LoadWordDisp instead. |
| 766 | // e.g. LoadWordDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR); |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 767 | LoadBaseDisp(rs_xSELF, GetThreadOffset<8>(trampoline).Int32Value(), rs_xLR, k64, kNotVolatile); |
Zheng Xu | baa7c88 | 2014-06-30 14:26:50 +0800 | [diff] [blame] | 768 | return rs_xLR; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 769 | } |
| 770 | |
| 771 | LIR* Arm64Mir2Lir::CheckSuspendUsingLoad() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 772 | RegStorage tmp = rs_x0; |
Zheng Xu | baa7c88 | 2014-06-30 14:26:50 +0800 | [diff] [blame] | 773 | LoadWordDisp(rs_xSELF, Thread::ThreadSuspendTriggerOffset<8>().Int32Value(), tmp); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 774 | LIR* load2 = LoadWordDisp(tmp, 0, tmp); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 775 | return load2; |
| 776 | } |
| 777 | |
| 778 | uint64_t Arm64Mir2Lir::GetTargetInstFlags(int opcode) { |
| 779 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 780 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 781 | } |
| 782 | |
| 783 | const char* Arm64Mir2Lir::GetTargetInstName(int opcode) { |
| 784 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 785 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 786 | } |
| 787 | |
| 788 | const char* Arm64Mir2Lir::GetTargetInstFmt(int opcode) { |
| 789 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 790 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 791 | } |
| 792 | |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 793 | RegStorage Arm64Mir2Lir::InToRegStorageArm64Mapper::GetNextReg(ShortyArg arg) { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 794 | const RegStorage coreArgMappingToPhysicalReg[] = |
| 795 | {rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7}; |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 796 | const size_t coreArgMappingToPhysicalRegSize = arraysize(coreArgMappingToPhysicalReg); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 797 | const RegStorage fpArgMappingToPhysicalReg[] = |
| 798 | {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7}; |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 799 | const size_t fpArgMappingToPhysicalRegSize = arraysize(fpArgMappingToPhysicalReg); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 800 | |
| 801 | RegStorage result = RegStorage::InvalidReg(); |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 802 | if (arg.IsFP()) { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 803 | if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 804 | DCHECK(!arg.IsRef()); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 805 | result = fpArgMappingToPhysicalReg[cur_fp_reg_++]; |
| 806 | if (result.Valid()) { |
| 807 | // TODO: switching between widths remains a bit ugly. Better way? |
| 808 | int res_reg = result.GetReg(); |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 809 | result = arg.IsWide() ? RegStorage::FloatSolo64(res_reg) : RegStorage::FloatSolo32(res_reg); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 810 | } |
| 811 | } |
| 812 | } else { |
| 813 | if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { |
| 814 | result = coreArgMappingToPhysicalReg[cur_core_reg_++]; |
| 815 | if (result.Valid()) { |
| 816 | // TODO: switching between widths remains a bit ugly. Better way? |
| 817 | int res_reg = result.GetReg(); |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 818 | DCHECK(!(arg.IsWide() && arg.IsRef())); |
| 819 | result = (arg.IsWide() || arg.IsRef()) ? |
| 820 | RegStorage::Solo64(res_reg) : RegStorage::Solo32(res_reg); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 821 | } |
| 822 | } |
| 823 | } |
| 824 | return result; |
| 825 | } |
| 826 | |
Vladimir Marko | 7c2ad5a | 2014-09-24 12:42:55 +0100 | [diff] [blame] | 827 | void Arm64Mir2Lir::InstallLiteralPools() { |
| 828 | // PC-relative calls to methods. |
| 829 | patches_.reserve(call_method_insns_.size()); |
| 830 | for (LIR* p : call_method_insns_) { |
| 831 | DCHECK_EQ(p->opcode, kA64Bl1t); |
| 832 | uint32_t target_method_idx = p->operands[1]; |
| 833 | const DexFile* target_dex_file = |
| 834 | reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); |
| 835 | |
| 836 | patches_.push_back(LinkerPatch::RelativeCodePatch(p->offset, |
| 837 | target_dex_file, target_method_idx)); |
| 838 | } |
| 839 | |
| 840 | // And do the normal processing. |
| 841 | Mir2Lir::InstallLiteralPools(); |
| 842 | } |
| 843 | |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 844 | int Arm64Mir2Lir::GenDalvikArgsBulkCopy(CallInfo* /*info*/, int /*first*/, int count) { |
| 845 | /* |
| 846 | * TODO: Improve by adding block copy for large number of arguments. For now, just |
| 847 | * copy a Dalvik vreg at a time. |
| 848 | */ |
| 849 | return count; |
| 850 | } |
| 851 | |
Ningsheng Jian | a262f77 | 2014-11-25 16:48:07 +0800 | [diff] [blame] | 852 | void Arm64Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { |
| 853 | UNUSED(bb); |
| 854 | DCHECK(MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)); |
| 855 | RegLocation rl_src[3]; |
| 856 | RegLocation rl_dest = mir_graph_->GetBadLoc(); |
| 857 | rl_src[0] = rl_src[1] = rl_src[2] = mir_graph_->GetBadLoc(); |
| 858 | ExtendedMIROpcode opcode = static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode); |
| 859 | switch (opcode) { |
| 860 | case kMirOpMaddInt: |
| 861 | case kMirOpMsubInt: |
| 862 | rl_dest = mir_graph_->GetDest(mir); |
| 863 | rl_src[0] = mir_graph_->GetSrc(mir, 0); |
| 864 | rl_src[1] = mir_graph_->GetSrc(mir, 1); |
| 865 | rl_src[2]= mir_graph_->GetSrc(mir, 2); |
| 866 | GenMaddMsubInt(rl_dest, rl_src[0], rl_src[1], rl_src[2], |
| 867 | (opcode == kMirOpMsubInt) ? true : false); |
| 868 | break; |
| 869 | case kMirOpMaddLong: |
| 870 | case kMirOpMsubLong: |
| 871 | rl_dest = mir_graph_->GetDestWide(mir); |
| 872 | rl_src[0] = mir_graph_->GetSrcWide(mir, 0); |
| 873 | rl_src[1] = mir_graph_->GetSrcWide(mir, 2); |
| 874 | rl_src[2] = mir_graph_->GetSrcWide(mir, 4); |
| 875 | GenMaddMsubLong(rl_dest, rl_src[0], rl_src[1], rl_src[2], |
| 876 | (opcode == kMirOpMsubLong) ? true : false); |
| 877 | break; |
| 878 | default: |
| 879 | LOG(FATAL) << "Unexpected opcode: " << static_cast<int>(opcode); |
| 880 | } |
| 881 | } |
| 882 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 883 | } // namespace art |