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XNNPACK Teamb455b122019-09-27 18:10:33 -07001// Copyright (c) Facebook, Inc. and its affiliates.
2// All rights reserved.
3//
4// Copyright 2019 Google LLC
5//
6// This source code is licensed under the BSD-style license found in the
7// LICENSE file in the root directory of this source tree.
8
9#pragma once
10
11#include <stddef.h>
12#include <stdint.h>
13
14#include <pthreadpool.h>
15
Marat Dukhaneeaa7bd2019-10-25 17:31:25 -070016#include <xnnpack/params.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070017#include <xnnpack/compute.h>
18
19
20enum xnn_ukernel_type {
21 xnn_ukernel_type_none = 0,
22 xnn_ukernel_type_add,
23 xnn_ukernel_type_argmax_pooling,
24 xnn_ukernel_type_average_pooling,
Marat Dukhanb1a0fc32019-12-02 19:32:02 -080025 xnn_ukernel_type_binary_elementwise,
XNNPACK Teamb455b122019-09-27 18:10:33 -070026 xnn_ukernel_type_channel_shuffle,
Marat Dukhan1f29b802020-05-15 23:46:39 -070027 xnn_ukernel_type_conv2d_hwc2chw,
XNNPACK Teamb455b122019-09-27 18:10:33 -070028 xnn_ukernel_type_dwconv,
29 xnn_ukernel_type_gemm,
30 xnn_ukernel_type_global_average_pooling,
Marat Dukhan346a9e52019-11-15 09:06:30 -080031 xnn_ukernel_type_igemm,
XNNPACK Teamb455b122019-09-27 18:10:33 -070032 xnn_ukernel_type_lut,
33 xnn_ukernel_type_max_pooling,
34 xnn_ukernel_type_pad,
35 xnn_ukernel_type_pixelwise_average_pooling,
36 xnn_ukernel_type_prelu,
Marat Dukhanfd8e6892020-01-27 15:25:25 -080037 xnn_ukernel_type_softmax,
XNNPACK Teamb455b122019-09-27 18:10:33 -070038 xnn_ukernel_type_spmm,
39 xnn_ukernel_type_subconv2d,
Marat Dukhanc3065f52020-06-04 13:33:32 -070040 xnn_ukernel_type_unary_elementwise,
XNNPACK Teamb455b122019-09-27 18:10:33 -070041 xnn_ukernel_type_unpooling,
42 xnn_ukernel_type_vmulcaddc,
43};
44
45enum xnn_operator_type {
Marat Dukhan3b59de22020-06-03 20:15:19 -070046 xnn_operator_type_invalid = 0,
Marat Dukhan5020b962020-06-08 13:30:10 -070047 xnn_operator_type_abs_nc_f32,
Frank Barchard01898c02020-06-23 21:49:50 -070048 xnn_operator_type_add_nd_f16,
Marat Dukhanb1a0fc32019-12-02 19:32:02 -080049 xnn_operator_type_add_nd_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080050 xnn_operator_type_argmax_pooling_nhwc_f32,
51 xnn_operator_type_average_pooling_nhwc_f32,
52 xnn_operator_type_average_pooling_nhwc_q8,
Marat Dukhan64e52512020-06-09 13:41:16 -070053 xnn_operator_type_bankers_rounding_nc_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080054 xnn_operator_type_channel_shuffle_nc_x32,
55 xnn_operator_type_channel_shuffle_nc_x8,
56 xnn_operator_type_clamp_nc_f32,
57 xnn_operator_type_clamp_nc_u8,
Marat Dukhan64e52512020-06-09 13:41:16 -070058 xnn_operator_type_ceiling_nc_f32,
Marat Dukhan065b11e2020-05-22 09:49:41 -070059 xnn_operator_type_constant_pad_nd_x32,
Marat Dukhan4e21b272020-06-04 18:45:01 -070060 xnn_operator_type_convolution_nchw_f32,
Frank Barchard49b4dcc2020-06-26 14:07:19 -070061 xnn_operator_type_convolution_nhwc_f16,
Marat Dukhanefc47b82019-11-18 09:25:38 -080062 xnn_operator_type_convolution_nhwc_f32,
63 xnn_operator_type_convolution_nhwc_q8,
Marat Dukhan4e21b272020-06-04 18:45:01 -070064 xnn_operator_type_copy_nc_x32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080065 xnn_operator_type_deconvolution_nhwc_f32,
66 xnn_operator_type_deconvolution_nhwc_q8,
Marat Dukhan69180502019-12-06 15:00:31 -080067 xnn_operator_type_divide_nd_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080068 xnn_operator_type_fully_connected_nc_f32,
69 xnn_operator_type_fully_connected_nc_q8,
Marat Dukhan64e52512020-06-09 13:41:16 -070070 xnn_operator_type_floor_nc_f32,
Frank Barchard7e2cbb02020-06-12 01:22:13 -070071 xnn_operator_type_global_average_pooling_nwc_f16,
Marat Dukhanefc47b82019-11-18 09:25:38 -080072 xnn_operator_type_global_average_pooling_nwc_f32,
73 xnn_operator_type_global_average_pooling_nwc_q8,
74 xnn_operator_type_global_average_pooling_ncw_f32,
75 xnn_operator_type_hardswish_nc_f32,
Marat Dukhan28813332020-06-10 18:05:38 -070076 xnn_operator_type_leaky_relu_nc_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080077 xnn_operator_type_leaky_relu_nc_q8,
78 xnn_operator_type_max_pooling_nhwc_f32,
79 xnn_operator_type_max_pooling_nhwc_u8,
Marat Dukhan79e7f842019-12-05 14:35:50 -080080 xnn_operator_type_maximum_nd_f32,
81 xnn_operator_type_minimum_nd_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080082 xnn_operator_type_multiply_nd_f32,
Marat Dukhan5020b962020-06-08 13:30:10 -070083 xnn_operator_type_negate_nc_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080084 xnn_operator_type_prelu_nc_f32,
85 xnn_operator_type_resize_bilinear_nhwc_f32,
86 xnn_operator_type_sigmoid_nc_f32,
87 xnn_operator_type_sigmoid_nc_q8,
Marat Dukhanfd8e6892020-01-27 15:25:25 -080088 xnn_operator_type_softmax_nc_f32,
89 xnn_operator_type_softmax_nc_q8,
Marat Dukhan5020b962020-06-08 13:30:10 -070090 xnn_operator_type_square_nc_f32,
Marat Dukhan6804bbd2020-06-30 19:26:11 -070091 xnn_operator_type_square_root_nc_f32,
Marat Dukhanf7399262020-06-05 10:58:44 -070092 xnn_operator_type_squared_difference_nd_f32,
Marat Dukhan05f3f6d2019-12-03 15:13:53 -080093 xnn_operator_type_subtract_nd_f32,
Marat Dukhan64e52512020-06-09 13:41:16 -070094 xnn_operator_type_truncation_nc_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080095 xnn_operator_type_unpooling_nhwc_x32,
XNNPACK Teamb455b122019-09-27 18:10:33 -070096};
97
Marat Dukhan1f29b802020-05-15 23:46:39 -070098struct xnn_ukernel_conv2d {
XNNPACK Teamb455b122019-09-27 18:10:33 -070099 union {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700100 xnn_conv_hwc2chw_ukernel_function hwc2chw_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700101 xnn_conv_hwc_ukernel_function hwc_function;
102 };
103 uint8_t output_height_tile;
104 uint8_t output_channel_tile;
105};
106
107struct xnn_ukernel_dwconv {
108 union {
Marat Dukhanaefaef32020-04-09 07:09:34 -0700109 xnn_dwconv_unipass_ukernel_function unipass_function;
110 xnn_dwconv_multipass_ukernel_function multipass_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700111 };
Marat Dukhanaefaef32020-04-09 07:09:34 -0700112 uint8_t primary_tile;
113 uint8_t incremental_tile;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700114};
115
116// Direct 2D Depthwise Convolution
117struct xnn_ukernel_dwconv2d {
118 union {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700119 xnn_dwconv_chw_ukernel_function chw_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700120 };
121 uint8_t input_width_tile;
122 uint8_t output_width_tile;
123};
124
125struct xnn_ukernel_gemm {
Marat Dukhan05702cf2020-03-26 15:41:33 -0700126 struct xnn_hmp_gemm_ukernel general_case;
127 struct xnn_hmp_gemm_ukernel mr1_case;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700128 uint8_t mr;
129 uint8_t nr;
130 uint8_t kr;
131};
132
133struct xnn_ukernel_igemm {
Marat Dukhan05702cf2020-03-26 15:41:33 -0700134 struct xnn_hmp_igemm_ukernel general_case;
135 struct xnn_hmp_igemm_ukernel mr1_case;
136 struct xnn_hmp_gemm_ukernel gemm_case;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700137 uint8_t mr;
138 uint8_t nr;
139 uint8_t kr;
140};
141
142struct xnn_ukernel_spmm {
143 xnn_spmm_ukernel_function function;
144 uint8_t mr;
145};
146
147struct xnn_ukernel_vmulcaddc {
148 xnn_vmulcaddc_ukernel_function function;
149 uint8_t mr;
150};
151
152struct xnn_ukernel {
153 enum xnn_ukernel_type type;
154 union {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700155 struct xnn_ukernel_conv2d conv2d;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700156 struct xnn_ukernel_dwconv dwconv;
157 struct xnn_ukernel_dwconv2d dwconv2d;
158 struct xnn_ukernel_gemm gemm;
159 struct xnn_ukernel_igemm igemm;
160 struct xnn_ukernel_spmm spmm;
161 struct xnn_ukernel_vmulcaddc vmulcaddc;
162 };
163};
164
165enum xnn_run_state {
166 xnn_run_state_invalid = 0,
167 xnn_run_state_ready,
168 xnn_run_state_skip,
169};
170
171struct subconvolution_params {
172 void* weights;
173 size_t w_stride;
174 const void** indirection_buffer;
175 void* output;
176 size_t slice_width;
177 size_t slice_height;
178 size_t indirection_y_stride;
179 size_t indirection_x_stride;
Marat Dukhan80fc9322019-09-29 21:06:36 -0700180 // scaled_kernel_size := kernel_size * mr * sizeof(void*).
XNNPACK Teamb455b122019-09-27 18:10:33 -0700181 size_t scaled_kernel_size;
182};
183
184struct xnn_operator {
185 size_t batch_size;
186 uint32_t padding_top;
187 uint32_t padding_right;
188 uint32_t padding_bottom;
189 uint32_t padding_left;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700190 uint32_t kernel_height;
191 uint32_t kernel_width;
192 uint32_t stride_height;
193 uint32_t stride_width;
194 uint32_t dilation_height;
195 uint32_t dilation_width;
196 uint32_t groups;
197 size_t group_channels;
198 size_t group_input_channels;
199 size_t group_output_channels;
200 size_t channels;
201
202 size_t pad_before_channels;
203 size_t pad_after_channels;
204 uint32_t pad_value;
205
206 size_t input_height;
207 size_t input_width;
208 size_t input_pixel_stride;
209 const void* input;
210 const void** indirection_buffer;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700211
212 size_t input2_pixel_stride;
213 const void* input2;
214
215 size_t output_height;
216 size_t output_width;
217 size_t output_pixel_stride;
218 void* output;
219
220 void* packed_weights;
221 // Total number of non-zero kernel elements when weights use sparse representation.
222 size_t num_nonzero_values;
223 // Total number of non-zero kernel blocks when weights use sparse representation.
224 size_t num_nonzero_blocks;
225 // Total number of output channel blocks when weights use sparse representation.
226 size_t num_output_channel_blocks;
227 // Input channel corresponding to the first non-zero kernel element.
228 size_t first_input_channel;
229
230 float input_scale;
231 float output_scale;
232 uint8_t input_zero_point;
233 uint8_t kernel_zero_point;
234 uint8_t output_zero_point;
235 uint8_t output_min;
236 uint8_t output_max;
237
238 size_t valid_batch_size;
239 size_t last_input_height;
240 size_t last_input_width;
241 const void* last_input;
Marat Dukhan69722492019-11-11 19:55:50 -0800242 size_t last_output_height;
243 size_t last_output_width;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700244 void* last_output;
245
246 void* zero_buffer;
247 void* lookup_table;
248 void* pixelwise_buffer;
249 struct subconvolution_params* subconvolution_buffer;
Marat Dukhan8440fde2019-10-24 12:46:13 -0700250 uint32_t flags;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700251
252 union {
Marat Dukhan5020b962020-06-08 13:30:10 -0700253 union xnn_f32_abs_params f32_abs;
Marat Dukhan28813332020-06-10 18:05:38 -0700254 union xnn_f32_lrelu_params f32_lrelu;
Marat Dukhan5020b962020-06-08 13:30:10 -0700255 union xnn_f32_neg_params f32_neg;
Marat Dukhan64e52512020-06-09 13:41:16 -0700256 union xnn_f32_rnd_params f32_rnd;
Marat Dukhan5868d802020-03-19 17:18:45 -0700257 // Parameters for Global Average Pooling in CHW layout
Marat Dukhanc3065f52020-06-04 13:33:32 -0700258 union xnn_f32_gavgpool_params f32_gavgpool;
259 union xnn_f32_hswish_params f32_hswish;
Frank Barchard01898c02020-06-23 21:49:50 -0700260 struct {
261 struct xnn_f16_minmax_params f16_minmax;
262 struct xnn_f16_scaleminmax_params f16_scaleminmax;
263 };
Marat Dukhan8452ff52020-04-08 20:44:58 -0700264 // Pixelwise Average Pooling normally use f32_minmax_params, but also initialize
265 // f32_scaleminmax_params in case it needs to switch to Global Average Pooling operation.
Marat Dukhan5868d802020-03-19 17:18:45 -0700266 struct {
Marat Dukhanc3065f52020-06-04 13:33:32 -0700267 union xnn_f32_minmax_params f32_minmax;
268 union xnn_f32_scaleminmax_params f32_scaleminmax;
Marat Dukhan5868d802020-03-19 17:18:45 -0700269 };
Marat Dukhanc3065f52020-06-04 13:33:32 -0700270 union xnn_f32_chw_params f32_chw;
271 union xnn_q8_add_params q8_add;
272 union xnn_q8_gemm_params q8_gemm;
Marat Dukhan5868d802020-03-19 17:18:45 -0700273 // Average Pooling normally use q8_avgpool_params, but also initialize q8_gavgpool_params in case it needs to switch
274 // to Global Average Pooling operation.
275 struct {
Marat Dukhanc3065f52020-06-04 13:33:32 -0700276 union xnn_q8_avgpool_params q8_avgpool;
277 union xnn_q8_avgpool_params q8_gavgpool;
Marat Dukhan5868d802020-03-19 17:18:45 -0700278 };
Marat Dukhanc3065f52020-06-04 13:33:32 -0700279 union xnn_u8_minmax_params u8_minmax;
280 } params;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700281 enum xnn_operator_type type;
282 struct xnn_ukernel ukernel;
283
284 struct compute_parameters compute;
285 struct compute_parameters compute2;
286 union {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700287 struct argmax_pooling_context argmax_pooling;
288 struct average_pooling_context average_pooling;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700289 struct channel_shuffle_context channel_shuffle;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700290 struct conv2d_context conv2d;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700291 struct dwconv2d_context dwconv2d;
292 struct dwconv_context dwconv;
Marat Dukhanca2733c2019-11-15 23:21:17 -0800293 struct elementwise_binary_context elementwise_binary;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700294 struct gemm_context gemm;
Marat Dukhanefc47b82019-11-18 09:25:38 -0800295 struct global_average_pooling_nwc_context global_average_pooling_nwc;
296 struct global_average_pooling_ncw_context global_average_pooling_ncw;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700297 struct igemm_context igemm;
298 struct lut_contiguous_context lut_contiguous;
299 struct lut_strided_context lut_strided;
300 struct max_pooling_context max_pooling;
Marat Dukhan4662b192020-05-21 15:52:03 -0700301 struct pad_context pad;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700302 struct pixelwise_average_pooling_context pixelwise_average_pooling;
303 struct prelu_context prelu;
Marat Dukhan69722492019-11-11 19:55:50 -0800304 struct resize_bilinear_context resize_bilinear;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700305 struct spmm_context spmm;
306 struct subconv_context subconv;
Marat Dukhan29954272020-02-13 17:56:11 -0800307 struct subgemm_context subgemm;
Marat Dukhanfd8e6892020-01-27 15:25:25 -0800308 struct f32_three_pass_softmax_context f32_three_pass_softmax;
309 struct u8_softmax_context u8_softmax;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700310 struct univector_contiguous_context univector_contiguous;
311 struct univector_strided_context univector_strided;
312 struct unpooling_context unpooling;
313 struct vmulcaddc_context vmulcaddc;
314 } context;
315
316 enum xnn_run_state state;
317};