Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 1 | /* |
Douglas Raillard | 32f0d3c | 2017-01-26 15:54:44 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 34 | #include <bl_common.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 35 | #include <context.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 36 | #include <context_mgmt.h> |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 37 | #include <interrupt_mgmt.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 38 | #include <platform.h> |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 39 | #include <platform_def.h> |
Yatharth Kochar | bbf8f6f | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 40 | #include <smcc_helpers.h> |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 41 | #include <string.h> |
Douglas Raillard | 32f0d3c | 2017-01-26 15:54:44 +0000 | [diff] [blame^] | 42 | #include <utils.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 43 | |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 44 | |
| 45 | /******************************************************************************* |
| 46 | * Context management library initialisation routine. This library is used by |
| 47 | * runtime services to share pointers to 'cpu_context' structures for the secure |
| 48 | * and non-secure states. Management of the structures and their associated |
| 49 | * memory is not done by the context management library e.g. the PSCI service |
| 50 | * manages the cpu context used for entry from and exit to the non-secure state. |
| 51 | * The Secure payload dispatcher service manages the context(s) corresponding to |
| 52 | * the secure state. It also uses this library to get access to the non-secure |
| 53 | * state cpu context pointers. |
| 54 | * Lastly, this library provides the api to make SP_EL3 point to the cpu context |
| 55 | * which will used for programming an entry into a lower EL. The same context |
| 56 | * will used to save state upon exception entry from that EL. |
| 57 | ******************************************************************************/ |
Juan Castillo | 4f2104f | 2014-06-13 17:05:10 +0100 | [diff] [blame] | 58 | void cm_init(void) |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 59 | { |
| 60 | /* |
| 61 | * The context management library has only global data to intialize, but |
| 62 | * that will be done when the BSS is zeroed out |
| 63 | */ |
| 64 | } |
| 65 | |
| 66 | /******************************************************************************* |
Soby Mathew | 12d0d00 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 67 | * The following function initializes the cpu_context 'ctx' for |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 68 | * first use, and sets the initial entrypoint state as specified by the |
| 69 | * entry_point_info structure. |
| 70 | * |
| 71 | * The security state to initialize is determined by the SECURE attribute |
| 72 | * of the entry_point_info. The function returns a pointer to the initialized |
| 73 | * context and sets this as the next context to return to. |
| 74 | * |
| 75 | * The EE and ST attributes are used to configure the endianess and secure |
Soby Mathew | 12d0d00 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 76 | * timer availability for the new execution context. |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 77 | * |
| 78 | * To prepare the register state for entry call cm_prepare_el3_exit() and |
| 79 | * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to |
| 80 | * cm_e1_sysreg_context_restore(). |
| 81 | ******************************************************************************/ |
Soby Mathew | 12d0d00 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 82 | static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 83 | { |
Soby Mathew | 12d0d00 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 84 | unsigned int security_state; |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 85 | uint32_t scr_el3; |
| 86 | el3_state_t *state; |
| 87 | gp_regs_t *gp_regs; |
| 88 | unsigned long sctlr_elx; |
| 89 | |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 90 | assert(ctx); |
| 91 | |
Soby Mathew | 12d0d00 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 92 | security_state = GET_SECURITY_STATE(ep->h.attr); |
| 93 | |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 94 | /* Clear any residual register values from the context */ |
Douglas Raillard | 32f0d3c | 2017-01-26 15:54:44 +0000 | [diff] [blame^] | 95 | zeromem(ctx, sizeof(*ctx)); |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * Base the context SCR on the current value, adjust for entry point |
| 99 | * specific requirements and set trap bits from the IMF |
| 100 | * TODO: provide the base/global SCR bits using another mechanism? |
| 101 | */ |
| 102 | scr_el3 = read_scr(); |
| 103 | scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | |
| 104 | SCR_ST_BIT | SCR_HCE_BIT); |
| 105 | |
| 106 | if (security_state != SECURE) |
| 107 | scr_el3 |= SCR_NS_BIT; |
| 108 | |
| 109 | if (GET_RW(ep->spsr) == MODE_RW_64) |
| 110 | scr_el3 |= SCR_RW_BIT; |
| 111 | |
| 112 | if (EP_GET_ST(ep->h.attr)) |
| 113 | scr_el3 |= SCR_ST_BIT; |
| 114 | |
Gerald Lejeune | adb4fcf | 2016-03-22 09:29:23 +0100 | [diff] [blame] | 115 | #ifndef HANDLE_EA_EL3_FIRST |
| 116 | /* Explicitly stop to trap aborts from lower exception levels. */ |
| 117 | scr_el3 &= ~SCR_EA_BIT; |
| 118 | #endif |
| 119 | |
Masahiro Yamada | 3d8256b | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 120 | #ifdef IMAGE_BL31 |
Yatharth Kochar | bbf8f6f | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 121 | /* |
| 122 | * IRQ/FIQ bits only need setting if interrupt routing |
| 123 | * model has been set up for BL31. |
| 124 | */ |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 125 | scr_el3 |= get_scr_el3_from_routing_model(security_state); |
Yatharth Kochar | bbf8f6f | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 126 | #endif |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * Set up SCTLR_ELx for the target exception level: |
Soren Brinkmann | 1c87351 | 2016-04-18 10:46:19 -0700 | [diff] [blame] | 130 | * EE bit is taken from the entrypoint attributes |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 131 | * M, C and I bits must be zero (as required by PSCI specification) |
| 132 | * |
| 133 | * The target exception level is based on the spsr mode requested. |
| 134 | * If execution is requested to EL2 or hyp mode, HVC is enabled |
| 135 | * via SCR_EL3.HCE. |
| 136 | * |
| 137 | * Always compute the SCTLR_EL1 value and save in the cpu_context |
| 138 | * - the EL2 registers are set up by cm_preapre_ns_entry() as they |
| 139 | * are not part of the stored cpu_context |
| 140 | * |
| 141 | * TODO: In debug builds the spsr should be validated and checked |
| 142 | * against the CPU support, security state, endianess and pc |
| 143 | */ |
| 144 | sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; |
Jens Wiklander | ae213ce | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 145 | if (GET_RW(ep->spsr) == MODE_RW_64) |
| 146 | sctlr_elx |= SCTLR_EL1_RES1; |
Soby Mathew | b7b0787 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 147 | else { |
Jens Wiklander | ae213ce | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 148 | sctlr_elx |= SCTLR_AARCH32_EL1_RES1; |
Soby Mathew | b7b0787 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 149 | /* |
| 150 | * If lower non-secure EL is AArch32, enable the CP15BEN, nTWI |
| 151 | * & nTWI bits. This aligns with SCTLR initialization on |
| 152 | * systems with an AArch32 EL3, where these bits |
| 153 | * architecturally reset to 1. |
| 154 | */ |
| 155 | if (security_state != SECURE) |
| 156 | sctlr_elx |= SCTLR_CP15BEN_BIT | SCTLR_NTWI_BIT |
| 157 | | SCTLR_NTWE_BIT; |
| 158 | } |
| 159 | |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 160 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); |
| 161 | |
| 162 | if ((GET_RW(ep->spsr) == MODE_RW_64 |
| 163 | && GET_EL(ep->spsr) == MODE_EL2) |
| 164 | || (GET_RW(ep->spsr) != MODE_RW_64 |
| 165 | && GET_M32(ep->spsr) == MODE32_hyp)) { |
| 166 | scr_el3 |= SCR_HCE_BIT; |
| 167 | } |
| 168 | |
| 169 | /* Populate EL3 state so that we've the right context before doing ERET */ |
| 170 | state = get_el3state_ctx(ctx); |
| 171 | write_ctx_reg(state, CTX_SCR_EL3, scr_el3); |
| 172 | write_ctx_reg(state, CTX_ELR_EL3, ep->pc); |
| 173 | write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); |
| 174 | |
| 175 | /* |
| 176 | * Store the X0-X7 value from the entrypoint into the context |
| 177 | * Use memcpy as we are in control of the layout of the structures |
| 178 | */ |
| 179 | gp_regs = get_gpregs_ctx(ctx); |
| 180 | memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); |
| 181 | } |
| 182 | |
| 183 | /******************************************************************************* |
Soby Mathew | 12d0d00 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 184 | * The following function initializes the cpu_context for a CPU specified by |
| 185 | * its `cpu_idx` for first use, and sets the initial entrypoint state as |
| 186 | * specified by the entry_point_info structure. |
| 187 | ******************************************************************************/ |
| 188 | void cm_init_context_by_index(unsigned int cpu_idx, |
| 189 | const entry_point_info_t *ep) |
| 190 | { |
| 191 | cpu_context_t *ctx; |
| 192 | ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); |
| 193 | cm_init_context_common(ctx, ep); |
| 194 | } |
| 195 | |
| 196 | /******************************************************************************* |
| 197 | * The following function initializes the cpu_context for the current CPU |
| 198 | * for first use, and sets the initial entrypoint state as specified by the |
| 199 | * entry_point_info structure. |
| 200 | ******************************************************************************/ |
| 201 | void cm_init_my_context(const entry_point_info_t *ep) |
| 202 | { |
| 203 | cpu_context_t *ctx; |
| 204 | ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); |
| 205 | cm_init_context_common(ctx, ep); |
| 206 | } |
| 207 | |
| 208 | /******************************************************************************* |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 209 | * Prepare the CPU system registers for first entry into secure or normal world |
| 210 | * |
| 211 | * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized |
| 212 | * If execution is requested to non-secure EL1 or svc mode, and the CPU supports |
| 213 | * EL2 then EL2 is disabled by configuring all necessary EL2 registers. |
| 214 | * For all entries, the EL1 registers are initialized from the cpu_context |
| 215 | ******************************************************************************/ |
| 216 | void cm_prepare_el3_exit(uint32_t security_state) |
| 217 | { |
| 218 | uint32_t sctlr_elx, scr_el3, cptr_el2; |
| 219 | cpu_context_t *ctx = cm_get_context(security_state); |
| 220 | |
| 221 | assert(ctx); |
| 222 | |
| 223 | if (security_state == NON_SECURE) { |
| 224 | scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); |
| 225 | if (scr_el3 & SCR_HCE_BIT) { |
| 226 | /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ |
| 227 | sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), |
| 228 | CTX_SCTLR_EL1); |
| 229 | sctlr_elx &= ~SCTLR_EE_BIT; |
| 230 | sctlr_elx |= SCTLR_EL2_RES1; |
| 231 | write_sctlr_el2(sctlr_elx); |
| 232 | } else if (read_id_aa64pfr0_el1() & |
| 233 | (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) { |
| 234 | /* EL2 present but unused, need to disable safely */ |
| 235 | |
| 236 | /* HCR_EL2 = 0, except RW bit set to match SCR_EL3 */ |
| 237 | write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); |
| 238 | |
| 239 | /* SCTLR_EL2 : can be ignored when bypassing */ |
| 240 | |
| 241 | /* CPTR_EL2 : disable all traps TCPAC, TTA, TFP */ |
| 242 | cptr_el2 = read_cptr_el2(); |
| 243 | cptr_el2 &= ~(TCPAC_BIT | TTA_BIT | TFP_BIT); |
| 244 | write_cptr_el2(cptr_el2); |
| 245 | |
| 246 | /* Enable EL1 access to timer */ |
| 247 | write_cnthctl_el2(EL1PCEN_BIT | EL1PCTEN_BIT); |
| 248 | |
Soby Mathew | 14c0526 | 2014-08-29 14:41:58 +0100 | [diff] [blame] | 249 | /* Reset CNTVOFF_EL2 */ |
| 250 | write_cntvoff_el2(0); |
| 251 | |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 252 | /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ |
| 253 | write_vpidr_el2(read_midr_el1()); |
| 254 | write_vmpidr_el2(read_mpidr_el1()); |
Sandrine Bailleux | 85d80e5 | 2015-11-25 17:00:44 +0000 | [diff] [blame] | 255 | |
| 256 | /* |
| 257 | * Reset VTTBR_EL2. |
| 258 | * Needed because cache maintenance operations depend on |
| 259 | * the VMID even when non-secure EL1&0 stage 2 address |
| 260 | * translation are disabled. |
| 261 | */ |
| 262 | write_vttbr_el2(0); |
David Cunado | 495f3d3 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 263 | /* |
| 264 | * Avoid unexpected debug traps in case where MDCR_EL2 |
| 265 | * is not completely reset by the hardware - set |
| 266 | * MDCR_EL2.HPMN to PMCR_EL0.N and zero the remaining |
| 267 | * bits. |
| 268 | * MDCR_EL2.HPMN and PMCR_EL0.N fields are the same size |
| 269 | * (5 bits) and HPMN is at offset zero within MDCR_EL2. |
| 270 | */ |
| 271 | write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS) |
| 272 | >> PMCR_EL0_N_SHIFT); |
David Cunado | 939f66d | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 273 | /* |
| 274 | * Avoid unexpected traps of non-secure access to |
| 275 | * certain system registers at EL1 or lower where |
| 276 | * HSTR_EL2 is not completely reset to zero by the |
| 277 | * hardware - zero the entire register. |
| 278 | */ |
| 279 | write_hstr_el2(0); |
| 280 | /* |
| 281 | * Reset CNTHP_CTL_EL2 to disable the EL2 physical timer |
| 282 | * and therefore prevent timer interrupts. |
| 283 | */ |
| 284 | write_cnthp_ctl_el2(0); |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 285 | } |
| 286 | } |
| 287 | |
| 288 | el1_sysregs_context_restore(get_sysregs_ctx(ctx)); |
| 289 | |
| 290 | cm_set_next_context(ctx); |
| 291 | } |
| 292 | |
| 293 | /******************************************************************************* |
Soby Mathew | fdfabec | 2014-07-04 16:02:26 +0100 | [diff] [blame] | 294 | * The next four functions are used by runtime services to save and restore |
| 295 | * EL1 context on the 'cpu_context' structure for the specified security |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 296 | * state. |
| 297 | ******************************************************************************/ |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 298 | void cm_el1_sysregs_context_save(uint32_t security_state) |
| 299 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 300 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 301 | |
Andrew Thoelke | 08ab89d | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 302 | ctx = cm_get_context(security_state); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 303 | assert(ctx); |
| 304 | |
| 305 | el1_sysregs_context_save(get_sysregs_ctx(ctx)); |
| 306 | } |
| 307 | |
| 308 | void cm_el1_sysregs_context_restore(uint32_t security_state) |
| 309 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 310 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 311 | |
Andrew Thoelke | 08ab89d | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 312 | ctx = cm_get_context(security_state); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 313 | assert(ctx); |
| 314 | |
| 315 | el1_sysregs_context_restore(get_sysregs_ctx(ctx)); |
| 316 | } |
| 317 | |
| 318 | /******************************************************************************* |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 319 | * This function populates ELR_EL3 member of 'cpu_context' pertaining to the |
| 320 | * given security state with the given entrypoint |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 321 | ******************************************************************************/ |
Soby Mathew | 4c0d039 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 322 | void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 323 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 324 | cpu_context_t *ctx; |
| 325 | el3_state_t *state; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 326 | |
Andrew Thoelke | 08ab89d | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 327 | ctx = cm_get_context(security_state); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 328 | assert(ctx); |
| 329 | |
| 330 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 331 | state = get_el3state_ctx(ctx); |
| 332 | write_ctx_reg(state, CTX_ELR_EL3, entrypoint); |
| 333 | } |
| 334 | |
| 335 | /******************************************************************************* |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 336 | * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' |
| 337 | * pertaining to the given security state |
| 338 | ******************************************************************************/ |
| 339 | void cm_set_elr_spsr_el3(uint32_t security_state, |
Soby Mathew | 4c0d039 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 340 | uintptr_t entrypoint, uint32_t spsr) |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 341 | { |
| 342 | cpu_context_t *ctx; |
| 343 | el3_state_t *state; |
| 344 | |
| 345 | ctx = cm_get_context(security_state); |
| 346 | assert(ctx); |
| 347 | |
| 348 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 349 | state = get_el3state_ctx(ctx); |
| 350 | write_ctx_reg(state, CTX_ELR_EL3, entrypoint); |
| 351 | write_ctx_reg(state, CTX_SPSR_EL3, spsr); |
| 352 | } |
| 353 | |
| 354 | /******************************************************************************* |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 355 | * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' |
| 356 | * pertaining to the given security state using the value and bit position |
| 357 | * specified in the parameters. It preserves all other bits. |
| 358 | ******************************************************************************/ |
| 359 | void cm_write_scr_el3_bit(uint32_t security_state, |
| 360 | uint32_t bit_pos, |
| 361 | uint32_t value) |
| 362 | { |
| 363 | cpu_context_t *ctx; |
| 364 | el3_state_t *state; |
| 365 | uint32_t scr_el3; |
| 366 | |
Andrew Thoelke | 08ab89d | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 367 | ctx = cm_get_context(security_state); |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 368 | assert(ctx); |
| 369 | |
| 370 | /* Ensure that the bit position is a valid one */ |
| 371 | assert((1 << bit_pos) & SCR_VALID_BIT_MASK); |
| 372 | |
| 373 | /* Ensure that the 'value' is only a bit wide */ |
| 374 | assert(value <= 1); |
| 375 | |
| 376 | /* |
| 377 | * Get the SCR_EL3 value from the cpu context, clear the desired bit |
| 378 | * and set it to its new value. |
| 379 | */ |
| 380 | state = get_el3state_ctx(ctx); |
| 381 | scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); |
| 382 | scr_el3 &= ~(1 << bit_pos); |
| 383 | scr_el3 |= value << bit_pos; |
| 384 | write_ctx_reg(state, CTX_SCR_EL3, scr_el3); |
| 385 | } |
| 386 | |
| 387 | /******************************************************************************* |
| 388 | * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the |
| 389 | * given security state. |
| 390 | ******************************************************************************/ |
| 391 | uint32_t cm_get_scr_el3(uint32_t security_state) |
| 392 | { |
| 393 | cpu_context_t *ctx; |
| 394 | el3_state_t *state; |
| 395 | |
Andrew Thoelke | 08ab89d | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 396 | ctx = cm_get_context(security_state); |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 397 | assert(ctx); |
| 398 | |
| 399 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 400 | state = get_el3state_ctx(ctx); |
| 401 | return read_ctx_reg(state, CTX_SCR_EL3); |
| 402 | } |
| 403 | |
| 404 | /******************************************************************************* |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 405 | * This function is used to program the context that's used for exception |
| 406 | * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for |
| 407 | * the required security state |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 408 | ******************************************************************************/ |
| 409 | void cm_set_next_eret_context(uint32_t security_state) |
| 410 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 411 | cpu_context_t *ctx; |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 412 | |
Andrew Thoelke | 08ab89d | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 413 | ctx = cm_get_context(security_state); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 414 | assert(ctx); |
| 415 | |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 416 | cm_set_next_context(ctx); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 417 | } |