Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1 | Arm CPU Specific Build Macros |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2 | ============================= |
| 3 | |
| 4 | |
| 5 | .. section-numbering:: |
| 6 | :suffix: . |
| 7 | |
| 8 | .. contents:: |
| 9 | |
| 10 | This document describes the various build options present in the CPU specific |
| 11 | operations framework to enable errata workarounds and to enable optimizations |
| 12 | for a specific CPU on a platform. |
| 13 | |
Dimitris Papastamos | f62ad32 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 14 | Security Vulnerability Workarounds |
| 15 | ---------------------------------- |
| 16 | |
Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 17 | TF-A exports a series of build flags which control which security |
| 18 | vulnerability workarounds should be applied at runtime. |
Dimitris Papastamos | f62ad32 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 19 | |
| 20 | - ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for |
Dimitris Papastamos | 59dc4ef | 2018-03-28 12:06:40 +0100 | [diff] [blame] | 21 | `CVE-2017-5715`_. This flag can be set to 0 by the platform if none |
| 22 | of the PEs in the system need the workaround. Setting this flag to 0 provides |
| 23 | no performance benefit for non-affected platforms, it just helps to comply |
| 24 | with the recommendation in the spec regarding workaround discovery. |
| 25 | Defaults to 1. |
Dimitris Papastamos | f62ad32 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 26 | |
Dimitris Papastamos | b8a25bb | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 27 | - ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for |
| 28 | `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep |
| 29 | the default value of 1 even on platforms that are unaffected by |
| 30 | CVE-2018-3639, in order to comply with the recommendation in the spec |
| 31 | regarding workaround discovery. |
| 32 | |
Dimitris Papastamos | fe007b2 | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 33 | - ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for |
| 34 | `CVE-2018-3639`_. This build option should be set to 1 if the target |
| 35 | platform contains at least 1 CPU that requires dynamic mitigation. |
| 36 | Defaults to 0. |
| 37 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 38 | CPU Errata Workarounds |
| 39 | ---------------------- |
| 40 | |
Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 41 | TF-A exports a series of build flags which control the errata workarounds that |
| 42 | are applied to each CPU by the reset handler. The errata details can be found |
| 43 | in the CPU specific errata documents published by Arm: |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 44 | |
| 45 | - `Cortex-A53 MPCore Software Developers Errata Notice`_ |
| 46 | - `Cortex-A57 MPCore Software Developers Errata Notice`_ |
Eleanor Bonnici | 6de9b33 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 47 | - `Cortex-A72 MPCore Software Developers Errata Notice`_ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 48 | |
| 49 | The errata workarounds are implemented for a particular revision or a set of |
| 50 | processor revisions. This is checked by the reset handler at runtime. Each |
| 51 | errata workaround is identified by its ``ID`` as specified in the processor's |
| 52 | errata notice document. The format of the define used to enable/disable the |
| 53 | errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` |
| 54 | is for example ``A57`` for the ``Cortex_A57`` CPU. |
| 55 | |
| 56 | Refer to the section *CPU errata status reporting* in |
Eleanor Bonnici | 45b52c2 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 57 | `Firmware Design guide`_ for information on how to write errata workaround |
| 58 | functions. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 59 | |
| 60 | All workarounds are disabled by default. The platform is responsible for |
| 61 | enabling these workarounds according to its requirement by defining the |
| 62 | errata workaround build flags in the platform specific makefile. In case |
| 63 | these workarounds are enabled for the wrong CPU revision then the errata |
| 64 | workaround is not applied. In the DEBUG build, this is indicated by |
| 65 | printing a warning to the crash console. |
| 66 | |
| 67 | In the current implementation, a platform which has more than 1 variant |
| 68 | with different revisions of a processor has no runtime mechanism available |
| 69 | for it to specify which errata workarounds should be enabled or not. |
| 70 | |
John Tsichritzis | 8a67718 | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 71 | The value of the build flags is 0 by default, that is, disabled. A value of 1 |
| 72 | will enable it. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 73 | |
John Tsichritzis | 8a67718 | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 74 | For Cortex-A53, the following errata build flags are defined : |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 75 | |
Ambroise Vincent | bd39370 | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 76 | - ``ERRATA_A53_819472``: This applies errata 819472 workaround to all |
| 77 | CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. |
| 78 | |
| 79 | - ``ERRATA_A53_824069``: This applies errata 824069 workaround to all |
| 80 | CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. |
| 81 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 82 | - ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 |
| 83 | CPU. This needs to be enabled only for revision <= r0p2 of the CPU. |
| 84 | |
Ambroise Vincent | bd39370 | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 85 | - ``ERRATA_A53_827319``: This applies errata 827319 workaround to all |
| 86 | CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. |
| 87 | |
Douglas Raillard | ca6b1cb | 2017-07-17 14:14:52 +0100 | [diff] [blame] | 88 | - ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and |
| 89 | link time to Cortex-A53 CPU. This needs to be enabled for some variants of |
| 90 | revision <= r0p4. This workaround can lead the linker to create ``*.stub`` |
| 91 | sections. |
| 92 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 93 | - ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 |
| 94 | CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From |
| 95 | r0p4 and onwards, this errata is enabled by default in hardware. |
| 96 | |
Douglas Raillard | ca6b1cb | 2017-07-17 14:14:52 +0100 | [diff] [blame] | 97 | - ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time |
| 98 | to Cortex-A53 CPU. This needs to be enabled for some variants of revision |
| 99 | <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections |
| 100 | which are 4kB aligned. |
| 101 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 102 | - ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 |
| 103 | CPUs. Though the erratum is present in every revision of the CPU, |
| 104 | this workaround is only applied to CPUs from r0p3 onwards, which feature |
Sandrine Bailleux | f3cacad | 2019-02-08 15:26:36 +0100 | [diff] [blame] | 105 | a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 106 | Earlier revisions of the CPU have other errata which require the same |
| 107 | workaround in software, so they should be covered anyway. |
| 108 | |
Ambroise Vincent | 1afeee9 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 109 | For Cortex-A55, the following errata build flags are defined : |
| 110 | |
| 111 | - ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 |
| 112 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 113 | |
Ambroise Vincent | a6cc661 | 2019-02-21 16:25:37 +0000 | [diff] [blame] | 114 | - ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 |
| 115 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 116 | |
Ambroise Vincent | 6ab87d2 | 2019-02-21 16:27:34 +0000 | [diff] [blame] | 117 | - ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 |
| 118 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 119 | |
Ambroise Vincent | 6e78973 | 2019-02-21 16:29:16 +0000 | [diff] [blame] | 120 | - ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 |
| 121 | CPU. This needs to be enabled only for revision <= r0p1 of the CPU. |
| 122 | |
Ambroise Vincent | 47949f3 | 2019-02-21 16:29:50 +0000 | [diff] [blame] | 123 | - ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 |
| 124 | CPU. This needs to be enabled only for revision <= r0p1 of the CPU. |
| 125 | |
John Tsichritzis | 8a67718 | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 126 | For Cortex-A57, the following errata build flags are defined : |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 127 | |
| 128 | - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 |
| 129 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 130 | |
| 131 | - ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 |
| 132 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 133 | |
| 134 | - ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 |
| 135 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 136 | |
Ambroise Vincent | 0f6fbbd | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 137 | - ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 |
| 138 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 139 | |
Ambroise Vincent | 5bd2c24 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 140 | - ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 |
| 141 | CPU. This needs to be enabled only for revision <= r0p1 of the CPU. |
| 142 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 143 | - ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 |
| 144 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 145 | |
| 146 | - ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 |
| 147 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 148 | |
| 149 | - ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 |
| 150 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 151 | |
| 152 | - ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 |
| 153 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 154 | |
| 155 | - ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 |
| 156 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 157 | |
Eleanor Bonnici | 45b52c2 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 158 | - ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 |
| 159 | CPU. This needs to be enabled only for revision <= r1p3 of the CPU. |
| 160 | |
Eleanor Bonnici | 6de9b33 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 161 | |
John Tsichritzis | 8a67718 | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 162 | For Cortex-A72, the following errata build flags are defined : |
Eleanor Bonnici | 6de9b33 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 163 | |
| 164 | - ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 |
| 165 | CPU. This needs to be enabled only for revision <= r0p3 of the CPU. |
| 166 | |
Louis Mayencourt | e6cab15 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 167 | For Cortex-A73, the following errata build flags are defined : |
| 168 | |
Louis Mayencourt | 25278ea | 2019-02-27 14:24:16 +0000 | [diff] [blame] | 169 | - ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 |
| 170 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 171 | |
Louis Mayencourt | e6cab15 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 172 | - ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 |
| 173 | CPU. This needs to be enabled only for revision <= r0p1 of the CPU. |
| 174 | |
Louis Mayencourt | 5f5d1ed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 175 | For Cortex-A75, the following errata build flags are defined : |
| 176 | |
| 177 | - ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 |
| 178 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 179 | |
Louis Mayencourt | 9855159 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 180 | - ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 |
| 181 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 182 | |
Louis Mayencourt | 508d711 | 2019-02-21 17:35:07 +0000 | [diff] [blame] | 183 | For Cortex-A76, the following errata build flags are defined : |
| 184 | |
Louis Mayencourt | 5c6aa01 | 2019-02-25 15:17:44 +0000 | [diff] [blame] | 185 | - ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 |
| 186 | CPU. This needs to be enabled only for revision <= r1p0 of the CPU. |
| 187 | |
Louis Mayencourt | 508d711 | 2019-02-21 17:35:07 +0000 | [diff] [blame] | 188 | - ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 |
| 189 | CPU. This needs to be enabled only for revision <= r2p0 of the CPU. |
| 190 | |
Louis Mayencourt | 5cc8c7b | 2019-02-25 11:37:38 +0000 | [diff] [blame] | 191 | - ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 |
| 192 | CPU. This needs to be enabled only for revision <= r2p0 of the CPU. |
| 193 | |
John Tsichritzis | 8a67718 | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 194 | DSU Errata Workarounds |
| 195 | ---------------------- |
| 196 | |
| 197 | Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ |
| 198 | Shared Unit) errata. The DSU errata details can be found in the respective Arm |
| 199 | documentation: |
| 200 | |
| 201 | - `Arm DSU Software Developers Errata Notice`_. |
| 202 | |
| 203 | Each erratum is identified by an ``ID``, as defined in the DSU errata notice |
| 204 | document. Thus, the build flags which enable/disable the errata workarounds |
| 205 | have the format ``ERRATA_DSU_<ID>``. The implementation and application logic |
| 206 | of DSU errata workarounds are similar to `CPU errata workarounds`_. |
| 207 | |
| 208 | For DSU errata, the following build flags are defined: |
| 209 | |
| 210 | - ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the |
| 211 | affected DSU configurations. This errata applies only for those DSUs that |
| 212 | contain the ACP interface **and** the DSU revision is older than r2p0 (on |
| 213 | r2p0 it is fixed). However, please note that this workaround results in |
| 214 | increased DSU power consumption on idle. |
| 215 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 216 | CPU Specific optimizations |
| 217 | -------------------------- |
| 218 | |
| 219 | This section describes some of the optimizations allowed by the CPU micro |
| 220 | architecture that can be enabled by the platform as desired. |
| 221 | |
| 222 | - ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the |
| 223 | Cortex-A57 cluster power down sequence by not flushing the Level 1 data |
| 224 | cache. The L1 data cache and the L2 unified cache are inclusive. A flush |
| 225 | of the L2 by set/way flushes any dirty lines from the L1 as well. This |
| 226 | is a known safe deviation from the Cortex-A57 TRM defined power down |
| 227 | sequence. Each Cortex-A57 based platform must make its own decision on |
| 228 | whether to use the optimization. |
| 229 | |
| 230 | - ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal |
| 231 | hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave |
| 232 | in a way most programmers expect, and will most probably result in a |
Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 233 | significant speed degradation to any code that employs them. The Armv8-A |
| 234 | architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 235 | the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this |
| 236 | flag enforces this behaviour. This needs to be enabled only for revisions |
| 237 | <= r0p3 of the CPU and is enabled by default. |
| 238 | |
| 239 | - ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as |
| 240 | ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be |
| 241 | enabled only for revisions <= r1p2 of the CPU and is enabled by default, |
| 242 | as recommended in section "4.7 Non-Temporal Loads/Stores" of the |
| 243 | `Cortex-A57 Software Optimization Guide`_. |
| 244 | |
| 245 | -------------- |
| 246 | |
Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 247 | *Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.* |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 248 | |
John Tsichritzis | af45d64 | 2018-09-04 10:56:53 +0100 | [diff] [blame] | 249 | .. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 |
| 250 | .. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 |
Paul Beesley | dd4e9a7 | 2019-02-08 16:43:05 +0000 | [diff] [blame] | 251 | .. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html |
| 252 | .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html |
Eleanor Bonnici | 6de9b33 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 253 | .. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 254 | .. _Firmware Design guide: firmware-design.rst |
| 255 | .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf |
Sandrine Bailleux | f3cacad | 2019-02-08 15:26:36 +0100 | [diff] [blame] | 256 | .. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html |