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gerrit-public.fairphone.software / platform / external / capstone / 4fe224b1ed9564d6e426e0c8ee4d327a492634b6 / . / arch / AArch64 / mapping.c
blob: cf8c8f0caf38cfedc4db03bf94b08344c5341bef [file] [log] [blame]
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1/* Capstone Unified Disassembler Engine */
2/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
3
4#include <stdio.h> // debug
5#include <string.h>
6
7#include "../../include/arm64.h"
8#include "../../utils.h"
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame^]9#include "../../cs_priv.h"
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]10
11#include "mapping.h"
12
13#define GET_INSTRINFO_ENUM
14#include "AArch64GenInstrInfo.inc"
15
16static name_map reg_name_maps[] = {
17 { ARM64_REG_INVALID, NULL },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]18 //=========
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]19 { ARM64_REG_NZCV, "nzcv"},
20 { ARM64_REG_WSP, "wsp"},
Nguyen Anh Quynhea8c5af2013-12-15 00:40:29 +0800[diff] [blame]21 { ARM64_REG_WZR, "wzr"}, // dummy data for array mapping order only
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]22 { ARM64_REG_SP, "sp"},
Nguyen Anh Quynhea8c5af2013-12-15 00:40:29 +0800[diff] [blame]23 { ARM64_REG_XZR, "xzr"}, // dummy data for array mapping order only
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]24 { ARM64_REG_B0, "b0"},
25 { ARM64_REG_B1, "b1"},
26 { ARM64_REG_B2, "b2"},
27 { ARM64_REG_B3, "b3"},
28 { ARM64_REG_B4, "b4"},
29 { ARM64_REG_B5, "b5"},
30 { ARM64_REG_B6, "b6"},
31 { ARM64_REG_B7, "b7"},
32 { ARM64_REG_B8, "b8"},
33 { ARM64_REG_B9, "b9"},
34 { ARM64_REG_B10, "b10"},
35 { ARM64_REG_B11, "b11"},
36 { ARM64_REG_B12, "b12"},
37 { ARM64_REG_B13, "b13"},
38 { ARM64_REG_B14, "b14"},
39 { ARM64_REG_B15, "b15"},
40 { ARM64_REG_B16, "b16"},
41 { ARM64_REG_B17, "b17"},
42 { ARM64_REG_B18, "b18"},
43 { ARM64_REG_B19, "b19"},
44 { ARM64_REG_B20, "b20"},
45 { ARM64_REG_B21, "b21"},
46 { ARM64_REG_B22, "b22"},
47 { ARM64_REG_B23, "b23"},
48 { ARM64_REG_B24, "b24"},
49 { ARM64_REG_B25, "b25"},
50 { ARM64_REG_B26, "b26"},
51 { ARM64_REG_B27, "b27"},
52 { ARM64_REG_B28, "b28"},
53 { ARM64_REG_B29, "b29"},
54 { ARM64_REG_B30, "b30"},
55 { ARM64_REG_B31, "b31"},
56 { ARM64_REG_D0, "d0"},
57 { ARM64_REG_D1, "d1"},
58 { ARM64_REG_D2, "d2"},
59 { ARM64_REG_D3, "d3"},
60 { ARM64_REG_D4, "d4"},
61 { ARM64_REG_D5, "d5"},
62 { ARM64_REG_D6, "d6"},
63 { ARM64_REG_D7, "d7"},
64 { ARM64_REG_D8, "d8"},
65 { ARM64_REG_D9, "d9"},
66 { ARM64_REG_D10, "d10"},
67 { ARM64_REG_D11, "d11"},
68 { ARM64_REG_D12, "d12"},
69 { ARM64_REG_D13, "d13"},
70 { ARM64_REG_D14, "d14"},
71 { ARM64_REG_D15, "d15"},
72 { ARM64_REG_D16, "d16"},
73 { ARM64_REG_D17, "d17"},
74 { ARM64_REG_D18, "d18"},
75 { ARM64_REG_D19, "d19"},
76 { ARM64_REG_D20, "d20"},
77 { ARM64_REG_D21, "d21"},
78 { ARM64_REG_D22, "d22"},
79 { ARM64_REG_D23, "d23"},
80 { ARM64_REG_D24, "d24"},
81 { ARM64_REG_D25, "d25"},
82 { ARM64_REG_D26, "d26"},
83 { ARM64_REG_D27, "d27"},
84 { ARM64_REG_D28, "d28"},
85 { ARM64_REG_D29, "d29"},
86 { ARM64_REG_D30, "d30"},
87 { ARM64_REG_D31, "d31"},
88 { ARM64_REG_H0, "h0"},
89 { ARM64_REG_H1, "h1"},
90 { ARM64_REG_H2, "h2"},
91 { ARM64_REG_H3, "h3"},
92 { ARM64_REG_H4, "h4"},
93 { ARM64_REG_H5, "h5"},
94 { ARM64_REG_H6, "h6"},
95 { ARM64_REG_H7, "h7"},
96 { ARM64_REG_H8, "h8"},
97 { ARM64_REG_H9, "h9"},
98 { ARM64_REG_H10, "h10"},
99 { ARM64_REG_H11, "h11"},
100 { ARM64_REG_H12, "h12"},
101 { ARM64_REG_H13, "h13"},
102 { ARM64_REG_H14, "h14"},
103 { ARM64_REG_H15, "h15"},
104 { ARM64_REG_H16, "h16"},
105 { ARM64_REG_H17, "h17"},
106 { ARM64_REG_H18, "h18"},
107 { ARM64_REG_H19, "h19"},
108 { ARM64_REG_H20, "h20"},
109 { ARM64_REG_H21, "h21"},
110 { ARM64_REG_H22, "h22"},
111 { ARM64_REG_H23, "h23"},
112 { ARM64_REG_H24, "h24"},
113 { ARM64_REG_H25, "h25"},
114 { ARM64_REG_H26, "h26"},
115 { ARM64_REG_H27, "h27"},
116 { ARM64_REG_H28, "h28"},
117 { ARM64_REG_H29, "h29"},
118 { ARM64_REG_H30, "h30"},
119 { ARM64_REG_H31, "h31"},
120 { ARM64_REG_Q0, "q0"},
121 { ARM64_REG_Q1, "q1"},
122 { ARM64_REG_Q2, "q2"},
123 { ARM64_REG_Q3, "q3"},
124 { ARM64_REG_Q4, "q4"},
125 { ARM64_REG_Q5, "q5"},
126 { ARM64_REG_Q6, "q6"},
127 { ARM64_REG_Q7, "q7"},
128 { ARM64_REG_Q8, "q8"},
129 { ARM64_REG_Q9, "q9"},
130 { ARM64_REG_Q10, "q10"},
131 { ARM64_REG_Q11, "q11"},
132 { ARM64_REG_Q12, "q12"},
133 { ARM64_REG_Q13, "q13"},
134 { ARM64_REG_Q14, "q14"},
135 { ARM64_REG_Q15, "q15"},
136 { ARM64_REG_Q16, "q16"},
137 { ARM64_REG_Q17, "q17"},
138 { ARM64_REG_Q18, "q18"},
139 { ARM64_REG_Q19, "q19"},
140 { ARM64_REG_Q20, "q20"},
141 { ARM64_REG_Q21, "q21"},
142 { ARM64_REG_Q22, "q22"},
143 { ARM64_REG_Q23, "q23"},
144 { ARM64_REG_Q24, "q24"},
145 { ARM64_REG_Q25, "q25"},
146 { ARM64_REG_Q26, "q26"},
147 { ARM64_REG_Q27, "q27"},
148 { ARM64_REG_Q28, "q28"},
149 { ARM64_REG_Q29, "q29"},
150 { ARM64_REG_Q30, "q30"},
151 { ARM64_REG_Q31, "q31"},
152 { ARM64_REG_S0, "s0"},
153 { ARM64_REG_S1, "s1"},
154 { ARM64_REG_S2, "s2"},
155 { ARM64_REG_S3, "s3"},
156 { ARM64_REG_S4, "s4"},
157 { ARM64_REG_S5, "s5"},
158 { ARM64_REG_S6, "s6"},
159 { ARM64_REG_S7, "s7"},
160 { ARM64_REG_S8, "s8"},
161 { ARM64_REG_S9, "s9"},
162 { ARM64_REG_S10, "s10"},
163 { ARM64_REG_S11, "s11"},
164 { ARM64_REG_S12, "s12"},
165 { ARM64_REG_S13, "s13"},
166 { ARM64_REG_S14, "s14"},
167 { ARM64_REG_S15, "s15"},
168 { ARM64_REG_S16, "s16"},
169 { ARM64_REG_S17, "s17"},
170 { ARM64_REG_S18, "s18"},
171 { ARM64_REG_S19, "s19"},
172 { ARM64_REG_S20, "s20"},
173 { ARM64_REG_S21, "s21"},
174 { ARM64_REG_S22, "s22"},
175 { ARM64_REG_S23, "s23"},
176 { ARM64_REG_S24, "s24"},
177 { ARM64_REG_S25, "s25"},
178 { ARM64_REG_S26, "s26"},
179 { ARM64_REG_S27, "s27"},
180 { ARM64_REG_S28, "s28"},
181 { ARM64_REG_S29, "s29"},
182 { ARM64_REG_S30, "s30"},
183 { ARM64_REG_S31, "s31"},
184 { ARM64_REG_W0, "w0"},
185 { ARM64_REG_W1, "w1"},
186 { ARM64_REG_W2, "w2"},
187 { ARM64_REG_W3, "w3"},
188 { ARM64_REG_W4, "w4"},
189 { ARM64_REG_W5, "w5"},
190 { ARM64_REG_W6, "w6"},
191 { ARM64_REG_W7, "w7"},
192 { ARM64_REG_W8, "w8"},
193 { ARM64_REG_W9, "w9"},
194 { ARM64_REG_W10, "w10"},
195 { ARM64_REG_W11, "w11"},
196 { ARM64_REG_W12, "w12"},
197 { ARM64_REG_W13, "w13"},
198 { ARM64_REG_W14, "w14"},
199 { ARM64_REG_W15, "w15"},
200 { ARM64_REG_W16, "w16"},
201 { ARM64_REG_W17, "w17"},
202 { ARM64_REG_W18, "w18"},
203 { ARM64_REG_W19, "w19"},
204 { ARM64_REG_W20, "w20"},
205 { ARM64_REG_W21, "w21"},
206 { ARM64_REG_W22, "w22"},
207 { ARM64_REG_W23, "w23"},
208 { ARM64_REG_W24, "w24"},
209 { ARM64_REG_W25, "w25"},
210 { ARM64_REG_W26, "w26"},
211 { ARM64_REG_W27, "w27"},
212 { ARM64_REG_W28, "w28"},
213 { ARM64_REG_W29, "w29"},
214 { ARM64_REG_W30, "w30"},
215 { ARM64_REG_X0, "x0"},
216 { ARM64_REG_X1, "x1"},
217 { ARM64_REG_X2, "x2"},
218 { ARM64_REG_X3, "x3"},
219 { ARM64_REG_X4, "x4"},
220 { ARM64_REG_X5, "x5"},
221 { ARM64_REG_X6, "x6"},
222 { ARM64_REG_X7, "x7"},
223 { ARM64_REG_X8, "x8"},
224 { ARM64_REG_X9, "x9"},
225 { ARM64_REG_X10, "x10"},
226 { ARM64_REG_X11, "x11"},
227 { ARM64_REG_X12, "x12"},
228 { ARM64_REG_X13, "x13"},
229 { ARM64_REG_X14, "x14"},
230 { ARM64_REG_X15, "x15"},
231 { ARM64_REG_X16, "x16"},
232 { ARM64_REG_X17, "x17"},
233 { ARM64_REG_X18, "x18"},
234 { ARM64_REG_X19, "x19"},
235 { ARM64_REG_X20, "x20"},
236 { ARM64_REG_X21, "x21"},
237 { ARM64_REG_X22, "x22"},
238 { ARM64_REG_X23, "x23"},
239 { ARM64_REG_X24, "x24"},
240 { ARM64_REG_X25, "x25"},
241 { ARM64_REG_X26, "x26"},
242 { ARM64_REG_X27, "x27"},
243 { ARM64_REG_X28, "x28"},
244 { ARM64_REG_X29, "x29"},
245 { ARM64_REG_X30, "x30"},
246};
247
pancakef0e4eed2013-12-11 22:14:42 +0100[diff] [blame]248const char *AArch64_reg_name(csh handle, unsigned int reg)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]249{
250 if (reg >= ARM64_REG_MAX)
251 return NULL;
252
253 return reg_name_maps[reg].name;
254}
255
256static insn_map insns[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]257 { AArch64_ABS16b, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
258 { AArch64_ABS2d, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
259 { AArch64_ABS2s, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
260 { AArch64_ABS4h, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
261 { AArch64_ABS4s, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
262 { AArch64_ABS8b, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
263 { AArch64_ABS8h, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
264 { AArch64_ABSdd, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
265 { AArch64_ADCSwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
266 { AArch64_ADCSxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
267 { AArch64_ADCwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
268 { AArch64_ADCxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
269 { AArch64_ADDHN2vvv_16b8h, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
270 { AArch64_ADDHN2vvv_4s2d, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
271 { AArch64_ADDHN2vvv_8h4s, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
272 { AArch64_ADDHNvvv_2s2d, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
273 { AArch64_ADDHNvvv_4h4s, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
274 { AArch64_ADDHNvvv_8b8h, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
275 { AArch64_ADDP_16B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
276 { AArch64_ADDP_2D, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
277 { AArch64_ADDP_2S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
278 { AArch64_ADDP_4H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
279 { AArch64_ADDP_4S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
280 { AArch64_ADDP_8B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
281 { AArch64_ADDP_8H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
282 { AArch64_ADDPvv_D_2D, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
283 { AArch64_ADDSwww_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
284 { AArch64_ADDSwww_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
285 { AArch64_ADDSwww_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
286 { AArch64_ADDSwww_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
287 { AArch64_ADDSwww_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
288 { AArch64_ADDSwww_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
289 { AArch64_ADDSwww_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
290 { AArch64_ADDSwww_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
291 { AArch64_ADDSwww_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
292 { AArch64_ADDSwww_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
293 { AArch64_ADDSwww_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
294 { AArch64_ADDSxxw_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
295 { AArch64_ADDSxxw_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
296 { AArch64_ADDSxxw_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
297 { AArch64_ADDSxxw_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
298 { AArch64_ADDSxxw_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
299 { AArch64_ADDSxxw_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
300 { AArch64_ADDSxxx_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
301 { AArch64_ADDSxxx_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
302 { AArch64_ADDSxxx_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
303 { AArch64_ADDSxxx_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
304 { AArch64_ADDSxxx_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
305 { AArch64_ADDV_1b16b, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
306 { AArch64_ADDV_1b8b, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
307 { AArch64_ADDV_1h4h, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
308 { AArch64_ADDV_1h8h, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
309 { AArch64_ADDV_1s4s, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
310 { AArch64_ADDddd, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
311 { AArch64_ADDvvv_16B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
312 { AArch64_ADDvvv_2D, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
313 { AArch64_ADDvvv_2S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
314 { AArch64_ADDvvv_4H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
315 { AArch64_ADDvvv_4S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
316 { AArch64_ADDvvv_8B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
317 { AArch64_ADDvvv_8H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
318 { AArch64_ADDwwi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
319 { AArch64_ADDwwi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
320 { AArch64_ADDwwi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
321 { AArch64_ADDwwi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
322 { AArch64_ADDwwi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
323 { AArch64_ADDwwi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
324 { AArch64_ADDwww_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
325 { AArch64_ADDwww_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
326 { AArch64_ADDwww_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
327 { AArch64_ADDwww_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
328 { AArch64_ADDwww_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
329 { AArch64_ADDwww_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
330 { AArch64_ADDwww_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
331 { AArch64_ADDwww_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
332 { AArch64_ADDwww_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
333 { AArch64_ADDwww_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
334 { AArch64_ADDwww_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
335 { AArch64_ADDxxi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
336 { AArch64_ADDxxi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
337 { AArch64_ADDxxi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
338 { AArch64_ADDxxi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
339 { AArch64_ADDxxi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
340 { AArch64_ADDxxi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
341 { AArch64_ADDxxw_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
342 { AArch64_ADDxxw_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
343 { AArch64_ADDxxw_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
344 { AArch64_ADDxxw_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
345 { AArch64_ADDxxw_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
346 { AArch64_ADDxxw_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
347 { AArch64_ADDxxx_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
348 { AArch64_ADDxxx_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
349 { AArch64_ADDxxx_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
350 { AArch64_ADDxxx_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
351 { AArch64_ADDxxx_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
352 { AArch64_ADRPxi, ARM64_INS_ADRP, { 0 }, { 0 }, { 0 }, 0, 0 },
353 { AArch64_ADRxi, ARM64_INS_ADR, { 0 }, { 0 }, { 0 }, 0, 0 },
354 { AArch64_AESD, ARM64_INS_AESD, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
355 { AArch64_AESE, ARM64_INS_AESE, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
356 { AArch64_AESIMC, ARM64_INS_AESIMC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
357 { AArch64_AESMC, ARM64_INS_AESMC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
358 { AArch64_ANDSwwi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
359 { AArch64_ANDSwww_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
360 { AArch64_ANDSwww_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
361 { AArch64_ANDSwww_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
362 { AArch64_ANDSwww_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
363 { AArch64_ANDSxxi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
364 { AArch64_ANDSxxx_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
365 { AArch64_ANDSxxx_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
366 { AArch64_ANDSxxx_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
367 { AArch64_ANDSxxx_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
368 { AArch64_ANDvvv_16B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
369 { AArch64_ANDvvv_8B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
370 { AArch64_ANDwwi, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
371 { AArch64_ANDwww_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
372 { AArch64_ANDwww_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
373 { AArch64_ANDwww_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
374 { AArch64_ANDwww_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
375 { AArch64_ANDxxi, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
376 { AArch64_ANDxxx_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
377 { AArch64_ANDxxx_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
378 { AArch64_ANDxxx_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
379 { AArch64_ANDxxx_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
380 { AArch64_ASRVwww, ARM64_INS_ASR, { 0 }, { 0 }, { 0 }, 0, 0 },
381 { AArch64_ASRVxxx, ARM64_INS_ASR, { 0 }, { 0 }, { 0 }, 0, 0 },
382 { AArch64_ASRwwi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 }, 0, 0 },
383 { AArch64_ASRxxi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 }, 0, 0 },
384 { AArch64_ATix, ARM64_INS_AT, { 0 }, { 0 }, { 0 }, 0, 0 },
385 { AArch64_BFIwwii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 }, 0, 0 },
386 { AArch64_BFIxxii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 }, 0, 0 },
387 { AArch64_BFMwwii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 }, 0, 0 },
388 { AArch64_BFMxxii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 }, 0, 0 },
389 { AArch64_BFXILwwii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 }, 0, 0 },
390 { AArch64_BFXILxxii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 }, 0, 0 },
391 { AArch64_BICSwww_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
392 { AArch64_BICSwww_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
393 { AArch64_BICSwww_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
394 { AArch64_BICSwww_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
395 { AArch64_BICSxxx_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
396 { AArch64_BICSxxx_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
397 { AArch64_BICSxxx_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
398 { AArch64_BICSxxx_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
399 { AArch64_BICvi_lsl_2S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
400 { AArch64_BICvi_lsl_4H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
401 { AArch64_BICvi_lsl_4S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
402 { AArch64_BICvi_lsl_8H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
403 { AArch64_BICvvv_16B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
404 { AArch64_BICvvv_8B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
405 { AArch64_BICwww_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
406 { AArch64_BICwww_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
407 { AArch64_BICwww_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
408 { AArch64_BICwww_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
409 { AArch64_BICxxx_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
410 { AArch64_BICxxx_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
411 { AArch64_BICxxx_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
412 { AArch64_BICxxx_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
413 { AArch64_BIFvvv_16B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
414 { AArch64_BIFvvv_8B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
415 { AArch64_BITvvv_16B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
416 { AArch64_BITvvv_8B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
417 { AArch64_BLRx, ARM64_INS_BLR, { 0 }, { ARM64_REG_X30, 0 }, { 0 }, 1, 1 },
418 { AArch64_BLimm, ARM64_INS_BL, { 0 }, { ARM64_REG_X30, 0 }, { 0 }, 1, 0 },
419 { AArch64_BRKi, ARM64_INS_BRK, { 0 }, { 0 }, { 0 }, 1, 0 },
420 { AArch64_BRx, ARM64_INS_BR, { 0 }, { 0 }, { 0 }, 1, 1 },
421 { AArch64_BSLvvv_16B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
422 { AArch64_BSLvvv_8B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
423 { AArch64_Bcc, ARM64_INS_B, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 1, 0 },
424 { AArch64_Bimm, ARM64_INS_B, { 0 }, { 0 }, { 0 }, 1, 0 },
425 { AArch64_CBNZw, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 }, 1, 0 },
426 { AArch64_CBNZx, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 }, 1, 0 },
427 { AArch64_CBZw, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 }, 1, 0 },
428 { AArch64_CBZx, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 }, 1, 0 },
429 { AArch64_CCMNwi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
430 { AArch64_CCMNww, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
431 { AArch64_CCMNxi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
432 { AArch64_CCMNxx, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
433 { AArch64_CCMPwi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
434 { AArch64_CCMPww, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
435 { AArch64_CCMPxi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
436 { AArch64_CCMPxx, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
437 { AArch64_CLREXi, ARM64_INS_CLREX, { 0 }, { 0 }, { 0 }, 0, 0 },
438 { AArch64_CLS16b, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
439 { AArch64_CLS2s, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
440 { AArch64_CLS4h, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
441 { AArch64_CLS4s, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
442 { AArch64_CLS8b, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
443 { AArch64_CLS8h, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
444 { AArch64_CLSww, ARM64_INS_CLS, { 0 }, { 0 }, { 0 }, 0, 0 },
445 { AArch64_CLSxx, ARM64_INS_CLS, { 0 }, { 0 }, { 0 }, 0, 0 },
446 { AArch64_CLZ16b, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
447 { AArch64_CLZ2s, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
448 { AArch64_CLZ4h, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
449 { AArch64_CLZ4s, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
450 { AArch64_CLZ8b, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
451 { AArch64_CLZ8h, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
452 { AArch64_CLZww, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 }, 0, 0 },
453 { AArch64_CLZxx, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 }, 0, 0 },
454 { AArch64_CMEQddd, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
455 { AArch64_CMEQddi, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
456 { AArch64_CMEQvvi_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
457 { AArch64_CMEQvvi_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
458 { AArch64_CMEQvvi_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
459 { AArch64_CMEQvvi_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
460 { AArch64_CMEQvvi_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
461 { AArch64_CMEQvvi_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
462 { AArch64_CMEQvvi_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
463 { AArch64_CMEQvvv_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
464 { AArch64_CMEQvvv_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
465 { AArch64_CMEQvvv_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
466 { AArch64_CMEQvvv_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
467 { AArch64_CMEQvvv_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
468 { AArch64_CMEQvvv_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
469 { AArch64_CMEQvvv_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
470 { AArch64_CMGEddd, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
471 { AArch64_CMGEddi, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
472 { AArch64_CMGEvvi_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
473 { AArch64_CMGEvvi_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
474 { AArch64_CMGEvvi_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
475 { AArch64_CMGEvvi_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
476 { AArch64_CMGEvvi_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
477 { AArch64_CMGEvvi_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
478 { AArch64_CMGEvvi_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
479 { AArch64_CMGEvvv_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
480 { AArch64_CMGEvvv_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
481 { AArch64_CMGEvvv_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
482 { AArch64_CMGEvvv_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
483 { AArch64_CMGEvvv_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
484 { AArch64_CMGEvvv_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
485 { AArch64_CMGEvvv_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
486 { AArch64_CMGTddd, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
487 { AArch64_CMGTddi, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
488 { AArch64_CMGTvvi_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
489 { AArch64_CMGTvvi_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
490 { AArch64_CMGTvvi_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
491 { AArch64_CMGTvvi_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
492 { AArch64_CMGTvvi_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
493 { AArch64_CMGTvvi_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
494 { AArch64_CMGTvvi_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
495 { AArch64_CMGTvvv_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
496 { AArch64_CMGTvvv_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
497 { AArch64_CMGTvvv_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
498 { AArch64_CMGTvvv_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
499 { AArch64_CMGTvvv_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
500 { AArch64_CMGTvvv_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
501 { AArch64_CMGTvvv_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
502 { AArch64_CMHIddd, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
503 { AArch64_CMHIvvv_16B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
504 { AArch64_CMHIvvv_2D, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
505 { AArch64_CMHIvvv_2S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
506 { AArch64_CMHIvvv_4H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
507 { AArch64_CMHIvvv_4S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
508 { AArch64_CMHIvvv_8B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
509 { AArch64_CMHIvvv_8H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
510 { AArch64_CMHSddd, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
511 { AArch64_CMHSvvv_16B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
512 { AArch64_CMHSvvv_2D, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
513 { AArch64_CMHSvvv_2S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
514 { AArch64_CMHSvvv_4H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
515 { AArch64_CMHSvvv_4S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
516 { AArch64_CMHSvvv_8B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
517 { AArch64_CMHSvvv_8H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
518 { AArch64_CMLEddi, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
519 { AArch64_CMLEvvi_16B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
520 { AArch64_CMLEvvi_2D, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
521 { AArch64_CMLEvvi_2S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
522 { AArch64_CMLEvvi_4H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
523 { AArch64_CMLEvvi_4S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
524 { AArch64_CMLEvvi_8B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
525 { AArch64_CMLEvvi_8H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
526 { AArch64_CMLTddi, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
527 { AArch64_CMLTvvi_16B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
528 { AArch64_CMLTvvi_2D, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
529 { AArch64_CMLTvvi_2S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
530 { AArch64_CMLTvvi_4H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
531 { AArch64_CMLTvvi_4S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
532 { AArch64_CMLTvvi_8B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
533 { AArch64_CMLTvvi_8H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
534 { AArch64_CMNww_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
535 { AArch64_CMNww_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
536 { AArch64_CMNww_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
537 { AArch64_CMNww_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
538 { AArch64_CMNww_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
539 { AArch64_CMNww_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
540 { AArch64_CMNww_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
541 { AArch64_CMNww_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
542 { AArch64_CMNww_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
543 { AArch64_CMNww_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
544 { AArch64_CMNww_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
545 { AArch64_CMNxw_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
546 { AArch64_CMNxw_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
547 { AArch64_CMNxw_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
548 { AArch64_CMNxw_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
549 { AArch64_CMNxw_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
550 { AArch64_CMNxw_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
551 { AArch64_CMNxx_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
552 { AArch64_CMNxx_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
553 { AArch64_CMNxx_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
554 { AArch64_CMNxx_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
555 { AArch64_CMNxx_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
556 { AArch64_CMPww_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
557 { AArch64_CMPww_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
558 { AArch64_CMPww_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
559 { AArch64_CMPww_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
560 { AArch64_CMPww_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
561 { AArch64_CMPww_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
562 { AArch64_CMPww_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
563 { AArch64_CMPww_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
564 { AArch64_CMPww_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
565 { AArch64_CMPww_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
566 { AArch64_CMPww_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
567 { AArch64_CMPxw_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
568 { AArch64_CMPxw_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
569 { AArch64_CMPxw_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
570 { AArch64_CMPxw_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
571 { AArch64_CMPxw_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
572 { AArch64_CMPxw_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
573 { AArch64_CMPxx_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
574 { AArch64_CMPxx_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
575 { AArch64_CMPxx_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
576 { AArch64_CMPxx_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
577 { AArch64_CMPxx_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
578 { AArch64_CMTSTddd, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
579 { AArch64_CMTSTvvv_16B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
580 { AArch64_CMTSTvvv_2D, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
581 { AArch64_CMTSTvvv_2S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
582 { AArch64_CMTSTvvv_4H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
583 { AArch64_CMTSTvvv_4S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
584 { AArch64_CMTSTvvv_8B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
585 { AArch64_CMTSTvvv_8H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
586 { AArch64_CNT16b, ARM64_INS_CNT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
587 { AArch64_CNT8b, ARM64_INS_CNT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
588 { AArch64_CRC32B_www, ARM64_INS_CRC32B, { 0 }, { 0 }, { 0 }, 0, 0 },
589 { AArch64_CRC32CB_www, ARM64_INS_CRC32CB, { 0 }, { 0 }, { 0 }, 0, 0 },
590 { AArch64_CRC32CH_www, ARM64_INS_CRC32CH, { 0 }, { 0 }, { 0 }, 0, 0 },
591 { AArch64_CRC32CW_www, ARM64_INS_CRC32CW, { 0 }, { 0 }, { 0 }, 0, 0 },
592 { AArch64_CRC32CX_wwx, ARM64_INS_CRC32CX, { 0 }, { 0 }, { 0 }, 0, 0 },
593 { AArch64_CRC32H_www, ARM64_INS_CRC32H, { 0 }, { 0 }, { 0 }, 0, 0 },
594 { AArch64_CRC32W_www, ARM64_INS_CRC32W, { 0 }, { 0 }, { 0 }, 0, 0 },
595 { AArch64_CRC32X_wwx, ARM64_INS_CRC32X, { 0 }, { 0 }, { 0 }, 0, 0 },
596 { AArch64_CSELwwwc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
597 { AArch64_CSELxxxc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
598 { AArch64_CSINCwwwc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
599 { AArch64_CSINCxxxc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
600 { AArch64_CSINVwwwc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
601 { AArch64_CSINVxxxc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
602 { AArch64_CSNEGwwwc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
603 { AArch64_CSNEGxxxc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
604 { AArch64_DCPS1i, ARM64_INS_DCPS1, { 0 }, { 0 }, { 0 }, 1, 0 },
605 { AArch64_DCPS2i, ARM64_INS_DCPS2, { 0 }, { 0 }, { 0 }, 1, 0 },
606 { AArch64_DCPS3i, ARM64_INS_DCPS3, { 0 }, { 0 }, { 0 }, 1, 0 },
607 { AArch64_DCix, ARM64_INS_DC, { 0 }, { 0 }, { 0 }, 0, 0 },
608 { AArch64_DMBi, ARM64_INS_DMB, { 0 }, { 0 }, { 0 }, 0, 0 },
609 { AArch64_DRPS, ARM64_INS_DRPS, { 0 }, { 0 }, { 0 }, 1, 1 },
610 { AArch64_DSBi, ARM64_INS_DSB, { 0 }, { 0 }, { 0 }, 0, 0 },
611 { AArch64_DUP16b, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
612 { AArch64_DUP2d, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
613 { AArch64_DUP2s, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
614 { AArch64_DUP4h, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
615 { AArch64_DUP4s, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
616 { AArch64_DUP8b, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
617 { AArch64_DUP8h, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
618 { AArch64_DUPELT16b, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
619 { AArch64_DUPELT2d, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
620 { AArch64_DUPELT2s, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
621 { AArch64_DUPELT4h, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
622 { AArch64_DUPELT4s, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
623 { AArch64_DUPELT8b, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
624 { AArch64_DUPELT8h, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
625 { AArch64_DUPbv_B, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
626 { AArch64_DUPdv_D, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
627 { AArch64_DUPhv_H, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
628 { AArch64_DUPsv_S, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
629 { AArch64_EONwww_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
630 { AArch64_EONwww_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
631 { AArch64_EONwww_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
632 { AArch64_EONwww_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
633 { AArch64_EONxxx_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
634 { AArch64_EONxxx_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
635 { AArch64_EONxxx_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
636 { AArch64_EONxxx_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
637 { AArch64_EORvvv_16B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
638 { AArch64_EORvvv_8B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
639 { AArch64_EORwwi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
640 { AArch64_EORwww_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
641 { AArch64_EORwww_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
642 { AArch64_EORwww_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
643 { AArch64_EORwww_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
644 { AArch64_EORxxi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
645 { AArch64_EORxxx_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
646 { AArch64_EORxxx_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
647 { AArch64_EORxxx_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
648 { AArch64_EORxxx_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
649 { AArch64_ERET, ARM64_INS_ERET, { 0 }, { 0 }, { 0 }, 1, 1 },
650 { AArch64_EXTRwwwi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 }, 0, 0 },
651 { AArch64_EXTRxxxi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 }, 0, 0 },
652 { AArch64_EXTvvvi_16b, ARM64_INS_EXT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
653 { AArch64_EXTvvvi_8b, ARM64_INS_EXT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
654 { AArch64_FABDddd, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
655 { AArch64_FABDsss, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
656 { AArch64_FABDvvv_2D, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
657 { AArch64_FABDvvv_2S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
658 { AArch64_FABDvvv_4S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
659 { AArch64_FABS2d, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
660 { AArch64_FABS2s, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
661 { AArch64_FABS4s, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
662 { AArch64_FABSdd, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
663 { AArch64_FABSss, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
664 { AArch64_FACGEddd, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
665 { AArch64_FACGEsss, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
666 { AArch64_FACGEvvv_2D, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
667 { AArch64_FACGEvvv_2S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
668 { AArch64_FACGEvvv_4S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
669 { AArch64_FACGTddd, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
670 { AArch64_FACGTsss, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
671 { AArch64_FACGTvvv_2D, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
672 { AArch64_FACGTvvv_2S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
673 { AArch64_FACGTvvv_4S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
674 { AArch64_FADDP_2D, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
675 { AArch64_FADDP_2S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
676 { AArch64_FADDP_4S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
677 { AArch64_FADDPvv_D_2D, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
678 { AArch64_FADDPvv_S_2S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
679 { AArch64_FADDddd, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
680 { AArch64_FADDsss, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
681 { AArch64_FADDvvv_2D, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
682 { AArch64_FADDvvv_2S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
683 { AArch64_FADDvvv_4S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
684 { AArch64_FCCMPEdd, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
685 { AArch64_FCCMPEss, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
686 { AArch64_FCCMPdd, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
687 { AArch64_FCCMPss, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
688 { AArch64_FCMEQZddi, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
689 { AArch64_FCMEQZssi, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
690 { AArch64_FCMEQddd, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
691 { AArch64_FCMEQsss, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
692 { AArch64_FCMEQvvi_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
693 { AArch64_FCMEQvvi_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
694 { AArch64_FCMEQvvi_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
695 { AArch64_FCMEQvvv_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
696 { AArch64_FCMEQvvv_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
697 { AArch64_FCMEQvvv_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
698 { AArch64_FCMGEZddi, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
699 { AArch64_FCMGEZssi, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
700 { AArch64_FCMGEddd, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
701 { AArch64_FCMGEsss, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
702 { AArch64_FCMGEvvi_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
703 { AArch64_FCMGEvvi_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
704 { AArch64_FCMGEvvi_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
705 { AArch64_FCMGEvvv_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
706 { AArch64_FCMGEvvv_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
707 { AArch64_FCMGEvvv_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
708 { AArch64_FCMGTZddi, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
709 { AArch64_FCMGTZssi, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
710 { AArch64_FCMGTddd, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
711 { AArch64_FCMGTsss, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
712 { AArch64_FCMGTvvi_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
713 { AArch64_FCMGTvvi_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
714 { AArch64_FCMGTvvi_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
715 { AArch64_FCMGTvvv_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
716 { AArch64_FCMGTvvv_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
717 { AArch64_FCMGTvvv_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
718 { AArch64_FCMLEZddi, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
719 { AArch64_FCMLEZssi, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
720 { AArch64_FCMLEvvi_2D, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
721 { AArch64_FCMLEvvi_2S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
722 { AArch64_FCMLEvvi_4S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
723 { AArch64_FCMLTZddi, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
724 { AArch64_FCMLTZssi, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
725 { AArch64_FCMLTvvi_2D, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
726 { AArch64_FCMLTvvi_2S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
727 { AArch64_FCMLTvvi_4S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
728 { AArch64_FCMPdd_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
729 { AArch64_FCMPdd_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
730 { AArch64_FCMPdi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
731 { AArch64_FCMPdi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
732 { AArch64_FCMPsi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
733 { AArch64_FCMPsi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
734 { AArch64_FCMPss_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
735 { AArch64_FCMPss_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
736 { AArch64_FCSELdddc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
737 { AArch64_FCSELsssc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
738 { AArch64_FCVTAS_2d, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
739 { AArch64_FCVTAS_2s, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
740 { AArch64_FCVTAS_4s, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
741 { AArch64_FCVTASdd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
742 { AArch64_FCVTASss, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
743 { AArch64_FCVTASwd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
744 { AArch64_FCVTASws, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
745 { AArch64_FCVTASxd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
746 { AArch64_FCVTASxs, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
747 { AArch64_FCVTAU_2d, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
748 { AArch64_FCVTAU_2s, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
749 { AArch64_FCVTAU_4s, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
750 { AArch64_FCVTAUdd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
751 { AArch64_FCVTAUss, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
752 { AArch64_FCVTAUwd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
753 { AArch64_FCVTAUws, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
754 { AArch64_FCVTAUxd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
755 { AArch64_FCVTAUxs, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
756 { AArch64_FCVTL2s2d, ARM64_INS_FCVTL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
757 { AArch64_FCVTL4h4s, ARM64_INS_FCVTL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
758 { AArch64_FCVTL4s2d, ARM64_INS_FCVTL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
759 { AArch64_FCVTL8h4s, ARM64_INS_FCVTL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
760 { AArch64_FCVTMS_2d, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
761 { AArch64_FCVTMS_2s, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
762 { AArch64_FCVTMS_4s, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
763 { AArch64_FCVTMSdd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
764 { AArch64_FCVTMSss, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
765 { AArch64_FCVTMSwd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
766 { AArch64_FCVTMSws, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
767 { AArch64_FCVTMSxd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
768 { AArch64_FCVTMSxs, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
769 { AArch64_FCVTMU_2d, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
770 { AArch64_FCVTMU_2s, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
771 { AArch64_FCVTMU_4s, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
772 { AArch64_FCVTMUdd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
773 { AArch64_FCVTMUss, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
774 { AArch64_FCVTMUwd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
775 { AArch64_FCVTMUws, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
776 { AArch64_FCVTMUxd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
777 { AArch64_FCVTMUxs, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
778 { AArch64_FCVTN2d2s, ARM64_INS_FCVTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
779 { AArch64_FCVTN2d4s, ARM64_INS_FCVTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
780 { AArch64_FCVTN4s4h, ARM64_INS_FCVTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
781 { AArch64_FCVTN4s8h, ARM64_INS_FCVTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
782 { AArch64_FCVTNS_2d, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
783 { AArch64_FCVTNS_2s, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
784 { AArch64_FCVTNS_4s, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
785 { AArch64_FCVTNSdd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
786 { AArch64_FCVTNSss, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
787 { AArch64_FCVTNSwd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
788 { AArch64_FCVTNSws, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
789 { AArch64_FCVTNSxd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
790 { AArch64_FCVTNSxs, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
791 { AArch64_FCVTNU_2d, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
792 { AArch64_FCVTNU_2s, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
793 { AArch64_FCVTNU_4s, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
794 { AArch64_FCVTNUdd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
795 { AArch64_FCVTNUss, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
796 { AArch64_FCVTNUwd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
797 { AArch64_FCVTNUws, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
798 { AArch64_FCVTNUxd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
799 { AArch64_FCVTNUxs, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
800 { AArch64_FCVTPS_2d, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
801 { AArch64_FCVTPS_2s, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
802 { AArch64_FCVTPS_4s, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
803 { AArch64_FCVTPSdd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
804 { AArch64_FCVTPSss, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
805 { AArch64_FCVTPSwd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
806 { AArch64_FCVTPSws, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
807 { AArch64_FCVTPSxd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
808 { AArch64_FCVTPSxs, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
809 { AArch64_FCVTPU_2d, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
810 { AArch64_FCVTPU_2s, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
811 { AArch64_FCVTPU_4s, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
812 { AArch64_FCVTPUdd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
813 { AArch64_FCVTPUss, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
814 { AArch64_FCVTPUwd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
815 { AArch64_FCVTPUws, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
816 { AArch64_FCVTPUxd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
817 { AArch64_FCVTPUxs, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
818 { AArch64_FCVTXN, ARM64_INS_FCVTXN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
819 { AArch64_FCVTXN2d2s, ARM64_INS_FCVTXN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
820 { AArch64_FCVTXN2d4s, ARM64_INS_FCVTXN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
821 { AArch64_FCVTZS_2d, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
822 { AArch64_FCVTZS_2s, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
823 { AArch64_FCVTZS_4s, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
824 { AArch64_FCVTZS_Nddi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
825 { AArch64_FCVTZS_Nssi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
826 { AArch64_FCVTZSdd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
827 { AArch64_FCVTZSss, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
828 { AArch64_FCVTZSwd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
829 { AArch64_FCVTZSwdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
830 { AArch64_FCVTZSws, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
831 { AArch64_FCVTZSwsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
832 { AArch64_FCVTZSxd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
833 { AArch64_FCVTZSxdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
834 { AArch64_FCVTZSxs, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
835 { AArch64_FCVTZSxsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
836 { AArch64_FCVTZU_2d, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
837 { AArch64_FCVTZU_2s, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
838 { AArch64_FCVTZU_4s, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
839 { AArch64_FCVTZU_Nddi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
840 { AArch64_FCVTZU_Nssi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
841 { AArch64_FCVTZUdd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
842 { AArch64_FCVTZUss, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
843 { AArch64_FCVTZUwd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
844 { AArch64_FCVTZUwdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
845 { AArch64_FCVTZUws, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
846 { AArch64_FCVTZUwsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
847 { AArch64_FCVTZUxd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
848 { AArch64_FCVTZUxdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
849 { AArch64_FCVTZUxs, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
850 { AArch64_FCVTZUxsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
851 { AArch64_FCVTdh, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
852 { AArch64_FCVTds, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
853 { AArch64_FCVThd, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
854 { AArch64_FCVThs, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
855 { AArch64_FCVTsd, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
856 { AArch64_FCVTsh, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
857 { AArch64_FDIVddd, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
858 { AArch64_FDIVsss, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
859 { AArch64_FDIVvvv_2D, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
860 { AArch64_FDIVvvv_2S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
861 { AArch64_FDIVvvv_4S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
862 { AArch64_FMADDdddd, ARM64_INS_FMADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
863 { AArch64_FMADDssss, ARM64_INS_FMADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
864 { AArch64_FMAXNMPvv_D_2D, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
865 { AArch64_FMAXNMPvv_S_2S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
866 { AArch64_FMAXNMPvvv_2D, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
867 { AArch64_FMAXNMPvvv_2S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
868 { AArch64_FMAXNMPvvv_4S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
869 { AArch64_FMAXNMV_1s4s, ARM64_INS_FMAXNMV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
870 { AArch64_FMAXNMddd, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
871 { AArch64_FMAXNMsss, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
872 { AArch64_FMAXNMvvv_2D, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
873 { AArch64_FMAXNMvvv_2S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
874 { AArch64_FMAXNMvvv_4S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
875 { AArch64_FMAXPvv_D_2D, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
876 { AArch64_FMAXPvv_S_2S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
877 { AArch64_FMAXPvvv_2D, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
878 { AArch64_FMAXPvvv_2S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
879 { AArch64_FMAXPvvv_4S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
880 { AArch64_FMAXV_1s4s, ARM64_INS_FMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
881 { AArch64_FMAXddd, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
882 { AArch64_FMAXsss, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
883 { AArch64_FMAXvvv_2D, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
884 { AArch64_FMAXvvv_2S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
885 { AArch64_FMAXvvv_4S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
886 { AArch64_FMINNMPvv_D_2D, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
887 { AArch64_FMINNMPvv_S_2S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
888 { AArch64_FMINNMPvvv_2D, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
889 { AArch64_FMINNMPvvv_2S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
890 { AArch64_FMINNMPvvv_4S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
891 { AArch64_FMINNMV_1s4s, ARM64_INS_FMINNMV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
892 { AArch64_FMINNMddd, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
893 { AArch64_FMINNMsss, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
894 { AArch64_FMINNMvvv_2D, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
895 { AArch64_FMINNMvvv_2S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
896 { AArch64_FMINNMvvv_4S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
897 { AArch64_FMINPvv_D_2D, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
898 { AArch64_FMINPvv_S_2S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
899 { AArch64_FMINPvvv_2D, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
900 { AArch64_FMINPvvv_2S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
901 { AArch64_FMINPvvv_4S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
902 { AArch64_FMINV_1s4s, ARM64_INS_FMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
903 { AArch64_FMINddd, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
904 { AArch64_FMINsss, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
905 { AArch64_FMINvvv_2D, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
906 { AArch64_FMINvvv_2S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
907 { AArch64_FMINvvv_4S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
908 { AArch64_FMLAddv_2D, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
909 { AArch64_FMLAssv_4S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
910 { AArch64_FMLAvve_2d2d, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
911 { AArch64_FMLAvve_2s4s, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
912 { AArch64_FMLAvve_4s4s, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
913 { AArch64_FMLAvvv_2D, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
914 { AArch64_FMLAvvv_2S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
915 { AArch64_FMLAvvv_4S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
916 { AArch64_FMLSddv_2D, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
917 { AArch64_FMLSssv_4S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
918 { AArch64_FMLSvve_2d2d, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
919 { AArch64_FMLSvve_2s4s, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
920 { AArch64_FMLSvve_4s4s, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
921 { AArch64_FMLSvvv_2D, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
922 { AArch64_FMLSvvv_2S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
923 { AArch64_FMLSvvv_4S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
924 { AArch64_FMOVdd, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
925 { AArch64_FMOVdi, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
926 { AArch64_FMOVdx, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
927 { AArch64_FMOVsi, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
928 { AArch64_FMOVss, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
929 { AArch64_FMOVsw, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
930 { AArch64_FMOVvi_2D, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
931 { AArch64_FMOVvi_2S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
932 { AArch64_FMOVvi_4S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
933 { AArch64_FMOVvx, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
934 { AArch64_FMOVws, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
935 { AArch64_FMOVxd, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
936 { AArch64_FMOVxv, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
937 { AArch64_FMSUBdddd, ARM64_INS_FMSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
938 { AArch64_FMSUBssss, ARM64_INS_FMSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
939 { AArch64_FMULXddd, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
940 { AArch64_FMULXddv_2D, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
941 { AArch64_FMULXsss, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
942 { AArch64_FMULXssv_4S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
943 { AArch64_FMULXve_2d2d, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
944 { AArch64_FMULXve_2s4s, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
945 { AArch64_FMULXve_4s4s, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
946 { AArch64_FMULXvvv_2D, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
947 { AArch64_FMULXvvv_2S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
948 { AArch64_FMULXvvv_4S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
949 { AArch64_FMULddd, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
950 { AArch64_FMULddv_2D, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
951 { AArch64_FMULsss, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
952 { AArch64_FMULssv_4S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
953 { AArch64_FMULve_2d2d, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
954 { AArch64_FMULve_2s4s, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
955 { AArch64_FMULve_4s4s, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
956 { AArch64_FMULvvv_2D, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
957 { AArch64_FMULvvv_2S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
958 { AArch64_FMULvvv_4S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
959 { AArch64_FNEG2d, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
960 { AArch64_FNEG2s, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
961 { AArch64_FNEG4s, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
962 { AArch64_FNEGdd, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
963 { AArch64_FNEGss, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
964 { AArch64_FNMADDdddd, ARM64_INS_FNMADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
965 { AArch64_FNMADDssss, ARM64_INS_FNMADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
966 { AArch64_FNMSUBdddd, ARM64_INS_FNMSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
967 { AArch64_FNMSUBssss, ARM64_INS_FNMSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
968 { AArch64_FNMULddd, ARM64_INS_FNMUL, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
969 { AArch64_FNMULsss, ARM64_INS_FNMUL, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
970 { AArch64_FRECPE_2d, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
971 { AArch64_FRECPE_2s, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
972 { AArch64_FRECPE_4s, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
973 { AArch64_FRECPEdd, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
974 { AArch64_FRECPEss, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
975 { AArch64_FRECPSddd, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
976 { AArch64_FRECPSsss, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
977 { AArch64_FRECPSvvv_2D, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
978 { AArch64_FRECPSvvv_2S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
979 { AArch64_FRECPSvvv_4S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
980 { AArch64_FRECPXdd, ARM64_INS_FRECPX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
981 { AArch64_FRECPXss, ARM64_INS_FRECPX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
982 { AArch64_FRINTA_2d, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
983 { AArch64_FRINTA_2s, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
984 { AArch64_FRINTA_4s, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
985 { AArch64_FRINTAdd, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
986 { AArch64_FRINTAss, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
987 { AArch64_FRINTI_2d, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
988 { AArch64_FRINTI_2s, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
989 { AArch64_FRINTI_4s, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
990 { AArch64_FRINTIdd, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
991 { AArch64_FRINTIss, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
992 { AArch64_FRINTM_2d, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
993 { AArch64_FRINTM_2s, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
994 { AArch64_FRINTM_4s, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
995 { AArch64_FRINTMdd, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
996 { AArch64_FRINTMss, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
997 { AArch64_FRINTN_2d, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
998 { AArch64_FRINTN_2s, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
999 { AArch64_FRINTN_4s, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1000 { AArch64_FRINTNdd, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1001 { AArch64_FRINTNss, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1002 { AArch64_FRINTP_2d, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1003 { AArch64_FRINTP_2s, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1004 { AArch64_FRINTP_4s, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1005 { AArch64_FRINTPdd, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1006 { AArch64_FRINTPss, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1007 { AArch64_FRINTX_2d, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1008 { AArch64_FRINTX_2s, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1009 { AArch64_FRINTX_4s, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1010 { AArch64_FRINTXdd, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1011 { AArch64_FRINTXss, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1012 { AArch64_FRINTZ_2d, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1013 { AArch64_FRINTZ_2s, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1014 { AArch64_FRINTZ_4s, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1015 { AArch64_FRINTZdd, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1016 { AArch64_FRINTZss, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1017 { AArch64_FRSQRTE_2d, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1018 { AArch64_FRSQRTE_2s, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1019 { AArch64_FRSQRTE_4s, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1020 { AArch64_FRSQRTEdd, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1021 { AArch64_FRSQRTEss, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1022 { AArch64_FRSQRTSddd, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1023 { AArch64_FRSQRTSsss, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1024 { AArch64_FRSQRTSvvv_2D, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1025 { AArch64_FRSQRTSvvv_2S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1026 { AArch64_FRSQRTSvvv_4S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1027 { AArch64_FSQRT_2d, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1028 { AArch64_FSQRT_2s, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1029 { AArch64_FSQRT_4s, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1030 { AArch64_FSQRTdd, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1031 { AArch64_FSQRTss, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1032 { AArch64_FSUBddd, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1033 { AArch64_FSUBsss, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1034 { AArch64_FSUBvvv_2D, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1035 { AArch64_FSUBvvv_2S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1036 { AArch64_FSUBvvv_4S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1037 { AArch64_HINTi, ARM64_INS_HINT, { 0 }, { 0 }, { 0 }, 0, 0 },
1038 { AArch64_HLTi, ARM64_INS_HLT, { 0 }, { 0 }, { 0 }, 1, 0 },
1039 { AArch64_HVCi, ARM64_INS_HVC, { 0 }, { 0 }, { 0 }, 1, 0 },
1040 { AArch64_ICi, ARM64_INS_IC, { 0 }, { 0 }, { 0 }, 0, 0 },
1041 { AArch64_ICix, ARM64_INS_IC, { 0 }, { 0 }, { 0 }, 0, 0 },
1042 { AArch64_INSELb, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1043 { AArch64_INSELd, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1044 { AArch64_INSELh, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1045 { AArch64_INSELs, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1046 { AArch64_INSbw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1047 { AArch64_INSdx, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1048 { AArch64_INShw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1049 { AArch64_INSsw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1050 { AArch64_ISBi, ARM64_INS_ISB, { 0 }, { 0 }, { 0 }, 0, 0 },
1051 { AArch64_LD1LN_B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1052 { AArch64_LD1LN_D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1053 { AArch64_LD1LN_H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1054 { AArch64_LD1LN_S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1055 { AArch64_LD1LN_WB_B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1056 { AArch64_LD1LN_WB_B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1057 { AArch64_LD1LN_WB_D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1058 { AArch64_LD1LN_WB_D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1059 { AArch64_LD1LN_WB_H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1060 { AArch64_LD1LN_WB_H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1061 { AArch64_LD1LN_WB_S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1062 { AArch64_LD1LN_WB_S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1063 { AArch64_LD1R_16B, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1064 { AArch64_LD1R_1D, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1065 { AArch64_LD1R_2D, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1066 { AArch64_LD1R_2S, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1067 { AArch64_LD1R_4H, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1068 { AArch64_LD1R_4S, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1069 { AArch64_LD1R_8B, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1070 { AArch64_LD1R_8H, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1071 { AArch64_LD1R_WB_16B_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1072 { AArch64_LD1R_WB_16B_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1073 { AArch64_LD1R_WB_1D_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1074 { AArch64_LD1R_WB_1D_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1075 { AArch64_LD1R_WB_2D_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1076 { AArch64_LD1R_WB_2D_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1077 { AArch64_LD1R_WB_2S_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1078 { AArch64_LD1R_WB_2S_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1079 { AArch64_LD1R_WB_4H_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1080 { AArch64_LD1R_WB_4H_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1081 { AArch64_LD1R_WB_4S_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1082 { AArch64_LD1R_WB_4S_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1083 { AArch64_LD1R_WB_8B_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1084 { AArch64_LD1R_WB_8B_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1085 { AArch64_LD1R_WB_8H_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1086 { AArch64_LD1R_WB_8H_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1087 { AArch64_LD1WB_16B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1088 { AArch64_LD1WB_16B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1089 { AArch64_LD1WB_1D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1090 { AArch64_LD1WB_1D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1091 { AArch64_LD1WB_2D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1092 { AArch64_LD1WB_2D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1093 { AArch64_LD1WB_2S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1094 { AArch64_LD1WB_2S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1095 { AArch64_LD1WB_4H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1096 { AArch64_LD1WB_4H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1097 { AArch64_LD1WB_4S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1098 { AArch64_LD1WB_4S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1099 { AArch64_LD1WB_8B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1100 { AArch64_LD1WB_8B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1101 { AArch64_LD1WB_8H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1102 { AArch64_LD1WB_8H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1103 { AArch64_LD1_16B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1104 { AArch64_LD1_1D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1105 { AArch64_LD1_2D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1106 { AArch64_LD1_2S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1107 { AArch64_LD1_4H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1108 { AArch64_LD1_4S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1109 { AArch64_LD1_8B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1110 { AArch64_LD1_8H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1111 { AArch64_LD1x2WB_16B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1112 { AArch64_LD1x2WB_16B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1113 { AArch64_LD1x2WB_1D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1114 { AArch64_LD1x2WB_1D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1115 { AArch64_LD1x2WB_2D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1116 { AArch64_LD1x2WB_2D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1117 { AArch64_LD1x2WB_2S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1118 { AArch64_LD1x2WB_2S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1119 { AArch64_LD1x2WB_4H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1120 { AArch64_LD1x2WB_4H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1121 { AArch64_LD1x2WB_4S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1122 { AArch64_LD1x2WB_4S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1123 { AArch64_LD1x2WB_8B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1124 { AArch64_LD1x2WB_8B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1125 { AArch64_LD1x2WB_8H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1126 { AArch64_LD1x2WB_8H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1127 { AArch64_LD1x2_16B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1128 { AArch64_LD1x2_1D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1129 { AArch64_LD1x2_2D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1130 { AArch64_LD1x2_2S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1131 { AArch64_LD1x2_4H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1132 { AArch64_LD1x2_4S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1133 { AArch64_LD1x2_8B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1134 { AArch64_LD1x2_8H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1135 { AArch64_LD1x3WB_16B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1136 { AArch64_LD1x3WB_16B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1137 { AArch64_LD1x3WB_1D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1138 { AArch64_LD1x3WB_1D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1139 { AArch64_LD1x3WB_2D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1140 { AArch64_LD1x3WB_2D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1141 { AArch64_LD1x3WB_2S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1142 { AArch64_LD1x3WB_2S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1143 { AArch64_LD1x3WB_4H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1144 { AArch64_LD1x3WB_4H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1145 { AArch64_LD1x3WB_4S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1146 { AArch64_LD1x3WB_4S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1147 { AArch64_LD1x3WB_8B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1148 { AArch64_LD1x3WB_8B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1149 { AArch64_LD1x3WB_8H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1150 { AArch64_LD1x3WB_8H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1151 { AArch64_LD1x3_16B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1152 { AArch64_LD1x3_1D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1153 { AArch64_LD1x3_2D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1154 { AArch64_LD1x3_2S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1155 { AArch64_LD1x3_4H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1156 { AArch64_LD1x3_4S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1157 { AArch64_LD1x3_8B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1158 { AArch64_LD1x3_8H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1159 { AArch64_LD1x4WB_16B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1160 { AArch64_LD1x4WB_16B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1161 { AArch64_LD1x4WB_1D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1162 { AArch64_LD1x4WB_1D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1163 { AArch64_LD1x4WB_2D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1164 { AArch64_LD1x4WB_2D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1165 { AArch64_LD1x4WB_2S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1166 { AArch64_LD1x4WB_2S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1167 { AArch64_LD1x4WB_4H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1168 { AArch64_LD1x4WB_4H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1169 { AArch64_LD1x4WB_4S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1170 { AArch64_LD1x4WB_4S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1171 { AArch64_LD1x4WB_8B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1172 { AArch64_LD1x4WB_8B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1173 { AArch64_LD1x4WB_8H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1174 { AArch64_LD1x4WB_8H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1175 { AArch64_LD1x4_16B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1176 { AArch64_LD1x4_1D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1177 { AArch64_LD1x4_2D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1178 { AArch64_LD1x4_2S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1179 { AArch64_LD1x4_4H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1180 { AArch64_LD1x4_4S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1181 { AArch64_LD1x4_8B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1182 { AArch64_LD1x4_8H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1183 { AArch64_LD2LN_B, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1184 { AArch64_LD2LN_D, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1185 { AArch64_LD2LN_H, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1186 { AArch64_LD2LN_S, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1187 { AArch64_LD2LN_WB_B_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1188 { AArch64_LD2LN_WB_B_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1189 { AArch64_LD2LN_WB_D_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1190 { AArch64_LD2LN_WB_D_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1191 { AArch64_LD2LN_WB_H_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1192 { AArch64_LD2LN_WB_H_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1193 { AArch64_LD2LN_WB_S_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1194 { AArch64_LD2LN_WB_S_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1195 { AArch64_LD2R_16B, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1196 { AArch64_LD2R_1D, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1197 { AArch64_LD2R_2D, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1198 { AArch64_LD2R_2S, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1199 { AArch64_LD2R_4H, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1200 { AArch64_LD2R_4S, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1201 { AArch64_LD2R_8B, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1202 { AArch64_LD2R_8H, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1203 { AArch64_LD2R_WB_16B_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1204 { AArch64_LD2R_WB_16B_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1205 { AArch64_LD2R_WB_1D_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1206 { AArch64_LD2R_WB_1D_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1207 { AArch64_LD2R_WB_2D_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1208 { AArch64_LD2R_WB_2D_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1209 { AArch64_LD2R_WB_2S_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1210 { AArch64_LD2R_WB_2S_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1211 { AArch64_LD2R_WB_4H_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1212 { AArch64_LD2R_WB_4H_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1213 { AArch64_LD2R_WB_4S_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1214 { AArch64_LD2R_WB_4S_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1215 { AArch64_LD2R_WB_8B_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1216 { AArch64_LD2R_WB_8B_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1217 { AArch64_LD2R_WB_8H_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1218 { AArch64_LD2R_WB_8H_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1219 { AArch64_LD2WB_16B_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1220 { AArch64_LD2WB_16B_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1221 { AArch64_LD2WB_2D_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1222 { AArch64_LD2WB_2D_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1223 { AArch64_LD2WB_2S_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1224 { AArch64_LD2WB_2S_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1225 { AArch64_LD2WB_4H_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1226 { AArch64_LD2WB_4H_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1227 { AArch64_LD2WB_4S_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1228 { AArch64_LD2WB_4S_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1229 { AArch64_LD2WB_8B_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1230 { AArch64_LD2WB_8B_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1231 { AArch64_LD2WB_8H_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1232 { AArch64_LD2WB_8H_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1233 { AArch64_LD2_16B, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1234 { AArch64_LD2_2D, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1235 { AArch64_LD2_2S, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1236 { AArch64_LD2_4H, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1237 { AArch64_LD2_4S, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1238 { AArch64_LD2_8B, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1239 { AArch64_LD2_8H, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1240 { AArch64_LD3LN_B, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1241 { AArch64_LD3LN_D, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1242 { AArch64_LD3LN_H, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1243 { AArch64_LD3LN_S, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1244 { AArch64_LD3LN_WB_B_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1245 { AArch64_LD3LN_WB_B_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1246 { AArch64_LD3LN_WB_D_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1247 { AArch64_LD3LN_WB_D_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1248 { AArch64_LD3LN_WB_H_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1249 { AArch64_LD3LN_WB_H_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1250 { AArch64_LD3LN_WB_S_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1251 { AArch64_LD3LN_WB_S_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1252 { AArch64_LD3R_16B, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1253 { AArch64_LD3R_1D, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1254 { AArch64_LD3R_2D, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1255 { AArch64_LD3R_2S, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1256 { AArch64_LD3R_4H, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1257 { AArch64_LD3R_4S, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1258 { AArch64_LD3R_8B, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1259 { AArch64_LD3R_8H, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1260 { AArch64_LD3R_WB_16B_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1261 { AArch64_LD3R_WB_16B_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1262 { AArch64_LD3R_WB_1D_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1263 { AArch64_LD3R_WB_1D_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1264 { AArch64_LD3R_WB_2D_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1265 { AArch64_LD3R_WB_2D_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1266 { AArch64_LD3R_WB_2S_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1267 { AArch64_LD3R_WB_2S_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1268 { AArch64_LD3R_WB_4H_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1269 { AArch64_LD3R_WB_4H_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1270 { AArch64_LD3R_WB_4S_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1271 { AArch64_LD3R_WB_4S_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1272 { AArch64_LD3R_WB_8B_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1273 { AArch64_LD3R_WB_8B_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1274 { AArch64_LD3R_WB_8H_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1275 { AArch64_LD3R_WB_8H_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1276 { AArch64_LD3WB_16B_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1277 { AArch64_LD3WB_16B_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1278 { AArch64_LD3WB_2D_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1279 { AArch64_LD3WB_2D_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1280 { AArch64_LD3WB_2S_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1281 { AArch64_LD3WB_2S_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1282 { AArch64_LD3WB_4H_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1283 { AArch64_LD3WB_4H_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1284 { AArch64_LD3WB_4S_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1285 { AArch64_LD3WB_4S_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1286 { AArch64_LD3WB_8B_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1287 { AArch64_LD3WB_8B_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1288 { AArch64_LD3WB_8H_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1289 { AArch64_LD3WB_8H_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1290 { AArch64_LD3_16B, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1291 { AArch64_LD3_2D, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1292 { AArch64_LD3_2S, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1293 { AArch64_LD3_4H, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1294 { AArch64_LD3_4S, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1295 { AArch64_LD3_8B, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1296 { AArch64_LD3_8H, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1297 { AArch64_LD4LN_B, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1298 { AArch64_LD4LN_D, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1299 { AArch64_LD4LN_H, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1300 { AArch64_LD4LN_S, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1301 { AArch64_LD4LN_WB_B_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1302 { AArch64_LD4LN_WB_B_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1303 { AArch64_LD4LN_WB_D_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1304 { AArch64_LD4LN_WB_D_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1305 { AArch64_LD4LN_WB_H_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1306 { AArch64_LD4LN_WB_H_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1307 { AArch64_LD4LN_WB_S_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1308 { AArch64_LD4LN_WB_S_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1309 { AArch64_LD4R_16B, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1310 { AArch64_LD4R_1D, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1311 { AArch64_LD4R_2D, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1312 { AArch64_LD4R_2S, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1313 { AArch64_LD4R_4H, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1314 { AArch64_LD4R_4S, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1315 { AArch64_LD4R_8B, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1316 { AArch64_LD4R_8H, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1317 { AArch64_LD4R_WB_16B_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1318 { AArch64_LD4R_WB_16B_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1319 { AArch64_LD4R_WB_1D_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1320 { AArch64_LD4R_WB_1D_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1321 { AArch64_LD4R_WB_2D_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1322 { AArch64_LD4R_WB_2D_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1323 { AArch64_LD4R_WB_2S_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1324 { AArch64_LD4R_WB_2S_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1325 { AArch64_LD4R_WB_4H_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1326 { AArch64_LD4R_WB_4H_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1327 { AArch64_LD4R_WB_4S_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1328 { AArch64_LD4R_WB_4S_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1329 { AArch64_LD4R_WB_8B_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1330 { AArch64_LD4R_WB_8B_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1331 { AArch64_LD4R_WB_8H_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1332 { AArch64_LD4R_WB_8H_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1333 { AArch64_LD4WB_16B_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1334 { AArch64_LD4WB_16B_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1335 { AArch64_LD4WB_2D_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1336 { AArch64_LD4WB_2D_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1337 { AArch64_LD4WB_2S_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1338 { AArch64_LD4WB_2S_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1339 { AArch64_LD4WB_4H_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1340 { AArch64_LD4WB_4H_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1341 { AArch64_LD4WB_4S_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1342 { AArch64_LD4WB_4S_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1343 { AArch64_LD4WB_8B_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1344 { AArch64_LD4WB_8B_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1345 { AArch64_LD4WB_8H_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1346 { AArch64_LD4WB_8H_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1347 { AArch64_LD4_16B, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1348 { AArch64_LD4_2D, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1349 { AArch64_LD4_2S, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1350 { AArch64_LD4_4H, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1351 { AArch64_LD4_4S, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1352 { AArch64_LD4_8B, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1353 { AArch64_LD4_8H, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1354 { AArch64_LDAR_byte, ARM64_INS_LDARB, { 0 }, { 0 }, { 0 }, 0, 0 },
1355 { AArch64_LDAR_dword, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 }, 0, 0 },
1356 { AArch64_LDAR_hword, ARM64_INS_LDARH, { 0 }, { 0 }, { 0 }, 0, 0 },
1357 { AArch64_LDAR_word, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 }, 0, 0 },
1358 { AArch64_LDAXP_dword, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 }, 0, 0 },
1359 { AArch64_LDAXP_word, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 }, 0, 0 },
1360 { AArch64_LDAXR_byte, ARM64_INS_LDAXRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1361 { AArch64_LDAXR_dword, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 }, 0, 0 },
1362 { AArch64_LDAXR_hword, ARM64_INS_LDAXRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1363 { AArch64_LDAXR_word, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 }, 0, 0 },
1364 { AArch64_LDPSWx, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1365 { AArch64_LDPSWx_PostInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1366 { AArch64_LDPSWx_PreInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1367 { AArch64_LDRSBw, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1368 { AArch64_LDRSBw_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1369 { AArch64_LDRSBw_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1370 { AArch64_LDRSBw_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1371 { AArch64_LDRSBw_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1372 { AArch64_LDRSBw_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1373 { AArch64_LDRSBx, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1374 { AArch64_LDRSBx_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1375 { AArch64_LDRSBx_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1376 { AArch64_LDRSBx_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1377 { AArch64_LDRSBx_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1378 { AArch64_LDRSBx_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1379 { AArch64_LDRSHw, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1380 { AArch64_LDRSHw_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1381 { AArch64_LDRSHw_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1382 { AArch64_LDRSHw_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1383 { AArch64_LDRSHw_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1384 { AArch64_LDRSHw_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1385 { AArch64_LDRSHx, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1386 { AArch64_LDRSHx_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1387 { AArch64_LDRSHx_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1388 { AArch64_LDRSHx_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1389 { AArch64_LDRSHx_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1390 { AArch64_LDRSHx_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1391 { AArch64_LDRSWx, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1392 { AArch64_LDRSWx_PostInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1393 { AArch64_LDRSWx_PreInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1394 { AArch64_LDRSWx_Wm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1395 { AArch64_LDRSWx_Xm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1396 { AArch64_LDRSWx_lit, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1397 { AArch64_LDRd_lit, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1398 { AArch64_LDRq_lit, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1399 { AArch64_LDRs_lit, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1400 { AArch64_LDRw_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1401 { AArch64_LDRx_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1402 { AArch64_LDTRSBw, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1403 { AArch64_LDTRSBx, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
1404 { AArch64_LDTRSHw, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1405 { AArch64_LDTRSHx, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
1406 { AArch64_LDTRSWx, ARM64_INS_LDTRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1407 { AArch64_LDURSWx, ARM64_INS_LDURSW, { 0 }, { 0 }, { 0 }, 0, 0 },
1408 { AArch64_LDXP_dword, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 }, 0, 0 },
1409 { AArch64_LDXP_word, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 }, 0, 0 },
1410 { AArch64_LDXR_byte, ARM64_INS_LDXRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1411 { AArch64_LDXR_dword, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 }, 0, 0 },
1412 { AArch64_LDXR_hword, ARM64_INS_LDXRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1413 { AArch64_LDXR_word, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 }, 0, 0 },
1414 { AArch64_LS16_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1415 { AArch64_LS16_LDUR, ARM64_INS_LDURH, { 0 }, { 0 }, { 0 }, 0, 0 },
1416 { AArch64_LS16_PostInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1417 { AArch64_LS16_PostInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1418 { AArch64_LS16_PreInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1419 { AArch64_LS16_PreInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1420 { AArch64_LS16_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1421 { AArch64_LS16_STUR, ARM64_INS_STURH, { 0 }, { 0 }, { 0 }, 0, 0 },
1422 { AArch64_LS16_UnPriv_LDR, ARM64_INS_LDTRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1423 { AArch64_LS16_UnPriv_STR, ARM64_INS_STTRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1424 { AArch64_LS16_Wm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1425 { AArch64_LS16_Wm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1426 { AArch64_LS16_Xm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1427 { AArch64_LS16_Xm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
1428 { AArch64_LS32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1429 { AArch64_LS32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 }, 0, 0 },
1430 { AArch64_LS32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1431 { AArch64_LS32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1432 { AArch64_LS32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1433 { AArch64_LS32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1434 { AArch64_LS32_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1435 { AArch64_LS32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 }, 0, 0 },
1436 { AArch64_LS32_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 }, 0, 0 },
1437 { AArch64_LS32_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 }, 0, 0 },
1438 { AArch64_LS32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1439 { AArch64_LS32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1440 { AArch64_LS32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1441 { AArch64_LS32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1442 { AArch64_LS64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1443 { AArch64_LS64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 }, 0, 0 },
1444 { AArch64_LS64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1445 { AArch64_LS64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1446 { AArch64_LS64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1447 { AArch64_LS64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1448 { AArch64_LS64_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1449 { AArch64_LS64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 }, 0, 0 },
1450 { AArch64_LS64_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 }, 0, 0 },
1451 { AArch64_LS64_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 }, 0, 0 },
1452 { AArch64_LS64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1453 { AArch64_LS64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1454 { AArch64_LS64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
1455 { AArch64_LS64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
1456 { AArch64_LS8_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1457 { AArch64_LS8_LDUR, ARM64_INS_LDURB, { 0 }, { 0 }, { 0 }, 0, 0 },
1458 { AArch64_LS8_PostInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1459 { AArch64_LS8_PostInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1460 { AArch64_LS8_PreInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1461 { AArch64_LS8_PreInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1462 { AArch64_LS8_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1463 { AArch64_LS8_STUR, ARM64_INS_STURB, { 0 }, { 0 }, { 0 }, 0, 0 },
1464 { AArch64_LS8_UnPriv_LDR, ARM64_INS_LDTRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1465 { AArch64_LS8_UnPriv_STR, ARM64_INS_STTRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1466 { AArch64_LS8_Wm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1467 { AArch64_LS8_Wm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1468 { AArch64_LS8_Xm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1469 { AArch64_LS8_Xm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
1470 { AArch64_LSFP128_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1471 { AArch64_LSFP128_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1472 { AArch64_LSFP128_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1473 { AArch64_LSFP128_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1474 { AArch64_LSFP128_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1475 { AArch64_LSFP128_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1476 { AArch64_LSFP128_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1477 { AArch64_LSFP128_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1478 { AArch64_LSFP128_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1479 { AArch64_LSFP128_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1480 { AArch64_LSFP128_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1481 { AArch64_LSFP128_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1482 { AArch64_LSFP16_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1483 { AArch64_LSFP16_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1484 { AArch64_LSFP16_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1485 { AArch64_LSFP16_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1486 { AArch64_LSFP16_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1487 { AArch64_LSFP16_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1488 { AArch64_LSFP16_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1489 { AArch64_LSFP16_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1490 { AArch64_LSFP16_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1491 { AArch64_LSFP16_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1492 { AArch64_LSFP16_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1493 { AArch64_LSFP16_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1494 { AArch64_LSFP32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1495 { AArch64_LSFP32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1496 { AArch64_LSFP32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1497 { AArch64_LSFP32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1498 { AArch64_LSFP32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1499 { AArch64_LSFP32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1500 { AArch64_LSFP32_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1501 { AArch64_LSFP32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1502 { AArch64_LSFP32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1503 { AArch64_LSFP32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1504 { AArch64_LSFP32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1505 { AArch64_LSFP32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1506 { AArch64_LSFP64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1507 { AArch64_LSFP64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1508 { AArch64_LSFP64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1509 { AArch64_LSFP64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1510 { AArch64_LSFP64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1511 { AArch64_LSFP64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1512 { AArch64_LSFP64_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1513 { AArch64_LSFP64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1514 { AArch64_LSFP64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1515 { AArch64_LSFP64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1516 { AArch64_LSFP64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1517 { AArch64_LSFP64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1518 { AArch64_LSFP8_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1519 { AArch64_LSFP8_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1520 { AArch64_LSFP8_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1521 { AArch64_LSFP8_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1522 { AArch64_LSFP8_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1523 { AArch64_LSFP8_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1524 { AArch64_LSFP8_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1525 { AArch64_LSFP8_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1526 { AArch64_LSFP8_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1527 { AArch64_LSFP8_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1528 { AArch64_LSFP8_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1529 { AArch64_LSFP8_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1530 { AArch64_LSFPPair128_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1531 { AArch64_LSFPPair128_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1532 { AArch64_LSFPPair128_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1533 { AArch64_LSFPPair128_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1534 { AArch64_LSFPPair128_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1535 { AArch64_LSFPPair128_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1536 { AArch64_LSFPPair128_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1537 { AArch64_LSFPPair128_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1538 { AArch64_LSFPPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1539 { AArch64_LSFPPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1540 { AArch64_LSFPPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1541 { AArch64_LSFPPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1542 { AArch64_LSFPPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1543 { AArch64_LSFPPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1544 { AArch64_LSFPPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1545 { AArch64_LSFPPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1546 { AArch64_LSFPPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1547 { AArch64_LSFPPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1548 { AArch64_LSFPPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1549 { AArch64_LSFPPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1550 { AArch64_LSFPPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1551 { AArch64_LSFPPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1552 { AArch64_LSFPPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1553 { AArch64_LSFPPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1554 { AArch64_LSLVwww, ARM64_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
1555 { AArch64_LSLVxxx, ARM64_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
1556 { AArch64_LSLwwi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
1557 { AArch64_LSLxxi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
1558 { AArch64_LSPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
1559 { AArch64_LSPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 }, 0, 0 },
1560 { AArch64_LSPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 }, 0, 0 },
1561 { AArch64_LSPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
1562 { AArch64_LSPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
1563 { AArch64_LSPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
1564 { AArch64_LSPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
1565 { AArch64_LSPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
1566 { AArch64_LSPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
1567 { AArch64_LSPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 }, 0, 0 },
1568 { AArch64_LSPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 }, 0, 0 },
1569 { AArch64_LSPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
1570 { AArch64_LSPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
1571 { AArch64_LSPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
1572 { AArch64_LSPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
1573 { AArch64_LSPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
1574 { AArch64_LSRVwww, ARM64_INS_LSR, { 0 }, { 0 }, { 0 }, 0, 0 },
1575 { AArch64_LSRVxxx, ARM64_INS_LSR, { 0 }, { 0 }, { 0 }, 0, 0 },
1576 { AArch64_LSRwwi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 }, 0, 0 },
1577 { AArch64_LSRxxi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 }, 0, 0 },
1578 { AArch64_MADDwwww, ARM64_INS_MADD, { 0 }, { 0 }, { 0 }, 0, 0 },
1579 { AArch64_MADDxxxx, ARM64_INS_MADD, { 0 }, { 0 }, { 0 }, 0, 0 },
1580 { AArch64_MLAvve_2s4s, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1581 { AArch64_MLAvve_4h8h, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1582 { AArch64_MLAvve_4s4s, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1583 { AArch64_MLAvve_8h8h, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1584 { AArch64_MLAvvv_16B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1585 { AArch64_MLAvvv_2S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1586 { AArch64_MLAvvv_4H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1587 { AArch64_MLAvvv_4S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1588 { AArch64_MLAvvv_8B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1589 { AArch64_MLAvvv_8H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1590 { AArch64_MLSvve_2s4s, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1591 { AArch64_MLSvve_4h8h, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1592 { AArch64_MLSvve_4s4s, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1593 { AArch64_MLSvve_8h8h, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1594 { AArch64_MLSvvv_16B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1595 { AArch64_MLSvvv_2S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1596 { AArch64_MLSvvv_4H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1597 { AArch64_MLSvvv_4S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1598 { AArch64_MLSvvv_8B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1599 { AArch64_MLSvvv_8H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1600 { AArch64_MOVIdi, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1601 { AArch64_MOVIvi_16B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1602 { AArch64_MOVIvi_2D, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1603 { AArch64_MOVIvi_8B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1604 { AArch64_MOVIvi_lsl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1605 { AArch64_MOVIvi_lsl_4H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1606 { AArch64_MOVIvi_lsl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1607 { AArch64_MOVIvi_lsl_8H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1608 { AArch64_MOVIvi_msl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1609 { AArch64_MOVIvi_msl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1610 { AArch64_MOVKwii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 }, 0, 0 },
1611 { AArch64_MOVKxii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 }, 0, 0 },
1612 { AArch64_MOVNwii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1613 { AArch64_MOVNxii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1614 { AArch64_MOVZwii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 }, 0, 0 },
1615 { AArch64_MOVZxii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 }, 0, 0 },
1616 { AArch64_MRSxi, ARM64_INS_MRS, { 0 }, { 0 }, { 0 }, 0, 0 },
1617 { AArch64_MSRii, ARM64_INS_MSR, { 0 }, { 0 }, { 0 }, 0, 0 },
1618 { AArch64_MSRix, ARM64_INS_MSR, { 0 }, { 0 }, { 0 }, 0, 0 },
1619 { AArch64_MSUBwwww, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 }, 0, 0 },
1620 { AArch64_MSUBxxxx, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 }, 0, 0 },
1621 { AArch64_MULve_2s4s, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1622 { AArch64_MULve_4h8h, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1623 { AArch64_MULve_4s4s, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1624 { AArch64_MULve_8h8h, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1625 { AArch64_MULvvv_16B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1626 { AArch64_MULvvv_2S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1627 { AArch64_MULvvv_4H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1628 { AArch64_MULvvv_4S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1629 { AArch64_MULvvv_8B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1630 { AArch64_MULvvv_8H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1631 { AArch64_MVNIvi_lsl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1632 { AArch64_MVNIvi_lsl_4H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1633 { AArch64_MVNIvi_lsl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1634 { AArch64_MVNIvi_lsl_8H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1635 { AArch64_MVNIvi_msl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1636 { AArch64_MVNIvi_msl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1637 { AArch64_MVNww_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1638 { AArch64_MVNww_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1639 { AArch64_MVNww_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1640 { AArch64_MVNww_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1641 { AArch64_MVNxx_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1642 { AArch64_MVNxx_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1643 { AArch64_MVNxx_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1644 { AArch64_MVNxx_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
1645 { AArch64_NEG16b, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1646 { AArch64_NEG2d, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1647 { AArch64_NEG2s, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1648 { AArch64_NEG4h, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1649 { AArch64_NEG4s, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1650 { AArch64_NEG8b, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1651 { AArch64_NEG8h, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1652 { AArch64_NEGdd, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1653 { AArch64_NOT16b, ARM64_INS_NOT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1654 { AArch64_NOT8b, ARM64_INS_NOT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1655 { AArch64_ORNvvv_16B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1656 { AArch64_ORNvvv_8B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1657 { AArch64_ORNwww_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
1658 { AArch64_ORNwww_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
1659 { AArch64_ORNwww_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
1660 { AArch64_ORNwww_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
1661 { AArch64_ORNxxx_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
1662 { AArch64_ORNxxx_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
1663 { AArch64_ORNxxx_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
1664 { AArch64_ORNxxx_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
1665 { AArch64_ORRvi_lsl_2S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1666 { AArch64_ORRvi_lsl_4H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1667 { AArch64_ORRvi_lsl_4S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1668 { AArch64_ORRvi_lsl_8H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1669 { AArch64_ORRvvv_16B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1670 { AArch64_ORRvvv_8B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1671 { AArch64_ORRwwi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1672 { AArch64_ORRwww_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1673 { AArch64_ORRwww_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1674 { AArch64_ORRwww_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1675 { AArch64_ORRwww_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1676 { AArch64_ORRxxi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1677 { AArch64_ORRxxx_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1678 { AArch64_ORRxxx_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1679 { AArch64_ORRxxx_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1680 { AArch64_ORRxxx_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
1681 { AArch64_PMULL2vvv_1q2d, ARM64_INS_PMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1682 { AArch64_PMULL2vvv_8h16b, ARM64_INS_PMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1683 { AArch64_PMULLvvv_1q1d, ARM64_INS_PMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1684 { AArch64_PMULLvvv_8h8b, ARM64_INS_PMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1685 { AArch64_PMULvvv_16B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1686 { AArch64_PMULvvv_8B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1687 { AArch64_PRFM, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 }, 0, 0 },
1688 { AArch64_PRFM_Wm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 }, 0, 0 },
1689 { AArch64_PRFM_Xm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 }, 0, 0 },
1690 { AArch64_PRFM_lit, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 }, 0, 0 },
1691 { AArch64_PRFUM, ARM64_INS_PRFUM, { 0 }, { 0 }, { 0 }, 0, 0 },
1692 { AArch64_QRSHRUNvvi_16B, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1693 { AArch64_QRSHRUNvvi_2S, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1694 { AArch64_QRSHRUNvvi_4H, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1695 { AArch64_QRSHRUNvvi_4S, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1696 { AArch64_QRSHRUNvvi_8B, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1697 { AArch64_QRSHRUNvvi_8H, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1698 { AArch64_QSHRUNvvi_16B, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1699 { AArch64_QSHRUNvvi_2S, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1700 { AArch64_QSHRUNvvi_4H, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1701 { AArch64_QSHRUNvvi_4S, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1702 { AArch64_QSHRUNvvi_8B, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1703 { AArch64_QSHRUNvvi_8H, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1704 { AArch64_RADDHN2vvv_16b8h, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1705 { AArch64_RADDHN2vvv_4s2d, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1706 { AArch64_RADDHN2vvv_8h4s, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1707 { AArch64_RADDHNvvv_2s2d, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1708 { AArch64_RADDHNvvv_4h4s, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1709 { AArch64_RADDHNvvv_8b8h, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1710 { AArch64_RBIT16b, ARM64_INS_RBIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1711 { AArch64_RBIT8b, ARM64_INS_RBIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1712 { AArch64_RBITww, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 }, 0, 0 },
1713 { AArch64_RBITxx, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 }, 0, 0 },
1714 { AArch64_RETx, ARM64_INS_RET, { 0 }, { 0 }, { 0 }, 1, 1 },
1715 { AArch64_REV16_16b, ARM64_INS_REV16, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1716 { AArch64_REV16_8b, ARM64_INS_REV16, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1717 { AArch64_REV16ww, ARM64_INS_REV16, { 0 }, { 0 }, { 0 }, 0, 0 },
1718 { AArch64_REV16xx, ARM64_INS_REV16, { 0 }, { 0 }, { 0 }, 0, 0 },
1719 { AArch64_REV32_16b, ARM64_INS_REV32, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1720 { AArch64_REV32_4h, ARM64_INS_REV32, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1721 { AArch64_REV32_8b, ARM64_INS_REV32, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1722 { AArch64_REV32_8h, ARM64_INS_REV32, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1723 { AArch64_REV32xx, ARM64_INS_REV32, { 0 }, { 0 }, { 0 }, 0, 0 },
1724 { AArch64_REV64_16b, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1725 { AArch64_REV64_2s, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1726 { AArch64_REV64_4h, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1727 { AArch64_REV64_4s, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1728 { AArch64_REV64_8b, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1729 { AArch64_REV64_8h, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1730 { AArch64_REVww, ARM64_INS_REV, { 0 }, { 0 }, { 0 }, 0, 0 },
1731 { AArch64_REVxx, ARM64_INS_REV, { 0 }, { 0 }, { 0 }, 0, 0 },
1732 { AArch64_RORVwww, ARM64_INS_ROR, { 0 }, { 0 }, { 0 }, 0, 0 },
1733 { AArch64_RORVxxx, ARM64_INS_ROR, { 0 }, { 0 }, { 0 }, 0, 0 },
1734 { AArch64_RSHRNvvi_16B, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1735 { AArch64_RSHRNvvi_2S, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1736 { AArch64_RSHRNvvi_4H, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1737 { AArch64_RSHRNvvi_4S, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1738 { AArch64_RSHRNvvi_8B, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1739 { AArch64_RSHRNvvi_8H, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1740 { AArch64_RSUBHN2vvv_16b8h, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1741 { AArch64_RSUBHN2vvv_4s2d, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1742 { AArch64_RSUBHN2vvv_8h4s, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1743 { AArch64_RSUBHNvvv_2s2d, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1744 { AArch64_RSUBHNvvv_4h4s, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1745 { AArch64_RSUBHNvvv_8b8h, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1746 { AArch64_SABAL2vvv_2d2s, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1747 { AArch64_SABAL2vvv_4s4h, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1748 { AArch64_SABAL2vvv_8h8b, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1749 { AArch64_SABALvvv_2d2s, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1750 { AArch64_SABALvvv_4s4h, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1751 { AArch64_SABALvvv_8h8b, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1752 { AArch64_SABAvvv_16B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1753 { AArch64_SABAvvv_2S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1754 { AArch64_SABAvvv_4H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1755 { AArch64_SABAvvv_4S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1756 { AArch64_SABAvvv_8B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1757 { AArch64_SABAvvv_8H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1758 { AArch64_SABDL2vvv_2d2s, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1759 { AArch64_SABDL2vvv_4s4h, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1760 { AArch64_SABDL2vvv_8h8b, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1761 { AArch64_SABDLvvv_2d2s, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1762 { AArch64_SABDLvvv_4s4h, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1763 { AArch64_SABDLvvv_8h8b, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1764 { AArch64_SABDvvv_16B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1765 { AArch64_SABDvvv_2S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1766 { AArch64_SABDvvv_4H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1767 { AArch64_SABDvvv_4S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1768 { AArch64_SABDvvv_8B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1769 { AArch64_SABDvvv_8H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1770 { AArch64_SADALP16b8h, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1771 { AArch64_SADALP2s1d, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1772 { AArch64_SADALP4h2s, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1773 { AArch64_SADALP4s2d, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1774 { AArch64_SADALP8b4h, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1775 { AArch64_SADALP8h4s, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1776 { AArch64_SADDL2vvv_2d4s, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1777 { AArch64_SADDL2vvv_4s8h, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1778 { AArch64_SADDL2vvv_8h16b, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1779 { AArch64_SADDLP16b8h, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1780 { AArch64_SADDLP2s1d, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1781 { AArch64_SADDLP4h2s, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1782 { AArch64_SADDLP4s2d, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1783 { AArch64_SADDLP8b4h, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1784 { AArch64_SADDLP8h4s, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1785 { AArch64_SADDLV_1d4s, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1786 { AArch64_SADDLV_1h16b, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1787 { AArch64_SADDLV_1h8b, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1788 { AArch64_SADDLV_1s4h, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1789 { AArch64_SADDLV_1s8h, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1790 { AArch64_SADDLvvv_2d2s, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1791 { AArch64_SADDLvvv_4s4h, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1792 { AArch64_SADDLvvv_8h8b, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1793 { AArch64_SADDW2vvv_2d4s, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1794 { AArch64_SADDW2vvv_4s8h, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1795 { AArch64_SADDW2vvv_8h16b, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1796 { AArch64_SADDWvvv_2d2s, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1797 { AArch64_SADDWvvv_4s4h, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1798 { AArch64_SADDWvvv_8h8b, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1799 { AArch64_SBCSwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
1800 { AArch64_SBCSxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
1801 { AArch64_SBCwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
1802 { AArch64_SBCxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
1803 { AArch64_SBFIZwwii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 }, 0, 0 },
1804 { AArch64_SBFIZxxii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 }, 0, 0 },
1805 { AArch64_SBFMwwii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 }, 0, 0 },
1806 { AArch64_SBFMxxii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 }, 0, 0 },
1807 { AArch64_SBFXwwii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 }, 0, 0 },
1808 { AArch64_SBFXxxii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 }, 0, 0 },
1809 { AArch64_SCVTF_2d, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1810 { AArch64_SCVTF_2s, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1811 { AArch64_SCVTF_4s, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1812 { AArch64_SCVTF_Nddi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1813 { AArch64_SCVTF_Nssi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1814 { AArch64_SCVTFdd, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1815 { AArch64_SCVTFdw, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1816 { AArch64_SCVTFdwi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1817 { AArch64_SCVTFdx, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1818 { AArch64_SCVTFdxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1819 { AArch64_SCVTFss, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1820 { AArch64_SCVTFsw, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1821 { AArch64_SCVTFswi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1822 { AArch64_SCVTFsx, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1823 { AArch64_SCVTFsxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
1824 { AArch64_SDIVwww, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
1825 { AArch64_SDIVxxx, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
1826 { AArch64_SHA1C, ARM64_INS_SHA1C, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1827 { AArch64_SHA1H, ARM64_INS_SHA1H, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1828 { AArch64_SHA1M, ARM64_INS_SHA1M, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1829 { AArch64_SHA1P, ARM64_INS_SHA1P, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1830 { AArch64_SHA1SU0, ARM64_INS_SHA1SU0, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1831 { AArch64_SHA1SU1, ARM64_INS_SHA1SU1, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1832 { AArch64_SHA256H, ARM64_INS_SHA256H, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1833 { AArch64_SHA256H2, ARM64_INS_SHA256H2, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1834 { AArch64_SHA256SU0, ARM64_INS_SHA256SU0, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1835 { AArch64_SHA256SU1, ARM64_INS_SHA256SU1, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
1836 { AArch64_SHADDvvv_16B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1837 { AArch64_SHADDvvv_2S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1838 { AArch64_SHADDvvv_4H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1839 { AArch64_SHADDvvv_4S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1840 { AArch64_SHADDvvv_8B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1841 { AArch64_SHADDvvv_8H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1842 { AArch64_SHLL16b8h, ARM64_INS_SHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1843 { AArch64_SHLL2s2d, ARM64_INS_SHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1844 { AArch64_SHLL4h4s, ARM64_INS_SHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1845 { AArch64_SHLL4s2d, ARM64_INS_SHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1846 { AArch64_SHLL8b8h, ARM64_INS_SHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1847 { AArch64_SHLL8h4s, ARM64_INS_SHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1848 { AArch64_SHLddi, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1849 { AArch64_SHLvvi_16B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1850 { AArch64_SHLvvi_2D, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1851 { AArch64_SHLvvi_2S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1852 { AArch64_SHLvvi_4H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1853 { AArch64_SHLvvi_4S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1854 { AArch64_SHLvvi_8B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1855 { AArch64_SHLvvi_8H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1856 { AArch64_SHRNvvi_16B, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1857 { AArch64_SHRNvvi_2S, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1858 { AArch64_SHRNvvi_4H, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1859 { AArch64_SHRNvvi_4S, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1860 { AArch64_SHRNvvi_8B, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1861 { AArch64_SHRNvvi_8H, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1862 { AArch64_SHSUBvvv_16B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1863 { AArch64_SHSUBvvv_2S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1864 { AArch64_SHSUBvvv_4H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1865 { AArch64_SHSUBvvv_4S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1866 { AArch64_SHSUBvvv_8B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1867 { AArch64_SHSUBvvv_8H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1868 { AArch64_SLI, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1869 { AArch64_SLIvvi_16B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1870 { AArch64_SLIvvi_2D, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1871 { AArch64_SLIvvi_2S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1872 { AArch64_SLIvvi_4H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1873 { AArch64_SLIvvi_4S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1874 { AArch64_SLIvvi_8B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1875 { AArch64_SLIvvi_8H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1876 { AArch64_SMADDLxwwx, ARM64_INS_SMADDL, { 0 }, { 0 }, { 0 }, 0, 0 },
1877 { AArch64_SMAXPvvv_16B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1878 { AArch64_SMAXPvvv_2S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1879 { AArch64_SMAXPvvv_4H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1880 { AArch64_SMAXPvvv_4S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1881 { AArch64_SMAXPvvv_8B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1882 { AArch64_SMAXPvvv_8H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1883 { AArch64_SMAXV_1b16b, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1884 { AArch64_SMAXV_1b8b, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1885 { AArch64_SMAXV_1h4h, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1886 { AArch64_SMAXV_1h8h, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1887 { AArch64_SMAXV_1s4s, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1888 { AArch64_SMAXvvv_16B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1889 { AArch64_SMAXvvv_2S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1890 { AArch64_SMAXvvv_4H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1891 { AArch64_SMAXvvv_4S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1892 { AArch64_SMAXvvv_8B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1893 { AArch64_SMAXvvv_8H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1894 { AArch64_SMCi, ARM64_INS_SMC, { 0 }, { 0 }, { 0 }, 1, 0 },
1895 { AArch64_SMINPvvv_16B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1896 { AArch64_SMINPvvv_2S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1897 { AArch64_SMINPvvv_4H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1898 { AArch64_SMINPvvv_4S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1899 { AArch64_SMINPvvv_8B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1900 { AArch64_SMINPvvv_8H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1901 { AArch64_SMINV_1b16b, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1902 { AArch64_SMINV_1b8b, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1903 { AArch64_SMINV_1h4h, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1904 { AArch64_SMINV_1h8h, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1905 { AArch64_SMINV_1s4s, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1906 { AArch64_SMINvvv_16B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1907 { AArch64_SMINvvv_2S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1908 { AArch64_SMINvvv_4H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1909 { AArch64_SMINvvv_4S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1910 { AArch64_SMINvvv_8B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1911 { AArch64_SMINvvv_8H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1912 { AArch64_SMLAL2vvv_2d4s, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1913 { AArch64_SMLAL2vvv_4s8h, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1914 { AArch64_SMLAL2vvv_8h16b, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1915 { AArch64_SMLALvve_2d2s, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1916 { AArch64_SMLALvve_2d4s, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1917 { AArch64_SMLALvve_4s4h, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1918 { AArch64_SMLALvve_4s8h, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1919 { AArch64_SMLALvvv_2d2s, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1920 { AArch64_SMLALvvv_4s4h, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1921 { AArch64_SMLALvvv_8h8b, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1922 { AArch64_SMLSL2vvv_2d4s, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1923 { AArch64_SMLSL2vvv_4s8h, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1924 { AArch64_SMLSL2vvv_8h16b, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1925 { AArch64_SMLSLvve_2d2s, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1926 { AArch64_SMLSLvve_2d4s, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1927 { AArch64_SMLSLvve_4s4h, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1928 { AArch64_SMLSLvve_4s8h, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1929 { AArch64_SMLSLvvv_2d2s, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1930 { AArch64_SMLSLvvv_4s4h, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1931 { AArch64_SMLSLvvv_8h8b, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1932 { AArch64_SMOVwb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1933 { AArch64_SMOVwh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1934 { AArch64_SMOVxb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1935 { AArch64_SMOVxh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1936 { AArch64_SMOVxs, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1937 { AArch64_SMSUBLxwwx, ARM64_INS_SMSUBL, { 0 }, { 0 }, { 0 }, 0, 0 },
1938 { AArch64_SMULHxxx, ARM64_INS_SMULH, { 0 }, { 0 }, { 0 }, 0, 0 },
1939 { AArch64_SMULL2vvv_2d4s, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1940 { AArch64_SMULL2vvv_4s8h, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1941 { AArch64_SMULL2vvv_8h16b, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1942 { AArch64_SMULLve_2d2s, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1943 { AArch64_SMULLve_2d4s, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1944 { AArch64_SMULLve_4s4h, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1945 { AArch64_SMULLve_4s8h, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1946 { AArch64_SMULLvvv_2d2s, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1947 { AArch64_SMULLvvv_4s4h, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1948 { AArch64_SMULLvvv_8h8b, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1949 { AArch64_SQABS16b, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1950 { AArch64_SQABS2d, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1951 { AArch64_SQABS2s, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1952 { AArch64_SQABS4h, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1953 { AArch64_SQABS4s, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1954 { AArch64_SQABS8b, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1955 { AArch64_SQABS8h, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1956 { AArch64_SQABSbb, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1957 { AArch64_SQABSdd, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1958 { AArch64_SQABShh, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1959 { AArch64_SQABSss, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1960 { AArch64_SQADDbbb, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1961 { AArch64_SQADDddd, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1962 { AArch64_SQADDhhh, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1963 { AArch64_SQADDsss, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1964 { AArch64_SQADDvvv_16B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1965 { AArch64_SQADDvvv_2D, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1966 { AArch64_SQADDvvv_2S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1967 { AArch64_SQADDvvv_4H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1968 { AArch64_SQADDvvv_4S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1969 { AArch64_SQADDvvv_8B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1970 { AArch64_SQADDvvv_8H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1971 { AArch64_SQDMLAL2vvv_2d4s, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1972 { AArch64_SQDMLAL2vvv_4s8h, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1973 { AArch64_SQDMLALdss, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1974 { AArch64_SQDMLALdsv_2S, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1975 { AArch64_SQDMLALdsv_4S, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1976 { AArch64_SQDMLALshh, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1977 { AArch64_SQDMLALshv_4H, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1978 { AArch64_SQDMLALshv_8H, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1979 { AArch64_SQDMLALvve_2d2s, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1980 { AArch64_SQDMLALvve_2d4s, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1981 { AArch64_SQDMLALvve_4s4h, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1982 { AArch64_SQDMLALvve_4s8h, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1983 { AArch64_SQDMLALvvv_2d2s, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1984 { AArch64_SQDMLALvvv_4s4h, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1985 { AArch64_SQDMLSL2vvv_2d4s, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1986 { AArch64_SQDMLSL2vvv_4s8h, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1987 { AArch64_SQDMLSLdss, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1988 { AArch64_SQDMLSLdsv_2S, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1989 { AArch64_SQDMLSLdsv_4S, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1990 { AArch64_SQDMLSLshh, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1991 { AArch64_SQDMLSLshv_4H, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1992 { AArch64_SQDMLSLshv_8H, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1993 { AArch64_SQDMLSLvve_2d2s, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1994 { AArch64_SQDMLSLvve_2d4s, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1995 { AArch64_SQDMLSLvve_4s4h, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1996 { AArch64_SQDMLSLvve_4s8h, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1997 { AArch64_SQDMLSLvvv_2d2s, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1998 { AArch64_SQDMLSLvvv_4s4h, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
1999 { AArch64_SQDMULHhhh, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2000 { AArch64_SQDMULHhhv_4H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2001 { AArch64_SQDMULHhhv_8H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2002 { AArch64_SQDMULHsss, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2003 { AArch64_SQDMULHssv_2S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2004 { AArch64_SQDMULHssv_4S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2005 { AArch64_SQDMULHve_2s4s, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2006 { AArch64_SQDMULHve_4h8h, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2007 { AArch64_SQDMULHve_4s4s, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2008 { AArch64_SQDMULHve_8h8h, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2009 { AArch64_SQDMULHvvv_2S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2010 { AArch64_SQDMULHvvv_4H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2011 { AArch64_SQDMULHvvv_4S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2012 { AArch64_SQDMULHvvv_8H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2013 { AArch64_SQDMULL2vvv_2d4s, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2014 { AArch64_SQDMULL2vvv_4s8h, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2015 { AArch64_SQDMULLdss, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2016 { AArch64_SQDMULLdsv_2S, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2017 { AArch64_SQDMULLdsv_4S, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2018 { AArch64_SQDMULLshh, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2019 { AArch64_SQDMULLshv_4H, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2020 { AArch64_SQDMULLshv_8H, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2021 { AArch64_SQDMULLve_2d2s, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2022 { AArch64_SQDMULLve_2d4s, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2023 { AArch64_SQDMULLve_4s4h, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2024 { AArch64_SQDMULLve_4s8h, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2025 { AArch64_SQDMULLvvv_2d2s, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2026 { AArch64_SQDMULLvvv_4s4h, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2027 { AArch64_SQNEG16b, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2028 { AArch64_SQNEG2d, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2029 { AArch64_SQNEG2s, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2030 { AArch64_SQNEG4h, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2031 { AArch64_SQNEG4s, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2032 { AArch64_SQNEG8b, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2033 { AArch64_SQNEG8h, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2034 { AArch64_SQNEGbb, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2035 { AArch64_SQNEGdd, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2036 { AArch64_SQNEGhh, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2037 { AArch64_SQNEGss, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2038 { AArch64_SQRDMULHhhh, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2039 { AArch64_SQRDMULHhhv_4H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2040 { AArch64_SQRDMULHhhv_8H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2041 { AArch64_SQRDMULHsss, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2042 { AArch64_SQRDMULHssv_2S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2043 { AArch64_SQRDMULHssv_4S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2044 { AArch64_SQRDMULHve_2s4s, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2045 { AArch64_SQRDMULHve_4h8h, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2046 { AArch64_SQRDMULHve_4s4s, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2047 { AArch64_SQRDMULHve_8h8h, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2048 { AArch64_SQRDMULHvvv_2S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2049 { AArch64_SQRDMULHvvv_4H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2050 { AArch64_SQRDMULHvvv_4S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2051 { AArch64_SQRDMULHvvv_8H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2052 { AArch64_SQRSHLbbb, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2053 { AArch64_SQRSHLddd, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2054 { AArch64_SQRSHLhhh, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2055 { AArch64_SQRSHLsss, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2056 { AArch64_SQRSHLvvv_16B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2057 { AArch64_SQRSHLvvv_2D, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2058 { AArch64_SQRSHLvvv_2S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2059 { AArch64_SQRSHLvvv_4H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2060 { AArch64_SQRSHLvvv_4S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2061 { AArch64_SQRSHLvvv_8B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2062 { AArch64_SQRSHLvvv_8H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2063 { AArch64_SQRSHRNbhi, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2064 { AArch64_SQRSHRNhsi, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2065 { AArch64_SQRSHRNsdi, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2066 { AArch64_SQRSHRNvvi_16B, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2067 { AArch64_SQRSHRNvvi_2S, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2068 { AArch64_SQRSHRNvvi_4H, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2069 { AArch64_SQRSHRNvvi_4S, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2070 { AArch64_SQRSHRNvvi_8B, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2071 { AArch64_SQRSHRNvvi_8H, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2072 { AArch64_SQRSHRUNbhi, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2073 { AArch64_SQRSHRUNhsi, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2074 { AArch64_SQRSHRUNsdi, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2075 { AArch64_SQSHLUbbi, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2076 { AArch64_SQSHLUddi, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2077 { AArch64_SQSHLUhhi, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2078 { AArch64_SQSHLUssi, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2079 { AArch64_SQSHLUvvi_16B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2080 { AArch64_SQSHLUvvi_2D, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2081 { AArch64_SQSHLUvvi_2S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2082 { AArch64_SQSHLUvvi_4H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2083 { AArch64_SQSHLUvvi_4S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2084 { AArch64_SQSHLUvvi_8B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2085 { AArch64_SQSHLUvvi_8H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2086 { AArch64_SQSHLbbb, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2087 { AArch64_SQSHLbbi, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2088 { AArch64_SQSHLddd, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2089 { AArch64_SQSHLddi, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2090 { AArch64_SQSHLhhh, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2091 { AArch64_SQSHLhhi, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2092 { AArch64_SQSHLssi, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2093 { AArch64_SQSHLsss, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2094 { AArch64_SQSHLvvi_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2095 { AArch64_SQSHLvvi_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2096 { AArch64_SQSHLvvi_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2097 { AArch64_SQSHLvvi_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2098 { AArch64_SQSHLvvi_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2099 { AArch64_SQSHLvvi_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2100 { AArch64_SQSHLvvi_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2101 { AArch64_SQSHLvvv_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2102 { AArch64_SQSHLvvv_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2103 { AArch64_SQSHLvvv_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2104 { AArch64_SQSHLvvv_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2105 { AArch64_SQSHLvvv_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2106 { AArch64_SQSHLvvv_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2107 { AArch64_SQSHLvvv_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2108 { AArch64_SQSHRNbhi, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2109 { AArch64_SQSHRNhsi, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2110 { AArch64_SQSHRNsdi, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2111 { AArch64_SQSHRNvvi_16B, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2112 { AArch64_SQSHRNvvi_2S, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2113 { AArch64_SQSHRNvvi_4H, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2114 { AArch64_SQSHRNvvi_4S, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2115 { AArch64_SQSHRNvvi_8B, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2116 { AArch64_SQSHRNvvi_8H, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2117 { AArch64_SQSHRUNbhi, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2118 { AArch64_SQSHRUNhsi, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2119 { AArch64_SQSHRUNsdi, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2120 { AArch64_SQSUBbbb, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2121 { AArch64_SQSUBddd, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2122 { AArch64_SQSUBhhh, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2123 { AArch64_SQSUBsss, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2124 { AArch64_SQSUBvvv_16B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2125 { AArch64_SQSUBvvv_2D, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2126 { AArch64_SQSUBvvv_2S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2127 { AArch64_SQSUBvvv_4H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2128 { AArch64_SQSUBvvv_4S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2129 { AArch64_SQSUBvvv_8B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2130 { AArch64_SQSUBvvv_8H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2131 { AArch64_SQXTN2d2s, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2132 { AArch64_SQXTN2d4s, ARM64_INS_SQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2133 { AArch64_SQXTN4s4h, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2134 { AArch64_SQXTN4s8h, ARM64_INS_SQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2135 { AArch64_SQXTN8h16b, ARM64_INS_SQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2136 { AArch64_SQXTN8h8b, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2137 { AArch64_SQXTNbh, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2138 { AArch64_SQXTNhs, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2139 { AArch64_SQXTNsd, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2140 { AArch64_SQXTUN2d2s, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2141 { AArch64_SQXTUN2d4s, ARM64_INS_SQXTUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2142 { AArch64_SQXTUN4s4h, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2143 { AArch64_SQXTUN4s8h, ARM64_INS_SQXTUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2144 { AArch64_SQXTUN8h16b, ARM64_INS_SQXTUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2145 { AArch64_SQXTUN8h8b, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2146 { AArch64_SQXTUNbh, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2147 { AArch64_SQXTUNhs, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2148 { AArch64_SQXTUNsd, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2149 { AArch64_SRHADDvvv_16B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2150 { AArch64_SRHADDvvv_2S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2151 { AArch64_SRHADDvvv_4H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2152 { AArch64_SRHADDvvv_4S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2153 { AArch64_SRHADDvvv_8B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2154 { AArch64_SRHADDvvv_8H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2155 { AArch64_SRI, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2156 { AArch64_SRIvvi_16B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2157 { AArch64_SRIvvi_2D, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2158 { AArch64_SRIvvi_2S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2159 { AArch64_SRIvvi_4H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2160 { AArch64_SRIvvi_4S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2161 { AArch64_SRIvvi_8B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2162 { AArch64_SRIvvi_8H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2163 { AArch64_SRSHLddd, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2164 { AArch64_SRSHLvvv_16B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2165 { AArch64_SRSHLvvv_2D, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2166 { AArch64_SRSHLvvv_2S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2167 { AArch64_SRSHLvvv_4H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2168 { AArch64_SRSHLvvv_4S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2169 { AArch64_SRSHLvvv_8B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2170 { AArch64_SRSHLvvv_8H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2171 { AArch64_SRSHRddi, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2172 { AArch64_SRSHRvvi_16B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2173 { AArch64_SRSHRvvi_2D, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2174 { AArch64_SRSHRvvi_2S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2175 { AArch64_SRSHRvvi_4H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2176 { AArch64_SRSHRvvi_4S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2177 { AArch64_SRSHRvvi_8B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2178 { AArch64_SRSHRvvi_8H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2179 { AArch64_SRSRA, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2180 { AArch64_SRSRAvvi_16B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2181 { AArch64_SRSRAvvi_2D, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2182 { AArch64_SRSRAvvi_2S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2183 { AArch64_SRSRAvvi_4H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2184 { AArch64_SRSRAvvi_4S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2185 { AArch64_SRSRAvvi_8B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2186 { AArch64_SRSRAvvi_8H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2187 { AArch64_SSHLLvvi_16B, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2188 { AArch64_SSHLLvvi_2S, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2189 { AArch64_SSHLLvvi_4H, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2190 { AArch64_SSHLLvvi_4S, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2191 { AArch64_SSHLLvvi_8B, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2192 { AArch64_SSHLLvvi_8H, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2193 { AArch64_SSHLddd, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2194 { AArch64_SSHLvvv_16B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2195 { AArch64_SSHLvvv_2D, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2196 { AArch64_SSHLvvv_2S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2197 { AArch64_SSHLvvv_4H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2198 { AArch64_SSHLvvv_4S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2199 { AArch64_SSHLvvv_8B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2200 { AArch64_SSHLvvv_8H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2201 { AArch64_SSHRddi, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2202 { AArch64_SSHRvvi_16B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2203 { AArch64_SSHRvvi_2D, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2204 { AArch64_SSHRvvi_2S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2205 { AArch64_SSHRvvi_4H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2206 { AArch64_SSHRvvi_4S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2207 { AArch64_SSHRvvi_8B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2208 { AArch64_SSHRvvi_8H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2209 { AArch64_SSRA, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2210 { AArch64_SSRAvvi_16B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2211 { AArch64_SSRAvvi_2D, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2212 { AArch64_SSRAvvi_2S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2213 { AArch64_SSRAvvi_4H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2214 { AArch64_SSRAvvi_4S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2215 { AArch64_SSRAvvi_8B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2216 { AArch64_SSRAvvi_8H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2217 { AArch64_SSUBL2vvv_2d4s, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2218 { AArch64_SSUBL2vvv_4s8h, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2219 { AArch64_SSUBL2vvv_8h16b, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2220 { AArch64_SSUBLvvv_2d2s, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2221 { AArch64_SSUBLvvv_4s4h, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2222 { AArch64_SSUBLvvv_8h8b, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2223 { AArch64_SSUBW2vvv_2d4s, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2224 { AArch64_SSUBW2vvv_4s8h, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2225 { AArch64_SSUBW2vvv_8h16b, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2226 { AArch64_SSUBWvvv_2d2s, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2227 { AArch64_SSUBWvvv_4s4h, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2228 { AArch64_SSUBWvvv_8h8b, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2229 { AArch64_ST1LN_B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2230 { AArch64_ST1LN_D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2231 { AArch64_ST1LN_H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2232 { AArch64_ST1LN_S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2233 { AArch64_ST1LN_WB_B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2234 { AArch64_ST1LN_WB_B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2235 { AArch64_ST1LN_WB_D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2236 { AArch64_ST1LN_WB_D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2237 { AArch64_ST1LN_WB_H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2238 { AArch64_ST1LN_WB_H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2239 { AArch64_ST1LN_WB_S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2240 { AArch64_ST1LN_WB_S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2241 { AArch64_ST1WB_16B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2242 { AArch64_ST1WB_16B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2243 { AArch64_ST1WB_1D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2244 { AArch64_ST1WB_1D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2245 { AArch64_ST1WB_2D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2246 { AArch64_ST1WB_2D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2247 { AArch64_ST1WB_2S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2248 { AArch64_ST1WB_2S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2249 { AArch64_ST1WB_4H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2250 { AArch64_ST1WB_4H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2251 { AArch64_ST1WB_4S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2252 { AArch64_ST1WB_4S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2253 { AArch64_ST1WB_8B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2254 { AArch64_ST1WB_8B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2255 { AArch64_ST1WB_8H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2256 { AArch64_ST1WB_8H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2257 { AArch64_ST1_16B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2258 { AArch64_ST1_1D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2259 { AArch64_ST1_2D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2260 { AArch64_ST1_2S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2261 { AArch64_ST1_4H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2262 { AArch64_ST1_4S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2263 { AArch64_ST1_8B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2264 { AArch64_ST1_8H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2265 { AArch64_ST1x2WB_16B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2266 { AArch64_ST1x2WB_16B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2267 { AArch64_ST1x2WB_1D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2268 { AArch64_ST1x2WB_1D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2269 { AArch64_ST1x2WB_2D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2270 { AArch64_ST1x2WB_2D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2271 { AArch64_ST1x2WB_2S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2272 { AArch64_ST1x2WB_2S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2273 { AArch64_ST1x2WB_4H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2274 { AArch64_ST1x2WB_4H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2275 { AArch64_ST1x2WB_4S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2276 { AArch64_ST1x2WB_4S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2277 { AArch64_ST1x2WB_8B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2278 { AArch64_ST1x2WB_8B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2279 { AArch64_ST1x2WB_8H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2280 { AArch64_ST1x2WB_8H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2281 { AArch64_ST1x2_16B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2282 { AArch64_ST1x2_1D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2283 { AArch64_ST1x2_2D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2284 { AArch64_ST1x2_2S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2285 { AArch64_ST1x2_4H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2286 { AArch64_ST1x2_4S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2287 { AArch64_ST1x2_8B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2288 { AArch64_ST1x2_8H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2289 { AArch64_ST1x3WB_16B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2290 { AArch64_ST1x3WB_16B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2291 { AArch64_ST1x3WB_1D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2292 { AArch64_ST1x3WB_1D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2293 { AArch64_ST1x3WB_2D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2294 { AArch64_ST1x3WB_2D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2295 { AArch64_ST1x3WB_2S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2296 { AArch64_ST1x3WB_2S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2297 { AArch64_ST1x3WB_4H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2298 { AArch64_ST1x3WB_4H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2299 { AArch64_ST1x3WB_4S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2300 { AArch64_ST1x3WB_4S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2301 { AArch64_ST1x3WB_8B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2302 { AArch64_ST1x3WB_8B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2303 { AArch64_ST1x3WB_8H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2304 { AArch64_ST1x3WB_8H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2305 { AArch64_ST1x3_16B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2306 { AArch64_ST1x3_1D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2307 { AArch64_ST1x3_2D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2308 { AArch64_ST1x3_2S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2309 { AArch64_ST1x3_4H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2310 { AArch64_ST1x3_4S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2311 { AArch64_ST1x3_8B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2312 { AArch64_ST1x3_8H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2313 { AArch64_ST1x4WB_16B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2314 { AArch64_ST1x4WB_16B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2315 { AArch64_ST1x4WB_1D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2316 { AArch64_ST1x4WB_1D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2317 { AArch64_ST1x4WB_2D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2318 { AArch64_ST1x4WB_2D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2319 { AArch64_ST1x4WB_2S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2320 { AArch64_ST1x4WB_2S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2321 { AArch64_ST1x4WB_4H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2322 { AArch64_ST1x4WB_4H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2323 { AArch64_ST1x4WB_4S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2324 { AArch64_ST1x4WB_4S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2325 { AArch64_ST1x4WB_8B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2326 { AArch64_ST1x4WB_8B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2327 { AArch64_ST1x4WB_8H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2328 { AArch64_ST1x4WB_8H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2329 { AArch64_ST1x4_16B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2330 { AArch64_ST1x4_1D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2331 { AArch64_ST1x4_2D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2332 { AArch64_ST1x4_2S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2333 { AArch64_ST1x4_4H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2334 { AArch64_ST1x4_4S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2335 { AArch64_ST1x4_8B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2336 { AArch64_ST1x4_8H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2337 { AArch64_ST2LN_B, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2338 { AArch64_ST2LN_D, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2339 { AArch64_ST2LN_H, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2340 { AArch64_ST2LN_S, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2341 { AArch64_ST2LN_WB_B_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2342 { AArch64_ST2LN_WB_B_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2343 { AArch64_ST2LN_WB_D_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2344 { AArch64_ST2LN_WB_D_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2345 { AArch64_ST2LN_WB_H_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2346 { AArch64_ST2LN_WB_H_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2347 { AArch64_ST2LN_WB_S_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2348 { AArch64_ST2LN_WB_S_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2349 { AArch64_ST2WB_16B_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2350 { AArch64_ST2WB_16B_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2351 { AArch64_ST2WB_2D_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2352 { AArch64_ST2WB_2D_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2353 { AArch64_ST2WB_2S_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2354 { AArch64_ST2WB_2S_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2355 { AArch64_ST2WB_4H_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2356 { AArch64_ST2WB_4H_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2357 { AArch64_ST2WB_4S_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2358 { AArch64_ST2WB_4S_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2359 { AArch64_ST2WB_8B_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2360 { AArch64_ST2WB_8B_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2361 { AArch64_ST2WB_8H_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2362 { AArch64_ST2WB_8H_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2363 { AArch64_ST2_16B, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2364 { AArch64_ST2_2D, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2365 { AArch64_ST2_2S, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2366 { AArch64_ST2_4H, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2367 { AArch64_ST2_4S, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2368 { AArch64_ST2_8B, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2369 { AArch64_ST2_8H, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2370 { AArch64_ST3LN_B, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2371 { AArch64_ST3LN_D, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2372 { AArch64_ST3LN_H, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2373 { AArch64_ST3LN_S, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2374 { AArch64_ST3LN_WB_B_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2375 { AArch64_ST3LN_WB_B_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2376 { AArch64_ST3LN_WB_D_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2377 { AArch64_ST3LN_WB_D_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2378 { AArch64_ST3LN_WB_H_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2379 { AArch64_ST3LN_WB_H_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2380 { AArch64_ST3LN_WB_S_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2381 { AArch64_ST3LN_WB_S_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2382 { AArch64_ST3WB_16B_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2383 { AArch64_ST3WB_16B_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2384 { AArch64_ST3WB_2D_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2385 { AArch64_ST3WB_2D_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2386 { AArch64_ST3WB_2S_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2387 { AArch64_ST3WB_2S_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2388 { AArch64_ST3WB_4H_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2389 { AArch64_ST3WB_4H_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2390 { AArch64_ST3WB_4S_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2391 { AArch64_ST3WB_4S_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2392 { AArch64_ST3WB_8B_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2393 { AArch64_ST3WB_8B_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2394 { AArch64_ST3WB_8H_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2395 { AArch64_ST3WB_8H_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2396 { AArch64_ST3_16B, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2397 { AArch64_ST3_2D, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2398 { AArch64_ST3_2S, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2399 { AArch64_ST3_4H, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2400 { AArch64_ST3_4S, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2401 { AArch64_ST3_8B, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2402 { AArch64_ST3_8H, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2403 { AArch64_ST4LN_B, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2404 { AArch64_ST4LN_D, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2405 { AArch64_ST4LN_H, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2406 { AArch64_ST4LN_S, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2407 { AArch64_ST4LN_WB_B_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2408 { AArch64_ST4LN_WB_B_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2409 { AArch64_ST4LN_WB_D_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2410 { AArch64_ST4LN_WB_D_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2411 { AArch64_ST4LN_WB_H_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2412 { AArch64_ST4LN_WB_H_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2413 { AArch64_ST4LN_WB_S_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2414 { AArch64_ST4LN_WB_S_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2415 { AArch64_ST4WB_16B_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2416 { AArch64_ST4WB_16B_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2417 { AArch64_ST4WB_2D_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2418 { AArch64_ST4WB_2D_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2419 { AArch64_ST4WB_2S_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2420 { AArch64_ST4WB_2S_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2421 { AArch64_ST4WB_4H_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2422 { AArch64_ST4WB_4H_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2423 { AArch64_ST4WB_4S_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2424 { AArch64_ST4WB_4S_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2425 { AArch64_ST4WB_8B_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2426 { AArch64_ST4WB_8B_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2427 { AArch64_ST4WB_8H_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2428 { AArch64_ST4WB_8H_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2429 { AArch64_ST4_16B, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2430 { AArch64_ST4_2D, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2431 { AArch64_ST4_2S, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2432 { AArch64_ST4_4H, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2433 { AArch64_ST4_4S, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2434 { AArch64_ST4_8B, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2435 { AArch64_ST4_8H, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2436 { AArch64_STLR_byte, ARM64_INS_STLRB, { 0 }, { 0 }, { 0 }, 0, 0 },
2437 { AArch64_STLR_dword, ARM64_INS_STLR, { 0 }, { 0 }, { 0 }, 0, 0 },
2438 { AArch64_STLR_hword, ARM64_INS_STLRH, { 0 }, { 0 }, { 0 }, 0, 0 },
2439 { AArch64_STLR_word, ARM64_INS_STLR, { 0 }, { 0 }, { 0 }, 0, 0 },
2440 { AArch64_STLXP_dword, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 }, 0, 0 },
2441 { AArch64_STLXP_word, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 }, 0, 0 },
2442 { AArch64_STLXR_byte, ARM64_INS_STLXRB, { 0 }, { 0 }, { 0 }, 0, 0 },
2443 { AArch64_STLXR_dword, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 }, 0, 0 },
2444 { AArch64_STLXR_hword, ARM64_INS_STLXRH, { 0 }, { 0 }, { 0 }, 0, 0 },
2445 { AArch64_STLXR_word, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 }, 0, 0 },
2446 { AArch64_STXP_dword, ARM64_INS_STXP, { 0 }, { 0 }, { 0 }, 0, 0 },
2447 { AArch64_STXP_word, ARM64_INS_STXP, { 0 }, { 0 }, { 0 }, 0, 0 },
2448 { AArch64_STXR_byte, ARM64_INS_STXRB, { 0 }, { 0 }, { 0 }, 0, 0 },
2449 { AArch64_STXR_dword, ARM64_INS_STXR, { 0 }, { 0 }, { 0 }, 0, 0 },
2450 { AArch64_STXR_hword, ARM64_INS_STXRH, { 0 }, { 0 }, { 0 }, 0, 0 },
2451 { AArch64_STXR_word, ARM64_INS_STXR, { 0 }, { 0 }, { 0 }, 0, 0 },
2452 { AArch64_SUBHN2vvv_16b8h, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2453 { AArch64_SUBHN2vvv_4s2d, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2454 { AArch64_SUBHN2vvv_8h4s, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2455 { AArch64_SUBHNvvv_2s2d, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2456 { AArch64_SUBHNvvv_4h4s, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2457 { AArch64_SUBHNvvv_8b8h, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2458 { AArch64_SUBSwww_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2459 { AArch64_SUBSwww_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2460 { AArch64_SUBSwww_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2461 { AArch64_SUBSwww_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2462 { AArch64_SUBSwww_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2463 { AArch64_SUBSwww_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2464 { AArch64_SUBSwww_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2465 { AArch64_SUBSwww_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2466 { AArch64_SUBSwww_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2467 { AArch64_SUBSwww_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2468 { AArch64_SUBSwww_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2469 { AArch64_SUBSxxw_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2470 { AArch64_SUBSxxw_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2471 { AArch64_SUBSxxw_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2472 { AArch64_SUBSxxw_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2473 { AArch64_SUBSxxw_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2474 { AArch64_SUBSxxw_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2475 { AArch64_SUBSxxx_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2476 { AArch64_SUBSxxx_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2477 { AArch64_SUBSxxx_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2478 { AArch64_SUBSxxx_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2479 { AArch64_SUBSxxx_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2480 { AArch64_SUBddd, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2481 { AArch64_SUBvvv_16B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2482 { AArch64_SUBvvv_2D, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2483 { AArch64_SUBvvv_2S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2484 { AArch64_SUBvvv_4H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2485 { AArch64_SUBvvv_4S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2486 { AArch64_SUBvvv_8B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2487 { AArch64_SUBvvv_8H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2488 { AArch64_SUBwwi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2489 { AArch64_SUBwwi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2490 { AArch64_SUBwwi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2491 { AArch64_SUBwwi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2492 { AArch64_SUBwwi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2493 { AArch64_SUBwwi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2494 { AArch64_SUBwww_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2495 { AArch64_SUBwww_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2496 { AArch64_SUBwww_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2497 { AArch64_SUBwww_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2498 { AArch64_SUBwww_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2499 { AArch64_SUBwww_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2500 { AArch64_SUBwww_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2501 { AArch64_SUBwww_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2502 { AArch64_SUBwww_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2503 { AArch64_SUBwww_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2504 { AArch64_SUBwww_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2505 { AArch64_SUBxxi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2506 { AArch64_SUBxxi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2507 { AArch64_SUBxxi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2508 { AArch64_SUBxxi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2509 { AArch64_SUBxxi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2510 { AArch64_SUBxxi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2511 { AArch64_SUBxxw_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2512 { AArch64_SUBxxw_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2513 { AArch64_SUBxxw_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2514 { AArch64_SUBxxw_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2515 { AArch64_SUBxxw_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2516 { AArch64_SUBxxw_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2517 { AArch64_SUBxxx_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2518 { AArch64_SUBxxx_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2519 { AArch64_SUBxxx_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2520 { AArch64_SUBxxx_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2521 { AArch64_SUBxxx_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
2522 { AArch64_SUQADD16b, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2523 { AArch64_SUQADD2d, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2524 { AArch64_SUQADD2s, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2525 { AArch64_SUQADD4h, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2526 { AArch64_SUQADD4s, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2527 { AArch64_SUQADD8b, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2528 { AArch64_SUQADD8h, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2529 { AArch64_SUQADDbb, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2530 { AArch64_SUQADDdd, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2531 { AArch64_SUQADDhh, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2532 { AArch64_SUQADDss, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2533 { AArch64_SVCi, ARM64_INS_SVC, { 0 }, { 0 }, { 0 }, 1, 0 },
2534 { AArch64_SXTBww, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 }, 0, 0 },
2535 { AArch64_SXTBxw, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 }, 0, 0 },
2536 { AArch64_SXTHww, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 }, 0, 0 },
2537 { AArch64_SXTHxw, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 }, 0, 0 },
2538 { AArch64_SXTWxw, ARM64_INS_SXTW, { 0 }, { 0 }, { 0 }, 0, 0 },
2539 { AArch64_SYSLxicci, ARM64_INS_SYSL, { 0 }, { 0 }, { 0 }, 0, 0 },
2540 { AArch64_SYSiccix, ARM64_INS_SYS, { 0 }, { 0 }, { 0 }, 0, 0 },
2541 { AArch64_TBL1_16b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2542 { AArch64_TBL1_8b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2543 { AArch64_TBL2_16b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2544 { AArch64_TBL2_8b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2545 { AArch64_TBL3_16b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2546 { AArch64_TBL3_8b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2547 { AArch64_TBL4_16b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2548 { AArch64_TBL4_8b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2549 { AArch64_TBNZwii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 }, 1, 0 },
2550 { AArch64_TBNZxii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 }, 1, 0 },
2551 { AArch64_TBX1_16b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2552 { AArch64_TBX1_8b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2553 { AArch64_TBX2_16b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2554 { AArch64_TBX2_8b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2555 { AArch64_TBX3_16b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2556 { AArch64_TBX3_8b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2557 { AArch64_TBX4_16b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2558 { AArch64_TBX4_8b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2559 { AArch64_TBZwii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 }, 1, 0 },
2560 { AArch64_TBZxii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 }, 1, 0 },
2561 { AArch64_TLBIi, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 }, 0, 0 },
2562 { AArch64_TLBIix, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 }, 0, 0 },
2563 { AArch64_TRN1vvv_16b, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2564 { AArch64_TRN1vvv_2d, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2565 { AArch64_TRN1vvv_2s, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2566 { AArch64_TRN1vvv_4h, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2567 { AArch64_TRN1vvv_4s, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2568 { AArch64_TRN1vvv_8b, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2569 { AArch64_TRN1vvv_8h, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2570 { AArch64_TRN2vvv_16b, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2571 { AArch64_TRN2vvv_2d, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2572 { AArch64_TRN2vvv_2s, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2573 { AArch64_TRN2vvv_4h, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2574 { AArch64_TRN2vvv_4s, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2575 { AArch64_TRN2vvv_8b, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2576 { AArch64_TRN2vvv_8h, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2577 { AArch64_TSTww_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2578 { AArch64_TSTww_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2579 { AArch64_TSTww_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2580 { AArch64_TSTww_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2581 { AArch64_TSTxx_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2582 { AArch64_TSTxx_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2583 { AArch64_TSTxx_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2584 { AArch64_TSTxx_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
2585 { AArch64_UABAL2vvv_2d2s, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2586 { AArch64_UABAL2vvv_4s4h, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2587 { AArch64_UABAL2vvv_8h8b, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2588 { AArch64_UABALvvv_2d2s, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2589 { AArch64_UABALvvv_4s4h, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2590 { AArch64_UABALvvv_8h8b, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2591 { AArch64_UABAvvv_16B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2592 { AArch64_UABAvvv_2S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2593 { AArch64_UABAvvv_4H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2594 { AArch64_UABAvvv_4S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2595 { AArch64_UABAvvv_8B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2596 { AArch64_UABAvvv_8H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2597 { AArch64_UABDL2vvv_2d2s, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2598 { AArch64_UABDL2vvv_4s4h, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2599 { AArch64_UABDL2vvv_8h8b, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2600 { AArch64_UABDLvvv_2d2s, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2601 { AArch64_UABDLvvv_4s4h, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2602 { AArch64_UABDLvvv_8h8b, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2603 { AArch64_UABDvvv_16B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2604 { AArch64_UABDvvv_2S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2605 { AArch64_UABDvvv_4H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2606 { AArch64_UABDvvv_4S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2607 { AArch64_UABDvvv_8B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2608 { AArch64_UABDvvv_8H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2609 { AArch64_UADALP16b8h, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2610 { AArch64_UADALP2s1d, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2611 { AArch64_UADALP4h2s, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2612 { AArch64_UADALP4s2d, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2613 { AArch64_UADALP8b4h, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2614 { AArch64_UADALP8h4s, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2615 { AArch64_UADDL2vvv_2d4s, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2616 { AArch64_UADDL2vvv_4s8h, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2617 { AArch64_UADDL2vvv_8h16b, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2618 { AArch64_UADDLP16b8h, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2619 { AArch64_UADDLP2s1d, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2620 { AArch64_UADDLP4h2s, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2621 { AArch64_UADDLP4s2d, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2622 { AArch64_UADDLP8b4h, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2623 { AArch64_UADDLP8h4s, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2624 { AArch64_UADDLV_1d4s, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2625 { AArch64_UADDLV_1h16b, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2626 { AArch64_UADDLV_1h8b, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2627 { AArch64_UADDLV_1s4h, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2628 { AArch64_UADDLV_1s8h, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2629 { AArch64_UADDLvvv_2d2s, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2630 { AArch64_UADDLvvv_4s4h, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2631 { AArch64_UADDLvvv_8h8b, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2632 { AArch64_UADDW2vvv_2d4s, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2633 { AArch64_UADDW2vvv_4s8h, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2634 { AArch64_UADDW2vvv_8h16b, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2635 { AArch64_UADDWvvv_2d2s, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2636 { AArch64_UADDWvvv_4s4h, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2637 { AArch64_UADDWvvv_8h8b, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2638 { AArch64_UBFIZwwii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 }, 0, 0 },
2639 { AArch64_UBFIZxxii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 }, 0, 0 },
2640 { AArch64_UBFMwwii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 }, 0, 0 },
2641 { AArch64_UBFMxxii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 }, 0, 0 },
2642 { AArch64_UBFXwwii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 }, 0, 0 },
2643 { AArch64_UBFXxxii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 }, 0, 0 },
2644 { AArch64_UCVTF_2d, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2645 { AArch64_UCVTF_2s, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2646 { AArch64_UCVTF_4s, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2647 { AArch64_UCVTF_Nddi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2648 { AArch64_UCVTF_Nssi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2649 { AArch64_UCVTFdd, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2650 { AArch64_UCVTFdw, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
2651 { AArch64_UCVTFdwi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
2652 { AArch64_UCVTFdx, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
2653 { AArch64_UCVTFdxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
2654 { AArch64_UCVTFss, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2655 { AArch64_UCVTFsw, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
2656 { AArch64_UCVTFswi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
2657 { AArch64_UCVTFsx, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
2658 { AArch64_UCVTFsxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
2659 { AArch64_UDIVwww, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
2660 { AArch64_UDIVxxx, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
2661 { AArch64_UHADDvvv_16B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2662 { AArch64_UHADDvvv_2S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2663 { AArch64_UHADDvvv_4H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2664 { AArch64_UHADDvvv_4S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2665 { AArch64_UHADDvvv_8B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2666 { AArch64_UHADDvvv_8H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2667 { AArch64_UHSUBvvv_16B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2668 { AArch64_UHSUBvvv_2S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2669 { AArch64_UHSUBvvv_4H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2670 { AArch64_UHSUBvvv_4S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2671 { AArch64_UHSUBvvv_8B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2672 { AArch64_UHSUBvvv_8H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2673 { AArch64_UMADDLxwwx, ARM64_INS_UMADDL, { 0 }, { 0 }, { 0 }, 0, 0 },
2674 { AArch64_UMAXPvvv_16B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2675 { AArch64_UMAXPvvv_2S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2676 { AArch64_UMAXPvvv_4H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2677 { AArch64_UMAXPvvv_4S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2678 { AArch64_UMAXPvvv_8B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2679 { AArch64_UMAXPvvv_8H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2680 { AArch64_UMAXV_1b16b, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2681 { AArch64_UMAXV_1b8b, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2682 { AArch64_UMAXV_1h4h, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2683 { AArch64_UMAXV_1h8h, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2684 { AArch64_UMAXV_1s4s, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2685 { AArch64_UMAXvvv_16B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2686 { AArch64_UMAXvvv_2S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2687 { AArch64_UMAXvvv_4H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2688 { AArch64_UMAXvvv_4S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2689 { AArch64_UMAXvvv_8B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2690 { AArch64_UMAXvvv_8H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2691 { AArch64_UMINPvvv_16B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2692 { AArch64_UMINPvvv_2S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2693 { AArch64_UMINPvvv_4H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2694 { AArch64_UMINPvvv_4S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2695 { AArch64_UMINPvvv_8B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2696 { AArch64_UMINPvvv_8H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2697 { AArch64_UMINV_1b16b, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2698 { AArch64_UMINV_1b8b, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2699 { AArch64_UMINV_1h4h, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2700 { AArch64_UMINV_1h8h, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2701 { AArch64_UMINV_1s4s, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2702 { AArch64_UMINvvv_16B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2703 { AArch64_UMINvvv_2S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2704 { AArch64_UMINvvv_4H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2705 { AArch64_UMINvvv_4S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2706 { AArch64_UMINvvv_8B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2707 { AArch64_UMINvvv_8H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2708 { AArch64_UMLAL2vvv_2d4s, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2709 { AArch64_UMLAL2vvv_4s8h, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2710 { AArch64_UMLAL2vvv_8h16b, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2711 { AArch64_UMLALvve_2d2s, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2712 { AArch64_UMLALvve_2d4s, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2713 { AArch64_UMLALvve_4s4h, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2714 { AArch64_UMLALvve_4s8h, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2715 { AArch64_UMLALvvv_2d2s, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2716 { AArch64_UMLALvvv_4s4h, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2717 { AArch64_UMLALvvv_8h8b, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2718 { AArch64_UMLSL2vvv_2d4s, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2719 { AArch64_UMLSL2vvv_4s8h, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2720 { AArch64_UMLSL2vvv_8h16b, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2721 { AArch64_UMLSLvve_2d2s, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2722 { AArch64_UMLSLvve_2d4s, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2723 { AArch64_UMLSLvve_4s4h, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2724 { AArch64_UMLSLvve_4s8h, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2725 { AArch64_UMLSLvvv_2d2s, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2726 { AArch64_UMLSLvvv_4s4h, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2727 { AArch64_UMLSLvvv_8h8b, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2728 { AArch64_UMOVwb, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2729 { AArch64_UMOVwh, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2730 { AArch64_UMOVws, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2731 { AArch64_UMOVxd, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2732 { AArch64_UMSUBLxwwx, ARM64_INS_UMSUBL, { 0 }, { 0 }, { 0 }, 0, 0 },
2733 { AArch64_UMULHxxx, ARM64_INS_UMULH, { 0 }, { 0 }, { 0 }, 0, 0 },
2734 { AArch64_UMULL2vvv_2d4s, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2735 { AArch64_UMULL2vvv_4s8h, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2736 { AArch64_UMULL2vvv_8h16b, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2737 { AArch64_UMULLve_2d2s, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2738 { AArch64_UMULLve_2d4s, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2739 { AArch64_UMULLve_4s4h, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2740 { AArch64_UMULLve_4s8h, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2741 { AArch64_UMULLvvv_2d2s, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2742 { AArch64_UMULLvvv_4s4h, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2743 { AArch64_UMULLvvv_8h8b, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2744 { AArch64_UQADDbbb, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2745 { AArch64_UQADDddd, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2746 { AArch64_UQADDhhh, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2747 { AArch64_UQADDsss, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2748 { AArch64_UQADDvvv_16B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2749 { AArch64_UQADDvvv_2D, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2750 { AArch64_UQADDvvv_2S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2751 { AArch64_UQADDvvv_4H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2752 { AArch64_UQADDvvv_4S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2753 { AArch64_UQADDvvv_8B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2754 { AArch64_UQADDvvv_8H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2755 { AArch64_UQRSHLbbb, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2756 { AArch64_UQRSHLddd, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2757 { AArch64_UQRSHLhhh, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2758 { AArch64_UQRSHLsss, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2759 { AArch64_UQRSHLvvv_16B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2760 { AArch64_UQRSHLvvv_2D, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2761 { AArch64_UQRSHLvvv_2S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2762 { AArch64_UQRSHLvvv_4H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2763 { AArch64_UQRSHLvvv_4S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2764 { AArch64_UQRSHLvvv_8B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2765 { AArch64_UQRSHLvvv_8H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2766 { AArch64_UQRSHRNbhi, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2767 { AArch64_UQRSHRNhsi, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2768 { AArch64_UQRSHRNsdi, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2769 { AArch64_UQRSHRNvvi_16B, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2770 { AArch64_UQRSHRNvvi_2S, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2771 { AArch64_UQRSHRNvvi_4H, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2772 { AArch64_UQRSHRNvvi_4S, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2773 { AArch64_UQRSHRNvvi_8B, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2774 { AArch64_UQRSHRNvvi_8H, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2775 { AArch64_UQSHLbbb, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2776 { AArch64_UQSHLbbi, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2777 { AArch64_UQSHLddd, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2778 { AArch64_UQSHLddi, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2779 { AArch64_UQSHLhhh, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2780 { AArch64_UQSHLhhi, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2781 { AArch64_UQSHLssi, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2782 { AArch64_UQSHLsss, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2783 { AArch64_UQSHLvvi_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2784 { AArch64_UQSHLvvi_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2785 { AArch64_UQSHLvvi_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2786 { AArch64_UQSHLvvi_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2787 { AArch64_UQSHLvvi_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2788 { AArch64_UQSHLvvi_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2789 { AArch64_UQSHLvvi_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2790 { AArch64_UQSHLvvv_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2791 { AArch64_UQSHLvvv_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2792 { AArch64_UQSHLvvv_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2793 { AArch64_UQSHLvvv_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2794 { AArch64_UQSHLvvv_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2795 { AArch64_UQSHLvvv_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2796 { AArch64_UQSHLvvv_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2797 { AArch64_UQSHRNbhi, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2798 { AArch64_UQSHRNhsi, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2799 { AArch64_UQSHRNsdi, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2800 { AArch64_UQSHRNvvi_16B, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2801 { AArch64_UQSHRNvvi_2S, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2802 { AArch64_UQSHRNvvi_4H, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2803 { AArch64_UQSHRNvvi_4S, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2804 { AArch64_UQSHRNvvi_8B, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2805 { AArch64_UQSHRNvvi_8H, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2806 { AArch64_UQSUBbbb, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2807 { AArch64_UQSUBddd, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2808 { AArch64_UQSUBhhh, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2809 { AArch64_UQSUBsss, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2810 { AArch64_UQSUBvvv_16B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2811 { AArch64_UQSUBvvv_2D, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2812 { AArch64_UQSUBvvv_2S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2813 { AArch64_UQSUBvvv_4H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2814 { AArch64_UQSUBvvv_4S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2815 { AArch64_UQSUBvvv_8B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2816 { AArch64_UQSUBvvv_8H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2817 { AArch64_UQXTN2d2s, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2818 { AArch64_UQXTN2d4s, ARM64_INS_UQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2819 { AArch64_UQXTN4s4h, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2820 { AArch64_UQXTN4s8h, ARM64_INS_UQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2821 { AArch64_UQXTN8h16b, ARM64_INS_UQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2822 { AArch64_UQXTN8h8b, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2823 { AArch64_UQXTNbh, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2824 { AArch64_UQXTNhs, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2825 { AArch64_UQXTNsd, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2826 { AArch64_URECPE2s, ARM64_INS_URECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2827 { AArch64_URECPE4s, ARM64_INS_URECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2828 { AArch64_URHADDvvv_16B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2829 { AArch64_URHADDvvv_2S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2830 { AArch64_URHADDvvv_4H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2831 { AArch64_URHADDvvv_4S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2832 { AArch64_URHADDvvv_8B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2833 { AArch64_URHADDvvv_8H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2834 { AArch64_URSHLddd, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2835 { AArch64_URSHLvvv_16B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2836 { AArch64_URSHLvvv_2D, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2837 { AArch64_URSHLvvv_2S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2838 { AArch64_URSHLvvv_4H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2839 { AArch64_URSHLvvv_4S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2840 { AArch64_URSHLvvv_8B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2841 { AArch64_URSHLvvv_8H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2842 { AArch64_URSHRddi, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2843 { AArch64_URSHRvvi_16B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2844 { AArch64_URSHRvvi_2D, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2845 { AArch64_URSHRvvi_2S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2846 { AArch64_URSHRvvi_4H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2847 { AArch64_URSHRvvi_4S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2848 { AArch64_URSHRvvi_8B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2849 { AArch64_URSHRvvi_8H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2850 { AArch64_URSQRTE2s, ARM64_INS_URSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2851 { AArch64_URSQRTE4s, ARM64_INS_URSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2852 { AArch64_URSRA, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2853 { AArch64_URSRAvvi_16B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2854 { AArch64_URSRAvvi_2D, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2855 { AArch64_URSRAvvi_2S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2856 { AArch64_URSRAvvi_4H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2857 { AArch64_URSRAvvi_4S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2858 { AArch64_URSRAvvi_8B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2859 { AArch64_URSRAvvi_8H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2860 { AArch64_USHLLvvi_16B, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2861 { AArch64_USHLLvvi_2S, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2862 { AArch64_USHLLvvi_4H, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2863 { AArch64_USHLLvvi_4S, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2864 { AArch64_USHLLvvi_8B, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2865 { AArch64_USHLLvvi_8H, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2866 { AArch64_USHLddd, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2867 { AArch64_USHLvvv_16B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2868 { AArch64_USHLvvv_2D, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2869 { AArch64_USHLvvv_2S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2870 { AArch64_USHLvvv_4H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2871 { AArch64_USHLvvv_4S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2872 { AArch64_USHLvvv_8B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2873 { AArch64_USHLvvv_8H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2874 { AArch64_USHRddi, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2875 { AArch64_USHRvvi_16B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2876 { AArch64_USHRvvi_2D, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2877 { AArch64_USHRvvi_2S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2878 { AArch64_USHRvvi_4H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2879 { AArch64_USHRvvi_4S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2880 { AArch64_USHRvvi_8B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2881 { AArch64_USHRvvi_8H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2882 { AArch64_USQADD16b, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2883 { AArch64_USQADD2d, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2884 { AArch64_USQADD2s, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2885 { AArch64_USQADD4h, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2886 { AArch64_USQADD4s, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2887 { AArch64_USQADD8b, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2888 { AArch64_USQADD8h, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2889 { AArch64_USQADDbb, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2890 { AArch64_USQADDdd, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2891 { AArch64_USQADDhh, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2892 { AArch64_USQADDss, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2893 { AArch64_USRA, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2894 { AArch64_USRAvvi_16B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2895 { AArch64_USRAvvi_2D, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2896 { AArch64_USRAvvi_2S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2897 { AArch64_USRAvvi_4H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2898 { AArch64_USRAvvi_4S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2899 { AArch64_USRAvvi_8B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2900 { AArch64_USRAvvi_8H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2901 { AArch64_USUBL2vvv_2d4s, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2902 { AArch64_USUBL2vvv_4s8h, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2903 { AArch64_USUBL2vvv_8h16b, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2904 { AArch64_USUBLvvv_2d2s, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2905 { AArch64_USUBLvvv_4s4h, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2906 { AArch64_USUBLvvv_8h8b, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2907 { AArch64_USUBW2vvv_2d4s, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2908 { AArch64_USUBW2vvv_4s8h, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2909 { AArch64_USUBW2vvv_8h16b, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2910 { AArch64_USUBWvvv_2d2s, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2911 { AArch64_USUBWvvv_4s4h, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2912 { AArch64_USUBWvvv_8h8b, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2913 { AArch64_UXTBww, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 }, 0, 0 },
2914 { AArch64_UXTBxw, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 }, 0, 0 },
2915 { AArch64_UXTHww, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 }, 0, 0 },
2916 { AArch64_UXTHxw, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 }, 0, 0 },
2917 { AArch64_UZP1vvv_16b, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2918 { AArch64_UZP1vvv_2d, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2919 { AArch64_UZP1vvv_2s, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2920 { AArch64_UZP1vvv_4h, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2921 { AArch64_UZP1vvv_4s, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2922 { AArch64_UZP1vvv_8b, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2923 { AArch64_UZP1vvv_8h, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2924 { AArch64_UZP2vvv_16b, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2925 { AArch64_UZP2vvv_2d, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2926 { AArch64_UZP2vvv_2s, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2927 { AArch64_UZP2vvv_4h, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2928 { AArch64_UZP2vvv_4s, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2929 { AArch64_UZP2vvv_8b, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2930 { AArch64_UZP2vvv_8h, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2931 { AArch64_VCVTf2xs_2D, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2932 { AArch64_VCVTf2xs_2S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2933 { AArch64_VCVTf2xs_4S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2934 { AArch64_VCVTf2xu_2D, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2935 { AArch64_VCVTf2xu_2S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2936 { AArch64_VCVTf2xu_4S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2937 { AArch64_VCVTxs2f_2D, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2938 { AArch64_VCVTxs2f_2S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2939 { AArch64_VCVTxs2f_4S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2940 { AArch64_VCVTxu2f_2D, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2941 { AArch64_VCVTxu2f_2S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2942 { AArch64_VCVTxu2f_4S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2943 { AArch64_XTN2d2s, ARM64_INS_XTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2944 { AArch64_XTN2d4s, ARM64_INS_XTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2945 { AArch64_XTN4s4h, ARM64_INS_XTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2946 { AArch64_XTN4s8h, ARM64_INS_XTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2947 { AArch64_XTN8h16b, ARM64_INS_XTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2948 { AArch64_XTN8h8b, ARM64_INS_XTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2949 { AArch64_ZIP1vvv_16b, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2950 { AArch64_ZIP1vvv_2d, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2951 { AArch64_ZIP1vvv_2s, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2952 { AArch64_ZIP1vvv_4h, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2953 { AArch64_ZIP1vvv_4s, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2954 { AArch64_ZIP1vvv_8b, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2955 { AArch64_ZIP1vvv_8h, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2956 { AArch64_ZIP2vvv_16b, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2957 { AArch64_ZIP2vvv_2d, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2958 { AArch64_ZIP2vvv_2s, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2959 { AArch64_ZIP2vvv_4h, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2960 { AArch64_ZIP2vvv_4s, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2961 { AArch64_ZIP2vvv_8b, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
2962 { AArch64_ZIP2vvv_8h, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]2963};
2964
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]2965// some alias instruction only need to be defined locally to satisfy
2966// some lookup functions
2967// just make sure these IDs never reuse any other IDs ARM_INS_*
2968#define ARM64_INS_NEGS -1
2969#define ARM64_INS_NGCS -2
2970
2971// all alias instructions & their semantic infos
2972static insn_map alias_insns[] = {
2973 { AArch64_MSUBwwww, ARM64_INS_MNEG, { 0 }, { 0 }, { 0 } },
2974 { AArch64_UMSUBLxwwx, ARM64_INS_UMNEGL, { 0 }, { 0 }, { 0 } },
2975 { AArch64_SMSUBLxwwx, ARM64_INS_SMNEGL, { 0 }, { 0 }, { 0 } },
2976 // MOV can be mapped back to ADD or ORR, but its semantic info is always same
2977 { AArch64_ADDwwi_lsl0_s, ARM64_INS_MOV, { 0 }, { 0 }, { 0 } },
2978 // { AArch64_ADDxxi_lsl0_s, ARM64_INS_MOV, { 0 }, { 0 }, { 0 } },
2979 // { AArch64_ORRwww_lsl, ARM64_INS_MOV, { 0 }, { 0 }, { 0 } },
2980 // { AArch64_ORRxxx_lsl, ARM64_INS_MOV, { 0 }, { 0 }, { 0 } },
2981 { AArch64_HINTi, ARM64_INS_NOP, { 0 }, { 0 }, { 0 } },
2982 { AArch64_HINTi, ARM64_INS_YIELD, { 0 }, { 0 }, { 0 } },
2983 { AArch64_HINTi, ARM64_INS_WFE, { 0 }, { 0 }, { 0 } },
2984 { AArch64_HINTi, ARM64_INS_WFI, { 0 }, { 0 }, { 0 } },
2985 { AArch64_HINTi, ARM64_INS_SEV, { 0 }, { 0 }, { 0 } },
2986 { AArch64_HINTi, ARM64_INS_SEVL, { 0 }, { 0 }, { 0 } },
2987 { AArch64_SBCwww, ARM64_INS_NGC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
2988 { AArch64_SBCSwww, ARM64_INS_NGCS, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
2989 { AArch64_SUBSwww_lsl, ARM64_INS_NEGS, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
2990 // { AArch64_SUBSxxx_lsl, ARM64_INS_NEGS, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]2991};
2992
Nguyen Anh Quynh4d3e8522013-12-14 10:45:09 +0800[diff] [blame]2993void AArch64_get_insn_id(cs_insn *insn, unsigned int id, int detail)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]2994{
2995 int i = insn_find(insns, ARR_SIZE(insns), id);
2996 if (i != -1) {
2997 insn->id = insns[i].mapid;
Nguyen Anh Quynhf35e2ad2013-12-03 11:10:26 +0800[diff] [blame]2998
Nguyen Anh Quynh4d3e8522013-12-14 10:45:09 +0800[diff] [blame]2999 if (detail) {
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame^]3000 cs_struct handle;
3001 handle.detail = detail;
3002 memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
3003 insn->detail->regs_read_count = count_positive(insns[i].regs_use);
Nguyen Anh Quynhf35e2ad2013-12-03 11:10:26 +0800[diff] [blame]3004
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame^]3005 memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
3006 insn->detail->regs_write_count = count_positive(insns[i].regs_mod);
Nguyen Anh Quynhf35e2ad2013-12-03 11:10:26 +0800[diff] [blame]3007
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame^]3008 memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
3009 insn->detail->groups_count = count_positive(insns[i].groups);
Nguyen Anh Quynhf35e2ad2013-12-03 11:10:26 +0800[diff] [blame]3010
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame^]3011 insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV);
Nguyen Anh Quynhec0ed8e2013-12-02 13:55:38 +0800[diff] [blame]3012
Nguyen Anh Quynh4d3e8522013-12-14 10:45:09 +0800[diff] [blame]3013 if (insns[i].branch || insns[i].indirect_branch) {
3014 // this insn also belongs to JUMP group. add JUMP group
Nguyen Anh Quynh4fe224b2013-12-24 16:49:36 +0800[diff] [blame^]3015 insn->detail->groups[insn->detail->groups_count] = ARM64_GRP_JUMP;
3016 insn->detail->groups_count++;
Nguyen Anh Quynh4d3e8522013-12-14 10:45:09 +0800[diff] [blame]3017 }
Nguyen Anh Quynhec0ed8e2013-12-02 13:55:38 +0800[diff] [blame]3018 }
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3019 }
3020}
3021
Nguyen Anh Quynh6b7abe32013-11-30 00:54:24 +0800[diff] [blame]3022// given public insn id, return internal instruction ID
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3023unsigned int AArch64_get_insn_id2(unsigned int id)
3024{
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]3025 unsigned int res = insn_reverse_id(insns, ARR_SIZE(insns), id);
3026 if (!res) // is this alias insn?
3027 res = insn_reverse_id(alias_insns, ARR_SIZE(alias_insns), id);
3028
3029 return res;
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3030}
3031
3032static name_map insn_name_maps[] = {
3033 { ARM64_INS_INVALID, NULL },
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]3034 //=========
3035
3036 { ARM64_INS_ABS, "abs" },
3037 { ARM64_INS_ADC, "adc" },
3038 { ARM64_INS_ADDHN2, "addhn2" },
3039 { ARM64_INS_ADDHN, "addhn" },
3040 { ARM64_INS_ADDP, "addp" },
3041 { ARM64_INS_ADDV, "addv" },
3042 { ARM64_INS_ADD, "add" },
3043 { ARM64_INS_CMN, "cmn" },
3044 { ARM64_INS_ADRP, "adrp" },
3045 { ARM64_INS_ADR, "adr" },
3046 { ARM64_INS_AESD, "aesd" },
3047 { ARM64_INS_AESE, "aese" },
3048 { ARM64_INS_AESIMC, "aesimc" },
3049 { ARM64_INS_AESMC, "aesmc" },
3050 { ARM64_INS_AND, "and" },
3051 { ARM64_INS_ASR, "asr" },
3052 { ARM64_INS_AT, "at" },
3053 { ARM64_INS_BFI, "bfi" },
3054 { ARM64_INS_BFM, "bfm" },
3055 { ARM64_INS_BFXIL, "bfxil" },
3056 { ARM64_INS_BIC, "bic" },
3057 { ARM64_INS_BIF, "bif" },
3058 { ARM64_INS_BIT, "bit" },
3059 { ARM64_INS_BLR, "blr" },
3060 { ARM64_INS_BL, "bl" },
3061 { ARM64_INS_BRK, "brk" },
3062 { ARM64_INS_BR, "br" },
3063 { ARM64_INS_BSL, "bsl" },
3064 { ARM64_INS_B, "b" },
3065 { ARM64_INS_CBNZ, "cbnz" },
3066 { ARM64_INS_CBZ, "cbz" },
3067 { ARM64_INS_CCMN, "ccmn" },
3068 { ARM64_INS_CCMP, "ccmp" },
3069 { ARM64_INS_CLREX, "clrex" },
3070 { ARM64_INS_CLS, "cls" },
3071 { ARM64_INS_CLZ, "clz" },
3072 { ARM64_INS_CMEQ, "cmeq" },
3073 { ARM64_INS_CMGE, "cmge" },
3074 { ARM64_INS_CMGT, "cmgt" },
3075 { ARM64_INS_CMHI, "cmhi" },
3076 { ARM64_INS_CMHS, "cmhs" },
3077 { ARM64_INS_CMLE, "cmle" },
3078 { ARM64_INS_CMLT, "cmlt" },
3079 { ARM64_INS_CMP, "cmp" },
3080 { ARM64_INS_CMTST, "cmtst" },
3081 { ARM64_INS_CNT, "cnt" },
3082 { ARM64_INS_CRC32B, "crc32b" },
3083 { ARM64_INS_CRC32CB, "crc32cb" },
3084 { ARM64_INS_CRC32CH, "crc32ch" },
3085 { ARM64_INS_CRC32CW, "crc32cw" },
3086 { ARM64_INS_CRC32CX, "crc32cx" },
3087 { ARM64_INS_CRC32H, "crc32h" },
3088 { ARM64_INS_CRC32W, "crc32w" },
3089 { ARM64_INS_CRC32X, "crc32x" },
3090 { ARM64_INS_CSEL, "csel" },
3091 { ARM64_INS_CSINC, "csinc" },
3092 { ARM64_INS_CSINV, "csinv" },
3093 { ARM64_INS_CSNEG, "csneg" },
3094 { ARM64_INS_DCPS1, "dcps1" },
3095 { ARM64_INS_DCPS2, "dcps2" },
3096 { ARM64_INS_DCPS3, "dcps3" },
3097 { ARM64_INS_DC, "dc" },
3098 { ARM64_INS_DMB, "dmb" },
3099 { ARM64_INS_DRPS, "drps" },
3100 { ARM64_INS_DSB, "dsb" },
3101 { ARM64_INS_DUP, "dup" },
3102 { ARM64_INS_EON, "eon" },
3103 { ARM64_INS_EOR, "eor" },
3104 { ARM64_INS_ERET, "eret" },
3105 { ARM64_INS_EXTR, "extr" },
3106 { ARM64_INS_EXT, "ext" },
3107 { ARM64_INS_FABD, "fabd" },
3108 { ARM64_INS_FABS, "fabs" },
3109 { ARM64_INS_FACGE, "facge" },
3110 { ARM64_INS_FACGT, "facgt" },
3111 { ARM64_INS_FADDP, "faddp" },
3112 { ARM64_INS_FADD, "fadd" },
3113 { ARM64_INS_FCCMPE, "fccmpe" },
3114 { ARM64_INS_FCCMP, "fccmp" },
3115 { ARM64_INS_FCMEQ, "fcmeq" },
3116 { ARM64_INS_FCMGE, "fcmge" },
3117 { ARM64_INS_FCMGT, "fcmgt" },
3118 { ARM64_INS_FCMLE, "fcmle" },
3119 { ARM64_INS_FCMLT, "fcmlt" },
3120 { ARM64_INS_FCMP, "fcmp" },
3121 { ARM64_INS_FCMPE, "fcmpe" },
3122 { ARM64_INS_FCSEL, "fcsel" },
3123 { ARM64_INS_FCVTAS, "fcvtas" },
3124 { ARM64_INS_FCVTAU, "fcvtau" },
3125 { ARM64_INS_FCVTL, "fcvtl" },
3126 { ARM64_INS_FCVTL2, "fcvtl2" },
3127 { ARM64_INS_FCVTMS, "fcvtms" },
3128 { ARM64_INS_FCVTMU, "fcvtmu" },
3129 { ARM64_INS_FCVTN, "fcvtn" },
3130 { ARM64_INS_FCVTN2, "fcvtn2" },
3131 { ARM64_INS_FCVTNS, "fcvtns" },
3132 { ARM64_INS_FCVTNU, "fcvtnu" },
3133 { ARM64_INS_FCVTPS, "fcvtps" },
3134 { ARM64_INS_FCVTPU, "fcvtpu" },
3135 { ARM64_INS_FCVTXN, "fcvtxn" },
3136 { ARM64_INS_FCVTXN2, "fcvtxn2" },
3137 { ARM64_INS_FCVTZS, "fcvtzs" },
3138 { ARM64_INS_FCVTZU, "fcvtzu" },
3139 { ARM64_INS_FCVT, "fcvt" },
3140 { ARM64_INS_FDIV, "fdiv" },
3141 { ARM64_INS_FMADD, "fmadd" },
3142 { ARM64_INS_FMAXNMP, "fmaxnmp" },
3143 { ARM64_INS_FMAXNMV, "fmaxnmv" },
3144 { ARM64_INS_FMAXNM, "fmaxnm" },
3145 { ARM64_INS_FMAXP, "fmaxp" },
3146 { ARM64_INS_FMAXV, "fmaxv" },
3147 { ARM64_INS_FMAX, "fmax" },
3148 { ARM64_INS_FMINNMP, "fminnmp" },
3149 { ARM64_INS_FMINNMV, "fminnmv" },
3150 { ARM64_INS_FMINNM, "fminnm" },
3151 { ARM64_INS_FMINP, "fminp" },
3152 { ARM64_INS_FMINV, "fminv" },
3153 { ARM64_INS_FMIN, "fmin" },
3154 { ARM64_INS_FMLA, "fmla" },
3155 { ARM64_INS_FMLS, "fmls" },
3156 { ARM64_INS_FMOV, "fmov" },
3157 { ARM64_INS_FMSUB, "fmsub" },
3158 { ARM64_INS_FMULX, "fmulx" },
3159 { ARM64_INS_FMUL, "fmul" },
3160 { ARM64_INS_FNEG, "fneg" },
3161 { ARM64_INS_FNMADD, "fnmadd" },
3162 { ARM64_INS_FNMSUB, "fnmsub" },
3163 { ARM64_INS_FNMUL, "fnmul" },
3164 { ARM64_INS_FRECPE, "frecpe" },
3165 { ARM64_INS_FRECPS, "frecps" },
3166 { ARM64_INS_FRECPX, "frecpx" },
3167 { ARM64_INS_FRINTA, "frinta" },
3168 { ARM64_INS_FRINTI, "frinti" },
3169 { ARM64_INS_FRINTM, "frintm" },
3170 { ARM64_INS_FRINTN, "frintn" },
3171 { ARM64_INS_FRINTP, "frintp" },
3172 { ARM64_INS_FRINTX, "frintx" },
3173 { ARM64_INS_FRINTZ, "frintz" },
3174 { ARM64_INS_FRSQRTE, "frsqrte" },
3175 { ARM64_INS_FRSQRTS, "frsqrts" },
3176 { ARM64_INS_FSQRT, "fsqrt" },
3177 { ARM64_INS_FSUB, "fsub" },
3178 { ARM64_INS_HINT, "hint" },
3179 { ARM64_INS_HLT, "hlt" },
3180 { ARM64_INS_HVC, "hvc" },
3181 { ARM64_INS_IC, "ic" },
3182 { ARM64_INS_INS, "ins" },
3183 { ARM64_INS_ISB, "isb" },
3184 { ARM64_INS_LD1, "ld1" },
3185 { ARM64_INS_LD1R, "ld1r" },
3186 { ARM64_INS_LD2, "ld2" },
3187 { ARM64_INS_LD2R, "ld2r" },
3188 { ARM64_INS_LD3, "ld3" },
3189 { ARM64_INS_LD3R, "ld3r" },
3190 { ARM64_INS_LD4, "ld4" },
3191 { ARM64_INS_LD4R, "ld4r" },
3192 { ARM64_INS_LDARB, "ldarb" },
3193 { ARM64_INS_LDAR, "ldar" },
3194 { ARM64_INS_LDARH, "ldarh" },
3195 { ARM64_INS_LDAXP, "ldaxp" },
3196 { ARM64_INS_LDAXRB, "ldaxrb" },
3197 { ARM64_INS_LDAXR, "ldaxr" },
3198 { ARM64_INS_LDAXRH, "ldaxrh" },
3199 { ARM64_INS_LDPSW, "ldpsw" },
3200 { ARM64_INS_LDRSB, "ldrsb" },
3201 { ARM64_INS_LDURSB, "ldursb" },
3202 { ARM64_INS_LDRSH, "ldrsh" },
3203 { ARM64_INS_LDURSH, "ldursh" },
3204 { ARM64_INS_LDRSW, "ldrsw" },
3205 { ARM64_INS_LDR, "ldr" },
3206 { ARM64_INS_LDTRSB, "ldtrsb" },
3207 { ARM64_INS_LDTRSH, "ldtrsh" },
3208 { ARM64_INS_LDTRSW, "ldtrsw" },
3209 { ARM64_INS_LDURSW, "ldursw" },
3210 { ARM64_INS_LDXP, "ldxp" },
3211 { ARM64_INS_LDXRB, "ldxrb" },
3212 { ARM64_INS_LDXR, "ldxr" },
3213 { ARM64_INS_LDXRH, "ldxrh" },
3214 { ARM64_INS_LDRH, "ldrh" },
3215 { ARM64_INS_LDURH, "ldurh" },
3216 { ARM64_INS_STRH, "strh" },
3217 { ARM64_INS_STURH, "sturh" },
3218 { ARM64_INS_LDTRH, "ldtrh" },
3219 { ARM64_INS_STTRH, "sttrh" },
3220 { ARM64_INS_LDUR, "ldur" },
3221 { ARM64_INS_STR, "str" },
3222 { ARM64_INS_STUR, "stur" },
3223 { ARM64_INS_LDTR, "ldtr" },
3224 { ARM64_INS_STTR, "sttr" },
3225 { ARM64_INS_LDRB, "ldrb" },
3226 { ARM64_INS_LDURB, "ldurb" },
3227 { ARM64_INS_STRB, "strb" },
3228 { ARM64_INS_STURB, "sturb" },
3229 { ARM64_INS_LDTRB, "ldtrb" },
3230 { ARM64_INS_STTRB, "sttrb" },
3231 { ARM64_INS_LDP, "ldp" },
3232 { ARM64_INS_LDNP, "ldnp" },
3233 { ARM64_INS_STNP, "stnp" },
3234 { ARM64_INS_STP, "stp" },
3235 { ARM64_INS_LSL, "lsl" },
3236 { ARM64_INS_LSR, "lsr" },
3237 { ARM64_INS_MADD, "madd" },
3238 { ARM64_INS_MLA, "mla" },
3239 { ARM64_INS_MLS, "mls" },
3240 { ARM64_INS_MOVI, "movi" },
3241 { ARM64_INS_MOVK, "movk" },
3242 { ARM64_INS_MOVN, "movn" },
3243 { ARM64_INS_MOVZ, "movz" },
3244 { ARM64_INS_MRS, "mrs" },
3245 { ARM64_INS_MSR, "msr" },
3246 { ARM64_INS_MSUB, "msub" },
3247 { ARM64_INS_MUL, "mul" },
3248 { ARM64_INS_MVNI, "mvni" },
3249 { ARM64_INS_MVN, "mvn" },
3250 { ARM64_INS_NEG, "neg" },
3251 { ARM64_INS_NOT, "not" },
3252 { ARM64_INS_ORN, "orn" },
3253 { ARM64_INS_ORR, "orr" },
3254 { ARM64_INS_PMULL2, "pmull2" },
3255 { ARM64_INS_PMULL, "pmull" },
3256 { ARM64_INS_PMUL, "pmul" },
3257 { ARM64_INS_PRFM, "prfm" },
3258 { ARM64_INS_PRFUM, "prfum" },
3259 { ARM64_INS_SQRSHRUN2, "sqrshrun2" },
3260 { ARM64_INS_SQRSHRUN, "sqrshrun" },
3261 { ARM64_INS_SQSHRUN2, "sqshrun2" },
3262 { ARM64_INS_SQSHRUN, "sqshrun" },
3263 { ARM64_INS_RADDHN2, "raddhn2" },
3264 { ARM64_INS_RADDHN, "raddhn" },
3265 { ARM64_INS_RBIT, "rbit" },
3266 { ARM64_INS_RET, "ret" },
3267 { ARM64_INS_REV16, "rev16" },
3268 { ARM64_INS_REV32, "rev32" },
3269 { ARM64_INS_REV64, "rev64" },
3270 { ARM64_INS_REV, "rev" },
3271 { ARM64_INS_ROR, "ror" },
3272 { ARM64_INS_RSHRN2, "rshrn2" },
3273 { ARM64_INS_RSHRN, "rshrn" },
3274 { ARM64_INS_RSUBHN2, "rsubhn2" },
3275 { ARM64_INS_RSUBHN, "rsubhn" },
3276 { ARM64_INS_SABAL2, "sabal2" },
3277 { ARM64_INS_SABAL, "sabal" },
3278 { ARM64_INS_SABA, "saba" },
3279 { ARM64_INS_SABDL2, "sabdl2" },
3280 { ARM64_INS_SABDL, "sabdl" },
3281 { ARM64_INS_SABD, "sabd" },
3282 { ARM64_INS_SADALP, "sadalp" },
3283 { ARM64_INS_SADDL2, "saddl2" },
3284 { ARM64_INS_SADDLP, "saddlp" },
3285 { ARM64_INS_SADDLV, "saddlv" },
3286 { ARM64_INS_SADDL, "saddl" },
3287 { ARM64_INS_SADDW2, "saddw2" },
3288 { ARM64_INS_SADDW, "saddw" },
3289 { ARM64_INS_SBC, "sbc" },
3290 { ARM64_INS_SBFIZ, "sbfiz" },
3291 { ARM64_INS_SBFM, "sbfm" },
3292 { ARM64_INS_SBFX, "sbfx" },
3293 { ARM64_INS_SCVTF, "scvtf" },
3294 { ARM64_INS_SDIV, "sdiv" },
3295 { ARM64_INS_SHA1C, "sha1c" },
3296 { ARM64_INS_SHA1H, "sha1h" },
3297 { ARM64_INS_SHA1M, "sha1m" },
3298 { ARM64_INS_SHA1P, "sha1p" },
3299 { ARM64_INS_SHA1SU0, "sha1su0" },
3300 { ARM64_INS_SHA1SU1, "sha1su1" },
3301 { ARM64_INS_SHA256H, "sha256h" },
3302 { ARM64_INS_SHA256H2, "sha256h2" },
3303 { ARM64_INS_SHA256SU0, "sha256su0" },
3304 { ARM64_INS_SHA256SU1, "sha256su1" },
3305 { ARM64_INS_SHADD, "shadd" },
3306 { ARM64_INS_SHLL2, "shll2" },
3307 { ARM64_INS_SHLL, "shll" },
3308 { ARM64_INS_SHL, "shl" },
3309 { ARM64_INS_SHRN2, "shrn2" },
3310 { ARM64_INS_SHRN, "shrn" },
3311 { ARM64_INS_SHSUB, "shsub" },
3312 { ARM64_INS_SLI, "sli" },
3313 { ARM64_INS_SMADDL, "smaddl" },
3314 { ARM64_INS_SMAXP, "smaxp" },
3315 { ARM64_INS_SMAXV, "smaxv" },
3316 { ARM64_INS_SMAX, "smax" },
3317 { ARM64_INS_SMC, "smc" },
3318 { ARM64_INS_SMINP, "sminp" },
3319 { ARM64_INS_SMINV, "sminv" },
3320 { ARM64_INS_SMIN, "smin" },
3321 { ARM64_INS_SMLAL2, "smlal2" },
3322 { ARM64_INS_SMLAL, "smlal" },
3323 { ARM64_INS_SMLSL2, "smlsl2" },
3324 { ARM64_INS_SMLSL, "smlsl" },
3325 { ARM64_INS_SMOV, "smov" },
3326 { ARM64_INS_SMSUBL, "smsubl" },
3327 { ARM64_INS_SMULH, "smulh" },
3328 { ARM64_INS_SMULL2, "smull2" },
3329 { ARM64_INS_SMULL, "smull" },
3330 { ARM64_INS_SQABS, "sqabs" },
3331 { ARM64_INS_SQADD, "sqadd" },
3332 { ARM64_INS_SQDMLAL2, "sqdmlal2" },
3333 { ARM64_INS_SQDMLAL, "sqdmlal" },
3334 { ARM64_INS_SQDMLSL2, "sqdmlsl2" },
3335 { ARM64_INS_SQDMLSL, "sqdmlsl" },
3336 { ARM64_INS_SQDMULH, "sqdmulh" },
3337 { ARM64_INS_SQDMULL2, "sqdmull2" },
3338 { ARM64_INS_SQDMULL, "sqdmull" },
3339 { ARM64_INS_SQNEG, "sqneg" },
3340 { ARM64_INS_SQRDMULH, "sqrdmulh" },
3341 { ARM64_INS_SQRSHL, "sqrshl" },
3342 { ARM64_INS_SQRSHRN, "sqrshrn" },
3343 { ARM64_INS_SQRSHRN2, "sqrshrn2" },
3344 { ARM64_INS_SQSHLU, "sqshlu" },
3345 { ARM64_INS_SQSHL, "sqshl" },
3346 { ARM64_INS_SQSHRN, "sqshrn" },
3347 { ARM64_INS_SQSHRN2, "sqshrn2" },
3348 { ARM64_INS_SQSUB, "sqsub" },
3349 { ARM64_INS_SQXTN, "sqxtn" },
3350 { ARM64_INS_SQXTN2, "sqxtn2" },
3351 { ARM64_INS_SQXTUN, "sqxtun" },
3352 { ARM64_INS_SQXTUN2, "sqxtun2" },
3353 { ARM64_INS_SRHADD, "srhadd" },
3354 { ARM64_INS_SRI, "sri" },
3355 { ARM64_INS_SRSHL, "srshl" },
3356 { ARM64_INS_SRSHR, "srshr" },
3357 { ARM64_INS_SRSRA, "srsra" },
3358 { ARM64_INS_SSHLL2, "sshll2" },
3359 { ARM64_INS_SSHLL, "sshll" },
3360 { ARM64_INS_SSHL, "sshl" },
3361 { ARM64_INS_SSHR, "sshr" },
3362 { ARM64_INS_SSRA, "ssra" },
3363 { ARM64_INS_SSUBL2, "ssubl2" },
3364 { ARM64_INS_SSUBL, "ssubl" },
3365 { ARM64_INS_SSUBW2, "ssubw2" },
3366 { ARM64_INS_SSUBW, "ssubw" },
3367 { ARM64_INS_ST1, "st1" },
3368 { ARM64_INS_ST2, "st2" },
3369 { ARM64_INS_ST3, "st3" },
3370 { ARM64_INS_ST4, "st4" },
3371 { ARM64_INS_STLRB, "stlrb" },
3372 { ARM64_INS_STLR, "stlr" },
3373 { ARM64_INS_STLRH, "stlrh" },
3374 { ARM64_INS_STLXP, "stlxp" },
3375 { ARM64_INS_STLXRB, "stlxrb" },
3376 { ARM64_INS_STLXR, "stlxr" },
3377 { ARM64_INS_STLXRH, "stlxrh" },
3378 { ARM64_INS_STXP, "stxp" },
3379 { ARM64_INS_STXRB, "stxrb" },
3380 { ARM64_INS_STXR, "stxr" },
3381 { ARM64_INS_STXRH, "stxrh" },
3382 { ARM64_INS_SUBHN2, "subhn2" },
3383 { ARM64_INS_SUBHN, "subhn" },
3384 { ARM64_INS_SUB, "sub" },
3385 { ARM64_INS_SUQADD, "suqadd" },
3386 { ARM64_INS_SVC, "svc" },
3387 { ARM64_INS_SXTB, "sxtb" },
3388 { ARM64_INS_SXTH, "sxth" },
3389 { ARM64_INS_SXTW, "sxtw" },
3390 { ARM64_INS_SYSL, "sysl" },
3391 { ARM64_INS_SYS, "sys" },
3392 { ARM64_INS_TBL, "tbl" },
3393 { ARM64_INS_TBNZ, "tbnz" },
3394 { ARM64_INS_TBX, "tbx" },
3395 { ARM64_INS_TBZ, "tbz" },
3396 { ARM64_INS_TLBI, "tlbi" },
3397 { ARM64_INS_TRN1, "trn1" },
3398 { ARM64_INS_TRN2, "trn2" },
3399 { ARM64_INS_TST, "tst" },
3400 { ARM64_INS_UABAL2, "uabal2" },
3401 { ARM64_INS_UABAL, "uabal" },
3402 { ARM64_INS_UABA, "uaba" },
3403 { ARM64_INS_UABDL2, "uabdl2" },
3404 { ARM64_INS_UABDL, "uabdl" },
3405 { ARM64_INS_UABD, "uabd" },
3406 { ARM64_INS_UADALP, "uadalp" },
3407 { ARM64_INS_UADDL2, "uaddl2" },
3408 { ARM64_INS_UADDLP, "uaddlp" },
3409 { ARM64_INS_UADDLV, "uaddlv" },
3410 { ARM64_INS_UADDL, "uaddl" },
3411 { ARM64_INS_UADDW2, "uaddw2" },
3412 { ARM64_INS_UADDW, "uaddw" },
3413 { ARM64_INS_UBFIZ, "ubfiz" },
3414 { ARM64_INS_UBFM, "ubfm" },
3415 { ARM64_INS_UBFX, "ubfx" },
3416 { ARM64_INS_UCVTF, "ucvtf" },
3417 { ARM64_INS_UDIV, "udiv" },
3418 { ARM64_INS_UHADD, "uhadd" },
3419 { ARM64_INS_UHSUB, "uhsub" },
3420 { ARM64_INS_UMADDL, "umaddl" },
3421 { ARM64_INS_UMAXP, "umaxp" },
3422 { ARM64_INS_UMAXV, "umaxv" },
3423 { ARM64_INS_UMAX, "umax" },
3424 { ARM64_INS_UMINP, "uminp" },
3425 { ARM64_INS_UMINV, "uminv" },
3426 { ARM64_INS_UMIN, "umin" },
3427 { ARM64_INS_UMLAL2, "umlal2" },
3428 { ARM64_INS_UMLAL, "umlal" },
3429 { ARM64_INS_UMLSL2, "umlsl2" },
3430 { ARM64_INS_UMLSL, "umlsl" },
3431 { ARM64_INS_UMOV, "umov" },
3432 { ARM64_INS_UMSUBL, "umsubl" },
3433 { ARM64_INS_UMULH, "umulh" },
3434 { ARM64_INS_UMULL2, "umull2" },
3435 { ARM64_INS_UMULL, "umull" },
3436 { ARM64_INS_UQADD, "uqadd" },
3437 { ARM64_INS_UQRSHL, "uqrshl" },
3438 { ARM64_INS_UQRSHRN, "uqrshrn" },
3439 { ARM64_INS_UQRSHRN2, "uqrshrn2" },
3440 { ARM64_INS_UQSHL, "uqshl" },
3441 { ARM64_INS_UQSHRN, "uqshrn" },
3442 { ARM64_INS_UQSHRN2, "uqshrn2" },
3443 { ARM64_INS_UQSUB, "uqsub" },
3444 { ARM64_INS_UQXTN, "uqxtn" },
3445 { ARM64_INS_UQXTN2, "uqxtn2" },
3446 { ARM64_INS_URECPE, "urecpe" },
3447 { ARM64_INS_URHADD, "urhadd" },
3448 { ARM64_INS_URSHL, "urshl" },
3449 { ARM64_INS_URSHR, "urshr" },
3450 { ARM64_INS_URSQRTE, "ursqrte" },
3451 { ARM64_INS_URSRA, "ursra" },
3452 { ARM64_INS_USHLL2, "ushll2" },
3453 { ARM64_INS_USHLL, "ushll" },
3454 { ARM64_INS_USHL, "ushl" },
3455 { ARM64_INS_USHR, "ushr" },
3456 { ARM64_INS_USQADD, "usqadd" },
3457 { ARM64_INS_USRA, "usra" },
3458 { ARM64_INS_USUBL2, "usubl2" },
3459 { ARM64_INS_USUBL, "usubl" },
3460 { ARM64_INS_USUBW2, "usubw2" },
3461 { ARM64_INS_USUBW, "usubw" },
3462 { ARM64_INS_UXTB, "uxtb" },
3463 { ARM64_INS_UXTH, "uxth" },
3464 { ARM64_INS_UZP1, "uzp1" },
3465 { ARM64_INS_UZP2, "uzp2" },
3466 { ARM64_INS_XTN, "xtn" },
3467 { ARM64_INS_XTN2, "xtn2" },
3468 { ARM64_INS_ZIP1, "zip1" },
3469 { ARM64_INS_ZIP2, "zip2" },
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3470};
3471
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]3472// map *S & alias instructions back to original id
3473static name_map alias_insn_name_maps[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]3474 { ARM64_INS_ADC, "adcs" },
3475 { ARM64_INS_AND, "ands" },
3476 { ARM64_INS_ADD, "adds" },
3477 { ARM64_INS_BIC, "bics" },
3478 { ARM64_INS_SBC, "sbcs" },
3479 { ARM64_INS_SUB, "subs" },
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]3480
3481 // alias insn
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]3482 { ARM64_INS_MNEG, "mneg" },
3483 { ARM64_INS_UMNEGL, "umnegl" },
3484 { ARM64_INS_SMNEGL, "smnegl" },
3485 { ARM64_INS_MOV, "mov" },
3486 { ARM64_INS_NOP, "nop" },
3487 { ARM64_INS_YIELD, "yield" },
3488 { ARM64_INS_WFE, "wfe" },
3489 { ARM64_INS_WFI, "wfi" },
3490 { ARM64_INS_SEV, "sev" },
3491 { ARM64_INS_SEVL, "sevl" },
3492 { ARM64_INS_NGC, "ngc" },
3493 { ARM64_INS_NGCS, "ngcs" },
3494 { ARM64_INS_NEGS, "negs" },
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]3495};
3496
pancakef0e4eed2013-12-11 22:14:42 +0100[diff] [blame]3497const char *AArch64_insn_name(csh handle, unsigned int id)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3498{
3499 if (id >= ARM64_INS_MAX)
3500 return NULL;
3501
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]3502 // try with alias insn first
3503 int i;
3504 for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) {
3505 if (alias_insn_name_maps[i].id == id)
3506 return alias_insn_name_maps[i].name;
3507 }
3508
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3509 return insn_name_maps[id].name;
3510}
3511
Nguyen Anh Quynh6b7abe32013-11-30 00:54:24 +0800[diff] [blame]3512// map instruction name to public instruction ID
pancakef0e4eed2013-12-11 22:14:42 +0100[diff] [blame]3513arm64_reg AArch64_map_insn(const char *name)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3514{
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3515 // NOTE: skip first NULL name in insn_name_maps
3516 int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
3517
3518 if (i == -1)
3519 // try again with 'special' insn that is not available in insn_name_maps
Nguyen Anh Quynhad61c492013-11-30 16:23:31 +0800[diff] [blame]3520 i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name);
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]3521
3522 return (i != -1)? i : ARM64_REG_INVALID;
3523}
3524