Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 1 | /* Capstone Disassembly Engine */ |
| 2 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ |
| 3 | |
| 4 | #ifdef CAPSTONE_HAS_ARM64 |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 5 | |
| 6 | #include <stdio.h> // debug |
| 7 | #include <string.h> |
| 8 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 9 | #include "../../utils.h" |
| 10 | |
Nguyen Anh Quynh | 3732725 | 2014-01-20 09:47:21 +0800 | [diff] [blame] | 11 | #include "AArch64Mapping.h" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 12 | |
| 13 | #define GET_INSTRINFO_ENUM |
| 14 | #include "AArch64GenInstrInfo.inc" |
| 15 | |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 16 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 17 | static name_map reg_name_maps[] = { |
| 18 | { ARM64_REG_INVALID, NULL }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 19 | //========= |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 20 | { ARM64_REG_NZCV, "nzcv"}, |
| 21 | { ARM64_REG_WSP, "wsp"}, |
Nguyen Anh Quynh | 1922b2f | 2014-05-18 10:30:09 +0800 | [diff] [blame] | 22 | { ARM64_REG_WZR, "wzr"}, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 23 | { ARM64_REG_SP, "sp"}, |
Nguyen Anh Quynh | 1922b2f | 2014-05-18 10:30:09 +0800 | [diff] [blame] | 24 | { ARM64_REG_XZR, "xzr"}, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 25 | { ARM64_REG_B0, "b0"}, |
| 26 | { ARM64_REG_B1, "b1"}, |
| 27 | { ARM64_REG_B2, "b2"}, |
| 28 | { ARM64_REG_B3, "b3"}, |
| 29 | { ARM64_REG_B4, "b4"}, |
| 30 | { ARM64_REG_B5, "b5"}, |
| 31 | { ARM64_REG_B6, "b6"}, |
| 32 | { ARM64_REG_B7, "b7"}, |
| 33 | { ARM64_REG_B8, "b8"}, |
| 34 | { ARM64_REG_B9, "b9"}, |
| 35 | { ARM64_REG_B10, "b10"}, |
| 36 | { ARM64_REG_B11, "b11"}, |
| 37 | { ARM64_REG_B12, "b12"}, |
| 38 | { ARM64_REG_B13, "b13"}, |
| 39 | { ARM64_REG_B14, "b14"}, |
| 40 | { ARM64_REG_B15, "b15"}, |
| 41 | { ARM64_REG_B16, "b16"}, |
| 42 | { ARM64_REG_B17, "b17"}, |
| 43 | { ARM64_REG_B18, "b18"}, |
| 44 | { ARM64_REG_B19, "b19"}, |
| 45 | { ARM64_REG_B20, "b20"}, |
| 46 | { ARM64_REG_B21, "b21"}, |
| 47 | { ARM64_REG_B22, "b22"}, |
| 48 | { ARM64_REG_B23, "b23"}, |
| 49 | { ARM64_REG_B24, "b24"}, |
| 50 | { ARM64_REG_B25, "b25"}, |
| 51 | { ARM64_REG_B26, "b26"}, |
| 52 | { ARM64_REG_B27, "b27"}, |
| 53 | { ARM64_REG_B28, "b28"}, |
| 54 | { ARM64_REG_B29, "b29"}, |
| 55 | { ARM64_REG_B30, "b30"}, |
| 56 | { ARM64_REG_B31, "b31"}, |
| 57 | { ARM64_REG_D0, "d0"}, |
| 58 | { ARM64_REG_D1, "d1"}, |
| 59 | { ARM64_REG_D2, "d2"}, |
| 60 | { ARM64_REG_D3, "d3"}, |
| 61 | { ARM64_REG_D4, "d4"}, |
| 62 | { ARM64_REG_D5, "d5"}, |
| 63 | { ARM64_REG_D6, "d6"}, |
| 64 | { ARM64_REG_D7, "d7"}, |
| 65 | { ARM64_REG_D8, "d8"}, |
| 66 | { ARM64_REG_D9, "d9"}, |
| 67 | { ARM64_REG_D10, "d10"}, |
| 68 | { ARM64_REG_D11, "d11"}, |
| 69 | { ARM64_REG_D12, "d12"}, |
| 70 | { ARM64_REG_D13, "d13"}, |
| 71 | { ARM64_REG_D14, "d14"}, |
| 72 | { ARM64_REG_D15, "d15"}, |
| 73 | { ARM64_REG_D16, "d16"}, |
| 74 | { ARM64_REG_D17, "d17"}, |
| 75 | { ARM64_REG_D18, "d18"}, |
| 76 | { ARM64_REG_D19, "d19"}, |
| 77 | { ARM64_REG_D20, "d20"}, |
| 78 | { ARM64_REG_D21, "d21"}, |
| 79 | { ARM64_REG_D22, "d22"}, |
| 80 | { ARM64_REG_D23, "d23"}, |
| 81 | { ARM64_REG_D24, "d24"}, |
| 82 | { ARM64_REG_D25, "d25"}, |
| 83 | { ARM64_REG_D26, "d26"}, |
| 84 | { ARM64_REG_D27, "d27"}, |
| 85 | { ARM64_REG_D28, "d28"}, |
| 86 | { ARM64_REG_D29, "d29"}, |
| 87 | { ARM64_REG_D30, "d30"}, |
| 88 | { ARM64_REG_D31, "d31"}, |
| 89 | { ARM64_REG_H0, "h0"}, |
| 90 | { ARM64_REG_H1, "h1"}, |
| 91 | { ARM64_REG_H2, "h2"}, |
| 92 | { ARM64_REG_H3, "h3"}, |
| 93 | { ARM64_REG_H4, "h4"}, |
| 94 | { ARM64_REG_H5, "h5"}, |
| 95 | { ARM64_REG_H6, "h6"}, |
| 96 | { ARM64_REG_H7, "h7"}, |
| 97 | { ARM64_REG_H8, "h8"}, |
| 98 | { ARM64_REG_H9, "h9"}, |
| 99 | { ARM64_REG_H10, "h10"}, |
| 100 | { ARM64_REG_H11, "h11"}, |
| 101 | { ARM64_REG_H12, "h12"}, |
| 102 | { ARM64_REG_H13, "h13"}, |
| 103 | { ARM64_REG_H14, "h14"}, |
| 104 | { ARM64_REG_H15, "h15"}, |
| 105 | { ARM64_REG_H16, "h16"}, |
| 106 | { ARM64_REG_H17, "h17"}, |
| 107 | { ARM64_REG_H18, "h18"}, |
| 108 | { ARM64_REG_H19, "h19"}, |
| 109 | { ARM64_REG_H20, "h20"}, |
| 110 | { ARM64_REG_H21, "h21"}, |
| 111 | { ARM64_REG_H22, "h22"}, |
| 112 | { ARM64_REG_H23, "h23"}, |
| 113 | { ARM64_REG_H24, "h24"}, |
| 114 | { ARM64_REG_H25, "h25"}, |
| 115 | { ARM64_REG_H26, "h26"}, |
| 116 | { ARM64_REG_H27, "h27"}, |
| 117 | { ARM64_REG_H28, "h28"}, |
| 118 | { ARM64_REG_H29, "h29"}, |
| 119 | { ARM64_REG_H30, "h30"}, |
| 120 | { ARM64_REG_H31, "h31"}, |
| 121 | { ARM64_REG_Q0, "q0"}, |
| 122 | { ARM64_REG_Q1, "q1"}, |
| 123 | { ARM64_REG_Q2, "q2"}, |
| 124 | { ARM64_REG_Q3, "q3"}, |
| 125 | { ARM64_REG_Q4, "q4"}, |
| 126 | { ARM64_REG_Q5, "q5"}, |
| 127 | { ARM64_REG_Q6, "q6"}, |
| 128 | { ARM64_REG_Q7, "q7"}, |
| 129 | { ARM64_REG_Q8, "q8"}, |
| 130 | { ARM64_REG_Q9, "q9"}, |
| 131 | { ARM64_REG_Q10, "q10"}, |
| 132 | { ARM64_REG_Q11, "q11"}, |
| 133 | { ARM64_REG_Q12, "q12"}, |
| 134 | { ARM64_REG_Q13, "q13"}, |
| 135 | { ARM64_REG_Q14, "q14"}, |
| 136 | { ARM64_REG_Q15, "q15"}, |
| 137 | { ARM64_REG_Q16, "q16"}, |
| 138 | { ARM64_REG_Q17, "q17"}, |
| 139 | { ARM64_REG_Q18, "q18"}, |
| 140 | { ARM64_REG_Q19, "q19"}, |
| 141 | { ARM64_REG_Q20, "q20"}, |
| 142 | { ARM64_REG_Q21, "q21"}, |
| 143 | { ARM64_REG_Q22, "q22"}, |
| 144 | { ARM64_REG_Q23, "q23"}, |
| 145 | { ARM64_REG_Q24, "q24"}, |
| 146 | { ARM64_REG_Q25, "q25"}, |
| 147 | { ARM64_REG_Q26, "q26"}, |
| 148 | { ARM64_REG_Q27, "q27"}, |
| 149 | { ARM64_REG_Q28, "q28"}, |
| 150 | { ARM64_REG_Q29, "q29"}, |
| 151 | { ARM64_REG_Q30, "q30"}, |
| 152 | { ARM64_REG_Q31, "q31"}, |
| 153 | { ARM64_REG_S0, "s0"}, |
| 154 | { ARM64_REG_S1, "s1"}, |
| 155 | { ARM64_REG_S2, "s2"}, |
| 156 | { ARM64_REG_S3, "s3"}, |
| 157 | { ARM64_REG_S4, "s4"}, |
| 158 | { ARM64_REG_S5, "s5"}, |
| 159 | { ARM64_REG_S6, "s6"}, |
| 160 | { ARM64_REG_S7, "s7"}, |
| 161 | { ARM64_REG_S8, "s8"}, |
| 162 | { ARM64_REG_S9, "s9"}, |
| 163 | { ARM64_REG_S10, "s10"}, |
| 164 | { ARM64_REG_S11, "s11"}, |
| 165 | { ARM64_REG_S12, "s12"}, |
| 166 | { ARM64_REG_S13, "s13"}, |
| 167 | { ARM64_REG_S14, "s14"}, |
| 168 | { ARM64_REG_S15, "s15"}, |
| 169 | { ARM64_REG_S16, "s16"}, |
| 170 | { ARM64_REG_S17, "s17"}, |
| 171 | { ARM64_REG_S18, "s18"}, |
| 172 | { ARM64_REG_S19, "s19"}, |
| 173 | { ARM64_REG_S20, "s20"}, |
| 174 | { ARM64_REG_S21, "s21"}, |
| 175 | { ARM64_REG_S22, "s22"}, |
| 176 | { ARM64_REG_S23, "s23"}, |
| 177 | { ARM64_REG_S24, "s24"}, |
| 178 | { ARM64_REG_S25, "s25"}, |
| 179 | { ARM64_REG_S26, "s26"}, |
| 180 | { ARM64_REG_S27, "s27"}, |
| 181 | { ARM64_REG_S28, "s28"}, |
| 182 | { ARM64_REG_S29, "s29"}, |
| 183 | { ARM64_REG_S30, "s30"}, |
| 184 | { ARM64_REG_S31, "s31"}, |
| 185 | { ARM64_REG_W0, "w0"}, |
| 186 | { ARM64_REG_W1, "w1"}, |
| 187 | { ARM64_REG_W2, "w2"}, |
| 188 | { ARM64_REG_W3, "w3"}, |
| 189 | { ARM64_REG_W4, "w4"}, |
| 190 | { ARM64_REG_W5, "w5"}, |
| 191 | { ARM64_REG_W6, "w6"}, |
| 192 | { ARM64_REG_W7, "w7"}, |
| 193 | { ARM64_REG_W8, "w8"}, |
| 194 | { ARM64_REG_W9, "w9"}, |
| 195 | { ARM64_REG_W10, "w10"}, |
| 196 | { ARM64_REG_W11, "w11"}, |
| 197 | { ARM64_REG_W12, "w12"}, |
| 198 | { ARM64_REG_W13, "w13"}, |
| 199 | { ARM64_REG_W14, "w14"}, |
| 200 | { ARM64_REG_W15, "w15"}, |
| 201 | { ARM64_REG_W16, "w16"}, |
| 202 | { ARM64_REG_W17, "w17"}, |
| 203 | { ARM64_REG_W18, "w18"}, |
| 204 | { ARM64_REG_W19, "w19"}, |
| 205 | { ARM64_REG_W20, "w20"}, |
| 206 | { ARM64_REG_W21, "w21"}, |
| 207 | { ARM64_REG_W22, "w22"}, |
| 208 | { ARM64_REG_W23, "w23"}, |
| 209 | { ARM64_REG_W24, "w24"}, |
| 210 | { ARM64_REG_W25, "w25"}, |
| 211 | { ARM64_REG_W26, "w26"}, |
| 212 | { ARM64_REG_W27, "w27"}, |
| 213 | { ARM64_REG_W28, "w28"}, |
| 214 | { ARM64_REG_W29, "w29"}, |
| 215 | { ARM64_REG_W30, "w30"}, |
| 216 | { ARM64_REG_X0, "x0"}, |
| 217 | { ARM64_REG_X1, "x1"}, |
| 218 | { ARM64_REG_X2, "x2"}, |
| 219 | { ARM64_REG_X3, "x3"}, |
| 220 | { ARM64_REG_X4, "x4"}, |
| 221 | { ARM64_REG_X5, "x5"}, |
| 222 | { ARM64_REG_X6, "x6"}, |
| 223 | { ARM64_REG_X7, "x7"}, |
| 224 | { ARM64_REG_X8, "x8"}, |
| 225 | { ARM64_REG_X9, "x9"}, |
| 226 | { ARM64_REG_X10, "x10"}, |
| 227 | { ARM64_REG_X11, "x11"}, |
| 228 | { ARM64_REG_X12, "x12"}, |
| 229 | { ARM64_REG_X13, "x13"}, |
| 230 | { ARM64_REG_X14, "x14"}, |
| 231 | { ARM64_REG_X15, "x15"}, |
| 232 | { ARM64_REG_X16, "x16"}, |
| 233 | { ARM64_REG_X17, "x17"}, |
| 234 | { ARM64_REG_X18, "x18"}, |
| 235 | { ARM64_REG_X19, "x19"}, |
| 236 | { ARM64_REG_X20, "x20"}, |
| 237 | { ARM64_REG_X21, "x21"}, |
| 238 | { ARM64_REG_X22, "x22"}, |
| 239 | { ARM64_REG_X23, "x23"}, |
| 240 | { ARM64_REG_X24, "x24"}, |
| 241 | { ARM64_REG_X25, "x25"}, |
| 242 | { ARM64_REG_X26, "x26"}, |
| 243 | { ARM64_REG_X27, "x27"}, |
| 244 | { ARM64_REG_X28, "x28"}, |
| 245 | { ARM64_REG_X29, "x29"}, |
| 246 | { ARM64_REG_X30, "x30"}, |
| 247 | }; |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 248 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 249 | |
pancake | f0e4eed | 2013-12-11 22:14:42 +0100 | [diff] [blame] | 250 | const char *AArch64_reg_name(csh handle, unsigned int reg) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 251 | { |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 252 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 253 | if (reg >= ARM64_REG_MAX) |
| 254 | return NULL; |
| 255 | |
| 256 | return reg_name_maps[reg].name; |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 257 | #else |
| 258 | return NULL; |
| 259 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | static insn_map insns[] = { |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 263 | // dummy item |
| 264 | { |
| 265 | 0, 0, |
| 266 | #ifndef CAPSTONE_DIET |
| 267 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 268 | #endif |
| 269 | }, |
Nguyen Anh Quynh | b265406 | 2014-01-03 17:08:58 +0800 | [diff] [blame] | 270 | |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 271 | { |
| 272 | AArch64_ABS16b, ARM64_INS_ABS, |
| 273 | #ifndef CAPSTONE_DIET |
| 274 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 275 | #endif |
| 276 | }, |
| 277 | { |
| 278 | AArch64_ABS2d, ARM64_INS_ABS, |
| 279 | #ifndef CAPSTONE_DIET |
| 280 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 281 | #endif |
| 282 | }, |
| 283 | { |
| 284 | AArch64_ABS2s, ARM64_INS_ABS, |
| 285 | #ifndef CAPSTONE_DIET |
| 286 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 287 | #endif |
| 288 | }, |
| 289 | { |
| 290 | AArch64_ABS4h, ARM64_INS_ABS, |
| 291 | #ifndef CAPSTONE_DIET |
| 292 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 293 | #endif |
| 294 | }, |
| 295 | { |
| 296 | AArch64_ABS4s, ARM64_INS_ABS, |
| 297 | #ifndef CAPSTONE_DIET |
| 298 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 299 | #endif |
| 300 | }, |
| 301 | { |
| 302 | AArch64_ABS8b, ARM64_INS_ABS, |
| 303 | #ifndef CAPSTONE_DIET |
| 304 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 305 | #endif |
| 306 | }, |
| 307 | { |
| 308 | AArch64_ABS8h, ARM64_INS_ABS, |
| 309 | #ifndef CAPSTONE_DIET |
| 310 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 311 | #endif |
| 312 | }, |
| 313 | { |
| 314 | AArch64_ABSdd, ARM64_INS_ABS, |
| 315 | #ifndef CAPSTONE_DIET |
| 316 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 317 | #endif |
| 318 | }, |
| 319 | { |
| 320 | AArch64_ADCSwww, ARM64_INS_ADC, |
| 321 | #ifndef CAPSTONE_DIET |
| 322 | { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 323 | #endif |
| 324 | }, |
| 325 | { |
| 326 | AArch64_ADCSxxx, ARM64_INS_ADC, |
| 327 | #ifndef CAPSTONE_DIET |
| 328 | { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 329 | #endif |
| 330 | }, |
| 331 | { |
| 332 | AArch64_ADCwww, ARM64_INS_ADC, |
| 333 | #ifndef CAPSTONE_DIET |
| 334 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 335 | #endif |
| 336 | }, |
| 337 | { |
| 338 | AArch64_ADCxxx, ARM64_INS_ADC, |
| 339 | #ifndef CAPSTONE_DIET |
| 340 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 341 | #endif |
| 342 | }, |
| 343 | { |
| 344 | AArch64_ADDHN2vvv_16b8h, ARM64_INS_ADDHN2, |
| 345 | #ifndef CAPSTONE_DIET |
| 346 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 347 | #endif |
| 348 | }, |
| 349 | { |
| 350 | AArch64_ADDHN2vvv_4s2d, ARM64_INS_ADDHN2, |
| 351 | #ifndef CAPSTONE_DIET |
| 352 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 353 | #endif |
| 354 | }, |
| 355 | { |
| 356 | AArch64_ADDHN2vvv_8h4s, ARM64_INS_ADDHN2, |
| 357 | #ifndef CAPSTONE_DIET |
| 358 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 359 | #endif |
| 360 | }, |
| 361 | { |
| 362 | AArch64_ADDHNvvv_2s2d, ARM64_INS_ADDHN, |
| 363 | #ifndef CAPSTONE_DIET |
| 364 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 365 | #endif |
| 366 | }, |
| 367 | { |
| 368 | AArch64_ADDHNvvv_4h4s, ARM64_INS_ADDHN, |
| 369 | #ifndef CAPSTONE_DIET |
| 370 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 371 | #endif |
| 372 | }, |
| 373 | { |
| 374 | AArch64_ADDHNvvv_8b8h, ARM64_INS_ADDHN, |
| 375 | #ifndef CAPSTONE_DIET |
| 376 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 377 | #endif |
| 378 | }, |
| 379 | { |
| 380 | AArch64_ADDP_16B, ARM64_INS_ADDP, |
| 381 | #ifndef CAPSTONE_DIET |
| 382 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 383 | #endif |
| 384 | }, |
| 385 | { |
| 386 | AArch64_ADDP_2D, ARM64_INS_ADDP, |
| 387 | #ifndef CAPSTONE_DIET |
| 388 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 389 | #endif |
| 390 | }, |
| 391 | { |
| 392 | AArch64_ADDP_2S, ARM64_INS_ADDP, |
| 393 | #ifndef CAPSTONE_DIET |
| 394 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 395 | #endif |
| 396 | }, |
| 397 | { |
| 398 | AArch64_ADDP_4H, ARM64_INS_ADDP, |
| 399 | #ifndef CAPSTONE_DIET |
| 400 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 401 | #endif |
| 402 | }, |
| 403 | { |
| 404 | AArch64_ADDP_4S, ARM64_INS_ADDP, |
| 405 | #ifndef CAPSTONE_DIET |
| 406 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 407 | #endif |
| 408 | }, |
| 409 | { |
| 410 | AArch64_ADDP_8B, ARM64_INS_ADDP, |
| 411 | #ifndef CAPSTONE_DIET |
| 412 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 413 | #endif |
| 414 | }, |
| 415 | { |
| 416 | AArch64_ADDP_8H, ARM64_INS_ADDP, |
| 417 | #ifndef CAPSTONE_DIET |
| 418 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 419 | #endif |
| 420 | }, |
| 421 | { |
| 422 | AArch64_ADDPvv_D_2D, ARM64_INS_ADDP, |
| 423 | #ifndef CAPSTONE_DIET |
| 424 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 425 | #endif |
| 426 | }, |
| 427 | { |
| 428 | AArch64_ADDSwww_asr, ARM64_INS_ADD, |
| 429 | #ifndef CAPSTONE_DIET |
| 430 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 431 | #endif |
| 432 | }, |
| 433 | { |
| 434 | AArch64_ADDSwww_lsl, ARM64_INS_ADD, |
| 435 | #ifndef CAPSTONE_DIET |
| 436 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 437 | #endif |
| 438 | }, |
| 439 | { |
| 440 | AArch64_ADDSwww_lsr, ARM64_INS_ADD, |
| 441 | #ifndef CAPSTONE_DIET |
| 442 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 443 | #endif |
| 444 | }, |
| 445 | { |
| 446 | AArch64_ADDSwww_sxtb, ARM64_INS_ADD, |
| 447 | #ifndef CAPSTONE_DIET |
| 448 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 449 | #endif |
| 450 | }, |
| 451 | { |
| 452 | AArch64_ADDSwww_sxth, ARM64_INS_ADD, |
| 453 | #ifndef CAPSTONE_DIET |
| 454 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 455 | #endif |
| 456 | }, |
| 457 | { |
| 458 | AArch64_ADDSwww_sxtw, ARM64_INS_ADD, |
| 459 | #ifndef CAPSTONE_DIET |
| 460 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 461 | #endif |
| 462 | }, |
| 463 | { |
| 464 | AArch64_ADDSwww_sxtx, ARM64_INS_ADD, |
| 465 | #ifndef CAPSTONE_DIET |
| 466 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 467 | #endif |
| 468 | }, |
| 469 | { |
| 470 | AArch64_ADDSwww_uxtb, ARM64_INS_ADD, |
| 471 | #ifndef CAPSTONE_DIET |
| 472 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 473 | #endif |
| 474 | }, |
| 475 | { |
| 476 | AArch64_ADDSwww_uxth, ARM64_INS_ADD, |
| 477 | #ifndef CAPSTONE_DIET |
| 478 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 479 | #endif |
| 480 | }, |
| 481 | { |
| 482 | AArch64_ADDSwww_uxtw, ARM64_INS_ADD, |
| 483 | #ifndef CAPSTONE_DIET |
| 484 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 485 | #endif |
| 486 | }, |
| 487 | { |
| 488 | AArch64_ADDSwww_uxtx, ARM64_INS_ADD, |
| 489 | #ifndef CAPSTONE_DIET |
| 490 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 491 | #endif |
| 492 | }, |
| 493 | { |
| 494 | AArch64_ADDSxxw_sxtb, ARM64_INS_ADD, |
| 495 | #ifndef CAPSTONE_DIET |
| 496 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 497 | #endif |
| 498 | }, |
| 499 | { |
| 500 | AArch64_ADDSxxw_sxth, ARM64_INS_ADD, |
| 501 | #ifndef CAPSTONE_DIET |
| 502 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 503 | #endif |
| 504 | }, |
| 505 | { |
| 506 | AArch64_ADDSxxw_sxtw, ARM64_INS_ADD, |
| 507 | #ifndef CAPSTONE_DIET |
| 508 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 509 | #endif |
| 510 | }, |
| 511 | { |
| 512 | AArch64_ADDSxxw_uxtb, ARM64_INS_ADD, |
| 513 | #ifndef CAPSTONE_DIET |
| 514 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 515 | #endif |
| 516 | }, |
| 517 | { |
| 518 | AArch64_ADDSxxw_uxth, ARM64_INS_ADD, |
| 519 | #ifndef CAPSTONE_DIET |
| 520 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 521 | #endif |
| 522 | }, |
| 523 | { |
| 524 | AArch64_ADDSxxw_uxtw, ARM64_INS_ADD, |
| 525 | #ifndef CAPSTONE_DIET |
| 526 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 527 | #endif |
| 528 | }, |
| 529 | { |
| 530 | AArch64_ADDSxxx_asr, ARM64_INS_ADD, |
| 531 | #ifndef CAPSTONE_DIET |
| 532 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 533 | #endif |
| 534 | }, |
| 535 | { |
| 536 | AArch64_ADDSxxx_lsl, ARM64_INS_ADD, |
| 537 | #ifndef CAPSTONE_DIET |
| 538 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 539 | #endif |
| 540 | }, |
| 541 | { |
| 542 | AArch64_ADDSxxx_lsr, ARM64_INS_ADD, |
| 543 | #ifndef CAPSTONE_DIET |
| 544 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 545 | #endif |
| 546 | }, |
| 547 | { |
| 548 | AArch64_ADDSxxx_sxtx, ARM64_INS_ADD, |
| 549 | #ifndef CAPSTONE_DIET |
| 550 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 551 | #endif |
| 552 | }, |
| 553 | { |
| 554 | AArch64_ADDSxxx_uxtx, ARM64_INS_ADD, |
| 555 | #ifndef CAPSTONE_DIET |
| 556 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 557 | #endif |
| 558 | }, |
| 559 | { |
| 560 | AArch64_ADDV_1b16b, ARM64_INS_ADDV, |
| 561 | #ifndef CAPSTONE_DIET |
| 562 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 563 | #endif |
| 564 | }, |
| 565 | { |
| 566 | AArch64_ADDV_1b8b, ARM64_INS_ADDV, |
| 567 | #ifndef CAPSTONE_DIET |
| 568 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 569 | #endif |
| 570 | }, |
| 571 | { |
| 572 | AArch64_ADDV_1h4h, ARM64_INS_ADDV, |
| 573 | #ifndef CAPSTONE_DIET |
| 574 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 575 | #endif |
| 576 | }, |
| 577 | { |
| 578 | AArch64_ADDV_1h8h, ARM64_INS_ADDV, |
| 579 | #ifndef CAPSTONE_DIET |
| 580 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 581 | #endif |
| 582 | }, |
| 583 | { |
| 584 | AArch64_ADDV_1s4s, ARM64_INS_ADDV, |
| 585 | #ifndef CAPSTONE_DIET |
| 586 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 587 | #endif |
| 588 | }, |
| 589 | { |
| 590 | AArch64_ADDddd, ARM64_INS_ADD, |
| 591 | #ifndef CAPSTONE_DIET |
| 592 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 593 | #endif |
| 594 | }, |
| 595 | { |
| 596 | AArch64_ADDvvv_16B, ARM64_INS_ADD, |
| 597 | #ifndef CAPSTONE_DIET |
| 598 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 599 | #endif |
| 600 | }, |
| 601 | { |
| 602 | AArch64_ADDvvv_2D, ARM64_INS_ADD, |
| 603 | #ifndef CAPSTONE_DIET |
| 604 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 605 | #endif |
| 606 | }, |
| 607 | { |
| 608 | AArch64_ADDvvv_2S, ARM64_INS_ADD, |
| 609 | #ifndef CAPSTONE_DIET |
| 610 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 611 | #endif |
| 612 | }, |
| 613 | { |
| 614 | AArch64_ADDvvv_4H, ARM64_INS_ADD, |
| 615 | #ifndef CAPSTONE_DIET |
| 616 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 617 | #endif |
| 618 | }, |
| 619 | { |
| 620 | AArch64_ADDvvv_4S, ARM64_INS_ADD, |
| 621 | #ifndef CAPSTONE_DIET |
| 622 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 623 | #endif |
| 624 | }, |
| 625 | { |
| 626 | AArch64_ADDvvv_8B, ARM64_INS_ADD, |
| 627 | #ifndef CAPSTONE_DIET |
| 628 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 629 | #endif |
| 630 | }, |
| 631 | { |
| 632 | AArch64_ADDvvv_8H, ARM64_INS_ADD, |
| 633 | #ifndef CAPSTONE_DIET |
| 634 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 635 | #endif |
| 636 | }, |
| 637 | { |
| 638 | AArch64_ADDwwi_lsl0_S, ARM64_INS_ADD, |
| 639 | #ifndef CAPSTONE_DIET |
| 640 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 641 | #endif |
| 642 | }, |
| 643 | { |
| 644 | AArch64_ADDwwi_lsl0_cmp, ARM64_INS_CMN, |
| 645 | #ifndef CAPSTONE_DIET |
| 646 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 647 | #endif |
| 648 | }, |
| 649 | { |
| 650 | AArch64_ADDwwi_lsl0_s, ARM64_INS_ADD, |
| 651 | #ifndef CAPSTONE_DIET |
| 652 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 653 | #endif |
| 654 | }, |
| 655 | { |
| 656 | AArch64_ADDwwi_lsl12_S, ARM64_INS_ADD, |
| 657 | #ifndef CAPSTONE_DIET |
| 658 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 659 | #endif |
| 660 | }, |
| 661 | { |
| 662 | AArch64_ADDwwi_lsl12_cmp, ARM64_INS_CMN, |
| 663 | #ifndef CAPSTONE_DIET |
| 664 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 665 | #endif |
| 666 | }, |
| 667 | { |
| 668 | AArch64_ADDwwi_lsl12_s, ARM64_INS_ADD, |
| 669 | #ifndef CAPSTONE_DIET |
| 670 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 671 | #endif |
| 672 | }, |
| 673 | { |
| 674 | AArch64_ADDwww_asr, ARM64_INS_ADD, |
| 675 | #ifndef CAPSTONE_DIET |
| 676 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 677 | #endif |
| 678 | }, |
| 679 | { |
| 680 | AArch64_ADDwww_lsl, ARM64_INS_ADD, |
| 681 | #ifndef CAPSTONE_DIET |
| 682 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 683 | #endif |
| 684 | }, |
| 685 | { |
| 686 | AArch64_ADDwww_lsr, ARM64_INS_ADD, |
| 687 | #ifndef CAPSTONE_DIET |
| 688 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 689 | #endif |
| 690 | }, |
| 691 | { |
| 692 | AArch64_ADDwww_sxtb, ARM64_INS_ADD, |
| 693 | #ifndef CAPSTONE_DIET |
| 694 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 695 | #endif |
| 696 | }, |
| 697 | { |
| 698 | AArch64_ADDwww_sxth, ARM64_INS_ADD, |
| 699 | #ifndef CAPSTONE_DIET |
| 700 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 701 | #endif |
| 702 | }, |
| 703 | { |
| 704 | AArch64_ADDwww_sxtw, ARM64_INS_ADD, |
| 705 | #ifndef CAPSTONE_DIET |
| 706 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 707 | #endif |
| 708 | }, |
| 709 | { |
| 710 | AArch64_ADDwww_sxtx, ARM64_INS_ADD, |
| 711 | #ifndef CAPSTONE_DIET |
| 712 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 713 | #endif |
| 714 | }, |
| 715 | { |
| 716 | AArch64_ADDwww_uxtb, ARM64_INS_ADD, |
| 717 | #ifndef CAPSTONE_DIET |
| 718 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 719 | #endif |
| 720 | }, |
| 721 | { |
| 722 | AArch64_ADDwww_uxth, ARM64_INS_ADD, |
| 723 | #ifndef CAPSTONE_DIET |
| 724 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 725 | #endif |
| 726 | }, |
| 727 | { |
| 728 | AArch64_ADDwww_uxtw, ARM64_INS_ADD, |
| 729 | #ifndef CAPSTONE_DIET |
| 730 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 731 | #endif |
| 732 | }, |
| 733 | { |
| 734 | AArch64_ADDwww_uxtx, ARM64_INS_ADD, |
| 735 | #ifndef CAPSTONE_DIET |
| 736 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 737 | #endif |
| 738 | }, |
| 739 | { |
| 740 | AArch64_ADDxxi_lsl0_S, ARM64_INS_ADD, |
| 741 | #ifndef CAPSTONE_DIET |
| 742 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 743 | #endif |
| 744 | }, |
| 745 | { |
| 746 | AArch64_ADDxxi_lsl0_cmp, ARM64_INS_CMN, |
| 747 | #ifndef CAPSTONE_DIET |
| 748 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 749 | #endif |
| 750 | }, |
| 751 | { |
| 752 | AArch64_ADDxxi_lsl0_s, ARM64_INS_ADD, |
| 753 | #ifndef CAPSTONE_DIET |
| 754 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 755 | #endif |
| 756 | }, |
| 757 | { |
| 758 | AArch64_ADDxxi_lsl12_S, ARM64_INS_ADD, |
| 759 | #ifndef CAPSTONE_DIET |
| 760 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 761 | #endif |
| 762 | }, |
| 763 | { |
| 764 | AArch64_ADDxxi_lsl12_cmp, ARM64_INS_CMN, |
| 765 | #ifndef CAPSTONE_DIET |
| 766 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 767 | #endif |
| 768 | }, |
| 769 | { |
| 770 | AArch64_ADDxxi_lsl12_s, ARM64_INS_ADD, |
| 771 | #ifndef CAPSTONE_DIET |
| 772 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 773 | #endif |
| 774 | }, |
| 775 | { |
| 776 | AArch64_ADDxxw_sxtb, ARM64_INS_ADD, |
| 777 | #ifndef CAPSTONE_DIET |
| 778 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 779 | #endif |
| 780 | }, |
| 781 | { |
| 782 | AArch64_ADDxxw_sxth, ARM64_INS_ADD, |
| 783 | #ifndef CAPSTONE_DIET |
| 784 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 785 | #endif |
| 786 | }, |
| 787 | { |
| 788 | AArch64_ADDxxw_sxtw, ARM64_INS_ADD, |
| 789 | #ifndef CAPSTONE_DIET |
| 790 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 791 | #endif |
| 792 | }, |
| 793 | { |
| 794 | AArch64_ADDxxw_uxtb, ARM64_INS_ADD, |
| 795 | #ifndef CAPSTONE_DIET |
| 796 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 797 | #endif |
| 798 | }, |
| 799 | { |
| 800 | AArch64_ADDxxw_uxth, ARM64_INS_ADD, |
| 801 | #ifndef CAPSTONE_DIET |
| 802 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 803 | #endif |
| 804 | }, |
| 805 | { |
| 806 | AArch64_ADDxxw_uxtw, ARM64_INS_ADD, |
| 807 | #ifndef CAPSTONE_DIET |
| 808 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 809 | #endif |
| 810 | }, |
| 811 | { |
| 812 | AArch64_ADDxxx_asr, ARM64_INS_ADD, |
| 813 | #ifndef CAPSTONE_DIET |
| 814 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 815 | #endif |
| 816 | }, |
| 817 | { |
| 818 | AArch64_ADDxxx_lsl, ARM64_INS_ADD, |
| 819 | #ifndef CAPSTONE_DIET |
| 820 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 821 | #endif |
| 822 | }, |
| 823 | { |
| 824 | AArch64_ADDxxx_lsr, ARM64_INS_ADD, |
| 825 | #ifndef CAPSTONE_DIET |
| 826 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 827 | #endif |
| 828 | }, |
| 829 | { |
| 830 | AArch64_ADDxxx_sxtx, ARM64_INS_ADD, |
| 831 | #ifndef CAPSTONE_DIET |
| 832 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 833 | #endif |
| 834 | }, |
| 835 | { |
| 836 | AArch64_ADDxxx_uxtx, ARM64_INS_ADD, |
| 837 | #ifndef CAPSTONE_DIET |
| 838 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 839 | #endif |
| 840 | }, |
| 841 | { |
| 842 | AArch64_ADRPxi, ARM64_INS_ADRP, |
| 843 | #ifndef CAPSTONE_DIET |
| 844 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 845 | #endif |
| 846 | }, |
| 847 | { |
| 848 | AArch64_ADRxi, ARM64_INS_ADR, |
| 849 | #ifndef CAPSTONE_DIET |
| 850 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 851 | #endif |
| 852 | }, |
| 853 | { |
| 854 | AArch64_AESD, ARM64_INS_AESD, |
| 855 | #ifndef CAPSTONE_DIET |
| 856 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 857 | #endif |
| 858 | }, |
| 859 | { |
| 860 | AArch64_AESE, ARM64_INS_AESE, |
| 861 | #ifndef CAPSTONE_DIET |
| 862 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 863 | #endif |
| 864 | }, |
| 865 | { |
| 866 | AArch64_AESIMC, ARM64_INS_AESIMC, |
| 867 | #ifndef CAPSTONE_DIET |
| 868 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 869 | #endif |
| 870 | }, |
| 871 | { |
| 872 | AArch64_AESMC, ARM64_INS_AESMC, |
| 873 | #ifndef CAPSTONE_DIET |
| 874 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 875 | #endif |
| 876 | }, |
| 877 | { |
| 878 | AArch64_ANDSwwi, ARM64_INS_AND, |
| 879 | #ifndef CAPSTONE_DIET |
| 880 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 881 | #endif |
| 882 | }, |
| 883 | { |
| 884 | AArch64_ANDSwww_asr, ARM64_INS_AND, |
| 885 | #ifndef CAPSTONE_DIET |
| 886 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 887 | #endif |
| 888 | }, |
| 889 | { |
| 890 | AArch64_ANDSwww_lsl, ARM64_INS_AND, |
| 891 | #ifndef CAPSTONE_DIET |
| 892 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 893 | #endif |
| 894 | }, |
| 895 | { |
| 896 | AArch64_ANDSwww_lsr, ARM64_INS_AND, |
| 897 | #ifndef CAPSTONE_DIET |
| 898 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 899 | #endif |
| 900 | }, |
| 901 | { |
| 902 | AArch64_ANDSwww_ror, ARM64_INS_AND, |
| 903 | #ifndef CAPSTONE_DIET |
| 904 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 905 | #endif |
| 906 | }, |
| 907 | { |
| 908 | AArch64_ANDSxxi, ARM64_INS_AND, |
| 909 | #ifndef CAPSTONE_DIET |
| 910 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 911 | #endif |
| 912 | }, |
| 913 | { |
| 914 | AArch64_ANDSxxx_asr, ARM64_INS_AND, |
| 915 | #ifndef CAPSTONE_DIET |
| 916 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 917 | #endif |
| 918 | }, |
| 919 | { |
| 920 | AArch64_ANDSxxx_lsl, ARM64_INS_AND, |
| 921 | #ifndef CAPSTONE_DIET |
| 922 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 923 | #endif |
| 924 | }, |
| 925 | { |
| 926 | AArch64_ANDSxxx_lsr, ARM64_INS_AND, |
| 927 | #ifndef CAPSTONE_DIET |
| 928 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 929 | #endif |
| 930 | }, |
| 931 | { |
| 932 | AArch64_ANDSxxx_ror, ARM64_INS_AND, |
| 933 | #ifndef CAPSTONE_DIET |
| 934 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 935 | #endif |
| 936 | }, |
| 937 | { |
| 938 | AArch64_ANDvvv_16B, ARM64_INS_AND, |
| 939 | #ifndef CAPSTONE_DIET |
| 940 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 941 | #endif |
| 942 | }, |
| 943 | { |
| 944 | AArch64_ANDvvv_8B, ARM64_INS_AND, |
| 945 | #ifndef CAPSTONE_DIET |
| 946 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 947 | #endif |
| 948 | }, |
| 949 | { |
| 950 | AArch64_ANDwwi, ARM64_INS_AND, |
| 951 | #ifndef CAPSTONE_DIET |
| 952 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 953 | #endif |
| 954 | }, |
| 955 | { |
| 956 | AArch64_ANDwww_asr, ARM64_INS_AND, |
| 957 | #ifndef CAPSTONE_DIET |
| 958 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 959 | #endif |
| 960 | }, |
| 961 | { |
| 962 | AArch64_ANDwww_lsl, ARM64_INS_AND, |
| 963 | #ifndef CAPSTONE_DIET |
| 964 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 965 | #endif |
| 966 | }, |
| 967 | { |
| 968 | AArch64_ANDwww_lsr, ARM64_INS_AND, |
| 969 | #ifndef CAPSTONE_DIET |
| 970 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 971 | #endif |
| 972 | }, |
| 973 | { |
| 974 | AArch64_ANDwww_ror, ARM64_INS_AND, |
| 975 | #ifndef CAPSTONE_DIET |
| 976 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 977 | #endif |
| 978 | }, |
| 979 | { |
| 980 | AArch64_ANDxxi, ARM64_INS_AND, |
| 981 | #ifndef CAPSTONE_DIET |
| 982 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 983 | #endif |
| 984 | }, |
| 985 | { |
| 986 | AArch64_ANDxxx_asr, ARM64_INS_AND, |
| 987 | #ifndef CAPSTONE_DIET |
| 988 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 989 | #endif |
| 990 | }, |
| 991 | { |
| 992 | AArch64_ANDxxx_lsl, ARM64_INS_AND, |
| 993 | #ifndef CAPSTONE_DIET |
| 994 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 995 | #endif |
| 996 | }, |
| 997 | { |
| 998 | AArch64_ANDxxx_lsr, ARM64_INS_AND, |
| 999 | #ifndef CAPSTONE_DIET |
| 1000 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1001 | #endif |
| 1002 | }, |
| 1003 | { |
| 1004 | AArch64_ANDxxx_ror, ARM64_INS_AND, |
| 1005 | #ifndef CAPSTONE_DIET |
| 1006 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1007 | #endif |
| 1008 | }, |
| 1009 | { |
| 1010 | AArch64_ASRVwww, ARM64_INS_ASR, |
| 1011 | #ifndef CAPSTONE_DIET |
| 1012 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1013 | #endif |
| 1014 | }, |
| 1015 | { |
| 1016 | AArch64_ASRVxxx, ARM64_INS_ASR, |
| 1017 | #ifndef CAPSTONE_DIET |
| 1018 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1019 | #endif |
| 1020 | }, |
| 1021 | { |
| 1022 | AArch64_ASRwwi, ARM64_INS_ASR, |
| 1023 | #ifndef CAPSTONE_DIET |
| 1024 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1025 | #endif |
| 1026 | }, |
| 1027 | { |
| 1028 | AArch64_ASRxxi, ARM64_INS_ASR, |
| 1029 | #ifndef CAPSTONE_DIET |
| 1030 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1031 | #endif |
| 1032 | }, |
| 1033 | { |
| 1034 | AArch64_ATix, ARM64_INS_AT, |
| 1035 | #ifndef CAPSTONE_DIET |
| 1036 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1037 | #endif |
| 1038 | }, |
| 1039 | { |
| 1040 | AArch64_BFIwwii, ARM64_INS_BFI, |
| 1041 | #ifndef CAPSTONE_DIET |
| 1042 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1043 | #endif |
| 1044 | }, |
| 1045 | { |
| 1046 | AArch64_BFIxxii, ARM64_INS_BFI, |
| 1047 | #ifndef CAPSTONE_DIET |
| 1048 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1049 | #endif |
| 1050 | }, |
| 1051 | { |
| 1052 | AArch64_BFMwwii, ARM64_INS_BFM, |
| 1053 | #ifndef CAPSTONE_DIET |
| 1054 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1055 | #endif |
| 1056 | }, |
| 1057 | { |
| 1058 | AArch64_BFMxxii, ARM64_INS_BFM, |
| 1059 | #ifndef CAPSTONE_DIET |
| 1060 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1061 | #endif |
| 1062 | }, |
| 1063 | { |
| 1064 | AArch64_BFXILwwii, ARM64_INS_BFXIL, |
| 1065 | #ifndef CAPSTONE_DIET |
| 1066 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1067 | #endif |
| 1068 | }, |
| 1069 | { |
| 1070 | AArch64_BFXILxxii, ARM64_INS_BFXIL, |
| 1071 | #ifndef CAPSTONE_DIET |
| 1072 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1073 | #endif |
| 1074 | }, |
| 1075 | { |
| 1076 | AArch64_BICSwww_asr, ARM64_INS_BIC, |
| 1077 | #ifndef CAPSTONE_DIET |
| 1078 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1079 | #endif |
| 1080 | }, |
| 1081 | { |
| 1082 | AArch64_BICSwww_lsl, ARM64_INS_BIC, |
| 1083 | #ifndef CAPSTONE_DIET |
| 1084 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1085 | #endif |
| 1086 | }, |
| 1087 | { |
| 1088 | AArch64_BICSwww_lsr, ARM64_INS_BIC, |
| 1089 | #ifndef CAPSTONE_DIET |
| 1090 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1091 | #endif |
| 1092 | }, |
| 1093 | { |
| 1094 | AArch64_BICSwww_ror, ARM64_INS_BIC, |
| 1095 | #ifndef CAPSTONE_DIET |
| 1096 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1097 | #endif |
| 1098 | }, |
| 1099 | { |
| 1100 | AArch64_BICSxxx_asr, ARM64_INS_BIC, |
| 1101 | #ifndef CAPSTONE_DIET |
| 1102 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1103 | #endif |
| 1104 | }, |
| 1105 | { |
| 1106 | AArch64_BICSxxx_lsl, ARM64_INS_BIC, |
| 1107 | #ifndef CAPSTONE_DIET |
| 1108 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1109 | #endif |
| 1110 | }, |
| 1111 | { |
| 1112 | AArch64_BICSxxx_lsr, ARM64_INS_BIC, |
| 1113 | #ifndef CAPSTONE_DIET |
| 1114 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1115 | #endif |
| 1116 | }, |
| 1117 | { |
| 1118 | AArch64_BICSxxx_ror, ARM64_INS_BIC, |
| 1119 | #ifndef CAPSTONE_DIET |
| 1120 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1121 | #endif |
| 1122 | }, |
| 1123 | { |
| 1124 | AArch64_BICvi_lsl_2S, ARM64_INS_BIC, |
| 1125 | #ifndef CAPSTONE_DIET |
| 1126 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1127 | #endif |
| 1128 | }, |
| 1129 | { |
| 1130 | AArch64_BICvi_lsl_4H, ARM64_INS_BIC, |
| 1131 | #ifndef CAPSTONE_DIET |
| 1132 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1133 | #endif |
| 1134 | }, |
| 1135 | { |
| 1136 | AArch64_BICvi_lsl_4S, ARM64_INS_BIC, |
| 1137 | #ifndef CAPSTONE_DIET |
| 1138 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1139 | #endif |
| 1140 | }, |
| 1141 | { |
| 1142 | AArch64_BICvi_lsl_8H, ARM64_INS_BIC, |
| 1143 | #ifndef CAPSTONE_DIET |
| 1144 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1145 | #endif |
| 1146 | }, |
| 1147 | { |
| 1148 | AArch64_BICvvv_16B, ARM64_INS_BIC, |
| 1149 | #ifndef CAPSTONE_DIET |
| 1150 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1151 | #endif |
| 1152 | }, |
| 1153 | { |
| 1154 | AArch64_BICvvv_8B, ARM64_INS_BIC, |
| 1155 | #ifndef CAPSTONE_DIET |
| 1156 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1157 | #endif |
| 1158 | }, |
| 1159 | { |
| 1160 | AArch64_BICwww_asr, ARM64_INS_BIC, |
| 1161 | #ifndef CAPSTONE_DIET |
| 1162 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1163 | #endif |
| 1164 | }, |
| 1165 | { |
| 1166 | AArch64_BICwww_lsl, ARM64_INS_BIC, |
| 1167 | #ifndef CAPSTONE_DIET |
| 1168 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1169 | #endif |
| 1170 | }, |
| 1171 | { |
| 1172 | AArch64_BICwww_lsr, ARM64_INS_BIC, |
| 1173 | #ifndef CAPSTONE_DIET |
| 1174 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1175 | #endif |
| 1176 | }, |
| 1177 | { |
| 1178 | AArch64_BICwww_ror, ARM64_INS_BIC, |
| 1179 | #ifndef CAPSTONE_DIET |
| 1180 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1181 | #endif |
| 1182 | }, |
| 1183 | { |
| 1184 | AArch64_BICxxx_asr, ARM64_INS_BIC, |
| 1185 | #ifndef CAPSTONE_DIET |
| 1186 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1187 | #endif |
| 1188 | }, |
| 1189 | { |
| 1190 | AArch64_BICxxx_lsl, ARM64_INS_BIC, |
| 1191 | #ifndef CAPSTONE_DIET |
| 1192 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1193 | #endif |
| 1194 | }, |
| 1195 | { |
| 1196 | AArch64_BICxxx_lsr, ARM64_INS_BIC, |
| 1197 | #ifndef CAPSTONE_DIET |
| 1198 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1199 | #endif |
| 1200 | }, |
| 1201 | { |
| 1202 | AArch64_BICxxx_ror, ARM64_INS_BIC, |
| 1203 | #ifndef CAPSTONE_DIET |
| 1204 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1205 | #endif |
| 1206 | }, |
| 1207 | { |
| 1208 | AArch64_BIFvvv_16B, ARM64_INS_BIF, |
| 1209 | #ifndef CAPSTONE_DIET |
| 1210 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1211 | #endif |
| 1212 | }, |
| 1213 | { |
| 1214 | AArch64_BIFvvv_8B, ARM64_INS_BIF, |
| 1215 | #ifndef CAPSTONE_DIET |
| 1216 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1217 | #endif |
| 1218 | }, |
| 1219 | { |
| 1220 | AArch64_BITvvv_16B, ARM64_INS_BIT, |
| 1221 | #ifndef CAPSTONE_DIET |
| 1222 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1223 | #endif |
| 1224 | }, |
| 1225 | { |
| 1226 | AArch64_BITvvv_8B, ARM64_INS_BIT, |
| 1227 | #ifndef CAPSTONE_DIET |
| 1228 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1229 | #endif |
| 1230 | }, |
| 1231 | { |
| 1232 | AArch64_BLRx, ARM64_INS_BLR, |
| 1233 | #ifndef CAPSTONE_DIET |
| 1234 | { 0 }, { ARM64_REG_X30, 0 }, { 0 }, 1, 1 |
| 1235 | #endif |
| 1236 | }, |
| 1237 | { |
| 1238 | AArch64_BLimm, ARM64_INS_BL, |
| 1239 | #ifndef CAPSTONE_DIET |
| 1240 | { 0 }, { ARM64_REG_X30, 0 }, { 0 }, 1, 0 |
| 1241 | #endif |
| 1242 | }, |
| 1243 | { |
| 1244 | AArch64_BRKi, ARM64_INS_BRK, |
| 1245 | #ifndef CAPSTONE_DIET |
| 1246 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 1247 | #endif |
| 1248 | }, |
| 1249 | { |
| 1250 | AArch64_BRx, ARM64_INS_BR, |
| 1251 | #ifndef CAPSTONE_DIET |
| 1252 | { 0 }, { 0 }, { 0 }, 1, 1 |
| 1253 | #endif |
| 1254 | }, |
| 1255 | { |
| 1256 | AArch64_BSLvvv_16B, ARM64_INS_BSL, |
| 1257 | #ifndef CAPSTONE_DIET |
| 1258 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1259 | #endif |
| 1260 | }, |
| 1261 | { |
| 1262 | AArch64_BSLvvv_8B, ARM64_INS_BSL, |
| 1263 | #ifndef CAPSTONE_DIET |
| 1264 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1265 | #endif |
| 1266 | }, |
| 1267 | { |
| 1268 | AArch64_Bcc, ARM64_INS_B, |
| 1269 | #ifndef CAPSTONE_DIET |
| 1270 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 1, 0 |
| 1271 | #endif |
| 1272 | }, |
| 1273 | { |
| 1274 | AArch64_Bimm, ARM64_INS_B, |
| 1275 | #ifndef CAPSTONE_DIET |
| 1276 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 1277 | #endif |
| 1278 | }, |
| 1279 | { |
| 1280 | AArch64_CBNZw, ARM64_INS_CBNZ, |
| 1281 | #ifndef CAPSTONE_DIET |
| 1282 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 1283 | #endif |
| 1284 | }, |
| 1285 | { |
| 1286 | AArch64_CBNZx, ARM64_INS_CBNZ, |
| 1287 | #ifndef CAPSTONE_DIET |
| 1288 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 1289 | #endif |
| 1290 | }, |
| 1291 | { |
| 1292 | AArch64_CBZw, ARM64_INS_CBZ, |
| 1293 | #ifndef CAPSTONE_DIET |
| 1294 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 1295 | #endif |
| 1296 | }, |
| 1297 | { |
| 1298 | AArch64_CBZx, ARM64_INS_CBZ, |
| 1299 | #ifndef CAPSTONE_DIET |
| 1300 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 1301 | #endif |
| 1302 | }, |
| 1303 | { |
| 1304 | AArch64_CCMNwi, ARM64_INS_CCMN, |
| 1305 | #ifndef CAPSTONE_DIET |
| 1306 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1307 | #endif |
| 1308 | }, |
| 1309 | { |
| 1310 | AArch64_CCMNww, ARM64_INS_CCMN, |
| 1311 | #ifndef CAPSTONE_DIET |
| 1312 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1313 | #endif |
| 1314 | }, |
| 1315 | { |
| 1316 | AArch64_CCMNxi, ARM64_INS_CCMN, |
| 1317 | #ifndef CAPSTONE_DIET |
| 1318 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1319 | #endif |
| 1320 | }, |
| 1321 | { |
| 1322 | AArch64_CCMNxx, ARM64_INS_CCMN, |
| 1323 | #ifndef CAPSTONE_DIET |
| 1324 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1325 | #endif |
| 1326 | }, |
| 1327 | { |
| 1328 | AArch64_CCMPwi, ARM64_INS_CCMP, |
| 1329 | #ifndef CAPSTONE_DIET |
| 1330 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1331 | #endif |
| 1332 | }, |
| 1333 | { |
| 1334 | AArch64_CCMPww, ARM64_INS_CCMP, |
| 1335 | #ifndef CAPSTONE_DIET |
| 1336 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1337 | #endif |
| 1338 | }, |
| 1339 | { |
| 1340 | AArch64_CCMPxi, ARM64_INS_CCMP, |
| 1341 | #ifndef CAPSTONE_DIET |
| 1342 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1343 | #endif |
| 1344 | }, |
| 1345 | { |
| 1346 | AArch64_CCMPxx, ARM64_INS_CCMP, |
| 1347 | #ifndef CAPSTONE_DIET |
| 1348 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1349 | #endif |
| 1350 | }, |
| 1351 | { |
| 1352 | AArch64_CLREXi, ARM64_INS_CLREX, |
| 1353 | #ifndef CAPSTONE_DIET |
| 1354 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1355 | #endif |
| 1356 | }, |
| 1357 | { |
| 1358 | AArch64_CLS16b, ARM64_INS_CLS, |
| 1359 | #ifndef CAPSTONE_DIET |
| 1360 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1361 | #endif |
| 1362 | }, |
| 1363 | { |
| 1364 | AArch64_CLS2s, ARM64_INS_CLS, |
| 1365 | #ifndef CAPSTONE_DIET |
| 1366 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1367 | #endif |
| 1368 | }, |
| 1369 | { |
| 1370 | AArch64_CLS4h, ARM64_INS_CLS, |
| 1371 | #ifndef CAPSTONE_DIET |
| 1372 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1373 | #endif |
| 1374 | }, |
| 1375 | { |
| 1376 | AArch64_CLS4s, ARM64_INS_CLS, |
| 1377 | #ifndef CAPSTONE_DIET |
| 1378 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1379 | #endif |
| 1380 | }, |
| 1381 | { |
| 1382 | AArch64_CLS8b, ARM64_INS_CLS, |
| 1383 | #ifndef CAPSTONE_DIET |
| 1384 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1385 | #endif |
| 1386 | }, |
| 1387 | { |
| 1388 | AArch64_CLS8h, ARM64_INS_CLS, |
| 1389 | #ifndef CAPSTONE_DIET |
| 1390 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1391 | #endif |
| 1392 | }, |
| 1393 | { |
| 1394 | AArch64_CLSww, ARM64_INS_CLS, |
| 1395 | #ifndef CAPSTONE_DIET |
| 1396 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1397 | #endif |
| 1398 | }, |
| 1399 | { |
| 1400 | AArch64_CLSxx, ARM64_INS_CLS, |
| 1401 | #ifndef CAPSTONE_DIET |
| 1402 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1403 | #endif |
| 1404 | }, |
| 1405 | { |
| 1406 | AArch64_CLZ16b, ARM64_INS_CLZ, |
| 1407 | #ifndef CAPSTONE_DIET |
| 1408 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1409 | #endif |
| 1410 | }, |
| 1411 | { |
| 1412 | AArch64_CLZ2s, ARM64_INS_CLZ, |
| 1413 | #ifndef CAPSTONE_DIET |
| 1414 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1415 | #endif |
| 1416 | }, |
| 1417 | { |
| 1418 | AArch64_CLZ4h, ARM64_INS_CLZ, |
| 1419 | #ifndef CAPSTONE_DIET |
| 1420 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1421 | #endif |
| 1422 | }, |
| 1423 | { |
| 1424 | AArch64_CLZ4s, ARM64_INS_CLZ, |
| 1425 | #ifndef CAPSTONE_DIET |
| 1426 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1427 | #endif |
| 1428 | }, |
| 1429 | { |
| 1430 | AArch64_CLZ8b, ARM64_INS_CLZ, |
| 1431 | #ifndef CAPSTONE_DIET |
| 1432 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1433 | #endif |
| 1434 | }, |
| 1435 | { |
| 1436 | AArch64_CLZ8h, ARM64_INS_CLZ, |
| 1437 | #ifndef CAPSTONE_DIET |
| 1438 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1439 | #endif |
| 1440 | }, |
| 1441 | { |
| 1442 | AArch64_CLZww, ARM64_INS_CLZ, |
| 1443 | #ifndef CAPSTONE_DIET |
| 1444 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1445 | #endif |
| 1446 | }, |
| 1447 | { |
| 1448 | AArch64_CLZxx, ARM64_INS_CLZ, |
| 1449 | #ifndef CAPSTONE_DIET |
| 1450 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 1451 | #endif |
| 1452 | }, |
| 1453 | { |
| 1454 | AArch64_CMEQddd, ARM64_INS_CMEQ, |
| 1455 | #ifndef CAPSTONE_DIET |
| 1456 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1457 | #endif |
| 1458 | }, |
| 1459 | { |
| 1460 | AArch64_CMEQddi, ARM64_INS_CMEQ, |
| 1461 | #ifndef CAPSTONE_DIET |
| 1462 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1463 | #endif |
| 1464 | }, |
| 1465 | { |
| 1466 | AArch64_CMEQvvi_16B, ARM64_INS_CMEQ, |
| 1467 | #ifndef CAPSTONE_DIET |
| 1468 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1469 | #endif |
| 1470 | }, |
| 1471 | { |
| 1472 | AArch64_CMEQvvi_2D, ARM64_INS_CMEQ, |
| 1473 | #ifndef CAPSTONE_DIET |
| 1474 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1475 | #endif |
| 1476 | }, |
| 1477 | { |
| 1478 | AArch64_CMEQvvi_2S, ARM64_INS_CMEQ, |
| 1479 | #ifndef CAPSTONE_DIET |
| 1480 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1481 | #endif |
| 1482 | }, |
| 1483 | { |
| 1484 | AArch64_CMEQvvi_4H, ARM64_INS_CMEQ, |
| 1485 | #ifndef CAPSTONE_DIET |
| 1486 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1487 | #endif |
| 1488 | }, |
| 1489 | { |
| 1490 | AArch64_CMEQvvi_4S, ARM64_INS_CMEQ, |
| 1491 | #ifndef CAPSTONE_DIET |
| 1492 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1493 | #endif |
| 1494 | }, |
| 1495 | { |
| 1496 | AArch64_CMEQvvi_8B, ARM64_INS_CMEQ, |
| 1497 | #ifndef CAPSTONE_DIET |
| 1498 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1499 | #endif |
| 1500 | }, |
| 1501 | { |
| 1502 | AArch64_CMEQvvi_8H, ARM64_INS_CMEQ, |
| 1503 | #ifndef CAPSTONE_DIET |
| 1504 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1505 | #endif |
| 1506 | }, |
| 1507 | { |
| 1508 | AArch64_CMEQvvv_16B, ARM64_INS_CMEQ, |
| 1509 | #ifndef CAPSTONE_DIET |
| 1510 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1511 | #endif |
| 1512 | }, |
| 1513 | { |
| 1514 | AArch64_CMEQvvv_2D, ARM64_INS_CMEQ, |
| 1515 | #ifndef CAPSTONE_DIET |
| 1516 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1517 | #endif |
| 1518 | }, |
| 1519 | { |
| 1520 | AArch64_CMEQvvv_2S, ARM64_INS_CMEQ, |
| 1521 | #ifndef CAPSTONE_DIET |
| 1522 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1523 | #endif |
| 1524 | }, |
| 1525 | { |
| 1526 | AArch64_CMEQvvv_4H, ARM64_INS_CMEQ, |
| 1527 | #ifndef CAPSTONE_DIET |
| 1528 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1529 | #endif |
| 1530 | }, |
| 1531 | { |
| 1532 | AArch64_CMEQvvv_4S, ARM64_INS_CMEQ, |
| 1533 | #ifndef CAPSTONE_DIET |
| 1534 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1535 | #endif |
| 1536 | }, |
| 1537 | { |
| 1538 | AArch64_CMEQvvv_8B, ARM64_INS_CMEQ, |
| 1539 | #ifndef CAPSTONE_DIET |
| 1540 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1541 | #endif |
| 1542 | }, |
| 1543 | { |
| 1544 | AArch64_CMEQvvv_8H, ARM64_INS_CMEQ, |
| 1545 | #ifndef CAPSTONE_DIET |
| 1546 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1547 | #endif |
| 1548 | }, |
| 1549 | { |
| 1550 | AArch64_CMGEddd, ARM64_INS_CMGE, |
| 1551 | #ifndef CAPSTONE_DIET |
| 1552 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1553 | #endif |
| 1554 | }, |
| 1555 | { |
| 1556 | AArch64_CMGEddi, ARM64_INS_CMGE, |
| 1557 | #ifndef CAPSTONE_DIET |
| 1558 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1559 | #endif |
| 1560 | }, |
| 1561 | { |
| 1562 | AArch64_CMGEvvi_16B, ARM64_INS_CMGE, |
| 1563 | #ifndef CAPSTONE_DIET |
| 1564 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1565 | #endif |
| 1566 | }, |
| 1567 | { |
| 1568 | AArch64_CMGEvvi_2D, ARM64_INS_CMGE, |
| 1569 | #ifndef CAPSTONE_DIET |
| 1570 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1571 | #endif |
| 1572 | }, |
| 1573 | { |
| 1574 | AArch64_CMGEvvi_2S, ARM64_INS_CMGE, |
| 1575 | #ifndef CAPSTONE_DIET |
| 1576 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1577 | #endif |
| 1578 | }, |
| 1579 | { |
| 1580 | AArch64_CMGEvvi_4H, ARM64_INS_CMGE, |
| 1581 | #ifndef CAPSTONE_DIET |
| 1582 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1583 | #endif |
| 1584 | }, |
| 1585 | { |
| 1586 | AArch64_CMGEvvi_4S, ARM64_INS_CMGE, |
| 1587 | #ifndef CAPSTONE_DIET |
| 1588 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1589 | #endif |
| 1590 | }, |
| 1591 | { |
| 1592 | AArch64_CMGEvvi_8B, ARM64_INS_CMGE, |
| 1593 | #ifndef CAPSTONE_DIET |
| 1594 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1595 | #endif |
| 1596 | }, |
| 1597 | { |
| 1598 | AArch64_CMGEvvi_8H, ARM64_INS_CMGE, |
| 1599 | #ifndef CAPSTONE_DIET |
| 1600 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1601 | #endif |
| 1602 | }, |
| 1603 | { |
| 1604 | AArch64_CMGEvvv_16B, ARM64_INS_CMGE, |
| 1605 | #ifndef CAPSTONE_DIET |
| 1606 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1607 | #endif |
| 1608 | }, |
| 1609 | { |
| 1610 | AArch64_CMGEvvv_2D, ARM64_INS_CMGE, |
| 1611 | #ifndef CAPSTONE_DIET |
| 1612 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1613 | #endif |
| 1614 | }, |
| 1615 | { |
| 1616 | AArch64_CMGEvvv_2S, ARM64_INS_CMGE, |
| 1617 | #ifndef CAPSTONE_DIET |
| 1618 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1619 | #endif |
| 1620 | }, |
| 1621 | { |
| 1622 | AArch64_CMGEvvv_4H, ARM64_INS_CMGE, |
| 1623 | #ifndef CAPSTONE_DIET |
| 1624 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1625 | #endif |
| 1626 | }, |
| 1627 | { |
| 1628 | AArch64_CMGEvvv_4S, ARM64_INS_CMGE, |
| 1629 | #ifndef CAPSTONE_DIET |
| 1630 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1631 | #endif |
| 1632 | }, |
| 1633 | { |
| 1634 | AArch64_CMGEvvv_8B, ARM64_INS_CMGE, |
| 1635 | #ifndef CAPSTONE_DIET |
| 1636 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1637 | #endif |
| 1638 | }, |
| 1639 | { |
| 1640 | AArch64_CMGEvvv_8H, ARM64_INS_CMGE, |
| 1641 | #ifndef CAPSTONE_DIET |
| 1642 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1643 | #endif |
| 1644 | }, |
| 1645 | { |
| 1646 | AArch64_CMGTddd, ARM64_INS_CMGT, |
| 1647 | #ifndef CAPSTONE_DIET |
| 1648 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1649 | #endif |
| 1650 | }, |
| 1651 | { |
| 1652 | AArch64_CMGTddi, ARM64_INS_CMGT, |
| 1653 | #ifndef CAPSTONE_DIET |
| 1654 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1655 | #endif |
| 1656 | }, |
| 1657 | { |
| 1658 | AArch64_CMGTvvi_16B, ARM64_INS_CMGT, |
| 1659 | #ifndef CAPSTONE_DIET |
| 1660 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1661 | #endif |
| 1662 | }, |
| 1663 | { |
| 1664 | AArch64_CMGTvvi_2D, ARM64_INS_CMGT, |
| 1665 | #ifndef CAPSTONE_DIET |
| 1666 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1667 | #endif |
| 1668 | }, |
| 1669 | { |
| 1670 | AArch64_CMGTvvi_2S, ARM64_INS_CMGT, |
| 1671 | #ifndef CAPSTONE_DIET |
| 1672 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1673 | #endif |
| 1674 | }, |
| 1675 | { |
| 1676 | AArch64_CMGTvvi_4H, ARM64_INS_CMGT, |
| 1677 | #ifndef CAPSTONE_DIET |
| 1678 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1679 | #endif |
| 1680 | }, |
| 1681 | { |
| 1682 | AArch64_CMGTvvi_4S, ARM64_INS_CMGT, |
| 1683 | #ifndef CAPSTONE_DIET |
| 1684 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1685 | #endif |
| 1686 | }, |
| 1687 | { |
| 1688 | AArch64_CMGTvvi_8B, ARM64_INS_CMGT, |
| 1689 | #ifndef CAPSTONE_DIET |
| 1690 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1691 | #endif |
| 1692 | }, |
| 1693 | { |
| 1694 | AArch64_CMGTvvi_8H, ARM64_INS_CMGT, |
| 1695 | #ifndef CAPSTONE_DIET |
| 1696 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1697 | #endif |
| 1698 | }, |
| 1699 | { |
| 1700 | AArch64_CMGTvvv_16B, ARM64_INS_CMGT, |
| 1701 | #ifndef CAPSTONE_DIET |
| 1702 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1703 | #endif |
| 1704 | }, |
| 1705 | { |
| 1706 | AArch64_CMGTvvv_2D, ARM64_INS_CMGT, |
| 1707 | #ifndef CAPSTONE_DIET |
| 1708 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1709 | #endif |
| 1710 | }, |
| 1711 | { |
| 1712 | AArch64_CMGTvvv_2S, ARM64_INS_CMGT, |
| 1713 | #ifndef CAPSTONE_DIET |
| 1714 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1715 | #endif |
| 1716 | }, |
| 1717 | { |
| 1718 | AArch64_CMGTvvv_4H, ARM64_INS_CMGT, |
| 1719 | #ifndef CAPSTONE_DIET |
| 1720 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1721 | #endif |
| 1722 | }, |
| 1723 | { |
| 1724 | AArch64_CMGTvvv_4S, ARM64_INS_CMGT, |
| 1725 | #ifndef CAPSTONE_DIET |
| 1726 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1727 | #endif |
| 1728 | }, |
| 1729 | { |
| 1730 | AArch64_CMGTvvv_8B, ARM64_INS_CMGT, |
| 1731 | #ifndef CAPSTONE_DIET |
| 1732 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1733 | #endif |
| 1734 | }, |
| 1735 | { |
| 1736 | AArch64_CMGTvvv_8H, ARM64_INS_CMGT, |
| 1737 | #ifndef CAPSTONE_DIET |
| 1738 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1739 | #endif |
| 1740 | }, |
| 1741 | { |
| 1742 | AArch64_CMHIddd, ARM64_INS_CMHI, |
| 1743 | #ifndef CAPSTONE_DIET |
| 1744 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1745 | #endif |
| 1746 | }, |
| 1747 | { |
| 1748 | AArch64_CMHIvvv_16B, ARM64_INS_CMHI, |
| 1749 | #ifndef CAPSTONE_DIET |
| 1750 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1751 | #endif |
| 1752 | }, |
| 1753 | { |
| 1754 | AArch64_CMHIvvv_2D, ARM64_INS_CMHI, |
| 1755 | #ifndef CAPSTONE_DIET |
| 1756 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1757 | #endif |
| 1758 | }, |
| 1759 | { |
| 1760 | AArch64_CMHIvvv_2S, ARM64_INS_CMHI, |
| 1761 | #ifndef CAPSTONE_DIET |
| 1762 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1763 | #endif |
| 1764 | }, |
| 1765 | { |
| 1766 | AArch64_CMHIvvv_4H, ARM64_INS_CMHI, |
| 1767 | #ifndef CAPSTONE_DIET |
| 1768 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1769 | #endif |
| 1770 | }, |
| 1771 | { |
| 1772 | AArch64_CMHIvvv_4S, ARM64_INS_CMHI, |
| 1773 | #ifndef CAPSTONE_DIET |
| 1774 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1775 | #endif |
| 1776 | }, |
| 1777 | { |
| 1778 | AArch64_CMHIvvv_8B, ARM64_INS_CMHI, |
| 1779 | #ifndef CAPSTONE_DIET |
| 1780 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1781 | #endif |
| 1782 | }, |
| 1783 | { |
| 1784 | AArch64_CMHIvvv_8H, ARM64_INS_CMHI, |
| 1785 | #ifndef CAPSTONE_DIET |
| 1786 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1787 | #endif |
| 1788 | }, |
| 1789 | { |
| 1790 | AArch64_CMHSddd, ARM64_INS_CMHS, |
| 1791 | #ifndef CAPSTONE_DIET |
| 1792 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1793 | #endif |
| 1794 | }, |
| 1795 | { |
| 1796 | AArch64_CMHSvvv_16B, ARM64_INS_CMHS, |
| 1797 | #ifndef CAPSTONE_DIET |
| 1798 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1799 | #endif |
| 1800 | }, |
| 1801 | { |
| 1802 | AArch64_CMHSvvv_2D, ARM64_INS_CMHS, |
| 1803 | #ifndef CAPSTONE_DIET |
| 1804 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1805 | #endif |
| 1806 | }, |
| 1807 | { |
| 1808 | AArch64_CMHSvvv_2S, ARM64_INS_CMHS, |
| 1809 | #ifndef CAPSTONE_DIET |
| 1810 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1811 | #endif |
| 1812 | }, |
| 1813 | { |
| 1814 | AArch64_CMHSvvv_4H, ARM64_INS_CMHS, |
| 1815 | #ifndef CAPSTONE_DIET |
| 1816 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1817 | #endif |
| 1818 | }, |
| 1819 | { |
| 1820 | AArch64_CMHSvvv_4S, ARM64_INS_CMHS, |
| 1821 | #ifndef CAPSTONE_DIET |
| 1822 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1823 | #endif |
| 1824 | }, |
| 1825 | { |
| 1826 | AArch64_CMHSvvv_8B, ARM64_INS_CMHS, |
| 1827 | #ifndef CAPSTONE_DIET |
| 1828 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1829 | #endif |
| 1830 | }, |
| 1831 | { |
| 1832 | AArch64_CMHSvvv_8H, ARM64_INS_CMHS, |
| 1833 | #ifndef CAPSTONE_DIET |
| 1834 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1835 | #endif |
| 1836 | }, |
| 1837 | { |
| 1838 | AArch64_CMLEddi, ARM64_INS_CMLE, |
| 1839 | #ifndef CAPSTONE_DIET |
| 1840 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1841 | #endif |
| 1842 | }, |
| 1843 | { |
| 1844 | AArch64_CMLEvvi_16B, ARM64_INS_CMLE, |
| 1845 | #ifndef CAPSTONE_DIET |
| 1846 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1847 | #endif |
| 1848 | }, |
| 1849 | { |
| 1850 | AArch64_CMLEvvi_2D, ARM64_INS_CMLE, |
| 1851 | #ifndef CAPSTONE_DIET |
| 1852 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1853 | #endif |
| 1854 | }, |
| 1855 | { |
| 1856 | AArch64_CMLEvvi_2S, ARM64_INS_CMLE, |
| 1857 | #ifndef CAPSTONE_DIET |
| 1858 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1859 | #endif |
| 1860 | }, |
| 1861 | { |
| 1862 | AArch64_CMLEvvi_4H, ARM64_INS_CMLE, |
| 1863 | #ifndef CAPSTONE_DIET |
| 1864 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1865 | #endif |
| 1866 | }, |
| 1867 | { |
| 1868 | AArch64_CMLEvvi_4S, ARM64_INS_CMLE, |
| 1869 | #ifndef CAPSTONE_DIET |
| 1870 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1871 | #endif |
| 1872 | }, |
| 1873 | { |
| 1874 | AArch64_CMLEvvi_8B, ARM64_INS_CMLE, |
| 1875 | #ifndef CAPSTONE_DIET |
| 1876 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1877 | #endif |
| 1878 | }, |
| 1879 | { |
| 1880 | AArch64_CMLEvvi_8H, ARM64_INS_CMLE, |
| 1881 | #ifndef CAPSTONE_DIET |
| 1882 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1883 | #endif |
| 1884 | }, |
| 1885 | { |
| 1886 | AArch64_CMLTddi, ARM64_INS_CMLT, |
| 1887 | #ifndef CAPSTONE_DIET |
| 1888 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1889 | #endif |
| 1890 | }, |
| 1891 | { |
| 1892 | AArch64_CMLTvvi_16B, ARM64_INS_CMLT, |
| 1893 | #ifndef CAPSTONE_DIET |
| 1894 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1895 | #endif |
| 1896 | }, |
| 1897 | { |
| 1898 | AArch64_CMLTvvi_2D, ARM64_INS_CMLT, |
| 1899 | #ifndef CAPSTONE_DIET |
| 1900 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1901 | #endif |
| 1902 | }, |
| 1903 | { |
| 1904 | AArch64_CMLTvvi_2S, ARM64_INS_CMLT, |
| 1905 | #ifndef CAPSTONE_DIET |
| 1906 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1907 | #endif |
| 1908 | }, |
| 1909 | { |
| 1910 | AArch64_CMLTvvi_4H, ARM64_INS_CMLT, |
| 1911 | #ifndef CAPSTONE_DIET |
| 1912 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1913 | #endif |
| 1914 | }, |
| 1915 | { |
| 1916 | AArch64_CMLTvvi_4S, ARM64_INS_CMLT, |
| 1917 | #ifndef CAPSTONE_DIET |
| 1918 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1919 | #endif |
| 1920 | }, |
| 1921 | { |
| 1922 | AArch64_CMLTvvi_8B, ARM64_INS_CMLT, |
| 1923 | #ifndef CAPSTONE_DIET |
| 1924 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1925 | #endif |
| 1926 | }, |
| 1927 | { |
| 1928 | AArch64_CMLTvvi_8H, ARM64_INS_CMLT, |
| 1929 | #ifndef CAPSTONE_DIET |
| 1930 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 1931 | #endif |
| 1932 | }, |
| 1933 | { |
| 1934 | AArch64_CMNww_asr, ARM64_INS_CMN, |
| 1935 | #ifndef CAPSTONE_DIET |
| 1936 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1937 | #endif |
| 1938 | }, |
| 1939 | { |
| 1940 | AArch64_CMNww_lsl, ARM64_INS_CMN, |
| 1941 | #ifndef CAPSTONE_DIET |
| 1942 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1943 | #endif |
| 1944 | }, |
| 1945 | { |
| 1946 | AArch64_CMNww_lsr, ARM64_INS_CMN, |
| 1947 | #ifndef CAPSTONE_DIET |
| 1948 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1949 | #endif |
| 1950 | }, |
| 1951 | { |
| 1952 | AArch64_CMNww_sxtb, ARM64_INS_CMN, |
| 1953 | #ifndef CAPSTONE_DIET |
| 1954 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1955 | #endif |
| 1956 | }, |
| 1957 | { |
| 1958 | AArch64_CMNww_sxth, ARM64_INS_CMN, |
| 1959 | #ifndef CAPSTONE_DIET |
| 1960 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1961 | #endif |
| 1962 | }, |
| 1963 | { |
| 1964 | AArch64_CMNww_sxtw, ARM64_INS_CMN, |
| 1965 | #ifndef CAPSTONE_DIET |
| 1966 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1967 | #endif |
| 1968 | }, |
| 1969 | { |
| 1970 | AArch64_CMNww_sxtx, ARM64_INS_CMN, |
| 1971 | #ifndef CAPSTONE_DIET |
| 1972 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1973 | #endif |
| 1974 | }, |
| 1975 | { |
| 1976 | AArch64_CMNww_uxtb, ARM64_INS_CMN, |
| 1977 | #ifndef CAPSTONE_DIET |
| 1978 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1979 | #endif |
| 1980 | }, |
| 1981 | { |
| 1982 | AArch64_CMNww_uxth, ARM64_INS_CMN, |
| 1983 | #ifndef CAPSTONE_DIET |
| 1984 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1985 | #endif |
| 1986 | }, |
| 1987 | { |
| 1988 | AArch64_CMNww_uxtw, ARM64_INS_CMN, |
| 1989 | #ifndef CAPSTONE_DIET |
| 1990 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1991 | #endif |
| 1992 | }, |
| 1993 | { |
| 1994 | AArch64_CMNww_uxtx, ARM64_INS_CMN, |
| 1995 | #ifndef CAPSTONE_DIET |
| 1996 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 1997 | #endif |
| 1998 | }, |
| 1999 | { |
| 2000 | AArch64_CMNxw_sxtb, ARM64_INS_CMN, |
| 2001 | #ifndef CAPSTONE_DIET |
| 2002 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2003 | #endif |
| 2004 | }, |
| 2005 | { |
| 2006 | AArch64_CMNxw_sxth, ARM64_INS_CMN, |
| 2007 | #ifndef CAPSTONE_DIET |
| 2008 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2009 | #endif |
| 2010 | }, |
| 2011 | { |
| 2012 | AArch64_CMNxw_sxtw, ARM64_INS_CMN, |
| 2013 | #ifndef CAPSTONE_DIET |
| 2014 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2015 | #endif |
| 2016 | }, |
| 2017 | { |
| 2018 | AArch64_CMNxw_uxtb, ARM64_INS_CMN, |
| 2019 | #ifndef CAPSTONE_DIET |
| 2020 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2021 | #endif |
| 2022 | }, |
| 2023 | { |
| 2024 | AArch64_CMNxw_uxth, ARM64_INS_CMN, |
| 2025 | #ifndef CAPSTONE_DIET |
| 2026 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2027 | #endif |
| 2028 | }, |
| 2029 | { |
| 2030 | AArch64_CMNxw_uxtw, ARM64_INS_CMN, |
| 2031 | #ifndef CAPSTONE_DIET |
| 2032 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2033 | #endif |
| 2034 | }, |
| 2035 | { |
| 2036 | AArch64_CMNxx_asr, ARM64_INS_CMN, |
| 2037 | #ifndef CAPSTONE_DIET |
| 2038 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2039 | #endif |
| 2040 | }, |
| 2041 | { |
| 2042 | AArch64_CMNxx_lsl, ARM64_INS_CMN, |
| 2043 | #ifndef CAPSTONE_DIET |
| 2044 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2045 | #endif |
| 2046 | }, |
| 2047 | { |
| 2048 | AArch64_CMNxx_lsr, ARM64_INS_CMN, |
| 2049 | #ifndef CAPSTONE_DIET |
| 2050 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2051 | #endif |
| 2052 | }, |
| 2053 | { |
| 2054 | AArch64_CMNxx_sxtx, ARM64_INS_CMN, |
| 2055 | #ifndef CAPSTONE_DIET |
| 2056 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2057 | #endif |
| 2058 | }, |
| 2059 | { |
| 2060 | AArch64_CMNxx_uxtx, ARM64_INS_CMN, |
| 2061 | #ifndef CAPSTONE_DIET |
| 2062 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2063 | #endif |
| 2064 | }, |
| 2065 | { |
| 2066 | AArch64_CMPww_asr, ARM64_INS_CMP, |
| 2067 | #ifndef CAPSTONE_DIET |
| 2068 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2069 | #endif |
| 2070 | }, |
| 2071 | { |
| 2072 | AArch64_CMPww_lsl, ARM64_INS_CMP, |
| 2073 | #ifndef CAPSTONE_DIET |
| 2074 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2075 | #endif |
| 2076 | }, |
| 2077 | { |
| 2078 | AArch64_CMPww_lsr, ARM64_INS_CMP, |
| 2079 | #ifndef CAPSTONE_DIET |
| 2080 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2081 | #endif |
| 2082 | }, |
| 2083 | { |
| 2084 | AArch64_CMPww_sxtb, ARM64_INS_CMP, |
| 2085 | #ifndef CAPSTONE_DIET |
| 2086 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2087 | #endif |
| 2088 | }, |
| 2089 | { |
| 2090 | AArch64_CMPww_sxth, ARM64_INS_CMP, |
| 2091 | #ifndef CAPSTONE_DIET |
| 2092 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2093 | #endif |
| 2094 | }, |
| 2095 | { |
| 2096 | AArch64_CMPww_sxtw, ARM64_INS_CMP, |
| 2097 | #ifndef CAPSTONE_DIET |
| 2098 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2099 | #endif |
| 2100 | }, |
| 2101 | { |
| 2102 | AArch64_CMPww_sxtx, ARM64_INS_CMP, |
| 2103 | #ifndef CAPSTONE_DIET |
| 2104 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2105 | #endif |
| 2106 | }, |
| 2107 | { |
| 2108 | AArch64_CMPww_uxtb, ARM64_INS_CMP, |
| 2109 | #ifndef CAPSTONE_DIET |
| 2110 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2111 | #endif |
| 2112 | }, |
| 2113 | { |
| 2114 | AArch64_CMPww_uxth, ARM64_INS_CMP, |
| 2115 | #ifndef CAPSTONE_DIET |
| 2116 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2117 | #endif |
| 2118 | }, |
| 2119 | { |
| 2120 | AArch64_CMPww_uxtw, ARM64_INS_CMP, |
| 2121 | #ifndef CAPSTONE_DIET |
| 2122 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2123 | #endif |
| 2124 | }, |
| 2125 | { |
| 2126 | AArch64_CMPww_uxtx, ARM64_INS_CMP, |
| 2127 | #ifndef CAPSTONE_DIET |
| 2128 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2129 | #endif |
| 2130 | }, |
| 2131 | { |
| 2132 | AArch64_CMPxw_sxtb, ARM64_INS_CMP, |
| 2133 | #ifndef CAPSTONE_DIET |
| 2134 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2135 | #endif |
| 2136 | }, |
| 2137 | { |
| 2138 | AArch64_CMPxw_sxth, ARM64_INS_CMP, |
| 2139 | #ifndef CAPSTONE_DIET |
| 2140 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2141 | #endif |
| 2142 | }, |
| 2143 | { |
| 2144 | AArch64_CMPxw_sxtw, ARM64_INS_CMP, |
| 2145 | #ifndef CAPSTONE_DIET |
| 2146 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2147 | #endif |
| 2148 | }, |
| 2149 | { |
| 2150 | AArch64_CMPxw_uxtb, ARM64_INS_CMP, |
| 2151 | #ifndef CAPSTONE_DIET |
| 2152 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2153 | #endif |
| 2154 | }, |
| 2155 | { |
| 2156 | AArch64_CMPxw_uxth, ARM64_INS_CMP, |
| 2157 | #ifndef CAPSTONE_DIET |
| 2158 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2159 | #endif |
| 2160 | }, |
| 2161 | { |
| 2162 | AArch64_CMPxw_uxtw, ARM64_INS_CMP, |
| 2163 | #ifndef CAPSTONE_DIET |
| 2164 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2165 | #endif |
| 2166 | }, |
| 2167 | { |
| 2168 | AArch64_CMPxx_asr, ARM64_INS_CMP, |
| 2169 | #ifndef CAPSTONE_DIET |
| 2170 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2171 | #endif |
| 2172 | }, |
| 2173 | { |
| 2174 | AArch64_CMPxx_lsl, ARM64_INS_CMP, |
| 2175 | #ifndef CAPSTONE_DIET |
| 2176 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2177 | #endif |
| 2178 | }, |
| 2179 | { |
| 2180 | AArch64_CMPxx_lsr, ARM64_INS_CMP, |
| 2181 | #ifndef CAPSTONE_DIET |
| 2182 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2183 | #endif |
| 2184 | }, |
| 2185 | { |
| 2186 | AArch64_CMPxx_sxtx, ARM64_INS_CMP, |
| 2187 | #ifndef CAPSTONE_DIET |
| 2188 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2189 | #endif |
| 2190 | }, |
| 2191 | { |
| 2192 | AArch64_CMPxx_uxtx, ARM64_INS_CMP, |
| 2193 | #ifndef CAPSTONE_DIET |
| 2194 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 2195 | #endif |
| 2196 | }, |
| 2197 | { |
| 2198 | AArch64_CMTSTddd, ARM64_INS_CMTST, |
| 2199 | #ifndef CAPSTONE_DIET |
| 2200 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2201 | #endif |
| 2202 | }, |
| 2203 | { |
| 2204 | AArch64_CMTSTvvv_16B, ARM64_INS_CMTST, |
| 2205 | #ifndef CAPSTONE_DIET |
| 2206 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2207 | #endif |
| 2208 | }, |
| 2209 | { |
| 2210 | AArch64_CMTSTvvv_2D, ARM64_INS_CMTST, |
| 2211 | #ifndef CAPSTONE_DIET |
| 2212 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2213 | #endif |
| 2214 | }, |
| 2215 | { |
| 2216 | AArch64_CMTSTvvv_2S, ARM64_INS_CMTST, |
| 2217 | #ifndef CAPSTONE_DIET |
| 2218 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2219 | #endif |
| 2220 | }, |
| 2221 | { |
| 2222 | AArch64_CMTSTvvv_4H, ARM64_INS_CMTST, |
| 2223 | #ifndef CAPSTONE_DIET |
| 2224 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2225 | #endif |
| 2226 | }, |
| 2227 | { |
| 2228 | AArch64_CMTSTvvv_4S, ARM64_INS_CMTST, |
| 2229 | #ifndef CAPSTONE_DIET |
| 2230 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2231 | #endif |
| 2232 | }, |
| 2233 | { |
| 2234 | AArch64_CMTSTvvv_8B, ARM64_INS_CMTST, |
| 2235 | #ifndef CAPSTONE_DIET |
| 2236 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2237 | #endif |
| 2238 | }, |
| 2239 | { |
| 2240 | AArch64_CMTSTvvv_8H, ARM64_INS_CMTST, |
| 2241 | #ifndef CAPSTONE_DIET |
| 2242 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2243 | #endif |
| 2244 | }, |
| 2245 | { |
| 2246 | AArch64_CNT16b, ARM64_INS_CNT, |
| 2247 | #ifndef CAPSTONE_DIET |
| 2248 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2249 | #endif |
| 2250 | }, |
| 2251 | { |
| 2252 | AArch64_CNT8b, ARM64_INS_CNT, |
| 2253 | #ifndef CAPSTONE_DIET |
| 2254 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2255 | #endif |
| 2256 | }, |
| 2257 | { |
| 2258 | AArch64_CRC32B_www, ARM64_INS_CRC32B, |
| 2259 | #ifndef CAPSTONE_DIET |
| 2260 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2261 | #endif |
| 2262 | }, |
| 2263 | { |
| 2264 | AArch64_CRC32CB_www, ARM64_INS_CRC32CB, |
| 2265 | #ifndef CAPSTONE_DIET |
| 2266 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2267 | #endif |
| 2268 | }, |
| 2269 | { |
| 2270 | AArch64_CRC32CH_www, ARM64_INS_CRC32CH, |
| 2271 | #ifndef CAPSTONE_DIET |
| 2272 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2273 | #endif |
| 2274 | }, |
| 2275 | { |
| 2276 | AArch64_CRC32CW_www, ARM64_INS_CRC32CW, |
| 2277 | #ifndef CAPSTONE_DIET |
| 2278 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2279 | #endif |
| 2280 | }, |
| 2281 | { |
| 2282 | AArch64_CRC32CX_wwx, ARM64_INS_CRC32CX, |
| 2283 | #ifndef CAPSTONE_DIET |
| 2284 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2285 | #endif |
| 2286 | }, |
| 2287 | { |
| 2288 | AArch64_CRC32H_www, ARM64_INS_CRC32H, |
| 2289 | #ifndef CAPSTONE_DIET |
| 2290 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2291 | #endif |
| 2292 | }, |
| 2293 | { |
| 2294 | AArch64_CRC32W_www, ARM64_INS_CRC32W, |
| 2295 | #ifndef CAPSTONE_DIET |
| 2296 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2297 | #endif |
| 2298 | }, |
| 2299 | { |
| 2300 | AArch64_CRC32X_wwx, ARM64_INS_CRC32X, |
| 2301 | #ifndef CAPSTONE_DIET |
| 2302 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2303 | #endif |
| 2304 | }, |
| 2305 | { |
| 2306 | AArch64_CSELwwwc, ARM64_INS_CSEL, |
| 2307 | #ifndef CAPSTONE_DIET |
| 2308 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 2309 | #endif |
| 2310 | }, |
| 2311 | { |
| 2312 | AArch64_CSELxxxc, ARM64_INS_CSEL, |
| 2313 | #ifndef CAPSTONE_DIET |
| 2314 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 2315 | #endif |
| 2316 | }, |
| 2317 | { |
| 2318 | AArch64_CSINCwwwc, ARM64_INS_CSINC, |
| 2319 | #ifndef CAPSTONE_DIET |
| 2320 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 2321 | #endif |
| 2322 | }, |
| 2323 | { |
| 2324 | AArch64_CSINCxxxc, ARM64_INS_CSINC, |
| 2325 | #ifndef CAPSTONE_DIET |
| 2326 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 2327 | #endif |
| 2328 | }, |
| 2329 | { |
| 2330 | AArch64_CSINVwwwc, ARM64_INS_CSINV, |
| 2331 | #ifndef CAPSTONE_DIET |
| 2332 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 2333 | #endif |
| 2334 | }, |
| 2335 | { |
| 2336 | AArch64_CSINVxxxc, ARM64_INS_CSINV, |
| 2337 | #ifndef CAPSTONE_DIET |
| 2338 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 2339 | #endif |
| 2340 | }, |
| 2341 | { |
| 2342 | AArch64_CSNEGwwwc, ARM64_INS_CSNEG, |
| 2343 | #ifndef CAPSTONE_DIET |
| 2344 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 2345 | #endif |
| 2346 | }, |
| 2347 | { |
| 2348 | AArch64_CSNEGxxxc, ARM64_INS_CSNEG, |
| 2349 | #ifndef CAPSTONE_DIET |
| 2350 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 2351 | #endif |
| 2352 | }, |
| 2353 | { |
| 2354 | AArch64_DCPS1i, ARM64_INS_DCPS1, |
| 2355 | #ifndef CAPSTONE_DIET |
| 2356 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 2357 | #endif |
| 2358 | }, |
| 2359 | { |
| 2360 | AArch64_DCPS2i, ARM64_INS_DCPS2, |
| 2361 | #ifndef CAPSTONE_DIET |
| 2362 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 2363 | #endif |
| 2364 | }, |
| 2365 | { |
| 2366 | AArch64_DCPS3i, ARM64_INS_DCPS3, |
| 2367 | #ifndef CAPSTONE_DIET |
| 2368 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 2369 | #endif |
| 2370 | }, |
| 2371 | { |
| 2372 | AArch64_DCix, ARM64_INS_DC, |
| 2373 | #ifndef CAPSTONE_DIET |
| 2374 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2375 | #endif |
| 2376 | }, |
| 2377 | { |
| 2378 | AArch64_DMBi, ARM64_INS_DMB, |
| 2379 | #ifndef CAPSTONE_DIET |
| 2380 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2381 | #endif |
| 2382 | }, |
| 2383 | { |
| 2384 | AArch64_DRPS, ARM64_INS_DRPS, |
| 2385 | #ifndef CAPSTONE_DIET |
| 2386 | { 0 }, { 0 }, { 0 }, 1, 1 |
| 2387 | #endif |
| 2388 | }, |
| 2389 | { |
| 2390 | AArch64_DSBi, ARM64_INS_DSB, |
| 2391 | #ifndef CAPSTONE_DIET |
| 2392 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2393 | #endif |
| 2394 | }, |
| 2395 | { |
| 2396 | AArch64_DUP16b, ARM64_INS_DUP, |
| 2397 | #ifndef CAPSTONE_DIET |
| 2398 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2399 | #endif |
| 2400 | }, |
| 2401 | { |
| 2402 | AArch64_DUP2d, ARM64_INS_DUP, |
| 2403 | #ifndef CAPSTONE_DIET |
| 2404 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2405 | #endif |
| 2406 | }, |
| 2407 | { |
| 2408 | AArch64_DUP2s, ARM64_INS_DUP, |
| 2409 | #ifndef CAPSTONE_DIET |
| 2410 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2411 | #endif |
| 2412 | }, |
| 2413 | { |
| 2414 | AArch64_DUP4h, ARM64_INS_DUP, |
| 2415 | #ifndef CAPSTONE_DIET |
| 2416 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2417 | #endif |
| 2418 | }, |
| 2419 | { |
| 2420 | AArch64_DUP4s, ARM64_INS_DUP, |
| 2421 | #ifndef CAPSTONE_DIET |
| 2422 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2423 | #endif |
| 2424 | }, |
| 2425 | { |
| 2426 | AArch64_DUP8b, ARM64_INS_DUP, |
| 2427 | #ifndef CAPSTONE_DIET |
| 2428 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2429 | #endif |
| 2430 | }, |
| 2431 | { |
| 2432 | AArch64_DUP8h, ARM64_INS_DUP, |
| 2433 | #ifndef CAPSTONE_DIET |
| 2434 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2435 | #endif |
| 2436 | }, |
| 2437 | { |
| 2438 | AArch64_DUPELT16b, ARM64_INS_DUP, |
| 2439 | #ifndef CAPSTONE_DIET |
| 2440 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2441 | #endif |
| 2442 | }, |
| 2443 | { |
| 2444 | AArch64_DUPELT2d, ARM64_INS_DUP, |
| 2445 | #ifndef CAPSTONE_DIET |
| 2446 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2447 | #endif |
| 2448 | }, |
| 2449 | { |
| 2450 | AArch64_DUPELT2s, ARM64_INS_DUP, |
| 2451 | #ifndef CAPSTONE_DIET |
| 2452 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2453 | #endif |
| 2454 | }, |
| 2455 | { |
| 2456 | AArch64_DUPELT4h, ARM64_INS_DUP, |
| 2457 | #ifndef CAPSTONE_DIET |
| 2458 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2459 | #endif |
| 2460 | }, |
| 2461 | { |
| 2462 | AArch64_DUPELT4s, ARM64_INS_DUP, |
| 2463 | #ifndef CAPSTONE_DIET |
| 2464 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2465 | #endif |
| 2466 | }, |
| 2467 | { |
| 2468 | AArch64_DUPELT8b, ARM64_INS_DUP, |
| 2469 | #ifndef CAPSTONE_DIET |
| 2470 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2471 | #endif |
| 2472 | }, |
| 2473 | { |
| 2474 | AArch64_DUPELT8h, ARM64_INS_DUP, |
| 2475 | #ifndef CAPSTONE_DIET |
| 2476 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2477 | #endif |
| 2478 | }, |
| 2479 | { |
| 2480 | AArch64_DUPbv_B, ARM64_INS_DUP, |
| 2481 | #ifndef CAPSTONE_DIET |
| 2482 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2483 | #endif |
| 2484 | }, |
| 2485 | { |
| 2486 | AArch64_DUPdv_D, ARM64_INS_DUP, |
| 2487 | #ifndef CAPSTONE_DIET |
| 2488 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2489 | #endif |
| 2490 | }, |
| 2491 | { |
| 2492 | AArch64_DUPhv_H, ARM64_INS_DUP, |
| 2493 | #ifndef CAPSTONE_DIET |
| 2494 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2495 | #endif |
| 2496 | }, |
| 2497 | { |
| 2498 | AArch64_DUPsv_S, ARM64_INS_DUP, |
| 2499 | #ifndef CAPSTONE_DIET |
| 2500 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2501 | #endif |
| 2502 | }, |
| 2503 | { |
| 2504 | AArch64_EONwww_asr, ARM64_INS_EON, |
| 2505 | #ifndef CAPSTONE_DIET |
| 2506 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2507 | #endif |
| 2508 | }, |
| 2509 | { |
| 2510 | AArch64_EONwww_lsl, ARM64_INS_EON, |
| 2511 | #ifndef CAPSTONE_DIET |
| 2512 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2513 | #endif |
| 2514 | }, |
| 2515 | { |
| 2516 | AArch64_EONwww_lsr, ARM64_INS_EON, |
| 2517 | #ifndef CAPSTONE_DIET |
| 2518 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2519 | #endif |
| 2520 | }, |
| 2521 | { |
| 2522 | AArch64_EONwww_ror, ARM64_INS_EON, |
| 2523 | #ifndef CAPSTONE_DIET |
| 2524 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2525 | #endif |
| 2526 | }, |
| 2527 | { |
| 2528 | AArch64_EONxxx_asr, ARM64_INS_EON, |
| 2529 | #ifndef CAPSTONE_DIET |
| 2530 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2531 | #endif |
| 2532 | }, |
| 2533 | { |
| 2534 | AArch64_EONxxx_lsl, ARM64_INS_EON, |
| 2535 | #ifndef CAPSTONE_DIET |
| 2536 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2537 | #endif |
| 2538 | }, |
| 2539 | { |
| 2540 | AArch64_EONxxx_lsr, ARM64_INS_EON, |
| 2541 | #ifndef CAPSTONE_DIET |
| 2542 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2543 | #endif |
| 2544 | }, |
| 2545 | { |
| 2546 | AArch64_EONxxx_ror, ARM64_INS_EON, |
| 2547 | #ifndef CAPSTONE_DIET |
| 2548 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2549 | #endif |
| 2550 | }, |
| 2551 | { |
| 2552 | AArch64_EORvvv_16B, ARM64_INS_EOR, |
| 2553 | #ifndef CAPSTONE_DIET |
| 2554 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2555 | #endif |
| 2556 | }, |
| 2557 | { |
| 2558 | AArch64_EORvvv_8B, ARM64_INS_EOR, |
| 2559 | #ifndef CAPSTONE_DIET |
| 2560 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2561 | #endif |
| 2562 | }, |
| 2563 | { |
| 2564 | AArch64_EORwwi, ARM64_INS_EOR, |
| 2565 | #ifndef CAPSTONE_DIET |
| 2566 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2567 | #endif |
| 2568 | }, |
| 2569 | { |
| 2570 | AArch64_EORwww_asr, ARM64_INS_EOR, |
| 2571 | #ifndef CAPSTONE_DIET |
| 2572 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2573 | #endif |
| 2574 | }, |
| 2575 | { |
| 2576 | AArch64_EORwww_lsl, ARM64_INS_EOR, |
| 2577 | #ifndef CAPSTONE_DIET |
| 2578 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2579 | #endif |
| 2580 | }, |
| 2581 | { |
| 2582 | AArch64_EORwww_lsr, ARM64_INS_EOR, |
| 2583 | #ifndef CAPSTONE_DIET |
| 2584 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2585 | #endif |
| 2586 | }, |
| 2587 | { |
| 2588 | AArch64_EORwww_ror, ARM64_INS_EOR, |
| 2589 | #ifndef CAPSTONE_DIET |
| 2590 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2591 | #endif |
| 2592 | }, |
| 2593 | { |
| 2594 | AArch64_EORxxi, ARM64_INS_EOR, |
| 2595 | #ifndef CAPSTONE_DIET |
| 2596 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2597 | #endif |
| 2598 | }, |
| 2599 | { |
| 2600 | AArch64_EORxxx_asr, ARM64_INS_EOR, |
| 2601 | #ifndef CAPSTONE_DIET |
| 2602 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2603 | #endif |
| 2604 | }, |
| 2605 | { |
| 2606 | AArch64_EORxxx_lsl, ARM64_INS_EOR, |
| 2607 | #ifndef CAPSTONE_DIET |
| 2608 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2609 | #endif |
| 2610 | }, |
| 2611 | { |
| 2612 | AArch64_EORxxx_lsr, ARM64_INS_EOR, |
| 2613 | #ifndef CAPSTONE_DIET |
| 2614 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2615 | #endif |
| 2616 | }, |
| 2617 | { |
| 2618 | AArch64_EORxxx_ror, ARM64_INS_EOR, |
| 2619 | #ifndef CAPSTONE_DIET |
| 2620 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2621 | #endif |
| 2622 | }, |
| 2623 | { |
| 2624 | AArch64_ERET, ARM64_INS_ERET, |
| 2625 | #ifndef CAPSTONE_DIET |
| 2626 | { 0 }, { 0 }, { 0 }, 1, 1 |
| 2627 | #endif |
| 2628 | }, |
| 2629 | { |
| 2630 | AArch64_EXTRwwwi, ARM64_INS_EXTR, |
| 2631 | #ifndef CAPSTONE_DIET |
| 2632 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2633 | #endif |
| 2634 | }, |
| 2635 | { |
| 2636 | AArch64_EXTRxxxi, ARM64_INS_EXTR, |
| 2637 | #ifndef CAPSTONE_DIET |
| 2638 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 2639 | #endif |
| 2640 | }, |
| 2641 | { |
| 2642 | AArch64_EXTvvvi_16b, ARM64_INS_EXT, |
| 2643 | #ifndef CAPSTONE_DIET |
| 2644 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2645 | #endif |
| 2646 | }, |
| 2647 | { |
| 2648 | AArch64_EXTvvvi_8b, ARM64_INS_EXT, |
| 2649 | #ifndef CAPSTONE_DIET |
| 2650 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2651 | #endif |
| 2652 | }, |
| 2653 | { |
| 2654 | AArch64_FABDddd, ARM64_INS_FABD, |
| 2655 | #ifndef CAPSTONE_DIET |
| 2656 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2657 | #endif |
| 2658 | }, |
| 2659 | { |
| 2660 | AArch64_FABDsss, ARM64_INS_FABD, |
| 2661 | #ifndef CAPSTONE_DIET |
| 2662 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2663 | #endif |
| 2664 | }, |
| 2665 | { |
| 2666 | AArch64_FABDvvv_2D, ARM64_INS_FABD, |
| 2667 | #ifndef CAPSTONE_DIET |
| 2668 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2669 | #endif |
| 2670 | }, |
| 2671 | { |
| 2672 | AArch64_FABDvvv_2S, ARM64_INS_FABD, |
| 2673 | #ifndef CAPSTONE_DIET |
| 2674 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2675 | #endif |
| 2676 | }, |
| 2677 | { |
| 2678 | AArch64_FABDvvv_4S, ARM64_INS_FABD, |
| 2679 | #ifndef CAPSTONE_DIET |
| 2680 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2681 | #endif |
| 2682 | }, |
| 2683 | { |
| 2684 | AArch64_FABS2d, ARM64_INS_FABS, |
| 2685 | #ifndef CAPSTONE_DIET |
| 2686 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2687 | #endif |
| 2688 | }, |
| 2689 | { |
| 2690 | AArch64_FABS2s, ARM64_INS_FABS, |
| 2691 | #ifndef CAPSTONE_DIET |
| 2692 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2693 | #endif |
| 2694 | }, |
| 2695 | { |
| 2696 | AArch64_FABS4s, ARM64_INS_FABS, |
| 2697 | #ifndef CAPSTONE_DIET |
| 2698 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2699 | #endif |
| 2700 | }, |
| 2701 | { |
| 2702 | AArch64_FABSdd, ARM64_INS_FABS, |
| 2703 | #ifndef CAPSTONE_DIET |
| 2704 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 2705 | #endif |
| 2706 | }, |
| 2707 | { |
| 2708 | AArch64_FABSss, ARM64_INS_FABS, |
| 2709 | #ifndef CAPSTONE_DIET |
| 2710 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 2711 | #endif |
| 2712 | }, |
| 2713 | { |
| 2714 | AArch64_FACGEddd, ARM64_INS_FACGE, |
| 2715 | #ifndef CAPSTONE_DIET |
| 2716 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2717 | #endif |
| 2718 | }, |
| 2719 | { |
| 2720 | AArch64_FACGEsss, ARM64_INS_FACGE, |
| 2721 | #ifndef CAPSTONE_DIET |
| 2722 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2723 | #endif |
| 2724 | }, |
| 2725 | { |
| 2726 | AArch64_FACGEvvv_2D, ARM64_INS_FACGE, |
| 2727 | #ifndef CAPSTONE_DIET |
| 2728 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2729 | #endif |
| 2730 | }, |
| 2731 | { |
| 2732 | AArch64_FACGEvvv_2S, ARM64_INS_FACGE, |
| 2733 | #ifndef CAPSTONE_DIET |
| 2734 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2735 | #endif |
| 2736 | }, |
| 2737 | { |
| 2738 | AArch64_FACGEvvv_4S, ARM64_INS_FACGE, |
| 2739 | #ifndef CAPSTONE_DIET |
| 2740 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2741 | #endif |
| 2742 | }, |
| 2743 | { |
| 2744 | AArch64_FACGTddd, ARM64_INS_FACGT, |
| 2745 | #ifndef CAPSTONE_DIET |
| 2746 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2747 | #endif |
| 2748 | }, |
| 2749 | { |
| 2750 | AArch64_FACGTsss, ARM64_INS_FACGT, |
| 2751 | #ifndef CAPSTONE_DIET |
| 2752 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2753 | #endif |
| 2754 | }, |
| 2755 | { |
| 2756 | AArch64_FACGTvvv_2D, ARM64_INS_FACGT, |
| 2757 | #ifndef CAPSTONE_DIET |
| 2758 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2759 | #endif |
| 2760 | }, |
| 2761 | { |
| 2762 | AArch64_FACGTvvv_2S, ARM64_INS_FACGT, |
| 2763 | #ifndef CAPSTONE_DIET |
| 2764 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2765 | #endif |
| 2766 | }, |
| 2767 | { |
| 2768 | AArch64_FACGTvvv_4S, ARM64_INS_FACGT, |
| 2769 | #ifndef CAPSTONE_DIET |
| 2770 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2771 | #endif |
| 2772 | }, |
| 2773 | { |
| 2774 | AArch64_FADDP_2D, ARM64_INS_FADDP, |
| 2775 | #ifndef CAPSTONE_DIET |
| 2776 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2777 | #endif |
| 2778 | }, |
| 2779 | { |
| 2780 | AArch64_FADDP_2S, ARM64_INS_FADDP, |
| 2781 | #ifndef CAPSTONE_DIET |
| 2782 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2783 | #endif |
| 2784 | }, |
| 2785 | { |
| 2786 | AArch64_FADDP_4S, ARM64_INS_FADDP, |
| 2787 | #ifndef CAPSTONE_DIET |
| 2788 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2789 | #endif |
| 2790 | }, |
| 2791 | { |
| 2792 | AArch64_FADDPvv_D_2D, ARM64_INS_FADDP, |
| 2793 | #ifndef CAPSTONE_DIET |
| 2794 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2795 | #endif |
| 2796 | }, |
| 2797 | { |
| 2798 | AArch64_FADDPvv_S_2S, ARM64_INS_FADDP, |
| 2799 | #ifndef CAPSTONE_DIET |
| 2800 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2801 | #endif |
| 2802 | }, |
| 2803 | { |
| 2804 | AArch64_FADDddd, ARM64_INS_FADD, |
| 2805 | #ifndef CAPSTONE_DIET |
| 2806 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 2807 | #endif |
| 2808 | }, |
| 2809 | { |
| 2810 | AArch64_FADDsss, ARM64_INS_FADD, |
| 2811 | #ifndef CAPSTONE_DIET |
| 2812 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 2813 | #endif |
| 2814 | }, |
| 2815 | { |
| 2816 | AArch64_FADDvvv_2D, ARM64_INS_FADD, |
| 2817 | #ifndef CAPSTONE_DIET |
| 2818 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2819 | #endif |
| 2820 | }, |
| 2821 | { |
| 2822 | AArch64_FADDvvv_2S, ARM64_INS_FADD, |
| 2823 | #ifndef CAPSTONE_DIET |
| 2824 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2825 | #endif |
| 2826 | }, |
| 2827 | { |
| 2828 | AArch64_FADDvvv_4S, ARM64_INS_FADD, |
| 2829 | #ifndef CAPSTONE_DIET |
| 2830 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2831 | #endif |
| 2832 | }, |
| 2833 | { |
| 2834 | AArch64_FCCMPEdd, ARM64_INS_FCCMPE, |
| 2835 | #ifndef CAPSTONE_DIET |
| 2836 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 2837 | #endif |
| 2838 | }, |
| 2839 | { |
| 2840 | AArch64_FCCMPEss, ARM64_INS_FCCMPE, |
| 2841 | #ifndef CAPSTONE_DIET |
| 2842 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 2843 | #endif |
| 2844 | }, |
| 2845 | { |
| 2846 | AArch64_FCCMPdd, ARM64_INS_FCCMP, |
| 2847 | #ifndef CAPSTONE_DIET |
| 2848 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 2849 | #endif |
| 2850 | }, |
| 2851 | { |
| 2852 | AArch64_FCCMPss, ARM64_INS_FCCMP, |
| 2853 | #ifndef CAPSTONE_DIET |
| 2854 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 2855 | #endif |
| 2856 | }, |
| 2857 | { |
| 2858 | AArch64_FCMEQZddi, ARM64_INS_FCMEQ, |
| 2859 | #ifndef CAPSTONE_DIET |
| 2860 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2861 | #endif |
| 2862 | }, |
| 2863 | { |
| 2864 | AArch64_FCMEQZssi, ARM64_INS_FCMEQ, |
| 2865 | #ifndef CAPSTONE_DIET |
| 2866 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2867 | #endif |
| 2868 | }, |
| 2869 | { |
| 2870 | AArch64_FCMEQddd, ARM64_INS_FCMEQ, |
| 2871 | #ifndef CAPSTONE_DIET |
| 2872 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2873 | #endif |
| 2874 | }, |
| 2875 | { |
| 2876 | AArch64_FCMEQsss, ARM64_INS_FCMEQ, |
| 2877 | #ifndef CAPSTONE_DIET |
| 2878 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2879 | #endif |
| 2880 | }, |
| 2881 | { |
| 2882 | AArch64_FCMEQvvi_2D, ARM64_INS_FCMEQ, |
| 2883 | #ifndef CAPSTONE_DIET |
| 2884 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2885 | #endif |
| 2886 | }, |
| 2887 | { |
| 2888 | AArch64_FCMEQvvi_2S, ARM64_INS_FCMEQ, |
| 2889 | #ifndef CAPSTONE_DIET |
| 2890 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2891 | #endif |
| 2892 | }, |
| 2893 | { |
| 2894 | AArch64_FCMEQvvi_4S, ARM64_INS_FCMEQ, |
| 2895 | #ifndef CAPSTONE_DIET |
| 2896 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2897 | #endif |
| 2898 | }, |
| 2899 | { |
| 2900 | AArch64_FCMEQvvv_2D, ARM64_INS_FCMEQ, |
| 2901 | #ifndef CAPSTONE_DIET |
| 2902 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2903 | #endif |
| 2904 | }, |
| 2905 | { |
| 2906 | AArch64_FCMEQvvv_2S, ARM64_INS_FCMEQ, |
| 2907 | #ifndef CAPSTONE_DIET |
| 2908 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2909 | #endif |
| 2910 | }, |
| 2911 | { |
| 2912 | AArch64_FCMEQvvv_4S, ARM64_INS_FCMEQ, |
| 2913 | #ifndef CAPSTONE_DIET |
| 2914 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2915 | #endif |
| 2916 | }, |
| 2917 | { |
| 2918 | AArch64_FCMGEZddi, ARM64_INS_FCMGE, |
| 2919 | #ifndef CAPSTONE_DIET |
| 2920 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2921 | #endif |
| 2922 | }, |
| 2923 | { |
| 2924 | AArch64_FCMGEZssi, ARM64_INS_FCMGE, |
| 2925 | #ifndef CAPSTONE_DIET |
| 2926 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2927 | #endif |
| 2928 | }, |
| 2929 | { |
| 2930 | AArch64_FCMGEddd, ARM64_INS_FCMGE, |
| 2931 | #ifndef CAPSTONE_DIET |
| 2932 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2933 | #endif |
| 2934 | }, |
| 2935 | { |
| 2936 | AArch64_FCMGEsss, ARM64_INS_FCMGE, |
| 2937 | #ifndef CAPSTONE_DIET |
| 2938 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2939 | #endif |
| 2940 | }, |
| 2941 | { |
| 2942 | AArch64_FCMGEvvi_2D, ARM64_INS_FCMGE, |
| 2943 | #ifndef CAPSTONE_DIET |
| 2944 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2945 | #endif |
| 2946 | }, |
| 2947 | { |
| 2948 | AArch64_FCMGEvvi_2S, ARM64_INS_FCMGE, |
| 2949 | #ifndef CAPSTONE_DIET |
| 2950 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2951 | #endif |
| 2952 | }, |
| 2953 | { |
| 2954 | AArch64_FCMGEvvi_4S, ARM64_INS_FCMGE, |
| 2955 | #ifndef CAPSTONE_DIET |
| 2956 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2957 | #endif |
| 2958 | }, |
| 2959 | { |
| 2960 | AArch64_FCMGEvvv_2D, ARM64_INS_FCMGE, |
| 2961 | #ifndef CAPSTONE_DIET |
| 2962 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2963 | #endif |
| 2964 | }, |
| 2965 | { |
| 2966 | AArch64_FCMGEvvv_2S, ARM64_INS_FCMGE, |
| 2967 | #ifndef CAPSTONE_DIET |
| 2968 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2969 | #endif |
| 2970 | }, |
| 2971 | { |
| 2972 | AArch64_FCMGEvvv_4S, ARM64_INS_FCMGE, |
| 2973 | #ifndef CAPSTONE_DIET |
| 2974 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2975 | #endif |
| 2976 | }, |
| 2977 | { |
| 2978 | AArch64_FCMGTZddi, ARM64_INS_FCMGT, |
| 2979 | #ifndef CAPSTONE_DIET |
| 2980 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2981 | #endif |
| 2982 | }, |
| 2983 | { |
| 2984 | AArch64_FCMGTZssi, ARM64_INS_FCMGT, |
| 2985 | #ifndef CAPSTONE_DIET |
| 2986 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2987 | #endif |
| 2988 | }, |
| 2989 | { |
| 2990 | AArch64_FCMGTddd, ARM64_INS_FCMGT, |
| 2991 | #ifndef CAPSTONE_DIET |
| 2992 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2993 | #endif |
| 2994 | }, |
| 2995 | { |
| 2996 | AArch64_FCMGTsss, ARM64_INS_FCMGT, |
| 2997 | #ifndef CAPSTONE_DIET |
| 2998 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 2999 | #endif |
| 3000 | }, |
| 3001 | { |
| 3002 | AArch64_FCMGTvvi_2D, ARM64_INS_FCMGT, |
| 3003 | #ifndef CAPSTONE_DIET |
| 3004 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3005 | #endif |
| 3006 | }, |
| 3007 | { |
| 3008 | AArch64_FCMGTvvi_2S, ARM64_INS_FCMGT, |
| 3009 | #ifndef CAPSTONE_DIET |
| 3010 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3011 | #endif |
| 3012 | }, |
| 3013 | { |
| 3014 | AArch64_FCMGTvvi_4S, ARM64_INS_FCMGT, |
| 3015 | #ifndef CAPSTONE_DIET |
| 3016 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3017 | #endif |
| 3018 | }, |
| 3019 | { |
| 3020 | AArch64_FCMGTvvv_2D, ARM64_INS_FCMGT, |
| 3021 | #ifndef CAPSTONE_DIET |
| 3022 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3023 | #endif |
| 3024 | }, |
| 3025 | { |
| 3026 | AArch64_FCMGTvvv_2S, ARM64_INS_FCMGT, |
| 3027 | #ifndef CAPSTONE_DIET |
| 3028 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3029 | #endif |
| 3030 | }, |
| 3031 | { |
| 3032 | AArch64_FCMGTvvv_4S, ARM64_INS_FCMGT, |
| 3033 | #ifndef CAPSTONE_DIET |
| 3034 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3035 | #endif |
| 3036 | }, |
| 3037 | { |
| 3038 | AArch64_FCMLEZddi, ARM64_INS_FCMLE, |
| 3039 | #ifndef CAPSTONE_DIET |
| 3040 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3041 | #endif |
| 3042 | }, |
| 3043 | { |
| 3044 | AArch64_FCMLEZssi, ARM64_INS_FCMLE, |
| 3045 | #ifndef CAPSTONE_DIET |
| 3046 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3047 | #endif |
| 3048 | }, |
| 3049 | { |
| 3050 | AArch64_FCMLEvvi_2D, ARM64_INS_FCMLE, |
| 3051 | #ifndef CAPSTONE_DIET |
| 3052 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3053 | #endif |
| 3054 | }, |
| 3055 | { |
| 3056 | AArch64_FCMLEvvi_2S, ARM64_INS_FCMLE, |
| 3057 | #ifndef CAPSTONE_DIET |
| 3058 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3059 | #endif |
| 3060 | }, |
| 3061 | { |
| 3062 | AArch64_FCMLEvvi_4S, ARM64_INS_FCMLE, |
| 3063 | #ifndef CAPSTONE_DIET |
| 3064 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3065 | #endif |
| 3066 | }, |
| 3067 | { |
| 3068 | AArch64_FCMLTZddi, ARM64_INS_FCMLT, |
| 3069 | #ifndef CAPSTONE_DIET |
| 3070 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3071 | #endif |
| 3072 | }, |
| 3073 | { |
| 3074 | AArch64_FCMLTZssi, ARM64_INS_FCMLT, |
| 3075 | #ifndef CAPSTONE_DIET |
| 3076 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3077 | #endif |
| 3078 | }, |
| 3079 | { |
| 3080 | AArch64_FCMLTvvi_2D, ARM64_INS_FCMLT, |
| 3081 | #ifndef CAPSTONE_DIET |
| 3082 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3083 | #endif |
| 3084 | }, |
| 3085 | { |
| 3086 | AArch64_FCMLTvvi_2S, ARM64_INS_FCMLT, |
| 3087 | #ifndef CAPSTONE_DIET |
| 3088 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3089 | #endif |
| 3090 | }, |
| 3091 | { |
| 3092 | AArch64_FCMLTvvi_4S, ARM64_INS_FCMLT, |
| 3093 | #ifndef CAPSTONE_DIET |
| 3094 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3095 | #endif |
| 3096 | }, |
| 3097 | { |
| 3098 | AArch64_FCMPdd_quiet, ARM64_INS_FCMP, |
| 3099 | #ifndef CAPSTONE_DIET |
| 3100 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3101 | #endif |
| 3102 | }, |
| 3103 | { |
| 3104 | AArch64_FCMPdd_sig, ARM64_INS_FCMPE, |
| 3105 | #ifndef CAPSTONE_DIET |
| 3106 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3107 | #endif |
| 3108 | }, |
| 3109 | { |
| 3110 | AArch64_FCMPdi_quiet, ARM64_INS_FCMP, |
| 3111 | #ifndef CAPSTONE_DIET |
| 3112 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3113 | #endif |
| 3114 | }, |
| 3115 | { |
| 3116 | AArch64_FCMPdi_sig, ARM64_INS_FCMPE, |
| 3117 | #ifndef CAPSTONE_DIET |
| 3118 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3119 | #endif |
| 3120 | }, |
| 3121 | { |
| 3122 | AArch64_FCMPsi_quiet, ARM64_INS_FCMP, |
| 3123 | #ifndef CAPSTONE_DIET |
| 3124 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3125 | #endif |
| 3126 | }, |
| 3127 | { |
| 3128 | AArch64_FCMPsi_sig, ARM64_INS_FCMPE, |
| 3129 | #ifndef CAPSTONE_DIET |
| 3130 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3131 | #endif |
| 3132 | }, |
| 3133 | { |
| 3134 | AArch64_FCMPss_quiet, ARM64_INS_FCMP, |
| 3135 | #ifndef CAPSTONE_DIET |
| 3136 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3137 | #endif |
| 3138 | }, |
| 3139 | { |
| 3140 | AArch64_FCMPss_sig, ARM64_INS_FCMPE, |
| 3141 | #ifndef CAPSTONE_DIET |
| 3142 | { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3143 | #endif |
| 3144 | }, |
| 3145 | { |
| 3146 | AArch64_FCSELdddc, ARM64_INS_FCSEL, |
| 3147 | #ifndef CAPSTONE_DIET |
| 3148 | { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3149 | #endif |
| 3150 | }, |
| 3151 | { |
| 3152 | AArch64_FCSELsssc, ARM64_INS_FCSEL, |
| 3153 | #ifndef CAPSTONE_DIET |
| 3154 | { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3155 | #endif |
| 3156 | }, |
| 3157 | { |
| 3158 | AArch64_FCVTAS_2d, ARM64_INS_FCVTAS, |
| 3159 | #ifndef CAPSTONE_DIET |
| 3160 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3161 | #endif |
| 3162 | }, |
| 3163 | { |
| 3164 | AArch64_FCVTAS_2s, ARM64_INS_FCVTAS, |
| 3165 | #ifndef CAPSTONE_DIET |
| 3166 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3167 | #endif |
| 3168 | }, |
| 3169 | { |
| 3170 | AArch64_FCVTAS_4s, ARM64_INS_FCVTAS, |
| 3171 | #ifndef CAPSTONE_DIET |
| 3172 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3173 | #endif |
| 3174 | }, |
| 3175 | { |
| 3176 | AArch64_FCVTASdd, ARM64_INS_FCVTAS, |
| 3177 | #ifndef CAPSTONE_DIET |
| 3178 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3179 | #endif |
| 3180 | }, |
| 3181 | { |
| 3182 | AArch64_FCVTASss, ARM64_INS_FCVTAS, |
| 3183 | #ifndef CAPSTONE_DIET |
| 3184 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3185 | #endif |
| 3186 | }, |
| 3187 | { |
| 3188 | AArch64_FCVTASwd, ARM64_INS_FCVTAS, |
| 3189 | #ifndef CAPSTONE_DIET |
| 3190 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3191 | #endif |
| 3192 | }, |
| 3193 | { |
| 3194 | AArch64_FCVTASws, ARM64_INS_FCVTAS, |
| 3195 | #ifndef CAPSTONE_DIET |
| 3196 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3197 | #endif |
| 3198 | }, |
| 3199 | { |
| 3200 | AArch64_FCVTASxd, ARM64_INS_FCVTAS, |
| 3201 | #ifndef CAPSTONE_DIET |
| 3202 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3203 | #endif |
| 3204 | }, |
| 3205 | { |
| 3206 | AArch64_FCVTASxs, ARM64_INS_FCVTAS, |
| 3207 | #ifndef CAPSTONE_DIET |
| 3208 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3209 | #endif |
| 3210 | }, |
| 3211 | { |
| 3212 | AArch64_FCVTAU_2d, ARM64_INS_FCVTAU, |
| 3213 | #ifndef CAPSTONE_DIET |
| 3214 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3215 | #endif |
| 3216 | }, |
| 3217 | { |
| 3218 | AArch64_FCVTAU_2s, ARM64_INS_FCVTAU, |
| 3219 | #ifndef CAPSTONE_DIET |
| 3220 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3221 | #endif |
| 3222 | }, |
| 3223 | { |
| 3224 | AArch64_FCVTAU_4s, ARM64_INS_FCVTAU, |
| 3225 | #ifndef CAPSTONE_DIET |
| 3226 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3227 | #endif |
| 3228 | }, |
| 3229 | { |
| 3230 | AArch64_FCVTAUdd, ARM64_INS_FCVTAU, |
| 3231 | #ifndef CAPSTONE_DIET |
| 3232 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3233 | #endif |
| 3234 | }, |
| 3235 | { |
| 3236 | AArch64_FCVTAUss, ARM64_INS_FCVTAU, |
| 3237 | #ifndef CAPSTONE_DIET |
| 3238 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3239 | #endif |
| 3240 | }, |
| 3241 | { |
| 3242 | AArch64_FCVTAUwd, ARM64_INS_FCVTAU, |
| 3243 | #ifndef CAPSTONE_DIET |
| 3244 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3245 | #endif |
| 3246 | }, |
| 3247 | { |
| 3248 | AArch64_FCVTAUws, ARM64_INS_FCVTAU, |
| 3249 | #ifndef CAPSTONE_DIET |
| 3250 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3251 | #endif |
| 3252 | }, |
| 3253 | { |
| 3254 | AArch64_FCVTAUxd, ARM64_INS_FCVTAU, |
| 3255 | #ifndef CAPSTONE_DIET |
| 3256 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3257 | #endif |
| 3258 | }, |
| 3259 | { |
| 3260 | AArch64_FCVTAUxs, ARM64_INS_FCVTAU, |
| 3261 | #ifndef CAPSTONE_DIET |
| 3262 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3263 | #endif |
| 3264 | }, |
| 3265 | { |
| 3266 | AArch64_FCVTL2s2d, ARM64_INS_FCVTL, |
| 3267 | #ifndef CAPSTONE_DIET |
| 3268 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3269 | #endif |
| 3270 | }, |
| 3271 | { |
| 3272 | AArch64_FCVTL4h4s, ARM64_INS_FCVTL, |
| 3273 | #ifndef CAPSTONE_DIET |
| 3274 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3275 | #endif |
| 3276 | }, |
| 3277 | { |
| 3278 | AArch64_FCVTL4s2d, ARM64_INS_FCVTL2, |
| 3279 | #ifndef CAPSTONE_DIET |
| 3280 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3281 | #endif |
| 3282 | }, |
| 3283 | { |
| 3284 | AArch64_FCVTL8h4s, ARM64_INS_FCVTL2, |
| 3285 | #ifndef CAPSTONE_DIET |
| 3286 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3287 | #endif |
| 3288 | }, |
| 3289 | { |
| 3290 | AArch64_FCVTMS_2d, ARM64_INS_FCVTMS, |
| 3291 | #ifndef CAPSTONE_DIET |
| 3292 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3293 | #endif |
| 3294 | }, |
| 3295 | { |
| 3296 | AArch64_FCVTMS_2s, ARM64_INS_FCVTMS, |
| 3297 | #ifndef CAPSTONE_DIET |
| 3298 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3299 | #endif |
| 3300 | }, |
| 3301 | { |
| 3302 | AArch64_FCVTMS_4s, ARM64_INS_FCVTMS, |
| 3303 | #ifndef CAPSTONE_DIET |
| 3304 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3305 | #endif |
| 3306 | }, |
| 3307 | { |
| 3308 | AArch64_FCVTMSdd, ARM64_INS_FCVTMS, |
| 3309 | #ifndef CAPSTONE_DIET |
| 3310 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3311 | #endif |
| 3312 | }, |
| 3313 | { |
| 3314 | AArch64_FCVTMSss, ARM64_INS_FCVTMS, |
| 3315 | #ifndef CAPSTONE_DIET |
| 3316 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3317 | #endif |
| 3318 | }, |
| 3319 | { |
| 3320 | AArch64_FCVTMSwd, ARM64_INS_FCVTMS, |
| 3321 | #ifndef CAPSTONE_DIET |
| 3322 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3323 | #endif |
| 3324 | }, |
| 3325 | { |
| 3326 | AArch64_FCVTMSws, ARM64_INS_FCVTMS, |
| 3327 | #ifndef CAPSTONE_DIET |
| 3328 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3329 | #endif |
| 3330 | }, |
| 3331 | { |
| 3332 | AArch64_FCVTMSxd, ARM64_INS_FCVTMS, |
| 3333 | #ifndef CAPSTONE_DIET |
| 3334 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3335 | #endif |
| 3336 | }, |
| 3337 | { |
| 3338 | AArch64_FCVTMSxs, ARM64_INS_FCVTMS, |
| 3339 | #ifndef CAPSTONE_DIET |
| 3340 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3341 | #endif |
| 3342 | }, |
| 3343 | { |
| 3344 | AArch64_FCVTMU_2d, ARM64_INS_FCVTMU, |
| 3345 | #ifndef CAPSTONE_DIET |
| 3346 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3347 | #endif |
| 3348 | }, |
| 3349 | { |
| 3350 | AArch64_FCVTMU_2s, ARM64_INS_FCVTMU, |
| 3351 | #ifndef CAPSTONE_DIET |
| 3352 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3353 | #endif |
| 3354 | }, |
| 3355 | { |
| 3356 | AArch64_FCVTMU_4s, ARM64_INS_FCVTMU, |
| 3357 | #ifndef CAPSTONE_DIET |
| 3358 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3359 | #endif |
| 3360 | }, |
| 3361 | { |
| 3362 | AArch64_FCVTMUdd, ARM64_INS_FCVTMU, |
| 3363 | #ifndef CAPSTONE_DIET |
| 3364 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3365 | #endif |
| 3366 | }, |
| 3367 | { |
| 3368 | AArch64_FCVTMUss, ARM64_INS_FCVTMU, |
| 3369 | #ifndef CAPSTONE_DIET |
| 3370 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3371 | #endif |
| 3372 | }, |
| 3373 | { |
| 3374 | AArch64_FCVTMUwd, ARM64_INS_FCVTMU, |
| 3375 | #ifndef CAPSTONE_DIET |
| 3376 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3377 | #endif |
| 3378 | }, |
| 3379 | { |
| 3380 | AArch64_FCVTMUws, ARM64_INS_FCVTMU, |
| 3381 | #ifndef CAPSTONE_DIET |
| 3382 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3383 | #endif |
| 3384 | }, |
| 3385 | { |
| 3386 | AArch64_FCVTMUxd, ARM64_INS_FCVTMU, |
| 3387 | #ifndef CAPSTONE_DIET |
| 3388 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3389 | #endif |
| 3390 | }, |
| 3391 | { |
| 3392 | AArch64_FCVTMUxs, ARM64_INS_FCVTMU, |
| 3393 | #ifndef CAPSTONE_DIET |
| 3394 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3395 | #endif |
| 3396 | }, |
| 3397 | { |
| 3398 | AArch64_FCVTN2d2s, ARM64_INS_FCVTN, |
| 3399 | #ifndef CAPSTONE_DIET |
| 3400 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3401 | #endif |
| 3402 | }, |
| 3403 | { |
| 3404 | AArch64_FCVTN2d4s, ARM64_INS_FCVTN2, |
| 3405 | #ifndef CAPSTONE_DIET |
| 3406 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3407 | #endif |
| 3408 | }, |
| 3409 | { |
| 3410 | AArch64_FCVTN4s4h, ARM64_INS_FCVTN, |
| 3411 | #ifndef CAPSTONE_DIET |
| 3412 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3413 | #endif |
| 3414 | }, |
| 3415 | { |
| 3416 | AArch64_FCVTN4s8h, ARM64_INS_FCVTN2, |
| 3417 | #ifndef CAPSTONE_DIET |
| 3418 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3419 | #endif |
| 3420 | }, |
| 3421 | { |
| 3422 | AArch64_FCVTNS_2d, ARM64_INS_FCVTNS, |
| 3423 | #ifndef CAPSTONE_DIET |
| 3424 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3425 | #endif |
| 3426 | }, |
| 3427 | { |
| 3428 | AArch64_FCVTNS_2s, ARM64_INS_FCVTNS, |
| 3429 | #ifndef CAPSTONE_DIET |
| 3430 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3431 | #endif |
| 3432 | }, |
| 3433 | { |
| 3434 | AArch64_FCVTNS_4s, ARM64_INS_FCVTNS, |
| 3435 | #ifndef CAPSTONE_DIET |
| 3436 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3437 | #endif |
| 3438 | }, |
| 3439 | { |
| 3440 | AArch64_FCVTNSdd, ARM64_INS_FCVTNS, |
| 3441 | #ifndef CAPSTONE_DIET |
| 3442 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3443 | #endif |
| 3444 | }, |
| 3445 | { |
| 3446 | AArch64_FCVTNSss, ARM64_INS_FCVTNS, |
| 3447 | #ifndef CAPSTONE_DIET |
| 3448 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3449 | #endif |
| 3450 | }, |
| 3451 | { |
| 3452 | AArch64_FCVTNSwd, ARM64_INS_FCVTNS, |
| 3453 | #ifndef CAPSTONE_DIET |
| 3454 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3455 | #endif |
| 3456 | }, |
| 3457 | { |
| 3458 | AArch64_FCVTNSws, ARM64_INS_FCVTNS, |
| 3459 | #ifndef CAPSTONE_DIET |
| 3460 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3461 | #endif |
| 3462 | }, |
| 3463 | { |
| 3464 | AArch64_FCVTNSxd, ARM64_INS_FCVTNS, |
| 3465 | #ifndef CAPSTONE_DIET |
| 3466 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3467 | #endif |
| 3468 | }, |
| 3469 | { |
| 3470 | AArch64_FCVTNSxs, ARM64_INS_FCVTNS, |
| 3471 | #ifndef CAPSTONE_DIET |
| 3472 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3473 | #endif |
| 3474 | }, |
| 3475 | { |
| 3476 | AArch64_FCVTNU_2d, ARM64_INS_FCVTNU, |
| 3477 | #ifndef CAPSTONE_DIET |
| 3478 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3479 | #endif |
| 3480 | }, |
| 3481 | { |
| 3482 | AArch64_FCVTNU_2s, ARM64_INS_FCVTNU, |
| 3483 | #ifndef CAPSTONE_DIET |
| 3484 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3485 | #endif |
| 3486 | }, |
| 3487 | { |
| 3488 | AArch64_FCVTNU_4s, ARM64_INS_FCVTNU, |
| 3489 | #ifndef CAPSTONE_DIET |
| 3490 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3491 | #endif |
| 3492 | }, |
| 3493 | { |
| 3494 | AArch64_FCVTNUdd, ARM64_INS_FCVTNU, |
| 3495 | #ifndef CAPSTONE_DIET |
| 3496 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3497 | #endif |
| 3498 | }, |
| 3499 | { |
| 3500 | AArch64_FCVTNUss, ARM64_INS_FCVTNU, |
| 3501 | #ifndef CAPSTONE_DIET |
| 3502 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3503 | #endif |
| 3504 | }, |
| 3505 | { |
| 3506 | AArch64_FCVTNUwd, ARM64_INS_FCVTNU, |
| 3507 | #ifndef CAPSTONE_DIET |
| 3508 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3509 | #endif |
| 3510 | }, |
| 3511 | { |
| 3512 | AArch64_FCVTNUws, ARM64_INS_FCVTNU, |
| 3513 | #ifndef CAPSTONE_DIET |
| 3514 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3515 | #endif |
| 3516 | }, |
| 3517 | { |
| 3518 | AArch64_FCVTNUxd, ARM64_INS_FCVTNU, |
| 3519 | #ifndef CAPSTONE_DIET |
| 3520 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3521 | #endif |
| 3522 | }, |
| 3523 | { |
| 3524 | AArch64_FCVTNUxs, ARM64_INS_FCVTNU, |
| 3525 | #ifndef CAPSTONE_DIET |
| 3526 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3527 | #endif |
| 3528 | }, |
| 3529 | { |
| 3530 | AArch64_FCVTPS_2d, ARM64_INS_FCVTPS, |
| 3531 | #ifndef CAPSTONE_DIET |
| 3532 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3533 | #endif |
| 3534 | }, |
| 3535 | { |
| 3536 | AArch64_FCVTPS_2s, ARM64_INS_FCVTPS, |
| 3537 | #ifndef CAPSTONE_DIET |
| 3538 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3539 | #endif |
| 3540 | }, |
| 3541 | { |
| 3542 | AArch64_FCVTPS_4s, ARM64_INS_FCVTPS, |
| 3543 | #ifndef CAPSTONE_DIET |
| 3544 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3545 | #endif |
| 3546 | }, |
| 3547 | { |
| 3548 | AArch64_FCVTPSdd, ARM64_INS_FCVTPS, |
| 3549 | #ifndef CAPSTONE_DIET |
| 3550 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3551 | #endif |
| 3552 | }, |
| 3553 | { |
| 3554 | AArch64_FCVTPSss, ARM64_INS_FCVTPS, |
| 3555 | #ifndef CAPSTONE_DIET |
| 3556 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3557 | #endif |
| 3558 | }, |
| 3559 | { |
| 3560 | AArch64_FCVTPSwd, ARM64_INS_FCVTPS, |
| 3561 | #ifndef CAPSTONE_DIET |
| 3562 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3563 | #endif |
| 3564 | }, |
| 3565 | { |
| 3566 | AArch64_FCVTPSws, ARM64_INS_FCVTPS, |
| 3567 | #ifndef CAPSTONE_DIET |
| 3568 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3569 | #endif |
| 3570 | }, |
| 3571 | { |
| 3572 | AArch64_FCVTPSxd, ARM64_INS_FCVTPS, |
| 3573 | #ifndef CAPSTONE_DIET |
| 3574 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3575 | #endif |
| 3576 | }, |
| 3577 | { |
| 3578 | AArch64_FCVTPSxs, ARM64_INS_FCVTPS, |
| 3579 | #ifndef CAPSTONE_DIET |
| 3580 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3581 | #endif |
| 3582 | }, |
| 3583 | { |
| 3584 | AArch64_FCVTPU_2d, ARM64_INS_FCVTPU, |
| 3585 | #ifndef CAPSTONE_DIET |
| 3586 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3587 | #endif |
| 3588 | }, |
| 3589 | { |
| 3590 | AArch64_FCVTPU_2s, ARM64_INS_FCVTPU, |
| 3591 | #ifndef CAPSTONE_DIET |
| 3592 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3593 | #endif |
| 3594 | }, |
| 3595 | { |
| 3596 | AArch64_FCVTPU_4s, ARM64_INS_FCVTPU, |
| 3597 | #ifndef CAPSTONE_DIET |
| 3598 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3599 | #endif |
| 3600 | }, |
| 3601 | { |
| 3602 | AArch64_FCVTPUdd, ARM64_INS_FCVTPU, |
| 3603 | #ifndef CAPSTONE_DIET |
| 3604 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3605 | #endif |
| 3606 | }, |
| 3607 | { |
| 3608 | AArch64_FCVTPUss, ARM64_INS_FCVTPU, |
| 3609 | #ifndef CAPSTONE_DIET |
| 3610 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3611 | #endif |
| 3612 | }, |
| 3613 | { |
| 3614 | AArch64_FCVTPUwd, ARM64_INS_FCVTPU, |
| 3615 | #ifndef CAPSTONE_DIET |
| 3616 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3617 | #endif |
| 3618 | }, |
| 3619 | { |
| 3620 | AArch64_FCVTPUws, ARM64_INS_FCVTPU, |
| 3621 | #ifndef CAPSTONE_DIET |
| 3622 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3623 | #endif |
| 3624 | }, |
| 3625 | { |
| 3626 | AArch64_FCVTPUxd, ARM64_INS_FCVTPU, |
| 3627 | #ifndef CAPSTONE_DIET |
| 3628 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3629 | #endif |
| 3630 | }, |
| 3631 | { |
| 3632 | AArch64_FCVTPUxs, ARM64_INS_FCVTPU, |
| 3633 | #ifndef CAPSTONE_DIET |
| 3634 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3635 | #endif |
| 3636 | }, |
| 3637 | { |
| 3638 | AArch64_FCVTXN, ARM64_INS_FCVTXN, |
| 3639 | #ifndef CAPSTONE_DIET |
| 3640 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3641 | #endif |
| 3642 | }, |
| 3643 | { |
| 3644 | AArch64_FCVTXN2d2s, ARM64_INS_FCVTXN, |
| 3645 | #ifndef CAPSTONE_DIET |
| 3646 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3647 | #endif |
| 3648 | }, |
| 3649 | { |
| 3650 | AArch64_FCVTXN2d4s, ARM64_INS_FCVTXN2, |
| 3651 | #ifndef CAPSTONE_DIET |
| 3652 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3653 | #endif |
| 3654 | }, |
| 3655 | { |
| 3656 | AArch64_FCVTZS_2d, ARM64_INS_FCVTZS, |
| 3657 | #ifndef CAPSTONE_DIET |
| 3658 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3659 | #endif |
| 3660 | }, |
| 3661 | { |
| 3662 | AArch64_FCVTZS_2s, ARM64_INS_FCVTZS, |
| 3663 | #ifndef CAPSTONE_DIET |
| 3664 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3665 | #endif |
| 3666 | }, |
| 3667 | { |
| 3668 | AArch64_FCVTZS_4s, ARM64_INS_FCVTZS, |
| 3669 | #ifndef CAPSTONE_DIET |
| 3670 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3671 | #endif |
| 3672 | }, |
| 3673 | { |
| 3674 | AArch64_FCVTZS_Nddi, ARM64_INS_FCVTZS, |
| 3675 | #ifndef CAPSTONE_DIET |
| 3676 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3677 | #endif |
| 3678 | }, |
| 3679 | { |
| 3680 | AArch64_FCVTZS_Nssi, ARM64_INS_FCVTZS, |
| 3681 | #ifndef CAPSTONE_DIET |
| 3682 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3683 | #endif |
| 3684 | }, |
| 3685 | { |
| 3686 | AArch64_FCVTZSdd, ARM64_INS_FCVTZS, |
| 3687 | #ifndef CAPSTONE_DIET |
| 3688 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3689 | #endif |
| 3690 | }, |
| 3691 | { |
| 3692 | AArch64_FCVTZSss, ARM64_INS_FCVTZS, |
| 3693 | #ifndef CAPSTONE_DIET |
| 3694 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3695 | #endif |
| 3696 | }, |
| 3697 | { |
| 3698 | AArch64_FCVTZSwd, ARM64_INS_FCVTZS, |
| 3699 | #ifndef CAPSTONE_DIET |
| 3700 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3701 | #endif |
| 3702 | }, |
| 3703 | { |
| 3704 | AArch64_FCVTZSwdi, ARM64_INS_FCVTZS, |
| 3705 | #ifndef CAPSTONE_DIET |
| 3706 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3707 | #endif |
| 3708 | }, |
| 3709 | { |
| 3710 | AArch64_FCVTZSws, ARM64_INS_FCVTZS, |
| 3711 | #ifndef CAPSTONE_DIET |
| 3712 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3713 | #endif |
| 3714 | }, |
| 3715 | { |
| 3716 | AArch64_FCVTZSwsi, ARM64_INS_FCVTZS, |
| 3717 | #ifndef CAPSTONE_DIET |
| 3718 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3719 | #endif |
| 3720 | }, |
| 3721 | { |
| 3722 | AArch64_FCVTZSxd, ARM64_INS_FCVTZS, |
| 3723 | #ifndef CAPSTONE_DIET |
| 3724 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3725 | #endif |
| 3726 | }, |
| 3727 | { |
| 3728 | AArch64_FCVTZSxdi, ARM64_INS_FCVTZS, |
| 3729 | #ifndef CAPSTONE_DIET |
| 3730 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3731 | #endif |
| 3732 | }, |
| 3733 | { |
| 3734 | AArch64_FCVTZSxs, ARM64_INS_FCVTZS, |
| 3735 | #ifndef CAPSTONE_DIET |
| 3736 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3737 | #endif |
| 3738 | }, |
| 3739 | { |
| 3740 | AArch64_FCVTZSxsi, ARM64_INS_FCVTZS, |
| 3741 | #ifndef CAPSTONE_DIET |
| 3742 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3743 | #endif |
| 3744 | }, |
| 3745 | { |
| 3746 | AArch64_FCVTZU_2d, ARM64_INS_FCVTZU, |
| 3747 | #ifndef CAPSTONE_DIET |
| 3748 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3749 | #endif |
| 3750 | }, |
| 3751 | { |
| 3752 | AArch64_FCVTZU_2s, ARM64_INS_FCVTZU, |
| 3753 | #ifndef CAPSTONE_DIET |
| 3754 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3755 | #endif |
| 3756 | }, |
| 3757 | { |
| 3758 | AArch64_FCVTZU_4s, ARM64_INS_FCVTZU, |
| 3759 | #ifndef CAPSTONE_DIET |
| 3760 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3761 | #endif |
| 3762 | }, |
| 3763 | { |
| 3764 | AArch64_FCVTZU_Nddi, ARM64_INS_FCVTZU, |
| 3765 | #ifndef CAPSTONE_DIET |
| 3766 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3767 | #endif |
| 3768 | }, |
| 3769 | { |
| 3770 | AArch64_FCVTZU_Nssi, ARM64_INS_FCVTZU, |
| 3771 | #ifndef CAPSTONE_DIET |
| 3772 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3773 | #endif |
| 3774 | }, |
| 3775 | { |
| 3776 | AArch64_FCVTZUdd, ARM64_INS_FCVTZU, |
| 3777 | #ifndef CAPSTONE_DIET |
| 3778 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3779 | #endif |
| 3780 | }, |
| 3781 | { |
| 3782 | AArch64_FCVTZUss, ARM64_INS_FCVTZU, |
| 3783 | #ifndef CAPSTONE_DIET |
| 3784 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3785 | #endif |
| 3786 | }, |
| 3787 | { |
| 3788 | AArch64_FCVTZUwd, ARM64_INS_FCVTZU, |
| 3789 | #ifndef CAPSTONE_DIET |
| 3790 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3791 | #endif |
| 3792 | }, |
| 3793 | { |
| 3794 | AArch64_FCVTZUwdi, ARM64_INS_FCVTZU, |
| 3795 | #ifndef CAPSTONE_DIET |
| 3796 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3797 | #endif |
| 3798 | }, |
| 3799 | { |
| 3800 | AArch64_FCVTZUws, ARM64_INS_FCVTZU, |
| 3801 | #ifndef CAPSTONE_DIET |
| 3802 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3803 | #endif |
| 3804 | }, |
| 3805 | { |
| 3806 | AArch64_FCVTZUwsi, ARM64_INS_FCVTZU, |
| 3807 | #ifndef CAPSTONE_DIET |
| 3808 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3809 | #endif |
| 3810 | }, |
| 3811 | { |
| 3812 | AArch64_FCVTZUxd, ARM64_INS_FCVTZU, |
| 3813 | #ifndef CAPSTONE_DIET |
| 3814 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3815 | #endif |
| 3816 | }, |
| 3817 | { |
| 3818 | AArch64_FCVTZUxdi, ARM64_INS_FCVTZU, |
| 3819 | #ifndef CAPSTONE_DIET |
| 3820 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3821 | #endif |
| 3822 | }, |
| 3823 | { |
| 3824 | AArch64_FCVTZUxs, ARM64_INS_FCVTZU, |
| 3825 | #ifndef CAPSTONE_DIET |
| 3826 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3827 | #endif |
| 3828 | }, |
| 3829 | { |
| 3830 | AArch64_FCVTZUxsi, ARM64_INS_FCVTZU, |
| 3831 | #ifndef CAPSTONE_DIET |
| 3832 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3833 | #endif |
| 3834 | }, |
| 3835 | { |
| 3836 | AArch64_FCVTdh, ARM64_INS_FCVT, |
| 3837 | #ifndef CAPSTONE_DIET |
| 3838 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3839 | #endif |
| 3840 | }, |
| 3841 | { |
| 3842 | AArch64_FCVTds, ARM64_INS_FCVT, |
| 3843 | #ifndef CAPSTONE_DIET |
| 3844 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3845 | #endif |
| 3846 | }, |
| 3847 | { |
| 3848 | AArch64_FCVThd, ARM64_INS_FCVT, |
| 3849 | #ifndef CAPSTONE_DIET |
| 3850 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3851 | #endif |
| 3852 | }, |
| 3853 | { |
| 3854 | AArch64_FCVThs, ARM64_INS_FCVT, |
| 3855 | #ifndef CAPSTONE_DIET |
| 3856 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3857 | #endif |
| 3858 | }, |
| 3859 | { |
| 3860 | AArch64_FCVTsd, ARM64_INS_FCVT, |
| 3861 | #ifndef CAPSTONE_DIET |
| 3862 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3863 | #endif |
| 3864 | }, |
| 3865 | { |
| 3866 | AArch64_FCVTsh, ARM64_INS_FCVT, |
| 3867 | #ifndef CAPSTONE_DIET |
| 3868 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3869 | #endif |
| 3870 | }, |
| 3871 | { |
| 3872 | AArch64_FDIVddd, ARM64_INS_FDIV, |
| 3873 | #ifndef CAPSTONE_DIET |
| 3874 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3875 | #endif |
| 3876 | }, |
| 3877 | { |
| 3878 | AArch64_FDIVsss, ARM64_INS_FDIV, |
| 3879 | #ifndef CAPSTONE_DIET |
| 3880 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3881 | #endif |
| 3882 | }, |
| 3883 | { |
| 3884 | AArch64_FDIVvvv_2D, ARM64_INS_FDIV, |
| 3885 | #ifndef CAPSTONE_DIET |
| 3886 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3887 | #endif |
| 3888 | }, |
| 3889 | { |
| 3890 | AArch64_FDIVvvv_2S, ARM64_INS_FDIV, |
| 3891 | #ifndef CAPSTONE_DIET |
| 3892 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3893 | #endif |
| 3894 | }, |
| 3895 | { |
| 3896 | AArch64_FDIVvvv_4S, ARM64_INS_FDIV, |
| 3897 | #ifndef CAPSTONE_DIET |
| 3898 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3899 | #endif |
| 3900 | }, |
| 3901 | { |
| 3902 | AArch64_FMADDdddd, ARM64_INS_FMADD, |
| 3903 | #ifndef CAPSTONE_DIET |
| 3904 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3905 | #endif |
| 3906 | }, |
| 3907 | { |
| 3908 | AArch64_FMADDssss, ARM64_INS_FMADD, |
| 3909 | #ifndef CAPSTONE_DIET |
| 3910 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3911 | #endif |
| 3912 | }, |
| 3913 | { |
| 3914 | AArch64_FMAXNMPvv_D_2D, ARM64_INS_FMAXNMP, |
| 3915 | #ifndef CAPSTONE_DIET |
| 3916 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3917 | #endif |
| 3918 | }, |
| 3919 | { |
| 3920 | AArch64_FMAXNMPvv_S_2S, ARM64_INS_FMAXNMP, |
| 3921 | #ifndef CAPSTONE_DIET |
| 3922 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3923 | #endif |
| 3924 | }, |
| 3925 | { |
| 3926 | AArch64_FMAXNMPvvv_2D, ARM64_INS_FMAXNMP, |
| 3927 | #ifndef CAPSTONE_DIET |
| 3928 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3929 | #endif |
| 3930 | }, |
| 3931 | { |
| 3932 | AArch64_FMAXNMPvvv_2S, ARM64_INS_FMAXNMP, |
| 3933 | #ifndef CAPSTONE_DIET |
| 3934 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3935 | #endif |
| 3936 | }, |
| 3937 | { |
| 3938 | AArch64_FMAXNMPvvv_4S, ARM64_INS_FMAXNMP, |
| 3939 | #ifndef CAPSTONE_DIET |
| 3940 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3941 | #endif |
| 3942 | }, |
| 3943 | { |
| 3944 | AArch64_FMAXNMV_1s4s, ARM64_INS_FMAXNMV, |
| 3945 | #ifndef CAPSTONE_DIET |
| 3946 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3947 | #endif |
| 3948 | }, |
| 3949 | { |
| 3950 | AArch64_FMAXNMddd, ARM64_INS_FMAXNM, |
| 3951 | #ifndef CAPSTONE_DIET |
| 3952 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3953 | #endif |
| 3954 | }, |
| 3955 | { |
| 3956 | AArch64_FMAXNMsss, ARM64_INS_FMAXNM, |
| 3957 | #ifndef CAPSTONE_DIET |
| 3958 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 3959 | #endif |
| 3960 | }, |
| 3961 | { |
| 3962 | AArch64_FMAXNMvvv_2D, ARM64_INS_FMAXNM, |
| 3963 | #ifndef CAPSTONE_DIET |
| 3964 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3965 | #endif |
| 3966 | }, |
| 3967 | { |
| 3968 | AArch64_FMAXNMvvv_2S, ARM64_INS_FMAXNM, |
| 3969 | #ifndef CAPSTONE_DIET |
| 3970 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3971 | #endif |
| 3972 | }, |
| 3973 | { |
| 3974 | AArch64_FMAXNMvvv_4S, ARM64_INS_FMAXNM, |
| 3975 | #ifndef CAPSTONE_DIET |
| 3976 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3977 | #endif |
| 3978 | }, |
| 3979 | { |
| 3980 | AArch64_FMAXPvv_D_2D, ARM64_INS_FMAXP, |
| 3981 | #ifndef CAPSTONE_DIET |
| 3982 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3983 | #endif |
| 3984 | }, |
| 3985 | { |
| 3986 | AArch64_FMAXPvv_S_2S, ARM64_INS_FMAXP, |
| 3987 | #ifndef CAPSTONE_DIET |
| 3988 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3989 | #endif |
| 3990 | }, |
| 3991 | { |
| 3992 | AArch64_FMAXPvvv_2D, ARM64_INS_FMAXP, |
| 3993 | #ifndef CAPSTONE_DIET |
| 3994 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 3995 | #endif |
| 3996 | }, |
| 3997 | { |
| 3998 | AArch64_FMAXPvvv_2S, ARM64_INS_FMAXP, |
| 3999 | #ifndef CAPSTONE_DIET |
| 4000 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4001 | #endif |
| 4002 | }, |
| 4003 | { |
| 4004 | AArch64_FMAXPvvv_4S, ARM64_INS_FMAXP, |
| 4005 | #ifndef CAPSTONE_DIET |
| 4006 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4007 | #endif |
| 4008 | }, |
| 4009 | { |
| 4010 | AArch64_FMAXV_1s4s, ARM64_INS_FMAXV, |
| 4011 | #ifndef CAPSTONE_DIET |
| 4012 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4013 | #endif |
| 4014 | }, |
| 4015 | { |
| 4016 | AArch64_FMAXddd, ARM64_INS_FMAX, |
| 4017 | #ifndef CAPSTONE_DIET |
| 4018 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4019 | #endif |
| 4020 | }, |
| 4021 | { |
| 4022 | AArch64_FMAXsss, ARM64_INS_FMAX, |
| 4023 | #ifndef CAPSTONE_DIET |
| 4024 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4025 | #endif |
| 4026 | }, |
| 4027 | { |
| 4028 | AArch64_FMAXvvv_2D, ARM64_INS_FMAX, |
| 4029 | #ifndef CAPSTONE_DIET |
| 4030 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4031 | #endif |
| 4032 | }, |
| 4033 | { |
| 4034 | AArch64_FMAXvvv_2S, ARM64_INS_FMAX, |
| 4035 | #ifndef CAPSTONE_DIET |
| 4036 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4037 | #endif |
| 4038 | }, |
| 4039 | { |
| 4040 | AArch64_FMAXvvv_4S, ARM64_INS_FMAX, |
| 4041 | #ifndef CAPSTONE_DIET |
| 4042 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4043 | #endif |
| 4044 | }, |
| 4045 | { |
| 4046 | AArch64_FMINNMPvv_D_2D, ARM64_INS_FMINNMP, |
| 4047 | #ifndef CAPSTONE_DIET |
| 4048 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4049 | #endif |
| 4050 | }, |
| 4051 | { |
| 4052 | AArch64_FMINNMPvv_S_2S, ARM64_INS_FMINNMP, |
| 4053 | #ifndef CAPSTONE_DIET |
| 4054 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4055 | #endif |
| 4056 | }, |
| 4057 | { |
| 4058 | AArch64_FMINNMPvvv_2D, ARM64_INS_FMINNMP, |
| 4059 | #ifndef CAPSTONE_DIET |
| 4060 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4061 | #endif |
| 4062 | }, |
| 4063 | { |
| 4064 | AArch64_FMINNMPvvv_2S, ARM64_INS_FMINNMP, |
| 4065 | #ifndef CAPSTONE_DIET |
| 4066 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4067 | #endif |
| 4068 | }, |
| 4069 | { |
| 4070 | AArch64_FMINNMPvvv_4S, ARM64_INS_FMINNMP, |
| 4071 | #ifndef CAPSTONE_DIET |
| 4072 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4073 | #endif |
| 4074 | }, |
| 4075 | { |
| 4076 | AArch64_FMINNMV_1s4s, ARM64_INS_FMINNMV, |
| 4077 | #ifndef CAPSTONE_DIET |
| 4078 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4079 | #endif |
| 4080 | }, |
| 4081 | { |
| 4082 | AArch64_FMINNMddd, ARM64_INS_FMINNM, |
| 4083 | #ifndef CAPSTONE_DIET |
| 4084 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4085 | #endif |
| 4086 | }, |
| 4087 | { |
| 4088 | AArch64_FMINNMsss, ARM64_INS_FMINNM, |
| 4089 | #ifndef CAPSTONE_DIET |
| 4090 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4091 | #endif |
| 4092 | }, |
| 4093 | { |
| 4094 | AArch64_FMINNMvvv_2D, ARM64_INS_FMINNM, |
| 4095 | #ifndef CAPSTONE_DIET |
| 4096 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4097 | #endif |
| 4098 | }, |
| 4099 | { |
| 4100 | AArch64_FMINNMvvv_2S, ARM64_INS_FMINNM, |
| 4101 | #ifndef CAPSTONE_DIET |
| 4102 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4103 | #endif |
| 4104 | }, |
| 4105 | { |
| 4106 | AArch64_FMINNMvvv_4S, ARM64_INS_FMINNM, |
| 4107 | #ifndef CAPSTONE_DIET |
| 4108 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4109 | #endif |
| 4110 | }, |
| 4111 | { |
| 4112 | AArch64_FMINPvv_D_2D, ARM64_INS_FMINP, |
| 4113 | #ifndef CAPSTONE_DIET |
| 4114 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4115 | #endif |
| 4116 | }, |
| 4117 | { |
| 4118 | AArch64_FMINPvv_S_2S, ARM64_INS_FMINP, |
| 4119 | #ifndef CAPSTONE_DIET |
| 4120 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4121 | #endif |
| 4122 | }, |
| 4123 | { |
| 4124 | AArch64_FMINPvvv_2D, ARM64_INS_FMINP, |
| 4125 | #ifndef CAPSTONE_DIET |
| 4126 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4127 | #endif |
| 4128 | }, |
| 4129 | { |
| 4130 | AArch64_FMINPvvv_2S, ARM64_INS_FMINP, |
| 4131 | #ifndef CAPSTONE_DIET |
| 4132 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4133 | #endif |
| 4134 | }, |
| 4135 | { |
| 4136 | AArch64_FMINPvvv_4S, ARM64_INS_FMINP, |
| 4137 | #ifndef CAPSTONE_DIET |
| 4138 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4139 | #endif |
| 4140 | }, |
| 4141 | { |
| 4142 | AArch64_FMINV_1s4s, ARM64_INS_FMINV, |
| 4143 | #ifndef CAPSTONE_DIET |
| 4144 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4145 | #endif |
| 4146 | }, |
| 4147 | { |
| 4148 | AArch64_FMINddd, ARM64_INS_FMIN, |
| 4149 | #ifndef CAPSTONE_DIET |
| 4150 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4151 | #endif |
| 4152 | }, |
| 4153 | { |
| 4154 | AArch64_FMINsss, ARM64_INS_FMIN, |
| 4155 | #ifndef CAPSTONE_DIET |
| 4156 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4157 | #endif |
| 4158 | }, |
| 4159 | { |
| 4160 | AArch64_FMINvvv_2D, ARM64_INS_FMIN, |
| 4161 | #ifndef CAPSTONE_DIET |
| 4162 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4163 | #endif |
| 4164 | }, |
| 4165 | { |
| 4166 | AArch64_FMINvvv_2S, ARM64_INS_FMIN, |
| 4167 | #ifndef CAPSTONE_DIET |
| 4168 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4169 | #endif |
| 4170 | }, |
| 4171 | { |
| 4172 | AArch64_FMINvvv_4S, ARM64_INS_FMIN, |
| 4173 | #ifndef CAPSTONE_DIET |
| 4174 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4175 | #endif |
| 4176 | }, |
| 4177 | { |
| 4178 | AArch64_FMLAddv_2D, ARM64_INS_FMLA, |
| 4179 | #ifndef CAPSTONE_DIET |
| 4180 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4181 | #endif |
| 4182 | }, |
| 4183 | { |
| 4184 | AArch64_FMLAssv_4S, ARM64_INS_FMLA, |
| 4185 | #ifndef CAPSTONE_DIET |
| 4186 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4187 | #endif |
| 4188 | }, |
| 4189 | { |
| 4190 | AArch64_FMLAvve_2d2d, ARM64_INS_FMLA, |
| 4191 | #ifndef CAPSTONE_DIET |
| 4192 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4193 | #endif |
| 4194 | }, |
| 4195 | { |
| 4196 | AArch64_FMLAvve_2s4s, ARM64_INS_FMLA, |
| 4197 | #ifndef CAPSTONE_DIET |
| 4198 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4199 | #endif |
| 4200 | }, |
| 4201 | { |
| 4202 | AArch64_FMLAvve_4s4s, ARM64_INS_FMLA, |
| 4203 | #ifndef CAPSTONE_DIET |
| 4204 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4205 | #endif |
| 4206 | }, |
| 4207 | { |
| 4208 | AArch64_FMLAvvv_2D, ARM64_INS_FMLA, |
| 4209 | #ifndef CAPSTONE_DIET |
| 4210 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4211 | #endif |
| 4212 | }, |
| 4213 | { |
| 4214 | AArch64_FMLAvvv_2S, ARM64_INS_FMLA, |
| 4215 | #ifndef CAPSTONE_DIET |
| 4216 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4217 | #endif |
| 4218 | }, |
| 4219 | { |
| 4220 | AArch64_FMLAvvv_4S, ARM64_INS_FMLA, |
| 4221 | #ifndef CAPSTONE_DIET |
| 4222 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4223 | #endif |
| 4224 | }, |
| 4225 | { |
| 4226 | AArch64_FMLSddv_2D, ARM64_INS_FMLS, |
| 4227 | #ifndef CAPSTONE_DIET |
| 4228 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4229 | #endif |
| 4230 | }, |
| 4231 | { |
| 4232 | AArch64_FMLSssv_4S, ARM64_INS_FMLS, |
| 4233 | #ifndef CAPSTONE_DIET |
| 4234 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4235 | #endif |
| 4236 | }, |
| 4237 | { |
| 4238 | AArch64_FMLSvve_2d2d, ARM64_INS_FMLS, |
| 4239 | #ifndef CAPSTONE_DIET |
| 4240 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4241 | #endif |
| 4242 | }, |
| 4243 | { |
| 4244 | AArch64_FMLSvve_2s4s, ARM64_INS_FMLS, |
| 4245 | #ifndef CAPSTONE_DIET |
| 4246 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4247 | #endif |
| 4248 | }, |
| 4249 | { |
| 4250 | AArch64_FMLSvve_4s4s, ARM64_INS_FMLS, |
| 4251 | #ifndef CAPSTONE_DIET |
| 4252 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4253 | #endif |
| 4254 | }, |
| 4255 | { |
| 4256 | AArch64_FMLSvvv_2D, ARM64_INS_FMLS, |
| 4257 | #ifndef CAPSTONE_DIET |
| 4258 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4259 | #endif |
| 4260 | }, |
| 4261 | { |
| 4262 | AArch64_FMLSvvv_2S, ARM64_INS_FMLS, |
| 4263 | #ifndef CAPSTONE_DIET |
| 4264 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4265 | #endif |
| 4266 | }, |
| 4267 | { |
| 4268 | AArch64_FMLSvvv_4S, ARM64_INS_FMLS, |
| 4269 | #ifndef CAPSTONE_DIET |
| 4270 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4271 | #endif |
| 4272 | }, |
| 4273 | { |
| 4274 | AArch64_FMOVdd, ARM64_INS_FMOV, |
| 4275 | #ifndef CAPSTONE_DIET |
| 4276 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4277 | #endif |
| 4278 | }, |
| 4279 | { |
| 4280 | AArch64_FMOVdi, ARM64_INS_FMOV, |
| 4281 | #ifndef CAPSTONE_DIET |
| 4282 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4283 | #endif |
| 4284 | }, |
| 4285 | { |
| 4286 | AArch64_FMOVdx, ARM64_INS_FMOV, |
| 4287 | #ifndef CAPSTONE_DIET |
| 4288 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4289 | #endif |
| 4290 | }, |
| 4291 | { |
| 4292 | AArch64_FMOVsi, ARM64_INS_FMOV, |
| 4293 | #ifndef CAPSTONE_DIET |
| 4294 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4295 | #endif |
| 4296 | }, |
| 4297 | { |
| 4298 | AArch64_FMOVss, ARM64_INS_FMOV, |
| 4299 | #ifndef CAPSTONE_DIET |
| 4300 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4301 | #endif |
| 4302 | }, |
| 4303 | { |
| 4304 | AArch64_FMOVsw, ARM64_INS_FMOV, |
| 4305 | #ifndef CAPSTONE_DIET |
| 4306 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4307 | #endif |
| 4308 | }, |
| 4309 | { |
| 4310 | AArch64_FMOVvi_2D, ARM64_INS_FMOV, |
| 4311 | #ifndef CAPSTONE_DIET |
| 4312 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4313 | #endif |
| 4314 | }, |
| 4315 | { |
| 4316 | AArch64_FMOVvi_2S, ARM64_INS_FMOV, |
| 4317 | #ifndef CAPSTONE_DIET |
| 4318 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4319 | #endif |
| 4320 | }, |
| 4321 | { |
| 4322 | AArch64_FMOVvi_4S, ARM64_INS_FMOV, |
| 4323 | #ifndef CAPSTONE_DIET |
| 4324 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4325 | #endif |
| 4326 | }, |
| 4327 | { |
| 4328 | AArch64_FMOVvx, ARM64_INS_FMOV, |
| 4329 | #ifndef CAPSTONE_DIET |
| 4330 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4331 | #endif |
| 4332 | }, |
| 4333 | { |
| 4334 | AArch64_FMOVws, ARM64_INS_FMOV, |
| 4335 | #ifndef CAPSTONE_DIET |
| 4336 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4337 | #endif |
| 4338 | }, |
| 4339 | { |
| 4340 | AArch64_FMOVxd, ARM64_INS_FMOV, |
| 4341 | #ifndef CAPSTONE_DIET |
| 4342 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4343 | #endif |
| 4344 | }, |
| 4345 | { |
| 4346 | AArch64_FMOVxv, ARM64_INS_FMOV, |
| 4347 | #ifndef CAPSTONE_DIET |
| 4348 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4349 | #endif |
| 4350 | }, |
| 4351 | { |
| 4352 | AArch64_FMSUBdddd, ARM64_INS_FMSUB, |
| 4353 | #ifndef CAPSTONE_DIET |
| 4354 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4355 | #endif |
| 4356 | }, |
| 4357 | { |
| 4358 | AArch64_FMSUBssss, ARM64_INS_FMSUB, |
| 4359 | #ifndef CAPSTONE_DIET |
| 4360 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4361 | #endif |
| 4362 | }, |
| 4363 | { |
| 4364 | AArch64_FMULXddd, ARM64_INS_FMULX, |
| 4365 | #ifndef CAPSTONE_DIET |
| 4366 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4367 | #endif |
| 4368 | }, |
| 4369 | { |
| 4370 | AArch64_FMULXddv_2D, ARM64_INS_FMULX, |
| 4371 | #ifndef CAPSTONE_DIET |
| 4372 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4373 | #endif |
| 4374 | }, |
| 4375 | { |
| 4376 | AArch64_FMULXsss, ARM64_INS_FMULX, |
| 4377 | #ifndef CAPSTONE_DIET |
| 4378 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4379 | #endif |
| 4380 | }, |
| 4381 | { |
| 4382 | AArch64_FMULXssv_4S, ARM64_INS_FMULX, |
| 4383 | #ifndef CAPSTONE_DIET |
| 4384 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4385 | #endif |
| 4386 | }, |
| 4387 | { |
| 4388 | AArch64_FMULXve_2d2d, ARM64_INS_FMULX, |
| 4389 | #ifndef CAPSTONE_DIET |
| 4390 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4391 | #endif |
| 4392 | }, |
| 4393 | { |
| 4394 | AArch64_FMULXve_2s4s, ARM64_INS_FMULX, |
| 4395 | #ifndef CAPSTONE_DIET |
| 4396 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4397 | #endif |
| 4398 | }, |
| 4399 | { |
| 4400 | AArch64_FMULXve_4s4s, ARM64_INS_FMULX, |
| 4401 | #ifndef CAPSTONE_DIET |
| 4402 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4403 | #endif |
| 4404 | }, |
| 4405 | { |
| 4406 | AArch64_FMULXvvv_2D, ARM64_INS_FMULX, |
| 4407 | #ifndef CAPSTONE_DIET |
| 4408 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4409 | #endif |
| 4410 | }, |
| 4411 | { |
| 4412 | AArch64_FMULXvvv_2S, ARM64_INS_FMULX, |
| 4413 | #ifndef CAPSTONE_DIET |
| 4414 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4415 | #endif |
| 4416 | }, |
| 4417 | { |
| 4418 | AArch64_FMULXvvv_4S, ARM64_INS_FMULX, |
| 4419 | #ifndef CAPSTONE_DIET |
| 4420 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4421 | #endif |
| 4422 | }, |
| 4423 | { |
| 4424 | AArch64_FMULddd, ARM64_INS_FMUL, |
| 4425 | #ifndef CAPSTONE_DIET |
| 4426 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4427 | #endif |
| 4428 | }, |
| 4429 | { |
| 4430 | AArch64_FMULddv_2D, ARM64_INS_FMUL, |
| 4431 | #ifndef CAPSTONE_DIET |
| 4432 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4433 | #endif |
| 4434 | }, |
| 4435 | { |
| 4436 | AArch64_FMULsss, ARM64_INS_FMUL, |
| 4437 | #ifndef CAPSTONE_DIET |
| 4438 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4439 | #endif |
| 4440 | }, |
| 4441 | { |
| 4442 | AArch64_FMULssv_4S, ARM64_INS_FMUL, |
| 4443 | #ifndef CAPSTONE_DIET |
| 4444 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4445 | #endif |
| 4446 | }, |
| 4447 | { |
| 4448 | AArch64_FMULve_2d2d, ARM64_INS_FMUL, |
| 4449 | #ifndef CAPSTONE_DIET |
| 4450 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4451 | #endif |
| 4452 | }, |
| 4453 | { |
| 4454 | AArch64_FMULve_2s4s, ARM64_INS_FMUL, |
| 4455 | #ifndef CAPSTONE_DIET |
| 4456 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4457 | #endif |
| 4458 | }, |
| 4459 | { |
| 4460 | AArch64_FMULve_4s4s, ARM64_INS_FMUL, |
| 4461 | #ifndef CAPSTONE_DIET |
| 4462 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4463 | #endif |
| 4464 | }, |
| 4465 | { |
| 4466 | AArch64_FMULvvv_2D, ARM64_INS_FMUL, |
| 4467 | #ifndef CAPSTONE_DIET |
| 4468 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4469 | #endif |
| 4470 | }, |
| 4471 | { |
| 4472 | AArch64_FMULvvv_2S, ARM64_INS_FMUL, |
| 4473 | #ifndef CAPSTONE_DIET |
| 4474 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4475 | #endif |
| 4476 | }, |
| 4477 | { |
| 4478 | AArch64_FMULvvv_4S, ARM64_INS_FMUL, |
| 4479 | #ifndef CAPSTONE_DIET |
| 4480 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4481 | #endif |
| 4482 | }, |
| 4483 | { |
| 4484 | AArch64_FNEG2d, ARM64_INS_FNEG, |
| 4485 | #ifndef CAPSTONE_DIET |
| 4486 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4487 | #endif |
| 4488 | }, |
| 4489 | { |
| 4490 | AArch64_FNEG2s, ARM64_INS_FNEG, |
| 4491 | #ifndef CAPSTONE_DIET |
| 4492 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4493 | #endif |
| 4494 | }, |
| 4495 | { |
| 4496 | AArch64_FNEG4s, ARM64_INS_FNEG, |
| 4497 | #ifndef CAPSTONE_DIET |
| 4498 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4499 | #endif |
| 4500 | }, |
| 4501 | { |
| 4502 | AArch64_FNEGdd, ARM64_INS_FNEG, |
| 4503 | #ifndef CAPSTONE_DIET |
| 4504 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4505 | #endif |
| 4506 | }, |
| 4507 | { |
| 4508 | AArch64_FNEGss, ARM64_INS_FNEG, |
| 4509 | #ifndef CAPSTONE_DIET |
| 4510 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4511 | #endif |
| 4512 | }, |
| 4513 | { |
| 4514 | AArch64_FNMADDdddd, ARM64_INS_FNMADD, |
| 4515 | #ifndef CAPSTONE_DIET |
| 4516 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4517 | #endif |
| 4518 | }, |
| 4519 | { |
| 4520 | AArch64_FNMADDssss, ARM64_INS_FNMADD, |
| 4521 | #ifndef CAPSTONE_DIET |
| 4522 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4523 | #endif |
| 4524 | }, |
| 4525 | { |
| 4526 | AArch64_FNMSUBdddd, ARM64_INS_FNMSUB, |
| 4527 | #ifndef CAPSTONE_DIET |
| 4528 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4529 | #endif |
| 4530 | }, |
| 4531 | { |
| 4532 | AArch64_FNMSUBssss, ARM64_INS_FNMSUB, |
| 4533 | #ifndef CAPSTONE_DIET |
| 4534 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4535 | #endif |
| 4536 | }, |
| 4537 | { |
| 4538 | AArch64_FNMULddd, ARM64_INS_FNMUL, |
| 4539 | #ifndef CAPSTONE_DIET |
| 4540 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4541 | #endif |
| 4542 | }, |
| 4543 | { |
| 4544 | AArch64_FNMULsss, ARM64_INS_FNMUL, |
| 4545 | #ifndef CAPSTONE_DIET |
| 4546 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4547 | #endif |
| 4548 | }, |
| 4549 | { |
| 4550 | AArch64_FRECPE_2d, ARM64_INS_FRECPE, |
| 4551 | #ifndef CAPSTONE_DIET |
| 4552 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4553 | #endif |
| 4554 | }, |
| 4555 | { |
| 4556 | AArch64_FRECPE_2s, ARM64_INS_FRECPE, |
| 4557 | #ifndef CAPSTONE_DIET |
| 4558 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4559 | #endif |
| 4560 | }, |
| 4561 | { |
| 4562 | AArch64_FRECPE_4s, ARM64_INS_FRECPE, |
| 4563 | #ifndef CAPSTONE_DIET |
| 4564 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4565 | #endif |
| 4566 | }, |
| 4567 | { |
| 4568 | AArch64_FRECPEdd, ARM64_INS_FRECPE, |
| 4569 | #ifndef CAPSTONE_DIET |
| 4570 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4571 | #endif |
| 4572 | }, |
| 4573 | { |
| 4574 | AArch64_FRECPEss, ARM64_INS_FRECPE, |
| 4575 | #ifndef CAPSTONE_DIET |
| 4576 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4577 | #endif |
| 4578 | }, |
| 4579 | { |
| 4580 | AArch64_FRECPSddd, ARM64_INS_FRECPS, |
| 4581 | #ifndef CAPSTONE_DIET |
| 4582 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4583 | #endif |
| 4584 | }, |
| 4585 | { |
| 4586 | AArch64_FRECPSsss, ARM64_INS_FRECPS, |
| 4587 | #ifndef CAPSTONE_DIET |
| 4588 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4589 | #endif |
| 4590 | }, |
| 4591 | { |
| 4592 | AArch64_FRECPSvvv_2D, ARM64_INS_FRECPS, |
| 4593 | #ifndef CAPSTONE_DIET |
| 4594 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4595 | #endif |
| 4596 | }, |
| 4597 | { |
| 4598 | AArch64_FRECPSvvv_2S, ARM64_INS_FRECPS, |
| 4599 | #ifndef CAPSTONE_DIET |
| 4600 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4601 | #endif |
| 4602 | }, |
| 4603 | { |
| 4604 | AArch64_FRECPSvvv_4S, ARM64_INS_FRECPS, |
| 4605 | #ifndef CAPSTONE_DIET |
| 4606 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4607 | #endif |
| 4608 | }, |
| 4609 | { |
| 4610 | AArch64_FRECPXdd, ARM64_INS_FRECPX, |
| 4611 | #ifndef CAPSTONE_DIET |
| 4612 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4613 | #endif |
| 4614 | }, |
| 4615 | { |
| 4616 | AArch64_FRECPXss, ARM64_INS_FRECPX, |
| 4617 | #ifndef CAPSTONE_DIET |
| 4618 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4619 | #endif |
| 4620 | }, |
| 4621 | { |
| 4622 | AArch64_FRINTA_2d, ARM64_INS_FRINTA, |
| 4623 | #ifndef CAPSTONE_DIET |
| 4624 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4625 | #endif |
| 4626 | }, |
| 4627 | { |
| 4628 | AArch64_FRINTA_2s, ARM64_INS_FRINTA, |
| 4629 | #ifndef CAPSTONE_DIET |
| 4630 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4631 | #endif |
| 4632 | }, |
| 4633 | { |
| 4634 | AArch64_FRINTA_4s, ARM64_INS_FRINTA, |
| 4635 | #ifndef CAPSTONE_DIET |
| 4636 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4637 | #endif |
| 4638 | }, |
| 4639 | { |
| 4640 | AArch64_FRINTAdd, ARM64_INS_FRINTA, |
| 4641 | #ifndef CAPSTONE_DIET |
| 4642 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4643 | #endif |
| 4644 | }, |
| 4645 | { |
| 4646 | AArch64_FRINTAss, ARM64_INS_FRINTA, |
| 4647 | #ifndef CAPSTONE_DIET |
| 4648 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4649 | #endif |
| 4650 | }, |
| 4651 | { |
| 4652 | AArch64_FRINTI_2d, ARM64_INS_FRINTI, |
| 4653 | #ifndef CAPSTONE_DIET |
| 4654 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4655 | #endif |
| 4656 | }, |
| 4657 | { |
| 4658 | AArch64_FRINTI_2s, ARM64_INS_FRINTI, |
| 4659 | #ifndef CAPSTONE_DIET |
| 4660 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4661 | #endif |
| 4662 | }, |
| 4663 | { |
| 4664 | AArch64_FRINTI_4s, ARM64_INS_FRINTI, |
| 4665 | #ifndef CAPSTONE_DIET |
| 4666 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4667 | #endif |
| 4668 | }, |
| 4669 | { |
| 4670 | AArch64_FRINTIdd, ARM64_INS_FRINTI, |
| 4671 | #ifndef CAPSTONE_DIET |
| 4672 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4673 | #endif |
| 4674 | }, |
| 4675 | { |
| 4676 | AArch64_FRINTIss, ARM64_INS_FRINTI, |
| 4677 | #ifndef CAPSTONE_DIET |
| 4678 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4679 | #endif |
| 4680 | }, |
| 4681 | { |
| 4682 | AArch64_FRINTM_2d, ARM64_INS_FRINTM, |
| 4683 | #ifndef CAPSTONE_DIET |
| 4684 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4685 | #endif |
| 4686 | }, |
| 4687 | { |
| 4688 | AArch64_FRINTM_2s, ARM64_INS_FRINTM, |
| 4689 | #ifndef CAPSTONE_DIET |
| 4690 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4691 | #endif |
| 4692 | }, |
| 4693 | { |
| 4694 | AArch64_FRINTM_4s, ARM64_INS_FRINTM, |
| 4695 | #ifndef CAPSTONE_DIET |
| 4696 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4697 | #endif |
| 4698 | }, |
| 4699 | { |
| 4700 | AArch64_FRINTMdd, ARM64_INS_FRINTM, |
| 4701 | #ifndef CAPSTONE_DIET |
| 4702 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4703 | #endif |
| 4704 | }, |
| 4705 | { |
| 4706 | AArch64_FRINTMss, ARM64_INS_FRINTM, |
| 4707 | #ifndef CAPSTONE_DIET |
| 4708 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4709 | #endif |
| 4710 | }, |
| 4711 | { |
| 4712 | AArch64_FRINTN_2d, ARM64_INS_FRINTN, |
| 4713 | #ifndef CAPSTONE_DIET |
| 4714 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4715 | #endif |
| 4716 | }, |
| 4717 | { |
| 4718 | AArch64_FRINTN_2s, ARM64_INS_FRINTN, |
| 4719 | #ifndef CAPSTONE_DIET |
| 4720 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4721 | #endif |
| 4722 | }, |
| 4723 | { |
| 4724 | AArch64_FRINTN_4s, ARM64_INS_FRINTN, |
| 4725 | #ifndef CAPSTONE_DIET |
| 4726 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4727 | #endif |
| 4728 | }, |
| 4729 | { |
| 4730 | AArch64_FRINTNdd, ARM64_INS_FRINTN, |
| 4731 | #ifndef CAPSTONE_DIET |
| 4732 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4733 | #endif |
| 4734 | }, |
| 4735 | { |
| 4736 | AArch64_FRINTNss, ARM64_INS_FRINTN, |
| 4737 | #ifndef CAPSTONE_DIET |
| 4738 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4739 | #endif |
| 4740 | }, |
| 4741 | { |
| 4742 | AArch64_FRINTP_2d, ARM64_INS_FRINTP, |
| 4743 | #ifndef CAPSTONE_DIET |
| 4744 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4745 | #endif |
| 4746 | }, |
| 4747 | { |
| 4748 | AArch64_FRINTP_2s, ARM64_INS_FRINTP, |
| 4749 | #ifndef CAPSTONE_DIET |
| 4750 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4751 | #endif |
| 4752 | }, |
| 4753 | { |
| 4754 | AArch64_FRINTP_4s, ARM64_INS_FRINTP, |
| 4755 | #ifndef CAPSTONE_DIET |
| 4756 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4757 | #endif |
| 4758 | }, |
| 4759 | { |
| 4760 | AArch64_FRINTPdd, ARM64_INS_FRINTP, |
| 4761 | #ifndef CAPSTONE_DIET |
| 4762 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4763 | #endif |
| 4764 | }, |
| 4765 | { |
| 4766 | AArch64_FRINTPss, ARM64_INS_FRINTP, |
| 4767 | #ifndef CAPSTONE_DIET |
| 4768 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4769 | #endif |
| 4770 | }, |
| 4771 | { |
| 4772 | AArch64_FRINTX_2d, ARM64_INS_FRINTX, |
| 4773 | #ifndef CAPSTONE_DIET |
| 4774 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4775 | #endif |
| 4776 | }, |
| 4777 | { |
| 4778 | AArch64_FRINTX_2s, ARM64_INS_FRINTX, |
| 4779 | #ifndef CAPSTONE_DIET |
| 4780 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4781 | #endif |
| 4782 | }, |
| 4783 | { |
| 4784 | AArch64_FRINTX_4s, ARM64_INS_FRINTX, |
| 4785 | #ifndef CAPSTONE_DIET |
| 4786 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4787 | #endif |
| 4788 | }, |
| 4789 | { |
| 4790 | AArch64_FRINTXdd, ARM64_INS_FRINTX, |
| 4791 | #ifndef CAPSTONE_DIET |
| 4792 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4793 | #endif |
| 4794 | }, |
| 4795 | { |
| 4796 | AArch64_FRINTXss, ARM64_INS_FRINTX, |
| 4797 | #ifndef CAPSTONE_DIET |
| 4798 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4799 | #endif |
| 4800 | }, |
| 4801 | { |
| 4802 | AArch64_FRINTZ_2d, ARM64_INS_FRINTZ, |
| 4803 | #ifndef CAPSTONE_DIET |
| 4804 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4805 | #endif |
| 4806 | }, |
| 4807 | { |
| 4808 | AArch64_FRINTZ_2s, ARM64_INS_FRINTZ, |
| 4809 | #ifndef CAPSTONE_DIET |
| 4810 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4811 | #endif |
| 4812 | }, |
| 4813 | { |
| 4814 | AArch64_FRINTZ_4s, ARM64_INS_FRINTZ, |
| 4815 | #ifndef CAPSTONE_DIET |
| 4816 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4817 | #endif |
| 4818 | }, |
| 4819 | { |
| 4820 | AArch64_FRINTZdd, ARM64_INS_FRINTZ, |
| 4821 | #ifndef CAPSTONE_DIET |
| 4822 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4823 | #endif |
| 4824 | }, |
| 4825 | { |
| 4826 | AArch64_FRINTZss, ARM64_INS_FRINTZ, |
| 4827 | #ifndef CAPSTONE_DIET |
| 4828 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4829 | #endif |
| 4830 | }, |
| 4831 | { |
| 4832 | AArch64_FRSQRTE_2d, ARM64_INS_FRSQRTE, |
| 4833 | #ifndef CAPSTONE_DIET |
| 4834 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4835 | #endif |
| 4836 | }, |
| 4837 | { |
| 4838 | AArch64_FRSQRTE_2s, ARM64_INS_FRSQRTE, |
| 4839 | #ifndef CAPSTONE_DIET |
| 4840 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4841 | #endif |
| 4842 | }, |
| 4843 | { |
| 4844 | AArch64_FRSQRTE_4s, ARM64_INS_FRSQRTE, |
| 4845 | #ifndef CAPSTONE_DIET |
| 4846 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4847 | #endif |
| 4848 | }, |
| 4849 | { |
| 4850 | AArch64_FRSQRTEdd, ARM64_INS_FRSQRTE, |
| 4851 | #ifndef CAPSTONE_DIET |
| 4852 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4853 | #endif |
| 4854 | }, |
| 4855 | { |
| 4856 | AArch64_FRSQRTEss, ARM64_INS_FRSQRTE, |
| 4857 | #ifndef CAPSTONE_DIET |
| 4858 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4859 | #endif |
| 4860 | }, |
| 4861 | { |
| 4862 | AArch64_FRSQRTSddd, ARM64_INS_FRSQRTS, |
| 4863 | #ifndef CAPSTONE_DIET |
| 4864 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4865 | #endif |
| 4866 | }, |
| 4867 | { |
| 4868 | AArch64_FRSQRTSsss, ARM64_INS_FRSQRTS, |
| 4869 | #ifndef CAPSTONE_DIET |
| 4870 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4871 | #endif |
| 4872 | }, |
| 4873 | { |
| 4874 | AArch64_FRSQRTSvvv_2D, ARM64_INS_FRSQRTS, |
| 4875 | #ifndef CAPSTONE_DIET |
| 4876 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4877 | #endif |
| 4878 | }, |
| 4879 | { |
| 4880 | AArch64_FRSQRTSvvv_2S, ARM64_INS_FRSQRTS, |
| 4881 | #ifndef CAPSTONE_DIET |
| 4882 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4883 | #endif |
| 4884 | }, |
| 4885 | { |
| 4886 | AArch64_FRSQRTSvvv_4S, ARM64_INS_FRSQRTS, |
| 4887 | #ifndef CAPSTONE_DIET |
| 4888 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4889 | #endif |
| 4890 | }, |
| 4891 | { |
| 4892 | AArch64_FSQRT_2d, ARM64_INS_FSQRT, |
| 4893 | #ifndef CAPSTONE_DIET |
| 4894 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4895 | #endif |
| 4896 | }, |
| 4897 | { |
| 4898 | AArch64_FSQRT_2s, ARM64_INS_FSQRT, |
| 4899 | #ifndef CAPSTONE_DIET |
| 4900 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4901 | #endif |
| 4902 | }, |
| 4903 | { |
| 4904 | AArch64_FSQRT_4s, ARM64_INS_FSQRT, |
| 4905 | #ifndef CAPSTONE_DIET |
| 4906 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4907 | #endif |
| 4908 | }, |
| 4909 | { |
| 4910 | AArch64_FSQRTdd, ARM64_INS_FSQRT, |
| 4911 | #ifndef CAPSTONE_DIET |
| 4912 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4913 | #endif |
| 4914 | }, |
| 4915 | { |
| 4916 | AArch64_FSQRTss, ARM64_INS_FSQRT, |
| 4917 | #ifndef CAPSTONE_DIET |
| 4918 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4919 | #endif |
| 4920 | }, |
| 4921 | { |
| 4922 | AArch64_FSUBddd, ARM64_INS_FSUB, |
| 4923 | #ifndef CAPSTONE_DIET |
| 4924 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4925 | #endif |
| 4926 | }, |
| 4927 | { |
| 4928 | AArch64_FSUBsss, ARM64_INS_FSUB, |
| 4929 | #ifndef CAPSTONE_DIET |
| 4930 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 4931 | #endif |
| 4932 | }, |
| 4933 | { |
| 4934 | AArch64_FSUBvvv_2D, ARM64_INS_FSUB, |
| 4935 | #ifndef CAPSTONE_DIET |
| 4936 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4937 | #endif |
| 4938 | }, |
| 4939 | { |
| 4940 | AArch64_FSUBvvv_2S, ARM64_INS_FSUB, |
| 4941 | #ifndef CAPSTONE_DIET |
| 4942 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4943 | #endif |
| 4944 | }, |
| 4945 | { |
| 4946 | AArch64_FSUBvvv_4S, ARM64_INS_FSUB, |
| 4947 | #ifndef CAPSTONE_DIET |
| 4948 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4949 | #endif |
| 4950 | }, |
| 4951 | { |
| 4952 | AArch64_HINTi, ARM64_INS_HINT, |
| 4953 | #ifndef CAPSTONE_DIET |
| 4954 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 4955 | #endif |
| 4956 | }, |
| 4957 | { |
| 4958 | AArch64_HLTi, ARM64_INS_HLT, |
| 4959 | #ifndef CAPSTONE_DIET |
| 4960 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 4961 | #endif |
| 4962 | }, |
| 4963 | { |
| 4964 | AArch64_HVCi, ARM64_INS_HVC, |
| 4965 | #ifndef CAPSTONE_DIET |
| 4966 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 4967 | #endif |
| 4968 | }, |
| 4969 | { |
| 4970 | AArch64_ICi, ARM64_INS_IC, |
| 4971 | #ifndef CAPSTONE_DIET |
| 4972 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 4973 | #endif |
| 4974 | }, |
| 4975 | { |
| 4976 | AArch64_ICix, ARM64_INS_IC, |
| 4977 | #ifndef CAPSTONE_DIET |
| 4978 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 4979 | #endif |
| 4980 | }, |
| 4981 | { |
| 4982 | AArch64_INSELb, ARM64_INS_INS, |
| 4983 | #ifndef CAPSTONE_DIET |
| 4984 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4985 | #endif |
| 4986 | }, |
| 4987 | { |
| 4988 | AArch64_INSELd, ARM64_INS_INS, |
| 4989 | #ifndef CAPSTONE_DIET |
| 4990 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4991 | #endif |
| 4992 | }, |
| 4993 | { |
| 4994 | AArch64_INSELh, ARM64_INS_INS, |
| 4995 | #ifndef CAPSTONE_DIET |
| 4996 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 4997 | #endif |
| 4998 | }, |
| 4999 | { |
| 5000 | AArch64_INSELs, ARM64_INS_INS, |
| 5001 | #ifndef CAPSTONE_DIET |
| 5002 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5003 | #endif |
| 5004 | }, |
| 5005 | { |
| 5006 | AArch64_INSbw, ARM64_INS_INS, |
| 5007 | #ifndef CAPSTONE_DIET |
| 5008 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5009 | #endif |
| 5010 | }, |
| 5011 | { |
| 5012 | AArch64_INSdx, ARM64_INS_INS, |
| 5013 | #ifndef CAPSTONE_DIET |
| 5014 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5015 | #endif |
| 5016 | }, |
| 5017 | { |
| 5018 | AArch64_INShw, ARM64_INS_INS, |
| 5019 | #ifndef CAPSTONE_DIET |
| 5020 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5021 | #endif |
| 5022 | }, |
| 5023 | { |
| 5024 | AArch64_INSsw, ARM64_INS_INS, |
| 5025 | #ifndef CAPSTONE_DIET |
| 5026 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5027 | #endif |
| 5028 | }, |
| 5029 | { |
| 5030 | AArch64_ISBi, ARM64_INS_ISB, |
| 5031 | #ifndef CAPSTONE_DIET |
| 5032 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 5033 | #endif |
| 5034 | }, |
| 5035 | { |
| 5036 | AArch64_LD1LN_B, ARM64_INS_LD1, |
| 5037 | #ifndef CAPSTONE_DIET |
| 5038 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5039 | #endif |
| 5040 | }, |
| 5041 | { |
| 5042 | AArch64_LD1LN_D, ARM64_INS_LD1, |
| 5043 | #ifndef CAPSTONE_DIET |
| 5044 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5045 | #endif |
| 5046 | }, |
| 5047 | { |
| 5048 | AArch64_LD1LN_H, ARM64_INS_LD1, |
| 5049 | #ifndef CAPSTONE_DIET |
| 5050 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5051 | #endif |
| 5052 | }, |
| 5053 | { |
| 5054 | AArch64_LD1LN_S, ARM64_INS_LD1, |
| 5055 | #ifndef CAPSTONE_DIET |
| 5056 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5057 | #endif |
| 5058 | }, |
| 5059 | { |
| 5060 | AArch64_LD1LN_WB_B_fixed, ARM64_INS_LD1, |
| 5061 | #ifndef CAPSTONE_DIET |
| 5062 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5063 | #endif |
| 5064 | }, |
| 5065 | { |
| 5066 | AArch64_LD1LN_WB_B_register, ARM64_INS_LD1, |
| 5067 | #ifndef CAPSTONE_DIET |
| 5068 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5069 | #endif |
| 5070 | }, |
| 5071 | { |
| 5072 | AArch64_LD1LN_WB_D_fixed, ARM64_INS_LD1, |
| 5073 | #ifndef CAPSTONE_DIET |
| 5074 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5075 | #endif |
| 5076 | }, |
| 5077 | { |
| 5078 | AArch64_LD1LN_WB_D_register, ARM64_INS_LD1, |
| 5079 | #ifndef CAPSTONE_DIET |
| 5080 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5081 | #endif |
| 5082 | }, |
| 5083 | { |
| 5084 | AArch64_LD1LN_WB_H_fixed, ARM64_INS_LD1, |
| 5085 | #ifndef CAPSTONE_DIET |
| 5086 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5087 | #endif |
| 5088 | }, |
| 5089 | { |
| 5090 | AArch64_LD1LN_WB_H_register, ARM64_INS_LD1, |
| 5091 | #ifndef CAPSTONE_DIET |
| 5092 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5093 | #endif |
| 5094 | }, |
| 5095 | { |
| 5096 | AArch64_LD1LN_WB_S_fixed, ARM64_INS_LD1, |
| 5097 | #ifndef CAPSTONE_DIET |
| 5098 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5099 | #endif |
| 5100 | }, |
| 5101 | { |
| 5102 | AArch64_LD1LN_WB_S_register, ARM64_INS_LD1, |
| 5103 | #ifndef CAPSTONE_DIET |
| 5104 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5105 | #endif |
| 5106 | }, |
| 5107 | { |
| 5108 | AArch64_LD1R_16B, ARM64_INS_LD1R, |
| 5109 | #ifndef CAPSTONE_DIET |
| 5110 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5111 | #endif |
| 5112 | }, |
| 5113 | { |
| 5114 | AArch64_LD1R_1D, ARM64_INS_LD1R, |
| 5115 | #ifndef CAPSTONE_DIET |
| 5116 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5117 | #endif |
| 5118 | }, |
| 5119 | { |
| 5120 | AArch64_LD1R_2D, ARM64_INS_LD1R, |
| 5121 | #ifndef CAPSTONE_DIET |
| 5122 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5123 | #endif |
| 5124 | }, |
| 5125 | { |
| 5126 | AArch64_LD1R_2S, ARM64_INS_LD1R, |
| 5127 | #ifndef CAPSTONE_DIET |
| 5128 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5129 | #endif |
| 5130 | }, |
| 5131 | { |
| 5132 | AArch64_LD1R_4H, ARM64_INS_LD1R, |
| 5133 | #ifndef CAPSTONE_DIET |
| 5134 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5135 | #endif |
| 5136 | }, |
| 5137 | { |
| 5138 | AArch64_LD1R_4S, ARM64_INS_LD1R, |
| 5139 | #ifndef CAPSTONE_DIET |
| 5140 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5141 | #endif |
| 5142 | }, |
| 5143 | { |
| 5144 | AArch64_LD1R_8B, ARM64_INS_LD1R, |
| 5145 | #ifndef CAPSTONE_DIET |
| 5146 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5147 | #endif |
| 5148 | }, |
| 5149 | { |
| 5150 | AArch64_LD1R_8H, ARM64_INS_LD1R, |
| 5151 | #ifndef CAPSTONE_DIET |
| 5152 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5153 | #endif |
| 5154 | }, |
| 5155 | { |
| 5156 | AArch64_LD1R_WB_16B_fixed, ARM64_INS_LD1R, |
| 5157 | #ifndef CAPSTONE_DIET |
| 5158 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5159 | #endif |
| 5160 | }, |
| 5161 | { |
| 5162 | AArch64_LD1R_WB_16B_register, ARM64_INS_LD1R, |
| 5163 | #ifndef CAPSTONE_DIET |
| 5164 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5165 | #endif |
| 5166 | }, |
| 5167 | { |
| 5168 | AArch64_LD1R_WB_1D_fixed, ARM64_INS_LD1R, |
| 5169 | #ifndef CAPSTONE_DIET |
| 5170 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5171 | #endif |
| 5172 | }, |
| 5173 | { |
| 5174 | AArch64_LD1R_WB_1D_register, ARM64_INS_LD1R, |
| 5175 | #ifndef CAPSTONE_DIET |
| 5176 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5177 | #endif |
| 5178 | }, |
| 5179 | { |
| 5180 | AArch64_LD1R_WB_2D_fixed, ARM64_INS_LD1R, |
| 5181 | #ifndef CAPSTONE_DIET |
| 5182 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5183 | #endif |
| 5184 | }, |
| 5185 | { |
| 5186 | AArch64_LD1R_WB_2D_register, ARM64_INS_LD1R, |
| 5187 | #ifndef CAPSTONE_DIET |
| 5188 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5189 | #endif |
| 5190 | }, |
| 5191 | { |
| 5192 | AArch64_LD1R_WB_2S_fixed, ARM64_INS_LD1R, |
| 5193 | #ifndef CAPSTONE_DIET |
| 5194 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5195 | #endif |
| 5196 | }, |
| 5197 | { |
| 5198 | AArch64_LD1R_WB_2S_register, ARM64_INS_LD1R, |
| 5199 | #ifndef CAPSTONE_DIET |
| 5200 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5201 | #endif |
| 5202 | }, |
| 5203 | { |
| 5204 | AArch64_LD1R_WB_4H_fixed, ARM64_INS_LD1R, |
| 5205 | #ifndef CAPSTONE_DIET |
| 5206 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5207 | #endif |
| 5208 | }, |
| 5209 | { |
| 5210 | AArch64_LD1R_WB_4H_register, ARM64_INS_LD1R, |
| 5211 | #ifndef CAPSTONE_DIET |
| 5212 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5213 | #endif |
| 5214 | }, |
| 5215 | { |
| 5216 | AArch64_LD1R_WB_4S_fixed, ARM64_INS_LD1R, |
| 5217 | #ifndef CAPSTONE_DIET |
| 5218 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5219 | #endif |
| 5220 | }, |
| 5221 | { |
| 5222 | AArch64_LD1R_WB_4S_register, ARM64_INS_LD1R, |
| 5223 | #ifndef CAPSTONE_DIET |
| 5224 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5225 | #endif |
| 5226 | }, |
| 5227 | { |
| 5228 | AArch64_LD1R_WB_8B_fixed, ARM64_INS_LD1R, |
| 5229 | #ifndef CAPSTONE_DIET |
| 5230 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5231 | #endif |
| 5232 | }, |
| 5233 | { |
| 5234 | AArch64_LD1R_WB_8B_register, ARM64_INS_LD1R, |
| 5235 | #ifndef CAPSTONE_DIET |
| 5236 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5237 | #endif |
| 5238 | }, |
| 5239 | { |
| 5240 | AArch64_LD1R_WB_8H_fixed, ARM64_INS_LD1R, |
| 5241 | #ifndef CAPSTONE_DIET |
| 5242 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5243 | #endif |
| 5244 | }, |
| 5245 | { |
| 5246 | AArch64_LD1R_WB_8H_register, ARM64_INS_LD1R, |
| 5247 | #ifndef CAPSTONE_DIET |
| 5248 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5249 | #endif |
| 5250 | }, |
| 5251 | { |
| 5252 | AArch64_LD1WB_16B_fixed, ARM64_INS_LD1, |
| 5253 | #ifndef CAPSTONE_DIET |
| 5254 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5255 | #endif |
| 5256 | }, |
| 5257 | { |
| 5258 | AArch64_LD1WB_16B_register, ARM64_INS_LD1, |
| 5259 | #ifndef CAPSTONE_DIET |
| 5260 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5261 | #endif |
| 5262 | }, |
| 5263 | { |
| 5264 | AArch64_LD1WB_1D_fixed, ARM64_INS_LD1, |
| 5265 | #ifndef CAPSTONE_DIET |
| 5266 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5267 | #endif |
| 5268 | }, |
| 5269 | { |
| 5270 | AArch64_LD1WB_1D_register, ARM64_INS_LD1, |
| 5271 | #ifndef CAPSTONE_DIET |
| 5272 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5273 | #endif |
| 5274 | }, |
| 5275 | { |
| 5276 | AArch64_LD1WB_2D_fixed, ARM64_INS_LD1, |
| 5277 | #ifndef CAPSTONE_DIET |
| 5278 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5279 | #endif |
| 5280 | }, |
| 5281 | { |
| 5282 | AArch64_LD1WB_2D_register, ARM64_INS_LD1, |
| 5283 | #ifndef CAPSTONE_DIET |
| 5284 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5285 | #endif |
| 5286 | }, |
| 5287 | { |
| 5288 | AArch64_LD1WB_2S_fixed, ARM64_INS_LD1, |
| 5289 | #ifndef CAPSTONE_DIET |
| 5290 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5291 | #endif |
| 5292 | }, |
| 5293 | { |
| 5294 | AArch64_LD1WB_2S_register, ARM64_INS_LD1, |
| 5295 | #ifndef CAPSTONE_DIET |
| 5296 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5297 | #endif |
| 5298 | }, |
| 5299 | { |
| 5300 | AArch64_LD1WB_4H_fixed, ARM64_INS_LD1, |
| 5301 | #ifndef CAPSTONE_DIET |
| 5302 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5303 | #endif |
| 5304 | }, |
| 5305 | { |
| 5306 | AArch64_LD1WB_4H_register, ARM64_INS_LD1, |
| 5307 | #ifndef CAPSTONE_DIET |
| 5308 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5309 | #endif |
| 5310 | }, |
| 5311 | { |
| 5312 | AArch64_LD1WB_4S_fixed, ARM64_INS_LD1, |
| 5313 | #ifndef CAPSTONE_DIET |
| 5314 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5315 | #endif |
| 5316 | }, |
| 5317 | { |
| 5318 | AArch64_LD1WB_4S_register, ARM64_INS_LD1, |
| 5319 | #ifndef CAPSTONE_DIET |
| 5320 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5321 | #endif |
| 5322 | }, |
| 5323 | { |
| 5324 | AArch64_LD1WB_8B_fixed, ARM64_INS_LD1, |
| 5325 | #ifndef CAPSTONE_DIET |
| 5326 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5327 | #endif |
| 5328 | }, |
| 5329 | { |
| 5330 | AArch64_LD1WB_8B_register, ARM64_INS_LD1, |
| 5331 | #ifndef CAPSTONE_DIET |
| 5332 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5333 | #endif |
| 5334 | }, |
| 5335 | { |
| 5336 | AArch64_LD1WB_8H_fixed, ARM64_INS_LD1, |
| 5337 | #ifndef CAPSTONE_DIET |
| 5338 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5339 | #endif |
| 5340 | }, |
| 5341 | { |
| 5342 | AArch64_LD1WB_8H_register, ARM64_INS_LD1, |
| 5343 | #ifndef CAPSTONE_DIET |
| 5344 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5345 | #endif |
| 5346 | }, |
| 5347 | { |
| 5348 | AArch64_LD1_16B, ARM64_INS_LD1, |
| 5349 | #ifndef CAPSTONE_DIET |
| 5350 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5351 | #endif |
| 5352 | }, |
| 5353 | { |
| 5354 | AArch64_LD1_1D, ARM64_INS_LD1, |
| 5355 | #ifndef CAPSTONE_DIET |
| 5356 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5357 | #endif |
| 5358 | }, |
| 5359 | { |
| 5360 | AArch64_LD1_2D, ARM64_INS_LD1, |
| 5361 | #ifndef CAPSTONE_DIET |
| 5362 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5363 | #endif |
| 5364 | }, |
| 5365 | { |
| 5366 | AArch64_LD1_2S, ARM64_INS_LD1, |
| 5367 | #ifndef CAPSTONE_DIET |
| 5368 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5369 | #endif |
| 5370 | }, |
| 5371 | { |
| 5372 | AArch64_LD1_4H, ARM64_INS_LD1, |
| 5373 | #ifndef CAPSTONE_DIET |
| 5374 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5375 | #endif |
| 5376 | }, |
| 5377 | { |
| 5378 | AArch64_LD1_4S, ARM64_INS_LD1, |
| 5379 | #ifndef CAPSTONE_DIET |
| 5380 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5381 | #endif |
| 5382 | }, |
| 5383 | { |
| 5384 | AArch64_LD1_8B, ARM64_INS_LD1, |
| 5385 | #ifndef CAPSTONE_DIET |
| 5386 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5387 | #endif |
| 5388 | }, |
| 5389 | { |
| 5390 | AArch64_LD1_8H, ARM64_INS_LD1, |
| 5391 | #ifndef CAPSTONE_DIET |
| 5392 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5393 | #endif |
| 5394 | }, |
| 5395 | { |
| 5396 | AArch64_LD1x2WB_16B_fixed, ARM64_INS_LD1, |
| 5397 | #ifndef CAPSTONE_DIET |
| 5398 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5399 | #endif |
| 5400 | }, |
| 5401 | { |
| 5402 | AArch64_LD1x2WB_16B_register, ARM64_INS_LD1, |
| 5403 | #ifndef CAPSTONE_DIET |
| 5404 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5405 | #endif |
| 5406 | }, |
| 5407 | { |
| 5408 | AArch64_LD1x2WB_1D_fixed, ARM64_INS_LD1, |
| 5409 | #ifndef CAPSTONE_DIET |
| 5410 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5411 | #endif |
| 5412 | }, |
| 5413 | { |
| 5414 | AArch64_LD1x2WB_1D_register, ARM64_INS_LD1, |
| 5415 | #ifndef CAPSTONE_DIET |
| 5416 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5417 | #endif |
| 5418 | }, |
| 5419 | { |
| 5420 | AArch64_LD1x2WB_2D_fixed, ARM64_INS_LD1, |
| 5421 | #ifndef CAPSTONE_DIET |
| 5422 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5423 | #endif |
| 5424 | }, |
| 5425 | { |
| 5426 | AArch64_LD1x2WB_2D_register, ARM64_INS_LD1, |
| 5427 | #ifndef CAPSTONE_DIET |
| 5428 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5429 | #endif |
| 5430 | }, |
| 5431 | { |
| 5432 | AArch64_LD1x2WB_2S_fixed, ARM64_INS_LD1, |
| 5433 | #ifndef CAPSTONE_DIET |
| 5434 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5435 | #endif |
| 5436 | }, |
| 5437 | { |
| 5438 | AArch64_LD1x2WB_2S_register, ARM64_INS_LD1, |
| 5439 | #ifndef CAPSTONE_DIET |
| 5440 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5441 | #endif |
| 5442 | }, |
| 5443 | { |
| 5444 | AArch64_LD1x2WB_4H_fixed, ARM64_INS_LD1, |
| 5445 | #ifndef CAPSTONE_DIET |
| 5446 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5447 | #endif |
| 5448 | }, |
| 5449 | { |
| 5450 | AArch64_LD1x2WB_4H_register, ARM64_INS_LD1, |
| 5451 | #ifndef CAPSTONE_DIET |
| 5452 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5453 | #endif |
| 5454 | }, |
| 5455 | { |
| 5456 | AArch64_LD1x2WB_4S_fixed, ARM64_INS_LD1, |
| 5457 | #ifndef CAPSTONE_DIET |
| 5458 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5459 | #endif |
| 5460 | }, |
| 5461 | { |
| 5462 | AArch64_LD1x2WB_4S_register, ARM64_INS_LD1, |
| 5463 | #ifndef CAPSTONE_DIET |
| 5464 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5465 | #endif |
| 5466 | }, |
| 5467 | { |
| 5468 | AArch64_LD1x2WB_8B_fixed, ARM64_INS_LD1, |
| 5469 | #ifndef CAPSTONE_DIET |
| 5470 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5471 | #endif |
| 5472 | }, |
| 5473 | { |
| 5474 | AArch64_LD1x2WB_8B_register, ARM64_INS_LD1, |
| 5475 | #ifndef CAPSTONE_DIET |
| 5476 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5477 | #endif |
| 5478 | }, |
| 5479 | { |
| 5480 | AArch64_LD1x2WB_8H_fixed, ARM64_INS_LD1, |
| 5481 | #ifndef CAPSTONE_DIET |
| 5482 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5483 | #endif |
| 5484 | }, |
| 5485 | { |
| 5486 | AArch64_LD1x2WB_8H_register, ARM64_INS_LD1, |
| 5487 | #ifndef CAPSTONE_DIET |
| 5488 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5489 | #endif |
| 5490 | }, |
| 5491 | { |
| 5492 | AArch64_LD1x2_16B, ARM64_INS_LD1, |
| 5493 | #ifndef CAPSTONE_DIET |
| 5494 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5495 | #endif |
| 5496 | }, |
| 5497 | { |
| 5498 | AArch64_LD1x2_1D, ARM64_INS_LD1, |
| 5499 | #ifndef CAPSTONE_DIET |
| 5500 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5501 | #endif |
| 5502 | }, |
| 5503 | { |
| 5504 | AArch64_LD1x2_2D, ARM64_INS_LD1, |
| 5505 | #ifndef CAPSTONE_DIET |
| 5506 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5507 | #endif |
| 5508 | }, |
| 5509 | { |
| 5510 | AArch64_LD1x2_2S, ARM64_INS_LD1, |
| 5511 | #ifndef CAPSTONE_DIET |
| 5512 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5513 | #endif |
| 5514 | }, |
| 5515 | { |
| 5516 | AArch64_LD1x2_4H, ARM64_INS_LD1, |
| 5517 | #ifndef CAPSTONE_DIET |
| 5518 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5519 | #endif |
| 5520 | }, |
| 5521 | { |
| 5522 | AArch64_LD1x2_4S, ARM64_INS_LD1, |
| 5523 | #ifndef CAPSTONE_DIET |
| 5524 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5525 | #endif |
| 5526 | }, |
| 5527 | { |
| 5528 | AArch64_LD1x2_8B, ARM64_INS_LD1, |
| 5529 | #ifndef CAPSTONE_DIET |
| 5530 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5531 | #endif |
| 5532 | }, |
| 5533 | { |
| 5534 | AArch64_LD1x2_8H, ARM64_INS_LD1, |
| 5535 | #ifndef CAPSTONE_DIET |
| 5536 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5537 | #endif |
| 5538 | }, |
| 5539 | { |
| 5540 | AArch64_LD1x3WB_16B_fixed, ARM64_INS_LD1, |
| 5541 | #ifndef CAPSTONE_DIET |
| 5542 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5543 | #endif |
| 5544 | }, |
| 5545 | { |
| 5546 | AArch64_LD1x3WB_16B_register, ARM64_INS_LD1, |
| 5547 | #ifndef CAPSTONE_DIET |
| 5548 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5549 | #endif |
| 5550 | }, |
| 5551 | { |
| 5552 | AArch64_LD1x3WB_1D_fixed, ARM64_INS_LD1, |
| 5553 | #ifndef CAPSTONE_DIET |
| 5554 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5555 | #endif |
| 5556 | }, |
| 5557 | { |
| 5558 | AArch64_LD1x3WB_1D_register, ARM64_INS_LD1, |
| 5559 | #ifndef CAPSTONE_DIET |
| 5560 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5561 | #endif |
| 5562 | }, |
| 5563 | { |
| 5564 | AArch64_LD1x3WB_2D_fixed, ARM64_INS_LD1, |
| 5565 | #ifndef CAPSTONE_DIET |
| 5566 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5567 | #endif |
| 5568 | }, |
| 5569 | { |
| 5570 | AArch64_LD1x3WB_2D_register, ARM64_INS_LD1, |
| 5571 | #ifndef CAPSTONE_DIET |
| 5572 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5573 | #endif |
| 5574 | }, |
| 5575 | { |
| 5576 | AArch64_LD1x3WB_2S_fixed, ARM64_INS_LD1, |
| 5577 | #ifndef CAPSTONE_DIET |
| 5578 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5579 | #endif |
| 5580 | }, |
| 5581 | { |
| 5582 | AArch64_LD1x3WB_2S_register, ARM64_INS_LD1, |
| 5583 | #ifndef CAPSTONE_DIET |
| 5584 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5585 | #endif |
| 5586 | }, |
| 5587 | { |
| 5588 | AArch64_LD1x3WB_4H_fixed, ARM64_INS_LD1, |
| 5589 | #ifndef CAPSTONE_DIET |
| 5590 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5591 | #endif |
| 5592 | }, |
| 5593 | { |
| 5594 | AArch64_LD1x3WB_4H_register, ARM64_INS_LD1, |
| 5595 | #ifndef CAPSTONE_DIET |
| 5596 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5597 | #endif |
| 5598 | }, |
| 5599 | { |
| 5600 | AArch64_LD1x3WB_4S_fixed, ARM64_INS_LD1, |
| 5601 | #ifndef CAPSTONE_DIET |
| 5602 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5603 | #endif |
| 5604 | }, |
| 5605 | { |
| 5606 | AArch64_LD1x3WB_4S_register, ARM64_INS_LD1, |
| 5607 | #ifndef CAPSTONE_DIET |
| 5608 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5609 | #endif |
| 5610 | }, |
| 5611 | { |
| 5612 | AArch64_LD1x3WB_8B_fixed, ARM64_INS_LD1, |
| 5613 | #ifndef CAPSTONE_DIET |
| 5614 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5615 | #endif |
| 5616 | }, |
| 5617 | { |
| 5618 | AArch64_LD1x3WB_8B_register, ARM64_INS_LD1, |
| 5619 | #ifndef CAPSTONE_DIET |
| 5620 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5621 | #endif |
| 5622 | }, |
| 5623 | { |
| 5624 | AArch64_LD1x3WB_8H_fixed, ARM64_INS_LD1, |
| 5625 | #ifndef CAPSTONE_DIET |
| 5626 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5627 | #endif |
| 5628 | }, |
| 5629 | { |
| 5630 | AArch64_LD1x3WB_8H_register, ARM64_INS_LD1, |
| 5631 | #ifndef CAPSTONE_DIET |
| 5632 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5633 | #endif |
| 5634 | }, |
| 5635 | { |
| 5636 | AArch64_LD1x3_16B, ARM64_INS_LD1, |
| 5637 | #ifndef CAPSTONE_DIET |
| 5638 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5639 | #endif |
| 5640 | }, |
| 5641 | { |
| 5642 | AArch64_LD1x3_1D, ARM64_INS_LD1, |
| 5643 | #ifndef CAPSTONE_DIET |
| 5644 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5645 | #endif |
| 5646 | }, |
| 5647 | { |
| 5648 | AArch64_LD1x3_2D, ARM64_INS_LD1, |
| 5649 | #ifndef CAPSTONE_DIET |
| 5650 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5651 | #endif |
| 5652 | }, |
| 5653 | { |
| 5654 | AArch64_LD1x3_2S, ARM64_INS_LD1, |
| 5655 | #ifndef CAPSTONE_DIET |
| 5656 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5657 | #endif |
| 5658 | }, |
| 5659 | { |
| 5660 | AArch64_LD1x3_4H, ARM64_INS_LD1, |
| 5661 | #ifndef CAPSTONE_DIET |
| 5662 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5663 | #endif |
| 5664 | }, |
| 5665 | { |
| 5666 | AArch64_LD1x3_4S, ARM64_INS_LD1, |
| 5667 | #ifndef CAPSTONE_DIET |
| 5668 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5669 | #endif |
| 5670 | }, |
| 5671 | { |
| 5672 | AArch64_LD1x3_8B, ARM64_INS_LD1, |
| 5673 | #ifndef CAPSTONE_DIET |
| 5674 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5675 | #endif |
| 5676 | }, |
| 5677 | { |
| 5678 | AArch64_LD1x3_8H, ARM64_INS_LD1, |
| 5679 | #ifndef CAPSTONE_DIET |
| 5680 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5681 | #endif |
| 5682 | }, |
| 5683 | { |
| 5684 | AArch64_LD1x4WB_16B_fixed, ARM64_INS_LD1, |
| 5685 | #ifndef CAPSTONE_DIET |
| 5686 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5687 | #endif |
| 5688 | }, |
| 5689 | { |
| 5690 | AArch64_LD1x4WB_16B_register, ARM64_INS_LD1, |
| 5691 | #ifndef CAPSTONE_DIET |
| 5692 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5693 | #endif |
| 5694 | }, |
| 5695 | { |
| 5696 | AArch64_LD1x4WB_1D_fixed, ARM64_INS_LD1, |
| 5697 | #ifndef CAPSTONE_DIET |
| 5698 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5699 | #endif |
| 5700 | }, |
| 5701 | { |
| 5702 | AArch64_LD1x4WB_1D_register, ARM64_INS_LD1, |
| 5703 | #ifndef CAPSTONE_DIET |
| 5704 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5705 | #endif |
| 5706 | }, |
| 5707 | { |
| 5708 | AArch64_LD1x4WB_2D_fixed, ARM64_INS_LD1, |
| 5709 | #ifndef CAPSTONE_DIET |
| 5710 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5711 | #endif |
| 5712 | }, |
| 5713 | { |
| 5714 | AArch64_LD1x4WB_2D_register, ARM64_INS_LD1, |
| 5715 | #ifndef CAPSTONE_DIET |
| 5716 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5717 | #endif |
| 5718 | }, |
| 5719 | { |
| 5720 | AArch64_LD1x4WB_2S_fixed, ARM64_INS_LD1, |
| 5721 | #ifndef CAPSTONE_DIET |
| 5722 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5723 | #endif |
| 5724 | }, |
| 5725 | { |
| 5726 | AArch64_LD1x4WB_2S_register, ARM64_INS_LD1, |
| 5727 | #ifndef CAPSTONE_DIET |
| 5728 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5729 | #endif |
| 5730 | }, |
| 5731 | { |
| 5732 | AArch64_LD1x4WB_4H_fixed, ARM64_INS_LD1, |
| 5733 | #ifndef CAPSTONE_DIET |
| 5734 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5735 | #endif |
| 5736 | }, |
| 5737 | { |
| 5738 | AArch64_LD1x4WB_4H_register, ARM64_INS_LD1, |
| 5739 | #ifndef CAPSTONE_DIET |
| 5740 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5741 | #endif |
| 5742 | }, |
| 5743 | { |
| 5744 | AArch64_LD1x4WB_4S_fixed, ARM64_INS_LD1, |
| 5745 | #ifndef CAPSTONE_DIET |
| 5746 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5747 | #endif |
| 5748 | }, |
| 5749 | { |
| 5750 | AArch64_LD1x4WB_4S_register, ARM64_INS_LD1, |
| 5751 | #ifndef CAPSTONE_DIET |
| 5752 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5753 | #endif |
| 5754 | }, |
| 5755 | { |
| 5756 | AArch64_LD1x4WB_8B_fixed, ARM64_INS_LD1, |
| 5757 | #ifndef CAPSTONE_DIET |
| 5758 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5759 | #endif |
| 5760 | }, |
| 5761 | { |
| 5762 | AArch64_LD1x4WB_8B_register, ARM64_INS_LD1, |
| 5763 | #ifndef CAPSTONE_DIET |
| 5764 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5765 | #endif |
| 5766 | }, |
| 5767 | { |
| 5768 | AArch64_LD1x4WB_8H_fixed, ARM64_INS_LD1, |
| 5769 | #ifndef CAPSTONE_DIET |
| 5770 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5771 | #endif |
| 5772 | }, |
| 5773 | { |
| 5774 | AArch64_LD1x4WB_8H_register, ARM64_INS_LD1, |
| 5775 | #ifndef CAPSTONE_DIET |
| 5776 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5777 | #endif |
| 5778 | }, |
| 5779 | { |
| 5780 | AArch64_LD1x4_16B, ARM64_INS_LD1, |
| 5781 | #ifndef CAPSTONE_DIET |
| 5782 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5783 | #endif |
| 5784 | }, |
| 5785 | { |
| 5786 | AArch64_LD1x4_1D, ARM64_INS_LD1, |
| 5787 | #ifndef CAPSTONE_DIET |
| 5788 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5789 | #endif |
| 5790 | }, |
| 5791 | { |
| 5792 | AArch64_LD1x4_2D, ARM64_INS_LD1, |
| 5793 | #ifndef CAPSTONE_DIET |
| 5794 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5795 | #endif |
| 5796 | }, |
| 5797 | { |
| 5798 | AArch64_LD1x4_2S, ARM64_INS_LD1, |
| 5799 | #ifndef CAPSTONE_DIET |
| 5800 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5801 | #endif |
| 5802 | }, |
| 5803 | { |
| 5804 | AArch64_LD1x4_4H, ARM64_INS_LD1, |
| 5805 | #ifndef CAPSTONE_DIET |
| 5806 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5807 | #endif |
| 5808 | }, |
| 5809 | { |
| 5810 | AArch64_LD1x4_4S, ARM64_INS_LD1, |
| 5811 | #ifndef CAPSTONE_DIET |
| 5812 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5813 | #endif |
| 5814 | }, |
| 5815 | { |
| 5816 | AArch64_LD1x4_8B, ARM64_INS_LD1, |
| 5817 | #ifndef CAPSTONE_DIET |
| 5818 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5819 | #endif |
| 5820 | }, |
| 5821 | { |
| 5822 | AArch64_LD1x4_8H, ARM64_INS_LD1, |
| 5823 | #ifndef CAPSTONE_DIET |
| 5824 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5825 | #endif |
| 5826 | }, |
| 5827 | { |
| 5828 | AArch64_LD2LN_B, ARM64_INS_LD2, |
| 5829 | #ifndef CAPSTONE_DIET |
| 5830 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5831 | #endif |
| 5832 | }, |
| 5833 | { |
| 5834 | AArch64_LD2LN_D, ARM64_INS_LD2, |
| 5835 | #ifndef CAPSTONE_DIET |
| 5836 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5837 | #endif |
| 5838 | }, |
| 5839 | { |
| 5840 | AArch64_LD2LN_H, ARM64_INS_LD2, |
| 5841 | #ifndef CAPSTONE_DIET |
| 5842 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5843 | #endif |
| 5844 | }, |
| 5845 | { |
| 5846 | AArch64_LD2LN_S, ARM64_INS_LD2, |
| 5847 | #ifndef CAPSTONE_DIET |
| 5848 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5849 | #endif |
| 5850 | }, |
| 5851 | { |
| 5852 | AArch64_LD2LN_WB_B_fixed, ARM64_INS_LD2, |
| 5853 | #ifndef CAPSTONE_DIET |
| 5854 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5855 | #endif |
| 5856 | }, |
| 5857 | { |
| 5858 | AArch64_LD2LN_WB_B_register, ARM64_INS_LD2, |
| 5859 | #ifndef CAPSTONE_DIET |
| 5860 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5861 | #endif |
| 5862 | }, |
| 5863 | { |
| 5864 | AArch64_LD2LN_WB_D_fixed, ARM64_INS_LD2, |
| 5865 | #ifndef CAPSTONE_DIET |
| 5866 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5867 | #endif |
| 5868 | }, |
| 5869 | { |
| 5870 | AArch64_LD2LN_WB_D_register, ARM64_INS_LD2, |
| 5871 | #ifndef CAPSTONE_DIET |
| 5872 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5873 | #endif |
| 5874 | }, |
| 5875 | { |
| 5876 | AArch64_LD2LN_WB_H_fixed, ARM64_INS_LD2, |
| 5877 | #ifndef CAPSTONE_DIET |
| 5878 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5879 | #endif |
| 5880 | }, |
| 5881 | { |
| 5882 | AArch64_LD2LN_WB_H_register, ARM64_INS_LD2, |
| 5883 | #ifndef CAPSTONE_DIET |
| 5884 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5885 | #endif |
| 5886 | }, |
| 5887 | { |
| 5888 | AArch64_LD2LN_WB_S_fixed, ARM64_INS_LD2, |
| 5889 | #ifndef CAPSTONE_DIET |
| 5890 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5891 | #endif |
| 5892 | }, |
| 5893 | { |
| 5894 | AArch64_LD2LN_WB_S_register, ARM64_INS_LD2, |
| 5895 | #ifndef CAPSTONE_DIET |
| 5896 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5897 | #endif |
| 5898 | }, |
| 5899 | { |
| 5900 | AArch64_LD2R_16B, ARM64_INS_LD2R, |
| 5901 | #ifndef CAPSTONE_DIET |
| 5902 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5903 | #endif |
| 5904 | }, |
| 5905 | { |
| 5906 | AArch64_LD2R_1D, ARM64_INS_LD2R, |
| 5907 | #ifndef CAPSTONE_DIET |
| 5908 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5909 | #endif |
| 5910 | }, |
| 5911 | { |
| 5912 | AArch64_LD2R_2D, ARM64_INS_LD2R, |
| 5913 | #ifndef CAPSTONE_DIET |
| 5914 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5915 | #endif |
| 5916 | }, |
| 5917 | { |
| 5918 | AArch64_LD2R_2S, ARM64_INS_LD2R, |
| 5919 | #ifndef CAPSTONE_DIET |
| 5920 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5921 | #endif |
| 5922 | }, |
| 5923 | { |
| 5924 | AArch64_LD2R_4H, ARM64_INS_LD2R, |
| 5925 | #ifndef CAPSTONE_DIET |
| 5926 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5927 | #endif |
| 5928 | }, |
| 5929 | { |
| 5930 | AArch64_LD2R_4S, ARM64_INS_LD2R, |
| 5931 | #ifndef CAPSTONE_DIET |
| 5932 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5933 | #endif |
| 5934 | }, |
| 5935 | { |
| 5936 | AArch64_LD2R_8B, ARM64_INS_LD2R, |
| 5937 | #ifndef CAPSTONE_DIET |
| 5938 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5939 | #endif |
| 5940 | }, |
| 5941 | { |
| 5942 | AArch64_LD2R_8H, ARM64_INS_LD2R, |
| 5943 | #ifndef CAPSTONE_DIET |
| 5944 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5945 | #endif |
| 5946 | }, |
| 5947 | { |
| 5948 | AArch64_LD2R_WB_16B_fixed, ARM64_INS_LD2R, |
| 5949 | #ifndef CAPSTONE_DIET |
| 5950 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5951 | #endif |
| 5952 | }, |
| 5953 | { |
| 5954 | AArch64_LD2R_WB_16B_register, ARM64_INS_LD2R, |
| 5955 | #ifndef CAPSTONE_DIET |
| 5956 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5957 | #endif |
| 5958 | }, |
| 5959 | { |
| 5960 | AArch64_LD2R_WB_1D_fixed, ARM64_INS_LD2R, |
| 5961 | #ifndef CAPSTONE_DIET |
| 5962 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5963 | #endif |
| 5964 | }, |
| 5965 | { |
| 5966 | AArch64_LD2R_WB_1D_register, ARM64_INS_LD2R, |
| 5967 | #ifndef CAPSTONE_DIET |
| 5968 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5969 | #endif |
| 5970 | }, |
| 5971 | { |
| 5972 | AArch64_LD2R_WB_2D_fixed, ARM64_INS_LD2R, |
| 5973 | #ifndef CAPSTONE_DIET |
| 5974 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5975 | #endif |
| 5976 | }, |
| 5977 | { |
| 5978 | AArch64_LD2R_WB_2D_register, ARM64_INS_LD2R, |
| 5979 | #ifndef CAPSTONE_DIET |
| 5980 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5981 | #endif |
| 5982 | }, |
| 5983 | { |
| 5984 | AArch64_LD2R_WB_2S_fixed, ARM64_INS_LD2R, |
| 5985 | #ifndef CAPSTONE_DIET |
| 5986 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5987 | #endif |
| 5988 | }, |
| 5989 | { |
| 5990 | AArch64_LD2R_WB_2S_register, ARM64_INS_LD2R, |
| 5991 | #ifndef CAPSTONE_DIET |
| 5992 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5993 | #endif |
| 5994 | }, |
| 5995 | { |
| 5996 | AArch64_LD2R_WB_4H_fixed, ARM64_INS_LD2R, |
| 5997 | #ifndef CAPSTONE_DIET |
| 5998 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 5999 | #endif |
| 6000 | }, |
| 6001 | { |
| 6002 | AArch64_LD2R_WB_4H_register, ARM64_INS_LD2R, |
| 6003 | #ifndef CAPSTONE_DIET |
| 6004 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6005 | #endif |
| 6006 | }, |
| 6007 | { |
| 6008 | AArch64_LD2R_WB_4S_fixed, ARM64_INS_LD2R, |
| 6009 | #ifndef CAPSTONE_DIET |
| 6010 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6011 | #endif |
| 6012 | }, |
| 6013 | { |
| 6014 | AArch64_LD2R_WB_4S_register, ARM64_INS_LD2R, |
| 6015 | #ifndef CAPSTONE_DIET |
| 6016 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6017 | #endif |
| 6018 | }, |
| 6019 | { |
| 6020 | AArch64_LD2R_WB_8B_fixed, ARM64_INS_LD2R, |
| 6021 | #ifndef CAPSTONE_DIET |
| 6022 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6023 | #endif |
| 6024 | }, |
| 6025 | { |
| 6026 | AArch64_LD2R_WB_8B_register, ARM64_INS_LD2R, |
| 6027 | #ifndef CAPSTONE_DIET |
| 6028 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6029 | #endif |
| 6030 | }, |
| 6031 | { |
| 6032 | AArch64_LD2R_WB_8H_fixed, ARM64_INS_LD2R, |
| 6033 | #ifndef CAPSTONE_DIET |
| 6034 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6035 | #endif |
| 6036 | }, |
| 6037 | { |
| 6038 | AArch64_LD2R_WB_8H_register, ARM64_INS_LD2R, |
| 6039 | #ifndef CAPSTONE_DIET |
| 6040 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6041 | #endif |
| 6042 | }, |
| 6043 | { |
| 6044 | AArch64_LD2WB_16B_fixed, ARM64_INS_LD2, |
| 6045 | #ifndef CAPSTONE_DIET |
| 6046 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6047 | #endif |
| 6048 | }, |
| 6049 | { |
| 6050 | AArch64_LD2WB_16B_register, ARM64_INS_LD2, |
| 6051 | #ifndef CAPSTONE_DIET |
| 6052 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6053 | #endif |
| 6054 | }, |
| 6055 | { |
| 6056 | AArch64_LD2WB_2D_fixed, ARM64_INS_LD2, |
| 6057 | #ifndef CAPSTONE_DIET |
| 6058 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6059 | #endif |
| 6060 | }, |
| 6061 | { |
| 6062 | AArch64_LD2WB_2D_register, ARM64_INS_LD2, |
| 6063 | #ifndef CAPSTONE_DIET |
| 6064 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6065 | #endif |
| 6066 | }, |
| 6067 | { |
| 6068 | AArch64_LD2WB_2S_fixed, ARM64_INS_LD2, |
| 6069 | #ifndef CAPSTONE_DIET |
| 6070 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6071 | #endif |
| 6072 | }, |
| 6073 | { |
| 6074 | AArch64_LD2WB_2S_register, ARM64_INS_LD2, |
| 6075 | #ifndef CAPSTONE_DIET |
| 6076 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6077 | #endif |
| 6078 | }, |
| 6079 | { |
| 6080 | AArch64_LD2WB_4H_fixed, ARM64_INS_LD2, |
| 6081 | #ifndef CAPSTONE_DIET |
| 6082 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6083 | #endif |
| 6084 | }, |
| 6085 | { |
| 6086 | AArch64_LD2WB_4H_register, ARM64_INS_LD2, |
| 6087 | #ifndef CAPSTONE_DIET |
| 6088 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6089 | #endif |
| 6090 | }, |
| 6091 | { |
| 6092 | AArch64_LD2WB_4S_fixed, ARM64_INS_LD2, |
| 6093 | #ifndef CAPSTONE_DIET |
| 6094 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6095 | #endif |
| 6096 | }, |
| 6097 | { |
| 6098 | AArch64_LD2WB_4S_register, ARM64_INS_LD2, |
| 6099 | #ifndef CAPSTONE_DIET |
| 6100 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6101 | #endif |
| 6102 | }, |
| 6103 | { |
| 6104 | AArch64_LD2WB_8B_fixed, ARM64_INS_LD2, |
| 6105 | #ifndef CAPSTONE_DIET |
| 6106 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6107 | #endif |
| 6108 | }, |
| 6109 | { |
| 6110 | AArch64_LD2WB_8B_register, ARM64_INS_LD2, |
| 6111 | #ifndef CAPSTONE_DIET |
| 6112 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6113 | #endif |
| 6114 | }, |
| 6115 | { |
| 6116 | AArch64_LD2WB_8H_fixed, ARM64_INS_LD2, |
| 6117 | #ifndef CAPSTONE_DIET |
| 6118 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6119 | #endif |
| 6120 | }, |
| 6121 | { |
| 6122 | AArch64_LD2WB_8H_register, ARM64_INS_LD2, |
| 6123 | #ifndef CAPSTONE_DIET |
| 6124 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6125 | #endif |
| 6126 | }, |
| 6127 | { |
| 6128 | AArch64_LD2_16B, ARM64_INS_LD2, |
| 6129 | #ifndef CAPSTONE_DIET |
| 6130 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6131 | #endif |
| 6132 | }, |
| 6133 | { |
| 6134 | AArch64_LD2_2D, ARM64_INS_LD2, |
| 6135 | #ifndef CAPSTONE_DIET |
| 6136 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6137 | #endif |
| 6138 | }, |
| 6139 | { |
| 6140 | AArch64_LD2_2S, ARM64_INS_LD2, |
| 6141 | #ifndef CAPSTONE_DIET |
| 6142 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6143 | #endif |
| 6144 | }, |
| 6145 | { |
| 6146 | AArch64_LD2_4H, ARM64_INS_LD2, |
| 6147 | #ifndef CAPSTONE_DIET |
| 6148 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6149 | #endif |
| 6150 | }, |
| 6151 | { |
| 6152 | AArch64_LD2_4S, ARM64_INS_LD2, |
| 6153 | #ifndef CAPSTONE_DIET |
| 6154 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6155 | #endif |
| 6156 | }, |
| 6157 | { |
| 6158 | AArch64_LD2_8B, ARM64_INS_LD2, |
| 6159 | #ifndef CAPSTONE_DIET |
| 6160 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6161 | #endif |
| 6162 | }, |
| 6163 | { |
| 6164 | AArch64_LD2_8H, ARM64_INS_LD2, |
| 6165 | #ifndef CAPSTONE_DIET |
| 6166 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6167 | #endif |
| 6168 | }, |
| 6169 | { |
| 6170 | AArch64_LD3LN_B, ARM64_INS_LD3, |
| 6171 | #ifndef CAPSTONE_DIET |
| 6172 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6173 | #endif |
| 6174 | }, |
| 6175 | { |
| 6176 | AArch64_LD3LN_D, ARM64_INS_LD3, |
| 6177 | #ifndef CAPSTONE_DIET |
| 6178 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6179 | #endif |
| 6180 | }, |
| 6181 | { |
| 6182 | AArch64_LD3LN_H, ARM64_INS_LD3, |
| 6183 | #ifndef CAPSTONE_DIET |
| 6184 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6185 | #endif |
| 6186 | }, |
| 6187 | { |
| 6188 | AArch64_LD3LN_S, ARM64_INS_LD3, |
| 6189 | #ifndef CAPSTONE_DIET |
| 6190 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6191 | #endif |
| 6192 | }, |
| 6193 | { |
| 6194 | AArch64_LD3LN_WB_B_fixed, ARM64_INS_LD3, |
| 6195 | #ifndef CAPSTONE_DIET |
| 6196 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6197 | #endif |
| 6198 | }, |
| 6199 | { |
| 6200 | AArch64_LD3LN_WB_B_register, ARM64_INS_LD3, |
| 6201 | #ifndef CAPSTONE_DIET |
| 6202 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6203 | #endif |
| 6204 | }, |
| 6205 | { |
| 6206 | AArch64_LD3LN_WB_D_fixed, ARM64_INS_LD3, |
| 6207 | #ifndef CAPSTONE_DIET |
| 6208 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6209 | #endif |
| 6210 | }, |
| 6211 | { |
| 6212 | AArch64_LD3LN_WB_D_register, ARM64_INS_LD3, |
| 6213 | #ifndef CAPSTONE_DIET |
| 6214 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6215 | #endif |
| 6216 | }, |
| 6217 | { |
| 6218 | AArch64_LD3LN_WB_H_fixed, ARM64_INS_LD3, |
| 6219 | #ifndef CAPSTONE_DIET |
| 6220 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6221 | #endif |
| 6222 | }, |
| 6223 | { |
| 6224 | AArch64_LD3LN_WB_H_register, ARM64_INS_LD3, |
| 6225 | #ifndef CAPSTONE_DIET |
| 6226 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6227 | #endif |
| 6228 | }, |
| 6229 | { |
| 6230 | AArch64_LD3LN_WB_S_fixed, ARM64_INS_LD3, |
| 6231 | #ifndef CAPSTONE_DIET |
| 6232 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6233 | #endif |
| 6234 | }, |
| 6235 | { |
| 6236 | AArch64_LD3LN_WB_S_register, ARM64_INS_LD3, |
| 6237 | #ifndef CAPSTONE_DIET |
| 6238 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6239 | #endif |
| 6240 | }, |
| 6241 | { |
| 6242 | AArch64_LD3R_16B, ARM64_INS_LD3R, |
| 6243 | #ifndef CAPSTONE_DIET |
| 6244 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6245 | #endif |
| 6246 | }, |
| 6247 | { |
| 6248 | AArch64_LD3R_1D, ARM64_INS_LD3R, |
| 6249 | #ifndef CAPSTONE_DIET |
| 6250 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6251 | #endif |
| 6252 | }, |
| 6253 | { |
| 6254 | AArch64_LD3R_2D, ARM64_INS_LD3R, |
| 6255 | #ifndef CAPSTONE_DIET |
| 6256 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6257 | #endif |
| 6258 | }, |
| 6259 | { |
| 6260 | AArch64_LD3R_2S, ARM64_INS_LD3R, |
| 6261 | #ifndef CAPSTONE_DIET |
| 6262 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6263 | #endif |
| 6264 | }, |
| 6265 | { |
| 6266 | AArch64_LD3R_4H, ARM64_INS_LD3R, |
| 6267 | #ifndef CAPSTONE_DIET |
| 6268 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6269 | #endif |
| 6270 | }, |
| 6271 | { |
| 6272 | AArch64_LD3R_4S, ARM64_INS_LD3R, |
| 6273 | #ifndef CAPSTONE_DIET |
| 6274 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6275 | #endif |
| 6276 | }, |
| 6277 | { |
| 6278 | AArch64_LD3R_8B, ARM64_INS_LD3R, |
| 6279 | #ifndef CAPSTONE_DIET |
| 6280 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6281 | #endif |
| 6282 | }, |
| 6283 | { |
| 6284 | AArch64_LD3R_8H, ARM64_INS_LD3R, |
| 6285 | #ifndef CAPSTONE_DIET |
| 6286 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6287 | #endif |
| 6288 | }, |
| 6289 | { |
| 6290 | AArch64_LD3R_WB_16B_fixed, ARM64_INS_LD3R, |
| 6291 | #ifndef CAPSTONE_DIET |
| 6292 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6293 | #endif |
| 6294 | }, |
| 6295 | { |
| 6296 | AArch64_LD3R_WB_16B_register, ARM64_INS_LD3R, |
| 6297 | #ifndef CAPSTONE_DIET |
| 6298 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6299 | #endif |
| 6300 | }, |
| 6301 | { |
| 6302 | AArch64_LD3R_WB_1D_fixed, ARM64_INS_LD3R, |
| 6303 | #ifndef CAPSTONE_DIET |
| 6304 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6305 | #endif |
| 6306 | }, |
| 6307 | { |
| 6308 | AArch64_LD3R_WB_1D_register, ARM64_INS_LD3R, |
| 6309 | #ifndef CAPSTONE_DIET |
| 6310 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6311 | #endif |
| 6312 | }, |
| 6313 | { |
| 6314 | AArch64_LD3R_WB_2D_fixed, ARM64_INS_LD3R, |
| 6315 | #ifndef CAPSTONE_DIET |
| 6316 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6317 | #endif |
| 6318 | }, |
| 6319 | { |
| 6320 | AArch64_LD3R_WB_2D_register, ARM64_INS_LD3R, |
| 6321 | #ifndef CAPSTONE_DIET |
| 6322 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6323 | #endif |
| 6324 | }, |
| 6325 | { |
| 6326 | AArch64_LD3R_WB_2S_fixed, ARM64_INS_LD3R, |
| 6327 | #ifndef CAPSTONE_DIET |
| 6328 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6329 | #endif |
| 6330 | }, |
| 6331 | { |
| 6332 | AArch64_LD3R_WB_2S_register, ARM64_INS_LD3R, |
| 6333 | #ifndef CAPSTONE_DIET |
| 6334 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6335 | #endif |
| 6336 | }, |
| 6337 | { |
| 6338 | AArch64_LD3R_WB_4H_fixed, ARM64_INS_LD3R, |
| 6339 | #ifndef CAPSTONE_DIET |
| 6340 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6341 | #endif |
| 6342 | }, |
| 6343 | { |
| 6344 | AArch64_LD3R_WB_4H_register, ARM64_INS_LD3R, |
| 6345 | #ifndef CAPSTONE_DIET |
| 6346 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6347 | #endif |
| 6348 | }, |
| 6349 | { |
| 6350 | AArch64_LD3R_WB_4S_fixed, ARM64_INS_LD3R, |
| 6351 | #ifndef CAPSTONE_DIET |
| 6352 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6353 | #endif |
| 6354 | }, |
| 6355 | { |
| 6356 | AArch64_LD3R_WB_4S_register, ARM64_INS_LD3R, |
| 6357 | #ifndef CAPSTONE_DIET |
| 6358 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6359 | #endif |
| 6360 | }, |
| 6361 | { |
| 6362 | AArch64_LD3R_WB_8B_fixed, ARM64_INS_LD3R, |
| 6363 | #ifndef CAPSTONE_DIET |
| 6364 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6365 | #endif |
| 6366 | }, |
| 6367 | { |
| 6368 | AArch64_LD3R_WB_8B_register, ARM64_INS_LD3R, |
| 6369 | #ifndef CAPSTONE_DIET |
| 6370 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6371 | #endif |
| 6372 | }, |
| 6373 | { |
| 6374 | AArch64_LD3R_WB_8H_fixed, ARM64_INS_LD3R, |
| 6375 | #ifndef CAPSTONE_DIET |
| 6376 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6377 | #endif |
| 6378 | }, |
| 6379 | { |
| 6380 | AArch64_LD3R_WB_8H_register, ARM64_INS_LD3R, |
| 6381 | #ifndef CAPSTONE_DIET |
| 6382 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6383 | #endif |
| 6384 | }, |
| 6385 | { |
| 6386 | AArch64_LD3WB_16B_fixed, ARM64_INS_LD3, |
| 6387 | #ifndef CAPSTONE_DIET |
| 6388 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6389 | #endif |
| 6390 | }, |
| 6391 | { |
| 6392 | AArch64_LD3WB_16B_register, ARM64_INS_LD3, |
| 6393 | #ifndef CAPSTONE_DIET |
| 6394 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6395 | #endif |
| 6396 | }, |
| 6397 | { |
| 6398 | AArch64_LD3WB_2D_fixed, ARM64_INS_LD3, |
| 6399 | #ifndef CAPSTONE_DIET |
| 6400 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6401 | #endif |
| 6402 | }, |
| 6403 | { |
| 6404 | AArch64_LD3WB_2D_register, ARM64_INS_LD3, |
| 6405 | #ifndef CAPSTONE_DIET |
| 6406 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6407 | #endif |
| 6408 | }, |
| 6409 | { |
| 6410 | AArch64_LD3WB_2S_fixed, ARM64_INS_LD3, |
| 6411 | #ifndef CAPSTONE_DIET |
| 6412 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6413 | #endif |
| 6414 | }, |
| 6415 | { |
| 6416 | AArch64_LD3WB_2S_register, ARM64_INS_LD3, |
| 6417 | #ifndef CAPSTONE_DIET |
| 6418 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6419 | #endif |
| 6420 | }, |
| 6421 | { |
| 6422 | AArch64_LD3WB_4H_fixed, ARM64_INS_LD3, |
| 6423 | #ifndef CAPSTONE_DIET |
| 6424 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6425 | #endif |
| 6426 | }, |
| 6427 | { |
| 6428 | AArch64_LD3WB_4H_register, ARM64_INS_LD3, |
| 6429 | #ifndef CAPSTONE_DIET |
| 6430 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6431 | #endif |
| 6432 | }, |
| 6433 | { |
| 6434 | AArch64_LD3WB_4S_fixed, ARM64_INS_LD3, |
| 6435 | #ifndef CAPSTONE_DIET |
| 6436 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6437 | #endif |
| 6438 | }, |
| 6439 | { |
| 6440 | AArch64_LD3WB_4S_register, ARM64_INS_LD3, |
| 6441 | #ifndef CAPSTONE_DIET |
| 6442 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6443 | #endif |
| 6444 | }, |
| 6445 | { |
| 6446 | AArch64_LD3WB_8B_fixed, ARM64_INS_LD3, |
| 6447 | #ifndef CAPSTONE_DIET |
| 6448 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6449 | #endif |
| 6450 | }, |
| 6451 | { |
| 6452 | AArch64_LD3WB_8B_register, ARM64_INS_LD3, |
| 6453 | #ifndef CAPSTONE_DIET |
| 6454 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6455 | #endif |
| 6456 | }, |
| 6457 | { |
| 6458 | AArch64_LD3WB_8H_fixed, ARM64_INS_LD3, |
| 6459 | #ifndef CAPSTONE_DIET |
| 6460 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6461 | #endif |
| 6462 | }, |
| 6463 | { |
| 6464 | AArch64_LD3WB_8H_register, ARM64_INS_LD3, |
| 6465 | #ifndef CAPSTONE_DIET |
| 6466 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6467 | #endif |
| 6468 | }, |
| 6469 | { |
| 6470 | AArch64_LD3_16B, ARM64_INS_LD3, |
| 6471 | #ifndef CAPSTONE_DIET |
| 6472 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6473 | #endif |
| 6474 | }, |
| 6475 | { |
| 6476 | AArch64_LD3_2D, ARM64_INS_LD3, |
| 6477 | #ifndef CAPSTONE_DIET |
| 6478 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6479 | #endif |
| 6480 | }, |
| 6481 | { |
| 6482 | AArch64_LD3_2S, ARM64_INS_LD3, |
| 6483 | #ifndef CAPSTONE_DIET |
| 6484 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6485 | #endif |
| 6486 | }, |
| 6487 | { |
| 6488 | AArch64_LD3_4H, ARM64_INS_LD3, |
| 6489 | #ifndef CAPSTONE_DIET |
| 6490 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6491 | #endif |
| 6492 | }, |
| 6493 | { |
| 6494 | AArch64_LD3_4S, ARM64_INS_LD3, |
| 6495 | #ifndef CAPSTONE_DIET |
| 6496 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6497 | #endif |
| 6498 | }, |
| 6499 | { |
| 6500 | AArch64_LD3_8B, ARM64_INS_LD3, |
| 6501 | #ifndef CAPSTONE_DIET |
| 6502 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6503 | #endif |
| 6504 | }, |
| 6505 | { |
| 6506 | AArch64_LD3_8H, ARM64_INS_LD3, |
| 6507 | #ifndef CAPSTONE_DIET |
| 6508 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6509 | #endif |
| 6510 | }, |
| 6511 | { |
| 6512 | AArch64_LD4LN_B, ARM64_INS_LD4, |
| 6513 | #ifndef CAPSTONE_DIET |
| 6514 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6515 | #endif |
| 6516 | }, |
| 6517 | { |
| 6518 | AArch64_LD4LN_D, ARM64_INS_LD4, |
| 6519 | #ifndef CAPSTONE_DIET |
| 6520 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6521 | #endif |
| 6522 | }, |
| 6523 | { |
| 6524 | AArch64_LD4LN_H, ARM64_INS_LD4, |
| 6525 | #ifndef CAPSTONE_DIET |
| 6526 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6527 | #endif |
| 6528 | }, |
| 6529 | { |
| 6530 | AArch64_LD4LN_S, ARM64_INS_LD4, |
| 6531 | #ifndef CAPSTONE_DIET |
| 6532 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6533 | #endif |
| 6534 | }, |
| 6535 | { |
| 6536 | AArch64_LD4LN_WB_B_fixed, ARM64_INS_LD4, |
| 6537 | #ifndef CAPSTONE_DIET |
| 6538 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6539 | #endif |
| 6540 | }, |
| 6541 | { |
| 6542 | AArch64_LD4LN_WB_B_register, ARM64_INS_LD4, |
| 6543 | #ifndef CAPSTONE_DIET |
| 6544 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6545 | #endif |
| 6546 | }, |
| 6547 | { |
| 6548 | AArch64_LD4LN_WB_D_fixed, ARM64_INS_LD4, |
| 6549 | #ifndef CAPSTONE_DIET |
| 6550 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6551 | #endif |
| 6552 | }, |
| 6553 | { |
| 6554 | AArch64_LD4LN_WB_D_register, ARM64_INS_LD4, |
| 6555 | #ifndef CAPSTONE_DIET |
| 6556 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6557 | #endif |
| 6558 | }, |
| 6559 | { |
| 6560 | AArch64_LD4LN_WB_H_fixed, ARM64_INS_LD4, |
| 6561 | #ifndef CAPSTONE_DIET |
| 6562 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6563 | #endif |
| 6564 | }, |
| 6565 | { |
| 6566 | AArch64_LD4LN_WB_H_register, ARM64_INS_LD4, |
| 6567 | #ifndef CAPSTONE_DIET |
| 6568 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6569 | #endif |
| 6570 | }, |
| 6571 | { |
| 6572 | AArch64_LD4LN_WB_S_fixed, ARM64_INS_LD4, |
| 6573 | #ifndef CAPSTONE_DIET |
| 6574 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6575 | #endif |
| 6576 | }, |
| 6577 | { |
| 6578 | AArch64_LD4LN_WB_S_register, ARM64_INS_LD4, |
| 6579 | #ifndef CAPSTONE_DIET |
| 6580 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6581 | #endif |
| 6582 | }, |
| 6583 | { |
| 6584 | AArch64_LD4R_16B, ARM64_INS_LD4R, |
| 6585 | #ifndef CAPSTONE_DIET |
| 6586 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6587 | #endif |
| 6588 | }, |
| 6589 | { |
| 6590 | AArch64_LD4R_1D, ARM64_INS_LD4R, |
| 6591 | #ifndef CAPSTONE_DIET |
| 6592 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6593 | #endif |
| 6594 | }, |
| 6595 | { |
| 6596 | AArch64_LD4R_2D, ARM64_INS_LD4R, |
| 6597 | #ifndef CAPSTONE_DIET |
| 6598 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6599 | #endif |
| 6600 | }, |
| 6601 | { |
| 6602 | AArch64_LD4R_2S, ARM64_INS_LD4R, |
| 6603 | #ifndef CAPSTONE_DIET |
| 6604 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6605 | #endif |
| 6606 | }, |
| 6607 | { |
| 6608 | AArch64_LD4R_4H, ARM64_INS_LD4R, |
| 6609 | #ifndef CAPSTONE_DIET |
| 6610 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6611 | #endif |
| 6612 | }, |
| 6613 | { |
| 6614 | AArch64_LD4R_4S, ARM64_INS_LD4R, |
| 6615 | #ifndef CAPSTONE_DIET |
| 6616 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6617 | #endif |
| 6618 | }, |
| 6619 | { |
| 6620 | AArch64_LD4R_8B, ARM64_INS_LD4R, |
| 6621 | #ifndef CAPSTONE_DIET |
| 6622 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6623 | #endif |
| 6624 | }, |
| 6625 | { |
| 6626 | AArch64_LD4R_8H, ARM64_INS_LD4R, |
| 6627 | #ifndef CAPSTONE_DIET |
| 6628 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6629 | #endif |
| 6630 | }, |
| 6631 | { |
| 6632 | AArch64_LD4R_WB_16B_fixed, ARM64_INS_LD4R, |
| 6633 | #ifndef CAPSTONE_DIET |
| 6634 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6635 | #endif |
| 6636 | }, |
| 6637 | { |
| 6638 | AArch64_LD4R_WB_16B_register, ARM64_INS_LD4R, |
| 6639 | #ifndef CAPSTONE_DIET |
| 6640 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6641 | #endif |
| 6642 | }, |
| 6643 | { |
| 6644 | AArch64_LD4R_WB_1D_fixed, ARM64_INS_LD4R, |
| 6645 | #ifndef CAPSTONE_DIET |
| 6646 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6647 | #endif |
| 6648 | }, |
| 6649 | { |
| 6650 | AArch64_LD4R_WB_1D_register, ARM64_INS_LD4R, |
| 6651 | #ifndef CAPSTONE_DIET |
| 6652 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6653 | #endif |
| 6654 | }, |
| 6655 | { |
| 6656 | AArch64_LD4R_WB_2D_fixed, ARM64_INS_LD4R, |
| 6657 | #ifndef CAPSTONE_DIET |
| 6658 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6659 | #endif |
| 6660 | }, |
| 6661 | { |
| 6662 | AArch64_LD4R_WB_2D_register, ARM64_INS_LD4R, |
| 6663 | #ifndef CAPSTONE_DIET |
| 6664 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6665 | #endif |
| 6666 | }, |
| 6667 | { |
| 6668 | AArch64_LD4R_WB_2S_fixed, ARM64_INS_LD4R, |
| 6669 | #ifndef CAPSTONE_DIET |
| 6670 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6671 | #endif |
| 6672 | }, |
| 6673 | { |
| 6674 | AArch64_LD4R_WB_2S_register, ARM64_INS_LD4R, |
| 6675 | #ifndef CAPSTONE_DIET |
| 6676 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6677 | #endif |
| 6678 | }, |
| 6679 | { |
| 6680 | AArch64_LD4R_WB_4H_fixed, ARM64_INS_LD4R, |
| 6681 | #ifndef CAPSTONE_DIET |
| 6682 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6683 | #endif |
| 6684 | }, |
| 6685 | { |
| 6686 | AArch64_LD4R_WB_4H_register, ARM64_INS_LD4R, |
| 6687 | #ifndef CAPSTONE_DIET |
| 6688 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6689 | #endif |
| 6690 | }, |
| 6691 | { |
| 6692 | AArch64_LD4R_WB_4S_fixed, ARM64_INS_LD4R, |
| 6693 | #ifndef CAPSTONE_DIET |
| 6694 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6695 | #endif |
| 6696 | }, |
| 6697 | { |
| 6698 | AArch64_LD4R_WB_4S_register, ARM64_INS_LD4R, |
| 6699 | #ifndef CAPSTONE_DIET |
| 6700 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6701 | #endif |
| 6702 | }, |
| 6703 | { |
| 6704 | AArch64_LD4R_WB_8B_fixed, ARM64_INS_LD4R, |
| 6705 | #ifndef CAPSTONE_DIET |
| 6706 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6707 | #endif |
| 6708 | }, |
| 6709 | { |
| 6710 | AArch64_LD4R_WB_8B_register, ARM64_INS_LD4R, |
| 6711 | #ifndef CAPSTONE_DIET |
| 6712 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6713 | #endif |
| 6714 | }, |
| 6715 | { |
| 6716 | AArch64_LD4R_WB_8H_fixed, ARM64_INS_LD4R, |
| 6717 | #ifndef CAPSTONE_DIET |
| 6718 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6719 | #endif |
| 6720 | }, |
| 6721 | { |
| 6722 | AArch64_LD4R_WB_8H_register, ARM64_INS_LD4R, |
| 6723 | #ifndef CAPSTONE_DIET |
| 6724 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6725 | #endif |
| 6726 | }, |
| 6727 | { |
| 6728 | AArch64_LD4WB_16B_fixed, ARM64_INS_LD4, |
| 6729 | #ifndef CAPSTONE_DIET |
| 6730 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6731 | #endif |
| 6732 | }, |
| 6733 | { |
| 6734 | AArch64_LD4WB_16B_register, ARM64_INS_LD4, |
| 6735 | #ifndef CAPSTONE_DIET |
| 6736 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6737 | #endif |
| 6738 | }, |
| 6739 | { |
| 6740 | AArch64_LD4WB_2D_fixed, ARM64_INS_LD4, |
| 6741 | #ifndef CAPSTONE_DIET |
| 6742 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6743 | #endif |
| 6744 | }, |
| 6745 | { |
| 6746 | AArch64_LD4WB_2D_register, ARM64_INS_LD4, |
| 6747 | #ifndef CAPSTONE_DIET |
| 6748 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6749 | #endif |
| 6750 | }, |
| 6751 | { |
| 6752 | AArch64_LD4WB_2S_fixed, ARM64_INS_LD4, |
| 6753 | #ifndef CAPSTONE_DIET |
| 6754 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6755 | #endif |
| 6756 | }, |
| 6757 | { |
| 6758 | AArch64_LD4WB_2S_register, ARM64_INS_LD4, |
| 6759 | #ifndef CAPSTONE_DIET |
| 6760 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6761 | #endif |
| 6762 | }, |
| 6763 | { |
| 6764 | AArch64_LD4WB_4H_fixed, ARM64_INS_LD4, |
| 6765 | #ifndef CAPSTONE_DIET |
| 6766 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6767 | #endif |
| 6768 | }, |
| 6769 | { |
| 6770 | AArch64_LD4WB_4H_register, ARM64_INS_LD4, |
| 6771 | #ifndef CAPSTONE_DIET |
| 6772 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6773 | #endif |
| 6774 | }, |
| 6775 | { |
| 6776 | AArch64_LD4WB_4S_fixed, ARM64_INS_LD4, |
| 6777 | #ifndef CAPSTONE_DIET |
| 6778 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6779 | #endif |
| 6780 | }, |
| 6781 | { |
| 6782 | AArch64_LD4WB_4S_register, ARM64_INS_LD4, |
| 6783 | #ifndef CAPSTONE_DIET |
| 6784 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6785 | #endif |
| 6786 | }, |
| 6787 | { |
| 6788 | AArch64_LD4WB_8B_fixed, ARM64_INS_LD4, |
| 6789 | #ifndef CAPSTONE_DIET |
| 6790 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6791 | #endif |
| 6792 | }, |
| 6793 | { |
| 6794 | AArch64_LD4WB_8B_register, ARM64_INS_LD4, |
| 6795 | #ifndef CAPSTONE_DIET |
| 6796 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6797 | #endif |
| 6798 | }, |
| 6799 | { |
| 6800 | AArch64_LD4WB_8H_fixed, ARM64_INS_LD4, |
| 6801 | #ifndef CAPSTONE_DIET |
| 6802 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6803 | #endif |
| 6804 | }, |
| 6805 | { |
| 6806 | AArch64_LD4WB_8H_register, ARM64_INS_LD4, |
| 6807 | #ifndef CAPSTONE_DIET |
| 6808 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6809 | #endif |
| 6810 | }, |
| 6811 | { |
| 6812 | AArch64_LD4_16B, ARM64_INS_LD4, |
| 6813 | #ifndef CAPSTONE_DIET |
| 6814 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6815 | #endif |
| 6816 | }, |
| 6817 | { |
| 6818 | AArch64_LD4_2D, ARM64_INS_LD4, |
| 6819 | #ifndef CAPSTONE_DIET |
| 6820 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6821 | #endif |
| 6822 | }, |
| 6823 | { |
| 6824 | AArch64_LD4_2S, ARM64_INS_LD4, |
| 6825 | #ifndef CAPSTONE_DIET |
| 6826 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6827 | #endif |
| 6828 | }, |
| 6829 | { |
| 6830 | AArch64_LD4_4H, ARM64_INS_LD4, |
| 6831 | #ifndef CAPSTONE_DIET |
| 6832 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6833 | #endif |
| 6834 | }, |
| 6835 | { |
| 6836 | AArch64_LD4_4S, ARM64_INS_LD4, |
| 6837 | #ifndef CAPSTONE_DIET |
| 6838 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6839 | #endif |
| 6840 | }, |
| 6841 | { |
| 6842 | AArch64_LD4_8B, ARM64_INS_LD4, |
| 6843 | #ifndef CAPSTONE_DIET |
| 6844 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6845 | #endif |
| 6846 | }, |
| 6847 | { |
| 6848 | AArch64_LD4_8H, ARM64_INS_LD4, |
| 6849 | #ifndef CAPSTONE_DIET |
| 6850 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 6851 | #endif |
| 6852 | }, |
| 6853 | { |
| 6854 | AArch64_LDAR_byte, ARM64_INS_LDARB, |
| 6855 | #ifndef CAPSTONE_DIET |
| 6856 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6857 | #endif |
| 6858 | }, |
| 6859 | { |
| 6860 | AArch64_LDAR_dword, ARM64_INS_LDAR, |
| 6861 | #ifndef CAPSTONE_DIET |
| 6862 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6863 | #endif |
| 6864 | }, |
| 6865 | { |
| 6866 | AArch64_LDAR_hword, ARM64_INS_LDARH, |
| 6867 | #ifndef CAPSTONE_DIET |
| 6868 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6869 | #endif |
| 6870 | }, |
| 6871 | { |
| 6872 | AArch64_LDAR_word, ARM64_INS_LDAR, |
| 6873 | #ifndef CAPSTONE_DIET |
| 6874 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6875 | #endif |
| 6876 | }, |
| 6877 | { |
| 6878 | AArch64_LDAXP_dword, ARM64_INS_LDAXP, |
| 6879 | #ifndef CAPSTONE_DIET |
| 6880 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6881 | #endif |
| 6882 | }, |
| 6883 | { |
| 6884 | AArch64_LDAXP_word, ARM64_INS_LDAXP, |
| 6885 | #ifndef CAPSTONE_DIET |
| 6886 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6887 | #endif |
| 6888 | }, |
| 6889 | { |
| 6890 | AArch64_LDAXR_byte, ARM64_INS_LDAXRB, |
| 6891 | #ifndef CAPSTONE_DIET |
| 6892 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6893 | #endif |
| 6894 | }, |
| 6895 | { |
| 6896 | AArch64_LDAXR_dword, ARM64_INS_LDAXR, |
| 6897 | #ifndef CAPSTONE_DIET |
| 6898 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6899 | #endif |
| 6900 | }, |
| 6901 | { |
| 6902 | AArch64_LDAXR_hword, ARM64_INS_LDAXRH, |
| 6903 | #ifndef CAPSTONE_DIET |
| 6904 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6905 | #endif |
| 6906 | }, |
| 6907 | { |
| 6908 | AArch64_LDAXR_word, ARM64_INS_LDAXR, |
| 6909 | #ifndef CAPSTONE_DIET |
| 6910 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6911 | #endif |
| 6912 | }, |
| 6913 | { |
| 6914 | AArch64_LDPSWx, ARM64_INS_LDPSW, |
| 6915 | #ifndef CAPSTONE_DIET |
| 6916 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6917 | #endif |
| 6918 | }, |
| 6919 | { |
| 6920 | AArch64_LDPSWx_PostInd, ARM64_INS_LDPSW, |
| 6921 | #ifndef CAPSTONE_DIET |
| 6922 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6923 | #endif |
| 6924 | }, |
| 6925 | { |
| 6926 | AArch64_LDPSWx_PreInd, ARM64_INS_LDPSW, |
| 6927 | #ifndef CAPSTONE_DIET |
| 6928 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6929 | #endif |
| 6930 | }, |
| 6931 | { |
| 6932 | AArch64_LDRSBw, ARM64_INS_LDRSB, |
| 6933 | #ifndef CAPSTONE_DIET |
| 6934 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6935 | #endif |
| 6936 | }, |
| 6937 | { |
| 6938 | AArch64_LDRSBw_PostInd, ARM64_INS_LDRSB, |
| 6939 | #ifndef CAPSTONE_DIET |
| 6940 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6941 | #endif |
| 6942 | }, |
| 6943 | { |
| 6944 | AArch64_LDRSBw_PreInd, ARM64_INS_LDRSB, |
| 6945 | #ifndef CAPSTONE_DIET |
| 6946 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6947 | #endif |
| 6948 | }, |
| 6949 | { |
| 6950 | AArch64_LDRSBw_U, ARM64_INS_LDURSB, |
| 6951 | #ifndef CAPSTONE_DIET |
| 6952 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6953 | #endif |
| 6954 | }, |
| 6955 | { |
| 6956 | AArch64_LDRSBw_Wm_RegOffset, ARM64_INS_LDRSB, |
| 6957 | #ifndef CAPSTONE_DIET |
| 6958 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6959 | #endif |
| 6960 | }, |
| 6961 | { |
| 6962 | AArch64_LDRSBw_Xm_RegOffset, ARM64_INS_LDRSB, |
| 6963 | #ifndef CAPSTONE_DIET |
| 6964 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6965 | #endif |
| 6966 | }, |
| 6967 | { |
| 6968 | AArch64_LDRSBx, ARM64_INS_LDRSB, |
| 6969 | #ifndef CAPSTONE_DIET |
| 6970 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6971 | #endif |
| 6972 | }, |
| 6973 | { |
| 6974 | AArch64_LDRSBx_PostInd, ARM64_INS_LDRSB, |
| 6975 | #ifndef CAPSTONE_DIET |
| 6976 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6977 | #endif |
| 6978 | }, |
| 6979 | { |
| 6980 | AArch64_LDRSBx_PreInd, ARM64_INS_LDRSB, |
| 6981 | #ifndef CAPSTONE_DIET |
| 6982 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6983 | #endif |
| 6984 | }, |
| 6985 | { |
| 6986 | AArch64_LDRSBx_U, ARM64_INS_LDURSB, |
| 6987 | #ifndef CAPSTONE_DIET |
| 6988 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6989 | #endif |
| 6990 | }, |
| 6991 | { |
| 6992 | AArch64_LDRSBx_Wm_RegOffset, ARM64_INS_LDRSB, |
| 6993 | #ifndef CAPSTONE_DIET |
| 6994 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 6995 | #endif |
| 6996 | }, |
| 6997 | { |
| 6998 | AArch64_LDRSBx_Xm_RegOffset, ARM64_INS_LDRSB, |
| 6999 | #ifndef CAPSTONE_DIET |
| 7000 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7001 | #endif |
| 7002 | }, |
| 7003 | { |
| 7004 | AArch64_LDRSHw, ARM64_INS_LDRSH, |
| 7005 | #ifndef CAPSTONE_DIET |
| 7006 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7007 | #endif |
| 7008 | }, |
| 7009 | { |
| 7010 | AArch64_LDRSHw_PostInd, ARM64_INS_LDRSH, |
| 7011 | #ifndef CAPSTONE_DIET |
| 7012 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7013 | #endif |
| 7014 | }, |
| 7015 | { |
| 7016 | AArch64_LDRSHw_PreInd, ARM64_INS_LDRSH, |
| 7017 | #ifndef CAPSTONE_DIET |
| 7018 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7019 | #endif |
| 7020 | }, |
| 7021 | { |
| 7022 | AArch64_LDRSHw_U, ARM64_INS_LDURSH, |
| 7023 | #ifndef CAPSTONE_DIET |
| 7024 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7025 | #endif |
| 7026 | }, |
| 7027 | { |
| 7028 | AArch64_LDRSHw_Wm_RegOffset, ARM64_INS_LDRSH, |
| 7029 | #ifndef CAPSTONE_DIET |
| 7030 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7031 | #endif |
| 7032 | }, |
| 7033 | { |
| 7034 | AArch64_LDRSHw_Xm_RegOffset, ARM64_INS_LDRSH, |
| 7035 | #ifndef CAPSTONE_DIET |
| 7036 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7037 | #endif |
| 7038 | }, |
| 7039 | { |
| 7040 | AArch64_LDRSHx, ARM64_INS_LDRSH, |
| 7041 | #ifndef CAPSTONE_DIET |
| 7042 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7043 | #endif |
| 7044 | }, |
| 7045 | { |
| 7046 | AArch64_LDRSHx_PostInd, ARM64_INS_LDRSH, |
| 7047 | #ifndef CAPSTONE_DIET |
| 7048 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7049 | #endif |
| 7050 | }, |
| 7051 | { |
| 7052 | AArch64_LDRSHx_PreInd, ARM64_INS_LDRSH, |
| 7053 | #ifndef CAPSTONE_DIET |
| 7054 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7055 | #endif |
| 7056 | }, |
| 7057 | { |
| 7058 | AArch64_LDRSHx_U, ARM64_INS_LDURSH, |
| 7059 | #ifndef CAPSTONE_DIET |
| 7060 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7061 | #endif |
| 7062 | }, |
| 7063 | { |
| 7064 | AArch64_LDRSHx_Wm_RegOffset, ARM64_INS_LDRSH, |
| 7065 | #ifndef CAPSTONE_DIET |
| 7066 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7067 | #endif |
| 7068 | }, |
| 7069 | { |
| 7070 | AArch64_LDRSHx_Xm_RegOffset, ARM64_INS_LDRSH, |
| 7071 | #ifndef CAPSTONE_DIET |
| 7072 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7073 | #endif |
| 7074 | }, |
| 7075 | { |
| 7076 | AArch64_LDRSWx, ARM64_INS_LDRSW, |
| 7077 | #ifndef CAPSTONE_DIET |
| 7078 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7079 | #endif |
| 7080 | }, |
| 7081 | { |
| 7082 | AArch64_LDRSWx_PostInd, ARM64_INS_LDRSW, |
| 7083 | #ifndef CAPSTONE_DIET |
| 7084 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7085 | #endif |
| 7086 | }, |
| 7087 | { |
| 7088 | AArch64_LDRSWx_PreInd, ARM64_INS_LDRSW, |
| 7089 | #ifndef CAPSTONE_DIET |
| 7090 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7091 | #endif |
| 7092 | }, |
| 7093 | { |
| 7094 | AArch64_LDRSWx_Wm_RegOffset, ARM64_INS_LDRSW, |
| 7095 | #ifndef CAPSTONE_DIET |
| 7096 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7097 | #endif |
| 7098 | }, |
| 7099 | { |
| 7100 | AArch64_LDRSWx_Xm_RegOffset, ARM64_INS_LDRSW, |
| 7101 | #ifndef CAPSTONE_DIET |
| 7102 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7103 | #endif |
| 7104 | }, |
| 7105 | { |
| 7106 | AArch64_LDRSWx_lit, ARM64_INS_LDRSW, |
| 7107 | #ifndef CAPSTONE_DIET |
| 7108 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7109 | #endif |
| 7110 | }, |
| 7111 | { |
| 7112 | AArch64_LDRd_lit, ARM64_INS_LDR, |
| 7113 | #ifndef CAPSTONE_DIET |
| 7114 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7115 | #endif |
| 7116 | }, |
| 7117 | { |
| 7118 | AArch64_LDRq_lit, ARM64_INS_LDR, |
| 7119 | #ifndef CAPSTONE_DIET |
| 7120 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7121 | #endif |
| 7122 | }, |
| 7123 | { |
| 7124 | AArch64_LDRs_lit, ARM64_INS_LDR, |
| 7125 | #ifndef CAPSTONE_DIET |
| 7126 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7127 | #endif |
| 7128 | }, |
| 7129 | { |
| 7130 | AArch64_LDRw_lit, ARM64_INS_LDR, |
| 7131 | #ifndef CAPSTONE_DIET |
| 7132 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7133 | #endif |
| 7134 | }, |
| 7135 | { |
| 7136 | AArch64_LDRx_lit, ARM64_INS_LDR, |
| 7137 | #ifndef CAPSTONE_DIET |
| 7138 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7139 | #endif |
| 7140 | }, |
| 7141 | { |
| 7142 | AArch64_LDTRSBw, ARM64_INS_LDTRSB, |
| 7143 | #ifndef CAPSTONE_DIET |
| 7144 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7145 | #endif |
| 7146 | }, |
| 7147 | { |
| 7148 | AArch64_LDTRSBx, ARM64_INS_LDTRSB, |
| 7149 | #ifndef CAPSTONE_DIET |
| 7150 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7151 | #endif |
| 7152 | }, |
| 7153 | { |
| 7154 | AArch64_LDTRSHw, ARM64_INS_LDTRSH, |
| 7155 | #ifndef CAPSTONE_DIET |
| 7156 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7157 | #endif |
| 7158 | }, |
| 7159 | { |
| 7160 | AArch64_LDTRSHx, ARM64_INS_LDTRSH, |
| 7161 | #ifndef CAPSTONE_DIET |
| 7162 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7163 | #endif |
| 7164 | }, |
| 7165 | { |
| 7166 | AArch64_LDTRSWx, ARM64_INS_LDTRSW, |
| 7167 | #ifndef CAPSTONE_DIET |
| 7168 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7169 | #endif |
| 7170 | }, |
| 7171 | { |
| 7172 | AArch64_LDURSWx, ARM64_INS_LDURSW, |
| 7173 | #ifndef CAPSTONE_DIET |
| 7174 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7175 | #endif |
| 7176 | }, |
| 7177 | { |
| 7178 | AArch64_LDXP_dword, ARM64_INS_LDXP, |
| 7179 | #ifndef CAPSTONE_DIET |
| 7180 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7181 | #endif |
| 7182 | }, |
| 7183 | { |
| 7184 | AArch64_LDXP_word, ARM64_INS_LDXP, |
| 7185 | #ifndef CAPSTONE_DIET |
| 7186 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7187 | #endif |
| 7188 | }, |
| 7189 | { |
| 7190 | AArch64_LDXR_byte, ARM64_INS_LDXRB, |
| 7191 | #ifndef CAPSTONE_DIET |
| 7192 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7193 | #endif |
| 7194 | }, |
| 7195 | { |
| 7196 | AArch64_LDXR_dword, ARM64_INS_LDXR, |
| 7197 | #ifndef CAPSTONE_DIET |
| 7198 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7199 | #endif |
| 7200 | }, |
| 7201 | { |
| 7202 | AArch64_LDXR_hword, ARM64_INS_LDXRH, |
| 7203 | #ifndef CAPSTONE_DIET |
| 7204 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7205 | #endif |
| 7206 | }, |
| 7207 | { |
| 7208 | AArch64_LDXR_word, ARM64_INS_LDXR, |
| 7209 | #ifndef CAPSTONE_DIET |
| 7210 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7211 | #endif |
| 7212 | }, |
| 7213 | { |
| 7214 | AArch64_LS16_LDR, ARM64_INS_LDRH, |
| 7215 | #ifndef CAPSTONE_DIET |
| 7216 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7217 | #endif |
| 7218 | }, |
| 7219 | { |
| 7220 | AArch64_LS16_LDUR, ARM64_INS_LDURH, |
| 7221 | #ifndef CAPSTONE_DIET |
| 7222 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7223 | #endif |
| 7224 | }, |
| 7225 | { |
| 7226 | AArch64_LS16_PostInd_LDR, ARM64_INS_LDRH, |
| 7227 | #ifndef CAPSTONE_DIET |
| 7228 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7229 | #endif |
| 7230 | }, |
| 7231 | { |
| 7232 | AArch64_LS16_PostInd_STR, ARM64_INS_STRH, |
| 7233 | #ifndef CAPSTONE_DIET |
| 7234 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7235 | #endif |
| 7236 | }, |
| 7237 | { |
| 7238 | AArch64_LS16_PreInd_LDR, ARM64_INS_LDRH, |
| 7239 | #ifndef CAPSTONE_DIET |
| 7240 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7241 | #endif |
| 7242 | }, |
| 7243 | { |
| 7244 | AArch64_LS16_PreInd_STR, ARM64_INS_STRH, |
| 7245 | #ifndef CAPSTONE_DIET |
| 7246 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7247 | #endif |
| 7248 | }, |
| 7249 | { |
| 7250 | AArch64_LS16_STR, ARM64_INS_STRH, |
| 7251 | #ifndef CAPSTONE_DIET |
| 7252 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7253 | #endif |
| 7254 | }, |
| 7255 | { |
| 7256 | AArch64_LS16_STUR, ARM64_INS_STURH, |
| 7257 | #ifndef CAPSTONE_DIET |
| 7258 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7259 | #endif |
| 7260 | }, |
| 7261 | { |
| 7262 | AArch64_LS16_UnPriv_LDR, ARM64_INS_LDTRH, |
| 7263 | #ifndef CAPSTONE_DIET |
| 7264 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7265 | #endif |
| 7266 | }, |
| 7267 | { |
| 7268 | AArch64_LS16_UnPriv_STR, ARM64_INS_STTRH, |
| 7269 | #ifndef CAPSTONE_DIET |
| 7270 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7271 | #endif |
| 7272 | }, |
| 7273 | { |
| 7274 | AArch64_LS16_Wm_RegOffset_LDR, ARM64_INS_LDRH, |
| 7275 | #ifndef CAPSTONE_DIET |
| 7276 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7277 | #endif |
| 7278 | }, |
| 7279 | { |
| 7280 | AArch64_LS16_Wm_RegOffset_STR, ARM64_INS_STRH, |
| 7281 | #ifndef CAPSTONE_DIET |
| 7282 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7283 | #endif |
| 7284 | }, |
| 7285 | { |
| 7286 | AArch64_LS16_Xm_RegOffset_LDR, ARM64_INS_LDRH, |
| 7287 | #ifndef CAPSTONE_DIET |
| 7288 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7289 | #endif |
| 7290 | }, |
| 7291 | { |
| 7292 | AArch64_LS16_Xm_RegOffset_STR, ARM64_INS_STRH, |
| 7293 | #ifndef CAPSTONE_DIET |
| 7294 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7295 | #endif |
| 7296 | }, |
| 7297 | { |
| 7298 | AArch64_LS32_LDR, ARM64_INS_LDR, |
| 7299 | #ifndef CAPSTONE_DIET |
| 7300 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7301 | #endif |
| 7302 | }, |
| 7303 | { |
| 7304 | AArch64_LS32_LDUR, ARM64_INS_LDUR, |
| 7305 | #ifndef CAPSTONE_DIET |
| 7306 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7307 | #endif |
| 7308 | }, |
| 7309 | { |
| 7310 | AArch64_LS32_PostInd_LDR, ARM64_INS_LDR, |
| 7311 | #ifndef CAPSTONE_DIET |
| 7312 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7313 | #endif |
| 7314 | }, |
| 7315 | { |
| 7316 | AArch64_LS32_PostInd_STR, ARM64_INS_STR, |
| 7317 | #ifndef CAPSTONE_DIET |
| 7318 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7319 | #endif |
| 7320 | }, |
| 7321 | { |
| 7322 | AArch64_LS32_PreInd_LDR, ARM64_INS_LDR, |
| 7323 | #ifndef CAPSTONE_DIET |
| 7324 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7325 | #endif |
| 7326 | }, |
| 7327 | { |
| 7328 | AArch64_LS32_PreInd_STR, ARM64_INS_STR, |
| 7329 | #ifndef CAPSTONE_DIET |
| 7330 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7331 | #endif |
| 7332 | }, |
| 7333 | { |
| 7334 | AArch64_LS32_STR, ARM64_INS_STR, |
| 7335 | #ifndef CAPSTONE_DIET |
| 7336 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7337 | #endif |
| 7338 | }, |
| 7339 | { |
| 7340 | AArch64_LS32_STUR, ARM64_INS_STUR, |
| 7341 | #ifndef CAPSTONE_DIET |
| 7342 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7343 | #endif |
| 7344 | }, |
| 7345 | { |
| 7346 | AArch64_LS32_UnPriv_LDR, ARM64_INS_LDTR, |
| 7347 | #ifndef CAPSTONE_DIET |
| 7348 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7349 | #endif |
| 7350 | }, |
| 7351 | { |
| 7352 | AArch64_LS32_UnPriv_STR, ARM64_INS_STTR, |
| 7353 | #ifndef CAPSTONE_DIET |
| 7354 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7355 | #endif |
| 7356 | }, |
| 7357 | { |
| 7358 | AArch64_LS32_Wm_RegOffset_LDR, ARM64_INS_LDR, |
| 7359 | #ifndef CAPSTONE_DIET |
| 7360 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7361 | #endif |
| 7362 | }, |
| 7363 | { |
| 7364 | AArch64_LS32_Wm_RegOffset_STR, ARM64_INS_STR, |
| 7365 | #ifndef CAPSTONE_DIET |
| 7366 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7367 | #endif |
| 7368 | }, |
| 7369 | { |
| 7370 | AArch64_LS32_Xm_RegOffset_LDR, ARM64_INS_LDR, |
| 7371 | #ifndef CAPSTONE_DIET |
| 7372 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7373 | #endif |
| 7374 | }, |
| 7375 | { |
| 7376 | AArch64_LS32_Xm_RegOffset_STR, ARM64_INS_STR, |
| 7377 | #ifndef CAPSTONE_DIET |
| 7378 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7379 | #endif |
| 7380 | }, |
| 7381 | { |
| 7382 | AArch64_LS64_LDR, ARM64_INS_LDR, |
| 7383 | #ifndef CAPSTONE_DIET |
| 7384 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7385 | #endif |
| 7386 | }, |
| 7387 | { |
| 7388 | AArch64_LS64_LDUR, ARM64_INS_LDUR, |
| 7389 | #ifndef CAPSTONE_DIET |
| 7390 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7391 | #endif |
| 7392 | }, |
| 7393 | { |
| 7394 | AArch64_LS64_PostInd_LDR, ARM64_INS_LDR, |
| 7395 | #ifndef CAPSTONE_DIET |
| 7396 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7397 | #endif |
| 7398 | }, |
| 7399 | { |
| 7400 | AArch64_LS64_PostInd_STR, ARM64_INS_STR, |
| 7401 | #ifndef CAPSTONE_DIET |
| 7402 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7403 | #endif |
| 7404 | }, |
| 7405 | { |
| 7406 | AArch64_LS64_PreInd_LDR, ARM64_INS_LDR, |
| 7407 | #ifndef CAPSTONE_DIET |
| 7408 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7409 | #endif |
| 7410 | }, |
| 7411 | { |
| 7412 | AArch64_LS64_PreInd_STR, ARM64_INS_STR, |
| 7413 | #ifndef CAPSTONE_DIET |
| 7414 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7415 | #endif |
| 7416 | }, |
| 7417 | { |
| 7418 | AArch64_LS64_STR, ARM64_INS_STR, |
| 7419 | #ifndef CAPSTONE_DIET |
| 7420 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7421 | #endif |
| 7422 | }, |
| 7423 | { |
| 7424 | AArch64_LS64_STUR, ARM64_INS_STUR, |
| 7425 | #ifndef CAPSTONE_DIET |
| 7426 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7427 | #endif |
| 7428 | }, |
| 7429 | { |
| 7430 | AArch64_LS64_UnPriv_LDR, ARM64_INS_LDTR, |
| 7431 | #ifndef CAPSTONE_DIET |
| 7432 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7433 | #endif |
| 7434 | }, |
| 7435 | { |
| 7436 | AArch64_LS64_UnPriv_STR, ARM64_INS_STTR, |
| 7437 | #ifndef CAPSTONE_DIET |
| 7438 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7439 | #endif |
| 7440 | }, |
| 7441 | { |
| 7442 | AArch64_LS64_Wm_RegOffset_LDR, ARM64_INS_LDR, |
| 7443 | #ifndef CAPSTONE_DIET |
| 7444 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7445 | #endif |
| 7446 | }, |
| 7447 | { |
| 7448 | AArch64_LS64_Wm_RegOffset_STR, ARM64_INS_STR, |
| 7449 | #ifndef CAPSTONE_DIET |
| 7450 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7451 | #endif |
| 7452 | }, |
| 7453 | { |
| 7454 | AArch64_LS64_Xm_RegOffset_LDR, ARM64_INS_LDR, |
| 7455 | #ifndef CAPSTONE_DIET |
| 7456 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7457 | #endif |
| 7458 | }, |
| 7459 | { |
| 7460 | AArch64_LS64_Xm_RegOffset_STR, ARM64_INS_STR, |
| 7461 | #ifndef CAPSTONE_DIET |
| 7462 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7463 | #endif |
| 7464 | }, |
| 7465 | { |
| 7466 | AArch64_LS8_LDR, ARM64_INS_LDRB, |
| 7467 | #ifndef CAPSTONE_DIET |
| 7468 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7469 | #endif |
| 7470 | }, |
| 7471 | { |
| 7472 | AArch64_LS8_LDUR, ARM64_INS_LDURB, |
| 7473 | #ifndef CAPSTONE_DIET |
| 7474 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7475 | #endif |
| 7476 | }, |
| 7477 | { |
| 7478 | AArch64_LS8_PostInd_LDR, ARM64_INS_LDRB, |
| 7479 | #ifndef CAPSTONE_DIET |
| 7480 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7481 | #endif |
| 7482 | }, |
| 7483 | { |
| 7484 | AArch64_LS8_PostInd_STR, ARM64_INS_STRB, |
| 7485 | #ifndef CAPSTONE_DIET |
| 7486 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7487 | #endif |
| 7488 | }, |
| 7489 | { |
| 7490 | AArch64_LS8_PreInd_LDR, ARM64_INS_LDRB, |
| 7491 | #ifndef CAPSTONE_DIET |
| 7492 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7493 | #endif |
| 7494 | }, |
| 7495 | { |
| 7496 | AArch64_LS8_PreInd_STR, ARM64_INS_STRB, |
| 7497 | #ifndef CAPSTONE_DIET |
| 7498 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7499 | #endif |
| 7500 | }, |
| 7501 | { |
| 7502 | AArch64_LS8_STR, ARM64_INS_STRB, |
| 7503 | #ifndef CAPSTONE_DIET |
| 7504 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7505 | #endif |
| 7506 | }, |
| 7507 | { |
| 7508 | AArch64_LS8_STUR, ARM64_INS_STURB, |
| 7509 | #ifndef CAPSTONE_DIET |
| 7510 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7511 | #endif |
| 7512 | }, |
| 7513 | { |
| 7514 | AArch64_LS8_UnPriv_LDR, ARM64_INS_LDTRB, |
| 7515 | #ifndef CAPSTONE_DIET |
| 7516 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7517 | #endif |
| 7518 | }, |
| 7519 | { |
| 7520 | AArch64_LS8_UnPriv_STR, ARM64_INS_STTRB, |
| 7521 | #ifndef CAPSTONE_DIET |
| 7522 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7523 | #endif |
| 7524 | }, |
| 7525 | { |
| 7526 | AArch64_LS8_Wm_RegOffset_LDR, ARM64_INS_LDRB, |
| 7527 | #ifndef CAPSTONE_DIET |
| 7528 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7529 | #endif |
| 7530 | }, |
| 7531 | { |
| 7532 | AArch64_LS8_Wm_RegOffset_STR, ARM64_INS_STRB, |
| 7533 | #ifndef CAPSTONE_DIET |
| 7534 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7535 | #endif |
| 7536 | }, |
| 7537 | { |
| 7538 | AArch64_LS8_Xm_RegOffset_LDR, ARM64_INS_LDRB, |
| 7539 | #ifndef CAPSTONE_DIET |
| 7540 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7541 | #endif |
| 7542 | }, |
| 7543 | { |
| 7544 | AArch64_LS8_Xm_RegOffset_STR, ARM64_INS_STRB, |
| 7545 | #ifndef CAPSTONE_DIET |
| 7546 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 7547 | #endif |
| 7548 | }, |
| 7549 | { |
| 7550 | AArch64_LSFP128_LDR, ARM64_INS_LDR, |
| 7551 | #ifndef CAPSTONE_DIET |
| 7552 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7553 | #endif |
| 7554 | }, |
| 7555 | { |
| 7556 | AArch64_LSFP128_LDUR, ARM64_INS_LDUR, |
| 7557 | #ifndef CAPSTONE_DIET |
| 7558 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7559 | #endif |
| 7560 | }, |
| 7561 | { |
| 7562 | AArch64_LSFP128_PostInd_LDR, ARM64_INS_LDR, |
| 7563 | #ifndef CAPSTONE_DIET |
| 7564 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7565 | #endif |
| 7566 | }, |
| 7567 | { |
| 7568 | AArch64_LSFP128_PostInd_STR, ARM64_INS_STR, |
| 7569 | #ifndef CAPSTONE_DIET |
| 7570 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7571 | #endif |
| 7572 | }, |
| 7573 | { |
| 7574 | AArch64_LSFP128_PreInd_LDR, ARM64_INS_LDR, |
| 7575 | #ifndef CAPSTONE_DIET |
| 7576 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7577 | #endif |
| 7578 | }, |
| 7579 | { |
| 7580 | AArch64_LSFP128_PreInd_STR, ARM64_INS_STR, |
| 7581 | #ifndef CAPSTONE_DIET |
| 7582 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7583 | #endif |
| 7584 | }, |
| 7585 | { |
| 7586 | AArch64_LSFP128_STR, ARM64_INS_STR, |
| 7587 | #ifndef CAPSTONE_DIET |
| 7588 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7589 | #endif |
| 7590 | }, |
| 7591 | { |
| 7592 | AArch64_LSFP128_STUR, ARM64_INS_STUR, |
| 7593 | #ifndef CAPSTONE_DIET |
| 7594 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7595 | #endif |
| 7596 | }, |
| 7597 | { |
| 7598 | AArch64_LSFP128_Wm_RegOffset_LDR, ARM64_INS_LDR, |
| 7599 | #ifndef CAPSTONE_DIET |
| 7600 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7601 | #endif |
| 7602 | }, |
| 7603 | { |
| 7604 | AArch64_LSFP128_Wm_RegOffset_STR, ARM64_INS_STR, |
| 7605 | #ifndef CAPSTONE_DIET |
| 7606 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7607 | #endif |
| 7608 | }, |
| 7609 | { |
| 7610 | AArch64_LSFP128_Xm_RegOffset_LDR, ARM64_INS_LDR, |
| 7611 | #ifndef CAPSTONE_DIET |
| 7612 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7613 | #endif |
| 7614 | }, |
| 7615 | { |
| 7616 | AArch64_LSFP128_Xm_RegOffset_STR, ARM64_INS_STR, |
| 7617 | #ifndef CAPSTONE_DIET |
| 7618 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7619 | #endif |
| 7620 | }, |
| 7621 | { |
| 7622 | AArch64_LSFP16_LDR, ARM64_INS_LDR, |
| 7623 | #ifndef CAPSTONE_DIET |
| 7624 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7625 | #endif |
| 7626 | }, |
| 7627 | { |
| 7628 | AArch64_LSFP16_LDUR, ARM64_INS_LDUR, |
| 7629 | #ifndef CAPSTONE_DIET |
| 7630 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7631 | #endif |
| 7632 | }, |
| 7633 | { |
| 7634 | AArch64_LSFP16_PostInd_LDR, ARM64_INS_LDR, |
| 7635 | #ifndef CAPSTONE_DIET |
| 7636 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7637 | #endif |
| 7638 | }, |
| 7639 | { |
| 7640 | AArch64_LSFP16_PostInd_STR, ARM64_INS_STR, |
| 7641 | #ifndef CAPSTONE_DIET |
| 7642 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7643 | #endif |
| 7644 | }, |
| 7645 | { |
| 7646 | AArch64_LSFP16_PreInd_LDR, ARM64_INS_LDR, |
| 7647 | #ifndef CAPSTONE_DIET |
| 7648 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7649 | #endif |
| 7650 | }, |
| 7651 | { |
| 7652 | AArch64_LSFP16_PreInd_STR, ARM64_INS_STR, |
| 7653 | #ifndef CAPSTONE_DIET |
| 7654 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7655 | #endif |
| 7656 | }, |
| 7657 | { |
| 7658 | AArch64_LSFP16_STR, ARM64_INS_STR, |
| 7659 | #ifndef CAPSTONE_DIET |
| 7660 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7661 | #endif |
| 7662 | }, |
| 7663 | { |
| 7664 | AArch64_LSFP16_STUR, ARM64_INS_STUR, |
| 7665 | #ifndef CAPSTONE_DIET |
| 7666 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7667 | #endif |
| 7668 | }, |
| 7669 | { |
| 7670 | AArch64_LSFP16_Wm_RegOffset_LDR, ARM64_INS_LDR, |
| 7671 | #ifndef CAPSTONE_DIET |
| 7672 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7673 | #endif |
| 7674 | }, |
| 7675 | { |
| 7676 | AArch64_LSFP16_Wm_RegOffset_STR, ARM64_INS_STR, |
| 7677 | #ifndef CAPSTONE_DIET |
| 7678 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7679 | #endif |
| 7680 | }, |
| 7681 | { |
| 7682 | AArch64_LSFP16_Xm_RegOffset_LDR, ARM64_INS_LDR, |
| 7683 | #ifndef CAPSTONE_DIET |
| 7684 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7685 | #endif |
| 7686 | }, |
| 7687 | { |
| 7688 | AArch64_LSFP16_Xm_RegOffset_STR, ARM64_INS_STR, |
| 7689 | #ifndef CAPSTONE_DIET |
| 7690 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7691 | #endif |
| 7692 | }, |
| 7693 | { |
| 7694 | AArch64_LSFP32_LDR, ARM64_INS_LDR, |
| 7695 | #ifndef CAPSTONE_DIET |
| 7696 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7697 | #endif |
| 7698 | }, |
| 7699 | { |
| 7700 | AArch64_LSFP32_LDUR, ARM64_INS_LDUR, |
| 7701 | #ifndef CAPSTONE_DIET |
| 7702 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7703 | #endif |
| 7704 | }, |
| 7705 | { |
| 7706 | AArch64_LSFP32_PostInd_LDR, ARM64_INS_LDR, |
| 7707 | #ifndef CAPSTONE_DIET |
| 7708 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7709 | #endif |
| 7710 | }, |
| 7711 | { |
| 7712 | AArch64_LSFP32_PostInd_STR, ARM64_INS_STR, |
| 7713 | #ifndef CAPSTONE_DIET |
| 7714 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7715 | #endif |
| 7716 | }, |
| 7717 | { |
| 7718 | AArch64_LSFP32_PreInd_LDR, ARM64_INS_LDR, |
| 7719 | #ifndef CAPSTONE_DIET |
| 7720 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7721 | #endif |
| 7722 | }, |
| 7723 | { |
| 7724 | AArch64_LSFP32_PreInd_STR, ARM64_INS_STR, |
| 7725 | #ifndef CAPSTONE_DIET |
| 7726 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7727 | #endif |
| 7728 | }, |
| 7729 | { |
| 7730 | AArch64_LSFP32_STR, ARM64_INS_STR, |
| 7731 | #ifndef CAPSTONE_DIET |
| 7732 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7733 | #endif |
| 7734 | }, |
| 7735 | { |
| 7736 | AArch64_LSFP32_STUR, ARM64_INS_STUR, |
| 7737 | #ifndef CAPSTONE_DIET |
| 7738 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7739 | #endif |
| 7740 | }, |
| 7741 | { |
| 7742 | AArch64_LSFP32_Wm_RegOffset_LDR, ARM64_INS_LDR, |
| 7743 | #ifndef CAPSTONE_DIET |
| 7744 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7745 | #endif |
| 7746 | }, |
| 7747 | { |
| 7748 | AArch64_LSFP32_Wm_RegOffset_STR, ARM64_INS_STR, |
| 7749 | #ifndef CAPSTONE_DIET |
| 7750 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7751 | #endif |
| 7752 | }, |
| 7753 | { |
| 7754 | AArch64_LSFP32_Xm_RegOffset_LDR, ARM64_INS_LDR, |
| 7755 | #ifndef CAPSTONE_DIET |
| 7756 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7757 | #endif |
| 7758 | }, |
| 7759 | { |
| 7760 | AArch64_LSFP32_Xm_RegOffset_STR, ARM64_INS_STR, |
| 7761 | #ifndef CAPSTONE_DIET |
| 7762 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7763 | #endif |
| 7764 | }, |
| 7765 | { |
| 7766 | AArch64_LSFP64_LDR, ARM64_INS_LDR, |
| 7767 | #ifndef CAPSTONE_DIET |
| 7768 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7769 | #endif |
| 7770 | }, |
| 7771 | { |
| 7772 | AArch64_LSFP64_LDUR, ARM64_INS_LDUR, |
| 7773 | #ifndef CAPSTONE_DIET |
| 7774 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7775 | #endif |
| 7776 | }, |
| 7777 | { |
| 7778 | AArch64_LSFP64_PostInd_LDR, ARM64_INS_LDR, |
| 7779 | #ifndef CAPSTONE_DIET |
| 7780 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7781 | #endif |
| 7782 | }, |
| 7783 | { |
| 7784 | AArch64_LSFP64_PostInd_STR, ARM64_INS_STR, |
| 7785 | #ifndef CAPSTONE_DIET |
| 7786 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7787 | #endif |
| 7788 | }, |
| 7789 | { |
| 7790 | AArch64_LSFP64_PreInd_LDR, ARM64_INS_LDR, |
| 7791 | #ifndef CAPSTONE_DIET |
| 7792 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7793 | #endif |
| 7794 | }, |
| 7795 | { |
| 7796 | AArch64_LSFP64_PreInd_STR, ARM64_INS_STR, |
| 7797 | #ifndef CAPSTONE_DIET |
| 7798 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7799 | #endif |
| 7800 | }, |
| 7801 | { |
| 7802 | AArch64_LSFP64_STR, ARM64_INS_STR, |
| 7803 | #ifndef CAPSTONE_DIET |
| 7804 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7805 | #endif |
| 7806 | }, |
| 7807 | { |
| 7808 | AArch64_LSFP64_STUR, ARM64_INS_STUR, |
| 7809 | #ifndef CAPSTONE_DIET |
| 7810 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7811 | #endif |
| 7812 | }, |
| 7813 | { |
| 7814 | AArch64_LSFP64_Wm_RegOffset_LDR, ARM64_INS_LDR, |
| 7815 | #ifndef CAPSTONE_DIET |
| 7816 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7817 | #endif |
| 7818 | }, |
| 7819 | { |
| 7820 | AArch64_LSFP64_Wm_RegOffset_STR, ARM64_INS_STR, |
| 7821 | #ifndef CAPSTONE_DIET |
| 7822 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7823 | #endif |
| 7824 | }, |
| 7825 | { |
| 7826 | AArch64_LSFP64_Xm_RegOffset_LDR, ARM64_INS_LDR, |
| 7827 | #ifndef CAPSTONE_DIET |
| 7828 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7829 | #endif |
| 7830 | }, |
| 7831 | { |
| 7832 | AArch64_LSFP64_Xm_RegOffset_STR, ARM64_INS_STR, |
| 7833 | #ifndef CAPSTONE_DIET |
| 7834 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7835 | #endif |
| 7836 | }, |
| 7837 | { |
| 7838 | AArch64_LSFP8_LDR, ARM64_INS_LDR, |
| 7839 | #ifndef CAPSTONE_DIET |
| 7840 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7841 | #endif |
| 7842 | }, |
| 7843 | { |
| 7844 | AArch64_LSFP8_LDUR, ARM64_INS_LDUR, |
| 7845 | #ifndef CAPSTONE_DIET |
| 7846 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7847 | #endif |
| 7848 | }, |
| 7849 | { |
| 7850 | AArch64_LSFP8_PostInd_LDR, ARM64_INS_LDR, |
| 7851 | #ifndef CAPSTONE_DIET |
| 7852 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7853 | #endif |
| 7854 | }, |
| 7855 | { |
| 7856 | AArch64_LSFP8_PostInd_STR, ARM64_INS_STR, |
| 7857 | #ifndef CAPSTONE_DIET |
| 7858 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7859 | #endif |
| 7860 | }, |
| 7861 | { |
| 7862 | AArch64_LSFP8_PreInd_LDR, ARM64_INS_LDR, |
| 7863 | #ifndef CAPSTONE_DIET |
| 7864 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7865 | #endif |
| 7866 | }, |
| 7867 | { |
| 7868 | AArch64_LSFP8_PreInd_STR, ARM64_INS_STR, |
| 7869 | #ifndef CAPSTONE_DIET |
| 7870 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7871 | #endif |
| 7872 | }, |
| 7873 | { |
| 7874 | AArch64_LSFP8_STR, ARM64_INS_STR, |
| 7875 | #ifndef CAPSTONE_DIET |
| 7876 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7877 | #endif |
| 7878 | }, |
| 7879 | { |
| 7880 | AArch64_LSFP8_STUR, ARM64_INS_STUR, |
| 7881 | #ifndef CAPSTONE_DIET |
| 7882 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7883 | #endif |
| 7884 | }, |
| 7885 | { |
| 7886 | AArch64_LSFP8_Wm_RegOffset_LDR, ARM64_INS_LDR, |
| 7887 | #ifndef CAPSTONE_DIET |
| 7888 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7889 | #endif |
| 7890 | }, |
| 7891 | { |
| 7892 | AArch64_LSFP8_Wm_RegOffset_STR, ARM64_INS_STR, |
| 7893 | #ifndef CAPSTONE_DIET |
| 7894 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7895 | #endif |
| 7896 | }, |
| 7897 | { |
| 7898 | AArch64_LSFP8_Xm_RegOffset_LDR, ARM64_INS_LDR, |
| 7899 | #ifndef CAPSTONE_DIET |
| 7900 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7901 | #endif |
| 7902 | }, |
| 7903 | { |
| 7904 | AArch64_LSFP8_Xm_RegOffset_STR, ARM64_INS_STR, |
| 7905 | #ifndef CAPSTONE_DIET |
| 7906 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7907 | #endif |
| 7908 | }, |
| 7909 | { |
| 7910 | AArch64_LSFPPair128_LDR, ARM64_INS_LDP, |
| 7911 | #ifndef CAPSTONE_DIET |
| 7912 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7913 | #endif |
| 7914 | }, |
| 7915 | { |
| 7916 | AArch64_LSFPPair128_NonTemp_LDR, ARM64_INS_LDNP, |
| 7917 | #ifndef CAPSTONE_DIET |
| 7918 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7919 | #endif |
| 7920 | }, |
| 7921 | { |
| 7922 | AArch64_LSFPPair128_NonTemp_STR, ARM64_INS_STNP, |
| 7923 | #ifndef CAPSTONE_DIET |
| 7924 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7925 | #endif |
| 7926 | }, |
| 7927 | { |
| 7928 | AArch64_LSFPPair128_PostInd_LDR, ARM64_INS_LDP, |
| 7929 | #ifndef CAPSTONE_DIET |
| 7930 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7931 | #endif |
| 7932 | }, |
| 7933 | { |
| 7934 | AArch64_LSFPPair128_PostInd_STR, ARM64_INS_STP, |
| 7935 | #ifndef CAPSTONE_DIET |
| 7936 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7937 | #endif |
| 7938 | }, |
| 7939 | { |
| 7940 | AArch64_LSFPPair128_PreInd_LDR, ARM64_INS_LDP, |
| 7941 | #ifndef CAPSTONE_DIET |
| 7942 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7943 | #endif |
| 7944 | }, |
| 7945 | { |
| 7946 | AArch64_LSFPPair128_PreInd_STR, ARM64_INS_STP, |
| 7947 | #ifndef CAPSTONE_DIET |
| 7948 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7949 | #endif |
| 7950 | }, |
| 7951 | { |
| 7952 | AArch64_LSFPPair128_STR, ARM64_INS_STP, |
| 7953 | #ifndef CAPSTONE_DIET |
| 7954 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7955 | #endif |
| 7956 | }, |
| 7957 | { |
| 7958 | AArch64_LSFPPair32_LDR, ARM64_INS_LDP, |
| 7959 | #ifndef CAPSTONE_DIET |
| 7960 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7961 | #endif |
| 7962 | }, |
| 7963 | { |
| 7964 | AArch64_LSFPPair32_NonTemp_LDR, ARM64_INS_LDNP, |
| 7965 | #ifndef CAPSTONE_DIET |
| 7966 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7967 | #endif |
| 7968 | }, |
| 7969 | { |
| 7970 | AArch64_LSFPPair32_NonTemp_STR, ARM64_INS_STNP, |
| 7971 | #ifndef CAPSTONE_DIET |
| 7972 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7973 | #endif |
| 7974 | }, |
| 7975 | { |
| 7976 | AArch64_LSFPPair32_PostInd_LDR, ARM64_INS_LDP, |
| 7977 | #ifndef CAPSTONE_DIET |
| 7978 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7979 | #endif |
| 7980 | }, |
| 7981 | { |
| 7982 | AArch64_LSFPPair32_PostInd_STR, ARM64_INS_STP, |
| 7983 | #ifndef CAPSTONE_DIET |
| 7984 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7985 | #endif |
| 7986 | }, |
| 7987 | { |
| 7988 | AArch64_LSFPPair32_PreInd_LDR, ARM64_INS_LDP, |
| 7989 | #ifndef CAPSTONE_DIET |
| 7990 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7991 | #endif |
| 7992 | }, |
| 7993 | { |
| 7994 | AArch64_LSFPPair32_PreInd_STR, ARM64_INS_STP, |
| 7995 | #ifndef CAPSTONE_DIET |
| 7996 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 7997 | #endif |
| 7998 | }, |
| 7999 | { |
| 8000 | AArch64_LSFPPair32_STR, ARM64_INS_STP, |
| 8001 | #ifndef CAPSTONE_DIET |
| 8002 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8003 | #endif |
| 8004 | }, |
| 8005 | { |
| 8006 | AArch64_LSFPPair64_LDR, ARM64_INS_LDP, |
| 8007 | #ifndef CAPSTONE_DIET |
| 8008 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8009 | #endif |
| 8010 | }, |
| 8011 | { |
| 8012 | AArch64_LSFPPair64_NonTemp_LDR, ARM64_INS_LDNP, |
| 8013 | #ifndef CAPSTONE_DIET |
| 8014 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8015 | #endif |
| 8016 | }, |
| 8017 | { |
| 8018 | AArch64_LSFPPair64_NonTemp_STR, ARM64_INS_STNP, |
| 8019 | #ifndef CAPSTONE_DIET |
| 8020 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8021 | #endif |
| 8022 | }, |
| 8023 | { |
| 8024 | AArch64_LSFPPair64_PostInd_LDR, ARM64_INS_LDP, |
| 8025 | #ifndef CAPSTONE_DIET |
| 8026 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8027 | #endif |
| 8028 | }, |
| 8029 | { |
| 8030 | AArch64_LSFPPair64_PostInd_STR, ARM64_INS_STP, |
| 8031 | #ifndef CAPSTONE_DIET |
| 8032 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8033 | #endif |
| 8034 | }, |
| 8035 | { |
| 8036 | AArch64_LSFPPair64_PreInd_LDR, ARM64_INS_LDP, |
| 8037 | #ifndef CAPSTONE_DIET |
| 8038 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8039 | #endif |
| 8040 | }, |
| 8041 | { |
| 8042 | AArch64_LSFPPair64_PreInd_STR, ARM64_INS_STP, |
| 8043 | #ifndef CAPSTONE_DIET |
| 8044 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8045 | #endif |
| 8046 | }, |
| 8047 | { |
| 8048 | AArch64_LSFPPair64_STR, ARM64_INS_STP, |
| 8049 | #ifndef CAPSTONE_DIET |
| 8050 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 8051 | #endif |
| 8052 | }, |
| 8053 | { |
| 8054 | AArch64_LSLVwww, ARM64_INS_LSL, |
| 8055 | #ifndef CAPSTONE_DIET |
| 8056 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8057 | #endif |
| 8058 | }, |
| 8059 | { |
| 8060 | AArch64_LSLVxxx, ARM64_INS_LSL, |
| 8061 | #ifndef CAPSTONE_DIET |
| 8062 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8063 | #endif |
| 8064 | }, |
| 8065 | { |
| 8066 | AArch64_LSLwwi, ARM64_INS_LSL, |
| 8067 | #ifndef CAPSTONE_DIET |
| 8068 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8069 | #endif |
| 8070 | }, |
| 8071 | { |
| 8072 | AArch64_LSLxxi, ARM64_INS_LSL, |
| 8073 | #ifndef CAPSTONE_DIET |
| 8074 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8075 | #endif |
| 8076 | }, |
| 8077 | { |
| 8078 | AArch64_LSPair32_LDR, ARM64_INS_LDP, |
| 8079 | #ifndef CAPSTONE_DIET |
| 8080 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8081 | #endif |
| 8082 | }, |
| 8083 | { |
| 8084 | AArch64_LSPair32_NonTemp_LDR, ARM64_INS_LDNP, |
| 8085 | #ifndef CAPSTONE_DIET |
| 8086 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8087 | #endif |
| 8088 | }, |
| 8089 | { |
| 8090 | AArch64_LSPair32_NonTemp_STR, ARM64_INS_STNP, |
| 8091 | #ifndef CAPSTONE_DIET |
| 8092 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8093 | #endif |
| 8094 | }, |
| 8095 | { |
| 8096 | AArch64_LSPair32_PostInd_LDR, ARM64_INS_LDP, |
| 8097 | #ifndef CAPSTONE_DIET |
| 8098 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8099 | #endif |
| 8100 | }, |
| 8101 | { |
| 8102 | AArch64_LSPair32_PostInd_STR, ARM64_INS_STP, |
| 8103 | #ifndef CAPSTONE_DIET |
| 8104 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8105 | #endif |
| 8106 | }, |
| 8107 | { |
| 8108 | AArch64_LSPair32_PreInd_LDR, ARM64_INS_LDP, |
| 8109 | #ifndef CAPSTONE_DIET |
| 8110 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8111 | #endif |
| 8112 | }, |
| 8113 | { |
| 8114 | AArch64_LSPair32_PreInd_STR, ARM64_INS_STP, |
| 8115 | #ifndef CAPSTONE_DIET |
| 8116 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8117 | #endif |
| 8118 | }, |
| 8119 | { |
| 8120 | AArch64_LSPair32_STR, ARM64_INS_STP, |
| 8121 | #ifndef CAPSTONE_DIET |
| 8122 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8123 | #endif |
| 8124 | }, |
| 8125 | { |
| 8126 | AArch64_LSPair64_LDR, ARM64_INS_LDP, |
| 8127 | #ifndef CAPSTONE_DIET |
| 8128 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8129 | #endif |
| 8130 | }, |
| 8131 | { |
| 8132 | AArch64_LSPair64_NonTemp_LDR, ARM64_INS_LDNP, |
| 8133 | #ifndef CAPSTONE_DIET |
| 8134 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8135 | #endif |
| 8136 | }, |
| 8137 | { |
| 8138 | AArch64_LSPair64_NonTemp_STR, ARM64_INS_STNP, |
| 8139 | #ifndef CAPSTONE_DIET |
| 8140 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8141 | #endif |
| 8142 | }, |
| 8143 | { |
| 8144 | AArch64_LSPair64_PostInd_LDR, ARM64_INS_LDP, |
| 8145 | #ifndef CAPSTONE_DIET |
| 8146 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8147 | #endif |
| 8148 | }, |
| 8149 | { |
| 8150 | AArch64_LSPair64_PostInd_STR, ARM64_INS_STP, |
| 8151 | #ifndef CAPSTONE_DIET |
| 8152 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8153 | #endif |
| 8154 | }, |
| 8155 | { |
| 8156 | AArch64_LSPair64_PreInd_LDR, ARM64_INS_LDP, |
| 8157 | #ifndef CAPSTONE_DIET |
| 8158 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8159 | #endif |
| 8160 | }, |
| 8161 | { |
| 8162 | AArch64_LSPair64_PreInd_STR, ARM64_INS_STP, |
| 8163 | #ifndef CAPSTONE_DIET |
| 8164 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8165 | #endif |
| 8166 | }, |
| 8167 | { |
| 8168 | AArch64_LSPair64_STR, ARM64_INS_STP, |
| 8169 | #ifndef CAPSTONE_DIET |
| 8170 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8171 | #endif |
| 8172 | }, |
| 8173 | { |
| 8174 | AArch64_LSRVwww, ARM64_INS_LSR, |
| 8175 | #ifndef CAPSTONE_DIET |
| 8176 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8177 | #endif |
| 8178 | }, |
| 8179 | { |
| 8180 | AArch64_LSRVxxx, ARM64_INS_LSR, |
| 8181 | #ifndef CAPSTONE_DIET |
| 8182 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8183 | #endif |
| 8184 | }, |
| 8185 | { |
| 8186 | AArch64_LSRwwi, ARM64_INS_LSR, |
| 8187 | #ifndef CAPSTONE_DIET |
| 8188 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8189 | #endif |
| 8190 | }, |
| 8191 | { |
| 8192 | AArch64_LSRxxi, ARM64_INS_LSR, |
| 8193 | #ifndef CAPSTONE_DIET |
| 8194 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8195 | #endif |
| 8196 | }, |
| 8197 | { |
| 8198 | AArch64_MADDwwww, ARM64_INS_MADD, |
| 8199 | #ifndef CAPSTONE_DIET |
| 8200 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8201 | #endif |
| 8202 | }, |
| 8203 | { |
| 8204 | AArch64_MADDxxxx, ARM64_INS_MADD, |
| 8205 | #ifndef CAPSTONE_DIET |
| 8206 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8207 | #endif |
| 8208 | }, |
| 8209 | { |
| 8210 | AArch64_MLAvve_2s4s, ARM64_INS_MLA, |
| 8211 | #ifndef CAPSTONE_DIET |
| 8212 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8213 | #endif |
| 8214 | }, |
| 8215 | { |
| 8216 | AArch64_MLAvve_4h8h, ARM64_INS_MLA, |
| 8217 | #ifndef CAPSTONE_DIET |
| 8218 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8219 | #endif |
| 8220 | }, |
| 8221 | { |
| 8222 | AArch64_MLAvve_4s4s, ARM64_INS_MLA, |
| 8223 | #ifndef CAPSTONE_DIET |
| 8224 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8225 | #endif |
| 8226 | }, |
| 8227 | { |
| 8228 | AArch64_MLAvve_8h8h, ARM64_INS_MLA, |
| 8229 | #ifndef CAPSTONE_DIET |
| 8230 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8231 | #endif |
| 8232 | }, |
| 8233 | { |
| 8234 | AArch64_MLAvvv_16B, ARM64_INS_MLA, |
| 8235 | #ifndef CAPSTONE_DIET |
| 8236 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8237 | #endif |
| 8238 | }, |
| 8239 | { |
| 8240 | AArch64_MLAvvv_2S, ARM64_INS_MLA, |
| 8241 | #ifndef CAPSTONE_DIET |
| 8242 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8243 | #endif |
| 8244 | }, |
| 8245 | { |
| 8246 | AArch64_MLAvvv_4H, ARM64_INS_MLA, |
| 8247 | #ifndef CAPSTONE_DIET |
| 8248 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8249 | #endif |
| 8250 | }, |
| 8251 | { |
| 8252 | AArch64_MLAvvv_4S, ARM64_INS_MLA, |
| 8253 | #ifndef CAPSTONE_DIET |
| 8254 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8255 | #endif |
| 8256 | }, |
| 8257 | { |
| 8258 | AArch64_MLAvvv_8B, ARM64_INS_MLA, |
| 8259 | #ifndef CAPSTONE_DIET |
| 8260 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8261 | #endif |
| 8262 | }, |
| 8263 | { |
| 8264 | AArch64_MLAvvv_8H, ARM64_INS_MLA, |
| 8265 | #ifndef CAPSTONE_DIET |
| 8266 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8267 | #endif |
| 8268 | }, |
| 8269 | { |
| 8270 | AArch64_MLSvve_2s4s, ARM64_INS_MLS, |
| 8271 | #ifndef CAPSTONE_DIET |
| 8272 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8273 | #endif |
| 8274 | }, |
| 8275 | { |
| 8276 | AArch64_MLSvve_4h8h, ARM64_INS_MLS, |
| 8277 | #ifndef CAPSTONE_DIET |
| 8278 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8279 | #endif |
| 8280 | }, |
| 8281 | { |
| 8282 | AArch64_MLSvve_4s4s, ARM64_INS_MLS, |
| 8283 | #ifndef CAPSTONE_DIET |
| 8284 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8285 | #endif |
| 8286 | }, |
| 8287 | { |
| 8288 | AArch64_MLSvve_8h8h, ARM64_INS_MLS, |
| 8289 | #ifndef CAPSTONE_DIET |
| 8290 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8291 | #endif |
| 8292 | }, |
| 8293 | { |
| 8294 | AArch64_MLSvvv_16B, ARM64_INS_MLS, |
| 8295 | #ifndef CAPSTONE_DIET |
| 8296 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8297 | #endif |
| 8298 | }, |
| 8299 | { |
| 8300 | AArch64_MLSvvv_2S, ARM64_INS_MLS, |
| 8301 | #ifndef CAPSTONE_DIET |
| 8302 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8303 | #endif |
| 8304 | }, |
| 8305 | { |
| 8306 | AArch64_MLSvvv_4H, ARM64_INS_MLS, |
| 8307 | #ifndef CAPSTONE_DIET |
| 8308 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8309 | #endif |
| 8310 | }, |
| 8311 | { |
| 8312 | AArch64_MLSvvv_4S, ARM64_INS_MLS, |
| 8313 | #ifndef CAPSTONE_DIET |
| 8314 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8315 | #endif |
| 8316 | }, |
| 8317 | { |
| 8318 | AArch64_MLSvvv_8B, ARM64_INS_MLS, |
| 8319 | #ifndef CAPSTONE_DIET |
| 8320 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8321 | #endif |
| 8322 | }, |
| 8323 | { |
| 8324 | AArch64_MLSvvv_8H, ARM64_INS_MLS, |
| 8325 | #ifndef CAPSTONE_DIET |
| 8326 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8327 | #endif |
| 8328 | }, |
| 8329 | { |
| 8330 | AArch64_MOVIdi, ARM64_INS_MOVI, |
| 8331 | #ifndef CAPSTONE_DIET |
| 8332 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8333 | #endif |
| 8334 | }, |
| 8335 | { |
| 8336 | AArch64_MOVIvi_16B, ARM64_INS_MOVI, |
| 8337 | #ifndef CAPSTONE_DIET |
| 8338 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8339 | #endif |
| 8340 | }, |
| 8341 | { |
| 8342 | AArch64_MOVIvi_2D, ARM64_INS_MOVI, |
| 8343 | #ifndef CAPSTONE_DIET |
| 8344 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8345 | #endif |
| 8346 | }, |
| 8347 | { |
| 8348 | AArch64_MOVIvi_8B, ARM64_INS_MOVI, |
| 8349 | #ifndef CAPSTONE_DIET |
| 8350 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8351 | #endif |
| 8352 | }, |
| 8353 | { |
| 8354 | AArch64_MOVIvi_lsl_2S, ARM64_INS_MOVI, |
| 8355 | #ifndef CAPSTONE_DIET |
| 8356 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8357 | #endif |
| 8358 | }, |
| 8359 | { |
| 8360 | AArch64_MOVIvi_lsl_4H, ARM64_INS_MOVI, |
| 8361 | #ifndef CAPSTONE_DIET |
| 8362 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8363 | #endif |
| 8364 | }, |
| 8365 | { |
| 8366 | AArch64_MOVIvi_lsl_4S, ARM64_INS_MOVI, |
| 8367 | #ifndef CAPSTONE_DIET |
| 8368 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8369 | #endif |
| 8370 | }, |
| 8371 | { |
| 8372 | AArch64_MOVIvi_lsl_8H, ARM64_INS_MOVI, |
| 8373 | #ifndef CAPSTONE_DIET |
| 8374 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8375 | #endif |
| 8376 | }, |
| 8377 | { |
| 8378 | AArch64_MOVIvi_msl_2S, ARM64_INS_MOVI, |
| 8379 | #ifndef CAPSTONE_DIET |
| 8380 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8381 | #endif |
| 8382 | }, |
| 8383 | { |
| 8384 | AArch64_MOVIvi_msl_4S, ARM64_INS_MOVI, |
| 8385 | #ifndef CAPSTONE_DIET |
| 8386 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8387 | #endif |
| 8388 | }, |
| 8389 | { |
| 8390 | AArch64_MOVKwii, ARM64_INS_MOVK, |
| 8391 | #ifndef CAPSTONE_DIET |
| 8392 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8393 | #endif |
| 8394 | }, |
| 8395 | { |
| 8396 | AArch64_MOVKxii, ARM64_INS_MOVK, |
| 8397 | #ifndef CAPSTONE_DIET |
| 8398 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8399 | #endif |
| 8400 | }, |
| 8401 | { |
| 8402 | AArch64_MOVNwii, ARM64_INS_MOVN, |
| 8403 | #ifndef CAPSTONE_DIET |
| 8404 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8405 | #endif |
| 8406 | }, |
| 8407 | { |
| 8408 | AArch64_MOVNxii, ARM64_INS_MOVN, |
| 8409 | #ifndef CAPSTONE_DIET |
| 8410 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8411 | #endif |
| 8412 | }, |
| 8413 | { |
| 8414 | AArch64_MOVZwii, ARM64_INS_MOVZ, |
| 8415 | #ifndef CAPSTONE_DIET |
| 8416 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8417 | #endif |
| 8418 | }, |
| 8419 | { |
| 8420 | AArch64_MOVZxii, ARM64_INS_MOVZ, |
| 8421 | #ifndef CAPSTONE_DIET |
| 8422 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8423 | #endif |
| 8424 | }, |
| 8425 | { |
| 8426 | AArch64_MRSxi, ARM64_INS_MRS, |
| 8427 | #ifndef CAPSTONE_DIET |
| 8428 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8429 | #endif |
| 8430 | }, |
| 8431 | { |
| 8432 | AArch64_MSRii, ARM64_INS_MSR, |
| 8433 | #ifndef CAPSTONE_DIET |
| 8434 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8435 | #endif |
| 8436 | }, |
| 8437 | { |
| 8438 | AArch64_MSRix, ARM64_INS_MSR, |
| 8439 | #ifndef CAPSTONE_DIET |
| 8440 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8441 | #endif |
| 8442 | }, |
| 8443 | { |
| 8444 | AArch64_MSUBwwww, ARM64_INS_MSUB, |
| 8445 | #ifndef CAPSTONE_DIET |
| 8446 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8447 | #endif |
| 8448 | }, |
| 8449 | { |
| 8450 | AArch64_MSUBxxxx, ARM64_INS_MSUB, |
| 8451 | #ifndef CAPSTONE_DIET |
| 8452 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8453 | #endif |
| 8454 | }, |
| 8455 | { |
| 8456 | AArch64_MULve_2s4s, ARM64_INS_MUL, |
| 8457 | #ifndef CAPSTONE_DIET |
| 8458 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8459 | #endif |
| 8460 | }, |
| 8461 | { |
| 8462 | AArch64_MULve_4h8h, ARM64_INS_MUL, |
| 8463 | #ifndef CAPSTONE_DIET |
| 8464 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8465 | #endif |
| 8466 | }, |
| 8467 | { |
| 8468 | AArch64_MULve_4s4s, ARM64_INS_MUL, |
| 8469 | #ifndef CAPSTONE_DIET |
| 8470 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8471 | #endif |
| 8472 | }, |
| 8473 | { |
| 8474 | AArch64_MULve_8h8h, ARM64_INS_MUL, |
| 8475 | #ifndef CAPSTONE_DIET |
| 8476 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8477 | #endif |
| 8478 | }, |
| 8479 | { |
| 8480 | AArch64_MULvvv_16B, ARM64_INS_MUL, |
| 8481 | #ifndef CAPSTONE_DIET |
| 8482 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8483 | #endif |
| 8484 | }, |
| 8485 | { |
| 8486 | AArch64_MULvvv_2S, ARM64_INS_MUL, |
| 8487 | #ifndef CAPSTONE_DIET |
| 8488 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8489 | #endif |
| 8490 | }, |
| 8491 | { |
| 8492 | AArch64_MULvvv_4H, ARM64_INS_MUL, |
| 8493 | #ifndef CAPSTONE_DIET |
| 8494 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8495 | #endif |
| 8496 | }, |
| 8497 | { |
| 8498 | AArch64_MULvvv_4S, ARM64_INS_MUL, |
| 8499 | #ifndef CAPSTONE_DIET |
| 8500 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8501 | #endif |
| 8502 | }, |
| 8503 | { |
| 8504 | AArch64_MULvvv_8B, ARM64_INS_MUL, |
| 8505 | #ifndef CAPSTONE_DIET |
| 8506 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8507 | #endif |
| 8508 | }, |
| 8509 | { |
| 8510 | AArch64_MULvvv_8H, ARM64_INS_MUL, |
| 8511 | #ifndef CAPSTONE_DIET |
| 8512 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8513 | #endif |
| 8514 | }, |
| 8515 | { |
| 8516 | AArch64_MVNIvi_lsl_2S, ARM64_INS_MVNI, |
| 8517 | #ifndef CAPSTONE_DIET |
| 8518 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8519 | #endif |
| 8520 | }, |
| 8521 | { |
| 8522 | AArch64_MVNIvi_lsl_4H, ARM64_INS_MVNI, |
| 8523 | #ifndef CAPSTONE_DIET |
| 8524 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8525 | #endif |
| 8526 | }, |
| 8527 | { |
| 8528 | AArch64_MVNIvi_lsl_4S, ARM64_INS_MVNI, |
| 8529 | #ifndef CAPSTONE_DIET |
| 8530 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8531 | #endif |
| 8532 | }, |
| 8533 | { |
| 8534 | AArch64_MVNIvi_lsl_8H, ARM64_INS_MVNI, |
| 8535 | #ifndef CAPSTONE_DIET |
| 8536 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8537 | #endif |
| 8538 | }, |
| 8539 | { |
| 8540 | AArch64_MVNIvi_msl_2S, ARM64_INS_MVNI, |
| 8541 | #ifndef CAPSTONE_DIET |
| 8542 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8543 | #endif |
| 8544 | }, |
| 8545 | { |
| 8546 | AArch64_MVNIvi_msl_4S, ARM64_INS_MVNI, |
| 8547 | #ifndef CAPSTONE_DIET |
| 8548 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8549 | #endif |
| 8550 | }, |
| 8551 | { |
| 8552 | AArch64_MVNww_asr, ARM64_INS_MVN, |
| 8553 | #ifndef CAPSTONE_DIET |
| 8554 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8555 | #endif |
| 8556 | }, |
| 8557 | { |
| 8558 | AArch64_MVNww_lsl, ARM64_INS_MVN, |
| 8559 | #ifndef CAPSTONE_DIET |
| 8560 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8561 | #endif |
| 8562 | }, |
| 8563 | { |
| 8564 | AArch64_MVNww_lsr, ARM64_INS_MVN, |
| 8565 | #ifndef CAPSTONE_DIET |
| 8566 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8567 | #endif |
| 8568 | }, |
| 8569 | { |
| 8570 | AArch64_MVNww_ror, ARM64_INS_MVN, |
| 8571 | #ifndef CAPSTONE_DIET |
| 8572 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8573 | #endif |
| 8574 | }, |
| 8575 | { |
| 8576 | AArch64_MVNxx_asr, ARM64_INS_MVN, |
| 8577 | #ifndef CAPSTONE_DIET |
| 8578 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8579 | #endif |
| 8580 | }, |
| 8581 | { |
| 8582 | AArch64_MVNxx_lsl, ARM64_INS_MVN, |
| 8583 | #ifndef CAPSTONE_DIET |
| 8584 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8585 | #endif |
| 8586 | }, |
| 8587 | { |
| 8588 | AArch64_MVNxx_lsr, ARM64_INS_MVN, |
| 8589 | #ifndef CAPSTONE_DIET |
| 8590 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8591 | #endif |
| 8592 | }, |
| 8593 | { |
| 8594 | AArch64_MVNxx_ror, ARM64_INS_MVN, |
| 8595 | #ifndef CAPSTONE_DIET |
| 8596 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8597 | #endif |
| 8598 | }, |
| 8599 | { |
| 8600 | AArch64_NEG16b, ARM64_INS_NEG, |
| 8601 | #ifndef CAPSTONE_DIET |
| 8602 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8603 | #endif |
| 8604 | }, |
| 8605 | { |
| 8606 | AArch64_NEG2d, ARM64_INS_NEG, |
| 8607 | #ifndef CAPSTONE_DIET |
| 8608 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8609 | #endif |
| 8610 | }, |
| 8611 | { |
| 8612 | AArch64_NEG2s, ARM64_INS_NEG, |
| 8613 | #ifndef CAPSTONE_DIET |
| 8614 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8615 | #endif |
| 8616 | }, |
| 8617 | { |
| 8618 | AArch64_NEG4h, ARM64_INS_NEG, |
| 8619 | #ifndef CAPSTONE_DIET |
| 8620 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8621 | #endif |
| 8622 | }, |
| 8623 | { |
| 8624 | AArch64_NEG4s, ARM64_INS_NEG, |
| 8625 | #ifndef CAPSTONE_DIET |
| 8626 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8627 | #endif |
| 8628 | }, |
| 8629 | { |
| 8630 | AArch64_NEG8b, ARM64_INS_NEG, |
| 8631 | #ifndef CAPSTONE_DIET |
| 8632 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8633 | #endif |
| 8634 | }, |
| 8635 | { |
| 8636 | AArch64_NEG8h, ARM64_INS_NEG, |
| 8637 | #ifndef CAPSTONE_DIET |
| 8638 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8639 | #endif |
| 8640 | }, |
| 8641 | { |
| 8642 | AArch64_NEGdd, ARM64_INS_NEG, |
| 8643 | #ifndef CAPSTONE_DIET |
| 8644 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8645 | #endif |
| 8646 | }, |
| 8647 | { |
| 8648 | AArch64_NOT16b, ARM64_INS_NOT, |
| 8649 | #ifndef CAPSTONE_DIET |
| 8650 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8651 | #endif |
| 8652 | }, |
| 8653 | { |
| 8654 | AArch64_NOT8b, ARM64_INS_NOT, |
| 8655 | #ifndef CAPSTONE_DIET |
| 8656 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8657 | #endif |
| 8658 | }, |
| 8659 | { |
| 8660 | AArch64_ORNvvv_16B, ARM64_INS_ORN, |
| 8661 | #ifndef CAPSTONE_DIET |
| 8662 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8663 | #endif |
| 8664 | }, |
| 8665 | { |
| 8666 | AArch64_ORNvvv_8B, ARM64_INS_ORN, |
| 8667 | #ifndef CAPSTONE_DIET |
| 8668 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8669 | #endif |
| 8670 | }, |
| 8671 | { |
| 8672 | AArch64_ORNwww_asr, ARM64_INS_ORN, |
| 8673 | #ifndef CAPSTONE_DIET |
| 8674 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8675 | #endif |
| 8676 | }, |
| 8677 | { |
| 8678 | AArch64_ORNwww_lsl, ARM64_INS_ORN, |
| 8679 | #ifndef CAPSTONE_DIET |
| 8680 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8681 | #endif |
| 8682 | }, |
| 8683 | { |
| 8684 | AArch64_ORNwww_lsr, ARM64_INS_ORN, |
| 8685 | #ifndef CAPSTONE_DIET |
| 8686 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8687 | #endif |
| 8688 | }, |
| 8689 | { |
| 8690 | AArch64_ORNwww_ror, ARM64_INS_ORN, |
| 8691 | #ifndef CAPSTONE_DIET |
| 8692 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8693 | #endif |
| 8694 | }, |
| 8695 | { |
| 8696 | AArch64_ORNxxx_asr, ARM64_INS_ORN, |
| 8697 | #ifndef CAPSTONE_DIET |
| 8698 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8699 | #endif |
| 8700 | }, |
| 8701 | { |
| 8702 | AArch64_ORNxxx_lsl, ARM64_INS_ORN, |
| 8703 | #ifndef CAPSTONE_DIET |
| 8704 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8705 | #endif |
| 8706 | }, |
| 8707 | { |
| 8708 | AArch64_ORNxxx_lsr, ARM64_INS_ORN, |
| 8709 | #ifndef CAPSTONE_DIET |
| 8710 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8711 | #endif |
| 8712 | }, |
| 8713 | { |
| 8714 | AArch64_ORNxxx_ror, ARM64_INS_ORN, |
| 8715 | #ifndef CAPSTONE_DIET |
| 8716 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8717 | #endif |
| 8718 | }, |
| 8719 | { |
| 8720 | AArch64_ORRvi_lsl_2S, ARM64_INS_ORR, |
| 8721 | #ifndef CAPSTONE_DIET |
| 8722 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8723 | #endif |
| 8724 | }, |
| 8725 | { |
| 8726 | AArch64_ORRvi_lsl_4H, ARM64_INS_ORR, |
| 8727 | #ifndef CAPSTONE_DIET |
| 8728 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8729 | #endif |
| 8730 | }, |
| 8731 | { |
| 8732 | AArch64_ORRvi_lsl_4S, ARM64_INS_ORR, |
| 8733 | #ifndef CAPSTONE_DIET |
| 8734 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8735 | #endif |
| 8736 | }, |
| 8737 | { |
| 8738 | AArch64_ORRvi_lsl_8H, ARM64_INS_ORR, |
| 8739 | #ifndef CAPSTONE_DIET |
| 8740 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8741 | #endif |
| 8742 | }, |
| 8743 | { |
| 8744 | AArch64_ORRvvv_16B, ARM64_INS_ORR, |
| 8745 | #ifndef CAPSTONE_DIET |
| 8746 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8747 | #endif |
| 8748 | }, |
| 8749 | { |
| 8750 | AArch64_ORRvvv_8B, ARM64_INS_ORR, |
| 8751 | #ifndef CAPSTONE_DIET |
| 8752 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8753 | #endif |
| 8754 | }, |
| 8755 | { |
| 8756 | AArch64_ORRwwi, ARM64_INS_ORR, |
| 8757 | #ifndef CAPSTONE_DIET |
| 8758 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8759 | #endif |
| 8760 | }, |
| 8761 | { |
| 8762 | AArch64_ORRwww_asr, ARM64_INS_ORR, |
| 8763 | #ifndef CAPSTONE_DIET |
| 8764 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8765 | #endif |
| 8766 | }, |
| 8767 | { |
| 8768 | AArch64_ORRwww_lsl, ARM64_INS_ORR, |
| 8769 | #ifndef CAPSTONE_DIET |
| 8770 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8771 | #endif |
| 8772 | }, |
| 8773 | { |
| 8774 | AArch64_ORRwww_lsr, ARM64_INS_ORR, |
| 8775 | #ifndef CAPSTONE_DIET |
| 8776 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8777 | #endif |
| 8778 | }, |
| 8779 | { |
| 8780 | AArch64_ORRwww_ror, ARM64_INS_ORR, |
| 8781 | #ifndef CAPSTONE_DIET |
| 8782 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8783 | #endif |
| 8784 | }, |
| 8785 | { |
| 8786 | AArch64_ORRxxi, ARM64_INS_ORR, |
| 8787 | #ifndef CAPSTONE_DIET |
| 8788 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8789 | #endif |
| 8790 | }, |
| 8791 | { |
| 8792 | AArch64_ORRxxx_asr, ARM64_INS_ORR, |
| 8793 | #ifndef CAPSTONE_DIET |
| 8794 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8795 | #endif |
| 8796 | }, |
| 8797 | { |
| 8798 | AArch64_ORRxxx_lsl, ARM64_INS_ORR, |
| 8799 | #ifndef CAPSTONE_DIET |
| 8800 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8801 | #endif |
| 8802 | }, |
| 8803 | { |
| 8804 | AArch64_ORRxxx_lsr, ARM64_INS_ORR, |
| 8805 | #ifndef CAPSTONE_DIET |
| 8806 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8807 | #endif |
| 8808 | }, |
| 8809 | { |
| 8810 | AArch64_ORRxxx_ror, ARM64_INS_ORR, |
| 8811 | #ifndef CAPSTONE_DIET |
| 8812 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8813 | #endif |
| 8814 | }, |
| 8815 | { |
| 8816 | AArch64_PMULL2vvv_1q2d, ARM64_INS_PMULL2, |
| 8817 | #ifndef CAPSTONE_DIET |
| 8818 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8819 | #endif |
| 8820 | }, |
| 8821 | { |
| 8822 | AArch64_PMULL2vvv_8h16b, ARM64_INS_PMULL2, |
| 8823 | #ifndef CAPSTONE_DIET |
| 8824 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8825 | #endif |
| 8826 | }, |
| 8827 | { |
| 8828 | AArch64_PMULLvvv_1q1d, ARM64_INS_PMULL, |
| 8829 | #ifndef CAPSTONE_DIET |
| 8830 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8831 | #endif |
| 8832 | }, |
| 8833 | { |
| 8834 | AArch64_PMULLvvv_8h8b, ARM64_INS_PMULL, |
| 8835 | #ifndef CAPSTONE_DIET |
| 8836 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8837 | #endif |
| 8838 | }, |
| 8839 | { |
| 8840 | AArch64_PMULvvv_16B, ARM64_INS_PMUL, |
| 8841 | #ifndef CAPSTONE_DIET |
| 8842 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8843 | #endif |
| 8844 | }, |
| 8845 | { |
| 8846 | AArch64_PMULvvv_8B, ARM64_INS_PMUL, |
| 8847 | #ifndef CAPSTONE_DIET |
| 8848 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8849 | #endif |
| 8850 | }, |
| 8851 | { |
| 8852 | AArch64_PRFM, ARM64_INS_PRFM, |
| 8853 | #ifndef CAPSTONE_DIET |
| 8854 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8855 | #endif |
| 8856 | }, |
| 8857 | { |
| 8858 | AArch64_PRFM_Wm_RegOffset, ARM64_INS_PRFM, |
| 8859 | #ifndef CAPSTONE_DIET |
| 8860 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8861 | #endif |
| 8862 | }, |
| 8863 | { |
| 8864 | AArch64_PRFM_Xm_RegOffset, ARM64_INS_PRFM, |
| 8865 | #ifndef CAPSTONE_DIET |
| 8866 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8867 | #endif |
| 8868 | }, |
| 8869 | { |
| 8870 | AArch64_PRFM_lit, ARM64_INS_PRFM, |
| 8871 | #ifndef CAPSTONE_DIET |
| 8872 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8873 | #endif |
| 8874 | }, |
| 8875 | { |
| 8876 | AArch64_PRFUM, ARM64_INS_PRFUM, |
| 8877 | #ifndef CAPSTONE_DIET |
| 8878 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 8879 | #endif |
| 8880 | }, |
| 8881 | { |
| 8882 | AArch64_QRSHRUNvvi_16B, ARM64_INS_SQRSHRUN2, |
| 8883 | #ifndef CAPSTONE_DIET |
| 8884 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8885 | #endif |
| 8886 | }, |
| 8887 | { |
| 8888 | AArch64_QRSHRUNvvi_2S, ARM64_INS_SQRSHRUN, |
| 8889 | #ifndef CAPSTONE_DIET |
| 8890 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8891 | #endif |
| 8892 | }, |
| 8893 | { |
| 8894 | AArch64_QRSHRUNvvi_4H, ARM64_INS_SQRSHRUN, |
| 8895 | #ifndef CAPSTONE_DIET |
| 8896 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8897 | #endif |
| 8898 | }, |
| 8899 | { |
| 8900 | AArch64_QRSHRUNvvi_4S, ARM64_INS_SQRSHRUN2, |
| 8901 | #ifndef CAPSTONE_DIET |
| 8902 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8903 | #endif |
| 8904 | }, |
| 8905 | { |
| 8906 | AArch64_QRSHRUNvvi_8B, ARM64_INS_SQRSHRUN, |
| 8907 | #ifndef CAPSTONE_DIET |
| 8908 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8909 | #endif |
| 8910 | }, |
| 8911 | { |
| 8912 | AArch64_QRSHRUNvvi_8H, ARM64_INS_SQRSHRUN2, |
| 8913 | #ifndef CAPSTONE_DIET |
| 8914 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8915 | #endif |
| 8916 | }, |
| 8917 | { |
| 8918 | AArch64_QSHRUNvvi_16B, ARM64_INS_SQSHRUN2, |
| 8919 | #ifndef CAPSTONE_DIET |
| 8920 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8921 | #endif |
| 8922 | }, |
| 8923 | { |
| 8924 | AArch64_QSHRUNvvi_2S, ARM64_INS_SQSHRUN, |
| 8925 | #ifndef CAPSTONE_DIET |
| 8926 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8927 | #endif |
| 8928 | }, |
| 8929 | { |
| 8930 | AArch64_QSHRUNvvi_4H, ARM64_INS_SQSHRUN, |
| 8931 | #ifndef CAPSTONE_DIET |
| 8932 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8933 | #endif |
| 8934 | }, |
| 8935 | { |
| 8936 | AArch64_QSHRUNvvi_4S, ARM64_INS_SQSHRUN2, |
| 8937 | #ifndef CAPSTONE_DIET |
| 8938 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8939 | #endif |
| 8940 | }, |
| 8941 | { |
| 8942 | AArch64_QSHRUNvvi_8B, ARM64_INS_SQSHRUN, |
| 8943 | #ifndef CAPSTONE_DIET |
| 8944 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8945 | #endif |
| 8946 | }, |
| 8947 | { |
| 8948 | AArch64_QSHRUNvvi_8H, ARM64_INS_SQSHRUN2, |
| 8949 | #ifndef CAPSTONE_DIET |
| 8950 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8951 | #endif |
| 8952 | }, |
| 8953 | { |
| 8954 | AArch64_RADDHN2vvv_16b8h, ARM64_INS_RADDHN2, |
| 8955 | #ifndef CAPSTONE_DIET |
| 8956 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8957 | #endif |
| 8958 | }, |
| 8959 | { |
| 8960 | AArch64_RADDHN2vvv_4s2d, ARM64_INS_RADDHN2, |
| 8961 | #ifndef CAPSTONE_DIET |
| 8962 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8963 | #endif |
| 8964 | }, |
| 8965 | { |
| 8966 | AArch64_RADDHN2vvv_8h4s, ARM64_INS_RADDHN2, |
| 8967 | #ifndef CAPSTONE_DIET |
| 8968 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8969 | #endif |
| 8970 | }, |
| 8971 | { |
| 8972 | AArch64_RADDHNvvv_2s2d, ARM64_INS_RADDHN, |
| 8973 | #ifndef CAPSTONE_DIET |
| 8974 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8975 | #endif |
| 8976 | }, |
| 8977 | { |
| 8978 | AArch64_RADDHNvvv_4h4s, ARM64_INS_RADDHN, |
| 8979 | #ifndef CAPSTONE_DIET |
| 8980 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8981 | #endif |
| 8982 | }, |
| 8983 | { |
| 8984 | AArch64_RADDHNvvv_8b8h, ARM64_INS_RADDHN, |
| 8985 | #ifndef CAPSTONE_DIET |
| 8986 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8987 | #endif |
| 8988 | }, |
| 8989 | { |
| 8990 | AArch64_RBIT16b, ARM64_INS_RBIT, |
| 8991 | #ifndef CAPSTONE_DIET |
| 8992 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8993 | #endif |
| 8994 | }, |
| 8995 | { |
| 8996 | AArch64_RBIT8b, ARM64_INS_RBIT, |
| 8997 | #ifndef CAPSTONE_DIET |
| 8998 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 8999 | #endif |
| 9000 | }, |
| 9001 | { |
| 9002 | AArch64_RBITww, ARM64_INS_RBIT, |
| 9003 | #ifndef CAPSTONE_DIET |
| 9004 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9005 | #endif |
| 9006 | }, |
| 9007 | { |
| 9008 | AArch64_RBITxx, ARM64_INS_RBIT, |
| 9009 | #ifndef CAPSTONE_DIET |
| 9010 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9011 | #endif |
| 9012 | }, |
| 9013 | { |
| 9014 | AArch64_RETx, ARM64_INS_RET, |
| 9015 | #ifndef CAPSTONE_DIET |
| 9016 | { 0 }, { 0 }, { 0 }, 1, 1 |
| 9017 | #endif |
| 9018 | }, |
| 9019 | { |
| 9020 | AArch64_REV16_16b, ARM64_INS_REV16, |
| 9021 | #ifndef CAPSTONE_DIET |
| 9022 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9023 | #endif |
| 9024 | }, |
| 9025 | { |
| 9026 | AArch64_REV16_8b, ARM64_INS_REV16, |
| 9027 | #ifndef CAPSTONE_DIET |
| 9028 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9029 | #endif |
| 9030 | }, |
| 9031 | { |
| 9032 | AArch64_REV16ww, ARM64_INS_REV16, |
| 9033 | #ifndef CAPSTONE_DIET |
| 9034 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9035 | #endif |
| 9036 | }, |
| 9037 | { |
| 9038 | AArch64_REV16xx, ARM64_INS_REV16, |
| 9039 | #ifndef CAPSTONE_DIET |
| 9040 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9041 | #endif |
| 9042 | }, |
| 9043 | { |
| 9044 | AArch64_REV32_16b, ARM64_INS_REV32, |
| 9045 | #ifndef CAPSTONE_DIET |
| 9046 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9047 | #endif |
| 9048 | }, |
| 9049 | { |
| 9050 | AArch64_REV32_4h, ARM64_INS_REV32, |
| 9051 | #ifndef CAPSTONE_DIET |
| 9052 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9053 | #endif |
| 9054 | }, |
| 9055 | { |
| 9056 | AArch64_REV32_8b, ARM64_INS_REV32, |
| 9057 | #ifndef CAPSTONE_DIET |
| 9058 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9059 | #endif |
| 9060 | }, |
| 9061 | { |
| 9062 | AArch64_REV32_8h, ARM64_INS_REV32, |
| 9063 | #ifndef CAPSTONE_DIET |
| 9064 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9065 | #endif |
| 9066 | }, |
| 9067 | { |
| 9068 | AArch64_REV32xx, ARM64_INS_REV32, |
| 9069 | #ifndef CAPSTONE_DIET |
| 9070 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9071 | #endif |
| 9072 | }, |
| 9073 | { |
| 9074 | AArch64_REV64_16b, ARM64_INS_REV64, |
| 9075 | #ifndef CAPSTONE_DIET |
| 9076 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9077 | #endif |
| 9078 | }, |
| 9079 | { |
| 9080 | AArch64_REV64_2s, ARM64_INS_REV64, |
| 9081 | #ifndef CAPSTONE_DIET |
| 9082 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9083 | #endif |
| 9084 | }, |
| 9085 | { |
| 9086 | AArch64_REV64_4h, ARM64_INS_REV64, |
| 9087 | #ifndef CAPSTONE_DIET |
| 9088 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9089 | #endif |
| 9090 | }, |
| 9091 | { |
| 9092 | AArch64_REV64_4s, ARM64_INS_REV64, |
| 9093 | #ifndef CAPSTONE_DIET |
| 9094 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9095 | #endif |
| 9096 | }, |
| 9097 | { |
| 9098 | AArch64_REV64_8b, ARM64_INS_REV64, |
| 9099 | #ifndef CAPSTONE_DIET |
| 9100 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9101 | #endif |
| 9102 | }, |
| 9103 | { |
| 9104 | AArch64_REV64_8h, ARM64_INS_REV64, |
| 9105 | #ifndef CAPSTONE_DIET |
| 9106 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9107 | #endif |
| 9108 | }, |
| 9109 | { |
| 9110 | AArch64_REVww, ARM64_INS_REV, |
| 9111 | #ifndef CAPSTONE_DIET |
| 9112 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9113 | #endif |
| 9114 | }, |
| 9115 | { |
| 9116 | AArch64_REVxx, ARM64_INS_REV, |
| 9117 | #ifndef CAPSTONE_DIET |
| 9118 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9119 | #endif |
| 9120 | }, |
| 9121 | { |
| 9122 | AArch64_RORVwww, ARM64_INS_ROR, |
| 9123 | #ifndef CAPSTONE_DIET |
| 9124 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9125 | #endif |
| 9126 | }, |
| 9127 | { |
| 9128 | AArch64_RORVxxx, ARM64_INS_ROR, |
| 9129 | #ifndef CAPSTONE_DIET |
| 9130 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9131 | #endif |
| 9132 | }, |
| 9133 | { |
| 9134 | AArch64_RSHRNvvi_16B, ARM64_INS_RSHRN2, |
| 9135 | #ifndef CAPSTONE_DIET |
| 9136 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9137 | #endif |
| 9138 | }, |
| 9139 | { |
| 9140 | AArch64_RSHRNvvi_2S, ARM64_INS_RSHRN, |
| 9141 | #ifndef CAPSTONE_DIET |
| 9142 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9143 | #endif |
| 9144 | }, |
| 9145 | { |
| 9146 | AArch64_RSHRNvvi_4H, ARM64_INS_RSHRN, |
| 9147 | #ifndef CAPSTONE_DIET |
| 9148 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9149 | #endif |
| 9150 | }, |
| 9151 | { |
| 9152 | AArch64_RSHRNvvi_4S, ARM64_INS_RSHRN2, |
| 9153 | #ifndef CAPSTONE_DIET |
| 9154 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9155 | #endif |
| 9156 | }, |
| 9157 | { |
| 9158 | AArch64_RSHRNvvi_8B, ARM64_INS_RSHRN, |
| 9159 | #ifndef CAPSTONE_DIET |
| 9160 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9161 | #endif |
| 9162 | }, |
| 9163 | { |
| 9164 | AArch64_RSHRNvvi_8H, ARM64_INS_RSHRN2, |
| 9165 | #ifndef CAPSTONE_DIET |
| 9166 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9167 | #endif |
| 9168 | }, |
| 9169 | { |
| 9170 | AArch64_RSUBHN2vvv_16b8h, ARM64_INS_RSUBHN2, |
| 9171 | #ifndef CAPSTONE_DIET |
| 9172 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9173 | #endif |
| 9174 | }, |
| 9175 | { |
| 9176 | AArch64_RSUBHN2vvv_4s2d, ARM64_INS_RSUBHN2, |
| 9177 | #ifndef CAPSTONE_DIET |
| 9178 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9179 | #endif |
| 9180 | }, |
| 9181 | { |
| 9182 | AArch64_RSUBHN2vvv_8h4s, ARM64_INS_RSUBHN2, |
| 9183 | #ifndef CAPSTONE_DIET |
| 9184 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9185 | #endif |
| 9186 | }, |
| 9187 | { |
| 9188 | AArch64_RSUBHNvvv_2s2d, ARM64_INS_RSUBHN, |
| 9189 | #ifndef CAPSTONE_DIET |
| 9190 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9191 | #endif |
| 9192 | }, |
| 9193 | { |
| 9194 | AArch64_RSUBHNvvv_4h4s, ARM64_INS_RSUBHN, |
| 9195 | #ifndef CAPSTONE_DIET |
| 9196 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9197 | #endif |
| 9198 | }, |
| 9199 | { |
| 9200 | AArch64_RSUBHNvvv_8b8h, ARM64_INS_RSUBHN, |
| 9201 | #ifndef CAPSTONE_DIET |
| 9202 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9203 | #endif |
| 9204 | }, |
| 9205 | { |
| 9206 | AArch64_SABAL2vvv_2d2s, ARM64_INS_SABAL2, |
| 9207 | #ifndef CAPSTONE_DIET |
| 9208 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9209 | #endif |
| 9210 | }, |
| 9211 | { |
| 9212 | AArch64_SABAL2vvv_4s4h, ARM64_INS_SABAL2, |
| 9213 | #ifndef CAPSTONE_DIET |
| 9214 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9215 | #endif |
| 9216 | }, |
| 9217 | { |
| 9218 | AArch64_SABAL2vvv_8h8b, ARM64_INS_SABAL2, |
| 9219 | #ifndef CAPSTONE_DIET |
| 9220 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9221 | #endif |
| 9222 | }, |
| 9223 | { |
| 9224 | AArch64_SABALvvv_2d2s, ARM64_INS_SABAL, |
| 9225 | #ifndef CAPSTONE_DIET |
| 9226 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9227 | #endif |
| 9228 | }, |
| 9229 | { |
| 9230 | AArch64_SABALvvv_4s4h, ARM64_INS_SABAL, |
| 9231 | #ifndef CAPSTONE_DIET |
| 9232 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9233 | #endif |
| 9234 | }, |
| 9235 | { |
| 9236 | AArch64_SABALvvv_8h8b, ARM64_INS_SABAL, |
| 9237 | #ifndef CAPSTONE_DIET |
| 9238 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9239 | #endif |
| 9240 | }, |
| 9241 | { |
| 9242 | AArch64_SABAvvv_16B, ARM64_INS_SABA, |
| 9243 | #ifndef CAPSTONE_DIET |
| 9244 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9245 | #endif |
| 9246 | }, |
| 9247 | { |
| 9248 | AArch64_SABAvvv_2S, ARM64_INS_SABA, |
| 9249 | #ifndef CAPSTONE_DIET |
| 9250 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9251 | #endif |
| 9252 | }, |
| 9253 | { |
| 9254 | AArch64_SABAvvv_4H, ARM64_INS_SABA, |
| 9255 | #ifndef CAPSTONE_DIET |
| 9256 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9257 | #endif |
| 9258 | }, |
| 9259 | { |
| 9260 | AArch64_SABAvvv_4S, ARM64_INS_SABA, |
| 9261 | #ifndef CAPSTONE_DIET |
| 9262 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9263 | #endif |
| 9264 | }, |
| 9265 | { |
| 9266 | AArch64_SABAvvv_8B, ARM64_INS_SABA, |
| 9267 | #ifndef CAPSTONE_DIET |
| 9268 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9269 | #endif |
| 9270 | }, |
| 9271 | { |
| 9272 | AArch64_SABAvvv_8H, ARM64_INS_SABA, |
| 9273 | #ifndef CAPSTONE_DIET |
| 9274 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9275 | #endif |
| 9276 | }, |
| 9277 | { |
| 9278 | AArch64_SABDL2vvv_2d2s, ARM64_INS_SABDL2, |
| 9279 | #ifndef CAPSTONE_DIET |
| 9280 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9281 | #endif |
| 9282 | }, |
| 9283 | { |
| 9284 | AArch64_SABDL2vvv_4s4h, ARM64_INS_SABDL2, |
| 9285 | #ifndef CAPSTONE_DIET |
| 9286 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9287 | #endif |
| 9288 | }, |
| 9289 | { |
| 9290 | AArch64_SABDL2vvv_8h8b, ARM64_INS_SABDL2, |
| 9291 | #ifndef CAPSTONE_DIET |
| 9292 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9293 | #endif |
| 9294 | }, |
| 9295 | { |
| 9296 | AArch64_SABDLvvv_2d2s, ARM64_INS_SABDL, |
| 9297 | #ifndef CAPSTONE_DIET |
| 9298 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9299 | #endif |
| 9300 | }, |
| 9301 | { |
| 9302 | AArch64_SABDLvvv_4s4h, ARM64_INS_SABDL, |
| 9303 | #ifndef CAPSTONE_DIET |
| 9304 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9305 | #endif |
| 9306 | }, |
| 9307 | { |
| 9308 | AArch64_SABDLvvv_8h8b, ARM64_INS_SABDL, |
| 9309 | #ifndef CAPSTONE_DIET |
| 9310 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9311 | #endif |
| 9312 | }, |
| 9313 | { |
| 9314 | AArch64_SABDvvv_16B, ARM64_INS_SABD, |
| 9315 | #ifndef CAPSTONE_DIET |
| 9316 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9317 | #endif |
| 9318 | }, |
| 9319 | { |
| 9320 | AArch64_SABDvvv_2S, ARM64_INS_SABD, |
| 9321 | #ifndef CAPSTONE_DIET |
| 9322 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9323 | #endif |
| 9324 | }, |
| 9325 | { |
| 9326 | AArch64_SABDvvv_4H, ARM64_INS_SABD, |
| 9327 | #ifndef CAPSTONE_DIET |
| 9328 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9329 | #endif |
| 9330 | }, |
| 9331 | { |
| 9332 | AArch64_SABDvvv_4S, ARM64_INS_SABD, |
| 9333 | #ifndef CAPSTONE_DIET |
| 9334 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9335 | #endif |
| 9336 | }, |
| 9337 | { |
| 9338 | AArch64_SABDvvv_8B, ARM64_INS_SABD, |
| 9339 | #ifndef CAPSTONE_DIET |
| 9340 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9341 | #endif |
| 9342 | }, |
| 9343 | { |
| 9344 | AArch64_SABDvvv_8H, ARM64_INS_SABD, |
| 9345 | #ifndef CAPSTONE_DIET |
| 9346 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9347 | #endif |
| 9348 | }, |
| 9349 | { |
| 9350 | AArch64_SADALP16b8h, ARM64_INS_SADALP, |
| 9351 | #ifndef CAPSTONE_DIET |
| 9352 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9353 | #endif |
| 9354 | }, |
| 9355 | { |
| 9356 | AArch64_SADALP2s1d, ARM64_INS_SADALP, |
| 9357 | #ifndef CAPSTONE_DIET |
| 9358 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9359 | #endif |
| 9360 | }, |
| 9361 | { |
| 9362 | AArch64_SADALP4h2s, ARM64_INS_SADALP, |
| 9363 | #ifndef CAPSTONE_DIET |
| 9364 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9365 | #endif |
| 9366 | }, |
| 9367 | { |
| 9368 | AArch64_SADALP4s2d, ARM64_INS_SADALP, |
| 9369 | #ifndef CAPSTONE_DIET |
| 9370 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9371 | #endif |
| 9372 | }, |
| 9373 | { |
| 9374 | AArch64_SADALP8b4h, ARM64_INS_SADALP, |
| 9375 | #ifndef CAPSTONE_DIET |
| 9376 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9377 | #endif |
| 9378 | }, |
| 9379 | { |
| 9380 | AArch64_SADALP8h4s, ARM64_INS_SADALP, |
| 9381 | #ifndef CAPSTONE_DIET |
| 9382 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9383 | #endif |
| 9384 | }, |
| 9385 | { |
| 9386 | AArch64_SADDL2vvv_2d4s, ARM64_INS_SADDL2, |
| 9387 | #ifndef CAPSTONE_DIET |
| 9388 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9389 | #endif |
| 9390 | }, |
| 9391 | { |
| 9392 | AArch64_SADDL2vvv_4s8h, ARM64_INS_SADDL2, |
| 9393 | #ifndef CAPSTONE_DIET |
| 9394 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9395 | #endif |
| 9396 | }, |
| 9397 | { |
| 9398 | AArch64_SADDL2vvv_8h16b, ARM64_INS_SADDL2, |
| 9399 | #ifndef CAPSTONE_DIET |
| 9400 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9401 | #endif |
| 9402 | }, |
| 9403 | { |
| 9404 | AArch64_SADDLP16b8h, ARM64_INS_SADDLP, |
| 9405 | #ifndef CAPSTONE_DIET |
| 9406 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9407 | #endif |
| 9408 | }, |
| 9409 | { |
| 9410 | AArch64_SADDLP2s1d, ARM64_INS_SADDLP, |
| 9411 | #ifndef CAPSTONE_DIET |
| 9412 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9413 | #endif |
| 9414 | }, |
| 9415 | { |
| 9416 | AArch64_SADDLP4h2s, ARM64_INS_SADDLP, |
| 9417 | #ifndef CAPSTONE_DIET |
| 9418 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9419 | #endif |
| 9420 | }, |
| 9421 | { |
| 9422 | AArch64_SADDLP4s2d, ARM64_INS_SADDLP, |
| 9423 | #ifndef CAPSTONE_DIET |
| 9424 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9425 | #endif |
| 9426 | }, |
| 9427 | { |
| 9428 | AArch64_SADDLP8b4h, ARM64_INS_SADDLP, |
| 9429 | #ifndef CAPSTONE_DIET |
| 9430 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9431 | #endif |
| 9432 | }, |
| 9433 | { |
| 9434 | AArch64_SADDLP8h4s, ARM64_INS_SADDLP, |
| 9435 | #ifndef CAPSTONE_DIET |
| 9436 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9437 | #endif |
| 9438 | }, |
| 9439 | { |
| 9440 | AArch64_SADDLV_1d4s, ARM64_INS_SADDLV, |
| 9441 | #ifndef CAPSTONE_DIET |
| 9442 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9443 | #endif |
| 9444 | }, |
| 9445 | { |
| 9446 | AArch64_SADDLV_1h16b, ARM64_INS_SADDLV, |
| 9447 | #ifndef CAPSTONE_DIET |
| 9448 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9449 | #endif |
| 9450 | }, |
| 9451 | { |
| 9452 | AArch64_SADDLV_1h8b, ARM64_INS_SADDLV, |
| 9453 | #ifndef CAPSTONE_DIET |
| 9454 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9455 | #endif |
| 9456 | }, |
| 9457 | { |
| 9458 | AArch64_SADDLV_1s4h, ARM64_INS_SADDLV, |
| 9459 | #ifndef CAPSTONE_DIET |
| 9460 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9461 | #endif |
| 9462 | }, |
| 9463 | { |
| 9464 | AArch64_SADDLV_1s8h, ARM64_INS_SADDLV, |
| 9465 | #ifndef CAPSTONE_DIET |
| 9466 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9467 | #endif |
| 9468 | }, |
| 9469 | { |
| 9470 | AArch64_SADDLvvv_2d2s, ARM64_INS_SADDL, |
| 9471 | #ifndef CAPSTONE_DIET |
| 9472 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9473 | #endif |
| 9474 | }, |
| 9475 | { |
| 9476 | AArch64_SADDLvvv_4s4h, ARM64_INS_SADDL, |
| 9477 | #ifndef CAPSTONE_DIET |
| 9478 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9479 | #endif |
| 9480 | }, |
| 9481 | { |
| 9482 | AArch64_SADDLvvv_8h8b, ARM64_INS_SADDL, |
| 9483 | #ifndef CAPSTONE_DIET |
| 9484 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9485 | #endif |
| 9486 | }, |
| 9487 | { |
| 9488 | AArch64_SADDW2vvv_2d4s, ARM64_INS_SADDW2, |
| 9489 | #ifndef CAPSTONE_DIET |
| 9490 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9491 | #endif |
| 9492 | }, |
| 9493 | { |
| 9494 | AArch64_SADDW2vvv_4s8h, ARM64_INS_SADDW2, |
| 9495 | #ifndef CAPSTONE_DIET |
| 9496 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9497 | #endif |
| 9498 | }, |
| 9499 | { |
| 9500 | AArch64_SADDW2vvv_8h16b, ARM64_INS_SADDW2, |
| 9501 | #ifndef CAPSTONE_DIET |
| 9502 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9503 | #endif |
| 9504 | }, |
| 9505 | { |
| 9506 | AArch64_SADDWvvv_2d2s, ARM64_INS_SADDW, |
| 9507 | #ifndef CAPSTONE_DIET |
| 9508 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9509 | #endif |
| 9510 | }, |
| 9511 | { |
| 9512 | AArch64_SADDWvvv_4s4h, ARM64_INS_SADDW, |
| 9513 | #ifndef CAPSTONE_DIET |
| 9514 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9515 | #endif |
| 9516 | }, |
| 9517 | { |
| 9518 | AArch64_SADDWvvv_8h8b, ARM64_INS_SADDW, |
| 9519 | #ifndef CAPSTONE_DIET |
| 9520 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9521 | #endif |
| 9522 | }, |
| 9523 | { |
| 9524 | AArch64_SBCSwww, ARM64_INS_SBC, |
| 9525 | #ifndef CAPSTONE_DIET |
| 9526 | { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 9527 | #endif |
| 9528 | }, |
| 9529 | { |
| 9530 | AArch64_SBCSxxx, ARM64_INS_SBC, |
| 9531 | #ifndef CAPSTONE_DIET |
| 9532 | { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 9533 | #endif |
| 9534 | }, |
| 9535 | { |
| 9536 | AArch64_SBCwww, ARM64_INS_SBC, |
| 9537 | #ifndef CAPSTONE_DIET |
| 9538 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 9539 | #endif |
| 9540 | }, |
| 9541 | { |
| 9542 | AArch64_SBCxxx, ARM64_INS_SBC, |
| 9543 | #ifndef CAPSTONE_DIET |
| 9544 | { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| 9545 | #endif |
| 9546 | }, |
| 9547 | { |
| 9548 | AArch64_SBFIZwwii, ARM64_INS_SBFIZ, |
| 9549 | #ifndef CAPSTONE_DIET |
| 9550 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9551 | #endif |
| 9552 | }, |
| 9553 | { |
| 9554 | AArch64_SBFIZxxii, ARM64_INS_SBFIZ, |
| 9555 | #ifndef CAPSTONE_DIET |
| 9556 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9557 | #endif |
| 9558 | }, |
| 9559 | { |
| 9560 | AArch64_SBFMwwii, ARM64_INS_SBFM, |
| 9561 | #ifndef CAPSTONE_DIET |
| 9562 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9563 | #endif |
| 9564 | }, |
| 9565 | { |
| 9566 | AArch64_SBFMxxii, ARM64_INS_SBFM, |
| 9567 | #ifndef CAPSTONE_DIET |
| 9568 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9569 | #endif |
| 9570 | }, |
| 9571 | { |
| 9572 | AArch64_SBFXwwii, ARM64_INS_SBFX, |
| 9573 | #ifndef CAPSTONE_DIET |
| 9574 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9575 | #endif |
| 9576 | }, |
| 9577 | { |
| 9578 | AArch64_SBFXxxii, ARM64_INS_SBFX, |
| 9579 | #ifndef CAPSTONE_DIET |
| 9580 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9581 | #endif |
| 9582 | }, |
| 9583 | { |
| 9584 | AArch64_SCVTF_2d, ARM64_INS_SCVTF, |
| 9585 | #ifndef CAPSTONE_DIET |
| 9586 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9587 | #endif |
| 9588 | }, |
| 9589 | { |
| 9590 | AArch64_SCVTF_2s, ARM64_INS_SCVTF, |
| 9591 | #ifndef CAPSTONE_DIET |
| 9592 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9593 | #endif |
| 9594 | }, |
| 9595 | { |
| 9596 | AArch64_SCVTF_4s, ARM64_INS_SCVTF, |
| 9597 | #ifndef CAPSTONE_DIET |
| 9598 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9599 | #endif |
| 9600 | }, |
| 9601 | { |
| 9602 | AArch64_SCVTF_Nddi, ARM64_INS_SCVTF, |
| 9603 | #ifndef CAPSTONE_DIET |
| 9604 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9605 | #endif |
| 9606 | }, |
| 9607 | { |
| 9608 | AArch64_SCVTF_Nssi, ARM64_INS_SCVTF, |
| 9609 | #ifndef CAPSTONE_DIET |
| 9610 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9611 | #endif |
| 9612 | }, |
| 9613 | { |
| 9614 | AArch64_SCVTFdd, ARM64_INS_SCVTF, |
| 9615 | #ifndef CAPSTONE_DIET |
| 9616 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9617 | #endif |
| 9618 | }, |
| 9619 | { |
| 9620 | AArch64_SCVTFdw, ARM64_INS_SCVTF, |
| 9621 | #ifndef CAPSTONE_DIET |
| 9622 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 9623 | #endif |
| 9624 | }, |
| 9625 | { |
| 9626 | AArch64_SCVTFdwi, ARM64_INS_SCVTF, |
| 9627 | #ifndef CAPSTONE_DIET |
| 9628 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 9629 | #endif |
| 9630 | }, |
| 9631 | { |
| 9632 | AArch64_SCVTFdx, ARM64_INS_SCVTF, |
| 9633 | #ifndef CAPSTONE_DIET |
| 9634 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 9635 | #endif |
| 9636 | }, |
| 9637 | { |
| 9638 | AArch64_SCVTFdxi, ARM64_INS_SCVTF, |
| 9639 | #ifndef CAPSTONE_DIET |
| 9640 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 9641 | #endif |
| 9642 | }, |
| 9643 | { |
| 9644 | AArch64_SCVTFss, ARM64_INS_SCVTF, |
| 9645 | #ifndef CAPSTONE_DIET |
| 9646 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9647 | #endif |
| 9648 | }, |
| 9649 | { |
| 9650 | AArch64_SCVTFsw, ARM64_INS_SCVTF, |
| 9651 | #ifndef CAPSTONE_DIET |
| 9652 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 9653 | #endif |
| 9654 | }, |
| 9655 | { |
| 9656 | AArch64_SCVTFswi, ARM64_INS_SCVTF, |
| 9657 | #ifndef CAPSTONE_DIET |
| 9658 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 9659 | #endif |
| 9660 | }, |
| 9661 | { |
| 9662 | AArch64_SCVTFsx, ARM64_INS_SCVTF, |
| 9663 | #ifndef CAPSTONE_DIET |
| 9664 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 9665 | #endif |
| 9666 | }, |
| 9667 | { |
| 9668 | AArch64_SCVTFsxi, ARM64_INS_SCVTF, |
| 9669 | #ifndef CAPSTONE_DIET |
| 9670 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 9671 | #endif |
| 9672 | }, |
| 9673 | { |
| 9674 | AArch64_SDIVwww, ARM64_INS_SDIV, |
| 9675 | #ifndef CAPSTONE_DIET |
| 9676 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9677 | #endif |
| 9678 | }, |
| 9679 | { |
| 9680 | AArch64_SDIVxxx, ARM64_INS_SDIV, |
| 9681 | #ifndef CAPSTONE_DIET |
| 9682 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9683 | #endif |
| 9684 | }, |
| 9685 | { |
| 9686 | AArch64_SHA1C, ARM64_INS_SHA1C, |
| 9687 | #ifndef CAPSTONE_DIET |
| 9688 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9689 | #endif |
| 9690 | }, |
| 9691 | { |
| 9692 | AArch64_SHA1H, ARM64_INS_SHA1H, |
| 9693 | #ifndef CAPSTONE_DIET |
| 9694 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9695 | #endif |
| 9696 | }, |
| 9697 | { |
| 9698 | AArch64_SHA1M, ARM64_INS_SHA1M, |
| 9699 | #ifndef CAPSTONE_DIET |
| 9700 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9701 | #endif |
| 9702 | }, |
| 9703 | { |
| 9704 | AArch64_SHA1P, ARM64_INS_SHA1P, |
| 9705 | #ifndef CAPSTONE_DIET |
| 9706 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9707 | #endif |
| 9708 | }, |
| 9709 | { |
| 9710 | AArch64_SHA1SU0, ARM64_INS_SHA1SU0, |
| 9711 | #ifndef CAPSTONE_DIET |
| 9712 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9713 | #endif |
| 9714 | }, |
| 9715 | { |
| 9716 | AArch64_SHA1SU1, ARM64_INS_SHA1SU1, |
| 9717 | #ifndef CAPSTONE_DIET |
| 9718 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9719 | #endif |
| 9720 | }, |
| 9721 | { |
| 9722 | AArch64_SHA256H, ARM64_INS_SHA256H, |
| 9723 | #ifndef CAPSTONE_DIET |
| 9724 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9725 | #endif |
| 9726 | }, |
| 9727 | { |
| 9728 | AArch64_SHA256H2, ARM64_INS_SHA256H2, |
| 9729 | #ifndef CAPSTONE_DIET |
| 9730 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9731 | #endif |
| 9732 | }, |
| 9733 | { |
| 9734 | AArch64_SHA256SU0, ARM64_INS_SHA256SU0, |
| 9735 | #ifndef CAPSTONE_DIET |
| 9736 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9737 | #endif |
| 9738 | }, |
| 9739 | { |
| 9740 | AArch64_SHA256SU1, ARM64_INS_SHA256SU1, |
| 9741 | #ifndef CAPSTONE_DIET |
| 9742 | { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| 9743 | #endif |
| 9744 | }, |
| 9745 | { |
| 9746 | AArch64_SHADDvvv_16B, ARM64_INS_SHADD, |
| 9747 | #ifndef CAPSTONE_DIET |
| 9748 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9749 | #endif |
| 9750 | }, |
| 9751 | { |
| 9752 | AArch64_SHADDvvv_2S, ARM64_INS_SHADD, |
| 9753 | #ifndef CAPSTONE_DIET |
| 9754 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9755 | #endif |
| 9756 | }, |
| 9757 | { |
| 9758 | AArch64_SHADDvvv_4H, ARM64_INS_SHADD, |
| 9759 | #ifndef CAPSTONE_DIET |
| 9760 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9761 | #endif |
| 9762 | }, |
| 9763 | { |
| 9764 | AArch64_SHADDvvv_4S, ARM64_INS_SHADD, |
| 9765 | #ifndef CAPSTONE_DIET |
| 9766 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9767 | #endif |
| 9768 | }, |
| 9769 | { |
| 9770 | AArch64_SHADDvvv_8B, ARM64_INS_SHADD, |
| 9771 | #ifndef CAPSTONE_DIET |
| 9772 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9773 | #endif |
| 9774 | }, |
| 9775 | { |
| 9776 | AArch64_SHADDvvv_8H, ARM64_INS_SHADD, |
| 9777 | #ifndef CAPSTONE_DIET |
| 9778 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9779 | #endif |
| 9780 | }, |
| 9781 | { |
| 9782 | AArch64_SHLL16b8h, ARM64_INS_SHLL2, |
| 9783 | #ifndef CAPSTONE_DIET |
| 9784 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9785 | #endif |
| 9786 | }, |
| 9787 | { |
| 9788 | AArch64_SHLL2s2d, ARM64_INS_SHLL, |
| 9789 | #ifndef CAPSTONE_DIET |
| 9790 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9791 | #endif |
| 9792 | }, |
| 9793 | { |
| 9794 | AArch64_SHLL4h4s, ARM64_INS_SHLL, |
| 9795 | #ifndef CAPSTONE_DIET |
| 9796 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9797 | #endif |
| 9798 | }, |
| 9799 | { |
| 9800 | AArch64_SHLL4s2d, ARM64_INS_SHLL2, |
| 9801 | #ifndef CAPSTONE_DIET |
| 9802 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9803 | #endif |
| 9804 | }, |
| 9805 | { |
| 9806 | AArch64_SHLL8b8h, ARM64_INS_SHLL, |
| 9807 | #ifndef CAPSTONE_DIET |
| 9808 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9809 | #endif |
| 9810 | }, |
| 9811 | { |
| 9812 | AArch64_SHLL8h4s, ARM64_INS_SHLL2, |
| 9813 | #ifndef CAPSTONE_DIET |
| 9814 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9815 | #endif |
| 9816 | }, |
| 9817 | { |
| 9818 | AArch64_SHLddi, ARM64_INS_SHL, |
| 9819 | #ifndef CAPSTONE_DIET |
| 9820 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9821 | #endif |
| 9822 | }, |
| 9823 | { |
| 9824 | AArch64_SHLvvi_16B, ARM64_INS_SHL, |
| 9825 | #ifndef CAPSTONE_DIET |
| 9826 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9827 | #endif |
| 9828 | }, |
| 9829 | { |
| 9830 | AArch64_SHLvvi_2D, ARM64_INS_SHL, |
| 9831 | #ifndef CAPSTONE_DIET |
| 9832 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9833 | #endif |
| 9834 | }, |
| 9835 | { |
| 9836 | AArch64_SHLvvi_2S, ARM64_INS_SHL, |
| 9837 | #ifndef CAPSTONE_DIET |
| 9838 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9839 | #endif |
| 9840 | }, |
| 9841 | { |
| 9842 | AArch64_SHLvvi_4H, ARM64_INS_SHL, |
| 9843 | #ifndef CAPSTONE_DIET |
| 9844 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9845 | #endif |
| 9846 | }, |
| 9847 | { |
| 9848 | AArch64_SHLvvi_4S, ARM64_INS_SHL, |
| 9849 | #ifndef CAPSTONE_DIET |
| 9850 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9851 | #endif |
| 9852 | }, |
| 9853 | { |
| 9854 | AArch64_SHLvvi_8B, ARM64_INS_SHL, |
| 9855 | #ifndef CAPSTONE_DIET |
| 9856 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9857 | #endif |
| 9858 | }, |
| 9859 | { |
| 9860 | AArch64_SHLvvi_8H, ARM64_INS_SHL, |
| 9861 | #ifndef CAPSTONE_DIET |
| 9862 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9863 | #endif |
| 9864 | }, |
| 9865 | { |
| 9866 | AArch64_SHRNvvi_16B, ARM64_INS_SHRN2, |
| 9867 | #ifndef CAPSTONE_DIET |
| 9868 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9869 | #endif |
| 9870 | }, |
| 9871 | { |
| 9872 | AArch64_SHRNvvi_2S, ARM64_INS_SHRN, |
| 9873 | #ifndef CAPSTONE_DIET |
| 9874 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9875 | #endif |
| 9876 | }, |
| 9877 | { |
| 9878 | AArch64_SHRNvvi_4H, ARM64_INS_SHRN, |
| 9879 | #ifndef CAPSTONE_DIET |
| 9880 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9881 | #endif |
| 9882 | }, |
| 9883 | { |
| 9884 | AArch64_SHRNvvi_4S, ARM64_INS_SHRN2, |
| 9885 | #ifndef CAPSTONE_DIET |
| 9886 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9887 | #endif |
| 9888 | }, |
| 9889 | { |
| 9890 | AArch64_SHRNvvi_8B, ARM64_INS_SHRN, |
| 9891 | #ifndef CAPSTONE_DIET |
| 9892 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9893 | #endif |
| 9894 | }, |
| 9895 | { |
| 9896 | AArch64_SHRNvvi_8H, ARM64_INS_SHRN2, |
| 9897 | #ifndef CAPSTONE_DIET |
| 9898 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9899 | #endif |
| 9900 | }, |
| 9901 | { |
| 9902 | AArch64_SHSUBvvv_16B, ARM64_INS_SHSUB, |
| 9903 | #ifndef CAPSTONE_DIET |
| 9904 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9905 | #endif |
| 9906 | }, |
| 9907 | { |
| 9908 | AArch64_SHSUBvvv_2S, ARM64_INS_SHSUB, |
| 9909 | #ifndef CAPSTONE_DIET |
| 9910 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9911 | #endif |
| 9912 | }, |
| 9913 | { |
| 9914 | AArch64_SHSUBvvv_4H, ARM64_INS_SHSUB, |
| 9915 | #ifndef CAPSTONE_DIET |
| 9916 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9917 | #endif |
| 9918 | }, |
| 9919 | { |
| 9920 | AArch64_SHSUBvvv_4S, ARM64_INS_SHSUB, |
| 9921 | #ifndef CAPSTONE_DIET |
| 9922 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9923 | #endif |
| 9924 | }, |
| 9925 | { |
| 9926 | AArch64_SHSUBvvv_8B, ARM64_INS_SHSUB, |
| 9927 | #ifndef CAPSTONE_DIET |
| 9928 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9929 | #endif |
| 9930 | }, |
| 9931 | { |
| 9932 | AArch64_SHSUBvvv_8H, ARM64_INS_SHSUB, |
| 9933 | #ifndef CAPSTONE_DIET |
| 9934 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9935 | #endif |
| 9936 | }, |
| 9937 | { |
| 9938 | AArch64_SLI, ARM64_INS_SLI, |
| 9939 | #ifndef CAPSTONE_DIET |
| 9940 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9941 | #endif |
| 9942 | }, |
| 9943 | { |
| 9944 | AArch64_SLIvvi_16B, ARM64_INS_SLI, |
| 9945 | #ifndef CAPSTONE_DIET |
| 9946 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9947 | #endif |
| 9948 | }, |
| 9949 | { |
| 9950 | AArch64_SLIvvi_2D, ARM64_INS_SLI, |
| 9951 | #ifndef CAPSTONE_DIET |
| 9952 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9953 | #endif |
| 9954 | }, |
| 9955 | { |
| 9956 | AArch64_SLIvvi_2S, ARM64_INS_SLI, |
| 9957 | #ifndef CAPSTONE_DIET |
| 9958 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9959 | #endif |
| 9960 | }, |
| 9961 | { |
| 9962 | AArch64_SLIvvi_4H, ARM64_INS_SLI, |
| 9963 | #ifndef CAPSTONE_DIET |
| 9964 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9965 | #endif |
| 9966 | }, |
| 9967 | { |
| 9968 | AArch64_SLIvvi_4S, ARM64_INS_SLI, |
| 9969 | #ifndef CAPSTONE_DIET |
| 9970 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9971 | #endif |
| 9972 | }, |
| 9973 | { |
| 9974 | AArch64_SLIvvi_8B, ARM64_INS_SLI, |
| 9975 | #ifndef CAPSTONE_DIET |
| 9976 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9977 | #endif |
| 9978 | }, |
| 9979 | { |
| 9980 | AArch64_SLIvvi_8H, ARM64_INS_SLI, |
| 9981 | #ifndef CAPSTONE_DIET |
| 9982 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9983 | #endif |
| 9984 | }, |
| 9985 | { |
| 9986 | AArch64_SMADDLxwwx, ARM64_INS_SMADDL, |
| 9987 | #ifndef CAPSTONE_DIET |
| 9988 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 9989 | #endif |
| 9990 | }, |
| 9991 | { |
| 9992 | AArch64_SMAXPvvv_16B, ARM64_INS_SMAXP, |
| 9993 | #ifndef CAPSTONE_DIET |
| 9994 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 9995 | #endif |
| 9996 | }, |
| 9997 | { |
| 9998 | AArch64_SMAXPvvv_2S, ARM64_INS_SMAXP, |
| 9999 | #ifndef CAPSTONE_DIET |
| 10000 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10001 | #endif |
| 10002 | }, |
| 10003 | { |
| 10004 | AArch64_SMAXPvvv_4H, ARM64_INS_SMAXP, |
| 10005 | #ifndef CAPSTONE_DIET |
| 10006 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10007 | #endif |
| 10008 | }, |
| 10009 | { |
| 10010 | AArch64_SMAXPvvv_4S, ARM64_INS_SMAXP, |
| 10011 | #ifndef CAPSTONE_DIET |
| 10012 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10013 | #endif |
| 10014 | }, |
| 10015 | { |
| 10016 | AArch64_SMAXPvvv_8B, ARM64_INS_SMAXP, |
| 10017 | #ifndef CAPSTONE_DIET |
| 10018 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10019 | #endif |
| 10020 | }, |
| 10021 | { |
| 10022 | AArch64_SMAXPvvv_8H, ARM64_INS_SMAXP, |
| 10023 | #ifndef CAPSTONE_DIET |
| 10024 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10025 | #endif |
| 10026 | }, |
| 10027 | { |
| 10028 | AArch64_SMAXV_1b16b, ARM64_INS_SMAXV, |
| 10029 | #ifndef CAPSTONE_DIET |
| 10030 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10031 | #endif |
| 10032 | }, |
| 10033 | { |
| 10034 | AArch64_SMAXV_1b8b, ARM64_INS_SMAXV, |
| 10035 | #ifndef CAPSTONE_DIET |
| 10036 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10037 | #endif |
| 10038 | }, |
| 10039 | { |
| 10040 | AArch64_SMAXV_1h4h, ARM64_INS_SMAXV, |
| 10041 | #ifndef CAPSTONE_DIET |
| 10042 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10043 | #endif |
| 10044 | }, |
| 10045 | { |
| 10046 | AArch64_SMAXV_1h8h, ARM64_INS_SMAXV, |
| 10047 | #ifndef CAPSTONE_DIET |
| 10048 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10049 | #endif |
| 10050 | }, |
| 10051 | { |
| 10052 | AArch64_SMAXV_1s4s, ARM64_INS_SMAXV, |
| 10053 | #ifndef CAPSTONE_DIET |
| 10054 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10055 | #endif |
| 10056 | }, |
| 10057 | { |
| 10058 | AArch64_SMAXvvv_16B, ARM64_INS_SMAX, |
| 10059 | #ifndef CAPSTONE_DIET |
| 10060 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10061 | #endif |
| 10062 | }, |
| 10063 | { |
| 10064 | AArch64_SMAXvvv_2S, ARM64_INS_SMAX, |
| 10065 | #ifndef CAPSTONE_DIET |
| 10066 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10067 | #endif |
| 10068 | }, |
| 10069 | { |
| 10070 | AArch64_SMAXvvv_4H, ARM64_INS_SMAX, |
| 10071 | #ifndef CAPSTONE_DIET |
| 10072 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10073 | #endif |
| 10074 | }, |
| 10075 | { |
| 10076 | AArch64_SMAXvvv_4S, ARM64_INS_SMAX, |
| 10077 | #ifndef CAPSTONE_DIET |
| 10078 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10079 | #endif |
| 10080 | }, |
| 10081 | { |
| 10082 | AArch64_SMAXvvv_8B, ARM64_INS_SMAX, |
| 10083 | #ifndef CAPSTONE_DIET |
| 10084 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10085 | #endif |
| 10086 | }, |
| 10087 | { |
| 10088 | AArch64_SMAXvvv_8H, ARM64_INS_SMAX, |
| 10089 | #ifndef CAPSTONE_DIET |
| 10090 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10091 | #endif |
| 10092 | }, |
| 10093 | { |
| 10094 | AArch64_SMCi, ARM64_INS_SMC, |
| 10095 | #ifndef CAPSTONE_DIET |
| 10096 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 10097 | #endif |
| 10098 | }, |
| 10099 | { |
| 10100 | AArch64_SMINPvvv_16B, ARM64_INS_SMINP, |
| 10101 | #ifndef CAPSTONE_DIET |
| 10102 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10103 | #endif |
| 10104 | }, |
| 10105 | { |
| 10106 | AArch64_SMINPvvv_2S, ARM64_INS_SMINP, |
| 10107 | #ifndef CAPSTONE_DIET |
| 10108 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10109 | #endif |
| 10110 | }, |
| 10111 | { |
| 10112 | AArch64_SMINPvvv_4H, ARM64_INS_SMINP, |
| 10113 | #ifndef CAPSTONE_DIET |
| 10114 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10115 | #endif |
| 10116 | }, |
| 10117 | { |
| 10118 | AArch64_SMINPvvv_4S, ARM64_INS_SMINP, |
| 10119 | #ifndef CAPSTONE_DIET |
| 10120 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10121 | #endif |
| 10122 | }, |
| 10123 | { |
| 10124 | AArch64_SMINPvvv_8B, ARM64_INS_SMINP, |
| 10125 | #ifndef CAPSTONE_DIET |
| 10126 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10127 | #endif |
| 10128 | }, |
| 10129 | { |
| 10130 | AArch64_SMINPvvv_8H, ARM64_INS_SMINP, |
| 10131 | #ifndef CAPSTONE_DIET |
| 10132 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10133 | #endif |
| 10134 | }, |
| 10135 | { |
| 10136 | AArch64_SMINV_1b16b, ARM64_INS_SMINV, |
| 10137 | #ifndef CAPSTONE_DIET |
| 10138 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10139 | #endif |
| 10140 | }, |
| 10141 | { |
| 10142 | AArch64_SMINV_1b8b, ARM64_INS_SMINV, |
| 10143 | #ifndef CAPSTONE_DIET |
| 10144 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10145 | #endif |
| 10146 | }, |
| 10147 | { |
| 10148 | AArch64_SMINV_1h4h, ARM64_INS_SMINV, |
| 10149 | #ifndef CAPSTONE_DIET |
| 10150 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10151 | #endif |
| 10152 | }, |
| 10153 | { |
| 10154 | AArch64_SMINV_1h8h, ARM64_INS_SMINV, |
| 10155 | #ifndef CAPSTONE_DIET |
| 10156 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10157 | #endif |
| 10158 | }, |
| 10159 | { |
| 10160 | AArch64_SMINV_1s4s, ARM64_INS_SMINV, |
| 10161 | #ifndef CAPSTONE_DIET |
| 10162 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10163 | #endif |
| 10164 | }, |
| 10165 | { |
| 10166 | AArch64_SMINvvv_16B, ARM64_INS_SMIN, |
| 10167 | #ifndef CAPSTONE_DIET |
| 10168 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10169 | #endif |
| 10170 | }, |
| 10171 | { |
| 10172 | AArch64_SMINvvv_2S, ARM64_INS_SMIN, |
| 10173 | #ifndef CAPSTONE_DIET |
| 10174 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10175 | #endif |
| 10176 | }, |
| 10177 | { |
| 10178 | AArch64_SMINvvv_4H, ARM64_INS_SMIN, |
| 10179 | #ifndef CAPSTONE_DIET |
| 10180 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10181 | #endif |
| 10182 | }, |
| 10183 | { |
| 10184 | AArch64_SMINvvv_4S, ARM64_INS_SMIN, |
| 10185 | #ifndef CAPSTONE_DIET |
| 10186 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10187 | #endif |
| 10188 | }, |
| 10189 | { |
| 10190 | AArch64_SMINvvv_8B, ARM64_INS_SMIN, |
| 10191 | #ifndef CAPSTONE_DIET |
| 10192 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10193 | #endif |
| 10194 | }, |
| 10195 | { |
| 10196 | AArch64_SMINvvv_8H, ARM64_INS_SMIN, |
| 10197 | #ifndef CAPSTONE_DIET |
| 10198 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10199 | #endif |
| 10200 | }, |
| 10201 | { |
| 10202 | AArch64_SMLAL2vvv_2d4s, ARM64_INS_SMLAL2, |
| 10203 | #ifndef CAPSTONE_DIET |
| 10204 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10205 | #endif |
| 10206 | }, |
| 10207 | { |
| 10208 | AArch64_SMLAL2vvv_4s8h, ARM64_INS_SMLAL2, |
| 10209 | #ifndef CAPSTONE_DIET |
| 10210 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10211 | #endif |
| 10212 | }, |
| 10213 | { |
| 10214 | AArch64_SMLAL2vvv_8h16b, ARM64_INS_SMLAL2, |
| 10215 | #ifndef CAPSTONE_DIET |
| 10216 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10217 | #endif |
| 10218 | }, |
| 10219 | { |
| 10220 | AArch64_SMLALvve_2d2s, ARM64_INS_SMLAL, |
| 10221 | #ifndef CAPSTONE_DIET |
| 10222 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10223 | #endif |
| 10224 | }, |
| 10225 | { |
| 10226 | AArch64_SMLALvve_2d4s, ARM64_INS_SMLAL2, |
| 10227 | #ifndef CAPSTONE_DIET |
| 10228 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10229 | #endif |
| 10230 | }, |
| 10231 | { |
| 10232 | AArch64_SMLALvve_4s4h, ARM64_INS_SMLAL, |
| 10233 | #ifndef CAPSTONE_DIET |
| 10234 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10235 | #endif |
| 10236 | }, |
| 10237 | { |
| 10238 | AArch64_SMLALvve_4s8h, ARM64_INS_SMLAL2, |
| 10239 | #ifndef CAPSTONE_DIET |
| 10240 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10241 | #endif |
| 10242 | }, |
| 10243 | { |
| 10244 | AArch64_SMLALvvv_2d2s, ARM64_INS_SMLAL, |
| 10245 | #ifndef CAPSTONE_DIET |
| 10246 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10247 | #endif |
| 10248 | }, |
| 10249 | { |
| 10250 | AArch64_SMLALvvv_4s4h, ARM64_INS_SMLAL, |
| 10251 | #ifndef CAPSTONE_DIET |
| 10252 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10253 | #endif |
| 10254 | }, |
| 10255 | { |
| 10256 | AArch64_SMLALvvv_8h8b, ARM64_INS_SMLAL, |
| 10257 | #ifndef CAPSTONE_DIET |
| 10258 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10259 | #endif |
| 10260 | }, |
| 10261 | { |
| 10262 | AArch64_SMLSL2vvv_2d4s, ARM64_INS_SMLSL2, |
| 10263 | #ifndef CAPSTONE_DIET |
| 10264 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10265 | #endif |
| 10266 | }, |
| 10267 | { |
| 10268 | AArch64_SMLSL2vvv_4s8h, ARM64_INS_SMLSL2, |
| 10269 | #ifndef CAPSTONE_DIET |
| 10270 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10271 | #endif |
| 10272 | }, |
| 10273 | { |
| 10274 | AArch64_SMLSL2vvv_8h16b, ARM64_INS_SMLSL2, |
| 10275 | #ifndef CAPSTONE_DIET |
| 10276 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10277 | #endif |
| 10278 | }, |
| 10279 | { |
| 10280 | AArch64_SMLSLvve_2d2s, ARM64_INS_SMLSL, |
| 10281 | #ifndef CAPSTONE_DIET |
| 10282 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10283 | #endif |
| 10284 | }, |
| 10285 | { |
| 10286 | AArch64_SMLSLvve_2d4s, ARM64_INS_SMLSL2, |
| 10287 | #ifndef CAPSTONE_DIET |
| 10288 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10289 | #endif |
| 10290 | }, |
| 10291 | { |
| 10292 | AArch64_SMLSLvve_4s4h, ARM64_INS_SMLSL, |
| 10293 | #ifndef CAPSTONE_DIET |
| 10294 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10295 | #endif |
| 10296 | }, |
| 10297 | { |
| 10298 | AArch64_SMLSLvve_4s8h, ARM64_INS_SMLSL2, |
| 10299 | #ifndef CAPSTONE_DIET |
| 10300 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10301 | #endif |
| 10302 | }, |
| 10303 | { |
| 10304 | AArch64_SMLSLvvv_2d2s, ARM64_INS_SMLSL, |
| 10305 | #ifndef CAPSTONE_DIET |
| 10306 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10307 | #endif |
| 10308 | }, |
| 10309 | { |
| 10310 | AArch64_SMLSLvvv_4s4h, ARM64_INS_SMLSL, |
| 10311 | #ifndef CAPSTONE_DIET |
| 10312 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10313 | #endif |
| 10314 | }, |
| 10315 | { |
| 10316 | AArch64_SMLSLvvv_8h8b, ARM64_INS_SMLSL, |
| 10317 | #ifndef CAPSTONE_DIET |
| 10318 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10319 | #endif |
| 10320 | }, |
| 10321 | { |
| 10322 | AArch64_SMOVwb, ARM64_INS_SMOV, |
| 10323 | #ifndef CAPSTONE_DIET |
| 10324 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10325 | #endif |
| 10326 | }, |
| 10327 | { |
| 10328 | AArch64_SMOVwh, ARM64_INS_SMOV, |
| 10329 | #ifndef CAPSTONE_DIET |
| 10330 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10331 | #endif |
| 10332 | }, |
| 10333 | { |
| 10334 | AArch64_SMOVxb, ARM64_INS_SMOV, |
| 10335 | #ifndef CAPSTONE_DIET |
| 10336 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10337 | #endif |
| 10338 | }, |
| 10339 | { |
| 10340 | AArch64_SMOVxh, ARM64_INS_SMOV, |
| 10341 | #ifndef CAPSTONE_DIET |
| 10342 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10343 | #endif |
| 10344 | }, |
| 10345 | { |
| 10346 | AArch64_SMOVxs, ARM64_INS_SMOV, |
| 10347 | #ifndef CAPSTONE_DIET |
| 10348 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10349 | #endif |
| 10350 | }, |
| 10351 | { |
| 10352 | AArch64_SMSUBLxwwx, ARM64_INS_SMSUBL, |
| 10353 | #ifndef CAPSTONE_DIET |
| 10354 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 10355 | #endif |
| 10356 | }, |
| 10357 | { |
| 10358 | AArch64_SMULHxxx, ARM64_INS_SMULH, |
| 10359 | #ifndef CAPSTONE_DIET |
| 10360 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 10361 | #endif |
| 10362 | }, |
| 10363 | { |
| 10364 | AArch64_SMULL2vvv_2d4s, ARM64_INS_SMULL2, |
| 10365 | #ifndef CAPSTONE_DIET |
| 10366 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10367 | #endif |
| 10368 | }, |
| 10369 | { |
| 10370 | AArch64_SMULL2vvv_4s8h, ARM64_INS_SMULL2, |
| 10371 | #ifndef CAPSTONE_DIET |
| 10372 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10373 | #endif |
| 10374 | }, |
| 10375 | { |
| 10376 | AArch64_SMULL2vvv_8h16b, ARM64_INS_SMULL2, |
| 10377 | #ifndef CAPSTONE_DIET |
| 10378 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10379 | #endif |
| 10380 | }, |
| 10381 | { |
| 10382 | AArch64_SMULLve_2d2s, ARM64_INS_SMULL, |
| 10383 | #ifndef CAPSTONE_DIET |
| 10384 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10385 | #endif |
| 10386 | }, |
| 10387 | { |
| 10388 | AArch64_SMULLve_2d4s, ARM64_INS_SMULL2, |
| 10389 | #ifndef CAPSTONE_DIET |
| 10390 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10391 | #endif |
| 10392 | }, |
| 10393 | { |
| 10394 | AArch64_SMULLve_4s4h, ARM64_INS_SMULL, |
| 10395 | #ifndef CAPSTONE_DIET |
| 10396 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10397 | #endif |
| 10398 | }, |
| 10399 | { |
| 10400 | AArch64_SMULLve_4s8h, ARM64_INS_SMULL2, |
| 10401 | #ifndef CAPSTONE_DIET |
| 10402 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10403 | #endif |
| 10404 | }, |
| 10405 | { |
| 10406 | AArch64_SMULLvvv_2d2s, ARM64_INS_SMULL, |
| 10407 | #ifndef CAPSTONE_DIET |
| 10408 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10409 | #endif |
| 10410 | }, |
| 10411 | { |
| 10412 | AArch64_SMULLvvv_4s4h, ARM64_INS_SMULL, |
| 10413 | #ifndef CAPSTONE_DIET |
| 10414 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10415 | #endif |
| 10416 | }, |
| 10417 | { |
| 10418 | AArch64_SMULLvvv_8h8b, ARM64_INS_SMULL, |
| 10419 | #ifndef CAPSTONE_DIET |
| 10420 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10421 | #endif |
| 10422 | }, |
| 10423 | { |
| 10424 | AArch64_SQABS16b, ARM64_INS_SQABS, |
| 10425 | #ifndef CAPSTONE_DIET |
| 10426 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10427 | #endif |
| 10428 | }, |
| 10429 | { |
| 10430 | AArch64_SQABS2d, ARM64_INS_SQABS, |
| 10431 | #ifndef CAPSTONE_DIET |
| 10432 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10433 | #endif |
| 10434 | }, |
| 10435 | { |
| 10436 | AArch64_SQABS2s, ARM64_INS_SQABS, |
| 10437 | #ifndef CAPSTONE_DIET |
| 10438 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10439 | #endif |
| 10440 | }, |
| 10441 | { |
| 10442 | AArch64_SQABS4h, ARM64_INS_SQABS, |
| 10443 | #ifndef CAPSTONE_DIET |
| 10444 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10445 | #endif |
| 10446 | }, |
| 10447 | { |
| 10448 | AArch64_SQABS4s, ARM64_INS_SQABS, |
| 10449 | #ifndef CAPSTONE_DIET |
| 10450 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10451 | #endif |
| 10452 | }, |
| 10453 | { |
| 10454 | AArch64_SQABS8b, ARM64_INS_SQABS, |
| 10455 | #ifndef CAPSTONE_DIET |
| 10456 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10457 | #endif |
| 10458 | }, |
| 10459 | { |
| 10460 | AArch64_SQABS8h, ARM64_INS_SQABS, |
| 10461 | #ifndef CAPSTONE_DIET |
| 10462 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10463 | #endif |
| 10464 | }, |
| 10465 | { |
| 10466 | AArch64_SQABSbb, ARM64_INS_SQABS, |
| 10467 | #ifndef CAPSTONE_DIET |
| 10468 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10469 | #endif |
| 10470 | }, |
| 10471 | { |
| 10472 | AArch64_SQABSdd, ARM64_INS_SQABS, |
| 10473 | #ifndef CAPSTONE_DIET |
| 10474 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10475 | #endif |
| 10476 | }, |
| 10477 | { |
| 10478 | AArch64_SQABShh, ARM64_INS_SQABS, |
| 10479 | #ifndef CAPSTONE_DIET |
| 10480 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10481 | #endif |
| 10482 | }, |
| 10483 | { |
| 10484 | AArch64_SQABSss, ARM64_INS_SQABS, |
| 10485 | #ifndef CAPSTONE_DIET |
| 10486 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10487 | #endif |
| 10488 | }, |
| 10489 | { |
| 10490 | AArch64_SQADDbbb, ARM64_INS_SQADD, |
| 10491 | #ifndef CAPSTONE_DIET |
| 10492 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10493 | #endif |
| 10494 | }, |
| 10495 | { |
| 10496 | AArch64_SQADDddd, ARM64_INS_SQADD, |
| 10497 | #ifndef CAPSTONE_DIET |
| 10498 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10499 | #endif |
| 10500 | }, |
| 10501 | { |
| 10502 | AArch64_SQADDhhh, ARM64_INS_SQADD, |
| 10503 | #ifndef CAPSTONE_DIET |
| 10504 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10505 | #endif |
| 10506 | }, |
| 10507 | { |
| 10508 | AArch64_SQADDsss, ARM64_INS_SQADD, |
| 10509 | #ifndef CAPSTONE_DIET |
| 10510 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10511 | #endif |
| 10512 | }, |
| 10513 | { |
| 10514 | AArch64_SQADDvvv_16B, ARM64_INS_SQADD, |
| 10515 | #ifndef CAPSTONE_DIET |
| 10516 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10517 | #endif |
| 10518 | }, |
| 10519 | { |
| 10520 | AArch64_SQADDvvv_2D, ARM64_INS_SQADD, |
| 10521 | #ifndef CAPSTONE_DIET |
| 10522 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10523 | #endif |
| 10524 | }, |
| 10525 | { |
| 10526 | AArch64_SQADDvvv_2S, ARM64_INS_SQADD, |
| 10527 | #ifndef CAPSTONE_DIET |
| 10528 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10529 | #endif |
| 10530 | }, |
| 10531 | { |
| 10532 | AArch64_SQADDvvv_4H, ARM64_INS_SQADD, |
| 10533 | #ifndef CAPSTONE_DIET |
| 10534 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10535 | #endif |
| 10536 | }, |
| 10537 | { |
| 10538 | AArch64_SQADDvvv_4S, ARM64_INS_SQADD, |
| 10539 | #ifndef CAPSTONE_DIET |
| 10540 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10541 | #endif |
| 10542 | }, |
| 10543 | { |
| 10544 | AArch64_SQADDvvv_8B, ARM64_INS_SQADD, |
| 10545 | #ifndef CAPSTONE_DIET |
| 10546 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10547 | #endif |
| 10548 | }, |
| 10549 | { |
| 10550 | AArch64_SQADDvvv_8H, ARM64_INS_SQADD, |
| 10551 | #ifndef CAPSTONE_DIET |
| 10552 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10553 | #endif |
| 10554 | }, |
| 10555 | { |
| 10556 | AArch64_SQDMLAL2vvv_2d4s, ARM64_INS_SQDMLAL2, |
| 10557 | #ifndef CAPSTONE_DIET |
| 10558 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10559 | #endif |
| 10560 | }, |
| 10561 | { |
| 10562 | AArch64_SQDMLAL2vvv_4s8h, ARM64_INS_SQDMLAL2, |
| 10563 | #ifndef CAPSTONE_DIET |
| 10564 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10565 | #endif |
| 10566 | }, |
| 10567 | { |
| 10568 | AArch64_SQDMLALdss, ARM64_INS_SQDMLAL, |
| 10569 | #ifndef CAPSTONE_DIET |
| 10570 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10571 | #endif |
| 10572 | }, |
| 10573 | { |
| 10574 | AArch64_SQDMLALdsv_2S, ARM64_INS_SQDMLAL, |
| 10575 | #ifndef CAPSTONE_DIET |
| 10576 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10577 | #endif |
| 10578 | }, |
| 10579 | { |
| 10580 | AArch64_SQDMLALdsv_4S, ARM64_INS_SQDMLAL, |
| 10581 | #ifndef CAPSTONE_DIET |
| 10582 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10583 | #endif |
| 10584 | }, |
| 10585 | { |
| 10586 | AArch64_SQDMLALshh, ARM64_INS_SQDMLAL, |
| 10587 | #ifndef CAPSTONE_DIET |
| 10588 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10589 | #endif |
| 10590 | }, |
| 10591 | { |
| 10592 | AArch64_SQDMLALshv_4H, ARM64_INS_SQDMLAL, |
| 10593 | #ifndef CAPSTONE_DIET |
| 10594 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10595 | #endif |
| 10596 | }, |
| 10597 | { |
| 10598 | AArch64_SQDMLALshv_8H, ARM64_INS_SQDMLAL, |
| 10599 | #ifndef CAPSTONE_DIET |
| 10600 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10601 | #endif |
| 10602 | }, |
| 10603 | { |
| 10604 | AArch64_SQDMLALvve_2d2s, ARM64_INS_SQDMLAL, |
| 10605 | #ifndef CAPSTONE_DIET |
| 10606 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10607 | #endif |
| 10608 | }, |
| 10609 | { |
| 10610 | AArch64_SQDMLALvve_2d4s, ARM64_INS_SQDMLAL2, |
| 10611 | #ifndef CAPSTONE_DIET |
| 10612 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10613 | #endif |
| 10614 | }, |
| 10615 | { |
| 10616 | AArch64_SQDMLALvve_4s4h, ARM64_INS_SQDMLAL, |
| 10617 | #ifndef CAPSTONE_DIET |
| 10618 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10619 | #endif |
| 10620 | }, |
| 10621 | { |
| 10622 | AArch64_SQDMLALvve_4s8h, ARM64_INS_SQDMLAL2, |
| 10623 | #ifndef CAPSTONE_DIET |
| 10624 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10625 | #endif |
| 10626 | }, |
| 10627 | { |
| 10628 | AArch64_SQDMLALvvv_2d2s, ARM64_INS_SQDMLAL, |
| 10629 | #ifndef CAPSTONE_DIET |
| 10630 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10631 | #endif |
| 10632 | }, |
| 10633 | { |
| 10634 | AArch64_SQDMLALvvv_4s4h, ARM64_INS_SQDMLAL, |
| 10635 | #ifndef CAPSTONE_DIET |
| 10636 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10637 | #endif |
| 10638 | }, |
| 10639 | { |
| 10640 | AArch64_SQDMLSL2vvv_2d4s, ARM64_INS_SQDMLSL2, |
| 10641 | #ifndef CAPSTONE_DIET |
| 10642 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10643 | #endif |
| 10644 | }, |
| 10645 | { |
| 10646 | AArch64_SQDMLSL2vvv_4s8h, ARM64_INS_SQDMLSL2, |
| 10647 | #ifndef CAPSTONE_DIET |
| 10648 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10649 | #endif |
| 10650 | }, |
| 10651 | { |
| 10652 | AArch64_SQDMLSLdss, ARM64_INS_SQDMLSL, |
| 10653 | #ifndef CAPSTONE_DIET |
| 10654 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10655 | #endif |
| 10656 | }, |
| 10657 | { |
| 10658 | AArch64_SQDMLSLdsv_2S, ARM64_INS_SQDMLSL, |
| 10659 | #ifndef CAPSTONE_DIET |
| 10660 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10661 | #endif |
| 10662 | }, |
| 10663 | { |
| 10664 | AArch64_SQDMLSLdsv_4S, ARM64_INS_SQDMLSL, |
| 10665 | #ifndef CAPSTONE_DIET |
| 10666 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10667 | #endif |
| 10668 | }, |
| 10669 | { |
| 10670 | AArch64_SQDMLSLshh, ARM64_INS_SQDMLSL, |
| 10671 | #ifndef CAPSTONE_DIET |
| 10672 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10673 | #endif |
| 10674 | }, |
| 10675 | { |
| 10676 | AArch64_SQDMLSLshv_4H, ARM64_INS_SQDMLSL, |
| 10677 | #ifndef CAPSTONE_DIET |
| 10678 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10679 | #endif |
| 10680 | }, |
| 10681 | { |
| 10682 | AArch64_SQDMLSLshv_8H, ARM64_INS_SQDMLSL, |
| 10683 | #ifndef CAPSTONE_DIET |
| 10684 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10685 | #endif |
| 10686 | }, |
| 10687 | { |
| 10688 | AArch64_SQDMLSLvve_2d2s, ARM64_INS_SQDMLSL, |
| 10689 | #ifndef CAPSTONE_DIET |
| 10690 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10691 | #endif |
| 10692 | }, |
| 10693 | { |
| 10694 | AArch64_SQDMLSLvve_2d4s, ARM64_INS_SQDMLSL2, |
| 10695 | #ifndef CAPSTONE_DIET |
| 10696 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10697 | #endif |
| 10698 | }, |
| 10699 | { |
| 10700 | AArch64_SQDMLSLvve_4s4h, ARM64_INS_SQDMLSL, |
| 10701 | #ifndef CAPSTONE_DIET |
| 10702 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10703 | #endif |
| 10704 | }, |
| 10705 | { |
| 10706 | AArch64_SQDMLSLvve_4s8h, ARM64_INS_SQDMLSL2, |
| 10707 | #ifndef CAPSTONE_DIET |
| 10708 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10709 | #endif |
| 10710 | }, |
| 10711 | { |
| 10712 | AArch64_SQDMLSLvvv_2d2s, ARM64_INS_SQDMLSL, |
| 10713 | #ifndef CAPSTONE_DIET |
| 10714 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10715 | #endif |
| 10716 | }, |
| 10717 | { |
| 10718 | AArch64_SQDMLSLvvv_4s4h, ARM64_INS_SQDMLSL, |
| 10719 | #ifndef CAPSTONE_DIET |
| 10720 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10721 | #endif |
| 10722 | }, |
| 10723 | { |
| 10724 | AArch64_SQDMULHhhh, ARM64_INS_SQDMULH, |
| 10725 | #ifndef CAPSTONE_DIET |
| 10726 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10727 | #endif |
| 10728 | }, |
| 10729 | { |
| 10730 | AArch64_SQDMULHhhv_4H, ARM64_INS_SQDMULH, |
| 10731 | #ifndef CAPSTONE_DIET |
| 10732 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10733 | #endif |
| 10734 | }, |
| 10735 | { |
| 10736 | AArch64_SQDMULHhhv_8H, ARM64_INS_SQDMULH, |
| 10737 | #ifndef CAPSTONE_DIET |
| 10738 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10739 | #endif |
| 10740 | }, |
| 10741 | { |
| 10742 | AArch64_SQDMULHsss, ARM64_INS_SQDMULH, |
| 10743 | #ifndef CAPSTONE_DIET |
| 10744 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10745 | #endif |
| 10746 | }, |
| 10747 | { |
| 10748 | AArch64_SQDMULHssv_2S, ARM64_INS_SQDMULH, |
| 10749 | #ifndef CAPSTONE_DIET |
| 10750 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10751 | #endif |
| 10752 | }, |
| 10753 | { |
| 10754 | AArch64_SQDMULHssv_4S, ARM64_INS_SQDMULH, |
| 10755 | #ifndef CAPSTONE_DIET |
| 10756 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10757 | #endif |
| 10758 | }, |
| 10759 | { |
| 10760 | AArch64_SQDMULHve_2s4s, ARM64_INS_SQDMULH, |
| 10761 | #ifndef CAPSTONE_DIET |
| 10762 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10763 | #endif |
| 10764 | }, |
| 10765 | { |
| 10766 | AArch64_SQDMULHve_4h8h, ARM64_INS_SQDMULH, |
| 10767 | #ifndef CAPSTONE_DIET |
| 10768 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10769 | #endif |
| 10770 | }, |
| 10771 | { |
| 10772 | AArch64_SQDMULHve_4s4s, ARM64_INS_SQDMULH, |
| 10773 | #ifndef CAPSTONE_DIET |
| 10774 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10775 | #endif |
| 10776 | }, |
| 10777 | { |
| 10778 | AArch64_SQDMULHve_8h8h, ARM64_INS_SQDMULH, |
| 10779 | #ifndef CAPSTONE_DIET |
| 10780 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10781 | #endif |
| 10782 | }, |
| 10783 | { |
| 10784 | AArch64_SQDMULHvvv_2S, ARM64_INS_SQDMULH, |
| 10785 | #ifndef CAPSTONE_DIET |
| 10786 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10787 | #endif |
| 10788 | }, |
| 10789 | { |
| 10790 | AArch64_SQDMULHvvv_4H, ARM64_INS_SQDMULH, |
| 10791 | #ifndef CAPSTONE_DIET |
| 10792 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10793 | #endif |
| 10794 | }, |
| 10795 | { |
| 10796 | AArch64_SQDMULHvvv_4S, ARM64_INS_SQDMULH, |
| 10797 | #ifndef CAPSTONE_DIET |
| 10798 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10799 | #endif |
| 10800 | }, |
| 10801 | { |
| 10802 | AArch64_SQDMULHvvv_8H, ARM64_INS_SQDMULH, |
| 10803 | #ifndef CAPSTONE_DIET |
| 10804 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10805 | #endif |
| 10806 | }, |
| 10807 | { |
| 10808 | AArch64_SQDMULL2vvv_2d4s, ARM64_INS_SQDMULL2, |
| 10809 | #ifndef CAPSTONE_DIET |
| 10810 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10811 | #endif |
| 10812 | }, |
| 10813 | { |
| 10814 | AArch64_SQDMULL2vvv_4s8h, ARM64_INS_SQDMULL2, |
| 10815 | #ifndef CAPSTONE_DIET |
| 10816 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10817 | #endif |
| 10818 | }, |
| 10819 | { |
| 10820 | AArch64_SQDMULLdss, ARM64_INS_SQDMULL, |
| 10821 | #ifndef CAPSTONE_DIET |
| 10822 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10823 | #endif |
| 10824 | }, |
| 10825 | { |
| 10826 | AArch64_SQDMULLdsv_2S, ARM64_INS_SQDMULL, |
| 10827 | #ifndef CAPSTONE_DIET |
| 10828 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10829 | #endif |
| 10830 | }, |
| 10831 | { |
| 10832 | AArch64_SQDMULLdsv_4S, ARM64_INS_SQDMULL, |
| 10833 | #ifndef CAPSTONE_DIET |
| 10834 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10835 | #endif |
| 10836 | }, |
| 10837 | { |
| 10838 | AArch64_SQDMULLshh, ARM64_INS_SQDMULL, |
| 10839 | #ifndef CAPSTONE_DIET |
| 10840 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10841 | #endif |
| 10842 | }, |
| 10843 | { |
| 10844 | AArch64_SQDMULLshv_4H, ARM64_INS_SQDMULL, |
| 10845 | #ifndef CAPSTONE_DIET |
| 10846 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10847 | #endif |
| 10848 | }, |
| 10849 | { |
| 10850 | AArch64_SQDMULLshv_8H, ARM64_INS_SQDMULL, |
| 10851 | #ifndef CAPSTONE_DIET |
| 10852 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10853 | #endif |
| 10854 | }, |
| 10855 | { |
| 10856 | AArch64_SQDMULLve_2d2s, ARM64_INS_SQDMULL, |
| 10857 | #ifndef CAPSTONE_DIET |
| 10858 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10859 | #endif |
| 10860 | }, |
| 10861 | { |
| 10862 | AArch64_SQDMULLve_2d4s, ARM64_INS_SQDMULL2, |
| 10863 | #ifndef CAPSTONE_DIET |
| 10864 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10865 | #endif |
| 10866 | }, |
| 10867 | { |
| 10868 | AArch64_SQDMULLve_4s4h, ARM64_INS_SQDMULL, |
| 10869 | #ifndef CAPSTONE_DIET |
| 10870 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10871 | #endif |
| 10872 | }, |
| 10873 | { |
| 10874 | AArch64_SQDMULLve_4s8h, ARM64_INS_SQDMULL2, |
| 10875 | #ifndef CAPSTONE_DIET |
| 10876 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10877 | #endif |
| 10878 | }, |
| 10879 | { |
| 10880 | AArch64_SQDMULLvvv_2d2s, ARM64_INS_SQDMULL, |
| 10881 | #ifndef CAPSTONE_DIET |
| 10882 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10883 | #endif |
| 10884 | }, |
| 10885 | { |
| 10886 | AArch64_SQDMULLvvv_4s4h, ARM64_INS_SQDMULL, |
| 10887 | #ifndef CAPSTONE_DIET |
| 10888 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10889 | #endif |
| 10890 | }, |
| 10891 | { |
| 10892 | AArch64_SQNEG16b, ARM64_INS_SQNEG, |
| 10893 | #ifndef CAPSTONE_DIET |
| 10894 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10895 | #endif |
| 10896 | }, |
| 10897 | { |
| 10898 | AArch64_SQNEG2d, ARM64_INS_SQNEG, |
| 10899 | #ifndef CAPSTONE_DIET |
| 10900 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10901 | #endif |
| 10902 | }, |
| 10903 | { |
| 10904 | AArch64_SQNEG2s, ARM64_INS_SQNEG, |
| 10905 | #ifndef CAPSTONE_DIET |
| 10906 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10907 | #endif |
| 10908 | }, |
| 10909 | { |
| 10910 | AArch64_SQNEG4h, ARM64_INS_SQNEG, |
| 10911 | #ifndef CAPSTONE_DIET |
| 10912 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10913 | #endif |
| 10914 | }, |
| 10915 | { |
| 10916 | AArch64_SQNEG4s, ARM64_INS_SQNEG, |
| 10917 | #ifndef CAPSTONE_DIET |
| 10918 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10919 | #endif |
| 10920 | }, |
| 10921 | { |
| 10922 | AArch64_SQNEG8b, ARM64_INS_SQNEG, |
| 10923 | #ifndef CAPSTONE_DIET |
| 10924 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10925 | #endif |
| 10926 | }, |
| 10927 | { |
| 10928 | AArch64_SQNEG8h, ARM64_INS_SQNEG, |
| 10929 | #ifndef CAPSTONE_DIET |
| 10930 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10931 | #endif |
| 10932 | }, |
| 10933 | { |
| 10934 | AArch64_SQNEGbb, ARM64_INS_SQNEG, |
| 10935 | #ifndef CAPSTONE_DIET |
| 10936 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10937 | #endif |
| 10938 | }, |
| 10939 | { |
| 10940 | AArch64_SQNEGdd, ARM64_INS_SQNEG, |
| 10941 | #ifndef CAPSTONE_DIET |
| 10942 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10943 | #endif |
| 10944 | }, |
| 10945 | { |
| 10946 | AArch64_SQNEGhh, ARM64_INS_SQNEG, |
| 10947 | #ifndef CAPSTONE_DIET |
| 10948 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10949 | #endif |
| 10950 | }, |
| 10951 | { |
| 10952 | AArch64_SQNEGss, ARM64_INS_SQNEG, |
| 10953 | #ifndef CAPSTONE_DIET |
| 10954 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10955 | #endif |
| 10956 | }, |
| 10957 | { |
| 10958 | AArch64_SQRDMULHhhh, ARM64_INS_SQRDMULH, |
| 10959 | #ifndef CAPSTONE_DIET |
| 10960 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10961 | #endif |
| 10962 | }, |
| 10963 | { |
| 10964 | AArch64_SQRDMULHhhv_4H, ARM64_INS_SQRDMULH, |
| 10965 | #ifndef CAPSTONE_DIET |
| 10966 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10967 | #endif |
| 10968 | }, |
| 10969 | { |
| 10970 | AArch64_SQRDMULHhhv_8H, ARM64_INS_SQRDMULH, |
| 10971 | #ifndef CAPSTONE_DIET |
| 10972 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10973 | #endif |
| 10974 | }, |
| 10975 | { |
| 10976 | AArch64_SQRDMULHsss, ARM64_INS_SQRDMULH, |
| 10977 | #ifndef CAPSTONE_DIET |
| 10978 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10979 | #endif |
| 10980 | }, |
| 10981 | { |
| 10982 | AArch64_SQRDMULHssv_2S, ARM64_INS_SQRDMULH, |
| 10983 | #ifndef CAPSTONE_DIET |
| 10984 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10985 | #endif |
| 10986 | }, |
| 10987 | { |
| 10988 | AArch64_SQRDMULHssv_4S, ARM64_INS_SQRDMULH, |
| 10989 | #ifndef CAPSTONE_DIET |
| 10990 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10991 | #endif |
| 10992 | }, |
| 10993 | { |
| 10994 | AArch64_SQRDMULHve_2s4s, ARM64_INS_SQRDMULH, |
| 10995 | #ifndef CAPSTONE_DIET |
| 10996 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 10997 | #endif |
| 10998 | }, |
| 10999 | { |
| 11000 | AArch64_SQRDMULHve_4h8h, ARM64_INS_SQRDMULH, |
| 11001 | #ifndef CAPSTONE_DIET |
| 11002 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11003 | #endif |
| 11004 | }, |
| 11005 | { |
| 11006 | AArch64_SQRDMULHve_4s4s, ARM64_INS_SQRDMULH, |
| 11007 | #ifndef CAPSTONE_DIET |
| 11008 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11009 | #endif |
| 11010 | }, |
| 11011 | { |
| 11012 | AArch64_SQRDMULHve_8h8h, ARM64_INS_SQRDMULH, |
| 11013 | #ifndef CAPSTONE_DIET |
| 11014 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11015 | #endif |
| 11016 | }, |
| 11017 | { |
| 11018 | AArch64_SQRDMULHvvv_2S, ARM64_INS_SQRDMULH, |
| 11019 | #ifndef CAPSTONE_DIET |
| 11020 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11021 | #endif |
| 11022 | }, |
| 11023 | { |
| 11024 | AArch64_SQRDMULHvvv_4H, ARM64_INS_SQRDMULH, |
| 11025 | #ifndef CAPSTONE_DIET |
| 11026 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11027 | #endif |
| 11028 | }, |
| 11029 | { |
| 11030 | AArch64_SQRDMULHvvv_4S, ARM64_INS_SQRDMULH, |
| 11031 | #ifndef CAPSTONE_DIET |
| 11032 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11033 | #endif |
| 11034 | }, |
| 11035 | { |
| 11036 | AArch64_SQRDMULHvvv_8H, ARM64_INS_SQRDMULH, |
| 11037 | #ifndef CAPSTONE_DIET |
| 11038 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11039 | #endif |
| 11040 | }, |
| 11041 | { |
| 11042 | AArch64_SQRSHLbbb, ARM64_INS_SQRSHL, |
| 11043 | #ifndef CAPSTONE_DIET |
| 11044 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11045 | #endif |
| 11046 | }, |
| 11047 | { |
| 11048 | AArch64_SQRSHLddd, ARM64_INS_SQRSHL, |
| 11049 | #ifndef CAPSTONE_DIET |
| 11050 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11051 | #endif |
| 11052 | }, |
| 11053 | { |
| 11054 | AArch64_SQRSHLhhh, ARM64_INS_SQRSHL, |
| 11055 | #ifndef CAPSTONE_DIET |
| 11056 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11057 | #endif |
| 11058 | }, |
| 11059 | { |
| 11060 | AArch64_SQRSHLsss, ARM64_INS_SQRSHL, |
| 11061 | #ifndef CAPSTONE_DIET |
| 11062 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11063 | #endif |
| 11064 | }, |
| 11065 | { |
| 11066 | AArch64_SQRSHLvvv_16B, ARM64_INS_SQRSHL, |
| 11067 | #ifndef CAPSTONE_DIET |
| 11068 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11069 | #endif |
| 11070 | }, |
| 11071 | { |
| 11072 | AArch64_SQRSHLvvv_2D, ARM64_INS_SQRSHL, |
| 11073 | #ifndef CAPSTONE_DIET |
| 11074 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11075 | #endif |
| 11076 | }, |
| 11077 | { |
| 11078 | AArch64_SQRSHLvvv_2S, ARM64_INS_SQRSHL, |
| 11079 | #ifndef CAPSTONE_DIET |
| 11080 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11081 | #endif |
| 11082 | }, |
| 11083 | { |
| 11084 | AArch64_SQRSHLvvv_4H, ARM64_INS_SQRSHL, |
| 11085 | #ifndef CAPSTONE_DIET |
| 11086 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11087 | #endif |
| 11088 | }, |
| 11089 | { |
| 11090 | AArch64_SQRSHLvvv_4S, ARM64_INS_SQRSHL, |
| 11091 | #ifndef CAPSTONE_DIET |
| 11092 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11093 | #endif |
| 11094 | }, |
| 11095 | { |
| 11096 | AArch64_SQRSHLvvv_8B, ARM64_INS_SQRSHL, |
| 11097 | #ifndef CAPSTONE_DIET |
| 11098 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11099 | #endif |
| 11100 | }, |
| 11101 | { |
| 11102 | AArch64_SQRSHLvvv_8H, ARM64_INS_SQRSHL, |
| 11103 | #ifndef CAPSTONE_DIET |
| 11104 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11105 | #endif |
| 11106 | }, |
| 11107 | { |
| 11108 | AArch64_SQRSHRNbhi, ARM64_INS_SQRSHRN, |
| 11109 | #ifndef CAPSTONE_DIET |
| 11110 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11111 | #endif |
| 11112 | }, |
| 11113 | { |
| 11114 | AArch64_SQRSHRNhsi, ARM64_INS_SQRSHRN, |
| 11115 | #ifndef CAPSTONE_DIET |
| 11116 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11117 | #endif |
| 11118 | }, |
| 11119 | { |
| 11120 | AArch64_SQRSHRNsdi, ARM64_INS_SQRSHRN, |
| 11121 | #ifndef CAPSTONE_DIET |
| 11122 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11123 | #endif |
| 11124 | }, |
| 11125 | { |
| 11126 | AArch64_SQRSHRNvvi_16B, ARM64_INS_SQRSHRN2, |
| 11127 | #ifndef CAPSTONE_DIET |
| 11128 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11129 | #endif |
| 11130 | }, |
| 11131 | { |
| 11132 | AArch64_SQRSHRNvvi_2S, ARM64_INS_SQRSHRN, |
| 11133 | #ifndef CAPSTONE_DIET |
| 11134 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11135 | #endif |
| 11136 | }, |
| 11137 | { |
| 11138 | AArch64_SQRSHRNvvi_4H, ARM64_INS_SQRSHRN, |
| 11139 | #ifndef CAPSTONE_DIET |
| 11140 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11141 | #endif |
| 11142 | }, |
| 11143 | { |
| 11144 | AArch64_SQRSHRNvvi_4S, ARM64_INS_SQRSHRN2, |
| 11145 | #ifndef CAPSTONE_DIET |
| 11146 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11147 | #endif |
| 11148 | }, |
| 11149 | { |
| 11150 | AArch64_SQRSHRNvvi_8B, ARM64_INS_SQRSHRN, |
| 11151 | #ifndef CAPSTONE_DIET |
| 11152 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11153 | #endif |
| 11154 | }, |
| 11155 | { |
| 11156 | AArch64_SQRSHRNvvi_8H, ARM64_INS_SQRSHRN2, |
| 11157 | #ifndef CAPSTONE_DIET |
| 11158 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11159 | #endif |
| 11160 | }, |
| 11161 | { |
| 11162 | AArch64_SQRSHRUNbhi, ARM64_INS_SQRSHRUN, |
| 11163 | #ifndef CAPSTONE_DIET |
| 11164 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11165 | #endif |
| 11166 | }, |
| 11167 | { |
| 11168 | AArch64_SQRSHRUNhsi, ARM64_INS_SQRSHRUN, |
| 11169 | #ifndef CAPSTONE_DIET |
| 11170 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11171 | #endif |
| 11172 | }, |
| 11173 | { |
| 11174 | AArch64_SQRSHRUNsdi, ARM64_INS_SQRSHRUN, |
| 11175 | #ifndef CAPSTONE_DIET |
| 11176 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11177 | #endif |
| 11178 | }, |
| 11179 | { |
| 11180 | AArch64_SQSHLUbbi, ARM64_INS_SQSHLU, |
| 11181 | #ifndef CAPSTONE_DIET |
| 11182 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11183 | #endif |
| 11184 | }, |
| 11185 | { |
| 11186 | AArch64_SQSHLUddi, ARM64_INS_SQSHLU, |
| 11187 | #ifndef CAPSTONE_DIET |
| 11188 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11189 | #endif |
| 11190 | }, |
| 11191 | { |
| 11192 | AArch64_SQSHLUhhi, ARM64_INS_SQSHLU, |
| 11193 | #ifndef CAPSTONE_DIET |
| 11194 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11195 | #endif |
| 11196 | }, |
| 11197 | { |
| 11198 | AArch64_SQSHLUssi, ARM64_INS_SQSHLU, |
| 11199 | #ifndef CAPSTONE_DIET |
| 11200 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11201 | #endif |
| 11202 | }, |
| 11203 | { |
| 11204 | AArch64_SQSHLUvvi_16B, ARM64_INS_SQSHLU, |
| 11205 | #ifndef CAPSTONE_DIET |
| 11206 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11207 | #endif |
| 11208 | }, |
| 11209 | { |
| 11210 | AArch64_SQSHLUvvi_2D, ARM64_INS_SQSHLU, |
| 11211 | #ifndef CAPSTONE_DIET |
| 11212 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11213 | #endif |
| 11214 | }, |
| 11215 | { |
| 11216 | AArch64_SQSHLUvvi_2S, ARM64_INS_SQSHLU, |
| 11217 | #ifndef CAPSTONE_DIET |
| 11218 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11219 | #endif |
| 11220 | }, |
| 11221 | { |
| 11222 | AArch64_SQSHLUvvi_4H, ARM64_INS_SQSHLU, |
| 11223 | #ifndef CAPSTONE_DIET |
| 11224 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11225 | #endif |
| 11226 | }, |
| 11227 | { |
| 11228 | AArch64_SQSHLUvvi_4S, ARM64_INS_SQSHLU, |
| 11229 | #ifndef CAPSTONE_DIET |
| 11230 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11231 | #endif |
| 11232 | }, |
| 11233 | { |
| 11234 | AArch64_SQSHLUvvi_8B, ARM64_INS_SQSHLU, |
| 11235 | #ifndef CAPSTONE_DIET |
| 11236 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11237 | #endif |
| 11238 | }, |
| 11239 | { |
| 11240 | AArch64_SQSHLUvvi_8H, ARM64_INS_SQSHLU, |
| 11241 | #ifndef CAPSTONE_DIET |
| 11242 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11243 | #endif |
| 11244 | }, |
| 11245 | { |
| 11246 | AArch64_SQSHLbbb, ARM64_INS_SQSHL, |
| 11247 | #ifndef CAPSTONE_DIET |
| 11248 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11249 | #endif |
| 11250 | }, |
| 11251 | { |
| 11252 | AArch64_SQSHLbbi, ARM64_INS_SQSHL, |
| 11253 | #ifndef CAPSTONE_DIET |
| 11254 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11255 | #endif |
| 11256 | }, |
| 11257 | { |
| 11258 | AArch64_SQSHLddd, ARM64_INS_SQSHL, |
| 11259 | #ifndef CAPSTONE_DIET |
| 11260 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11261 | #endif |
| 11262 | }, |
| 11263 | { |
| 11264 | AArch64_SQSHLddi, ARM64_INS_SQSHL, |
| 11265 | #ifndef CAPSTONE_DIET |
| 11266 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11267 | #endif |
| 11268 | }, |
| 11269 | { |
| 11270 | AArch64_SQSHLhhh, ARM64_INS_SQSHL, |
| 11271 | #ifndef CAPSTONE_DIET |
| 11272 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11273 | #endif |
| 11274 | }, |
| 11275 | { |
| 11276 | AArch64_SQSHLhhi, ARM64_INS_SQSHL, |
| 11277 | #ifndef CAPSTONE_DIET |
| 11278 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11279 | #endif |
| 11280 | }, |
| 11281 | { |
| 11282 | AArch64_SQSHLssi, ARM64_INS_SQSHL, |
| 11283 | #ifndef CAPSTONE_DIET |
| 11284 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11285 | #endif |
| 11286 | }, |
| 11287 | { |
| 11288 | AArch64_SQSHLsss, ARM64_INS_SQSHL, |
| 11289 | #ifndef CAPSTONE_DIET |
| 11290 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11291 | #endif |
| 11292 | }, |
| 11293 | { |
| 11294 | AArch64_SQSHLvvi_16B, ARM64_INS_SQSHL, |
| 11295 | #ifndef CAPSTONE_DIET |
| 11296 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11297 | #endif |
| 11298 | }, |
| 11299 | { |
| 11300 | AArch64_SQSHLvvi_2D, ARM64_INS_SQSHL, |
| 11301 | #ifndef CAPSTONE_DIET |
| 11302 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11303 | #endif |
| 11304 | }, |
| 11305 | { |
| 11306 | AArch64_SQSHLvvi_2S, ARM64_INS_SQSHL, |
| 11307 | #ifndef CAPSTONE_DIET |
| 11308 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11309 | #endif |
| 11310 | }, |
| 11311 | { |
| 11312 | AArch64_SQSHLvvi_4H, ARM64_INS_SQSHL, |
| 11313 | #ifndef CAPSTONE_DIET |
| 11314 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11315 | #endif |
| 11316 | }, |
| 11317 | { |
| 11318 | AArch64_SQSHLvvi_4S, ARM64_INS_SQSHL, |
| 11319 | #ifndef CAPSTONE_DIET |
| 11320 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11321 | #endif |
| 11322 | }, |
| 11323 | { |
| 11324 | AArch64_SQSHLvvi_8B, ARM64_INS_SQSHL, |
| 11325 | #ifndef CAPSTONE_DIET |
| 11326 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11327 | #endif |
| 11328 | }, |
| 11329 | { |
| 11330 | AArch64_SQSHLvvi_8H, ARM64_INS_SQSHL, |
| 11331 | #ifndef CAPSTONE_DIET |
| 11332 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11333 | #endif |
| 11334 | }, |
| 11335 | { |
| 11336 | AArch64_SQSHLvvv_16B, ARM64_INS_SQSHL, |
| 11337 | #ifndef CAPSTONE_DIET |
| 11338 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11339 | #endif |
| 11340 | }, |
| 11341 | { |
| 11342 | AArch64_SQSHLvvv_2D, ARM64_INS_SQSHL, |
| 11343 | #ifndef CAPSTONE_DIET |
| 11344 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11345 | #endif |
| 11346 | }, |
| 11347 | { |
| 11348 | AArch64_SQSHLvvv_2S, ARM64_INS_SQSHL, |
| 11349 | #ifndef CAPSTONE_DIET |
| 11350 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11351 | #endif |
| 11352 | }, |
| 11353 | { |
| 11354 | AArch64_SQSHLvvv_4H, ARM64_INS_SQSHL, |
| 11355 | #ifndef CAPSTONE_DIET |
| 11356 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11357 | #endif |
| 11358 | }, |
| 11359 | { |
| 11360 | AArch64_SQSHLvvv_4S, ARM64_INS_SQSHL, |
| 11361 | #ifndef CAPSTONE_DIET |
| 11362 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11363 | #endif |
| 11364 | }, |
| 11365 | { |
| 11366 | AArch64_SQSHLvvv_8B, ARM64_INS_SQSHL, |
| 11367 | #ifndef CAPSTONE_DIET |
| 11368 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11369 | #endif |
| 11370 | }, |
| 11371 | { |
| 11372 | AArch64_SQSHLvvv_8H, ARM64_INS_SQSHL, |
| 11373 | #ifndef CAPSTONE_DIET |
| 11374 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11375 | #endif |
| 11376 | }, |
| 11377 | { |
| 11378 | AArch64_SQSHRNbhi, ARM64_INS_SQSHRN, |
| 11379 | #ifndef CAPSTONE_DIET |
| 11380 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11381 | #endif |
| 11382 | }, |
| 11383 | { |
| 11384 | AArch64_SQSHRNhsi, ARM64_INS_SQSHRN, |
| 11385 | #ifndef CAPSTONE_DIET |
| 11386 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11387 | #endif |
| 11388 | }, |
| 11389 | { |
| 11390 | AArch64_SQSHRNsdi, ARM64_INS_SQSHRN, |
| 11391 | #ifndef CAPSTONE_DIET |
| 11392 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11393 | #endif |
| 11394 | }, |
| 11395 | { |
| 11396 | AArch64_SQSHRNvvi_16B, ARM64_INS_SQSHRN2, |
| 11397 | #ifndef CAPSTONE_DIET |
| 11398 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11399 | #endif |
| 11400 | }, |
| 11401 | { |
| 11402 | AArch64_SQSHRNvvi_2S, ARM64_INS_SQSHRN, |
| 11403 | #ifndef CAPSTONE_DIET |
| 11404 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11405 | #endif |
| 11406 | }, |
| 11407 | { |
| 11408 | AArch64_SQSHRNvvi_4H, ARM64_INS_SQSHRN, |
| 11409 | #ifndef CAPSTONE_DIET |
| 11410 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11411 | #endif |
| 11412 | }, |
| 11413 | { |
| 11414 | AArch64_SQSHRNvvi_4S, ARM64_INS_SQSHRN2, |
| 11415 | #ifndef CAPSTONE_DIET |
| 11416 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11417 | #endif |
| 11418 | }, |
| 11419 | { |
| 11420 | AArch64_SQSHRNvvi_8B, ARM64_INS_SQSHRN, |
| 11421 | #ifndef CAPSTONE_DIET |
| 11422 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11423 | #endif |
| 11424 | }, |
| 11425 | { |
| 11426 | AArch64_SQSHRNvvi_8H, ARM64_INS_SQSHRN2, |
| 11427 | #ifndef CAPSTONE_DIET |
| 11428 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11429 | #endif |
| 11430 | }, |
| 11431 | { |
| 11432 | AArch64_SQSHRUNbhi, ARM64_INS_SQSHRUN, |
| 11433 | #ifndef CAPSTONE_DIET |
| 11434 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11435 | #endif |
| 11436 | }, |
| 11437 | { |
| 11438 | AArch64_SQSHRUNhsi, ARM64_INS_SQSHRUN, |
| 11439 | #ifndef CAPSTONE_DIET |
| 11440 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11441 | #endif |
| 11442 | }, |
| 11443 | { |
| 11444 | AArch64_SQSHRUNsdi, ARM64_INS_SQSHRUN, |
| 11445 | #ifndef CAPSTONE_DIET |
| 11446 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11447 | #endif |
| 11448 | }, |
| 11449 | { |
| 11450 | AArch64_SQSUBbbb, ARM64_INS_SQSUB, |
| 11451 | #ifndef CAPSTONE_DIET |
| 11452 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11453 | #endif |
| 11454 | }, |
| 11455 | { |
| 11456 | AArch64_SQSUBddd, ARM64_INS_SQSUB, |
| 11457 | #ifndef CAPSTONE_DIET |
| 11458 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11459 | #endif |
| 11460 | }, |
| 11461 | { |
| 11462 | AArch64_SQSUBhhh, ARM64_INS_SQSUB, |
| 11463 | #ifndef CAPSTONE_DIET |
| 11464 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11465 | #endif |
| 11466 | }, |
| 11467 | { |
| 11468 | AArch64_SQSUBsss, ARM64_INS_SQSUB, |
| 11469 | #ifndef CAPSTONE_DIET |
| 11470 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11471 | #endif |
| 11472 | }, |
| 11473 | { |
| 11474 | AArch64_SQSUBvvv_16B, ARM64_INS_SQSUB, |
| 11475 | #ifndef CAPSTONE_DIET |
| 11476 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11477 | #endif |
| 11478 | }, |
| 11479 | { |
| 11480 | AArch64_SQSUBvvv_2D, ARM64_INS_SQSUB, |
| 11481 | #ifndef CAPSTONE_DIET |
| 11482 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11483 | #endif |
| 11484 | }, |
| 11485 | { |
| 11486 | AArch64_SQSUBvvv_2S, ARM64_INS_SQSUB, |
| 11487 | #ifndef CAPSTONE_DIET |
| 11488 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11489 | #endif |
| 11490 | }, |
| 11491 | { |
| 11492 | AArch64_SQSUBvvv_4H, ARM64_INS_SQSUB, |
| 11493 | #ifndef CAPSTONE_DIET |
| 11494 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11495 | #endif |
| 11496 | }, |
| 11497 | { |
| 11498 | AArch64_SQSUBvvv_4S, ARM64_INS_SQSUB, |
| 11499 | #ifndef CAPSTONE_DIET |
| 11500 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11501 | #endif |
| 11502 | }, |
| 11503 | { |
| 11504 | AArch64_SQSUBvvv_8B, ARM64_INS_SQSUB, |
| 11505 | #ifndef CAPSTONE_DIET |
| 11506 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11507 | #endif |
| 11508 | }, |
| 11509 | { |
| 11510 | AArch64_SQSUBvvv_8H, ARM64_INS_SQSUB, |
| 11511 | #ifndef CAPSTONE_DIET |
| 11512 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11513 | #endif |
| 11514 | }, |
| 11515 | { |
| 11516 | AArch64_SQXTN2d2s, ARM64_INS_SQXTN, |
| 11517 | #ifndef CAPSTONE_DIET |
| 11518 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11519 | #endif |
| 11520 | }, |
| 11521 | { |
| 11522 | AArch64_SQXTN2d4s, ARM64_INS_SQXTN2, |
| 11523 | #ifndef CAPSTONE_DIET |
| 11524 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11525 | #endif |
| 11526 | }, |
| 11527 | { |
| 11528 | AArch64_SQXTN4s4h, ARM64_INS_SQXTN, |
| 11529 | #ifndef CAPSTONE_DIET |
| 11530 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11531 | #endif |
| 11532 | }, |
| 11533 | { |
| 11534 | AArch64_SQXTN4s8h, ARM64_INS_SQXTN2, |
| 11535 | #ifndef CAPSTONE_DIET |
| 11536 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11537 | #endif |
| 11538 | }, |
| 11539 | { |
| 11540 | AArch64_SQXTN8h16b, ARM64_INS_SQXTN2, |
| 11541 | #ifndef CAPSTONE_DIET |
| 11542 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11543 | #endif |
| 11544 | }, |
| 11545 | { |
| 11546 | AArch64_SQXTN8h8b, ARM64_INS_SQXTN, |
| 11547 | #ifndef CAPSTONE_DIET |
| 11548 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11549 | #endif |
| 11550 | }, |
| 11551 | { |
| 11552 | AArch64_SQXTNbh, ARM64_INS_SQXTN, |
| 11553 | #ifndef CAPSTONE_DIET |
| 11554 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11555 | #endif |
| 11556 | }, |
| 11557 | { |
| 11558 | AArch64_SQXTNhs, ARM64_INS_SQXTN, |
| 11559 | #ifndef CAPSTONE_DIET |
| 11560 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11561 | #endif |
| 11562 | }, |
| 11563 | { |
| 11564 | AArch64_SQXTNsd, ARM64_INS_SQXTN, |
| 11565 | #ifndef CAPSTONE_DIET |
| 11566 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11567 | #endif |
| 11568 | }, |
| 11569 | { |
| 11570 | AArch64_SQXTUN2d2s, ARM64_INS_SQXTUN, |
| 11571 | #ifndef CAPSTONE_DIET |
| 11572 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11573 | #endif |
| 11574 | }, |
| 11575 | { |
| 11576 | AArch64_SQXTUN2d4s, ARM64_INS_SQXTUN2, |
| 11577 | #ifndef CAPSTONE_DIET |
| 11578 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11579 | #endif |
| 11580 | }, |
| 11581 | { |
| 11582 | AArch64_SQXTUN4s4h, ARM64_INS_SQXTUN, |
| 11583 | #ifndef CAPSTONE_DIET |
| 11584 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11585 | #endif |
| 11586 | }, |
| 11587 | { |
| 11588 | AArch64_SQXTUN4s8h, ARM64_INS_SQXTUN2, |
| 11589 | #ifndef CAPSTONE_DIET |
| 11590 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11591 | #endif |
| 11592 | }, |
| 11593 | { |
| 11594 | AArch64_SQXTUN8h16b, ARM64_INS_SQXTUN2, |
| 11595 | #ifndef CAPSTONE_DIET |
| 11596 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11597 | #endif |
| 11598 | }, |
| 11599 | { |
| 11600 | AArch64_SQXTUN8h8b, ARM64_INS_SQXTUN, |
| 11601 | #ifndef CAPSTONE_DIET |
| 11602 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11603 | #endif |
| 11604 | }, |
| 11605 | { |
| 11606 | AArch64_SQXTUNbh, ARM64_INS_SQXTUN, |
| 11607 | #ifndef CAPSTONE_DIET |
| 11608 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11609 | #endif |
| 11610 | }, |
| 11611 | { |
| 11612 | AArch64_SQXTUNhs, ARM64_INS_SQXTUN, |
| 11613 | #ifndef CAPSTONE_DIET |
| 11614 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11615 | #endif |
| 11616 | }, |
| 11617 | { |
| 11618 | AArch64_SQXTUNsd, ARM64_INS_SQXTUN, |
| 11619 | #ifndef CAPSTONE_DIET |
| 11620 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11621 | #endif |
| 11622 | }, |
| 11623 | { |
| 11624 | AArch64_SRHADDvvv_16B, ARM64_INS_SRHADD, |
| 11625 | #ifndef CAPSTONE_DIET |
| 11626 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11627 | #endif |
| 11628 | }, |
| 11629 | { |
| 11630 | AArch64_SRHADDvvv_2S, ARM64_INS_SRHADD, |
| 11631 | #ifndef CAPSTONE_DIET |
| 11632 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11633 | #endif |
| 11634 | }, |
| 11635 | { |
| 11636 | AArch64_SRHADDvvv_4H, ARM64_INS_SRHADD, |
| 11637 | #ifndef CAPSTONE_DIET |
| 11638 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11639 | #endif |
| 11640 | }, |
| 11641 | { |
| 11642 | AArch64_SRHADDvvv_4S, ARM64_INS_SRHADD, |
| 11643 | #ifndef CAPSTONE_DIET |
| 11644 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11645 | #endif |
| 11646 | }, |
| 11647 | { |
| 11648 | AArch64_SRHADDvvv_8B, ARM64_INS_SRHADD, |
| 11649 | #ifndef CAPSTONE_DIET |
| 11650 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11651 | #endif |
| 11652 | }, |
| 11653 | { |
| 11654 | AArch64_SRHADDvvv_8H, ARM64_INS_SRHADD, |
| 11655 | #ifndef CAPSTONE_DIET |
| 11656 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11657 | #endif |
| 11658 | }, |
| 11659 | { |
| 11660 | AArch64_SRI, ARM64_INS_SRI, |
| 11661 | #ifndef CAPSTONE_DIET |
| 11662 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11663 | #endif |
| 11664 | }, |
| 11665 | { |
| 11666 | AArch64_SRIvvi_16B, ARM64_INS_SRI, |
| 11667 | #ifndef CAPSTONE_DIET |
| 11668 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11669 | #endif |
| 11670 | }, |
| 11671 | { |
| 11672 | AArch64_SRIvvi_2D, ARM64_INS_SRI, |
| 11673 | #ifndef CAPSTONE_DIET |
| 11674 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11675 | #endif |
| 11676 | }, |
| 11677 | { |
| 11678 | AArch64_SRIvvi_2S, ARM64_INS_SRI, |
| 11679 | #ifndef CAPSTONE_DIET |
| 11680 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11681 | #endif |
| 11682 | }, |
| 11683 | { |
| 11684 | AArch64_SRIvvi_4H, ARM64_INS_SRI, |
| 11685 | #ifndef CAPSTONE_DIET |
| 11686 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11687 | #endif |
| 11688 | }, |
| 11689 | { |
| 11690 | AArch64_SRIvvi_4S, ARM64_INS_SRI, |
| 11691 | #ifndef CAPSTONE_DIET |
| 11692 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11693 | #endif |
| 11694 | }, |
| 11695 | { |
| 11696 | AArch64_SRIvvi_8B, ARM64_INS_SRI, |
| 11697 | #ifndef CAPSTONE_DIET |
| 11698 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11699 | #endif |
| 11700 | }, |
| 11701 | { |
| 11702 | AArch64_SRIvvi_8H, ARM64_INS_SRI, |
| 11703 | #ifndef CAPSTONE_DIET |
| 11704 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11705 | #endif |
| 11706 | }, |
| 11707 | { |
| 11708 | AArch64_SRSHLddd, ARM64_INS_SRSHL, |
| 11709 | #ifndef CAPSTONE_DIET |
| 11710 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11711 | #endif |
| 11712 | }, |
| 11713 | { |
| 11714 | AArch64_SRSHLvvv_16B, ARM64_INS_SRSHL, |
| 11715 | #ifndef CAPSTONE_DIET |
| 11716 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11717 | #endif |
| 11718 | }, |
| 11719 | { |
| 11720 | AArch64_SRSHLvvv_2D, ARM64_INS_SRSHL, |
| 11721 | #ifndef CAPSTONE_DIET |
| 11722 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11723 | #endif |
| 11724 | }, |
| 11725 | { |
| 11726 | AArch64_SRSHLvvv_2S, ARM64_INS_SRSHL, |
| 11727 | #ifndef CAPSTONE_DIET |
| 11728 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11729 | #endif |
| 11730 | }, |
| 11731 | { |
| 11732 | AArch64_SRSHLvvv_4H, ARM64_INS_SRSHL, |
| 11733 | #ifndef CAPSTONE_DIET |
| 11734 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11735 | #endif |
| 11736 | }, |
| 11737 | { |
| 11738 | AArch64_SRSHLvvv_4S, ARM64_INS_SRSHL, |
| 11739 | #ifndef CAPSTONE_DIET |
| 11740 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11741 | #endif |
| 11742 | }, |
| 11743 | { |
| 11744 | AArch64_SRSHLvvv_8B, ARM64_INS_SRSHL, |
| 11745 | #ifndef CAPSTONE_DIET |
| 11746 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11747 | #endif |
| 11748 | }, |
| 11749 | { |
| 11750 | AArch64_SRSHLvvv_8H, ARM64_INS_SRSHL, |
| 11751 | #ifndef CAPSTONE_DIET |
| 11752 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11753 | #endif |
| 11754 | }, |
| 11755 | { |
| 11756 | AArch64_SRSHRddi, ARM64_INS_SRSHR, |
| 11757 | #ifndef CAPSTONE_DIET |
| 11758 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11759 | #endif |
| 11760 | }, |
| 11761 | { |
| 11762 | AArch64_SRSHRvvi_16B, ARM64_INS_SRSHR, |
| 11763 | #ifndef CAPSTONE_DIET |
| 11764 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11765 | #endif |
| 11766 | }, |
| 11767 | { |
| 11768 | AArch64_SRSHRvvi_2D, ARM64_INS_SRSHR, |
| 11769 | #ifndef CAPSTONE_DIET |
| 11770 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11771 | #endif |
| 11772 | }, |
| 11773 | { |
| 11774 | AArch64_SRSHRvvi_2S, ARM64_INS_SRSHR, |
| 11775 | #ifndef CAPSTONE_DIET |
| 11776 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11777 | #endif |
| 11778 | }, |
| 11779 | { |
| 11780 | AArch64_SRSHRvvi_4H, ARM64_INS_SRSHR, |
| 11781 | #ifndef CAPSTONE_DIET |
| 11782 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11783 | #endif |
| 11784 | }, |
| 11785 | { |
| 11786 | AArch64_SRSHRvvi_4S, ARM64_INS_SRSHR, |
| 11787 | #ifndef CAPSTONE_DIET |
| 11788 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11789 | #endif |
| 11790 | }, |
| 11791 | { |
| 11792 | AArch64_SRSHRvvi_8B, ARM64_INS_SRSHR, |
| 11793 | #ifndef CAPSTONE_DIET |
| 11794 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11795 | #endif |
| 11796 | }, |
| 11797 | { |
| 11798 | AArch64_SRSHRvvi_8H, ARM64_INS_SRSHR, |
| 11799 | #ifndef CAPSTONE_DIET |
| 11800 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11801 | #endif |
| 11802 | }, |
| 11803 | { |
| 11804 | AArch64_SRSRA, ARM64_INS_SRSRA, |
| 11805 | #ifndef CAPSTONE_DIET |
| 11806 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11807 | #endif |
| 11808 | }, |
| 11809 | { |
| 11810 | AArch64_SRSRAvvi_16B, ARM64_INS_SRSRA, |
| 11811 | #ifndef CAPSTONE_DIET |
| 11812 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11813 | #endif |
| 11814 | }, |
| 11815 | { |
| 11816 | AArch64_SRSRAvvi_2D, ARM64_INS_SRSRA, |
| 11817 | #ifndef CAPSTONE_DIET |
| 11818 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11819 | #endif |
| 11820 | }, |
| 11821 | { |
| 11822 | AArch64_SRSRAvvi_2S, ARM64_INS_SRSRA, |
| 11823 | #ifndef CAPSTONE_DIET |
| 11824 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11825 | #endif |
| 11826 | }, |
| 11827 | { |
| 11828 | AArch64_SRSRAvvi_4H, ARM64_INS_SRSRA, |
| 11829 | #ifndef CAPSTONE_DIET |
| 11830 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11831 | #endif |
| 11832 | }, |
| 11833 | { |
| 11834 | AArch64_SRSRAvvi_4S, ARM64_INS_SRSRA, |
| 11835 | #ifndef CAPSTONE_DIET |
| 11836 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11837 | #endif |
| 11838 | }, |
| 11839 | { |
| 11840 | AArch64_SRSRAvvi_8B, ARM64_INS_SRSRA, |
| 11841 | #ifndef CAPSTONE_DIET |
| 11842 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11843 | #endif |
| 11844 | }, |
| 11845 | { |
| 11846 | AArch64_SRSRAvvi_8H, ARM64_INS_SRSRA, |
| 11847 | #ifndef CAPSTONE_DIET |
| 11848 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11849 | #endif |
| 11850 | }, |
| 11851 | { |
| 11852 | AArch64_SSHLLvvi_16B, ARM64_INS_SSHLL2, |
| 11853 | #ifndef CAPSTONE_DIET |
| 11854 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11855 | #endif |
| 11856 | }, |
| 11857 | { |
| 11858 | AArch64_SSHLLvvi_2S, ARM64_INS_SSHLL, |
| 11859 | #ifndef CAPSTONE_DIET |
| 11860 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11861 | #endif |
| 11862 | }, |
| 11863 | { |
| 11864 | AArch64_SSHLLvvi_4H, ARM64_INS_SSHLL, |
| 11865 | #ifndef CAPSTONE_DIET |
| 11866 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11867 | #endif |
| 11868 | }, |
| 11869 | { |
| 11870 | AArch64_SSHLLvvi_4S, ARM64_INS_SSHLL2, |
| 11871 | #ifndef CAPSTONE_DIET |
| 11872 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11873 | #endif |
| 11874 | }, |
| 11875 | { |
| 11876 | AArch64_SSHLLvvi_8B, ARM64_INS_SSHLL, |
| 11877 | #ifndef CAPSTONE_DIET |
| 11878 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11879 | #endif |
| 11880 | }, |
| 11881 | { |
| 11882 | AArch64_SSHLLvvi_8H, ARM64_INS_SSHLL2, |
| 11883 | #ifndef CAPSTONE_DIET |
| 11884 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11885 | #endif |
| 11886 | }, |
| 11887 | { |
| 11888 | AArch64_SSHLddd, ARM64_INS_SSHL, |
| 11889 | #ifndef CAPSTONE_DIET |
| 11890 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11891 | #endif |
| 11892 | }, |
| 11893 | { |
| 11894 | AArch64_SSHLvvv_16B, ARM64_INS_SSHL, |
| 11895 | #ifndef CAPSTONE_DIET |
| 11896 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11897 | #endif |
| 11898 | }, |
| 11899 | { |
| 11900 | AArch64_SSHLvvv_2D, ARM64_INS_SSHL, |
| 11901 | #ifndef CAPSTONE_DIET |
| 11902 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11903 | #endif |
| 11904 | }, |
| 11905 | { |
| 11906 | AArch64_SSHLvvv_2S, ARM64_INS_SSHL, |
| 11907 | #ifndef CAPSTONE_DIET |
| 11908 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11909 | #endif |
| 11910 | }, |
| 11911 | { |
| 11912 | AArch64_SSHLvvv_4H, ARM64_INS_SSHL, |
| 11913 | #ifndef CAPSTONE_DIET |
| 11914 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11915 | #endif |
| 11916 | }, |
| 11917 | { |
| 11918 | AArch64_SSHLvvv_4S, ARM64_INS_SSHL, |
| 11919 | #ifndef CAPSTONE_DIET |
| 11920 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11921 | #endif |
| 11922 | }, |
| 11923 | { |
| 11924 | AArch64_SSHLvvv_8B, ARM64_INS_SSHL, |
| 11925 | #ifndef CAPSTONE_DIET |
| 11926 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11927 | #endif |
| 11928 | }, |
| 11929 | { |
| 11930 | AArch64_SSHLvvv_8H, ARM64_INS_SSHL, |
| 11931 | #ifndef CAPSTONE_DIET |
| 11932 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11933 | #endif |
| 11934 | }, |
| 11935 | { |
| 11936 | AArch64_SSHRddi, ARM64_INS_SSHR, |
| 11937 | #ifndef CAPSTONE_DIET |
| 11938 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11939 | #endif |
| 11940 | }, |
| 11941 | { |
| 11942 | AArch64_SSHRvvi_16B, ARM64_INS_SSHR, |
| 11943 | #ifndef CAPSTONE_DIET |
| 11944 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11945 | #endif |
| 11946 | }, |
| 11947 | { |
| 11948 | AArch64_SSHRvvi_2D, ARM64_INS_SSHR, |
| 11949 | #ifndef CAPSTONE_DIET |
| 11950 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11951 | #endif |
| 11952 | }, |
| 11953 | { |
| 11954 | AArch64_SSHRvvi_2S, ARM64_INS_SSHR, |
| 11955 | #ifndef CAPSTONE_DIET |
| 11956 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11957 | #endif |
| 11958 | }, |
| 11959 | { |
| 11960 | AArch64_SSHRvvi_4H, ARM64_INS_SSHR, |
| 11961 | #ifndef CAPSTONE_DIET |
| 11962 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11963 | #endif |
| 11964 | }, |
| 11965 | { |
| 11966 | AArch64_SSHRvvi_4S, ARM64_INS_SSHR, |
| 11967 | #ifndef CAPSTONE_DIET |
| 11968 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11969 | #endif |
| 11970 | }, |
| 11971 | { |
| 11972 | AArch64_SSHRvvi_8B, ARM64_INS_SSHR, |
| 11973 | #ifndef CAPSTONE_DIET |
| 11974 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11975 | #endif |
| 11976 | }, |
| 11977 | { |
| 11978 | AArch64_SSHRvvi_8H, ARM64_INS_SSHR, |
| 11979 | #ifndef CAPSTONE_DIET |
| 11980 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11981 | #endif |
| 11982 | }, |
| 11983 | { |
| 11984 | AArch64_SSRA, ARM64_INS_SSRA, |
| 11985 | #ifndef CAPSTONE_DIET |
| 11986 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11987 | #endif |
| 11988 | }, |
| 11989 | { |
| 11990 | AArch64_SSRAvvi_16B, ARM64_INS_SSRA, |
| 11991 | #ifndef CAPSTONE_DIET |
| 11992 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11993 | #endif |
| 11994 | }, |
| 11995 | { |
| 11996 | AArch64_SSRAvvi_2D, ARM64_INS_SSRA, |
| 11997 | #ifndef CAPSTONE_DIET |
| 11998 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 11999 | #endif |
| 12000 | }, |
| 12001 | { |
| 12002 | AArch64_SSRAvvi_2S, ARM64_INS_SSRA, |
| 12003 | #ifndef CAPSTONE_DIET |
| 12004 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12005 | #endif |
| 12006 | }, |
| 12007 | { |
| 12008 | AArch64_SSRAvvi_4H, ARM64_INS_SSRA, |
| 12009 | #ifndef CAPSTONE_DIET |
| 12010 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12011 | #endif |
| 12012 | }, |
| 12013 | { |
| 12014 | AArch64_SSRAvvi_4S, ARM64_INS_SSRA, |
| 12015 | #ifndef CAPSTONE_DIET |
| 12016 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12017 | #endif |
| 12018 | }, |
| 12019 | { |
| 12020 | AArch64_SSRAvvi_8B, ARM64_INS_SSRA, |
| 12021 | #ifndef CAPSTONE_DIET |
| 12022 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12023 | #endif |
| 12024 | }, |
| 12025 | { |
| 12026 | AArch64_SSRAvvi_8H, ARM64_INS_SSRA, |
| 12027 | #ifndef CAPSTONE_DIET |
| 12028 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12029 | #endif |
| 12030 | }, |
| 12031 | { |
| 12032 | AArch64_SSUBL2vvv_2d4s, ARM64_INS_SSUBL2, |
| 12033 | #ifndef CAPSTONE_DIET |
| 12034 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12035 | #endif |
| 12036 | }, |
| 12037 | { |
| 12038 | AArch64_SSUBL2vvv_4s8h, ARM64_INS_SSUBL2, |
| 12039 | #ifndef CAPSTONE_DIET |
| 12040 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12041 | #endif |
| 12042 | }, |
| 12043 | { |
| 12044 | AArch64_SSUBL2vvv_8h16b, ARM64_INS_SSUBL2, |
| 12045 | #ifndef CAPSTONE_DIET |
| 12046 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12047 | #endif |
| 12048 | }, |
| 12049 | { |
| 12050 | AArch64_SSUBLvvv_2d2s, ARM64_INS_SSUBL, |
| 12051 | #ifndef CAPSTONE_DIET |
| 12052 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12053 | #endif |
| 12054 | }, |
| 12055 | { |
| 12056 | AArch64_SSUBLvvv_4s4h, ARM64_INS_SSUBL, |
| 12057 | #ifndef CAPSTONE_DIET |
| 12058 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12059 | #endif |
| 12060 | }, |
| 12061 | { |
| 12062 | AArch64_SSUBLvvv_8h8b, ARM64_INS_SSUBL, |
| 12063 | #ifndef CAPSTONE_DIET |
| 12064 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12065 | #endif |
| 12066 | }, |
| 12067 | { |
| 12068 | AArch64_SSUBW2vvv_2d4s, ARM64_INS_SSUBW2, |
| 12069 | #ifndef CAPSTONE_DIET |
| 12070 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12071 | #endif |
| 12072 | }, |
| 12073 | { |
| 12074 | AArch64_SSUBW2vvv_4s8h, ARM64_INS_SSUBW2, |
| 12075 | #ifndef CAPSTONE_DIET |
| 12076 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12077 | #endif |
| 12078 | }, |
| 12079 | { |
| 12080 | AArch64_SSUBW2vvv_8h16b, ARM64_INS_SSUBW2, |
| 12081 | #ifndef CAPSTONE_DIET |
| 12082 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12083 | #endif |
| 12084 | }, |
| 12085 | { |
| 12086 | AArch64_SSUBWvvv_2d2s, ARM64_INS_SSUBW, |
| 12087 | #ifndef CAPSTONE_DIET |
| 12088 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12089 | #endif |
| 12090 | }, |
| 12091 | { |
| 12092 | AArch64_SSUBWvvv_4s4h, ARM64_INS_SSUBW, |
| 12093 | #ifndef CAPSTONE_DIET |
| 12094 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12095 | #endif |
| 12096 | }, |
| 12097 | { |
| 12098 | AArch64_SSUBWvvv_8h8b, ARM64_INS_SSUBW, |
| 12099 | #ifndef CAPSTONE_DIET |
| 12100 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12101 | #endif |
| 12102 | }, |
| 12103 | { |
| 12104 | AArch64_ST1LN_B, ARM64_INS_ST1, |
| 12105 | #ifndef CAPSTONE_DIET |
| 12106 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12107 | #endif |
| 12108 | }, |
| 12109 | { |
| 12110 | AArch64_ST1LN_D, ARM64_INS_ST1, |
| 12111 | #ifndef CAPSTONE_DIET |
| 12112 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12113 | #endif |
| 12114 | }, |
| 12115 | { |
| 12116 | AArch64_ST1LN_H, ARM64_INS_ST1, |
| 12117 | #ifndef CAPSTONE_DIET |
| 12118 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12119 | #endif |
| 12120 | }, |
| 12121 | { |
| 12122 | AArch64_ST1LN_S, ARM64_INS_ST1, |
| 12123 | #ifndef CAPSTONE_DIET |
| 12124 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12125 | #endif |
| 12126 | }, |
| 12127 | { |
| 12128 | AArch64_ST1LN_WB_B_fixed, ARM64_INS_ST1, |
| 12129 | #ifndef CAPSTONE_DIET |
| 12130 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12131 | #endif |
| 12132 | }, |
| 12133 | { |
| 12134 | AArch64_ST1LN_WB_B_register, ARM64_INS_ST1, |
| 12135 | #ifndef CAPSTONE_DIET |
| 12136 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12137 | #endif |
| 12138 | }, |
| 12139 | { |
| 12140 | AArch64_ST1LN_WB_D_fixed, ARM64_INS_ST1, |
| 12141 | #ifndef CAPSTONE_DIET |
| 12142 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12143 | #endif |
| 12144 | }, |
| 12145 | { |
| 12146 | AArch64_ST1LN_WB_D_register, ARM64_INS_ST1, |
| 12147 | #ifndef CAPSTONE_DIET |
| 12148 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12149 | #endif |
| 12150 | }, |
| 12151 | { |
| 12152 | AArch64_ST1LN_WB_H_fixed, ARM64_INS_ST1, |
| 12153 | #ifndef CAPSTONE_DIET |
| 12154 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12155 | #endif |
| 12156 | }, |
| 12157 | { |
| 12158 | AArch64_ST1LN_WB_H_register, ARM64_INS_ST1, |
| 12159 | #ifndef CAPSTONE_DIET |
| 12160 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12161 | #endif |
| 12162 | }, |
| 12163 | { |
| 12164 | AArch64_ST1LN_WB_S_fixed, ARM64_INS_ST1, |
| 12165 | #ifndef CAPSTONE_DIET |
| 12166 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12167 | #endif |
| 12168 | }, |
| 12169 | { |
| 12170 | AArch64_ST1LN_WB_S_register, ARM64_INS_ST1, |
| 12171 | #ifndef CAPSTONE_DIET |
| 12172 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12173 | #endif |
| 12174 | }, |
| 12175 | { |
| 12176 | AArch64_ST1WB_16B_fixed, ARM64_INS_ST1, |
| 12177 | #ifndef CAPSTONE_DIET |
| 12178 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12179 | #endif |
| 12180 | }, |
| 12181 | { |
| 12182 | AArch64_ST1WB_16B_register, ARM64_INS_ST1, |
| 12183 | #ifndef CAPSTONE_DIET |
| 12184 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12185 | #endif |
| 12186 | }, |
| 12187 | { |
| 12188 | AArch64_ST1WB_1D_fixed, ARM64_INS_ST1, |
| 12189 | #ifndef CAPSTONE_DIET |
| 12190 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12191 | #endif |
| 12192 | }, |
| 12193 | { |
| 12194 | AArch64_ST1WB_1D_register, ARM64_INS_ST1, |
| 12195 | #ifndef CAPSTONE_DIET |
| 12196 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12197 | #endif |
| 12198 | }, |
| 12199 | { |
| 12200 | AArch64_ST1WB_2D_fixed, ARM64_INS_ST1, |
| 12201 | #ifndef CAPSTONE_DIET |
| 12202 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12203 | #endif |
| 12204 | }, |
| 12205 | { |
| 12206 | AArch64_ST1WB_2D_register, ARM64_INS_ST1, |
| 12207 | #ifndef CAPSTONE_DIET |
| 12208 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12209 | #endif |
| 12210 | }, |
| 12211 | { |
| 12212 | AArch64_ST1WB_2S_fixed, ARM64_INS_ST1, |
| 12213 | #ifndef CAPSTONE_DIET |
| 12214 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12215 | #endif |
| 12216 | }, |
| 12217 | { |
| 12218 | AArch64_ST1WB_2S_register, ARM64_INS_ST1, |
| 12219 | #ifndef CAPSTONE_DIET |
| 12220 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12221 | #endif |
| 12222 | }, |
| 12223 | { |
| 12224 | AArch64_ST1WB_4H_fixed, ARM64_INS_ST1, |
| 12225 | #ifndef CAPSTONE_DIET |
| 12226 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12227 | #endif |
| 12228 | }, |
| 12229 | { |
| 12230 | AArch64_ST1WB_4H_register, ARM64_INS_ST1, |
| 12231 | #ifndef CAPSTONE_DIET |
| 12232 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12233 | #endif |
| 12234 | }, |
| 12235 | { |
| 12236 | AArch64_ST1WB_4S_fixed, ARM64_INS_ST1, |
| 12237 | #ifndef CAPSTONE_DIET |
| 12238 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12239 | #endif |
| 12240 | }, |
| 12241 | { |
| 12242 | AArch64_ST1WB_4S_register, ARM64_INS_ST1, |
| 12243 | #ifndef CAPSTONE_DIET |
| 12244 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12245 | #endif |
| 12246 | }, |
| 12247 | { |
| 12248 | AArch64_ST1WB_8B_fixed, ARM64_INS_ST1, |
| 12249 | #ifndef CAPSTONE_DIET |
| 12250 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12251 | #endif |
| 12252 | }, |
| 12253 | { |
| 12254 | AArch64_ST1WB_8B_register, ARM64_INS_ST1, |
| 12255 | #ifndef CAPSTONE_DIET |
| 12256 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12257 | #endif |
| 12258 | }, |
| 12259 | { |
| 12260 | AArch64_ST1WB_8H_fixed, ARM64_INS_ST1, |
| 12261 | #ifndef CAPSTONE_DIET |
| 12262 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12263 | #endif |
| 12264 | }, |
| 12265 | { |
| 12266 | AArch64_ST1WB_8H_register, ARM64_INS_ST1, |
| 12267 | #ifndef CAPSTONE_DIET |
| 12268 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12269 | #endif |
| 12270 | }, |
| 12271 | { |
| 12272 | AArch64_ST1_16B, ARM64_INS_ST1, |
| 12273 | #ifndef CAPSTONE_DIET |
| 12274 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12275 | #endif |
| 12276 | }, |
| 12277 | { |
| 12278 | AArch64_ST1_1D, ARM64_INS_ST1, |
| 12279 | #ifndef CAPSTONE_DIET |
| 12280 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12281 | #endif |
| 12282 | }, |
| 12283 | { |
| 12284 | AArch64_ST1_2D, ARM64_INS_ST1, |
| 12285 | #ifndef CAPSTONE_DIET |
| 12286 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12287 | #endif |
| 12288 | }, |
| 12289 | { |
| 12290 | AArch64_ST1_2S, ARM64_INS_ST1, |
| 12291 | #ifndef CAPSTONE_DIET |
| 12292 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12293 | #endif |
| 12294 | }, |
| 12295 | { |
| 12296 | AArch64_ST1_4H, ARM64_INS_ST1, |
| 12297 | #ifndef CAPSTONE_DIET |
| 12298 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12299 | #endif |
| 12300 | }, |
| 12301 | { |
| 12302 | AArch64_ST1_4S, ARM64_INS_ST1, |
| 12303 | #ifndef CAPSTONE_DIET |
| 12304 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12305 | #endif |
| 12306 | }, |
| 12307 | { |
| 12308 | AArch64_ST1_8B, ARM64_INS_ST1, |
| 12309 | #ifndef CAPSTONE_DIET |
| 12310 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12311 | #endif |
| 12312 | }, |
| 12313 | { |
| 12314 | AArch64_ST1_8H, ARM64_INS_ST1, |
| 12315 | #ifndef CAPSTONE_DIET |
| 12316 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12317 | #endif |
| 12318 | }, |
| 12319 | { |
| 12320 | AArch64_ST1x2WB_16B_fixed, ARM64_INS_ST1, |
| 12321 | #ifndef CAPSTONE_DIET |
| 12322 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12323 | #endif |
| 12324 | }, |
| 12325 | { |
| 12326 | AArch64_ST1x2WB_16B_register, ARM64_INS_ST1, |
| 12327 | #ifndef CAPSTONE_DIET |
| 12328 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12329 | #endif |
| 12330 | }, |
| 12331 | { |
| 12332 | AArch64_ST1x2WB_1D_fixed, ARM64_INS_ST1, |
| 12333 | #ifndef CAPSTONE_DIET |
| 12334 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12335 | #endif |
| 12336 | }, |
| 12337 | { |
| 12338 | AArch64_ST1x2WB_1D_register, ARM64_INS_ST1, |
| 12339 | #ifndef CAPSTONE_DIET |
| 12340 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12341 | #endif |
| 12342 | }, |
| 12343 | { |
| 12344 | AArch64_ST1x2WB_2D_fixed, ARM64_INS_ST1, |
| 12345 | #ifndef CAPSTONE_DIET |
| 12346 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12347 | #endif |
| 12348 | }, |
| 12349 | { |
| 12350 | AArch64_ST1x2WB_2D_register, ARM64_INS_ST1, |
| 12351 | #ifndef CAPSTONE_DIET |
| 12352 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12353 | #endif |
| 12354 | }, |
| 12355 | { |
| 12356 | AArch64_ST1x2WB_2S_fixed, ARM64_INS_ST1, |
| 12357 | #ifndef CAPSTONE_DIET |
| 12358 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12359 | #endif |
| 12360 | }, |
| 12361 | { |
| 12362 | AArch64_ST1x2WB_2S_register, ARM64_INS_ST1, |
| 12363 | #ifndef CAPSTONE_DIET |
| 12364 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12365 | #endif |
| 12366 | }, |
| 12367 | { |
| 12368 | AArch64_ST1x2WB_4H_fixed, ARM64_INS_ST1, |
| 12369 | #ifndef CAPSTONE_DIET |
| 12370 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12371 | #endif |
| 12372 | }, |
| 12373 | { |
| 12374 | AArch64_ST1x2WB_4H_register, ARM64_INS_ST1, |
| 12375 | #ifndef CAPSTONE_DIET |
| 12376 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12377 | #endif |
| 12378 | }, |
| 12379 | { |
| 12380 | AArch64_ST1x2WB_4S_fixed, ARM64_INS_ST1, |
| 12381 | #ifndef CAPSTONE_DIET |
| 12382 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12383 | #endif |
| 12384 | }, |
| 12385 | { |
| 12386 | AArch64_ST1x2WB_4S_register, ARM64_INS_ST1, |
| 12387 | #ifndef CAPSTONE_DIET |
| 12388 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12389 | #endif |
| 12390 | }, |
| 12391 | { |
| 12392 | AArch64_ST1x2WB_8B_fixed, ARM64_INS_ST1, |
| 12393 | #ifndef CAPSTONE_DIET |
| 12394 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12395 | #endif |
| 12396 | }, |
| 12397 | { |
| 12398 | AArch64_ST1x2WB_8B_register, ARM64_INS_ST1, |
| 12399 | #ifndef CAPSTONE_DIET |
| 12400 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12401 | #endif |
| 12402 | }, |
| 12403 | { |
| 12404 | AArch64_ST1x2WB_8H_fixed, ARM64_INS_ST1, |
| 12405 | #ifndef CAPSTONE_DIET |
| 12406 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12407 | #endif |
| 12408 | }, |
| 12409 | { |
| 12410 | AArch64_ST1x2WB_8H_register, ARM64_INS_ST1, |
| 12411 | #ifndef CAPSTONE_DIET |
| 12412 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12413 | #endif |
| 12414 | }, |
| 12415 | { |
| 12416 | AArch64_ST1x2_16B, ARM64_INS_ST1, |
| 12417 | #ifndef CAPSTONE_DIET |
| 12418 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12419 | #endif |
| 12420 | }, |
| 12421 | { |
| 12422 | AArch64_ST1x2_1D, ARM64_INS_ST1, |
| 12423 | #ifndef CAPSTONE_DIET |
| 12424 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12425 | #endif |
| 12426 | }, |
| 12427 | { |
| 12428 | AArch64_ST1x2_2D, ARM64_INS_ST1, |
| 12429 | #ifndef CAPSTONE_DIET |
| 12430 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12431 | #endif |
| 12432 | }, |
| 12433 | { |
| 12434 | AArch64_ST1x2_2S, ARM64_INS_ST1, |
| 12435 | #ifndef CAPSTONE_DIET |
| 12436 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12437 | #endif |
| 12438 | }, |
| 12439 | { |
| 12440 | AArch64_ST1x2_4H, ARM64_INS_ST1, |
| 12441 | #ifndef CAPSTONE_DIET |
| 12442 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12443 | #endif |
| 12444 | }, |
| 12445 | { |
| 12446 | AArch64_ST1x2_4S, ARM64_INS_ST1, |
| 12447 | #ifndef CAPSTONE_DIET |
| 12448 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12449 | #endif |
| 12450 | }, |
| 12451 | { |
| 12452 | AArch64_ST1x2_8B, ARM64_INS_ST1, |
| 12453 | #ifndef CAPSTONE_DIET |
| 12454 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12455 | #endif |
| 12456 | }, |
| 12457 | { |
| 12458 | AArch64_ST1x2_8H, ARM64_INS_ST1, |
| 12459 | #ifndef CAPSTONE_DIET |
| 12460 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12461 | #endif |
| 12462 | }, |
| 12463 | { |
| 12464 | AArch64_ST1x3WB_16B_fixed, ARM64_INS_ST1, |
| 12465 | #ifndef CAPSTONE_DIET |
| 12466 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12467 | #endif |
| 12468 | }, |
| 12469 | { |
| 12470 | AArch64_ST1x3WB_16B_register, ARM64_INS_ST1, |
| 12471 | #ifndef CAPSTONE_DIET |
| 12472 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12473 | #endif |
| 12474 | }, |
| 12475 | { |
| 12476 | AArch64_ST1x3WB_1D_fixed, ARM64_INS_ST1, |
| 12477 | #ifndef CAPSTONE_DIET |
| 12478 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12479 | #endif |
| 12480 | }, |
| 12481 | { |
| 12482 | AArch64_ST1x3WB_1D_register, ARM64_INS_ST1, |
| 12483 | #ifndef CAPSTONE_DIET |
| 12484 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12485 | #endif |
| 12486 | }, |
| 12487 | { |
| 12488 | AArch64_ST1x3WB_2D_fixed, ARM64_INS_ST1, |
| 12489 | #ifndef CAPSTONE_DIET |
| 12490 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12491 | #endif |
| 12492 | }, |
| 12493 | { |
| 12494 | AArch64_ST1x3WB_2D_register, ARM64_INS_ST1, |
| 12495 | #ifndef CAPSTONE_DIET |
| 12496 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12497 | #endif |
| 12498 | }, |
| 12499 | { |
| 12500 | AArch64_ST1x3WB_2S_fixed, ARM64_INS_ST1, |
| 12501 | #ifndef CAPSTONE_DIET |
| 12502 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12503 | #endif |
| 12504 | }, |
| 12505 | { |
| 12506 | AArch64_ST1x3WB_2S_register, ARM64_INS_ST1, |
| 12507 | #ifndef CAPSTONE_DIET |
| 12508 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12509 | #endif |
| 12510 | }, |
| 12511 | { |
| 12512 | AArch64_ST1x3WB_4H_fixed, ARM64_INS_ST1, |
| 12513 | #ifndef CAPSTONE_DIET |
| 12514 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12515 | #endif |
| 12516 | }, |
| 12517 | { |
| 12518 | AArch64_ST1x3WB_4H_register, ARM64_INS_ST1, |
| 12519 | #ifndef CAPSTONE_DIET |
| 12520 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12521 | #endif |
| 12522 | }, |
| 12523 | { |
| 12524 | AArch64_ST1x3WB_4S_fixed, ARM64_INS_ST1, |
| 12525 | #ifndef CAPSTONE_DIET |
| 12526 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12527 | #endif |
| 12528 | }, |
| 12529 | { |
| 12530 | AArch64_ST1x3WB_4S_register, ARM64_INS_ST1, |
| 12531 | #ifndef CAPSTONE_DIET |
| 12532 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12533 | #endif |
| 12534 | }, |
| 12535 | { |
| 12536 | AArch64_ST1x3WB_8B_fixed, ARM64_INS_ST1, |
| 12537 | #ifndef CAPSTONE_DIET |
| 12538 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12539 | #endif |
| 12540 | }, |
| 12541 | { |
| 12542 | AArch64_ST1x3WB_8B_register, ARM64_INS_ST1, |
| 12543 | #ifndef CAPSTONE_DIET |
| 12544 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12545 | #endif |
| 12546 | }, |
| 12547 | { |
| 12548 | AArch64_ST1x3WB_8H_fixed, ARM64_INS_ST1, |
| 12549 | #ifndef CAPSTONE_DIET |
| 12550 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12551 | #endif |
| 12552 | }, |
| 12553 | { |
| 12554 | AArch64_ST1x3WB_8H_register, ARM64_INS_ST1, |
| 12555 | #ifndef CAPSTONE_DIET |
| 12556 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12557 | #endif |
| 12558 | }, |
| 12559 | { |
| 12560 | AArch64_ST1x3_16B, ARM64_INS_ST1, |
| 12561 | #ifndef CAPSTONE_DIET |
| 12562 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12563 | #endif |
| 12564 | }, |
| 12565 | { |
| 12566 | AArch64_ST1x3_1D, ARM64_INS_ST1, |
| 12567 | #ifndef CAPSTONE_DIET |
| 12568 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12569 | #endif |
| 12570 | }, |
| 12571 | { |
| 12572 | AArch64_ST1x3_2D, ARM64_INS_ST1, |
| 12573 | #ifndef CAPSTONE_DIET |
| 12574 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12575 | #endif |
| 12576 | }, |
| 12577 | { |
| 12578 | AArch64_ST1x3_2S, ARM64_INS_ST1, |
| 12579 | #ifndef CAPSTONE_DIET |
| 12580 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12581 | #endif |
| 12582 | }, |
| 12583 | { |
| 12584 | AArch64_ST1x3_4H, ARM64_INS_ST1, |
| 12585 | #ifndef CAPSTONE_DIET |
| 12586 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12587 | #endif |
| 12588 | }, |
| 12589 | { |
| 12590 | AArch64_ST1x3_4S, ARM64_INS_ST1, |
| 12591 | #ifndef CAPSTONE_DIET |
| 12592 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12593 | #endif |
| 12594 | }, |
| 12595 | { |
| 12596 | AArch64_ST1x3_8B, ARM64_INS_ST1, |
| 12597 | #ifndef CAPSTONE_DIET |
| 12598 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12599 | #endif |
| 12600 | }, |
| 12601 | { |
| 12602 | AArch64_ST1x3_8H, ARM64_INS_ST1, |
| 12603 | #ifndef CAPSTONE_DIET |
| 12604 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12605 | #endif |
| 12606 | }, |
| 12607 | { |
| 12608 | AArch64_ST1x4WB_16B_fixed, ARM64_INS_ST1, |
| 12609 | #ifndef CAPSTONE_DIET |
| 12610 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12611 | #endif |
| 12612 | }, |
| 12613 | { |
| 12614 | AArch64_ST1x4WB_16B_register, ARM64_INS_ST1, |
| 12615 | #ifndef CAPSTONE_DIET |
| 12616 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12617 | #endif |
| 12618 | }, |
| 12619 | { |
| 12620 | AArch64_ST1x4WB_1D_fixed, ARM64_INS_ST1, |
| 12621 | #ifndef CAPSTONE_DIET |
| 12622 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12623 | #endif |
| 12624 | }, |
| 12625 | { |
| 12626 | AArch64_ST1x4WB_1D_register, ARM64_INS_ST1, |
| 12627 | #ifndef CAPSTONE_DIET |
| 12628 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12629 | #endif |
| 12630 | }, |
| 12631 | { |
| 12632 | AArch64_ST1x4WB_2D_fixed, ARM64_INS_ST1, |
| 12633 | #ifndef CAPSTONE_DIET |
| 12634 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12635 | #endif |
| 12636 | }, |
| 12637 | { |
| 12638 | AArch64_ST1x4WB_2D_register, ARM64_INS_ST1, |
| 12639 | #ifndef CAPSTONE_DIET |
| 12640 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12641 | #endif |
| 12642 | }, |
| 12643 | { |
| 12644 | AArch64_ST1x4WB_2S_fixed, ARM64_INS_ST1, |
| 12645 | #ifndef CAPSTONE_DIET |
| 12646 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12647 | #endif |
| 12648 | }, |
| 12649 | { |
| 12650 | AArch64_ST1x4WB_2S_register, ARM64_INS_ST1, |
| 12651 | #ifndef CAPSTONE_DIET |
| 12652 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12653 | #endif |
| 12654 | }, |
| 12655 | { |
| 12656 | AArch64_ST1x4WB_4H_fixed, ARM64_INS_ST1, |
| 12657 | #ifndef CAPSTONE_DIET |
| 12658 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12659 | #endif |
| 12660 | }, |
| 12661 | { |
| 12662 | AArch64_ST1x4WB_4H_register, ARM64_INS_ST1, |
| 12663 | #ifndef CAPSTONE_DIET |
| 12664 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12665 | #endif |
| 12666 | }, |
| 12667 | { |
| 12668 | AArch64_ST1x4WB_4S_fixed, ARM64_INS_ST1, |
| 12669 | #ifndef CAPSTONE_DIET |
| 12670 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12671 | #endif |
| 12672 | }, |
| 12673 | { |
| 12674 | AArch64_ST1x4WB_4S_register, ARM64_INS_ST1, |
| 12675 | #ifndef CAPSTONE_DIET |
| 12676 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12677 | #endif |
| 12678 | }, |
| 12679 | { |
| 12680 | AArch64_ST1x4WB_8B_fixed, ARM64_INS_ST1, |
| 12681 | #ifndef CAPSTONE_DIET |
| 12682 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12683 | #endif |
| 12684 | }, |
| 12685 | { |
| 12686 | AArch64_ST1x4WB_8B_register, ARM64_INS_ST1, |
| 12687 | #ifndef CAPSTONE_DIET |
| 12688 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12689 | #endif |
| 12690 | }, |
| 12691 | { |
| 12692 | AArch64_ST1x4WB_8H_fixed, ARM64_INS_ST1, |
| 12693 | #ifndef CAPSTONE_DIET |
| 12694 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12695 | #endif |
| 12696 | }, |
| 12697 | { |
| 12698 | AArch64_ST1x4WB_8H_register, ARM64_INS_ST1, |
| 12699 | #ifndef CAPSTONE_DIET |
| 12700 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12701 | #endif |
| 12702 | }, |
| 12703 | { |
| 12704 | AArch64_ST1x4_16B, ARM64_INS_ST1, |
| 12705 | #ifndef CAPSTONE_DIET |
| 12706 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12707 | #endif |
| 12708 | }, |
| 12709 | { |
| 12710 | AArch64_ST1x4_1D, ARM64_INS_ST1, |
| 12711 | #ifndef CAPSTONE_DIET |
| 12712 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12713 | #endif |
| 12714 | }, |
| 12715 | { |
| 12716 | AArch64_ST1x4_2D, ARM64_INS_ST1, |
| 12717 | #ifndef CAPSTONE_DIET |
| 12718 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12719 | #endif |
| 12720 | }, |
| 12721 | { |
| 12722 | AArch64_ST1x4_2S, ARM64_INS_ST1, |
| 12723 | #ifndef CAPSTONE_DIET |
| 12724 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12725 | #endif |
| 12726 | }, |
| 12727 | { |
| 12728 | AArch64_ST1x4_4H, ARM64_INS_ST1, |
| 12729 | #ifndef CAPSTONE_DIET |
| 12730 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12731 | #endif |
| 12732 | }, |
| 12733 | { |
| 12734 | AArch64_ST1x4_4S, ARM64_INS_ST1, |
| 12735 | #ifndef CAPSTONE_DIET |
| 12736 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12737 | #endif |
| 12738 | }, |
| 12739 | { |
| 12740 | AArch64_ST1x4_8B, ARM64_INS_ST1, |
| 12741 | #ifndef CAPSTONE_DIET |
| 12742 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12743 | #endif |
| 12744 | }, |
| 12745 | { |
| 12746 | AArch64_ST1x4_8H, ARM64_INS_ST1, |
| 12747 | #ifndef CAPSTONE_DIET |
| 12748 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12749 | #endif |
| 12750 | }, |
| 12751 | { |
| 12752 | AArch64_ST2LN_B, ARM64_INS_ST2, |
| 12753 | #ifndef CAPSTONE_DIET |
| 12754 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12755 | #endif |
| 12756 | }, |
| 12757 | { |
| 12758 | AArch64_ST2LN_D, ARM64_INS_ST2, |
| 12759 | #ifndef CAPSTONE_DIET |
| 12760 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12761 | #endif |
| 12762 | }, |
| 12763 | { |
| 12764 | AArch64_ST2LN_H, ARM64_INS_ST2, |
| 12765 | #ifndef CAPSTONE_DIET |
| 12766 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12767 | #endif |
| 12768 | }, |
| 12769 | { |
| 12770 | AArch64_ST2LN_S, ARM64_INS_ST2, |
| 12771 | #ifndef CAPSTONE_DIET |
| 12772 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12773 | #endif |
| 12774 | }, |
| 12775 | { |
| 12776 | AArch64_ST2LN_WB_B_fixed, ARM64_INS_ST2, |
| 12777 | #ifndef CAPSTONE_DIET |
| 12778 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12779 | #endif |
| 12780 | }, |
| 12781 | { |
| 12782 | AArch64_ST2LN_WB_B_register, ARM64_INS_ST2, |
| 12783 | #ifndef CAPSTONE_DIET |
| 12784 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12785 | #endif |
| 12786 | }, |
| 12787 | { |
| 12788 | AArch64_ST2LN_WB_D_fixed, ARM64_INS_ST2, |
| 12789 | #ifndef CAPSTONE_DIET |
| 12790 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12791 | #endif |
| 12792 | }, |
| 12793 | { |
| 12794 | AArch64_ST2LN_WB_D_register, ARM64_INS_ST2, |
| 12795 | #ifndef CAPSTONE_DIET |
| 12796 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12797 | #endif |
| 12798 | }, |
| 12799 | { |
| 12800 | AArch64_ST2LN_WB_H_fixed, ARM64_INS_ST2, |
| 12801 | #ifndef CAPSTONE_DIET |
| 12802 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12803 | #endif |
| 12804 | }, |
| 12805 | { |
| 12806 | AArch64_ST2LN_WB_H_register, ARM64_INS_ST2, |
| 12807 | #ifndef CAPSTONE_DIET |
| 12808 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12809 | #endif |
| 12810 | }, |
| 12811 | { |
| 12812 | AArch64_ST2LN_WB_S_fixed, ARM64_INS_ST2, |
| 12813 | #ifndef CAPSTONE_DIET |
| 12814 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12815 | #endif |
| 12816 | }, |
| 12817 | { |
| 12818 | AArch64_ST2LN_WB_S_register, ARM64_INS_ST2, |
| 12819 | #ifndef CAPSTONE_DIET |
| 12820 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12821 | #endif |
| 12822 | }, |
| 12823 | { |
| 12824 | AArch64_ST2WB_16B_fixed, ARM64_INS_ST2, |
| 12825 | #ifndef CAPSTONE_DIET |
| 12826 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12827 | #endif |
| 12828 | }, |
| 12829 | { |
| 12830 | AArch64_ST2WB_16B_register, ARM64_INS_ST2, |
| 12831 | #ifndef CAPSTONE_DIET |
| 12832 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12833 | #endif |
| 12834 | }, |
| 12835 | { |
| 12836 | AArch64_ST2WB_2D_fixed, ARM64_INS_ST2, |
| 12837 | #ifndef CAPSTONE_DIET |
| 12838 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12839 | #endif |
| 12840 | }, |
| 12841 | { |
| 12842 | AArch64_ST2WB_2D_register, ARM64_INS_ST2, |
| 12843 | #ifndef CAPSTONE_DIET |
| 12844 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12845 | #endif |
| 12846 | }, |
| 12847 | { |
| 12848 | AArch64_ST2WB_2S_fixed, ARM64_INS_ST2, |
| 12849 | #ifndef CAPSTONE_DIET |
| 12850 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12851 | #endif |
| 12852 | }, |
| 12853 | { |
| 12854 | AArch64_ST2WB_2S_register, ARM64_INS_ST2, |
| 12855 | #ifndef CAPSTONE_DIET |
| 12856 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12857 | #endif |
| 12858 | }, |
| 12859 | { |
| 12860 | AArch64_ST2WB_4H_fixed, ARM64_INS_ST2, |
| 12861 | #ifndef CAPSTONE_DIET |
| 12862 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12863 | #endif |
| 12864 | }, |
| 12865 | { |
| 12866 | AArch64_ST2WB_4H_register, ARM64_INS_ST2, |
| 12867 | #ifndef CAPSTONE_DIET |
| 12868 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12869 | #endif |
| 12870 | }, |
| 12871 | { |
| 12872 | AArch64_ST2WB_4S_fixed, ARM64_INS_ST2, |
| 12873 | #ifndef CAPSTONE_DIET |
| 12874 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12875 | #endif |
| 12876 | }, |
| 12877 | { |
| 12878 | AArch64_ST2WB_4S_register, ARM64_INS_ST2, |
| 12879 | #ifndef CAPSTONE_DIET |
| 12880 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12881 | #endif |
| 12882 | }, |
| 12883 | { |
| 12884 | AArch64_ST2WB_8B_fixed, ARM64_INS_ST2, |
| 12885 | #ifndef CAPSTONE_DIET |
| 12886 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12887 | #endif |
| 12888 | }, |
| 12889 | { |
| 12890 | AArch64_ST2WB_8B_register, ARM64_INS_ST2, |
| 12891 | #ifndef CAPSTONE_DIET |
| 12892 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12893 | #endif |
| 12894 | }, |
| 12895 | { |
| 12896 | AArch64_ST2WB_8H_fixed, ARM64_INS_ST2, |
| 12897 | #ifndef CAPSTONE_DIET |
| 12898 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12899 | #endif |
| 12900 | }, |
| 12901 | { |
| 12902 | AArch64_ST2WB_8H_register, ARM64_INS_ST2, |
| 12903 | #ifndef CAPSTONE_DIET |
| 12904 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12905 | #endif |
| 12906 | }, |
| 12907 | { |
| 12908 | AArch64_ST2_16B, ARM64_INS_ST2, |
| 12909 | #ifndef CAPSTONE_DIET |
| 12910 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12911 | #endif |
| 12912 | }, |
| 12913 | { |
| 12914 | AArch64_ST2_2D, ARM64_INS_ST2, |
| 12915 | #ifndef CAPSTONE_DIET |
| 12916 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12917 | #endif |
| 12918 | }, |
| 12919 | { |
| 12920 | AArch64_ST2_2S, ARM64_INS_ST2, |
| 12921 | #ifndef CAPSTONE_DIET |
| 12922 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12923 | #endif |
| 12924 | }, |
| 12925 | { |
| 12926 | AArch64_ST2_4H, ARM64_INS_ST2, |
| 12927 | #ifndef CAPSTONE_DIET |
| 12928 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12929 | #endif |
| 12930 | }, |
| 12931 | { |
| 12932 | AArch64_ST2_4S, ARM64_INS_ST2, |
| 12933 | #ifndef CAPSTONE_DIET |
| 12934 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12935 | #endif |
| 12936 | }, |
| 12937 | { |
| 12938 | AArch64_ST2_8B, ARM64_INS_ST2, |
| 12939 | #ifndef CAPSTONE_DIET |
| 12940 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12941 | #endif |
| 12942 | }, |
| 12943 | { |
| 12944 | AArch64_ST2_8H, ARM64_INS_ST2, |
| 12945 | #ifndef CAPSTONE_DIET |
| 12946 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12947 | #endif |
| 12948 | }, |
| 12949 | { |
| 12950 | AArch64_ST3LN_B, ARM64_INS_ST3, |
| 12951 | #ifndef CAPSTONE_DIET |
| 12952 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12953 | #endif |
| 12954 | }, |
| 12955 | { |
| 12956 | AArch64_ST3LN_D, ARM64_INS_ST3, |
| 12957 | #ifndef CAPSTONE_DIET |
| 12958 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12959 | #endif |
| 12960 | }, |
| 12961 | { |
| 12962 | AArch64_ST3LN_H, ARM64_INS_ST3, |
| 12963 | #ifndef CAPSTONE_DIET |
| 12964 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12965 | #endif |
| 12966 | }, |
| 12967 | { |
| 12968 | AArch64_ST3LN_S, ARM64_INS_ST3, |
| 12969 | #ifndef CAPSTONE_DIET |
| 12970 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12971 | #endif |
| 12972 | }, |
| 12973 | { |
| 12974 | AArch64_ST3LN_WB_B_fixed, ARM64_INS_ST3, |
| 12975 | #ifndef CAPSTONE_DIET |
| 12976 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12977 | #endif |
| 12978 | }, |
| 12979 | { |
| 12980 | AArch64_ST3LN_WB_B_register, ARM64_INS_ST3, |
| 12981 | #ifndef CAPSTONE_DIET |
| 12982 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12983 | #endif |
| 12984 | }, |
| 12985 | { |
| 12986 | AArch64_ST3LN_WB_D_fixed, ARM64_INS_ST3, |
| 12987 | #ifndef CAPSTONE_DIET |
| 12988 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12989 | #endif |
| 12990 | }, |
| 12991 | { |
| 12992 | AArch64_ST3LN_WB_D_register, ARM64_INS_ST3, |
| 12993 | #ifndef CAPSTONE_DIET |
| 12994 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 12995 | #endif |
| 12996 | }, |
| 12997 | { |
| 12998 | AArch64_ST3LN_WB_H_fixed, ARM64_INS_ST3, |
| 12999 | #ifndef CAPSTONE_DIET |
| 13000 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13001 | #endif |
| 13002 | }, |
| 13003 | { |
| 13004 | AArch64_ST3LN_WB_H_register, ARM64_INS_ST3, |
| 13005 | #ifndef CAPSTONE_DIET |
| 13006 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13007 | #endif |
| 13008 | }, |
| 13009 | { |
| 13010 | AArch64_ST3LN_WB_S_fixed, ARM64_INS_ST3, |
| 13011 | #ifndef CAPSTONE_DIET |
| 13012 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13013 | #endif |
| 13014 | }, |
| 13015 | { |
| 13016 | AArch64_ST3LN_WB_S_register, ARM64_INS_ST3, |
| 13017 | #ifndef CAPSTONE_DIET |
| 13018 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13019 | #endif |
| 13020 | }, |
| 13021 | { |
| 13022 | AArch64_ST3WB_16B_fixed, ARM64_INS_ST3, |
| 13023 | #ifndef CAPSTONE_DIET |
| 13024 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13025 | #endif |
| 13026 | }, |
| 13027 | { |
| 13028 | AArch64_ST3WB_16B_register, ARM64_INS_ST3, |
| 13029 | #ifndef CAPSTONE_DIET |
| 13030 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13031 | #endif |
| 13032 | }, |
| 13033 | { |
| 13034 | AArch64_ST3WB_2D_fixed, ARM64_INS_ST3, |
| 13035 | #ifndef CAPSTONE_DIET |
| 13036 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13037 | #endif |
| 13038 | }, |
| 13039 | { |
| 13040 | AArch64_ST3WB_2D_register, ARM64_INS_ST3, |
| 13041 | #ifndef CAPSTONE_DIET |
| 13042 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13043 | #endif |
| 13044 | }, |
| 13045 | { |
| 13046 | AArch64_ST3WB_2S_fixed, ARM64_INS_ST3, |
| 13047 | #ifndef CAPSTONE_DIET |
| 13048 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13049 | #endif |
| 13050 | }, |
| 13051 | { |
| 13052 | AArch64_ST3WB_2S_register, ARM64_INS_ST3, |
| 13053 | #ifndef CAPSTONE_DIET |
| 13054 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13055 | #endif |
| 13056 | }, |
| 13057 | { |
| 13058 | AArch64_ST3WB_4H_fixed, ARM64_INS_ST3, |
| 13059 | #ifndef CAPSTONE_DIET |
| 13060 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13061 | #endif |
| 13062 | }, |
| 13063 | { |
| 13064 | AArch64_ST3WB_4H_register, ARM64_INS_ST3, |
| 13065 | #ifndef CAPSTONE_DIET |
| 13066 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13067 | #endif |
| 13068 | }, |
| 13069 | { |
| 13070 | AArch64_ST3WB_4S_fixed, ARM64_INS_ST3, |
| 13071 | #ifndef CAPSTONE_DIET |
| 13072 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13073 | #endif |
| 13074 | }, |
| 13075 | { |
| 13076 | AArch64_ST3WB_4S_register, ARM64_INS_ST3, |
| 13077 | #ifndef CAPSTONE_DIET |
| 13078 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13079 | #endif |
| 13080 | }, |
| 13081 | { |
| 13082 | AArch64_ST3WB_8B_fixed, ARM64_INS_ST3, |
| 13083 | #ifndef CAPSTONE_DIET |
| 13084 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13085 | #endif |
| 13086 | }, |
| 13087 | { |
| 13088 | AArch64_ST3WB_8B_register, ARM64_INS_ST3, |
| 13089 | #ifndef CAPSTONE_DIET |
| 13090 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13091 | #endif |
| 13092 | }, |
| 13093 | { |
| 13094 | AArch64_ST3WB_8H_fixed, ARM64_INS_ST3, |
| 13095 | #ifndef CAPSTONE_DIET |
| 13096 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13097 | #endif |
| 13098 | }, |
| 13099 | { |
| 13100 | AArch64_ST3WB_8H_register, ARM64_INS_ST3, |
| 13101 | #ifndef CAPSTONE_DIET |
| 13102 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13103 | #endif |
| 13104 | }, |
| 13105 | { |
| 13106 | AArch64_ST3_16B, ARM64_INS_ST3, |
| 13107 | #ifndef CAPSTONE_DIET |
| 13108 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13109 | #endif |
| 13110 | }, |
| 13111 | { |
| 13112 | AArch64_ST3_2D, ARM64_INS_ST3, |
| 13113 | #ifndef CAPSTONE_DIET |
| 13114 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13115 | #endif |
| 13116 | }, |
| 13117 | { |
| 13118 | AArch64_ST3_2S, ARM64_INS_ST3, |
| 13119 | #ifndef CAPSTONE_DIET |
| 13120 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13121 | #endif |
| 13122 | }, |
| 13123 | { |
| 13124 | AArch64_ST3_4H, ARM64_INS_ST3, |
| 13125 | #ifndef CAPSTONE_DIET |
| 13126 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13127 | #endif |
| 13128 | }, |
| 13129 | { |
| 13130 | AArch64_ST3_4S, ARM64_INS_ST3, |
| 13131 | #ifndef CAPSTONE_DIET |
| 13132 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13133 | #endif |
| 13134 | }, |
| 13135 | { |
| 13136 | AArch64_ST3_8B, ARM64_INS_ST3, |
| 13137 | #ifndef CAPSTONE_DIET |
| 13138 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13139 | #endif |
| 13140 | }, |
| 13141 | { |
| 13142 | AArch64_ST3_8H, ARM64_INS_ST3, |
| 13143 | #ifndef CAPSTONE_DIET |
| 13144 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13145 | #endif |
| 13146 | }, |
| 13147 | { |
| 13148 | AArch64_ST4LN_B, ARM64_INS_ST4, |
| 13149 | #ifndef CAPSTONE_DIET |
| 13150 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13151 | #endif |
| 13152 | }, |
| 13153 | { |
| 13154 | AArch64_ST4LN_D, ARM64_INS_ST4, |
| 13155 | #ifndef CAPSTONE_DIET |
| 13156 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13157 | #endif |
| 13158 | }, |
| 13159 | { |
| 13160 | AArch64_ST4LN_H, ARM64_INS_ST4, |
| 13161 | #ifndef CAPSTONE_DIET |
| 13162 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13163 | #endif |
| 13164 | }, |
| 13165 | { |
| 13166 | AArch64_ST4LN_S, ARM64_INS_ST4, |
| 13167 | #ifndef CAPSTONE_DIET |
| 13168 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13169 | #endif |
| 13170 | }, |
| 13171 | { |
| 13172 | AArch64_ST4LN_WB_B_fixed, ARM64_INS_ST4, |
| 13173 | #ifndef CAPSTONE_DIET |
| 13174 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13175 | #endif |
| 13176 | }, |
| 13177 | { |
| 13178 | AArch64_ST4LN_WB_B_register, ARM64_INS_ST4, |
| 13179 | #ifndef CAPSTONE_DIET |
| 13180 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13181 | #endif |
| 13182 | }, |
| 13183 | { |
| 13184 | AArch64_ST4LN_WB_D_fixed, ARM64_INS_ST4, |
| 13185 | #ifndef CAPSTONE_DIET |
| 13186 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13187 | #endif |
| 13188 | }, |
| 13189 | { |
| 13190 | AArch64_ST4LN_WB_D_register, ARM64_INS_ST4, |
| 13191 | #ifndef CAPSTONE_DIET |
| 13192 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13193 | #endif |
| 13194 | }, |
| 13195 | { |
| 13196 | AArch64_ST4LN_WB_H_fixed, ARM64_INS_ST4, |
| 13197 | #ifndef CAPSTONE_DIET |
| 13198 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13199 | #endif |
| 13200 | }, |
| 13201 | { |
| 13202 | AArch64_ST4LN_WB_H_register, ARM64_INS_ST4, |
| 13203 | #ifndef CAPSTONE_DIET |
| 13204 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13205 | #endif |
| 13206 | }, |
| 13207 | { |
| 13208 | AArch64_ST4LN_WB_S_fixed, ARM64_INS_ST4, |
| 13209 | #ifndef CAPSTONE_DIET |
| 13210 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13211 | #endif |
| 13212 | }, |
| 13213 | { |
| 13214 | AArch64_ST4LN_WB_S_register, ARM64_INS_ST4, |
| 13215 | #ifndef CAPSTONE_DIET |
| 13216 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13217 | #endif |
| 13218 | }, |
| 13219 | { |
| 13220 | AArch64_ST4WB_16B_fixed, ARM64_INS_ST4, |
| 13221 | #ifndef CAPSTONE_DIET |
| 13222 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13223 | #endif |
| 13224 | }, |
| 13225 | { |
| 13226 | AArch64_ST4WB_16B_register, ARM64_INS_ST4, |
| 13227 | #ifndef CAPSTONE_DIET |
| 13228 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13229 | #endif |
| 13230 | }, |
| 13231 | { |
| 13232 | AArch64_ST4WB_2D_fixed, ARM64_INS_ST4, |
| 13233 | #ifndef CAPSTONE_DIET |
| 13234 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13235 | #endif |
| 13236 | }, |
| 13237 | { |
| 13238 | AArch64_ST4WB_2D_register, ARM64_INS_ST4, |
| 13239 | #ifndef CAPSTONE_DIET |
| 13240 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13241 | #endif |
| 13242 | }, |
| 13243 | { |
| 13244 | AArch64_ST4WB_2S_fixed, ARM64_INS_ST4, |
| 13245 | #ifndef CAPSTONE_DIET |
| 13246 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13247 | #endif |
| 13248 | }, |
| 13249 | { |
| 13250 | AArch64_ST4WB_2S_register, ARM64_INS_ST4, |
| 13251 | #ifndef CAPSTONE_DIET |
| 13252 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13253 | #endif |
| 13254 | }, |
| 13255 | { |
| 13256 | AArch64_ST4WB_4H_fixed, ARM64_INS_ST4, |
| 13257 | #ifndef CAPSTONE_DIET |
| 13258 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13259 | #endif |
| 13260 | }, |
| 13261 | { |
| 13262 | AArch64_ST4WB_4H_register, ARM64_INS_ST4, |
| 13263 | #ifndef CAPSTONE_DIET |
| 13264 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13265 | #endif |
| 13266 | }, |
| 13267 | { |
| 13268 | AArch64_ST4WB_4S_fixed, ARM64_INS_ST4, |
| 13269 | #ifndef CAPSTONE_DIET |
| 13270 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13271 | #endif |
| 13272 | }, |
| 13273 | { |
| 13274 | AArch64_ST4WB_4S_register, ARM64_INS_ST4, |
| 13275 | #ifndef CAPSTONE_DIET |
| 13276 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13277 | #endif |
| 13278 | }, |
| 13279 | { |
| 13280 | AArch64_ST4WB_8B_fixed, ARM64_INS_ST4, |
| 13281 | #ifndef CAPSTONE_DIET |
| 13282 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13283 | #endif |
| 13284 | }, |
| 13285 | { |
| 13286 | AArch64_ST4WB_8B_register, ARM64_INS_ST4, |
| 13287 | #ifndef CAPSTONE_DIET |
| 13288 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13289 | #endif |
| 13290 | }, |
| 13291 | { |
| 13292 | AArch64_ST4WB_8H_fixed, ARM64_INS_ST4, |
| 13293 | #ifndef CAPSTONE_DIET |
| 13294 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13295 | #endif |
| 13296 | }, |
| 13297 | { |
| 13298 | AArch64_ST4WB_8H_register, ARM64_INS_ST4, |
| 13299 | #ifndef CAPSTONE_DIET |
| 13300 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13301 | #endif |
| 13302 | }, |
| 13303 | { |
| 13304 | AArch64_ST4_16B, ARM64_INS_ST4, |
| 13305 | #ifndef CAPSTONE_DIET |
| 13306 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13307 | #endif |
| 13308 | }, |
| 13309 | { |
| 13310 | AArch64_ST4_2D, ARM64_INS_ST4, |
| 13311 | #ifndef CAPSTONE_DIET |
| 13312 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13313 | #endif |
| 13314 | }, |
| 13315 | { |
| 13316 | AArch64_ST4_2S, ARM64_INS_ST4, |
| 13317 | #ifndef CAPSTONE_DIET |
| 13318 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13319 | #endif |
| 13320 | }, |
| 13321 | { |
| 13322 | AArch64_ST4_4H, ARM64_INS_ST4, |
| 13323 | #ifndef CAPSTONE_DIET |
| 13324 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13325 | #endif |
| 13326 | }, |
| 13327 | { |
| 13328 | AArch64_ST4_4S, ARM64_INS_ST4, |
| 13329 | #ifndef CAPSTONE_DIET |
| 13330 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13331 | #endif |
| 13332 | }, |
| 13333 | { |
| 13334 | AArch64_ST4_8B, ARM64_INS_ST4, |
| 13335 | #ifndef CAPSTONE_DIET |
| 13336 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13337 | #endif |
| 13338 | }, |
| 13339 | { |
| 13340 | AArch64_ST4_8H, ARM64_INS_ST4, |
| 13341 | #ifndef CAPSTONE_DIET |
| 13342 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13343 | #endif |
| 13344 | }, |
| 13345 | { |
| 13346 | AArch64_STLR_byte, ARM64_INS_STLRB, |
| 13347 | #ifndef CAPSTONE_DIET |
| 13348 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13349 | #endif |
| 13350 | }, |
| 13351 | { |
| 13352 | AArch64_STLR_dword, ARM64_INS_STLR, |
| 13353 | #ifndef CAPSTONE_DIET |
| 13354 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13355 | #endif |
| 13356 | }, |
| 13357 | { |
| 13358 | AArch64_STLR_hword, ARM64_INS_STLRH, |
| 13359 | #ifndef CAPSTONE_DIET |
| 13360 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13361 | #endif |
| 13362 | }, |
| 13363 | { |
| 13364 | AArch64_STLR_word, ARM64_INS_STLR, |
| 13365 | #ifndef CAPSTONE_DIET |
| 13366 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13367 | #endif |
| 13368 | }, |
| 13369 | { |
| 13370 | AArch64_STLXP_dword, ARM64_INS_STLXP, |
| 13371 | #ifndef CAPSTONE_DIET |
| 13372 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13373 | #endif |
| 13374 | }, |
| 13375 | { |
| 13376 | AArch64_STLXP_word, ARM64_INS_STLXP, |
| 13377 | #ifndef CAPSTONE_DIET |
| 13378 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13379 | #endif |
| 13380 | }, |
| 13381 | { |
| 13382 | AArch64_STLXR_byte, ARM64_INS_STLXRB, |
| 13383 | #ifndef CAPSTONE_DIET |
| 13384 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13385 | #endif |
| 13386 | }, |
| 13387 | { |
| 13388 | AArch64_STLXR_dword, ARM64_INS_STLXR, |
| 13389 | #ifndef CAPSTONE_DIET |
| 13390 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13391 | #endif |
| 13392 | }, |
| 13393 | { |
| 13394 | AArch64_STLXR_hword, ARM64_INS_STLXRH, |
| 13395 | #ifndef CAPSTONE_DIET |
| 13396 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13397 | #endif |
| 13398 | }, |
| 13399 | { |
| 13400 | AArch64_STLXR_word, ARM64_INS_STLXR, |
| 13401 | #ifndef CAPSTONE_DIET |
| 13402 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13403 | #endif |
| 13404 | }, |
| 13405 | { |
| 13406 | AArch64_STXP_dword, ARM64_INS_STXP, |
| 13407 | #ifndef CAPSTONE_DIET |
| 13408 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13409 | #endif |
| 13410 | }, |
| 13411 | { |
| 13412 | AArch64_STXP_word, ARM64_INS_STXP, |
| 13413 | #ifndef CAPSTONE_DIET |
| 13414 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13415 | #endif |
| 13416 | }, |
| 13417 | { |
| 13418 | AArch64_STXR_byte, ARM64_INS_STXRB, |
| 13419 | #ifndef CAPSTONE_DIET |
| 13420 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13421 | #endif |
| 13422 | }, |
| 13423 | { |
| 13424 | AArch64_STXR_dword, ARM64_INS_STXR, |
| 13425 | #ifndef CAPSTONE_DIET |
| 13426 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13427 | #endif |
| 13428 | }, |
| 13429 | { |
| 13430 | AArch64_STXR_hword, ARM64_INS_STXRH, |
| 13431 | #ifndef CAPSTONE_DIET |
| 13432 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13433 | #endif |
| 13434 | }, |
| 13435 | { |
| 13436 | AArch64_STXR_word, ARM64_INS_STXR, |
| 13437 | #ifndef CAPSTONE_DIET |
| 13438 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13439 | #endif |
| 13440 | }, |
| 13441 | { |
| 13442 | AArch64_SUBHN2vvv_16b8h, ARM64_INS_SUBHN2, |
| 13443 | #ifndef CAPSTONE_DIET |
| 13444 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13445 | #endif |
| 13446 | }, |
| 13447 | { |
| 13448 | AArch64_SUBHN2vvv_4s2d, ARM64_INS_SUBHN2, |
| 13449 | #ifndef CAPSTONE_DIET |
| 13450 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13451 | #endif |
| 13452 | }, |
| 13453 | { |
| 13454 | AArch64_SUBHN2vvv_8h4s, ARM64_INS_SUBHN2, |
| 13455 | #ifndef CAPSTONE_DIET |
| 13456 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13457 | #endif |
| 13458 | }, |
| 13459 | { |
| 13460 | AArch64_SUBHNvvv_2s2d, ARM64_INS_SUBHN, |
| 13461 | #ifndef CAPSTONE_DIET |
| 13462 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13463 | #endif |
| 13464 | }, |
| 13465 | { |
| 13466 | AArch64_SUBHNvvv_4h4s, ARM64_INS_SUBHN, |
| 13467 | #ifndef CAPSTONE_DIET |
| 13468 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13469 | #endif |
| 13470 | }, |
| 13471 | { |
| 13472 | AArch64_SUBHNvvv_8b8h, ARM64_INS_SUBHN, |
| 13473 | #ifndef CAPSTONE_DIET |
| 13474 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13475 | #endif |
| 13476 | }, |
| 13477 | { |
| 13478 | AArch64_SUBSwww_asr, ARM64_INS_SUB, |
| 13479 | #ifndef CAPSTONE_DIET |
| 13480 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13481 | #endif |
| 13482 | }, |
| 13483 | { |
| 13484 | AArch64_SUBSwww_lsl, ARM64_INS_SUB, |
| 13485 | #ifndef CAPSTONE_DIET |
| 13486 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13487 | #endif |
| 13488 | }, |
| 13489 | { |
| 13490 | AArch64_SUBSwww_lsr, ARM64_INS_SUB, |
| 13491 | #ifndef CAPSTONE_DIET |
| 13492 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13493 | #endif |
| 13494 | }, |
| 13495 | { |
| 13496 | AArch64_SUBSwww_sxtb, ARM64_INS_SUB, |
| 13497 | #ifndef CAPSTONE_DIET |
| 13498 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13499 | #endif |
| 13500 | }, |
| 13501 | { |
| 13502 | AArch64_SUBSwww_sxth, ARM64_INS_SUB, |
| 13503 | #ifndef CAPSTONE_DIET |
| 13504 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13505 | #endif |
| 13506 | }, |
| 13507 | { |
| 13508 | AArch64_SUBSwww_sxtw, ARM64_INS_SUB, |
| 13509 | #ifndef CAPSTONE_DIET |
| 13510 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13511 | #endif |
| 13512 | }, |
| 13513 | { |
| 13514 | AArch64_SUBSwww_sxtx, ARM64_INS_SUB, |
| 13515 | #ifndef CAPSTONE_DIET |
| 13516 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13517 | #endif |
| 13518 | }, |
| 13519 | { |
| 13520 | AArch64_SUBSwww_uxtb, ARM64_INS_SUB, |
| 13521 | #ifndef CAPSTONE_DIET |
| 13522 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13523 | #endif |
| 13524 | }, |
| 13525 | { |
| 13526 | AArch64_SUBSwww_uxth, ARM64_INS_SUB, |
| 13527 | #ifndef CAPSTONE_DIET |
| 13528 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13529 | #endif |
| 13530 | }, |
| 13531 | { |
| 13532 | AArch64_SUBSwww_uxtw, ARM64_INS_SUB, |
| 13533 | #ifndef CAPSTONE_DIET |
| 13534 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13535 | #endif |
| 13536 | }, |
| 13537 | { |
| 13538 | AArch64_SUBSwww_uxtx, ARM64_INS_SUB, |
| 13539 | #ifndef CAPSTONE_DIET |
| 13540 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13541 | #endif |
| 13542 | }, |
| 13543 | { |
| 13544 | AArch64_SUBSxxw_sxtb, ARM64_INS_SUB, |
| 13545 | #ifndef CAPSTONE_DIET |
| 13546 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13547 | #endif |
| 13548 | }, |
| 13549 | { |
| 13550 | AArch64_SUBSxxw_sxth, ARM64_INS_SUB, |
| 13551 | #ifndef CAPSTONE_DIET |
| 13552 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13553 | #endif |
| 13554 | }, |
| 13555 | { |
| 13556 | AArch64_SUBSxxw_sxtw, ARM64_INS_SUB, |
| 13557 | #ifndef CAPSTONE_DIET |
| 13558 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13559 | #endif |
| 13560 | }, |
| 13561 | { |
| 13562 | AArch64_SUBSxxw_uxtb, ARM64_INS_SUB, |
| 13563 | #ifndef CAPSTONE_DIET |
| 13564 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13565 | #endif |
| 13566 | }, |
| 13567 | { |
| 13568 | AArch64_SUBSxxw_uxth, ARM64_INS_SUB, |
| 13569 | #ifndef CAPSTONE_DIET |
| 13570 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13571 | #endif |
| 13572 | }, |
| 13573 | { |
| 13574 | AArch64_SUBSxxw_uxtw, ARM64_INS_SUB, |
| 13575 | #ifndef CAPSTONE_DIET |
| 13576 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13577 | #endif |
| 13578 | }, |
| 13579 | { |
| 13580 | AArch64_SUBSxxx_asr, ARM64_INS_SUB, |
| 13581 | #ifndef CAPSTONE_DIET |
| 13582 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13583 | #endif |
| 13584 | }, |
| 13585 | { |
| 13586 | AArch64_SUBSxxx_lsl, ARM64_INS_SUB, |
| 13587 | #ifndef CAPSTONE_DIET |
| 13588 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13589 | #endif |
| 13590 | }, |
| 13591 | { |
| 13592 | AArch64_SUBSxxx_lsr, ARM64_INS_SUB, |
| 13593 | #ifndef CAPSTONE_DIET |
| 13594 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13595 | #endif |
| 13596 | }, |
| 13597 | { |
| 13598 | AArch64_SUBSxxx_sxtx, ARM64_INS_SUB, |
| 13599 | #ifndef CAPSTONE_DIET |
| 13600 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13601 | #endif |
| 13602 | }, |
| 13603 | { |
| 13604 | AArch64_SUBSxxx_uxtx, ARM64_INS_SUB, |
| 13605 | #ifndef CAPSTONE_DIET |
| 13606 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13607 | #endif |
| 13608 | }, |
| 13609 | { |
| 13610 | AArch64_SUBddd, ARM64_INS_SUB, |
| 13611 | #ifndef CAPSTONE_DIET |
| 13612 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13613 | #endif |
| 13614 | }, |
| 13615 | { |
| 13616 | AArch64_SUBvvv_16B, ARM64_INS_SUB, |
| 13617 | #ifndef CAPSTONE_DIET |
| 13618 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13619 | #endif |
| 13620 | }, |
| 13621 | { |
| 13622 | AArch64_SUBvvv_2D, ARM64_INS_SUB, |
| 13623 | #ifndef CAPSTONE_DIET |
| 13624 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13625 | #endif |
| 13626 | }, |
| 13627 | { |
| 13628 | AArch64_SUBvvv_2S, ARM64_INS_SUB, |
| 13629 | #ifndef CAPSTONE_DIET |
| 13630 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13631 | #endif |
| 13632 | }, |
| 13633 | { |
| 13634 | AArch64_SUBvvv_4H, ARM64_INS_SUB, |
| 13635 | #ifndef CAPSTONE_DIET |
| 13636 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13637 | #endif |
| 13638 | }, |
| 13639 | { |
| 13640 | AArch64_SUBvvv_4S, ARM64_INS_SUB, |
| 13641 | #ifndef CAPSTONE_DIET |
| 13642 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13643 | #endif |
| 13644 | }, |
| 13645 | { |
| 13646 | AArch64_SUBvvv_8B, ARM64_INS_SUB, |
| 13647 | #ifndef CAPSTONE_DIET |
| 13648 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13649 | #endif |
| 13650 | }, |
| 13651 | { |
| 13652 | AArch64_SUBvvv_8H, ARM64_INS_SUB, |
| 13653 | #ifndef CAPSTONE_DIET |
| 13654 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13655 | #endif |
| 13656 | }, |
| 13657 | { |
| 13658 | AArch64_SUBwwi_lsl0_S, ARM64_INS_SUB, |
| 13659 | #ifndef CAPSTONE_DIET |
| 13660 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13661 | #endif |
| 13662 | }, |
| 13663 | { |
| 13664 | AArch64_SUBwwi_lsl0_cmp, ARM64_INS_CMP, |
| 13665 | #ifndef CAPSTONE_DIET |
| 13666 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13667 | #endif |
| 13668 | }, |
| 13669 | { |
| 13670 | AArch64_SUBwwi_lsl0_s, ARM64_INS_SUB, |
| 13671 | #ifndef CAPSTONE_DIET |
| 13672 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13673 | #endif |
| 13674 | }, |
| 13675 | { |
| 13676 | AArch64_SUBwwi_lsl12_S, ARM64_INS_SUB, |
| 13677 | #ifndef CAPSTONE_DIET |
| 13678 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13679 | #endif |
| 13680 | }, |
| 13681 | { |
| 13682 | AArch64_SUBwwi_lsl12_cmp, ARM64_INS_CMP, |
| 13683 | #ifndef CAPSTONE_DIET |
| 13684 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13685 | #endif |
| 13686 | }, |
| 13687 | { |
| 13688 | AArch64_SUBwwi_lsl12_s, ARM64_INS_SUB, |
| 13689 | #ifndef CAPSTONE_DIET |
| 13690 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13691 | #endif |
| 13692 | }, |
| 13693 | { |
| 13694 | AArch64_SUBwww_asr, ARM64_INS_SUB, |
| 13695 | #ifndef CAPSTONE_DIET |
| 13696 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13697 | #endif |
| 13698 | }, |
| 13699 | { |
| 13700 | AArch64_SUBwww_lsl, ARM64_INS_SUB, |
| 13701 | #ifndef CAPSTONE_DIET |
| 13702 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13703 | #endif |
| 13704 | }, |
| 13705 | { |
| 13706 | AArch64_SUBwww_lsr, ARM64_INS_SUB, |
| 13707 | #ifndef CAPSTONE_DIET |
| 13708 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13709 | #endif |
| 13710 | }, |
| 13711 | { |
| 13712 | AArch64_SUBwww_sxtb, ARM64_INS_SUB, |
| 13713 | #ifndef CAPSTONE_DIET |
| 13714 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13715 | #endif |
| 13716 | }, |
| 13717 | { |
| 13718 | AArch64_SUBwww_sxth, ARM64_INS_SUB, |
| 13719 | #ifndef CAPSTONE_DIET |
| 13720 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13721 | #endif |
| 13722 | }, |
| 13723 | { |
| 13724 | AArch64_SUBwww_sxtw, ARM64_INS_SUB, |
| 13725 | #ifndef CAPSTONE_DIET |
| 13726 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13727 | #endif |
| 13728 | }, |
| 13729 | { |
| 13730 | AArch64_SUBwww_sxtx, ARM64_INS_SUB, |
| 13731 | #ifndef CAPSTONE_DIET |
| 13732 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13733 | #endif |
| 13734 | }, |
| 13735 | { |
| 13736 | AArch64_SUBwww_uxtb, ARM64_INS_SUB, |
| 13737 | #ifndef CAPSTONE_DIET |
| 13738 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13739 | #endif |
| 13740 | }, |
| 13741 | { |
| 13742 | AArch64_SUBwww_uxth, ARM64_INS_SUB, |
| 13743 | #ifndef CAPSTONE_DIET |
| 13744 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13745 | #endif |
| 13746 | }, |
| 13747 | { |
| 13748 | AArch64_SUBwww_uxtw, ARM64_INS_SUB, |
| 13749 | #ifndef CAPSTONE_DIET |
| 13750 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13751 | #endif |
| 13752 | }, |
| 13753 | { |
| 13754 | AArch64_SUBwww_uxtx, ARM64_INS_SUB, |
| 13755 | #ifndef CAPSTONE_DIET |
| 13756 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13757 | #endif |
| 13758 | }, |
| 13759 | { |
| 13760 | AArch64_SUBxxi_lsl0_S, ARM64_INS_SUB, |
| 13761 | #ifndef CAPSTONE_DIET |
| 13762 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13763 | #endif |
| 13764 | }, |
| 13765 | { |
| 13766 | AArch64_SUBxxi_lsl0_cmp, ARM64_INS_CMP, |
| 13767 | #ifndef CAPSTONE_DIET |
| 13768 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13769 | #endif |
| 13770 | }, |
| 13771 | { |
| 13772 | AArch64_SUBxxi_lsl0_s, ARM64_INS_SUB, |
| 13773 | #ifndef CAPSTONE_DIET |
| 13774 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13775 | #endif |
| 13776 | }, |
| 13777 | { |
| 13778 | AArch64_SUBxxi_lsl12_S, ARM64_INS_SUB, |
| 13779 | #ifndef CAPSTONE_DIET |
| 13780 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13781 | #endif |
| 13782 | }, |
| 13783 | { |
| 13784 | AArch64_SUBxxi_lsl12_cmp, ARM64_INS_CMP, |
| 13785 | #ifndef CAPSTONE_DIET |
| 13786 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 13787 | #endif |
| 13788 | }, |
| 13789 | { |
| 13790 | AArch64_SUBxxi_lsl12_s, ARM64_INS_SUB, |
| 13791 | #ifndef CAPSTONE_DIET |
| 13792 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13793 | #endif |
| 13794 | }, |
| 13795 | { |
| 13796 | AArch64_SUBxxw_sxtb, ARM64_INS_SUB, |
| 13797 | #ifndef CAPSTONE_DIET |
| 13798 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13799 | #endif |
| 13800 | }, |
| 13801 | { |
| 13802 | AArch64_SUBxxw_sxth, ARM64_INS_SUB, |
| 13803 | #ifndef CAPSTONE_DIET |
| 13804 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13805 | #endif |
| 13806 | }, |
| 13807 | { |
| 13808 | AArch64_SUBxxw_sxtw, ARM64_INS_SUB, |
| 13809 | #ifndef CAPSTONE_DIET |
| 13810 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13811 | #endif |
| 13812 | }, |
| 13813 | { |
| 13814 | AArch64_SUBxxw_uxtb, ARM64_INS_SUB, |
| 13815 | #ifndef CAPSTONE_DIET |
| 13816 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13817 | #endif |
| 13818 | }, |
| 13819 | { |
| 13820 | AArch64_SUBxxw_uxth, ARM64_INS_SUB, |
| 13821 | #ifndef CAPSTONE_DIET |
| 13822 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13823 | #endif |
| 13824 | }, |
| 13825 | { |
| 13826 | AArch64_SUBxxw_uxtw, ARM64_INS_SUB, |
| 13827 | #ifndef CAPSTONE_DIET |
| 13828 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13829 | #endif |
| 13830 | }, |
| 13831 | { |
| 13832 | AArch64_SUBxxx_asr, ARM64_INS_SUB, |
| 13833 | #ifndef CAPSTONE_DIET |
| 13834 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13835 | #endif |
| 13836 | }, |
| 13837 | { |
| 13838 | AArch64_SUBxxx_lsl, ARM64_INS_SUB, |
| 13839 | #ifndef CAPSTONE_DIET |
| 13840 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13841 | #endif |
| 13842 | }, |
| 13843 | { |
| 13844 | AArch64_SUBxxx_lsr, ARM64_INS_SUB, |
| 13845 | #ifndef CAPSTONE_DIET |
| 13846 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13847 | #endif |
| 13848 | }, |
| 13849 | { |
| 13850 | AArch64_SUBxxx_sxtx, ARM64_INS_SUB, |
| 13851 | #ifndef CAPSTONE_DIET |
| 13852 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13853 | #endif |
| 13854 | }, |
| 13855 | { |
| 13856 | AArch64_SUBxxx_uxtx, ARM64_INS_SUB, |
| 13857 | #ifndef CAPSTONE_DIET |
| 13858 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13859 | #endif |
| 13860 | }, |
| 13861 | { |
| 13862 | AArch64_SUQADD16b, ARM64_INS_SUQADD, |
| 13863 | #ifndef CAPSTONE_DIET |
| 13864 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13865 | #endif |
| 13866 | }, |
| 13867 | { |
| 13868 | AArch64_SUQADD2d, ARM64_INS_SUQADD, |
| 13869 | #ifndef CAPSTONE_DIET |
| 13870 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13871 | #endif |
| 13872 | }, |
| 13873 | { |
| 13874 | AArch64_SUQADD2s, ARM64_INS_SUQADD, |
| 13875 | #ifndef CAPSTONE_DIET |
| 13876 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13877 | #endif |
| 13878 | }, |
| 13879 | { |
| 13880 | AArch64_SUQADD4h, ARM64_INS_SUQADD, |
| 13881 | #ifndef CAPSTONE_DIET |
| 13882 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13883 | #endif |
| 13884 | }, |
| 13885 | { |
| 13886 | AArch64_SUQADD4s, ARM64_INS_SUQADD, |
| 13887 | #ifndef CAPSTONE_DIET |
| 13888 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13889 | #endif |
| 13890 | }, |
| 13891 | { |
| 13892 | AArch64_SUQADD8b, ARM64_INS_SUQADD, |
| 13893 | #ifndef CAPSTONE_DIET |
| 13894 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13895 | #endif |
| 13896 | }, |
| 13897 | { |
| 13898 | AArch64_SUQADD8h, ARM64_INS_SUQADD, |
| 13899 | #ifndef CAPSTONE_DIET |
| 13900 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13901 | #endif |
| 13902 | }, |
| 13903 | { |
| 13904 | AArch64_SUQADDbb, ARM64_INS_SUQADD, |
| 13905 | #ifndef CAPSTONE_DIET |
| 13906 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13907 | #endif |
| 13908 | }, |
| 13909 | { |
| 13910 | AArch64_SUQADDdd, ARM64_INS_SUQADD, |
| 13911 | #ifndef CAPSTONE_DIET |
| 13912 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13913 | #endif |
| 13914 | }, |
| 13915 | { |
| 13916 | AArch64_SUQADDhh, ARM64_INS_SUQADD, |
| 13917 | #ifndef CAPSTONE_DIET |
| 13918 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13919 | #endif |
| 13920 | }, |
| 13921 | { |
| 13922 | AArch64_SUQADDss, ARM64_INS_SUQADD, |
| 13923 | #ifndef CAPSTONE_DIET |
| 13924 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13925 | #endif |
| 13926 | }, |
| 13927 | { |
| 13928 | AArch64_SVCi, ARM64_INS_SVC, |
| 13929 | #ifndef CAPSTONE_DIET |
| 13930 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 13931 | #endif |
| 13932 | }, |
| 13933 | { |
| 13934 | AArch64_SXTBww, ARM64_INS_SXTB, |
| 13935 | #ifndef CAPSTONE_DIET |
| 13936 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13937 | #endif |
| 13938 | }, |
| 13939 | { |
| 13940 | AArch64_SXTBxw, ARM64_INS_SXTB, |
| 13941 | #ifndef CAPSTONE_DIET |
| 13942 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13943 | #endif |
| 13944 | }, |
| 13945 | { |
| 13946 | AArch64_SXTHww, ARM64_INS_SXTH, |
| 13947 | #ifndef CAPSTONE_DIET |
| 13948 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13949 | #endif |
| 13950 | }, |
| 13951 | { |
| 13952 | AArch64_SXTHxw, ARM64_INS_SXTH, |
| 13953 | #ifndef CAPSTONE_DIET |
| 13954 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13955 | #endif |
| 13956 | }, |
| 13957 | { |
| 13958 | AArch64_SXTWxw, ARM64_INS_SXTW, |
| 13959 | #ifndef CAPSTONE_DIET |
| 13960 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13961 | #endif |
| 13962 | }, |
| 13963 | { |
| 13964 | AArch64_SYSLxicci, ARM64_INS_SYSL, |
| 13965 | #ifndef CAPSTONE_DIET |
| 13966 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13967 | #endif |
| 13968 | }, |
| 13969 | { |
| 13970 | AArch64_SYSiccix, ARM64_INS_SYS, |
| 13971 | #ifndef CAPSTONE_DIET |
| 13972 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 13973 | #endif |
| 13974 | }, |
| 13975 | { |
| 13976 | AArch64_TBL1_16b, ARM64_INS_TBL, |
| 13977 | #ifndef CAPSTONE_DIET |
| 13978 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13979 | #endif |
| 13980 | }, |
| 13981 | { |
| 13982 | AArch64_TBL1_8b, ARM64_INS_TBL, |
| 13983 | #ifndef CAPSTONE_DIET |
| 13984 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13985 | #endif |
| 13986 | }, |
| 13987 | { |
| 13988 | AArch64_TBL2_16b, ARM64_INS_TBL, |
| 13989 | #ifndef CAPSTONE_DIET |
| 13990 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13991 | #endif |
| 13992 | }, |
| 13993 | { |
| 13994 | AArch64_TBL2_8b, ARM64_INS_TBL, |
| 13995 | #ifndef CAPSTONE_DIET |
| 13996 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 13997 | #endif |
| 13998 | }, |
| 13999 | { |
| 14000 | AArch64_TBL3_16b, ARM64_INS_TBL, |
| 14001 | #ifndef CAPSTONE_DIET |
| 14002 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14003 | #endif |
| 14004 | }, |
| 14005 | { |
| 14006 | AArch64_TBL3_8b, ARM64_INS_TBL, |
| 14007 | #ifndef CAPSTONE_DIET |
| 14008 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14009 | #endif |
| 14010 | }, |
| 14011 | { |
| 14012 | AArch64_TBL4_16b, ARM64_INS_TBL, |
| 14013 | #ifndef CAPSTONE_DIET |
| 14014 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14015 | #endif |
| 14016 | }, |
| 14017 | { |
| 14018 | AArch64_TBL4_8b, ARM64_INS_TBL, |
| 14019 | #ifndef CAPSTONE_DIET |
| 14020 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14021 | #endif |
| 14022 | }, |
| 14023 | { |
| 14024 | AArch64_TBNZwii, ARM64_INS_TBNZ, |
| 14025 | #ifndef CAPSTONE_DIET |
| 14026 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 14027 | #endif |
| 14028 | }, |
| 14029 | { |
| 14030 | AArch64_TBNZxii, ARM64_INS_TBNZ, |
| 14031 | #ifndef CAPSTONE_DIET |
| 14032 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 14033 | #endif |
| 14034 | }, |
| 14035 | { |
| 14036 | AArch64_TBX1_16b, ARM64_INS_TBX, |
| 14037 | #ifndef CAPSTONE_DIET |
| 14038 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14039 | #endif |
| 14040 | }, |
| 14041 | { |
| 14042 | AArch64_TBX1_8b, ARM64_INS_TBX, |
| 14043 | #ifndef CAPSTONE_DIET |
| 14044 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14045 | #endif |
| 14046 | }, |
| 14047 | { |
| 14048 | AArch64_TBX2_16b, ARM64_INS_TBX, |
| 14049 | #ifndef CAPSTONE_DIET |
| 14050 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14051 | #endif |
| 14052 | }, |
| 14053 | { |
| 14054 | AArch64_TBX2_8b, ARM64_INS_TBX, |
| 14055 | #ifndef CAPSTONE_DIET |
| 14056 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14057 | #endif |
| 14058 | }, |
| 14059 | { |
| 14060 | AArch64_TBX3_16b, ARM64_INS_TBX, |
| 14061 | #ifndef CAPSTONE_DIET |
| 14062 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14063 | #endif |
| 14064 | }, |
| 14065 | { |
| 14066 | AArch64_TBX3_8b, ARM64_INS_TBX, |
| 14067 | #ifndef CAPSTONE_DIET |
| 14068 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14069 | #endif |
| 14070 | }, |
| 14071 | { |
| 14072 | AArch64_TBX4_16b, ARM64_INS_TBX, |
| 14073 | #ifndef CAPSTONE_DIET |
| 14074 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14075 | #endif |
| 14076 | }, |
| 14077 | { |
| 14078 | AArch64_TBX4_8b, ARM64_INS_TBX, |
| 14079 | #ifndef CAPSTONE_DIET |
| 14080 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14081 | #endif |
| 14082 | }, |
| 14083 | { |
| 14084 | AArch64_TBZwii, ARM64_INS_TBZ, |
| 14085 | #ifndef CAPSTONE_DIET |
| 14086 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 14087 | #endif |
| 14088 | }, |
| 14089 | { |
| 14090 | AArch64_TBZxii, ARM64_INS_TBZ, |
| 14091 | #ifndef CAPSTONE_DIET |
| 14092 | { 0 }, { 0 }, { 0 }, 1, 0 |
| 14093 | #endif |
| 14094 | }, |
| 14095 | { |
| 14096 | AArch64_TLBIi, ARM64_INS_TLBI, |
| 14097 | #ifndef CAPSTONE_DIET |
| 14098 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14099 | #endif |
| 14100 | }, |
| 14101 | { |
| 14102 | AArch64_TLBIix, ARM64_INS_TLBI, |
| 14103 | #ifndef CAPSTONE_DIET |
| 14104 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14105 | #endif |
| 14106 | }, |
| 14107 | { |
| 14108 | AArch64_TRN1vvv_16b, ARM64_INS_TRN1, |
| 14109 | #ifndef CAPSTONE_DIET |
| 14110 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14111 | #endif |
| 14112 | }, |
| 14113 | { |
| 14114 | AArch64_TRN1vvv_2d, ARM64_INS_TRN1, |
| 14115 | #ifndef CAPSTONE_DIET |
| 14116 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14117 | #endif |
| 14118 | }, |
| 14119 | { |
| 14120 | AArch64_TRN1vvv_2s, ARM64_INS_TRN1, |
| 14121 | #ifndef CAPSTONE_DIET |
| 14122 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14123 | #endif |
| 14124 | }, |
| 14125 | { |
| 14126 | AArch64_TRN1vvv_4h, ARM64_INS_TRN1, |
| 14127 | #ifndef CAPSTONE_DIET |
| 14128 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14129 | #endif |
| 14130 | }, |
| 14131 | { |
| 14132 | AArch64_TRN1vvv_4s, ARM64_INS_TRN1, |
| 14133 | #ifndef CAPSTONE_DIET |
| 14134 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14135 | #endif |
| 14136 | }, |
| 14137 | { |
| 14138 | AArch64_TRN1vvv_8b, ARM64_INS_TRN1, |
| 14139 | #ifndef CAPSTONE_DIET |
| 14140 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14141 | #endif |
| 14142 | }, |
| 14143 | { |
| 14144 | AArch64_TRN1vvv_8h, ARM64_INS_TRN1, |
| 14145 | #ifndef CAPSTONE_DIET |
| 14146 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14147 | #endif |
| 14148 | }, |
| 14149 | { |
| 14150 | AArch64_TRN2vvv_16b, ARM64_INS_TRN2, |
| 14151 | #ifndef CAPSTONE_DIET |
| 14152 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14153 | #endif |
| 14154 | }, |
| 14155 | { |
| 14156 | AArch64_TRN2vvv_2d, ARM64_INS_TRN2, |
| 14157 | #ifndef CAPSTONE_DIET |
| 14158 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14159 | #endif |
| 14160 | }, |
| 14161 | { |
| 14162 | AArch64_TRN2vvv_2s, ARM64_INS_TRN2, |
| 14163 | #ifndef CAPSTONE_DIET |
| 14164 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14165 | #endif |
| 14166 | }, |
| 14167 | { |
| 14168 | AArch64_TRN2vvv_4h, ARM64_INS_TRN2, |
| 14169 | #ifndef CAPSTONE_DIET |
| 14170 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14171 | #endif |
| 14172 | }, |
| 14173 | { |
| 14174 | AArch64_TRN2vvv_4s, ARM64_INS_TRN2, |
| 14175 | #ifndef CAPSTONE_DIET |
| 14176 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14177 | #endif |
| 14178 | }, |
| 14179 | { |
| 14180 | AArch64_TRN2vvv_8b, ARM64_INS_TRN2, |
| 14181 | #ifndef CAPSTONE_DIET |
| 14182 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14183 | #endif |
| 14184 | }, |
| 14185 | { |
| 14186 | AArch64_TRN2vvv_8h, ARM64_INS_TRN2, |
| 14187 | #ifndef CAPSTONE_DIET |
| 14188 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14189 | #endif |
| 14190 | }, |
| 14191 | { |
| 14192 | AArch64_TSTww_asr, ARM64_INS_TST, |
| 14193 | #ifndef CAPSTONE_DIET |
| 14194 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 14195 | #endif |
| 14196 | }, |
| 14197 | { |
| 14198 | AArch64_TSTww_lsl, ARM64_INS_TST, |
| 14199 | #ifndef CAPSTONE_DIET |
| 14200 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 14201 | #endif |
| 14202 | }, |
| 14203 | { |
| 14204 | AArch64_TSTww_lsr, ARM64_INS_TST, |
| 14205 | #ifndef CAPSTONE_DIET |
| 14206 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 14207 | #endif |
| 14208 | }, |
| 14209 | { |
| 14210 | AArch64_TSTww_ror, ARM64_INS_TST, |
| 14211 | #ifndef CAPSTONE_DIET |
| 14212 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 14213 | #endif |
| 14214 | }, |
| 14215 | { |
| 14216 | AArch64_TSTxx_asr, ARM64_INS_TST, |
| 14217 | #ifndef CAPSTONE_DIET |
| 14218 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 14219 | #endif |
| 14220 | }, |
| 14221 | { |
| 14222 | AArch64_TSTxx_lsl, ARM64_INS_TST, |
| 14223 | #ifndef CAPSTONE_DIET |
| 14224 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 14225 | #endif |
| 14226 | }, |
| 14227 | { |
| 14228 | AArch64_TSTxx_lsr, ARM64_INS_TST, |
| 14229 | #ifndef CAPSTONE_DIET |
| 14230 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 14231 | #endif |
| 14232 | }, |
| 14233 | { |
| 14234 | AArch64_TSTxx_ror, ARM64_INS_TST, |
| 14235 | #ifndef CAPSTONE_DIET |
| 14236 | { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| 14237 | #endif |
| 14238 | }, |
| 14239 | { |
| 14240 | AArch64_UABAL2vvv_2d2s, ARM64_INS_UABAL2, |
| 14241 | #ifndef CAPSTONE_DIET |
| 14242 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14243 | #endif |
| 14244 | }, |
| 14245 | { |
| 14246 | AArch64_UABAL2vvv_4s4h, ARM64_INS_UABAL2, |
| 14247 | #ifndef CAPSTONE_DIET |
| 14248 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14249 | #endif |
| 14250 | }, |
| 14251 | { |
| 14252 | AArch64_UABAL2vvv_8h8b, ARM64_INS_UABAL2, |
| 14253 | #ifndef CAPSTONE_DIET |
| 14254 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14255 | #endif |
| 14256 | }, |
| 14257 | { |
| 14258 | AArch64_UABALvvv_2d2s, ARM64_INS_UABAL, |
| 14259 | #ifndef CAPSTONE_DIET |
| 14260 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14261 | #endif |
| 14262 | }, |
| 14263 | { |
| 14264 | AArch64_UABALvvv_4s4h, ARM64_INS_UABAL, |
| 14265 | #ifndef CAPSTONE_DIET |
| 14266 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14267 | #endif |
| 14268 | }, |
| 14269 | { |
| 14270 | AArch64_UABALvvv_8h8b, ARM64_INS_UABAL, |
| 14271 | #ifndef CAPSTONE_DIET |
| 14272 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14273 | #endif |
| 14274 | }, |
| 14275 | { |
| 14276 | AArch64_UABAvvv_16B, ARM64_INS_UABA, |
| 14277 | #ifndef CAPSTONE_DIET |
| 14278 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14279 | #endif |
| 14280 | }, |
| 14281 | { |
| 14282 | AArch64_UABAvvv_2S, ARM64_INS_UABA, |
| 14283 | #ifndef CAPSTONE_DIET |
| 14284 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14285 | #endif |
| 14286 | }, |
| 14287 | { |
| 14288 | AArch64_UABAvvv_4H, ARM64_INS_UABA, |
| 14289 | #ifndef CAPSTONE_DIET |
| 14290 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14291 | #endif |
| 14292 | }, |
| 14293 | { |
| 14294 | AArch64_UABAvvv_4S, ARM64_INS_UABA, |
| 14295 | #ifndef CAPSTONE_DIET |
| 14296 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14297 | #endif |
| 14298 | }, |
| 14299 | { |
| 14300 | AArch64_UABAvvv_8B, ARM64_INS_UABA, |
| 14301 | #ifndef CAPSTONE_DIET |
| 14302 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14303 | #endif |
| 14304 | }, |
| 14305 | { |
| 14306 | AArch64_UABAvvv_8H, ARM64_INS_UABA, |
| 14307 | #ifndef CAPSTONE_DIET |
| 14308 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14309 | #endif |
| 14310 | }, |
| 14311 | { |
| 14312 | AArch64_UABDL2vvv_2d2s, ARM64_INS_UABDL2, |
| 14313 | #ifndef CAPSTONE_DIET |
| 14314 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14315 | #endif |
| 14316 | }, |
| 14317 | { |
| 14318 | AArch64_UABDL2vvv_4s4h, ARM64_INS_UABDL2, |
| 14319 | #ifndef CAPSTONE_DIET |
| 14320 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14321 | #endif |
| 14322 | }, |
| 14323 | { |
| 14324 | AArch64_UABDL2vvv_8h8b, ARM64_INS_UABDL2, |
| 14325 | #ifndef CAPSTONE_DIET |
| 14326 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14327 | #endif |
| 14328 | }, |
| 14329 | { |
| 14330 | AArch64_UABDLvvv_2d2s, ARM64_INS_UABDL, |
| 14331 | #ifndef CAPSTONE_DIET |
| 14332 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14333 | #endif |
| 14334 | }, |
| 14335 | { |
| 14336 | AArch64_UABDLvvv_4s4h, ARM64_INS_UABDL, |
| 14337 | #ifndef CAPSTONE_DIET |
| 14338 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14339 | #endif |
| 14340 | }, |
| 14341 | { |
| 14342 | AArch64_UABDLvvv_8h8b, ARM64_INS_UABDL, |
| 14343 | #ifndef CAPSTONE_DIET |
| 14344 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14345 | #endif |
| 14346 | }, |
| 14347 | { |
| 14348 | AArch64_UABDvvv_16B, ARM64_INS_UABD, |
| 14349 | #ifndef CAPSTONE_DIET |
| 14350 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14351 | #endif |
| 14352 | }, |
| 14353 | { |
| 14354 | AArch64_UABDvvv_2S, ARM64_INS_UABD, |
| 14355 | #ifndef CAPSTONE_DIET |
| 14356 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14357 | #endif |
| 14358 | }, |
| 14359 | { |
| 14360 | AArch64_UABDvvv_4H, ARM64_INS_UABD, |
| 14361 | #ifndef CAPSTONE_DIET |
| 14362 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14363 | #endif |
| 14364 | }, |
| 14365 | { |
| 14366 | AArch64_UABDvvv_4S, ARM64_INS_UABD, |
| 14367 | #ifndef CAPSTONE_DIET |
| 14368 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14369 | #endif |
| 14370 | }, |
| 14371 | { |
| 14372 | AArch64_UABDvvv_8B, ARM64_INS_UABD, |
| 14373 | #ifndef CAPSTONE_DIET |
| 14374 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14375 | #endif |
| 14376 | }, |
| 14377 | { |
| 14378 | AArch64_UABDvvv_8H, ARM64_INS_UABD, |
| 14379 | #ifndef CAPSTONE_DIET |
| 14380 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14381 | #endif |
| 14382 | }, |
| 14383 | { |
| 14384 | AArch64_UADALP16b8h, ARM64_INS_UADALP, |
| 14385 | #ifndef CAPSTONE_DIET |
| 14386 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14387 | #endif |
| 14388 | }, |
| 14389 | { |
| 14390 | AArch64_UADALP2s1d, ARM64_INS_UADALP, |
| 14391 | #ifndef CAPSTONE_DIET |
| 14392 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14393 | #endif |
| 14394 | }, |
| 14395 | { |
| 14396 | AArch64_UADALP4h2s, ARM64_INS_UADALP, |
| 14397 | #ifndef CAPSTONE_DIET |
| 14398 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14399 | #endif |
| 14400 | }, |
| 14401 | { |
| 14402 | AArch64_UADALP4s2d, ARM64_INS_UADALP, |
| 14403 | #ifndef CAPSTONE_DIET |
| 14404 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14405 | #endif |
| 14406 | }, |
| 14407 | { |
| 14408 | AArch64_UADALP8b4h, ARM64_INS_UADALP, |
| 14409 | #ifndef CAPSTONE_DIET |
| 14410 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14411 | #endif |
| 14412 | }, |
| 14413 | { |
| 14414 | AArch64_UADALP8h4s, ARM64_INS_UADALP, |
| 14415 | #ifndef CAPSTONE_DIET |
| 14416 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14417 | #endif |
| 14418 | }, |
| 14419 | { |
| 14420 | AArch64_UADDL2vvv_2d4s, ARM64_INS_UADDL2, |
| 14421 | #ifndef CAPSTONE_DIET |
| 14422 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14423 | #endif |
| 14424 | }, |
| 14425 | { |
| 14426 | AArch64_UADDL2vvv_4s8h, ARM64_INS_UADDL2, |
| 14427 | #ifndef CAPSTONE_DIET |
| 14428 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14429 | #endif |
| 14430 | }, |
| 14431 | { |
| 14432 | AArch64_UADDL2vvv_8h16b, ARM64_INS_UADDL2, |
| 14433 | #ifndef CAPSTONE_DIET |
| 14434 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14435 | #endif |
| 14436 | }, |
| 14437 | { |
| 14438 | AArch64_UADDLP16b8h, ARM64_INS_UADDLP, |
| 14439 | #ifndef CAPSTONE_DIET |
| 14440 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14441 | #endif |
| 14442 | }, |
| 14443 | { |
| 14444 | AArch64_UADDLP2s1d, ARM64_INS_UADDLP, |
| 14445 | #ifndef CAPSTONE_DIET |
| 14446 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14447 | #endif |
| 14448 | }, |
| 14449 | { |
| 14450 | AArch64_UADDLP4h2s, ARM64_INS_UADDLP, |
| 14451 | #ifndef CAPSTONE_DIET |
| 14452 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14453 | #endif |
| 14454 | }, |
| 14455 | { |
| 14456 | AArch64_UADDLP4s2d, ARM64_INS_UADDLP, |
| 14457 | #ifndef CAPSTONE_DIET |
| 14458 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14459 | #endif |
| 14460 | }, |
| 14461 | { |
| 14462 | AArch64_UADDLP8b4h, ARM64_INS_UADDLP, |
| 14463 | #ifndef CAPSTONE_DIET |
| 14464 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14465 | #endif |
| 14466 | }, |
| 14467 | { |
| 14468 | AArch64_UADDLP8h4s, ARM64_INS_UADDLP, |
| 14469 | #ifndef CAPSTONE_DIET |
| 14470 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14471 | #endif |
| 14472 | }, |
| 14473 | { |
| 14474 | AArch64_UADDLV_1d4s, ARM64_INS_UADDLV, |
| 14475 | #ifndef CAPSTONE_DIET |
| 14476 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14477 | #endif |
| 14478 | }, |
| 14479 | { |
| 14480 | AArch64_UADDLV_1h16b, ARM64_INS_UADDLV, |
| 14481 | #ifndef CAPSTONE_DIET |
| 14482 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14483 | #endif |
| 14484 | }, |
| 14485 | { |
| 14486 | AArch64_UADDLV_1h8b, ARM64_INS_UADDLV, |
| 14487 | #ifndef CAPSTONE_DIET |
| 14488 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14489 | #endif |
| 14490 | }, |
| 14491 | { |
| 14492 | AArch64_UADDLV_1s4h, ARM64_INS_UADDLV, |
| 14493 | #ifndef CAPSTONE_DIET |
| 14494 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14495 | #endif |
| 14496 | }, |
| 14497 | { |
| 14498 | AArch64_UADDLV_1s8h, ARM64_INS_UADDLV, |
| 14499 | #ifndef CAPSTONE_DIET |
| 14500 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14501 | #endif |
| 14502 | }, |
| 14503 | { |
| 14504 | AArch64_UADDLvvv_2d2s, ARM64_INS_UADDL, |
| 14505 | #ifndef CAPSTONE_DIET |
| 14506 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14507 | #endif |
| 14508 | }, |
| 14509 | { |
| 14510 | AArch64_UADDLvvv_4s4h, ARM64_INS_UADDL, |
| 14511 | #ifndef CAPSTONE_DIET |
| 14512 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14513 | #endif |
| 14514 | }, |
| 14515 | { |
| 14516 | AArch64_UADDLvvv_8h8b, ARM64_INS_UADDL, |
| 14517 | #ifndef CAPSTONE_DIET |
| 14518 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14519 | #endif |
| 14520 | }, |
| 14521 | { |
| 14522 | AArch64_UADDW2vvv_2d4s, ARM64_INS_UADDW2, |
| 14523 | #ifndef CAPSTONE_DIET |
| 14524 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14525 | #endif |
| 14526 | }, |
| 14527 | { |
| 14528 | AArch64_UADDW2vvv_4s8h, ARM64_INS_UADDW2, |
| 14529 | #ifndef CAPSTONE_DIET |
| 14530 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14531 | #endif |
| 14532 | }, |
| 14533 | { |
| 14534 | AArch64_UADDW2vvv_8h16b, ARM64_INS_UADDW2, |
| 14535 | #ifndef CAPSTONE_DIET |
| 14536 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14537 | #endif |
| 14538 | }, |
| 14539 | { |
| 14540 | AArch64_UADDWvvv_2d2s, ARM64_INS_UADDW, |
| 14541 | #ifndef CAPSTONE_DIET |
| 14542 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14543 | #endif |
| 14544 | }, |
| 14545 | { |
| 14546 | AArch64_UADDWvvv_4s4h, ARM64_INS_UADDW, |
| 14547 | #ifndef CAPSTONE_DIET |
| 14548 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14549 | #endif |
| 14550 | }, |
| 14551 | { |
| 14552 | AArch64_UADDWvvv_8h8b, ARM64_INS_UADDW, |
| 14553 | #ifndef CAPSTONE_DIET |
| 14554 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14555 | #endif |
| 14556 | }, |
| 14557 | { |
| 14558 | AArch64_UBFIZwwii, ARM64_INS_UBFIZ, |
| 14559 | #ifndef CAPSTONE_DIET |
| 14560 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14561 | #endif |
| 14562 | }, |
| 14563 | { |
| 14564 | AArch64_UBFIZxxii, ARM64_INS_UBFIZ, |
| 14565 | #ifndef CAPSTONE_DIET |
| 14566 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14567 | #endif |
| 14568 | }, |
| 14569 | { |
| 14570 | AArch64_UBFMwwii, ARM64_INS_UBFM, |
| 14571 | #ifndef CAPSTONE_DIET |
| 14572 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14573 | #endif |
| 14574 | }, |
| 14575 | { |
| 14576 | AArch64_UBFMxxii, ARM64_INS_UBFM, |
| 14577 | #ifndef CAPSTONE_DIET |
| 14578 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14579 | #endif |
| 14580 | }, |
| 14581 | { |
| 14582 | AArch64_UBFXwwii, ARM64_INS_UBFX, |
| 14583 | #ifndef CAPSTONE_DIET |
| 14584 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14585 | #endif |
| 14586 | }, |
| 14587 | { |
| 14588 | AArch64_UBFXxxii, ARM64_INS_UBFX, |
| 14589 | #ifndef CAPSTONE_DIET |
| 14590 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14591 | #endif |
| 14592 | }, |
| 14593 | { |
| 14594 | AArch64_UCVTF_2d, ARM64_INS_UCVTF, |
| 14595 | #ifndef CAPSTONE_DIET |
| 14596 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14597 | #endif |
| 14598 | }, |
| 14599 | { |
| 14600 | AArch64_UCVTF_2s, ARM64_INS_UCVTF, |
| 14601 | #ifndef CAPSTONE_DIET |
| 14602 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14603 | #endif |
| 14604 | }, |
| 14605 | { |
| 14606 | AArch64_UCVTF_4s, ARM64_INS_UCVTF, |
| 14607 | #ifndef CAPSTONE_DIET |
| 14608 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14609 | #endif |
| 14610 | }, |
| 14611 | { |
| 14612 | AArch64_UCVTF_Nddi, ARM64_INS_UCVTF, |
| 14613 | #ifndef CAPSTONE_DIET |
| 14614 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14615 | #endif |
| 14616 | }, |
| 14617 | { |
| 14618 | AArch64_UCVTF_Nssi, ARM64_INS_UCVTF, |
| 14619 | #ifndef CAPSTONE_DIET |
| 14620 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14621 | #endif |
| 14622 | }, |
| 14623 | { |
| 14624 | AArch64_UCVTFdd, ARM64_INS_UCVTF, |
| 14625 | #ifndef CAPSTONE_DIET |
| 14626 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14627 | #endif |
| 14628 | }, |
| 14629 | { |
| 14630 | AArch64_UCVTFdw, ARM64_INS_UCVTF, |
| 14631 | #ifndef CAPSTONE_DIET |
| 14632 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 14633 | #endif |
| 14634 | }, |
| 14635 | { |
| 14636 | AArch64_UCVTFdwi, ARM64_INS_UCVTF, |
| 14637 | #ifndef CAPSTONE_DIET |
| 14638 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 14639 | #endif |
| 14640 | }, |
| 14641 | { |
| 14642 | AArch64_UCVTFdx, ARM64_INS_UCVTF, |
| 14643 | #ifndef CAPSTONE_DIET |
| 14644 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 14645 | #endif |
| 14646 | }, |
| 14647 | { |
| 14648 | AArch64_UCVTFdxi, ARM64_INS_UCVTF, |
| 14649 | #ifndef CAPSTONE_DIET |
| 14650 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 14651 | #endif |
| 14652 | }, |
| 14653 | { |
| 14654 | AArch64_UCVTFss, ARM64_INS_UCVTF, |
| 14655 | #ifndef CAPSTONE_DIET |
| 14656 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14657 | #endif |
| 14658 | }, |
| 14659 | { |
| 14660 | AArch64_UCVTFsw, ARM64_INS_UCVTF, |
| 14661 | #ifndef CAPSTONE_DIET |
| 14662 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 14663 | #endif |
| 14664 | }, |
| 14665 | { |
| 14666 | AArch64_UCVTFswi, ARM64_INS_UCVTF, |
| 14667 | #ifndef CAPSTONE_DIET |
| 14668 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 14669 | #endif |
| 14670 | }, |
| 14671 | { |
| 14672 | AArch64_UCVTFsx, ARM64_INS_UCVTF, |
| 14673 | #ifndef CAPSTONE_DIET |
| 14674 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 14675 | #endif |
| 14676 | }, |
| 14677 | { |
| 14678 | AArch64_UCVTFsxi, ARM64_INS_UCVTF, |
| 14679 | #ifndef CAPSTONE_DIET |
| 14680 | { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| 14681 | #endif |
| 14682 | }, |
| 14683 | { |
| 14684 | AArch64_UDIVwww, ARM64_INS_UDIV, |
| 14685 | #ifndef CAPSTONE_DIET |
| 14686 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14687 | #endif |
| 14688 | }, |
| 14689 | { |
| 14690 | AArch64_UDIVxxx, ARM64_INS_UDIV, |
| 14691 | #ifndef CAPSTONE_DIET |
| 14692 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14693 | #endif |
| 14694 | }, |
| 14695 | { |
| 14696 | AArch64_UHADDvvv_16B, ARM64_INS_UHADD, |
| 14697 | #ifndef CAPSTONE_DIET |
| 14698 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14699 | #endif |
| 14700 | }, |
| 14701 | { |
| 14702 | AArch64_UHADDvvv_2S, ARM64_INS_UHADD, |
| 14703 | #ifndef CAPSTONE_DIET |
| 14704 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14705 | #endif |
| 14706 | }, |
| 14707 | { |
| 14708 | AArch64_UHADDvvv_4H, ARM64_INS_UHADD, |
| 14709 | #ifndef CAPSTONE_DIET |
| 14710 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14711 | #endif |
| 14712 | }, |
| 14713 | { |
| 14714 | AArch64_UHADDvvv_4S, ARM64_INS_UHADD, |
| 14715 | #ifndef CAPSTONE_DIET |
| 14716 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14717 | #endif |
| 14718 | }, |
| 14719 | { |
| 14720 | AArch64_UHADDvvv_8B, ARM64_INS_UHADD, |
| 14721 | #ifndef CAPSTONE_DIET |
| 14722 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14723 | #endif |
| 14724 | }, |
| 14725 | { |
| 14726 | AArch64_UHADDvvv_8H, ARM64_INS_UHADD, |
| 14727 | #ifndef CAPSTONE_DIET |
| 14728 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14729 | #endif |
| 14730 | }, |
| 14731 | { |
| 14732 | AArch64_UHSUBvvv_16B, ARM64_INS_UHSUB, |
| 14733 | #ifndef CAPSTONE_DIET |
| 14734 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14735 | #endif |
| 14736 | }, |
| 14737 | { |
| 14738 | AArch64_UHSUBvvv_2S, ARM64_INS_UHSUB, |
| 14739 | #ifndef CAPSTONE_DIET |
| 14740 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14741 | #endif |
| 14742 | }, |
| 14743 | { |
| 14744 | AArch64_UHSUBvvv_4H, ARM64_INS_UHSUB, |
| 14745 | #ifndef CAPSTONE_DIET |
| 14746 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14747 | #endif |
| 14748 | }, |
| 14749 | { |
| 14750 | AArch64_UHSUBvvv_4S, ARM64_INS_UHSUB, |
| 14751 | #ifndef CAPSTONE_DIET |
| 14752 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14753 | #endif |
| 14754 | }, |
| 14755 | { |
| 14756 | AArch64_UHSUBvvv_8B, ARM64_INS_UHSUB, |
| 14757 | #ifndef CAPSTONE_DIET |
| 14758 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14759 | #endif |
| 14760 | }, |
| 14761 | { |
| 14762 | AArch64_UHSUBvvv_8H, ARM64_INS_UHSUB, |
| 14763 | #ifndef CAPSTONE_DIET |
| 14764 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14765 | #endif |
| 14766 | }, |
| 14767 | { |
| 14768 | AArch64_UMADDLxwwx, ARM64_INS_UMADDL, |
| 14769 | #ifndef CAPSTONE_DIET |
| 14770 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 14771 | #endif |
| 14772 | }, |
| 14773 | { |
| 14774 | AArch64_UMAXPvvv_16B, ARM64_INS_UMAXP, |
| 14775 | #ifndef CAPSTONE_DIET |
| 14776 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14777 | #endif |
| 14778 | }, |
| 14779 | { |
| 14780 | AArch64_UMAXPvvv_2S, ARM64_INS_UMAXP, |
| 14781 | #ifndef CAPSTONE_DIET |
| 14782 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14783 | #endif |
| 14784 | }, |
| 14785 | { |
| 14786 | AArch64_UMAXPvvv_4H, ARM64_INS_UMAXP, |
| 14787 | #ifndef CAPSTONE_DIET |
| 14788 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14789 | #endif |
| 14790 | }, |
| 14791 | { |
| 14792 | AArch64_UMAXPvvv_4S, ARM64_INS_UMAXP, |
| 14793 | #ifndef CAPSTONE_DIET |
| 14794 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14795 | #endif |
| 14796 | }, |
| 14797 | { |
| 14798 | AArch64_UMAXPvvv_8B, ARM64_INS_UMAXP, |
| 14799 | #ifndef CAPSTONE_DIET |
| 14800 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14801 | #endif |
| 14802 | }, |
| 14803 | { |
| 14804 | AArch64_UMAXPvvv_8H, ARM64_INS_UMAXP, |
| 14805 | #ifndef CAPSTONE_DIET |
| 14806 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14807 | #endif |
| 14808 | }, |
| 14809 | { |
| 14810 | AArch64_UMAXV_1b16b, ARM64_INS_UMAXV, |
| 14811 | #ifndef CAPSTONE_DIET |
| 14812 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14813 | #endif |
| 14814 | }, |
| 14815 | { |
| 14816 | AArch64_UMAXV_1b8b, ARM64_INS_UMAXV, |
| 14817 | #ifndef CAPSTONE_DIET |
| 14818 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14819 | #endif |
| 14820 | }, |
| 14821 | { |
| 14822 | AArch64_UMAXV_1h4h, ARM64_INS_UMAXV, |
| 14823 | #ifndef CAPSTONE_DIET |
| 14824 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14825 | #endif |
| 14826 | }, |
| 14827 | { |
| 14828 | AArch64_UMAXV_1h8h, ARM64_INS_UMAXV, |
| 14829 | #ifndef CAPSTONE_DIET |
| 14830 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14831 | #endif |
| 14832 | }, |
| 14833 | { |
| 14834 | AArch64_UMAXV_1s4s, ARM64_INS_UMAXV, |
| 14835 | #ifndef CAPSTONE_DIET |
| 14836 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14837 | #endif |
| 14838 | }, |
| 14839 | { |
| 14840 | AArch64_UMAXvvv_16B, ARM64_INS_UMAX, |
| 14841 | #ifndef CAPSTONE_DIET |
| 14842 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14843 | #endif |
| 14844 | }, |
| 14845 | { |
| 14846 | AArch64_UMAXvvv_2S, ARM64_INS_UMAX, |
| 14847 | #ifndef CAPSTONE_DIET |
| 14848 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14849 | #endif |
| 14850 | }, |
| 14851 | { |
| 14852 | AArch64_UMAXvvv_4H, ARM64_INS_UMAX, |
| 14853 | #ifndef CAPSTONE_DIET |
| 14854 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14855 | #endif |
| 14856 | }, |
| 14857 | { |
| 14858 | AArch64_UMAXvvv_4S, ARM64_INS_UMAX, |
| 14859 | #ifndef CAPSTONE_DIET |
| 14860 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14861 | #endif |
| 14862 | }, |
| 14863 | { |
| 14864 | AArch64_UMAXvvv_8B, ARM64_INS_UMAX, |
| 14865 | #ifndef CAPSTONE_DIET |
| 14866 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14867 | #endif |
| 14868 | }, |
| 14869 | { |
| 14870 | AArch64_UMAXvvv_8H, ARM64_INS_UMAX, |
| 14871 | #ifndef CAPSTONE_DIET |
| 14872 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14873 | #endif |
| 14874 | }, |
| 14875 | { |
| 14876 | AArch64_UMINPvvv_16B, ARM64_INS_UMINP, |
| 14877 | #ifndef CAPSTONE_DIET |
| 14878 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14879 | #endif |
| 14880 | }, |
| 14881 | { |
| 14882 | AArch64_UMINPvvv_2S, ARM64_INS_UMINP, |
| 14883 | #ifndef CAPSTONE_DIET |
| 14884 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14885 | #endif |
| 14886 | }, |
| 14887 | { |
| 14888 | AArch64_UMINPvvv_4H, ARM64_INS_UMINP, |
| 14889 | #ifndef CAPSTONE_DIET |
| 14890 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14891 | #endif |
| 14892 | }, |
| 14893 | { |
| 14894 | AArch64_UMINPvvv_4S, ARM64_INS_UMINP, |
| 14895 | #ifndef CAPSTONE_DIET |
| 14896 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14897 | #endif |
| 14898 | }, |
| 14899 | { |
| 14900 | AArch64_UMINPvvv_8B, ARM64_INS_UMINP, |
| 14901 | #ifndef CAPSTONE_DIET |
| 14902 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14903 | #endif |
| 14904 | }, |
| 14905 | { |
| 14906 | AArch64_UMINPvvv_8H, ARM64_INS_UMINP, |
| 14907 | #ifndef CAPSTONE_DIET |
| 14908 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14909 | #endif |
| 14910 | }, |
| 14911 | { |
| 14912 | AArch64_UMINV_1b16b, ARM64_INS_UMINV, |
| 14913 | #ifndef CAPSTONE_DIET |
| 14914 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14915 | #endif |
| 14916 | }, |
| 14917 | { |
| 14918 | AArch64_UMINV_1b8b, ARM64_INS_UMINV, |
| 14919 | #ifndef CAPSTONE_DIET |
| 14920 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14921 | #endif |
| 14922 | }, |
| 14923 | { |
| 14924 | AArch64_UMINV_1h4h, ARM64_INS_UMINV, |
| 14925 | #ifndef CAPSTONE_DIET |
| 14926 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14927 | #endif |
| 14928 | }, |
| 14929 | { |
| 14930 | AArch64_UMINV_1h8h, ARM64_INS_UMINV, |
| 14931 | #ifndef CAPSTONE_DIET |
| 14932 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14933 | #endif |
| 14934 | }, |
| 14935 | { |
| 14936 | AArch64_UMINV_1s4s, ARM64_INS_UMINV, |
| 14937 | #ifndef CAPSTONE_DIET |
| 14938 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14939 | #endif |
| 14940 | }, |
| 14941 | { |
| 14942 | AArch64_UMINvvv_16B, ARM64_INS_UMIN, |
| 14943 | #ifndef CAPSTONE_DIET |
| 14944 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14945 | #endif |
| 14946 | }, |
| 14947 | { |
| 14948 | AArch64_UMINvvv_2S, ARM64_INS_UMIN, |
| 14949 | #ifndef CAPSTONE_DIET |
| 14950 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14951 | #endif |
| 14952 | }, |
| 14953 | { |
| 14954 | AArch64_UMINvvv_4H, ARM64_INS_UMIN, |
| 14955 | #ifndef CAPSTONE_DIET |
| 14956 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14957 | #endif |
| 14958 | }, |
| 14959 | { |
| 14960 | AArch64_UMINvvv_4S, ARM64_INS_UMIN, |
| 14961 | #ifndef CAPSTONE_DIET |
| 14962 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14963 | #endif |
| 14964 | }, |
| 14965 | { |
| 14966 | AArch64_UMINvvv_8B, ARM64_INS_UMIN, |
| 14967 | #ifndef CAPSTONE_DIET |
| 14968 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14969 | #endif |
| 14970 | }, |
| 14971 | { |
| 14972 | AArch64_UMINvvv_8H, ARM64_INS_UMIN, |
| 14973 | #ifndef CAPSTONE_DIET |
| 14974 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14975 | #endif |
| 14976 | }, |
| 14977 | { |
| 14978 | AArch64_UMLAL2vvv_2d4s, ARM64_INS_UMLAL2, |
| 14979 | #ifndef CAPSTONE_DIET |
| 14980 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14981 | #endif |
| 14982 | }, |
| 14983 | { |
| 14984 | AArch64_UMLAL2vvv_4s8h, ARM64_INS_UMLAL2, |
| 14985 | #ifndef CAPSTONE_DIET |
| 14986 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14987 | #endif |
| 14988 | }, |
| 14989 | { |
| 14990 | AArch64_UMLAL2vvv_8h16b, ARM64_INS_UMLAL2, |
| 14991 | #ifndef CAPSTONE_DIET |
| 14992 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14993 | #endif |
| 14994 | }, |
| 14995 | { |
| 14996 | AArch64_UMLALvve_2d2s, ARM64_INS_UMLAL, |
| 14997 | #ifndef CAPSTONE_DIET |
| 14998 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 14999 | #endif |
| 15000 | }, |
| 15001 | { |
| 15002 | AArch64_UMLALvve_2d4s, ARM64_INS_UMLAL2, |
| 15003 | #ifndef CAPSTONE_DIET |
| 15004 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15005 | #endif |
| 15006 | }, |
| 15007 | { |
| 15008 | AArch64_UMLALvve_4s4h, ARM64_INS_UMLAL, |
| 15009 | #ifndef CAPSTONE_DIET |
| 15010 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15011 | #endif |
| 15012 | }, |
| 15013 | { |
| 15014 | AArch64_UMLALvve_4s8h, ARM64_INS_UMLAL2, |
| 15015 | #ifndef CAPSTONE_DIET |
| 15016 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15017 | #endif |
| 15018 | }, |
| 15019 | { |
| 15020 | AArch64_UMLALvvv_2d2s, ARM64_INS_UMLAL, |
| 15021 | #ifndef CAPSTONE_DIET |
| 15022 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15023 | #endif |
| 15024 | }, |
| 15025 | { |
| 15026 | AArch64_UMLALvvv_4s4h, ARM64_INS_UMLAL, |
| 15027 | #ifndef CAPSTONE_DIET |
| 15028 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15029 | #endif |
| 15030 | }, |
| 15031 | { |
| 15032 | AArch64_UMLALvvv_8h8b, ARM64_INS_UMLAL, |
| 15033 | #ifndef CAPSTONE_DIET |
| 15034 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15035 | #endif |
| 15036 | }, |
| 15037 | { |
| 15038 | AArch64_UMLSL2vvv_2d4s, ARM64_INS_UMLSL2, |
| 15039 | #ifndef CAPSTONE_DIET |
| 15040 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15041 | #endif |
| 15042 | }, |
| 15043 | { |
| 15044 | AArch64_UMLSL2vvv_4s8h, ARM64_INS_UMLSL2, |
| 15045 | #ifndef CAPSTONE_DIET |
| 15046 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15047 | #endif |
| 15048 | }, |
| 15049 | { |
| 15050 | AArch64_UMLSL2vvv_8h16b, ARM64_INS_UMLSL2, |
| 15051 | #ifndef CAPSTONE_DIET |
| 15052 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15053 | #endif |
| 15054 | }, |
| 15055 | { |
| 15056 | AArch64_UMLSLvve_2d2s, ARM64_INS_UMLSL, |
| 15057 | #ifndef CAPSTONE_DIET |
| 15058 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15059 | #endif |
| 15060 | }, |
| 15061 | { |
| 15062 | AArch64_UMLSLvve_2d4s, ARM64_INS_UMLSL2, |
| 15063 | #ifndef CAPSTONE_DIET |
| 15064 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15065 | #endif |
| 15066 | }, |
| 15067 | { |
| 15068 | AArch64_UMLSLvve_4s4h, ARM64_INS_UMLSL, |
| 15069 | #ifndef CAPSTONE_DIET |
| 15070 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15071 | #endif |
| 15072 | }, |
| 15073 | { |
| 15074 | AArch64_UMLSLvve_4s8h, ARM64_INS_UMLSL2, |
| 15075 | #ifndef CAPSTONE_DIET |
| 15076 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15077 | #endif |
| 15078 | }, |
| 15079 | { |
| 15080 | AArch64_UMLSLvvv_2d2s, ARM64_INS_UMLSL, |
| 15081 | #ifndef CAPSTONE_DIET |
| 15082 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15083 | #endif |
| 15084 | }, |
| 15085 | { |
| 15086 | AArch64_UMLSLvvv_4s4h, ARM64_INS_UMLSL, |
| 15087 | #ifndef CAPSTONE_DIET |
| 15088 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15089 | #endif |
| 15090 | }, |
| 15091 | { |
| 15092 | AArch64_UMLSLvvv_8h8b, ARM64_INS_UMLSL, |
| 15093 | #ifndef CAPSTONE_DIET |
| 15094 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15095 | #endif |
| 15096 | }, |
| 15097 | { |
| 15098 | AArch64_UMOVwb, ARM64_INS_UMOV, |
| 15099 | #ifndef CAPSTONE_DIET |
| 15100 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15101 | #endif |
| 15102 | }, |
| 15103 | { |
| 15104 | AArch64_UMOVwh, ARM64_INS_UMOV, |
| 15105 | #ifndef CAPSTONE_DIET |
| 15106 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15107 | #endif |
| 15108 | }, |
| 15109 | { |
| 15110 | AArch64_UMOVws, ARM64_INS_UMOV, |
| 15111 | #ifndef CAPSTONE_DIET |
| 15112 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15113 | #endif |
| 15114 | }, |
| 15115 | { |
| 15116 | AArch64_UMOVxd, ARM64_INS_UMOV, |
| 15117 | #ifndef CAPSTONE_DIET |
| 15118 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15119 | #endif |
| 15120 | }, |
| 15121 | { |
| 15122 | AArch64_UMSUBLxwwx, ARM64_INS_UMSUBL, |
| 15123 | #ifndef CAPSTONE_DIET |
| 15124 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 15125 | #endif |
| 15126 | }, |
| 15127 | { |
| 15128 | AArch64_UMULHxxx, ARM64_INS_UMULH, |
| 15129 | #ifndef CAPSTONE_DIET |
| 15130 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 15131 | #endif |
| 15132 | }, |
| 15133 | { |
| 15134 | AArch64_UMULL2vvv_2d4s, ARM64_INS_UMULL2, |
| 15135 | #ifndef CAPSTONE_DIET |
| 15136 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15137 | #endif |
| 15138 | }, |
| 15139 | { |
| 15140 | AArch64_UMULL2vvv_4s8h, ARM64_INS_UMULL2, |
| 15141 | #ifndef CAPSTONE_DIET |
| 15142 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15143 | #endif |
| 15144 | }, |
| 15145 | { |
| 15146 | AArch64_UMULL2vvv_8h16b, ARM64_INS_UMULL2, |
| 15147 | #ifndef CAPSTONE_DIET |
| 15148 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15149 | #endif |
| 15150 | }, |
| 15151 | { |
| 15152 | AArch64_UMULLve_2d2s, ARM64_INS_UMULL, |
| 15153 | #ifndef CAPSTONE_DIET |
| 15154 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15155 | #endif |
| 15156 | }, |
| 15157 | { |
| 15158 | AArch64_UMULLve_2d4s, ARM64_INS_UMULL2, |
| 15159 | #ifndef CAPSTONE_DIET |
| 15160 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15161 | #endif |
| 15162 | }, |
| 15163 | { |
| 15164 | AArch64_UMULLve_4s4h, ARM64_INS_UMULL, |
| 15165 | #ifndef CAPSTONE_DIET |
| 15166 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15167 | #endif |
| 15168 | }, |
| 15169 | { |
| 15170 | AArch64_UMULLve_4s8h, ARM64_INS_UMULL2, |
| 15171 | #ifndef CAPSTONE_DIET |
| 15172 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15173 | #endif |
| 15174 | }, |
| 15175 | { |
| 15176 | AArch64_UMULLvvv_2d2s, ARM64_INS_UMULL, |
| 15177 | #ifndef CAPSTONE_DIET |
| 15178 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15179 | #endif |
| 15180 | }, |
| 15181 | { |
| 15182 | AArch64_UMULLvvv_4s4h, ARM64_INS_UMULL, |
| 15183 | #ifndef CAPSTONE_DIET |
| 15184 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15185 | #endif |
| 15186 | }, |
| 15187 | { |
| 15188 | AArch64_UMULLvvv_8h8b, ARM64_INS_UMULL, |
| 15189 | #ifndef CAPSTONE_DIET |
| 15190 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15191 | #endif |
| 15192 | }, |
| 15193 | { |
| 15194 | AArch64_UQADDbbb, ARM64_INS_UQADD, |
| 15195 | #ifndef CAPSTONE_DIET |
| 15196 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15197 | #endif |
| 15198 | }, |
| 15199 | { |
| 15200 | AArch64_UQADDddd, ARM64_INS_UQADD, |
| 15201 | #ifndef CAPSTONE_DIET |
| 15202 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15203 | #endif |
| 15204 | }, |
| 15205 | { |
| 15206 | AArch64_UQADDhhh, ARM64_INS_UQADD, |
| 15207 | #ifndef CAPSTONE_DIET |
| 15208 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15209 | #endif |
| 15210 | }, |
| 15211 | { |
| 15212 | AArch64_UQADDsss, ARM64_INS_UQADD, |
| 15213 | #ifndef CAPSTONE_DIET |
| 15214 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15215 | #endif |
| 15216 | }, |
| 15217 | { |
| 15218 | AArch64_UQADDvvv_16B, ARM64_INS_UQADD, |
| 15219 | #ifndef CAPSTONE_DIET |
| 15220 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15221 | #endif |
| 15222 | }, |
| 15223 | { |
| 15224 | AArch64_UQADDvvv_2D, ARM64_INS_UQADD, |
| 15225 | #ifndef CAPSTONE_DIET |
| 15226 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15227 | #endif |
| 15228 | }, |
| 15229 | { |
| 15230 | AArch64_UQADDvvv_2S, ARM64_INS_UQADD, |
| 15231 | #ifndef CAPSTONE_DIET |
| 15232 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15233 | #endif |
| 15234 | }, |
| 15235 | { |
| 15236 | AArch64_UQADDvvv_4H, ARM64_INS_UQADD, |
| 15237 | #ifndef CAPSTONE_DIET |
| 15238 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15239 | #endif |
| 15240 | }, |
| 15241 | { |
| 15242 | AArch64_UQADDvvv_4S, ARM64_INS_UQADD, |
| 15243 | #ifndef CAPSTONE_DIET |
| 15244 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15245 | #endif |
| 15246 | }, |
| 15247 | { |
| 15248 | AArch64_UQADDvvv_8B, ARM64_INS_UQADD, |
| 15249 | #ifndef CAPSTONE_DIET |
| 15250 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15251 | #endif |
| 15252 | }, |
| 15253 | { |
| 15254 | AArch64_UQADDvvv_8H, ARM64_INS_UQADD, |
| 15255 | #ifndef CAPSTONE_DIET |
| 15256 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15257 | #endif |
| 15258 | }, |
| 15259 | { |
| 15260 | AArch64_UQRSHLbbb, ARM64_INS_UQRSHL, |
| 15261 | #ifndef CAPSTONE_DIET |
| 15262 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15263 | #endif |
| 15264 | }, |
| 15265 | { |
| 15266 | AArch64_UQRSHLddd, ARM64_INS_UQRSHL, |
| 15267 | #ifndef CAPSTONE_DIET |
| 15268 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15269 | #endif |
| 15270 | }, |
| 15271 | { |
| 15272 | AArch64_UQRSHLhhh, ARM64_INS_UQRSHL, |
| 15273 | #ifndef CAPSTONE_DIET |
| 15274 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15275 | #endif |
| 15276 | }, |
| 15277 | { |
| 15278 | AArch64_UQRSHLsss, ARM64_INS_UQRSHL, |
| 15279 | #ifndef CAPSTONE_DIET |
| 15280 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15281 | #endif |
| 15282 | }, |
| 15283 | { |
| 15284 | AArch64_UQRSHLvvv_16B, ARM64_INS_UQRSHL, |
| 15285 | #ifndef CAPSTONE_DIET |
| 15286 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15287 | #endif |
| 15288 | }, |
| 15289 | { |
| 15290 | AArch64_UQRSHLvvv_2D, ARM64_INS_UQRSHL, |
| 15291 | #ifndef CAPSTONE_DIET |
| 15292 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15293 | #endif |
| 15294 | }, |
| 15295 | { |
| 15296 | AArch64_UQRSHLvvv_2S, ARM64_INS_UQRSHL, |
| 15297 | #ifndef CAPSTONE_DIET |
| 15298 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15299 | #endif |
| 15300 | }, |
| 15301 | { |
| 15302 | AArch64_UQRSHLvvv_4H, ARM64_INS_UQRSHL, |
| 15303 | #ifndef CAPSTONE_DIET |
| 15304 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15305 | #endif |
| 15306 | }, |
| 15307 | { |
| 15308 | AArch64_UQRSHLvvv_4S, ARM64_INS_UQRSHL, |
| 15309 | #ifndef CAPSTONE_DIET |
| 15310 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15311 | #endif |
| 15312 | }, |
| 15313 | { |
| 15314 | AArch64_UQRSHLvvv_8B, ARM64_INS_UQRSHL, |
| 15315 | #ifndef CAPSTONE_DIET |
| 15316 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15317 | #endif |
| 15318 | }, |
| 15319 | { |
| 15320 | AArch64_UQRSHLvvv_8H, ARM64_INS_UQRSHL, |
| 15321 | #ifndef CAPSTONE_DIET |
| 15322 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15323 | #endif |
| 15324 | }, |
| 15325 | { |
| 15326 | AArch64_UQRSHRNbhi, ARM64_INS_UQRSHRN, |
| 15327 | #ifndef CAPSTONE_DIET |
| 15328 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15329 | #endif |
| 15330 | }, |
| 15331 | { |
| 15332 | AArch64_UQRSHRNhsi, ARM64_INS_UQRSHRN, |
| 15333 | #ifndef CAPSTONE_DIET |
| 15334 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15335 | #endif |
| 15336 | }, |
| 15337 | { |
| 15338 | AArch64_UQRSHRNsdi, ARM64_INS_UQRSHRN, |
| 15339 | #ifndef CAPSTONE_DIET |
| 15340 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15341 | #endif |
| 15342 | }, |
| 15343 | { |
| 15344 | AArch64_UQRSHRNvvi_16B, ARM64_INS_UQRSHRN2, |
| 15345 | #ifndef CAPSTONE_DIET |
| 15346 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15347 | #endif |
| 15348 | }, |
| 15349 | { |
| 15350 | AArch64_UQRSHRNvvi_2S, ARM64_INS_UQRSHRN, |
| 15351 | #ifndef CAPSTONE_DIET |
| 15352 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15353 | #endif |
| 15354 | }, |
| 15355 | { |
| 15356 | AArch64_UQRSHRNvvi_4H, ARM64_INS_UQRSHRN, |
| 15357 | #ifndef CAPSTONE_DIET |
| 15358 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15359 | #endif |
| 15360 | }, |
| 15361 | { |
| 15362 | AArch64_UQRSHRNvvi_4S, ARM64_INS_UQRSHRN2, |
| 15363 | #ifndef CAPSTONE_DIET |
| 15364 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15365 | #endif |
| 15366 | }, |
| 15367 | { |
| 15368 | AArch64_UQRSHRNvvi_8B, ARM64_INS_UQRSHRN, |
| 15369 | #ifndef CAPSTONE_DIET |
| 15370 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15371 | #endif |
| 15372 | }, |
| 15373 | { |
| 15374 | AArch64_UQRSHRNvvi_8H, ARM64_INS_UQRSHRN2, |
| 15375 | #ifndef CAPSTONE_DIET |
| 15376 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15377 | #endif |
| 15378 | }, |
| 15379 | { |
| 15380 | AArch64_UQSHLbbb, ARM64_INS_UQSHL, |
| 15381 | #ifndef CAPSTONE_DIET |
| 15382 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15383 | #endif |
| 15384 | }, |
| 15385 | { |
| 15386 | AArch64_UQSHLbbi, ARM64_INS_UQSHL, |
| 15387 | #ifndef CAPSTONE_DIET |
| 15388 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15389 | #endif |
| 15390 | }, |
| 15391 | { |
| 15392 | AArch64_UQSHLddd, ARM64_INS_UQSHL, |
| 15393 | #ifndef CAPSTONE_DIET |
| 15394 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15395 | #endif |
| 15396 | }, |
| 15397 | { |
| 15398 | AArch64_UQSHLddi, ARM64_INS_UQSHL, |
| 15399 | #ifndef CAPSTONE_DIET |
| 15400 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15401 | #endif |
| 15402 | }, |
| 15403 | { |
| 15404 | AArch64_UQSHLhhh, ARM64_INS_UQSHL, |
| 15405 | #ifndef CAPSTONE_DIET |
| 15406 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15407 | #endif |
| 15408 | }, |
| 15409 | { |
| 15410 | AArch64_UQSHLhhi, ARM64_INS_UQSHL, |
| 15411 | #ifndef CAPSTONE_DIET |
| 15412 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15413 | #endif |
| 15414 | }, |
| 15415 | { |
| 15416 | AArch64_UQSHLssi, ARM64_INS_UQSHL, |
| 15417 | #ifndef CAPSTONE_DIET |
| 15418 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15419 | #endif |
| 15420 | }, |
| 15421 | { |
| 15422 | AArch64_UQSHLsss, ARM64_INS_UQSHL, |
| 15423 | #ifndef CAPSTONE_DIET |
| 15424 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15425 | #endif |
| 15426 | }, |
| 15427 | { |
| 15428 | AArch64_UQSHLvvi_16B, ARM64_INS_UQSHL, |
| 15429 | #ifndef CAPSTONE_DIET |
| 15430 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15431 | #endif |
| 15432 | }, |
| 15433 | { |
| 15434 | AArch64_UQSHLvvi_2D, ARM64_INS_UQSHL, |
| 15435 | #ifndef CAPSTONE_DIET |
| 15436 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15437 | #endif |
| 15438 | }, |
| 15439 | { |
| 15440 | AArch64_UQSHLvvi_2S, ARM64_INS_UQSHL, |
| 15441 | #ifndef CAPSTONE_DIET |
| 15442 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15443 | #endif |
| 15444 | }, |
| 15445 | { |
| 15446 | AArch64_UQSHLvvi_4H, ARM64_INS_UQSHL, |
| 15447 | #ifndef CAPSTONE_DIET |
| 15448 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15449 | #endif |
| 15450 | }, |
| 15451 | { |
| 15452 | AArch64_UQSHLvvi_4S, ARM64_INS_UQSHL, |
| 15453 | #ifndef CAPSTONE_DIET |
| 15454 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15455 | #endif |
| 15456 | }, |
| 15457 | { |
| 15458 | AArch64_UQSHLvvi_8B, ARM64_INS_UQSHL, |
| 15459 | #ifndef CAPSTONE_DIET |
| 15460 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15461 | #endif |
| 15462 | }, |
| 15463 | { |
| 15464 | AArch64_UQSHLvvi_8H, ARM64_INS_UQSHL, |
| 15465 | #ifndef CAPSTONE_DIET |
| 15466 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15467 | #endif |
| 15468 | }, |
| 15469 | { |
| 15470 | AArch64_UQSHLvvv_16B, ARM64_INS_UQSHL, |
| 15471 | #ifndef CAPSTONE_DIET |
| 15472 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15473 | #endif |
| 15474 | }, |
| 15475 | { |
| 15476 | AArch64_UQSHLvvv_2D, ARM64_INS_UQSHL, |
| 15477 | #ifndef CAPSTONE_DIET |
| 15478 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15479 | #endif |
| 15480 | }, |
| 15481 | { |
| 15482 | AArch64_UQSHLvvv_2S, ARM64_INS_UQSHL, |
| 15483 | #ifndef CAPSTONE_DIET |
| 15484 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15485 | #endif |
| 15486 | }, |
| 15487 | { |
| 15488 | AArch64_UQSHLvvv_4H, ARM64_INS_UQSHL, |
| 15489 | #ifndef CAPSTONE_DIET |
| 15490 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15491 | #endif |
| 15492 | }, |
| 15493 | { |
| 15494 | AArch64_UQSHLvvv_4S, ARM64_INS_UQSHL, |
| 15495 | #ifndef CAPSTONE_DIET |
| 15496 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15497 | #endif |
| 15498 | }, |
| 15499 | { |
| 15500 | AArch64_UQSHLvvv_8B, ARM64_INS_UQSHL, |
| 15501 | #ifndef CAPSTONE_DIET |
| 15502 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15503 | #endif |
| 15504 | }, |
| 15505 | { |
| 15506 | AArch64_UQSHLvvv_8H, ARM64_INS_UQSHL, |
| 15507 | #ifndef CAPSTONE_DIET |
| 15508 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15509 | #endif |
| 15510 | }, |
| 15511 | { |
| 15512 | AArch64_UQSHRNbhi, ARM64_INS_UQSHRN, |
| 15513 | #ifndef CAPSTONE_DIET |
| 15514 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15515 | #endif |
| 15516 | }, |
| 15517 | { |
| 15518 | AArch64_UQSHRNhsi, ARM64_INS_UQSHRN, |
| 15519 | #ifndef CAPSTONE_DIET |
| 15520 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15521 | #endif |
| 15522 | }, |
| 15523 | { |
| 15524 | AArch64_UQSHRNsdi, ARM64_INS_UQSHRN, |
| 15525 | #ifndef CAPSTONE_DIET |
| 15526 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15527 | #endif |
| 15528 | }, |
| 15529 | { |
| 15530 | AArch64_UQSHRNvvi_16B, ARM64_INS_UQSHRN2, |
| 15531 | #ifndef CAPSTONE_DIET |
| 15532 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15533 | #endif |
| 15534 | }, |
| 15535 | { |
| 15536 | AArch64_UQSHRNvvi_2S, ARM64_INS_UQSHRN, |
| 15537 | #ifndef CAPSTONE_DIET |
| 15538 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15539 | #endif |
| 15540 | }, |
| 15541 | { |
| 15542 | AArch64_UQSHRNvvi_4H, ARM64_INS_UQSHRN, |
| 15543 | #ifndef CAPSTONE_DIET |
| 15544 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15545 | #endif |
| 15546 | }, |
| 15547 | { |
| 15548 | AArch64_UQSHRNvvi_4S, ARM64_INS_UQSHRN2, |
| 15549 | #ifndef CAPSTONE_DIET |
| 15550 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15551 | #endif |
| 15552 | }, |
| 15553 | { |
| 15554 | AArch64_UQSHRNvvi_8B, ARM64_INS_UQSHRN, |
| 15555 | #ifndef CAPSTONE_DIET |
| 15556 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15557 | #endif |
| 15558 | }, |
| 15559 | { |
| 15560 | AArch64_UQSHRNvvi_8H, ARM64_INS_UQSHRN2, |
| 15561 | #ifndef CAPSTONE_DIET |
| 15562 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15563 | #endif |
| 15564 | }, |
| 15565 | { |
| 15566 | AArch64_UQSUBbbb, ARM64_INS_UQSUB, |
| 15567 | #ifndef CAPSTONE_DIET |
| 15568 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15569 | #endif |
| 15570 | }, |
| 15571 | { |
| 15572 | AArch64_UQSUBddd, ARM64_INS_UQSUB, |
| 15573 | #ifndef CAPSTONE_DIET |
| 15574 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15575 | #endif |
| 15576 | }, |
| 15577 | { |
| 15578 | AArch64_UQSUBhhh, ARM64_INS_UQSUB, |
| 15579 | #ifndef CAPSTONE_DIET |
| 15580 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15581 | #endif |
| 15582 | }, |
| 15583 | { |
| 15584 | AArch64_UQSUBsss, ARM64_INS_UQSUB, |
| 15585 | #ifndef CAPSTONE_DIET |
| 15586 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15587 | #endif |
| 15588 | }, |
| 15589 | { |
| 15590 | AArch64_UQSUBvvv_16B, ARM64_INS_UQSUB, |
| 15591 | #ifndef CAPSTONE_DIET |
| 15592 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15593 | #endif |
| 15594 | }, |
| 15595 | { |
| 15596 | AArch64_UQSUBvvv_2D, ARM64_INS_UQSUB, |
| 15597 | #ifndef CAPSTONE_DIET |
| 15598 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15599 | #endif |
| 15600 | }, |
| 15601 | { |
| 15602 | AArch64_UQSUBvvv_2S, ARM64_INS_UQSUB, |
| 15603 | #ifndef CAPSTONE_DIET |
| 15604 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15605 | #endif |
| 15606 | }, |
| 15607 | { |
| 15608 | AArch64_UQSUBvvv_4H, ARM64_INS_UQSUB, |
| 15609 | #ifndef CAPSTONE_DIET |
| 15610 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15611 | #endif |
| 15612 | }, |
| 15613 | { |
| 15614 | AArch64_UQSUBvvv_4S, ARM64_INS_UQSUB, |
| 15615 | #ifndef CAPSTONE_DIET |
| 15616 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15617 | #endif |
| 15618 | }, |
| 15619 | { |
| 15620 | AArch64_UQSUBvvv_8B, ARM64_INS_UQSUB, |
| 15621 | #ifndef CAPSTONE_DIET |
| 15622 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15623 | #endif |
| 15624 | }, |
| 15625 | { |
| 15626 | AArch64_UQSUBvvv_8H, ARM64_INS_UQSUB, |
| 15627 | #ifndef CAPSTONE_DIET |
| 15628 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15629 | #endif |
| 15630 | }, |
| 15631 | { |
| 15632 | AArch64_UQXTN2d2s, ARM64_INS_UQXTN, |
| 15633 | #ifndef CAPSTONE_DIET |
| 15634 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15635 | #endif |
| 15636 | }, |
| 15637 | { |
| 15638 | AArch64_UQXTN2d4s, ARM64_INS_UQXTN2, |
| 15639 | #ifndef CAPSTONE_DIET |
| 15640 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15641 | #endif |
| 15642 | }, |
| 15643 | { |
| 15644 | AArch64_UQXTN4s4h, ARM64_INS_UQXTN, |
| 15645 | #ifndef CAPSTONE_DIET |
| 15646 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15647 | #endif |
| 15648 | }, |
| 15649 | { |
| 15650 | AArch64_UQXTN4s8h, ARM64_INS_UQXTN2, |
| 15651 | #ifndef CAPSTONE_DIET |
| 15652 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15653 | #endif |
| 15654 | }, |
| 15655 | { |
| 15656 | AArch64_UQXTN8h16b, ARM64_INS_UQXTN2, |
| 15657 | #ifndef CAPSTONE_DIET |
| 15658 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15659 | #endif |
| 15660 | }, |
| 15661 | { |
| 15662 | AArch64_UQXTN8h8b, ARM64_INS_UQXTN, |
| 15663 | #ifndef CAPSTONE_DIET |
| 15664 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15665 | #endif |
| 15666 | }, |
| 15667 | { |
| 15668 | AArch64_UQXTNbh, ARM64_INS_UQXTN, |
| 15669 | #ifndef CAPSTONE_DIET |
| 15670 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15671 | #endif |
| 15672 | }, |
| 15673 | { |
| 15674 | AArch64_UQXTNhs, ARM64_INS_UQXTN, |
| 15675 | #ifndef CAPSTONE_DIET |
| 15676 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15677 | #endif |
| 15678 | }, |
| 15679 | { |
| 15680 | AArch64_UQXTNsd, ARM64_INS_UQXTN, |
| 15681 | #ifndef CAPSTONE_DIET |
| 15682 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15683 | #endif |
| 15684 | }, |
| 15685 | { |
| 15686 | AArch64_URECPE2s, ARM64_INS_URECPE, |
| 15687 | #ifndef CAPSTONE_DIET |
| 15688 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15689 | #endif |
| 15690 | }, |
| 15691 | { |
| 15692 | AArch64_URECPE4s, ARM64_INS_URECPE, |
| 15693 | #ifndef CAPSTONE_DIET |
| 15694 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15695 | #endif |
| 15696 | }, |
| 15697 | { |
| 15698 | AArch64_URHADDvvv_16B, ARM64_INS_URHADD, |
| 15699 | #ifndef CAPSTONE_DIET |
| 15700 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15701 | #endif |
| 15702 | }, |
| 15703 | { |
| 15704 | AArch64_URHADDvvv_2S, ARM64_INS_URHADD, |
| 15705 | #ifndef CAPSTONE_DIET |
| 15706 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15707 | #endif |
| 15708 | }, |
| 15709 | { |
| 15710 | AArch64_URHADDvvv_4H, ARM64_INS_URHADD, |
| 15711 | #ifndef CAPSTONE_DIET |
| 15712 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15713 | #endif |
| 15714 | }, |
| 15715 | { |
| 15716 | AArch64_URHADDvvv_4S, ARM64_INS_URHADD, |
| 15717 | #ifndef CAPSTONE_DIET |
| 15718 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15719 | #endif |
| 15720 | }, |
| 15721 | { |
| 15722 | AArch64_URHADDvvv_8B, ARM64_INS_URHADD, |
| 15723 | #ifndef CAPSTONE_DIET |
| 15724 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15725 | #endif |
| 15726 | }, |
| 15727 | { |
| 15728 | AArch64_URHADDvvv_8H, ARM64_INS_URHADD, |
| 15729 | #ifndef CAPSTONE_DIET |
| 15730 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15731 | #endif |
| 15732 | }, |
| 15733 | { |
| 15734 | AArch64_URSHLddd, ARM64_INS_URSHL, |
| 15735 | #ifndef CAPSTONE_DIET |
| 15736 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15737 | #endif |
| 15738 | }, |
| 15739 | { |
| 15740 | AArch64_URSHLvvv_16B, ARM64_INS_URSHL, |
| 15741 | #ifndef CAPSTONE_DIET |
| 15742 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15743 | #endif |
| 15744 | }, |
| 15745 | { |
| 15746 | AArch64_URSHLvvv_2D, ARM64_INS_URSHL, |
| 15747 | #ifndef CAPSTONE_DIET |
| 15748 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15749 | #endif |
| 15750 | }, |
| 15751 | { |
| 15752 | AArch64_URSHLvvv_2S, ARM64_INS_URSHL, |
| 15753 | #ifndef CAPSTONE_DIET |
| 15754 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15755 | #endif |
| 15756 | }, |
| 15757 | { |
| 15758 | AArch64_URSHLvvv_4H, ARM64_INS_URSHL, |
| 15759 | #ifndef CAPSTONE_DIET |
| 15760 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15761 | #endif |
| 15762 | }, |
| 15763 | { |
| 15764 | AArch64_URSHLvvv_4S, ARM64_INS_URSHL, |
| 15765 | #ifndef CAPSTONE_DIET |
| 15766 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15767 | #endif |
| 15768 | }, |
| 15769 | { |
| 15770 | AArch64_URSHLvvv_8B, ARM64_INS_URSHL, |
| 15771 | #ifndef CAPSTONE_DIET |
| 15772 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15773 | #endif |
| 15774 | }, |
| 15775 | { |
| 15776 | AArch64_URSHLvvv_8H, ARM64_INS_URSHL, |
| 15777 | #ifndef CAPSTONE_DIET |
| 15778 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15779 | #endif |
| 15780 | }, |
| 15781 | { |
| 15782 | AArch64_URSHRddi, ARM64_INS_URSHR, |
| 15783 | #ifndef CAPSTONE_DIET |
| 15784 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15785 | #endif |
| 15786 | }, |
| 15787 | { |
| 15788 | AArch64_URSHRvvi_16B, ARM64_INS_URSHR, |
| 15789 | #ifndef CAPSTONE_DIET |
| 15790 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15791 | #endif |
| 15792 | }, |
| 15793 | { |
| 15794 | AArch64_URSHRvvi_2D, ARM64_INS_URSHR, |
| 15795 | #ifndef CAPSTONE_DIET |
| 15796 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15797 | #endif |
| 15798 | }, |
| 15799 | { |
| 15800 | AArch64_URSHRvvi_2S, ARM64_INS_URSHR, |
| 15801 | #ifndef CAPSTONE_DIET |
| 15802 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15803 | #endif |
| 15804 | }, |
| 15805 | { |
| 15806 | AArch64_URSHRvvi_4H, ARM64_INS_URSHR, |
| 15807 | #ifndef CAPSTONE_DIET |
| 15808 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15809 | #endif |
| 15810 | }, |
| 15811 | { |
| 15812 | AArch64_URSHRvvi_4S, ARM64_INS_URSHR, |
| 15813 | #ifndef CAPSTONE_DIET |
| 15814 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15815 | #endif |
| 15816 | }, |
| 15817 | { |
| 15818 | AArch64_URSHRvvi_8B, ARM64_INS_URSHR, |
| 15819 | #ifndef CAPSTONE_DIET |
| 15820 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15821 | #endif |
| 15822 | }, |
| 15823 | { |
| 15824 | AArch64_URSHRvvi_8H, ARM64_INS_URSHR, |
| 15825 | #ifndef CAPSTONE_DIET |
| 15826 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15827 | #endif |
| 15828 | }, |
| 15829 | { |
| 15830 | AArch64_URSQRTE2s, ARM64_INS_URSQRTE, |
| 15831 | #ifndef CAPSTONE_DIET |
| 15832 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15833 | #endif |
| 15834 | }, |
| 15835 | { |
| 15836 | AArch64_URSQRTE4s, ARM64_INS_URSQRTE, |
| 15837 | #ifndef CAPSTONE_DIET |
| 15838 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15839 | #endif |
| 15840 | }, |
| 15841 | { |
| 15842 | AArch64_URSRA, ARM64_INS_URSRA, |
| 15843 | #ifndef CAPSTONE_DIET |
| 15844 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15845 | #endif |
| 15846 | }, |
| 15847 | { |
| 15848 | AArch64_URSRAvvi_16B, ARM64_INS_URSRA, |
| 15849 | #ifndef CAPSTONE_DIET |
| 15850 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15851 | #endif |
| 15852 | }, |
| 15853 | { |
| 15854 | AArch64_URSRAvvi_2D, ARM64_INS_URSRA, |
| 15855 | #ifndef CAPSTONE_DIET |
| 15856 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15857 | #endif |
| 15858 | }, |
| 15859 | { |
| 15860 | AArch64_URSRAvvi_2S, ARM64_INS_URSRA, |
| 15861 | #ifndef CAPSTONE_DIET |
| 15862 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15863 | #endif |
| 15864 | }, |
| 15865 | { |
| 15866 | AArch64_URSRAvvi_4H, ARM64_INS_URSRA, |
| 15867 | #ifndef CAPSTONE_DIET |
| 15868 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15869 | #endif |
| 15870 | }, |
| 15871 | { |
| 15872 | AArch64_URSRAvvi_4S, ARM64_INS_URSRA, |
| 15873 | #ifndef CAPSTONE_DIET |
| 15874 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15875 | #endif |
| 15876 | }, |
| 15877 | { |
| 15878 | AArch64_URSRAvvi_8B, ARM64_INS_URSRA, |
| 15879 | #ifndef CAPSTONE_DIET |
| 15880 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15881 | #endif |
| 15882 | }, |
| 15883 | { |
| 15884 | AArch64_URSRAvvi_8H, ARM64_INS_URSRA, |
| 15885 | #ifndef CAPSTONE_DIET |
| 15886 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15887 | #endif |
| 15888 | }, |
| 15889 | { |
| 15890 | AArch64_USHLLvvi_16B, ARM64_INS_USHLL2, |
| 15891 | #ifndef CAPSTONE_DIET |
| 15892 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15893 | #endif |
| 15894 | }, |
| 15895 | { |
| 15896 | AArch64_USHLLvvi_2S, ARM64_INS_USHLL, |
| 15897 | #ifndef CAPSTONE_DIET |
| 15898 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15899 | #endif |
| 15900 | }, |
| 15901 | { |
| 15902 | AArch64_USHLLvvi_4H, ARM64_INS_USHLL, |
| 15903 | #ifndef CAPSTONE_DIET |
| 15904 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15905 | #endif |
| 15906 | }, |
| 15907 | { |
| 15908 | AArch64_USHLLvvi_4S, ARM64_INS_USHLL2, |
| 15909 | #ifndef CAPSTONE_DIET |
| 15910 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15911 | #endif |
| 15912 | }, |
| 15913 | { |
| 15914 | AArch64_USHLLvvi_8B, ARM64_INS_USHLL, |
| 15915 | #ifndef CAPSTONE_DIET |
| 15916 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15917 | #endif |
| 15918 | }, |
| 15919 | { |
| 15920 | AArch64_USHLLvvi_8H, ARM64_INS_USHLL2, |
| 15921 | #ifndef CAPSTONE_DIET |
| 15922 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15923 | #endif |
| 15924 | }, |
| 15925 | { |
| 15926 | AArch64_USHLddd, ARM64_INS_USHL, |
| 15927 | #ifndef CAPSTONE_DIET |
| 15928 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15929 | #endif |
| 15930 | }, |
| 15931 | { |
| 15932 | AArch64_USHLvvv_16B, ARM64_INS_USHL, |
| 15933 | #ifndef CAPSTONE_DIET |
| 15934 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15935 | #endif |
| 15936 | }, |
| 15937 | { |
| 15938 | AArch64_USHLvvv_2D, ARM64_INS_USHL, |
| 15939 | #ifndef CAPSTONE_DIET |
| 15940 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15941 | #endif |
| 15942 | }, |
| 15943 | { |
| 15944 | AArch64_USHLvvv_2S, ARM64_INS_USHL, |
| 15945 | #ifndef CAPSTONE_DIET |
| 15946 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15947 | #endif |
| 15948 | }, |
| 15949 | { |
| 15950 | AArch64_USHLvvv_4H, ARM64_INS_USHL, |
| 15951 | #ifndef CAPSTONE_DIET |
| 15952 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15953 | #endif |
| 15954 | }, |
| 15955 | { |
| 15956 | AArch64_USHLvvv_4S, ARM64_INS_USHL, |
| 15957 | #ifndef CAPSTONE_DIET |
| 15958 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15959 | #endif |
| 15960 | }, |
| 15961 | { |
| 15962 | AArch64_USHLvvv_8B, ARM64_INS_USHL, |
| 15963 | #ifndef CAPSTONE_DIET |
| 15964 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15965 | #endif |
| 15966 | }, |
| 15967 | { |
| 15968 | AArch64_USHLvvv_8H, ARM64_INS_USHL, |
| 15969 | #ifndef CAPSTONE_DIET |
| 15970 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15971 | #endif |
| 15972 | }, |
| 15973 | { |
| 15974 | AArch64_USHRddi, ARM64_INS_USHR, |
| 15975 | #ifndef CAPSTONE_DIET |
| 15976 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15977 | #endif |
| 15978 | }, |
| 15979 | { |
| 15980 | AArch64_USHRvvi_16B, ARM64_INS_USHR, |
| 15981 | #ifndef CAPSTONE_DIET |
| 15982 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15983 | #endif |
| 15984 | }, |
| 15985 | { |
| 15986 | AArch64_USHRvvi_2D, ARM64_INS_USHR, |
| 15987 | #ifndef CAPSTONE_DIET |
| 15988 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15989 | #endif |
| 15990 | }, |
| 15991 | { |
| 15992 | AArch64_USHRvvi_2S, ARM64_INS_USHR, |
| 15993 | #ifndef CAPSTONE_DIET |
| 15994 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 15995 | #endif |
| 15996 | }, |
| 15997 | { |
| 15998 | AArch64_USHRvvi_4H, ARM64_INS_USHR, |
| 15999 | #ifndef CAPSTONE_DIET |
| 16000 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16001 | #endif |
| 16002 | }, |
| 16003 | { |
| 16004 | AArch64_USHRvvi_4S, ARM64_INS_USHR, |
| 16005 | #ifndef CAPSTONE_DIET |
| 16006 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16007 | #endif |
| 16008 | }, |
| 16009 | { |
| 16010 | AArch64_USHRvvi_8B, ARM64_INS_USHR, |
| 16011 | #ifndef CAPSTONE_DIET |
| 16012 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16013 | #endif |
| 16014 | }, |
| 16015 | { |
| 16016 | AArch64_USHRvvi_8H, ARM64_INS_USHR, |
| 16017 | #ifndef CAPSTONE_DIET |
| 16018 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16019 | #endif |
| 16020 | }, |
| 16021 | { |
| 16022 | AArch64_USQADD16b, ARM64_INS_USQADD, |
| 16023 | #ifndef CAPSTONE_DIET |
| 16024 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16025 | #endif |
| 16026 | }, |
| 16027 | { |
| 16028 | AArch64_USQADD2d, ARM64_INS_USQADD, |
| 16029 | #ifndef CAPSTONE_DIET |
| 16030 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16031 | #endif |
| 16032 | }, |
| 16033 | { |
| 16034 | AArch64_USQADD2s, ARM64_INS_USQADD, |
| 16035 | #ifndef CAPSTONE_DIET |
| 16036 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16037 | #endif |
| 16038 | }, |
| 16039 | { |
| 16040 | AArch64_USQADD4h, ARM64_INS_USQADD, |
| 16041 | #ifndef CAPSTONE_DIET |
| 16042 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16043 | #endif |
| 16044 | }, |
| 16045 | { |
| 16046 | AArch64_USQADD4s, ARM64_INS_USQADD, |
| 16047 | #ifndef CAPSTONE_DIET |
| 16048 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16049 | #endif |
| 16050 | }, |
| 16051 | { |
| 16052 | AArch64_USQADD8b, ARM64_INS_USQADD, |
| 16053 | #ifndef CAPSTONE_DIET |
| 16054 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16055 | #endif |
| 16056 | }, |
| 16057 | { |
| 16058 | AArch64_USQADD8h, ARM64_INS_USQADD, |
| 16059 | #ifndef CAPSTONE_DIET |
| 16060 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16061 | #endif |
| 16062 | }, |
| 16063 | { |
| 16064 | AArch64_USQADDbb, ARM64_INS_USQADD, |
| 16065 | #ifndef CAPSTONE_DIET |
| 16066 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16067 | #endif |
| 16068 | }, |
| 16069 | { |
| 16070 | AArch64_USQADDdd, ARM64_INS_USQADD, |
| 16071 | #ifndef CAPSTONE_DIET |
| 16072 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16073 | #endif |
| 16074 | }, |
| 16075 | { |
| 16076 | AArch64_USQADDhh, ARM64_INS_USQADD, |
| 16077 | #ifndef CAPSTONE_DIET |
| 16078 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16079 | #endif |
| 16080 | }, |
| 16081 | { |
| 16082 | AArch64_USQADDss, ARM64_INS_USQADD, |
| 16083 | #ifndef CAPSTONE_DIET |
| 16084 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16085 | #endif |
| 16086 | }, |
| 16087 | { |
| 16088 | AArch64_USRA, ARM64_INS_USRA, |
| 16089 | #ifndef CAPSTONE_DIET |
| 16090 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16091 | #endif |
| 16092 | }, |
| 16093 | { |
| 16094 | AArch64_USRAvvi_16B, ARM64_INS_USRA, |
| 16095 | #ifndef CAPSTONE_DIET |
| 16096 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16097 | #endif |
| 16098 | }, |
| 16099 | { |
| 16100 | AArch64_USRAvvi_2D, ARM64_INS_USRA, |
| 16101 | #ifndef CAPSTONE_DIET |
| 16102 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16103 | #endif |
| 16104 | }, |
| 16105 | { |
| 16106 | AArch64_USRAvvi_2S, ARM64_INS_USRA, |
| 16107 | #ifndef CAPSTONE_DIET |
| 16108 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16109 | #endif |
| 16110 | }, |
| 16111 | { |
| 16112 | AArch64_USRAvvi_4H, ARM64_INS_USRA, |
| 16113 | #ifndef CAPSTONE_DIET |
| 16114 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16115 | #endif |
| 16116 | }, |
| 16117 | { |
| 16118 | AArch64_USRAvvi_4S, ARM64_INS_USRA, |
| 16119 | #ifndef CAPSTONE_DIET |
| 16120 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16121 | #endif |
| 16122 | }, |
| 16123 | { |
| 16124 | AArch64_USRAvvi_8B, ARM64_INS_USRA, |
| 16125 | #ifndef CAPSTONE_DIET |
| 16126 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16127 | #endif |
| 16128 | }, |
| 16129 | { |
| 16130 | AArch64_USRAvvi_8H, ARM64_INS_USRA, |
| 16131 | #ifndef CAPSTONE_DIET |
| 16132 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16133 | #endif |
| 16134 | }, |
| 16135 | { |
| 16136 | AArch64_USUBL2vvv_2d4s, ARM64_INS_USUBL2, |
| 16137 | #ifndef CAPSTONE_DIET |
| 16138 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16139 | #endif |
| 16140 | }, |
| 16141 | { |
| 16142 | AArch64_USUBL2vvv_4s8h, ARM64_INS_USUBL2, |
| 16143 | #ifndef CAPSTONE_DIET |
| 16144 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16145 | #endif |
| 16146 | }, |
| 16147 | { |
| 16148 | AArch64_USUBL2vvv_8h16b, ARM64_INS_USUBL2, |
| 16149 | #ifndef CAPSTONE_DIET |
| 16150 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16151 | #endif |
| 16152 | }, |
| 16153 | { |
| 16154 | AArch64_USUBLvvv_2d2s, ARM64_INS_USUBL, |
| 16155 | #ifndef CAPSTONE_DIET |
| 16156 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16157 | #endif |
| 16158 | }, |
| 16159 | { |
| 16160 | AArch64_USUBLvvv_4s4h, ARM64_INS_USUBL, |
| 16161 | #ifndef CAPSTONE_DIET |
| 16162 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16163 | #endif |
| 16164 | }, |
| 16165 | { |
| 16166 | AArch64_USUBLvvv_8h8b, ARM64_INS_USUBL, |
| 16167 | #ifndef CAPSTONE_DIET |
| 16168 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16169 | #endif |
| 16170 | }, |
| 16171 | { |
| 16172 | AArch64_USUBW2vvv_2d4s, ARM64_INS_USUBW2, |
| 16173 | #ifndef CAPSTONE_DIET |
| 16174 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16175 | #endif |
| 16176 | }, |
| 16177 | { |
| 16178 | AArch64_USUBW2vvv_4s8h, ARM64_INS_USUBW2, |
| 16179 | #ifndef CAPSTONE_DIET |
| 16180 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16181 | #endif |
| 16182 | }, |
| 16183 | { |
| 16184 | AArch64_USUBW2vvv_8h16b, ARM64_INS_USUBW2, |
| 16185 | #ifndef CAPSTONE_DIET |
| 16186 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16187 | #endif |
| 16188 | }, |
| 16189 | { |
| 16190 | AArch64_USUBWvvv_2d2s, ARM64_INS_USUBW, |
| 16191 | #ifndef CAPSTONE_DIET |
| 16192 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16193 | #endif |
| 16194 | }, |
| 16195 | { |
| 16196 | AArch64_USUBWvvv_4s4h, ARM64_INS_USUBW, |
| 16197 | #ifndef CAPSTONE_DIET |
| 16198 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16199 | #endif |
| 16200 | }, |
| 16201 | { |
| 16202 | AArch64_USUBWvvv_8h8b, ARM64_INS_USUBW, |
| 16203 | #ifndef CAPSTONE_DIET |
| 16204 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16205 | #endif |
| 16206 | }, |
| 16207 | { |
| 16208 | AArch64_UXTBww, ARM64_INS_UXTB, |
| 16209 | #ifndef CAPSTONE_DIET |
| 16210 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 16211 | #endif |
| 16212 | }, |
| 16213 | { |
| 16214 | AArch64_UXTBxw, ARM64_INS_UXTB, |
| 16215 | #ifndef CAPSTONE_DIET |
| 16216 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 16217 | #endif |
| 16218 | }, |
| 16219 | { |
| 16220 | AArch64_UXTHww, ARM64_INS_UXTH, |
| 16221 | #ifndef CAPSTONE_DIET |
| 16222 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 16223 | #endif |
| 16224 | }, |
| 16225 | { |
| 16226 | AArch64_UXTHxw, ARM64_INS_UXTH, |
| 16227 | #ifndef CAPSTONE_DIET |
| 16228 | { 0 }, { 0 }, { 0 }, 0, 0 |
| 16229 | #endif |
| 16230 | }, |
| 16231 | { |
| 16232 | AArch64_UZP1vvv_16b, ARM64_INS_UZP1, |
| 16233 | #ifndef CAPSTONE_DIET |
| 16234 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16235 | #endif |
| 16236 | }, |
| 16237 | { |
| 16238 | AArch64_UZP1vvv_2d, ARM64_INS_UZP1, |
| 16239 | #ifndef CAPSTONE_DIET |
| 16240 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16241 | #endif |
| 16242 | }, |
| 16243 | { |
| 16244 | AArch64_UZP1vvv_2s, ARM64_INS_UZP1, |
| 16245 | #ifndef CAPSTONE_DIET |
| 16246 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16247 | #endif |
| 16248 | }, |
| 16249 | { |
| 16250 | AArch64_UZP1vvv_4h, ARM64_INS_UZP1, |
| 16251 | #ifndef CAPSTONE_DIET |
| 16252 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16253 | #endif |
| 16254 | }, |
| 16255 | { |
| 16256 | AArch64_UZP1vvv_4s, ARM64_INS_UZP1, |
| 16257 | #ifndef CAPSTONE_DIET |
| 16258 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16259 | #endif |
| 16260 | }, |
| 16261 | { |
| 16262 | AArch64_UZP1vvv_8b, ARM64_INS_UZP1, |
| 16263 | #ifndef CAPSTONE_DIET |
| 16264 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16265 | #endif |
| 16266 | }, |
| 16267 | { |
| 16268 | AArch64_UZP1vvv_8h, ARM64_INS_UZP1, |
| 16269 | #ifndef CAPSTONE_DIET |
| 16270 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16271 | #endif |
| 16272 | }, |
| 16273 | { |
| 16274 | AArch64_UZP2vvv_16b, ARM64_INS_UZP2, |
| 16275 | #ifndef CAPSTONE_DIET |
| 16276 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16277 | #endif |
| 16278 | }, |
| 16279 | { |
| 16280 | AArch64_UZP2vvv_2d, ARM64_INS_UZP2, |
| 16281 | #ifndef CAPSTONE_DIET |
| 16282 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16283 | #endif |
| 16284 | }, |
| 16285 | { |
| 16286 | AArch64_UZP2vvv_2s, ARM64_INS_UZP2, |
| 16287 | #ifndef CAPSTONE_DIET |
| 16288 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16289 | #endif |
| 16290 | }, |
| 16291 | { |
| 16292 | AArch64_UZP2vvv_4h, ARM64_INS_UZP2, |
| 16293 | #ifndef CAPSTONE_DIET |
| 16294 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16295 | #endif |
| 16296 | }, |
| 16297 | { |
| 16298 | AArch64_UZP2vvv_4s, ARM64_INS_UZP2, |
| 16299 | #ifndef CAPSTONE_DIET |
| 16300 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16301 | #endif |
| 16302 | }, |
| 16303 | { |
| 16304 | AArch64_UZP2vvv_8b, ARM64_INS_UZP2, |
| 16305 | #ifndef CAPSTONE_DIET |
| 16306 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16307 | #endif |
| 16308 | }, |
| 16309 | { |
| 16310 | AArch64_UZP2vvv_8h, ARM64_INS_UZP2, |
| 16311 | #ifndef CAPSTONE_DIET |
| 16312 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16313 | #endif |
| 16314 | }, |
| 16315 | { |
| 16316 | AArch64_VCVTf2xs_2D, ARM64_INS_FCVTZS, |
| 16317 | #ifndef CAPSTONE_DIET |
| 16318 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16319 | #endif |
| 16320 | }, |
| 16321 | { |
| 16322 | AArch64_VCVTf2xs_2S, ARM64_INS_FCVTZS, |
| 16323 | #ifndef CAPSTONE_DIET |
| 16324 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16325 | #endif |
| 16326 | }, |
| 16327 | { |
| 16328 | AArch64_VCVTf2xs_4S, ARM64_INS_FCVTZS, |
| 16329 | #ifndef CAPSTONE_DIET |
| 16330 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16331 | #endif |
| 16332 | }, |
| 16333 | { |
| 16334 | AArch64_VCVTf2xu_2D, ARM64_INS_FCVTZU, |
| 16335 | #ifndef CAPSTONE_DIET |
| 16336 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16337 | #endif |
| 16338 | }, |
| 16339 | { |
| 16340 | AArch64_VCVTf2xu_2S, ARM64_INS_FCVTZU, |
| 16341 | #ifndef CAPSTONE_DIET |
| 16342 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16343 | #endif |
| 16344 | }, |
| 16345 | { |
| 16346 | AArch64_VCVTf2xu_4S, ARM64_INS_FCVTZU, |
| 16347 | #ifndef CAPSTONE_DIET |
| 16348 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16349 | #endif |
| 16350 | }, |
| 16351 | { |
| 16352 | AArch64_VCVTxs2f_2D, ARM64_INS_SCVTF, |
| 16353 | #ifndef CAPSTONE_DIET |
| 16354 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16355 | #endif |
| 16356 | }, |
| 16357 | { |
| 16358 | AArch64_VCVTxs2f_2S, ARM64_INS_SCVTF, |
| 16359 | #ifndef CAPSTONE_DIET |
| 16360 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16361 | #endif |
| 16362 | }, |
| 16363 | { |
| 16364 | AArch64_VCVTxs2f_4S, ARM64_INS_SCVTF, |
| 16365 | #ifndef CAPSTONE_DIET |
| 16366 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16367 | #endif |
| 16368 | }, |
| 16369 | { |
| 16370 | AArch64_VCVTxu2f_2D, ARM64_INS_UCVTF, |
| 16371 | #ifndef CAPSTONE_DIET |
| 16372 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16373 | #endif |
| 16374 | }, |
| 16375 | { |
| 16376 | AArch64_VCVTxu2f_2S, ARM64_INS_UCVTF, |
| 16377 | #ifndef CAPSTONE_DIET |
| 16378 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16379 | #endif |
| 16380 | }, |
| 16381 | { |
| 16382 | AArch64_VCVTxu2f_4S, ARM64_INS_UCVTF, |
| 16383 | #ifndef CAPSTONE_DIET |
| 16384 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16385 | #endif |
| 16386 | }, |
| 16387 | { |
| 16388 | AArch64_XTN2d2s, ARM64_INS_XTN, |
| 16389 | #ifndef CAPSTONE_DIET |
| 16390 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16391 | #endif |
| 16392 | }, |
| 16393 | { |
| 16394 | AArch64_XTN2d4s, ARM64_INS_XTN2, |
| 16395 | #ifndef CAPSTONE_DIET |
| 16396 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16397 | #endif |
| 16398 | }, |
| 16399 | { |
| 16400 | AArch64_XTN4s4h, ARM64_INS_XTN, |
| 16401 | #ifndef CAPSTONE_DIET |
| 16402 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16403 | #endif |
| 16404 | }, |
| 16405 | { |
| 16406 | AArch64_XTN4s8h, ARM64_INS_XTN2, |
| 16407 | #ifndef CAPSTONE_DIET |
| 16408 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16409 | #endif |
| 16410 | }, |
| 16411 | { |
| 16412 | AArch64_XTN8h16b, ARM64_INS_XTN2, |
| 16413 | #ifndef CAPSTONE_DIET |
| 16414 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16415 | #endif |
| 16416 | }, |
| 16417 | { |
| 16418 | AArch64_XTN8h8b, ARM64_INS_XTN, |
| 16419 | #ifndef CAPSTONE_DIET |
| 16420 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16421 | #endif |
| 16422 | }, |
| 16423 | { |
| 16424 | AArch64_ZIP1vvv_16b, ARM64_INS_ZIP1, |
| 16425 | #ifndef CAPSTONE_DIET |
| 16426 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16427 | #endif |
| 16428 | }, |
| 16429 | { |
| 16430 | AArch64_ZIP1vvv_2d, ARM64_INS_ZIP1, |
| 16431 | #ifndef CAPSTONE_DIET |
| 16432 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16433 | #endif |
| 16434 | }, |
| 16435 | { |
| 16436 | AArch64_ZIP1vvv_2s, ARM64_INS_ZIP1, |
| 16437 | #ifndef CAPSTONE_DIET |
| 16438 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16439 | #endif |
| 16440 | }, |
| 16441 | { |
| 16442 | AArch64_ZIP1vvv_4h, ARM64_INS_ZIP1, |
| 16443 | #ifndef CAPSTONE_DIET |
| 16444 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16445 | #endif |
| 16446 | }, |
| 16447 | { |
| 16448 | AArch64_ZIP1vvv_4s, ARM64_INS_ZIP1, |
| 16449 | #ifndef CAPSTONE_DIET |
| 16450 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16451 | #endif |
| 16452 | }, |
| 16453 | { |
| 16454 | AArch64_ZIP1vvv_8b, ARM64_INS_ZIP1, |
| 16455 | #ifndef CAPSTONE_DIET |
| 16456 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16457 | #endif |
| 16458 | }, |
| 16459 | { |
| 16460 | AArch64_ZIP1vvv_8h, ARM64_INS_ZIP1, |
| 16461 | #ifndef CAPSTONE_DIET |
| 16462 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16463 | #endif |
| 16464 | }, |
| 16465 | { |
| 16466 | AArch64_ZIP2vvv_16b, ARM64_INS_ZIP2, |
| 16467 | #ifndef CAPSTONE_DIET |
| 16468 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16469 | #endif |
| 16470 | }, |
| 16471 | { |
| 16472 | AArch64_ZIP2vvv_2d, ARM64_INS_ZIP2, |
| 16473 | #ifndef CAPSTONE_DIET |
| 16474 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16475 | #endif |
| 16476 | }, |
| 16477 | { |
| 16478 | AArch64_ZIP2vvv_2s, ARM64_INS_ZIP2, |
| 16479 | #ifndef CAPSTONE_DIET |
| 16480 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16481 | #endif |
| 16482 | }, |
| 16483 | { |
| 16484 | AArch64_ZIP2vvv_4h, ARM64_INS_ZIP2, |
| 16485 | #ifndef CAPSTONE_DIET |
| 16486 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16487 | #endif |
| 16488 | }, |
| 16489 | { |
| 16490 | AArch64_ZIP2vvv_4s, ARM64_INS_ZIP2, |
| 16491 | #ifndef CAPSTONE_DIET |
| 16492 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16493 | #endif |
| 16494 | }, |
| 16495 | { |
| 16496 | AArch64_ZIP2vvv_8b, ARM64_INS_ZIP2, |
| 16497 | #ifndef CAPSTONE_DIET |
| 16498 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16499 | #endif |
| 16500 | }, |
| 16501 | { |
| 16502 | AArch64_ZIP2vvv_8h, ARM64_INS_ZIP2, |
| 16503 | #ifndef CAPSTONE_DIET |
| 16504 | { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| 16505 | #endif |
| 16506 | }, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 16507 | }; |
| 16508 | |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 16509 | // some alias instruction only need to be defined locally to satisfy |
| 16510 | // some lookup functions |
| 16511 | // just make sure these IDs never reuse any other IDs ARM_INS_* |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 16512 | #define ARM64_INS_NEGS (unsigned short)-1 |
| 16513 | #define ARM64_INS_NGCS (unsigned short)-2 |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 16514 | |
Nguyen Anh Quynh | b265406 | 2014-01-03 17:08:58 +0800 | [diff] [blame] | 16515 | // given internal insn id, return public instruction info |
Nguyen Anh Quynh | 1acfd0b | 2014-01-06 10:56:59 +0800 | [diff] [blame] | 16516 | void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 16517 | { |
Nguyen Anh Quynh | 1acfd0b | 2014-01-06 10:56:59 +0800 | [diff] [blame] | 16518 | int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); |
Nguyen Anh Quynh | b265406 | 2014-01-03 17:08:58 +0800 | [diff] [blame] | 16519 | if (i != 0) { |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 16520 | insn->id = insns[i].mapid; |
Nguyen Anh Quynh | f35e2ad | 2013-12-03 11:10:26 +0800 | [diff] [blame] | 16521 | |
Nguyen Anh Quynh | 1acfd0b | 2014-01-06 10:56:59 +0800 | [diff] [blame] | 16522 | if (h->detail) { |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 16523 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 16524 | cs_struct handle; |
Nguyen Anh Quynh | 1acfd0b | 2014-01-06 10:56:59 +0800 | [diff] [blame] | 16525 | handle.detail = h->detail; |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 16526 | |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 16527 | memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 16528 | insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); |
Nguyen Anh Quynh | f35e2ad | 2013-12-03 11:10:26 +0800 | [diff] [blame] | 16529 | |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 16530 | memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 16531 | insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); |
Nguyen Anh Quynh | f35e2ad | 2013-12-03 11:10:26 +0800 | [diff] [blame] | 16532 | |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 16533 | memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 16534 | insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups); |
Nguyen Anh Quynh | f35e2ad | 2013-12-03 11:10:26 +0800 | [diff] [blame] | 16535 | |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 16536 | insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV); |
Nguyen Anh Quynh | ec0ed8e | 2013-12-02 13:55:38 +0800 | [diff] [blame] | 16537 | |
Nguyen Anh Quynh | 4d3e852 | 2013-12-14 10:45:09 +0800 | [diff] [blame] | 16538 | if (insns[i].branch || insns[i].indirect_branch) { |
| 16539 | // this insn also belongs to JUMP group. add JUMP group |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 16540 | insn->detail->groups[insn->detail->groups_count] = ARM64_GRP_JUMP; |
| 16541 | insn->detail->groups_count++; |
Nguyen Anh Quynh | 4d3e852 | 2013-12-14 10:45:09 +0800 | [diff] [blame] | 16542 | } |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 16543 | #endif |
Nguyen Anh Quynh | ec0ed8e | 2013-12-02 13:55:38 +0800 | [diff] [blame] | 16544 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 16545 | } |
| 16546 | } |
| 16547 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 16548 | static name_map insn_name_maps[] = { |
| 16549 | { ARM64_INS_INVALID, NULL }, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 16550 | //========= |
| 16551 | |
| 16552 | { ARM64_INS_ABS, "abs" }, |
| 16553 | { ARM64_INS_ADC, "adc" }, |
| 16554 | { ARM64_INS_ADDHN2, "addhn2" }, |
| 16555 | { ARM64_INS_ADDHN, "addhn" }, |
| 16556 | { ARM64_INS_ADDP, "addp" }, |
| 16557 | { ARM64_INS_ADDV, "addv" }, |
| 16558 | { ARM64_INS_ADD, "add" }, |
| 16559 | { ARM64_INS_CMN, "cmn" }, |
| 16560 | { ARM64_INS_ADRP, "adrp" }, |
| 16561 | { ARM64_INS_ADR, "adr" }, |
| 16562 | { ARM64_INS_AESD, "aesd" }, |
| 16563 | { ARM64_INS_AESE, "aese" }, |
| 16564 | { ARM64_INS_AESIMC, "aesimc" }, |
| 16565 | { ARM64_INS_AESMC, "aesmc" }, |
| 16566 | { ARM64_INS_AND, "and" }, |
| 16567 | { ARM64_INS_ASR, "asr" }, |
| 16568 | { ARM64_INS_AT, "at" }, |
| 16569 | { ARM64_INS_BFI, "bfi" }, |
| 16570 | { ARM64_INS_BFM, "bfm" }, |
| 16571 | { ARM64_INS_BFXIL, "bfxil" }, |
| 16572 | { ARM64_INS_BIC, "bic" }, |
| 16573 | { ARM64_INS_BIF, "bif" }, |
| 16574 | { ARM64_INS_BIT, "bit" }, |
| 16575 | { ARM64_INS_BLR, "blr" }, |
| 16576 | { ARM64_INS_BL, "bl" }, |
| 16577 | { ARM64_INS_BRK, "brk" }, |
| 16578 | { ARM64_INS_BR, "br" }, |
| 16579 | { ARM64_INS_BSL, "bsl" }, |
| 16580 | { ARM64_INS_B, "b" }, |
| 16581 | { ARM64_INS_CBNZ, "cbnz" }, |
| 16582 | { ARM64_INS_CBZ, "cbz" }, |
| 16583 | { ARM64_INS_CCMN, "ccmn" }, |
| 16584 | { ARM64_INS_CCMP, "ccmp" }, |
| 16585 | { ARM64_INS_CLREX, "clrex" }, |
| 16586 | { ARM64_INS_CLS, "cls" }, |
| 16587 | { ARM64_INS_CLZ, "clz" }, |
| 16588 | { ARM64_INS_CMEQ, "cmeq" }, |
| 16589 | { ARM64_INS_CMGE, "cmge" }, |
| 16590 | { ARM64_INS_CMGT, "cmgt" }, |
| 16591 | { ARM64_INS_CMHI, "cmhi" }, |
| 16592 | { ARM64_INS_CMHS, "cmhs" }, |
| 16593 | { ARM64_INS_CMLE, "cmle" }, |
| 16594 | { ARM64_INS_CMLT, "cmlt" }, |
| 16595 | { ARM64_INS_CMP, "cmp" }, |
| 16596 | { ARM64_INS_CMTST, "cmtst" }, |
| 16597 | { ARM64_INS_CNT, "cnt" }, |
| 16598 | { ARM64_INS_CRC32B, "crc32b" }, |
| 16599 | { ARM64_INS_CRC32CB, "crc32cb" }, |
| 16600 | { ARM64_INS_CRC32CH, "crc32ch" }, |
| 16601 | { ARM64_INS_CRC32CW, "crc32cw" }, |
| 16602 | { ARM64_INS_CRC32CX, "crc32cx" }, |
| 16603 | { ARM64_INS_CRC32H, "crc32h" }, |
| 16604 | { ARM64_INS_CRC32W, "crc32w" }, |
| 16605 | { ARM64_INS_CRC32X, "crc32x" }, |
| 16606 | { ARM64_INS_CSEL, "csel" }, |
| 16607 | { ARM64_INS_CSINC, "csinc" }, |
| 16608 | { ARM64_INS_CSINV, "csinv" }, |
| 16609 | { ARM64_INS_CSNEG, "csneg" }, |
| 16610 | { ARM64_INS_DCPS1, "dcps1" }, |
| 16611 | { ARM64_INS_DCPS2, "dcps2" }, |
| 16612 | { ARM64_INS_DCPS3, "dcps3" }, |
| 16613 | { ARM64_INS_DC, "dc" }, |
| 16614 | { ARM64_INS_DMB, "dmb" }, |
| 16615 | { ARM64_INS_DRPS, "drps" }, |
| 16616 | { ARM64_INS_DSB, "dsb" }, |
| 16617 | { ARM64_INS_DUP, "dup" }, |
| 16618 | { ARM64_INS_EON, "eon" }, |
| 16619 | { ARM64_INS_EOR, "eor" }, |
| 16620 | { ARM64_INS_ERET, "eret" }, |
| 16621 | { ARM64_INS_EXTR, "extr" }, |
| 16622 | { ARM64_INS_EXT, "ext" }, |
| 16623 | { ARM64_INS_FABD, "fabd" }, |
| 16624 | { ARM64_INS_FABS, "fabs" }, |
| 16625 | { ARM64_INS_FACGE, "facge" }, |
| 16626 | { ARM64_INS_FACGT, "facgt" }, |
| 16627 | { ARM64_INS_FADDP, "faddp" }, |
| 16628 | { ARM64_INS_FADD, "fadd" }, |
| 16629 | { ARM64_INS_FCCMPE, "fccmpe" }, |
| 16630 | { ARM64_INS_FCCMP, "fccmp" }, |
| 16631 | { ARM64_INS_FCMEQ, "fcmeq" }, |
| 16632 | { ARM64_INS_FCMGE, "fcmge" }, |
| 16633 | { ARM64_INS_FCMGT, "fcmgt" }, |
| 16634 | { ARM64_INS_FCMLE, "fcmle" }, |
| 16635 | { ARM64_INS_FCMLT, "fcmlt" }, |
| 16636 | { ARM64_INS_FCMP, "fcmp" }, |
| 16637 | { ARM64_INS_FCMPE, "fcmpe" }, |
| 16638 | { ARM64_INS_FCSEL, "fcsel" }, |
| 16639 | { ARM64_INS_FCVTAS, "fcvtas" }, |
| 16640 | { ARM64_INS_FCVTAU, "fcvtau" }, |
| 16641 | { ARM64_INS_FCVTL, "fcvtl" }, |
| 16642 | { ARM64_INS_FCVTL2, "fcvtl2" }, |
| 16643 | { ARM64_INS_FCVTMS, "fcvtms" }, |
| 16644 | { ARM64_INS_FCVTMU, "fcvtmu" }, |
| 16645 | { ARM64_INS_FCVTN, "fcvtn" }, |
| 16646 | { ARM64_INS_FCVTN2, "fcvtn2" }, |
| 16647 | { ARM64_INS_FCVTNS, "fcvtns" }, |
| 16648 | { ARM64_INS_FCVTNU, "fcvtnu" }, |
| 16649 | { ARM64_INS_FCVTPS, "fcvtps" }, |
| 16650 | { ARM64_INS_FCVTPU, "fcvtpu" }, |
| 16651 | { ARM64_INS_FCVTXN, "fcvtxn" }, |
| 16652 | { ARM64_INS_FCVTXN2, "fcvtxn2" }, |
| 16653 | { ARM64_INS_FCVTZS, "fcvtzs" }, |
| 16654 | { ARM64_INS_FCVTZU, "fcvtzu" }, |
| 16655 | { ARM64_INS_FCVT, "fcvt" }, |
| 16656 | { ARM64_INS_FDIV, "fdiv" }, |
| 16657 | { ARM64_INS_FMADD, "fmadd" }, |
| 16658 | { ARM64_INS_FMAXNMP, "fmaxnmp" }, |
| 16659 | { ARM64_INS_FMAXNMV, "fmaxnmv" }, |
| 16660 | { ARM64_INS_FMAXNM, "fmaxnm" }, |
| 16661 | { ARM64_INS_FMAXP, "fmaxp" }, |
| 16662 | { ARM64_INS_FMAXV, "fmaxv" }, |
| 16663 | { ARM64_INS_FMAX, "fmax" }, |
| 16664 | { ARM64_INS_FMINNMP, "fminnmp" }, |
| 16665 | { ARM64_INS_FMINNMV, "fminnmv" }, |
| 16666 | { ARM64_INS_FMINNM, "fminnm" }, |
| 16667 | { ARM64_INS_FMINP, "fminp" }, |
| 16668 | { ARM64_INS_FMINV, "fminv" }, |
| 16669 | { ARM64_INS_FMIN, "fmin" }, |
| 16670 | { ARM64_INS_FMLA, "fmla" }, |
| 16671 | { ARM64_INS_FMLS, "fmls" }, |
| 16672 | { ARM64_INS_FMOV, "fmov" }, |
| 16673 | { ARM64_INS_FMSUB, "fmsub" }, |
| 16674 | { ARM64_INS_FMULX, "fmulx" }, |
| 16675 | { ARM64_INS_FMUL, "fmul" }, |
| 16676 | { ARM64_INS_FNEG, "fneg" }, |
| 16677 | { ARM64_INS_FNMADD, "fnmadd" }, |
| 16678 | { ARM64_INS_FNMSUB, "fnmsub" }, |
| 16679 | { ARM64_INS_FNMUL, "fnmul" }, |
| 16680 | { ARM64_INS_FRECPE, "frecpe" }, |
| 16681 | { ARM64_INS_FRECPS, "frecps" }, |
| 16682 | { ARM64_INS_FRECPX, "frecpx" }, |
| 16683 | { ARM64_INS_FRINTA, "frinta" }, |
| 16684 | { ARM64_INS_FRINTI, "frinti" }, |
| 16685 | { ARM64_INS_FRINTM, "frintm" }, |
| 16686 | { ARM64_INS_FRINTN, "frintn" }, |
| 16687 | { ARM64_INS_FRINTP, "frintp" }, |
| 16688 | { ARM64_INS_FRINTX, "frintx" }, |
| 16689 | { ARM64_INS_FRINTZ, "frintz" }, |
| 16690 | { ARM64_INS_FRSQRTE, "frsqrte" }, |
| 16691 | { ARM64_INS_FRSQRTS, "frsqrts" }, |
| 16692 | { ARM64_INS_FSQRT, "fsqrt" }, |
| 16693 | { ARM64_INS_FSUB, "fsub" }, |
| 16694 | { ARM64_INS_HINT, "hint" }, |
| 16695 | { ARM64_INS_HLT, "hlt" }, |
| 16696 | { ARM64_INS_HVC, "hvc" }, |
| 16697 | { ARM64_INS_IC, "ic" }, |
| 16698 | { ARM64_INS_INS, "ins" }, |
| 16699 | { ARM64_INS_ISB, "isb" }, |
| 16700 | { ARM64_INS_LD1, "ld1" }, |
| 16701 | { ARM64_INS_LD1R, "ld1r" }, |
| 16702 | { ARM64_INS_LD2, "ld2" }, |
| 16703 | { ARM64_INS_LD2R, "ld2r" }, |
| 16704 | { ARM64_INS_LD3, "ld3" }, |
| 16705 | { ARM64_INS_LD3R, "ld3r" }, |
| 16706 | { ARM64_INS_LD4, "ld4" }, |
| 16707 | { ARM64_INS_LD4R, "ld4r" }, |
| 16708 | { ARM64_INS_LDARB, "ldarb" }, |
| 16709 | { ARM64_INS_LDAR, "ldar" }, |
| 16710 | { ARM64_INS_LDARH, "ldarh" }, |
| 16711 | { ARM64_INS_LDAXP, "ldaxp" }, |
| 16712 | { ARM64_INS_LDAXRB, "ldaxrb" }, |
| 16713 | { ARM64_INS_LDAXR, "ldaxr" }, |
| 16714 | { ARM64_INS_LDAXRH, "ldaxrh" }, |
| 16715 | { ARM64_INS_LDPSW, "ldpsw" }, |
| 16716 | { ARM64_INS_LDRSB, "ldrsb" }, |
| 16717 | { ARM64_INS_LDURSB, "ldursb" }, |
| 16718 | { ARM64_INS_LDRSH, "ldrsh" }, |
| 16719 | { ARM64_INS_LDURSH, "ldursh" }, |
| 16720 | { ARM64_INS_LDRSW, "ldrsw" }, |
| 16721 | { ARM64_INS_LDR, "ldr" }, |
| 16722 | { ARM64_INS_LDTRSB, "ldtrsb" }, |
| 16723 | { ARM64_INS_LDTRSH, "ldtrsh" }, |
| 16724 | { ARM64_INS_LDTRSW, "ldtrsw" }, |
| 16725 | { ARM64_INS_LDURSW, "ldursw" }, |
| 16726 | { ARM64_INS_LDXP, "ldxp" }, |
| 16727 | { ARM64_INS_LDXRB, "ldxrb" }, |
| 16728 | { ARM64_INS_LDXR, "ldxr" }, |
| 16729 | { ARM64_INS_LDXRH, "ldxrh" }, |
| 16730 | { ARM64_INS_LDRH, "ldrh" }, |
| 16731 | { ARM64_INS_LDURH, "ldurh" }, |
| 16732 | { ARM64_INS_STRH, "strh" }, |
| 16733 | { ARM64_INS_STURH, "sturh" }, |
| 16734 | { ARM64_INS_LDTRH, "ldtrh" }, |
| 16735 | { ARM64_INS_STTRH, "sttrh" }, |
| 16736 | { ARM64_INS_LDUR, "ldur" }, |
| 16737 | { ARM64_INS_STR, "str" }, |
| 16738 | { ARM64_INS_STUR, "stur" }, |
| 16739 | { ARM64_INS_LDTR, "ldtr" }, |
| 16740 | { ARM64_INS_STTR, "sttr" }, |
| 16741 | { ARM64_INS_LDRB, "ldrb" }, |
| 16742 | { ARM64_INS_LDURB, "ldurb" }, |
| 16743 | { ARM64_INS_STRB, "strb" }, |
| 16744 | { ARM64_INS_STURB, "sturb" }, |
| 16745 | { ARM64_INS_LDTRB, "ldtrb" }, |
| 16746 | { ARM64_INS_STTRB, "sttrb" }, |
| 16747 | { ARM64_INS_LDP, "ldp" }, |
| 16748 | { ARM64_INS_LDNP, "ldnp" }, |
| 16749 | { ARM64_INS_STNP, "stnp" }, |
| 16750 | { ARM64_INS_STP, "stp" }, |
| 16751 | { ARM64_INS_LSL, "lsl" }, |
| 16752 | { ARM64_INS_LSR, "lsr" }, |
| 16753 | { ARM64_INS_MADD, "madd" }, |
| 16754 | { ARM64_INS_MLA, "mla" }, |
| 16755 | { ARM64_INS_MLS, "mls" }, |
| 16756 | { ARM64_INS_MOVI, "movi" }, |
| 16757 | { ARM64_INS_MOVK, "movk" }, |
| 16758 | { ARM64_INS_MOVN, "movn" }, |
| 16759 | { ARM64_INS_MOVZ, "movz" }, |
| 16760 | { ARM64_INS_MRS, "mrs" }, |
| 16761 | { ARM64_INS_MSR, "msr" }, |
| 16762 | { ARM64_INS_MSUB, "msub" }, |
| 16763 | { ARM64_INS_MUL, "mul" }, |
| 16764 | { ARM64_INS_MVNI, "mvni" }, |
| 16765 | { ARM64_INS_MVN, "mvn" }, |
| 16766 | { ARM64_INS_NEG, "neg" }, |
| 16767 | { ARM64_INS_NOT, "not" }, |
| 16768 | { ARM64_INS_ORN, "orn" }, |
| 16769 | { ARM64_INS_ORR, "orr" }, |
| 16770 | { ARM64_INS_PMULL2, "pmull2" }, |
| 16771 | { ARM64_INS_PMULL, "pmull" }, |
| 16772 | { ARM64_INS_PMUL, "pmul" }, |
| 16773 | { ARM64_INS_PRFM, "prfm" }, |
| 16774 | { ARM64_INS_PRFUM, "prfum" }, |
| 16775 | { ARM64_INS_SQRSHRUN2, "sqrshrun2" }, |
| 16776 | { ARM64_INS_SQRSHRUN, "sqrshrun" }, |
| 16777 | { ARM64_INS_SQSHRUN2, "sqshrun2" }, |
| 16778 | { ARM64_INS_SQSHRUN, "sqshrun" }, |
| 16779 | { ARM64_INS_RADDHN2, "raddhn2" }, |
| 16780 | { ARM64_INS_RADDHN, "raddhn" }, |
| 16781 | { ARM64_INS_RBIT, "rbit" }, |
| 16782 | { ARM64_INS_RET, "ret" }, |
| 16783 | { ARM64_INS_REV16, "rev16" }, |
| 16784 | { ARM64_INS_REV32, "rev32" }, |
| 16785 | { ARM64_INS_REV64, "rev64" }, |
| 16786 | { ARM64_INS_REV, "rev" }, |
| 16787 | { ARM64_INS_ROR, "ror" }, |
| 16788 | { ARM64_INS_RSHRN2, "rshrn2" }, |
| 16789 | { ARM64_INS_RSHRN, "rshrn" }, |
| 16790 | { ARM64_INS_RSUBHN2, "rsubhn2" }, |
| 16791 | { ARM64_INS_RSUBHN, "rsubhn" }, |
| 16792 | { ARM64_INS_SABAL2, "sabal2" }, |
| 16793 | { ARM64_INS_SABAL, "sabal" }, |
| 16794 | { ARM64_INS_SABA, "saba" }, |
| 16795 | { ARM64_INS_SABDL2, "sabdl2" }, |
| 16796 | { ARM64_INS_SABDL, "sabdl" }, |
| 16797 | { ARM64_INS_SABD, "sabd" }, |
| 16798 | { ARM64_INS_SADALP, "sadalp" }, |
| 16799 | { ARM64_INS_SADDL2, "saddl2" }, |
| 16800 | { ARM64_INS_SADDLP, "saddlp" }, |
| 16801 | { ARM64_INS_SADDLV, "saddlv" }, |
| 16802 | { ARM64_INS_SADDL, "saddl" }, |
| 16803 | { ARM64_INS_SADDW2, "saddw2" }, |
| 16804 | { ARM64_INS_SADDW, "saddw" }, |
| 16805 | { ARM64_INS_SBC, "sbc" }, |
| 16806 | { ARM64_INS_SBFIZ, "sbfiz" }, |
| 16807 | { ARM64_INS_SBFM, "sbfm" }, |
| 16808 | { ARM64_INS_SBFX, "sbfx" }, |
| 16809 | { ARM64_INS_SCVTF, "scvtf" }, |
| 16810 | { ARM64_INS_SDIV, "sdiv" }, |
| 16811 | { ARM64_INS_SHA1C, "sha1c" }, |
| 16812 | { ARM64_INS_SHA1H, "sha1h" }, |
| 16813 | { ARM64_INS_SHA1M, "sha1m" }, |
| 16814 | { ARM64_INS_SHA1P, "sha1p" }, |
| 16815 | { ARM64_INS_SHA1SU0, "sha1su0" }, |
| 16816 | { ARM64_INS_SHA1SU1, "sha1su1" }, |
| 16817 | { ARM64_INS_SHA256H, "sha256h" }, |
| 16818 | { ARM64_INS_SHA256H2, "sha256h2" }, |
| 16819 | { ARM64_INS_SHA256SU0, "sha256su0" }, |
| 16820 | { ARM64_INS_SHA256SU1, "sha256su1" }, |
| 16821 | { ARM64_INS_SHADD, "shadd" }, |
| 16822 | { ARM64_INS_SHLL2, "shll2" }, |
| 16823 | { ARM64_INS_SHLL, "shll" }, |
| 16824 | { ARM64_INS_SHL, "shl" }, |
| 16825 | { ARM64_INS_SHRN2, "shrn2" }, |
| 16826 | { ARM64_INS_SHRN, "shrn" }, |
| 16827 | { ARM64_INS_SHSUB, "shsub" }, |
| 16828 | { ARM64_INS_SLI, "sli" }, |
| 16829 | { ARM64_INS_SMADDL, "smaddl" }, |
| 16830 | { ARM64_INS_SMAXP, "smaxp" }, |
| 16831 | { ARM64_INS_SMAXV, "smaxv" }, |
| 16832 | { ARM64_INS_SMAX, "smax" }, |
| 16833 | { ARM64_INS_SMC, "smc" }, |
| 16834 | { ARM64_INS_SMINP, "sminp" }, |
| 16835 | { ARM64_INS_SMINV, "sminv" }, |
| 16836 | { ARM64_INS_SMIN, "smin" }, |
| 16837 | { ARM64_INS_SMLAL2, "smlal2" }, |
| 16838 | { ARM64_INS_SMLAL, "smlal" }, |
| 16839 | { ARM64_INS_SMLSL2, "smlsl2" }, |
| 16840 | { ARM64_INS_SMLSL, "smlsl" }, |
| 16841 | { ARM64_INS_SMOV, "smov" }, |
| 16842 | { ARM64_INS_SMSUBL, "smsubl" }, |
| 16843 | { ARM64_INS_SMULH, "smulh" }, |
| 16844 | { ARM64_INS_SMULL2, "smull2" }, |
| 16845 | { ARM64_INS_SMULL, "smull" }, |
| 16846 | { ARM64_INS_SQABS, "sqabs" }, |
| 16847 | { ARM64_INS_SQADD, "sqadd" }, |
| 16848 | { ARM64_INS_SQDMLAL2, "sqdmlal2" }, |
| 16849 | { ARM64_INS_SQDMLAL, "sqdmlal" }, |
| 16850 | { ARM64_INS_SQDMLSL2, "sqdmlsl2" }, |
| 16851 | { ARM64_INS_SQDMLSL, "sqdmlsl" }, |
| 16852 | { ARM64_INS_SQDMULH, "sqdmulh" }, |
| 16853 | { ARM64_INS_SQDMULL2, "sqdmull2" }, |
| 16854 | { ARM64_INS_SQDMULL, "sqdmull" }, |
| 16855 | { ARM64_INS_SQNEG, "sqneg" }, |
| 16856 | { ARM64_INS_SQRDMULH, "sqrdmulh" }, |
| 16857 | { ARM64_INS_SQRSHL, "sqrshl" }, |
| 16858 | { ARM64_INS_SQRSHRN, "sqrshrn" }, |
| 16859 | { ARM64_INS_SQRSHRN2, "sqrshrn2" }, |
| 16860 | { ARM64_INS_SQSHLU, "sqshlu" }, |
| 16861 | { ARM64_INS_SQSHL, "sqshl" }, |
| 16862 | { ARM64_INS_SQSHRN, "sqshrn" }, |
| 16863 | { ARM64_INS_SQSHRN2, "sqshrn2" }, |
| 16864 | { ARM64_INS_SQSUB, "sqsub" }, |
| 16865 | { ARM64_INS_SQXTN, "sqxtn" }, |
| 16866 | { ARM64_INS_SQXTN2, "sqxtn2" }, |
| 16867 | { ARM64_INS_SQXTUN, "sqxtun" }, |
| 16868 | { ARM64_INS_SQXTUN2, "sqxtun2" }, |
| 16869 | { ARM64_INS_SRHADD, "srhadd" }, |
| 16870 | { ARM64_INS_SRI, "sri" }, |
| 16871 | { ARM64_INS_SRSHL, "srshl" }, |
| 16872 | { ARM64_INS_SRSHR, "srshr" }, |
| 16873 | { ARM64_INS_SRSRA, "srsra" }, |
| 16874 | { ARM64_INS_SSHLL2, "sshll2" }, |
| 16875 | { ARM64_INS_SSHLL, "sshll" }, |
| 16876 | { ARM64_INS_SSHL, "sshl" }, |
| 16877 | { ARM64_INS_SSHR, "sshr" }, |
| 16878 | { ARM64_INS_SSRA, "ssra" }, |
| 16879 | { ARM64_INS_SSUBL2, "ssubl2" }, |
| 16880 | { ARM64_INS_SSUBL, "ssubl" }, |
| 16881 | { ARM64_INS_SSUBW2, "ssubw2" }, |
| 16882 | { ARM64_INS_SSUBW, "ssubw" }, |
| 16883 | { ARM64_INS_ST1, "st1" }, |
| 16884 | { ARM64_INS_ST2, "st2" }, |
| 16885 | { ARM64_INS_ST3, "st3" }, |
| 16886 | { ARM64_INS_ST4, "st4" }, |
| 16887 | { ARM64_INS_STLRB, "stlrb" }, |
| 16888 | { ARM64_INS_STLR, "stlr" }, |
| 16889 | { ARM64_INS_STLRH, "stlrh" }, |
| 16890 | { ARM64_INS_STLXP, "stlxp" }, |
| 16891 | { ARM64_INS_STLXRB, "stlxrb" }, |
| 16892 | { ARM64_INS_STLXR, "stlxr" }, |
| 16893 | { ARM64_INS_STLXRH, "stlxrh" }, |
| 16894 | { ARM64_INS_STXP, "stxp" }, |
| 16895 | { ARM64_INS_STXRB, "stxrb" }, |
| 16896 | { ARM64_INS_STXR, "stxr" }, |
| 16897 | { ARM64_INS_STXRH, "stxrh" }, |
| 16898 | { ARM64_INS_SUBHN2, "subhn2" }, |
| 16899 | { ARM64_INS_SUBHN, "subhn" }, |
| 16900 | { ARM64_INS_SUB, "sub" }, |
| 16901 | { ARM64_INS_SUQADD, "suqadd" }, |
| 16902 | { ARM64_INS_SVC, "svc" }, |
| 16903 | { ARM64_INS_SXTB, "sxtb" }, |
| 16904 | { ARM64_INS_SXTH, "sxth" }, |
| 16905 | { ARM64_INS_SXTW, "sxtw" }, |
| 16906 | { ARM64_INS_SYSL, "sysl" }, |
| 16907 | { ARM64_INS_SYS, "sys" }, |
| 16908 | { ARM64_INS_TBL, "tbl" }, |
| 16909 | { ARM64_INS_TBNZ, "tbnz" }, |
| 16910 | { ARM64_INS_TBX, "tbx" }, |
| 16911 | { ARM64_INS_TBZ, "tbz" }, |
| 16912 | { ARM64_INS_TLBI, "tlbi" }, |
| 16913 | { ARM64_INS_TRN1, "trn1" }, |
| 16914 | { ARM64_INS_TRN2, "trn2" }, |
| 16915 | { ARM64_INS_TST, "tst" }, |
| 16916 | { ARM64_INS_UABAL2, "uabal2" }, |
| 16917 | { ARM64_INS_UABAL, "uabal" }, |
| 16918 | { ARM64_INS_UABA, "uaba" }, |
| 16919 | { ARM64_INS_UABDL2, "uabdl2" }, |
| 16920 | { ARM64_INS_UABDL, "uabdl" }, |
| 16921 | { ARM64_INS_UABD, "uabd" }, |
| 16922 | { ARM64_INS_UADALP, "uadalp" }, |
| 16923 | { ARM64_INS_UADDL2, "uaddl2" }, |
| 16924 | { ARM64_INS_UADDLP, "uaddlp" }, |
| 16925 | { ARM64_INS_UADDLV, "uaddlv" }, |
| 16926 | { ARM64_INS_UADDL, "uaddl" }, |
| 16927 | { ARM64_INS_UADDW2, "uaddw2" }, |
| 16928 | { ARM64_INS_UADDW, "uaddw" }, |
| 16929 | { ARM64_INS_UBFIZ, "ubfiz" }, |
| 16930 | { ARM64_INS_UBFM, "ubfm" }, |
| 16931 | { ARM64_INS_UBFX, "ubfx" }, |
| 16932 | { ARM64_INS_UCVTF, "ucvtf" }, |
| 16933 | { ARM64_INS_UDIV, "udiv" }, |
| 16934 | { ARM64_INS_UHADD, "uhadd" }, |
| 16935 | { ARM64_INS_UHSUB, "uhsub" }, |
| 16936 | { ARM64_INS_UMADDL, "umaddl" }, |
| 16937 | { ARM64_INS_UMAXP, "umaxp" }, |
| 16938 | { ARM64_INS_UMAXV, "umaxv" }, |
| 16939 | { ARM64_INS_UMAX, "umax" }, |
| 16940 | { ARM64_INS_UMINP, "uminp" }, |
| 16941 | { ARM64_INS_UMINV, "uminv" }, |
| 16942 | { ARM64_INS_UMIN, "umin" }, |
| 16943 | { ARM64_INS_UMLAL2, "umlal2" }, |
| 16944 | { ARM64_INS_UMLAL, "umlal" }, |
| 16945 | { ARM64_INS_UMLSL2, "umlsl2" }, |
| 16946 | { ARM64_INS_UMLSL, "umlsl" }, |
| 16947 | { ARM64_INS_UMOV, "umov" }, |
| 16948 | { ARM64_INS_UMSUBL, "umsubl" }, |
| 16949 | { ARM64_INS_UMULH, "umulh" }, |
| 16950 | { ARM64_INS_UMULL2, "umull2" }, |
| 16951 | { ARM64_INS_UMULL, "umull" }, |
| 16952 | { ARM64_INS_UQADD, "uqadd" }, |
| 16953 | { ARM64_INS_UQRSHL, "uqrshl" }, |
| 16954 | { ARM64_INS_UQRSHRN, "uqrshrn" }, |
| 16955 | { ARM64_INS_UQRSHRN2, "uqrshrn2" }, |
| 16956 | { ARM64_INS_UQSHL, "uqshl" }, |
| 16957 | { ARM64_INS_UQSHRN, "uqshrn" }, |
| 16958 | { ARM64_INS_UQSHRN2, "uqshrn2" }, |
| 16959 | { ARM64_INS_UQSUB, "uqsub" }, |
| 16960 | { ARM64_INS_UQXTN, "uqxtn" }, |
| 16961 | { ARM64_INS_UQXTN2, "uqxtn2" }, |
| 16962 | { ARM64_INS_URECPE, "urecpe" }, |
| 16963 | { ARM64_INS_URHADD, "urhadd" }, |
| 16964 | { ARM64_INS_URSHL, "urshl" }, |
| 16965 | { ARM64_INS_URSHR, "urshr" }, |
| 16966 | { ARM64_INS_URSQRTE, "ursqrte" }, |
| 16967 | { ARM64_INS_URSRA, "ursra" }, |
| 16968 | { ARM64_INS_USHLL2, "ushll2" }, |
| 16969 | { ARM64_INS_USHLL, "ushll" }, |
| 16970 | { ARM64_INS_USHL, "ushl" }, |
| 16971 | { ARM64_INS_USHR, "ushr" }, |
| 16972 | { ARM64_INS_USQADD, "usqadd" }, |
| 16973 | { ARM64_INS_USRA, "usra" }, |
| 16974 | { ARM64_INS_USUBL2, "usubl2" }, |
| 16975 | { ARM64_INS_USUBL, "usubl" }, |
| 16976 | { ARM64_INS_USUBW2, "usubw2" }, |
| 16977 | { ARM64_INS_USUBW, "usubw" }, |
| 16978 | { ARM64_INS_UXTB, "uxtb" }, |
| 16979 | { ARM64_INS_UXTH, "uxth" }, |
| 16980 | { ARM64_INS_UZP1, "uzp1" }, |
| 16981 | { ARM64_INS_UZP2, "uzp2" }, |
| 16982 | { ARM64_INS_XTN, "xtn" }, |
| 16983 | { ARM64_INS_XTN2, "xtn2" }, |
| 16984 | { ARM64_INS_ZIP1, "zip1" }, |
| 16985 | { ARM64_INS_ZIP2, "zip2" }, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 16986 | }; |
| 16987 | |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 16988 | // map *S & alias instructions back to original id |
| 16989 | static name_map alias_insn_name_maps[] = { |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 16990 | { ARM64_INS_ADC, "adcs" }, |
| 16991 | { ARM64_INS_AND, "ands" }, |
| 16992 | { ARM64_INS_ADD, "adds" }, |
| 16993 | { ARM64_INS_BIC, "bics" }, |
| 16994 | { ARM64_INS_SBC, "sbcs" }, |
| 16995 | { ARM64_INS_SUB, "subs" }, |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 16996 | |
| 16997 | // alias insn |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 16998 | { ARM64_INS_MNEG, "mneg" }, |
| 16999 | { ARM64_INS_UMNEGL, "umnegl" }, |
| 17000 | { ARM64_INS_SMNEGL, "smnegl" }, |
| 17001 | { ARM64_INS_MOV, "mov" }, |
| 17002 | { ARM64_INS_NOP, "nop" }, |
| 17003 | { ARM64_INS_YIELD, "yield" }, |
| 17004 | { ARM64_INS_WFE, "wfe" }, |
| 17005 | { ARM64_INS_WFI, "wfi" }, |
| 17006 | { ARM64_INS_SEV, "sev" }, |
| 17007 | { ARM64_INS_SEVL, "sevl" }, |
| 17008 | { ARM64_INS_NGC, "ngc" }, |
| 17009 | { ARM64_INS_NGCS, "ngcs" }, |
| 17010 | { ARM64_INS_NEGS, "negs" }, |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 17011 | }; |
| 17012 | |
pancake | f0e4eed | 2013-12-11 22:14:42 +0100 | [diff] [blame] | 17013 | const char *AArch64_insn_name(csh handle, unsigned int id) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 17014 | { |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 17015 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | f6c7cbc | 2014-03-12 12:50:54 +0800 | [diff] [blame] | 17016 | unsigned int i; |
| 17017 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 17018 | if (id >= ARM64_INS_MAX) |
| 17019 | return NULL; |
| 17020 | |
Nguyen Anh Quynh | dcbe0f8 | 2014-01-12 10:11:36 +0800 | [diff] [blame] | 17021 | if (id < ARR_SIZE(insn_name_maps)) |
| 17022 | return insn_name_maps[id].name; |
| 17023 | |
| 17024 | // then find alias insn |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 17025 | for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { |
| 17026 | if (alias_insn_name_maps[i].id == id) |
| 17027 | return alias_insn_name_maps[i].name; |
| 17028 | } |
| 17029 | |
Nguyen Anh Quynh | dcbe0f8 | 2014-01-12 10:11:36 +0800 | [diff] [blame] | 17030 | // not found |
| 17031 | return NULL; |
Nguyen Anh Quynh | fc83a43 | 2014-02-22 23:26:27 +0800 | [diff] [blame] | 17032 | #else |
| 17033 | return NULL; |
| 17034 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 17035 | } |
| 17036 | |
Nguyen Anh Quynh | 650f96c | 2014-07-08 08:59:27 +0800 | [diff] [blame^] | 17037 | #ifndef CAPSTONE_DIET |
| 17038 | static name_map group_name_maps[] = { |
| 17039 | { ARM64_GRP_INVALID, NULL }, |
| 17040 | { ARM64_GRP_CRYPTO, "crypto" }, |
| 17041 | { ARM64_GRP_FPARMV8, "fparmv8" }, |
| 17042 | { ARM64_GRP_NEON, "neon" }, |
| 17043 | |
| 17044 | { ARM64_GRP_JUMP, "jump" }, |
| 17045 | }; |
| 17046 | #endif |
| 17047 | |
| 17048 | const char *AArch64_group_name(csh handle, unsigned int id) |
| 17049 | { |
| 17050 | #ifndef CAPSTONE_DIET |
| 17051 | if (id >= ARM64_GRP_MAX) |
| 17052 | return NULL; |
| 17053 | |
| 17054 | return group_name_maps[id].name; |
| 17055 | #else |
| 17056 | return NULL; |
| 17057 | #endif |
| 17058 | } |
| 17059 | |
Nguyen Anh Quynh | 6b7abe3 | 2013-11-30 00:54:24 +0800 | [diff] [blame] | 17060 | // map instruction name to public instruction ID |
pancake | f0e4eed | 2013-12-11 22:14:42 +0100 | [diff] [blame] | 17061 | arm64_reg AArch64_map_insn(const char *name) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 17062 | { |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 17063 | // NOTE: skip first NULL name in insn_name_maps |
| 17064 | int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); |
| 17065 | |
| 17066 | if (i == -1) |
| 17067 | // try again with 'special' insn that is not available in insn_name_maps |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame] | 17068 | i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 17069 | |
| 17070 | return (i != -1)? i : ARM64_REG_INVALID; |
| 17071 | } |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 17072 | |
| 17073 | #endif |