blob: 4e81832169ac714fd70ce8063f1c1ce19dd4fd2a [file] [log] [blame]
Marat Dukhand51d3952018-03-17 19:18:06 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
8 ASSERT_EQ(8, cpuinfo_get_processors_count());
9}
10
11TEST(PROCESSORS, non_null) {
12 ASSERT_TRUE(cpuinfo_get_processors());
13}
14
15TEST(PROCESSORS, smt_id) {
16 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
18 }
19}
20
21TEST(PROCESSORS, core) {
22 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
24 }
25}
26
Marat Dukhan2b307932018-03-18 16:15:36 -070027TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 switch (i) {
30 case 0:
31 case 1:
32 case 2:
33 case 3:
34 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
35 break;
36 case 4:
37 case 5:
38 case 6:
39 case 7:
40 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
41 break;
42 }
43 }
44}
45
Marat Dukhand51d3952018-03-17 19:18:06 -070046TEST(PROCESSORS, package) {
47 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
48 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
49 }
50}
51
52TEST(PROCESSORS, linux_id) {
53 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
54 switch (i) {
55 case 0:
56 case 1:
57 case 2:
58 case 3:
59 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
60 break;
61 case 4:
62 case 5:
63 case 6:
64 case 7:
65 ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id);
66 break;
67 }
68 }
69}
70
71TEST(PROCESSORS, l1i) {
72 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
73 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
74 }
75}
76
77TEST(PROCESSORS, l1d) {
78 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
79 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
80 }
81}
82
Marat Dukhan8b814e32018-04-29 02:47:41 -070083TEST(PROCESSORS, l2) {
Marat Dukhand51d3952018-03-17 19:18:06 -070084 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2b307932018-03-18 16:15:36 -070085 ASSERT_EQ(cpuinfo_get_l2_cache(i), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhand51d3952018-03-17 19:18:06 -070086 }
87}
88
Marat Dukhan8b814e32018-04-29 02:47:41 -070089TEST(PROCESSORS, l3) {
Marat Dukhand51d3952018-03-17 19:18:06 -070090 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2b307932018-03-18 16:15:36 -070091 ASSERT_EQ(cpuinfo_get_l3_cache(0), cpuinfo_get_processor(i)->cache.l3);
Marat Dukhand51d3952018-03-17 19:18:06 -070092 }
93}
94
95TEST(PROCESSORS, l4) {
96 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
97 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
98 }
99}
100
101TEST(CORES, count) {
102 ASSERT_EQ(8, cpuinfo_get_cores_count());
103}
104
105TEST(CORES, non_null) {
106 ASSERT_TRUE(cpuinfo_get_cores());
107}
108
109TEST(CORES, processor_start) {
110 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
111 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
112 }
113}
114
115TEST(CORES, processor_count) {
116 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
117 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
118 }
119}
120
121TEST(CORES, core_id) {
122 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
123 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
124 }
125}
126
Marat Dukhan2b307932018-03-18 16:15:36 -0700127TEST(CORES, cluster) {
128 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
129 switch (i) {
130 case 0:
131 case 1:
132 case 2:
133 case 3:
134 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
135 break;
136 case 4:
137 case 5:
138 case 6:
139 case 7:
140 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
141 break;
142 }
143 }
144}
145
Marat Dukhand51d3952018-03-17 19:18:06 -0700146TEST(CORES, package) {
147 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
148 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
149 }
150}
151
152TEST(CORES, vendor) {
153 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
154 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
155 }
156}
157
158TEST(CORES, uarch) {
159 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
160 switch (i) {
161 case 0:
162 case 1:
163 case 2:
164 case 3:
165 ASSERT_EQ(cpuinfo_uarch_cortex_a75, cpuinfo_get_core(i)->uarch);
166 break;
167 case 4:
168 case 5:
169 case 6:
170 case 7:
171 ASSERT_EQ(cpuinfo_uarch_cortex_a55, cpuinfo_get_core(i)->uarch);
172 break;
173 }
174 }
175}
176
177TEST(CORES, midr) {
178 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
179 switch (i) {
180 case 0:
181 case 1:
182 case 2:
183 case 3:
184 ASSERT_EQ(UINT32_C(0x516F802D), cpuinfo_get_core(i)->midr);
185 break;
186 case 4:
187 case 5:
188 case 6:
189 case 7:
190 ASSERT_EQ(UINT32_C(0x517F803C), cpuinfo_get_core(i)->midr);
191 break;
192 }
193 }
194}
195
196TEST(CORES, DISABLED_frequency) {
197 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
198 switch (i) {
199 case 0:
200 case 1:
201 case 2:
202 case 3:
203 ASSERT_EQ(UINT64_C(2803200000), cpuinfo_get_core(i)->frequency);
204 break;
205 case 4:
206 case 5:
207 case 6:
208 case 7:
209 ASSERT_EQ(UINT64_C(1766400000), cpuinfo_get_core(i)->frequency);
210 break;
211 }
212 }
213}
214
Marat Dukhandbc78402018-03-18 22:49:35 -0700215TEST(CLUSTERS, count) {
216 ASSERT_EQ(2, cpuinfo_get_clusters_count());
217}
218
219TEST(CLUSTERS, non_null) {
220 ASSERT_TRUE(cpuinfo_get_clusters());
221}
222
223TEST(CLUSTERS, processor_start) {
224 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
225 switch (i) {
226 case 0:
227 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start);
228 break;
229 case 1:
230 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_start);
231 break;
232 }
233 }
234}
235
236TEST(CLUSTERS, processor_count) {
237 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
238 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count);
239 }
240}
241
242TEST(CLUSTERS, core_start) {
243 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
244 switch (i) {
245 case 0:
246 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start);
247 break;
248 case 1:
249 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_start);
250 break;
251 }
252 }
253}
254
255TEST(CLUSTERS, core_count) {
256 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
257 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count);
258 }
259}
260
261TEST(CLUSTERS, cluster_id) {
262 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
263 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id);
264 }
265}
266
267TEST(CLUSTERS, package) {
268 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
269 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package);
270 }
271}
272
273TEST(CLUSTERS, vendor) {
274 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
275 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor);
276 }
277}
278
279TEST(CLUSTERS, uarch) {
280 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
281 switch (i) {
282 case 0:
283 ASSERT_EQ(cpuinfo_uarch_cortex_a75, cpuinfo_get_cluster(i)->uarch);
284 break;
285 case 1:
286 ASSERT_EQ(cpuinfo_uarch_cortex_a55, cpuinfo_get_cluster(i)->uarch);
287 break;
288 }
289 }
290}
291
292TEST(CLUSTERS, midr) {
293 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
294 switch (i) {
295 case 0:
296 ASSERT_EQ(UINT32_C(0x516F802D), cpuinfo_get_cluster(i)->midr);
297 break;
298 case 1:
299 ASSERT_EQ(UINT32_C(0x517F803C), cpuinfo_get_cluster(i)->midr);
300 break;
301 }
302 }
303}
304
305TEST(CLUSTERS, DISABLED_frequency) {
306 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
307 switch (i) {
308 case 0:
309 ASSERT_EQ(UINT64_C(2803200000), cpuinfo_get_cluster(i)->frequency);
310 break;
311 case 1:
312 ASSERT_EQ(UINT64_C(1766400000), cpuinfo_get_cluster(i)->frequency);
313 break;
314 }
315 }
316}
317
Marat Dukhand51d3952018-03-17 19:18:06 -0700318TEST(PACKAGES, count) {
319 ASSERT_EQ(1, cpuinfo_get_packages_count());
320}
321
322TEST(PACKAGES, name) {
323 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
324 ASSERT_EQ("Qualcomm Snapdragon 845",
325 std::string(cpuinfo_get_package(i)->name,
326 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
327 }
328}
329
330TEST(PACKAGES, gpu_name) {
331 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
332 ASSERT_EQ("Qualcomm Adreno 630",
333 std::string(cpuinfo_get_package(i)->gpu_name,
334 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
335 }
336}
337
338TEST(PACKAGES, processor_start) {
339 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
340 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
341 }
342}
343
344TEST(PACKAGES, processor_count) {
345 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
346 ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count);
347 }
348}
349
350TEST(PACKAGES, core_start) {
351 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
352 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
353 }
354}
355
356TEST(PACKAGES, core_count) {
357 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
358 ASSERT_EQ(8, cpuinfo_get_package(i)->core_count);
359 }
360}
361
Marat Dukhan2b307932018-03-18 16:15:36 -0700362TEST(PACKAGES, cluster_start) {
363 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
364 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
365 }
366}
367
368TEST(PACKAGES, cluster_count) {
369 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
370 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
371 }
372}
373
Marat Dukhand51d3952018-03-17 19:18:06 -0700374TEST(ISA, thumb) {
375 #if CPUINFO_ARCH_ARM
376 ASSERT_TRUE(cpuinfo_has_arm_thumb());
377 #elif CPUINFO_ARCH_ARM64
378 ASSERT_FALSE(cpuinfo_has_arm_thumb());
379 #endif
380}
381
382TEST(ISA, thumb2) {
383 #if CPUINFO_ARCH_ARM
384 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
385 #elif CPUINFO_ARCH_ARM64
386 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
387 #endif
388}
389
390TEST(ISA, armv5e) {
391 #if CPUINFO_ARCH_ARM
392 ASSERT_TRUE(cpuinfo_has_arm_v5e());
393 #elif CPUINFO_ARCH_ARM64
394 ASSERT_FALSE(cpuinfo_has_arm_v5e());
395 #endif
396}
397
398TEST(ISA, armv6) {
399 #if CPUINFO_ARCH_ARM
400 ASSERT_TRUE(cpuinfo_has_arm_v6());
401 #elif CPUINFO_ARCH_ARM64
402 ASSERT_FALSE(cpuinfo_has_arm_v6());
403 #endif
404}
405
406TEST(ISA, armv6k) {
407 #if CPUINFO_ARCH_ARM
408 ASSERT_TRUE(cpuinfo_has_arm_v6k());
409 #elif CPUINFO_ARCH_ARM64
410 ASSERT_FALSE(cpuinfo_has_arm_v6k());
411 #endif
412}
413
414TEST(ISA, armv7) {
415 #if CPUINFO_ARCH_ARM
416 ASSERT_TRUE(cpuinfo_has_arm_v7());
417 #elif CPUINFO_ARCH_ARM64
418 ASSERT_FALSE(cpuinfo_has_arm_v7());
419 #endif
420}
421
422TEST(ISA, armv7mp) {
423 #if CPUINFO_ARCH_ARM
424 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
425 #elif CPUINFO_ARCH_ARM64
426 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
427 #endif
428}
429
430TEST(ISA, idiv) {
431 ASSERT_TRUE(cpuinfo_has_arm_idiv());
432}
433
434TEST(ISA, vfpv2) {
435 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
436}
437
438TEST(ISA, vfpv3) {
439 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
440}
441
442TEST(ISA, vfpv3_d32) {
443 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
444}
445
446TEST(ISA, vfpv3_fp16) {
447 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
448}
449
450TEST(ISA, vfpv3_fp16_d32) {
451 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
452}
453
454TEST(ISA, vfpv4) {
455 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
456}
457
458TEST(ISA, vfpv4_d32) {
459 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
460}
461
462TEST(ISA, wmmx) {
463 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
464}
465
466TEST(ISA, wmmx2) {
467 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
468}
469
470TEST(ISA, neon) {
471 ASSERT_TRUE(cpuinfo_has_arm_neon());
472}
473
474TEST(ISA, neon_fp16) {
475 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
476}
477
478TEST(ISA, neon_fma) {
479 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
480}
481
482TEST(ISA, atomics) {
483 #if CPUINFO_ARCH_ARM
484 ASSERT_FALSE(cpuinfo_has_arm_atomics());
485 #elif CPUINFO_ARCH_ARM64
486 ASSERT_TRUE(cpuinfo_has_arm_atomics());
487 #endif
488}
489
490TEST(ISA, neon_rdm) {
Marat Dukhan292e9b52018-04-19 22:11:37 -0700491 ASSERT_TRUE(cpuinfo_has_arm_neon_rdm());
Marat Dukhand51d3952018-03-17 19:18:06 -0700492}
493
494TEST(ISA, fp16_arith) {
Marat Dukhan292e9b52018-04-19 22:11:37 -0700495 ASSERT_TRUE(cpuinfo_has_arm_fp16_arith());
Marat Dukhand51d3952018-03-17 19:18:06 -0700496}
497
498TEST(ISA, jscvt) {
499 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
500}
501
502TEST(ISA, fcma) {
503 ASSERT_FALSE(cpuinfo_has_arm_fcma());
504}
505
506TEST(ISA, aes) {
507 ASSERT_TRUE(cpuinfo_has_arm_aes());
508}
509
510TEST(ISA, sha1) {
511 ASSERT_TRUE(cpuinfo_has_arm_sha1());
512}
513
514TEST(ISA, sha2) {
515 ASSERT_TRUE(cpuinfo_has_arm_sha2());
516}
517
518TEST(ISA, pmull) {
519 ASSERT_TRUE(cpuinfo_has_arm_pmull());
520}
521
522TEST(ISA, crc32) {
523 ASSERT_TRUE(cpuinfo_has_arm_crc32());
524}
525
526TEST(L1I, count) {
527 ASSERT_EQ(8, cpuinfo_get_l1i_caches_count());
528}
529
530TEST(L1I, non_null) {
531 ASSERT_TRUE(cpuinfo_get_l1i_caches());
532}
533
Marat Dukhan8b814e32018-04-29 02:47:41 -0700534TEST(L1I, size) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700535 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
536 switch (i) {
537 case 0:
538 case 1:
539 case 2:
540 case 3:
541 ASSERT_EQ(64 * 1024, cpuinfo_get_l1i_cache(i)->size);
542 break;
543 case 4:
544 case 5:
545 case 6:
546 case 7:
547 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
548 break;
549 }
550 }
551}
552
Marat Dukhan8b814e32018-04-29 02:47:41 -0700553TEST(L1I, associativity) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700554 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
555 ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity);
556 }
557}
558
559TEST(L1I, sets) {
560 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
561 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
562 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
563 }
564}
565
566TEST(L1I, partitions) {
567 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
568 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
569 }
570}
571
572TEST(L1I, line_size) {
573 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
574 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
575 }
576}
577
578TEST(L1I, flags) {
579 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
580 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
581 }
582}
583
584TEST(L1I, processors) {
585 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
586 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
587 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
588 }
589}
590
591TEST(L1D, count) {
592 ASSERT_EQ(8, cpuinfo_get_l1d_caches_count());
593}
594
595TEST(L1D, non_null) {
596 ASSERT_TRUE(cpuinfo_get_l1d_caches());
597}
598
Marat Dukhan8b814e32018-04-29 02:47:41 -0700599TEST(L1D, size) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700600 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
601 switch (i) {
602 case 0:
603 case 1:
604 case 2:
605 case 3:
606 ASSERT_EQ(64 * 1024, cpuinfo_get_l1d_cache(i)->size);
607 break;
608 case 4:
609 case 5:
610 case 6:
611 case 7:
612 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
613 break;
614 }
615 }
616}
617
Marat Dukhan8b814e32018-04-29 02:47:41 -0700618TEST(L1D, associativity) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700619 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
620 switch (i) {
621 case 0:
622 case 1:
623 case 2:
624 case 3:
625 ASSERT_EQ(16, cpuinfo_get_l1d_cache(i)->associativity);
626 break;
627 case 4:
628 case 5:
629 case 6:
630 case 7:
631 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
632 break;
633 }
634 }
635}
636
637TEST(L1D, sets) {
638 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
639 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
640 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
641 }
642}
643
644TEST(L1D, partitions) {
645 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
646 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
647 }
648}
649
650TEST(L1D, line_size) {
651 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
652 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
653 }
654}
655
656TEST(L1D, flags) {
657 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
658 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
659 }
660}
661
662TEST(L1D, processors) {
663 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
664 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
665 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
666 }
667}
668
Marat Dukhan8b814e32018-04-29 02:47:41 -0700669TEST(L2, count) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700670 ASSERT_EQ(8, cpuinfo_get_l2_caches_count());
671}
672
673TEST(L2, non_null) {
674 ASSERT_TRUE(cpuinfo_get_l2_caches());
675}
676
Marat Dukhan8b814e32018-04-29 02:47:41 -0700677TEST(L2, size) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700678 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
679 switch (i) {
680 case 0:
681 case 1:
682 case 2:
683 case 3:
Marat Dukhan8b814e32018-04-29 02:47:41 -0700684 ASSERT_EQ(256 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhand51d3952018-03-17 19:18:06 -0700685 break;
686 case 4:
687 case 5:
688 case 6:
689 case 7:
Marat Dukhan8b814e32018-04-29 02:47:41 -0700690 ASSERT_EQ(128 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhand51d3952018-03-17 19:18:06 -0700691 break;
692 }
693 }
694}
695
Marat Dukhan8b814e32018-04-29 02:47:41 -0700696TEST(L2, associativity) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700697 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
698 switch (i) {
699 case 0:
700 case 1:
701 case 2:
702 case 3:
703 ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity);
704 break;
705 case 4:
706 case 5:
707 case 6:
708 case 7:
709 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->associativity);
710 break;
711 }
712 }
713}
714
715TEST(L2, sets) {
716 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
717 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
718 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
719 }
720}
721
722TEST(L2, partitions) {
723 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
724 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
725 }
726}
727
728TEST(L2, line_size) {
729 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
730 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
731 }
732}
733
Marat Dukhan8b814e32018-04-29 02:47:41 -0700734TEST(L2, flags) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700735 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
736 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
737 }
738}
739
Marat Dukhan8b814e32018-04-29 02:47:41 -0700740TEST(L2, processors) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700741 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
742 ASSERT_EQ(i, cpuinfo_get_l2_cache(i)->processor_start);
743 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->processor_count);
744 }
745}
746
Marat Dukhan8b814e32018-04-29 02:47:41 -0700747TEST(L3, count) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700748 ASSERT_EQ(1, cpuinfo_get_l3_caches_count());
749}
750
Marat Dukhan8b814e32018-04-29 02:47:41 -0700751TEST(L3, non_null) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700752 ASSERT_TRUE(cpuinfo_get_l3_caches());
753}
754
Marat Dukhan8b814e32018-04-29 02:47:41 -0700755TEST(L3, size) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700756 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
757 ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l3_cache(i)->size);
758 }
759}
760
Marat Dukhan8b814e32018-04-29 02:47:41 -0700761TEST(L3, associativity) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700762 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
Marat Dukhan8b814e32018-04-29 02:47:41 -0700763 ASSERT_EQ(16, cpuinfo_get_l3_cache(i)->associativity);
Marat Dukhand51d3952018-03-17 19:18:06 -0700764 }
765}
766
767TEST(L3, sets) {
768 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
769 ASSERT_EQ(cpuinfo_get_l3_cache(i)->size,
770 cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity);
771 }
772}
773
774TEST(L3, partitions) {
775 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
776 ASSERT_EQ(1, cpuinfo_get_l3_cache(i)->partitions);
777 }
778}
779
780TEST(L3, line_size) {
781 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
782 ASSERT_EQ(64, cpuinfo_get_l3_cache(i)->line_size);
783 }
784}
785
Marat Dukhan8b814e32018-04-29 02:47:41 -0700786TEST(L3, flags) {
Marat Dukhand51d3952018-03-17 19:18:06 -0700787 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
788 ASSERT_EQ(0, cpuinfo_get_l3_cache(i)->flags);
789 }
790}
791
792TEST(L3, processors) {
793 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
794 ASSERT_EQ(0, cpuinfo_get_l3_cache(i)->processor_start);
795 ASSERT_EQ(8, cpuinfo_get_l3_cache(i)->processor_count);
796 }
797}
798
799TEST(L4, none) {
800 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
801 ASSERT_FALSE(cpuinfo_get_l4_caches());
802}
803
804#include <galaxy-s9-us.h>
805
806int main(int argc, char* argv[]) {
807#if CPUINFO_ARCH_ARM
808 cpuinfo_set_hwcap(UINT32_C(0x0037B0D6));
809 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
810#elif CPUINFO_ARCH_ARM64
811 cpuinfo_set_hwcap(UINT32_C(0x000007FF));
812#endif
813 cpuinfo_mock_filesystem(filesystem);
814#ifdef __ANDROID__
815 cpuinfo_mock_android_properties(properties);
816 cpuinfo_mock_gl_renderer("Adreno (TM) 630");
817#endif
818 cpuinfo_initialize();
819 ::testing::InitGoogleTest(&argc, argv);
820 return RUN_ALL_TESTS();
821}