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gerrit-public.fairphone.software / platform / external / elfutils / 9e6925dd43d4e6572b69194232f6152f232e737d / . / libcpu / defs / i386
blob: 8c6602e2148654b6a5f57f39c09a9b2b632d8dba [file] [log] [blame]
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]1%mask {s} 1
2%mask {w} 1
3%mask {w1} 1
4dnl floating point reg suffix
5%mask {D} 1
6%mask {imm8} 8
7%mask {imms8} 8
8%mask {imm16} 16
9%mask {reg} 3
10%mask {reg16} 3
11%mask {tttn} 4
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]12%mask {mod} 2
13%mask {moda} 2
14%mask {MOD} 2
15%mask {r_m} 3
16dnl like {r_m} but referencing byte register
17%mask {8r_m} 3
18dnl like {r_m} but referencing 16-bit register
19%mask {16r_m} 3
20%mask {disp8} 8
21dnl imm really is 8/16/32 bit depending on the situation.
22%mask {imm} 8
23%mask {imms} 8
24%mask {rel} 32
25%mask {abs} 32
26%mask {absval} 32
27%mask {sel} 16
28%mask {imm32} 32
29%mask {ccc} 3
30%mask {ddd} 3
31%mask {sreg3} 3
32%mask {sreg2} 2
33%mask {mmxreg} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]34%mask {R_M} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]35%mask {Mod} 2
36%mask {xmmreg} 3
37%mask {R_m} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]38%mask {xmmreg1} 3
39%mask {xmmreg2} 3
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]40%mask {mmxreg1} 3
41%mask {mmxreg2} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]42%mask {predps} 8
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]43%mask {freg} 3
44%mask {fmod} 2
45%mask {fr_m} 3
46%prefix {R}
47%prefix {RE}
48%suffix {W}
49%suffix {w0}
50%synonym {xmmreg1} {xmmreg}
51%synonym {xmmreg2} {xmmreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]52%synonym {mmxreg1} {mmxreg}
53%synonym {mmxreg2} {mmxreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]54
55%%
56ifdef(`i386',
57`00110111:aaa
5811010101,00001010:aad
5911010100,00001010:aam
6000111111:aas
61')dnl
620001010{w},{imm}:adc {imm}{w},{ax}{w}
631000000{w},{mod}010{r_m},{imm}:adc{w} {imm}{w},{mod}{r_m}{w}
641000001{w},{mod}010{r_m},{imms8}:adc{w} {imms8},{mod}{r_m}
650001000{w},{mod}{reg}{r_m}:adc {reg}{w},{mod}{r_m}
660001001{w},{mod}{reg}{r_m}:adc {mod}{r_m},{reg}{w}
670000010{w},{imm}:add {imm}{w},{ax}{w}
681000000{w},{mod}000{r_m},{imm}:add{w} {imm}{w},{mod}{r_m}{w}
6910000011,{mod}000{r_m},{imms8}:add{w0} {imms8},{mod}{r_m}
700000000{w},{mod}{reg}{r_m}:add {reg}{w},{mod}{r_m}
710000001{w},{mod}{reg}{r_m}:add {mod}{r_m},{reg}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]7201100110,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubpd {Mod}{R_m},{xmmreg}
7311110010,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubps {Mod}{R_m},{xmmreg}
740010010{w},{imm}:and {imm}{w},{ax}{w}
751000000{w},{mod}100{r_m},{imm}:and{w} {imm}{w},{mod}{r_m}{w}
761000001{w},{mod}100{r_m},{imms}:and{w} {imms},{mod}{r_m}
770010000{w},{mod}{reg}{r_m}:and {reg}{w},{mod}{r_m}{w}
780010001{w},{mod}{reg}{r_m}:and {mod}{r_m}{w},{reg}{w}
7901100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg}
8000001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
8101100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg}
8200001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
83ifdef(`i386',
84`01100011,{mod}{reg16}{r_m}:arpl {reg16},{mod}{r_m}
8501100010,{moda}{reg}{r_m}:bound {reg},{moda}{r_m}
86')dnl
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]8700001111,10111100,{mod}{reg}{r_m}:bsf {mod}{r_m},{reg}
8800001111,10111101,{mod}{reg}{r_m}:bsr {mod}{r_m},{reg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]8900001111,11001{reg}:bswap {reg}
9000001111,10100011,{mod}{reg}{r_m}:bt {reg},{mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]9100001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]9200001111,10111011,{mod}{reg}{r_m}:btc {reg},{mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]9300001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]9400001111,10110011,{mod}{reg}{r_m}:btr {reg},{mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]9500001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]9600001111,10101011,{mod}{reg}{r_m}:bts {reg},{mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]9700001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]9811101000,{rel}:call {rel}
9911111111,{mod}010{r_m}:call *{mod}{r_m}
100ifdef(`i386',
101`10011010,{absval},{sel}:lcall {sel},{absval}
102')dnl
10311111111,{mod}011{r_m}:lcall *{mod}{r_m}
104# SPECIAL 10011000:[{rex.w}?cltq:{dpfx}?cbtw:cwtl]
10510011000:INVALID
106# SPECIAL 10011001:[{rew.w}?cqto:{dpfx}?cltd:cwtd]
10710011001:INVALID
10811111000:clc
10911111100:cld
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]11011111010:cli
11100001111,00000101:syscall
11200001111,00000110:clts
11300001111,00000111:sysret
11400001111,00110100:sysenter
11500001111,00110101:sysexit
11611110101:cmc
11700001111,0100{tttn},{mod}{reg}{r_m}:cmov{tttn} {mod}{r_m},{reg}
1180011110{w},{imm}:cmp {imm}{w},{ax}{w}
1191000000{w},{mod}111{r_m},{imm}:cmp{w} {imm}{w},{mod}{r_m}{w}
12010000011,{mod}111{r_m},{imms8}:cmp{w0} {imms8},{mod}{r_m}
1210011100{w},{mod}{reg}{r_m}:cmp {reg}{w},{mod}{r_m}{w}
1220011101{w},{mod}{reg}{r_m}:cmp {mod}{r_m}{w},{reg}{w}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]12311110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg}
12411110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg}
12501100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg}
12600001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]1271010011{w}:{RE}cmps{w} {es_di},{ds_si}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]12800001111,1011000{w},{mod}{reg}{r_m}:cmpxchg {reg}{w},{mod}{r_m}{w}
129ifdef(`i386',
130`00001111,11000111,{mod}001{r_m}:cmpxchg8b {mod}{r_m}
131',
132`# SPECIAL 00001111,11000111,{mod}001{r_m}:[{rex.w}?cmpxchg16b:cmpxchg8b] {reg},{mod}{r_m}
13300001111,11000111,{mod}001{r_m}:INVALID {mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]134')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]13500001111,10100010:cpuid
13611110011,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtdq2pd {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]13711110010,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtpd2dq {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]13801100110,00001111,11100110,{Mod}{xmmreg}{R_m}:cvttpd2dq {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]139ifdef(`i386',
140`00100111:daa
14100101111:das
142')dnl
1431111111{w},{mod}001{r_m}:dec{w} {mod}{r_m}{w}
144ifdef(`i386',
145`01001{reg}:dec {reg}
146')dnl
1471111011{w},{mod}110{r_m}:div{w} {mod}{r_m}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]14800001111,01110111:emms
14911001000,{imm16},{imm8}:enter {imm16},{imm8}
15011011001,11010000:fnop
15111011001,11100000:fchs
15211011001,11100001:fabs
15311011001,11100100:ftst
15411011001,11100101:fxam
15511011001,11101000:fld1
15611011001,11101001:fldl2t
15711011001,11101010:fldl2e
15811011001,11101011:fldpi
15911011001,11101100:fldlg2
16011011001,11101101:fldln2
16111011001,11101110:fldz
16211011001,11110000:f2xm1
16311011001,11110001:fyl2x
16411011001,11110010:fptan
16511011001,11110011:fpatan
16611011001,11110100:fxtract
16711011001,11110101:fprem1
16811011001,11110110:fdecstp
16911011001,11110111:fincstp
17011011001,11111000:fprem
17111011001,11111001:fyl2xp1
17211011001,11111010:fsqrt
17311011001,11111011:fsincos
17411011001,11111100:frndint
17511011001,11111101:fscale
17611011001,11111110:fsin
17711011001,11111111:fcos
178# ORDER
17911011000,11000{freg}:fadd {freg},%st
18011011100,11000{freg}:fadd %st,{freg}
18111011{D}00,{mod}000{r_m}:fadd{D} {mod}{r_m}
182# ORDER END
183# ORDER
18411011000,11001{freg}:fmul {freg},%st
18511011100,11001{freg}:fmul %st,{freg}
18611011{D}00,{mod}001{r_m}:fmul{D} {mod}{r_m}
187# ORDER END
188# ORDER
18911011000,11100{freg}:fsub {freg},%st
19011011100,11100{freg}:fsub %st,{freg}
19111011{D}00,{mod}100{r_m}:fsub{D} {mod}{r_m}
192# ORDER END
193# ORDER
19411011000,11101{freg}:fsubr {freg},%st
19511011100,11101{freg}:fsubr %st,{freg}
19611011{D}00,{mod}101{r_m}:fsubr{D} {mod}{r_m}
197# ORDER END
198# ORDER
19911011101,11010{freg}:fst {freg}
20011011{D}01,{mod}010{r_m}:fst{D} {mod}{r_m}
201# ORDER END
202# ORDER
20311011101,11011{freg}:fstp {freg}
20411011{D}01,{mod}011{r_m}:fstp{D} {mod}{r_m}
205# ORDER END
20611011001,{mod}100{r_m}:fldenv {mod}{r_m}
20711011001,{mod}101{r_m}:fldcw {mod}{r_m}
20811011001,{mod}110{r_m}:fnstenv {mod}{r_m}
20911011001,{mod}111{r_m}:fnstcw {mod}{r_m}
21011011001,11001{freg}:fxch {freg}
211# ORDER
21211011110,11000{freg}:faddp %st,{freg}
213ifdef(`ASSEMBLER',
214`11011110,11000001:faddp
215')dnl
216# ORDER
21711011010,11000{freg}:fcmovb {freg},%st
21811011{w1}10,{mod}000{r_m}:fiadd{w1} {mod}{r_m}
219# ORDER END
220# ORDER
22111011010,11001{freg}:fcmove {freg},%st
22211011110,11001{freg}:fmulp %st,{freg}
22311011{w1}10,{mod}001{r_m}:fimul{w1} {mod}{r_m}
224# ORDER END
225# ORDER
22611011110,11100{freg}:fsubp %st,{freg}
22711011{w1}10,{mod}100{r_m}:fisub{w1} {mod}{r_m}
228# ORDER END
229# ORDER
23011011110,11101{freg}:fsubrp %st,{freg}
23111011{w1}10,{mod}101{r_m}:fisubr{w1} {mod}{r_m}
232# ORDER END
233# ORDER
23411011111,11100000:fnstsw %ax
23511011111,{mod}100{r_m}:fbld {mod}{r_m}
236# ORDER END
237# ORDER
23811011111,11110{freg}:fcomip {freg},%st
23911011111,{mod}110{r_m}:fbstp {mod}{r_m}
240# ORDER END
24111011001,11100000:fchs
242# ORDER
24310011011,11011011,11100010:fclex
24410011011,11011011,11100011:finit
24510011011:fwait
246# END ORDER
24711011011,11100010:fnclex
24811011010,11000{freg}:fcmovb {freg},%st
24911011010,11001{freg}:fcmove {freg},%st
25011011010,11010{freg}:fcmovbe {freg},%st
25111011010,11011{freg}:fcmovu {freg},%st
25211011011,11000{freg}:fcmovnb {freg},%st
25311011011,11001{freg}:fcmovne {freg},%st
25411011011,11010{freg}:fcmovnbe {freg},%st
25511011011,11011{freg}:fcmovnu {freg},%st
256# ORDER
25711011000,11010{freg}:fcom {freg}
258ifdef(`ASSEMBLER',
259`11011000,11010001:fcom
260')dnl
26111011{D}00,{mod}010{r_m}:fcom{D} {mod}{r_m}
262# END ORDER
263# ORDER
26411011000,11011{freg}:fcomp {freg}
265ifdef(`ASSEMBLER',
266`11011000,11011001:fcomp
267')dnl
26811011{D}00,{mod}011{r_m}:fcomp{D} {mod}{r_m}
269# END ORDER
27011011110,11011001:fcompp
27111011011,11110{freg}:fcomi {freg},%st
27211011111,11110{freg}:fcomip {freg},%st
27311011011,11101{freg}:fucomi {freg},%st
27411011111,11101{freg}:fucomip {freg},%st
27511011001,11111111:fcos
27611011001,11110110:fdecstp
277# ORDER
27811011000,11110{freg}:fdiv {freg},%st
27911011100,11110{freg}:fdiv %st,{freg}
28011011{D}00,{mod}110{r_m}:fdiv{D} {mod}{r_m}
281# END ORDER
28211011010,{mod}110{r_m}:fidivl {mod}{r_m}
283# ORDER
28411011110,11110{freg}:fdivp %st,{freg}
28511011110,{mod}110{r_m}:fidiv {mod}{r_m}
286# END ORDER
28711011110,11111{freg}:fdivrp %st,{freg}
288ifdef(`ASSEMBLER',
289`11011110,11111001:fdivp
290')dnl
291# ORDER
29211011000,11111{freg}:fdivr {freg},%st
29311011100,11111{freg}:fdivr %st,{freg}
29411011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m}
295# END ORDER
29611011010,{mod}111{r_m}:fidivrl {mod}{r_m}
29711011110,{mod}111{r_m}:fidivr {mod}{r_m}
29811011110,11110{freg}:fdivrp %st,{freg}
299ifdef(`ASSEMBLER',
300`11011110,11110001:fdivrp
301')dnl
30211011101,11000{freg}:ffree {freg}
30311011010,11010{freg}:fcmovbe {freg}
30411011{w1}10,{mod}010{r_m}:ficom{w1} {mod}{r_m}
30511011010,11011{freg}:fcmovu {freg}
30611011{w1}10,{mod}011{r_m}:ficomp{w1} {mod}{r_m}
30711011111,{mod}000{r_m}:fild {mod}{r_m}
30811011011,{mod}000{r_m}:fildl {mod}{r_m}
30911011111,{mod}101{r_m}:fildll {mod}{r_m}
31011011001,11110111:fincstp
31111011011,11100011:fninit
31211011{w1}11,{mod}010{r_m}:fist{w1} {mod}{r_m}
31311011{w1}11,{mod}011{r_m}:fistp{w1} {mod}{r_m}
31411011111,{mod}111{r_m}:fistpll {mod}{r_m}
31511011{w1}11,{mod}001{r_m}:fisttp{w1} {mod}{r_m}
31611011101,{mod}001{r_m}:fisttpll {mod}{r_m}
31711011011,{mod}101{r_m}:fldt {mod}{r_m}
31811011011,{mod}111{r_m}:fstpt {mod}{r_m}
319# ORDER
32011011001,11000{freg}:fld {freg}
32111011{D}01,{mod}000{r_m}:fld{D} {mod}{r_m}
322# ORDER END
323# ORDER
32411011101,11100{freg}:fucom {freg}
32511011101,{mod}100{r_m}:frstor {mod}{r_m}
326# ORDER END
32711011101,11101{freg}:fucomp {freg}
32811011101,{mod}110{r_m}:fnsave {mod}{r_m}
32911011101,{mod}111{r_m}:fnstsw {mod}{r_m}
330#
331#
332#
33311110100:hlt
3341111011{w},{mod}111{r_m}:idiv{w} {mod}{r_m}{w}
3351111011{w},{mod}101{r_m}:imul{w} {mod}{r_m}{w}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]33600001111,10101111,{mod}{reg}{r_m}:imul {mod}{r_m},{reg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]337011010{s}1,{mod}{reg}{r_m},{imm}:imul {imm}{s},{mod}{r_m},{reg}
3381110010{w},{imm8}:in {imm8},{ax}{w}
3391110110{w}:in {dx},{ax}{w}
3401111111{w},{mod}000{r_m}:inc{w} {mod}{r_m}{w}
34101000{reg}:inc {reg}
3420110110{w}:{R}ins{w} {dx},{es_di}
34311001101,{imm8}:int {imm8}
34411001100:int3
34511001110:into
34600001111,00001000:invd
347# ORDER
34800001111,00000001,11111000:swapgs
34900001111,00000001,{mod}111{r_m}:invlpg {mod}{r_m}
350# ORDER END
35111001111:iret{W}
3520111{tttn},{disp8}:j{tttn} {disp8}
35300001111,1000{tttn},{rel}:j{tttn} {rel}
35400001111,1001{tttn},{mod}000{8r_m}:set{tttn} {mod}{8r_m}
355# SPECIAL 11100011,{disp8}:[{dpfx}?jcxz:jecxz] {disp8}
35611100011,{disp8}:INVALID {disp8}
35711101011,{disp8}:jmp {disp8}
35811101001,{rel}:jmp {rel}
35911111111,{mod}100{r_m}:jmp *{mod}{r_m}
36011101010,{absval},{sel}:ljmp {sel},{absval}
36111111111,{mod}101{r_m}:ljmp *{mod}{r_m}
36210011111:lahf
36300001111,00000010,{mod}{reg}{16r_m}:lar {mod}{16r_m},{reg}
36411000101,{mod}{reg}{r_m}:lds {mod}{r_m},{reg}
36510001101,{mod}{reg}{r_m}:lea {mod}{r_m},{reg}
36611001001:leave
36711000100,{mod}{reg}{r_m}:les {mod}{r_m},{reg}
36800001111,10110100,{mod}{reg}{r_m}:lfs {mod}{r_m},{reg}
36900001111,00000001,{mod}010{r_m}:lgdt{w0} {mod}{r_m}
37000001111,10110101,{mod}{reg}{r_m}:lgs {mod}{r_m},{reg}
37100001111,00000001,{mod}011{r_m}:lidt{w0} {mod}{r_m}
37200001111,00000000,{mod}010{16r_m}:lldt {mod}{16r_m}
37300001111,00000001,{mod}110{16r_m}:lmsw {mod}{16r_m}
37411110000:lock
3751010110{w}:{R}lods {ds_si},{ax}{w}
37611100010,{disp8}:loop {disp8}
37711100001,{disp8}:loope {disp8}
37811100000,{disp8}:loopne {disp8}
37900001111,00000011,{mod}{reg}{16r_m}:lsl {mod}{16r_m},{reg}
38000001111,10110010,{mod}{reg}{r_m}:lss {mod}{r_m},{reg}
38100001111,00000000,{mod}011{16r_m}:ltr {mod}{16r_m}
3821000100{w},{mod}{reg}{r_m}:mov {reg}{w},{mod}{r_m}{w}
3831000101{w},{mod}{reg}{r_m}:mov {mod}{r_m}{w},{reg}{w}
3841100011{w},{mod}000{r_m},{imm}:mov{w} {imm}{w},{mod}{r_m}{w}
3851011{w}{reg},{imm}:mov {imm}{w},{reg}{w}
3861010000{w},{abs}:mov {abs},{ax}{w}
3871010001{w},{abs}:mov {ax}{w},{abs}
38800001111,00100000,11{ccc}{reg}:mov {ccc},{reg}
38900001111,00100010,11{ccc}{reg}:mov {reg},{ccc}
39000001111,00100001,11{ddd}{reg}:mov {ddd},{reg}
39100001111,00100011,11{ddd}{reg}:mov {reg},{ddd}
39210001100,{mod}{sreg3}{r_m}:mov {sreg3},{mod}{r_m}
39310001110,{mod}{sreg3}{r_m}:mov {mod}{r_m},{sreg3}
3941010010{w}:{R}movs{w} {ds_si},{es_di}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]39500001111,10111110,{mod}{reg}{8r_m}:movsbl {mod}{8r_m},{reg}
39600001111,10111111,{mod}{reg}{16r_m}:movswl {mod}{16r_m},{reg}
39700001111,10110110,{mod}{reg}{8r_m}:movzbl {mod}{8r_m},{reg}
39800001111,10110111,{mod}{reg}{16r_m}:movzwl {mod}{16r_m},{reg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]3991111011{w},{mod}100{r_m}:mul{w} {mod}{r_m}{w}
4001111011{w},{mod}011{r_m}:neg{w} {mod}{r_m}{w}
401ifdef(`ASSEMBLER',
402`10010000:nop
40311110011,10010000:pause
404',
405`10010000:{R}INVALID
406')dnl
4071111011{w},{mod}010{r_m}:not{w} {mod}{r_m}{w}
4080000100{w},{mod}{reg}{r_m}:or {reg}{w},{mod}{r_m}{w}
4090000101{w},{mod}{reg}{r_m}:or {mod}{r_m}{w},{reg}{w}
4101000000{w},{mod}001{r_m},{imm}:or{w} {imm}{w},{mod}{r_m}{w}
411100000{s}{w},{mod}001{r_m},{imm}:or{w} {imm}{s},{mod}{r_m}{w}
4120000110{w},{imm}:or {imm}{w},{ax}{w}
4131110011{w},{imm8}:out {ax}{w},{imm8}
4141110111{w}:out {ax}{w},{dx}
4150110111{w}:{R}outs{w} {ds_si},{dx}
41610001111,{mod}000{r_m}:pop{w} {mod}{r_m}
41701011{reg}:pop {reg}
41800001111,10{sreg3}001:pop {sreg3}
41901100001:popa{W}
42010011101:popf{W}
42111111111,{mod}110{r_m}:push{w} {mod}{r_m}
42201010{reg}:push {reg}
423011010{s}0,{imm}:push {imm}{s}
424000{sreg2}110:push {sreg2}
42500001111,10{sreg3}000:push {sreg3}
42601100000:pusha{W}
42710011100:pushf{W}
4281101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w}
4291101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w}
4301100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w}
4311101000{w},{mod}011{r_m}:rcr{w} {mod}{r_m}{w}
4321101001{w},{mod}011{r_m}:rcr{w} %cl,{mod}{r_m}{w}
4331100000{w},{mod}011{r_m},{imm8}:rcr{w} {imm8},{mod}{r_m}{w}
43400001111,00110010:rdmsr
43500001111,00110011:rdpmc
43600001111,00110001:rdtsc
43711000011:ret
43811000010,{imm16}:ret {imm16}
43911001011:lret
44011001010,{imm16}:lret {imm16}
4411101000{w},{mod}000{r_m}:rol{w} {mod}{r_m}{w}
4421101001{w},{mod}000{r_m}:rol{w} %cl,{mod}{r_m}{w}
4431100000{w},{mod}000{r_m},{imm8}:rol{w} {imm8},{mod}{r_m}{w}
4441101000{w},{mod}001{r_m}:ror{w} {mod}{r_m}{w}
4451101001{w},{mod}001{r_m}:ror{w} %cl,{mod}{r_m}{w}
4461100000{w},{mod}001{r_m},{imm8}:ror{w} {imm8},{mod}{r_m}{w}
44700001111,10101010:rsm
44810011110:sahf
4491101000{w},{mod}111{r_m}:sar{w} {mod}{r_m}{w}
4501101001{w},{mod}111{r_m}:sar{w} %cl,{mod}{r_m}{w}
4511100000{w},{mod}111{r_m},{imm8}:sar{w} {imm8},{mod}{r_m}{w}
4520001100{w},{mod}{reg}{r_m}:sbb {reg}{w},{mod}{r_m}{w}
4530001101{w},{mod}{reg}{r_m}:sbb {mod}{r_m}{w},{reg}{w}
4540001110{w},{imm}:sbb {imm}{w},{ax}{w}
4551000000{w},{mod}011{r_m},{imm}:sbb{w} {imm}{w},{mod}{r_m}{w}
4561000001{w},{mod}011{r_m},{imms}:sbb{w} {imms},{mod}{r_m}
4571010111{w}:{RE}scas {es_di},{ax}{w}
45800001111,1001{tttn},{mod}000{r_m}:set{tttn} {mod}{r_m}
4591101000{w},{mod}100{r_m}:shl{w} {mod}{r_m}{w}
4601101001{w},{mod}100{r_m}:shl{w} %cl,{mod}{r_m}{w}
4611100000{w},{mod}100{r_m},{imm8}:shl{w} {imm8},{mod}{r_m}{w}
4621101000{w},{mod}101{r_m}:shr{w} {mod}{r_m}{w}
46300001111,10100100,{mod}{reg}{r_m},{imm8}:shld {imm8},{reg},{mod}{r_m}
46400001111,10100101,{mod}{reg}{r_m}:shld %cl,{reg},{mod}{r_m}
4651101001{w},{mod}101{r_m}:shr{w} %cl,{mod}{r_m}{w}
4661100000{w},{mod}101{r_m},{imm8}:shr{w} {imm8},{mod}{r_m}{w}
46700001111,10101100,{mod}{reg}{r_m},{imm8}:shrd {imm8},{reg},{mod}{r_m}
46800001111,10101101,{mod}{reg}{r_m}:shrd %cl,{reg},{mod}{r_m}
469# ORDER
47000001111,00000001,11000001:vmcall
47100001111,00000001,11000010:vmlaunch
47200001111,00000001,11000011:vmresume
47300001111,00000001,11000100:vmxoff
Ulrich Drepperfea4e9d2008-01-04 03:21:38 +0000[diff] [blame]47400001111,01111000,{mod}{reg}{r_m}:vmread {reg},{mod}{r_m}
47500001111,01111001,{mod}{reg}{r_m}:vmwrite {mod}{r_m},{reg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]47600001111,00000001,{mod}000{r_m}:sgdtl {mod}{r_m}
477# ORDER END
478# ORDER
47900001111,00000001,11001000:monitor %eax,%ecx,%edx
48000001111,00000001,11001001:mwait %eax,%ecx
48100001111,00000001,{mod}001{r_m}:sidtl {mod}{r_m}
482# ORDER END
48300001111,00000000,{mod}000{r_m}:sldt {mod}{r_m}
48400001111,00000001,{mod}100{r_m}:smsw {mod}{r_m}
48511111001:stc
48611111101:std
48711111011:sti
4881010101{w}:{R}stos {ax}{w},{es_di}
48900001111,00000000,{mod}001{r_m}:str {mod}{r_m}
4900010100{w},{mod}{reg}{r_m}:sub {reg}{w},{mod}{r_m}{w}
4910010101{w},{mod}{reg}{r_m}:sub {mod}{r_m}{w},{reg}{w}
4920010110{w},{imm}:sub {imm}{w},{ax}{w}
4931000000{w},{mod}101{r_m},{imm}:sub{w} {imm}{w},{mod}{r_m}{w}
4941000001{w},{mod}101{r_m},{imms}:sub{w} {imms},{mod}{r_m}
4951000010{w},{mod}{reg}{r_m}:test {reg}{w},{mod}{r_m}{w}
4961010100{w},{imm}:test {imm}{w},{ax}{w}
4971111011{w},{mod}000{r_m},{imm}:test{w} {imm}{w},{mod}{r_m}{w}
49800001111,00001011:ud2a
49900001111,00000000,{mod}100{16r_m}:verr {mod}{16r_m}
50000001111,00000000,{mod}101{16r_m}:verw {mod}{16r_m}
50100001111,00001001:wbinvd
50200001111,00001101,{mod}000{8r_m}:prefetch {mod}{8r_m}
50300001111,00001101,{mod}001{8r_m}:prefetchw {mod}{8r_m}
50400001111,00011000,{mod}000{r_m}:prefetchnta {mod}{r_m}
50500001111,00011000,{mod}001{r_m}:prefetcht0 {mod}{r_m}
50600001111,00011000,{mod}010{r_m}:prefetcht1 {mod}{r_m}
50700001111,00011000,{mod}011{r_m}:prefetcht2 {mod}{r_m}
50800001111,00011111,{mod}{reg}{r_m}:nop{w} {mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]50900001111,00110000:wrmsr
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]51000001111,1100000{w},{mod}{reg}{r_m}:xadd {reg}{w},{mod}{r_m}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]5111000011{w},{mod}{reg}{r_m}:xchg {reg}{w},{mod}{r_m}{w}
51210010{reg}:xchg {ax},{reg}
51311010111:xlat {ds_bx}
5140011000{w},{mod}{reg}{r_m}:xor {reg}{w},{mod}{r_m}{w}
5150011001{w},{mod}{reg}{r_m}:xor {mod}{r_m}{w},{reg}{w}
5160011010{w},{imm}:xor {imm}{w},{ax}{w}
5171000000{w},{mod}110{r_m},{imm}:xor{w} {imm}{w},{mod}{r_m}{w}
5181000001{w},{mod}110{r_m},{imms}:xor{w} {imms},{mod}{r_m}
51900001111,01110111:emms
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]52001100110,00001111,11011011,{Mod}{xmmreg}{R_m}:pand {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]52100001111,11011011,{MOD}{mmxreg}{R_M}:pand {MOD}{R_M},{mmxreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]52201100110,00001111,11011111,{Mod}{xmmreg}{R_m}:pandn {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]52300001111,11011111,{MOD}{mmxreg}{R_M}:pandn {MOD}{R_M},{mmxreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]52401100110,00001111,11110101,{Mod}{xmmreg}{R_m}:pmaddwd {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]52500001111,11110101,{MOD}{mmxreg}{R_M}:pmaddwd {MOD}{R_M},{mmxreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]52601100110,00001111,11101011,{Mod}{xmmreg}{R_m}:por {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]52700001111,11101011,{MOD}{mmxreg}{R_M}:por {MOD}{R_M},{mmxreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]52801100110,00001111,11101111,{Mod}{xmmreg}{R_m}:pxor {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]52900001111,11101111,{MOD}{mmxreg}{R_M}:pxor {MOD}{R_M},{mmxreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]53000001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
53100001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
53200001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqps {Mod}{R_m},{xmmreg}
53300001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltps {Mod}{R_m},{xmmreg}
53400001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpleps {Mod}{R_m},{xmmreg}
53500001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordps {Mod}{R_m},{xmmreg}
53600001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqps {Mod}{R_m},{xmmreg}
53700001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltps {Mod}{R_m},{xmmreg}
53800001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnleps {Mod}{R_m},{xmmreg}
53900001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordps {Mod}{R_m},{xmmreg}
54011110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqss {Mod}{R_m},{xmmreg}
54111110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltss {Mod}{R_m},{xmmreg}
54211110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpless {Mod}{R_m},{xmmreg}
54311110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordss {Mod}{R_m},{xmmreg}
54411110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqss {Mod}{R_m},{xmmreg}
54511110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltss {Mod}{R_m},{xmmreg}
54611110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnless {Mod}{R_m},{xmmreg}
54711110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordss {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]54800001111,10101110,{mod}001{r_m}:fxrstor {mod}{r_m}
54900001111,10101110,{mod}000{r_m}:fxsave {mod}{r_m}
55000001111,10101110,{mod}010{r_m}:ldmxcsr {mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]55100001111,10101110,{mod}011{r_m}:stmxcsr {mod}{r_m}
Ulrich Drepper515d8d72008-01-03 07:41:03 +0000[diff] [blame]55211110010,00001111,00010000,{Mod}{xmmreg}{R_m}:movsd {Mod}{R_m},{xmmreg}
55311110011,00001111,00010000,{Mod}{xmmreg}{R_m}:movss {Mod}{R_m},{xmmreg}
55401100110,00001111,00010000,{Mod}{xmmreg}{R_m}:movupd {Mod}{R_m},{xmmreg}
55500001111,00010000,{Mod}{xmmreg}{R_m}:movups {Mod}{R_m},{xmmreg}
55611110010,00001111,00010001,{Mod}{xmmreg}{R_m}:movsd {xmmreg},{Mod}{R_m}
55711110011,00001111,00010001,{Mod}{xmmreg}{R_m}:movss {xmmreg},{Mod}{R_m}
55801100110,00001111,00010001,{Mod}{xmmreg}{R_m}:movupd {xmmreg},{Mod}{R_m}
55900001111,00010001,{Mod}{xmmreg}{R_m}:movups {xmmreg},{Mod}{R_m}
56011110010,00001111,00010010,{Mod}{xmmreg}{R_m}:movddup {Mod}{R_m},{xmmreg}
56111110011,00001111,00010010,{Mod}{xmmreg}{R_m}:movsldup {Mod}{R_m},{xmmreg}
56201100110,00001111,00010010,{Mod}{xmmreg}{R_m}:movlpd {Mod}{R_m},{xmmreg}
56300001111,00010010,11{xmmreg1}{xmmreg2}:movhlps {xmmreg2},{xmmreg1}
56400001111,00010010,{Mod}{xmmreg}{R_m}:movlps {Mod}{R_m},{xmmreg}
56501100110,00001111,00010011,11{xmmreg1}{xmmreg2}:movhlpd {xmmreg1},{xmmreg2}
56600001111,00010011,11{xmmreg1}{xmmreg2}:movhlps {xmmreg1},{xmmreg2}
56701100110,00001111,00010011,{Mod}{xmmreg}{R_m}:movlpd {xmmreg},{Mod}{R_m}
56800001111,00010011,{Mod}{xmmreg}{R_m}:movlps {xmmreg},{Mod}{R_m}
56901100110,00001111,00010100,{Mod}{xmmreg}{R_m}:unpcklpd {Mod}{R_m},{xmmreg}
57000001111,00010100,{Mod}{xmmreg}{R_m}:unpcklps {Mod}{R_m},{xmmreg}
57101100110,00001111,00010101,{Mod}{xmmreg}{R_m}:unpckhpd {Mod}{R_m},{xmmreg}
57200001111,00010101,{Mod}{xmmreg}{R_m}:unpckhps {Mod}{R_m},{xmmreg}
57311110011,00001111,00010110,{Mod}{xmmreg}{R_m}:movshdup {Mod}{R_m},{xmmreg}
57401100110,00001111,00010110,{Mod}{xmmreg}{R_m}:movhpd {Mod}{R_m},{xmmreg}
57500001111,00010110,11{xmmreg1}{xmmreg2}:movlhps {xmmreg2},{xmmreg1}
57600001111,00010110,{Mod}{xmmreg}{R_m}:movhps {Mod}{R_m},{xmmreg}
57701100110,00001111,00010111,11{xmmreg1}{xmmreg2}:movlhpd {xmmreg1},{xmmreg2}
57800001111,00010111,11{xmmreg1}{xmmreg2}:movlhps {xmmreg1},{xmmreg2}
57901100110,00001111,00010111,{Mod}{xmmreg}{R_m}:movhpd {xmmreg},{Mod}{R_m}
58000001111,00010111,{Mod}{xmmreg}{R_m}:movhps {xmmreg},{Mod}{R_m}
58101100110,00001111,00101000,{Mod}{xmmreg}{R_m}:movapd {Mod}{R_m},{xmmreg}
58200001111,00101000,{Mod}{xmmreg}{R_m}:movaps {Mod}{R_m},{xmmreg}
58301100110,00001111,00101001,{Mod}{xmmreg}{R_m}:movapd {xmmreg},{Mod}{R_m}
58400001111,00101001,{Mod}{xmmreg}{R_m}:movaps {xmmreg},{Mod}{R_m}
58511110010,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2sd {mod}{r_m},{xmmreg}
58611110011,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2ss {mod}{r_m},{xmmreg}
58701100110,00001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2pd {MOD}{R_M},{xmmreg}
58800001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2ps {MOD}{R_M},{xmmreg}
58901100110,00001111,00101011,{mod}{xmmreg}{r_m}:movntpd {xmmreg},{mod}{r_m}
59000001111,00101011,{mod}{xmmreg}{r_m}:movntps {xmmreg},{mod}{r_m}
59111110010,00001111,00101100,{Mod}{reg}{R_m}:cvttsd2si {Mod}{R_m},{reg}
59211110011,00001111,00101100,{Mod}{reg}{R_m}:cvttss2si {Mod}{R_m},{reg}
59301100110,00001111,00101100,{Mod}{mmxreg}{R_m}:cvttpd2pi {Mod}{R_m},{mmxreg}
59400001111,00101100,{Mod}{mmxreg}{R_m}:cvttps2pi {Mod}{R_m},{mmxreg}
59501100110,00001111,00101101,{Mod}{mmxreg}{R_m}:cvtpd2pi {Mod}{R_m},{mmxreg}
59611110010,00001111,00101101,{Mod}{reg}{R_m}:cvtsd2si {Mod}{R_m},{reg}
59711110011,00001111,00101101,{Mod}{reg}{R_m}:cvtss2si {Mod}{R_m},{reg}
59800001111,00101101,{Mod}{mmxreg}{R_m}:cvtps2pi {Mod}{R_m},{mmxreg}
59901100110,00001111,00101110,{Mod}{xmmreg}{R_m}:ucomisd {Mod}{R_m},{xmmreg}
60000001111,00101110,{Mod}{xmmreg}{R_m}:ucomiss {Mod}{R_m},{xmmreg}
60101100110,00001111,00101111,{Mod}{xmmreg}{R_m}:comisd {Mod}{R_m},{xmmreg}
60200001111,00101111,{Mod}{xmmreg}{R_m}:comiss {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]60300001111,00110111:getsec
Ulrich Drepper515d8d72008-01-03 07:41:03 +0000[diff] [blame]60401100110,00001111,01010000,11{reg}{xmmreg}:movmskpd {xmmreg},{reg}
60500001111,01010000,11{reg}{xmmreg}:movmskps {xmmreg},{reg}
60601100110,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtpd {Mod}{R_m},{xmmreg}
60711110010,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtsd {Mod}{R_m},{xmmreg}
60811110011,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtss {Mod}{R_m},{xmmreg}
60900001111,01010001,{Mod}{xmmreg}{R_m}:sqrtps {Mod}{R_m},{xmmreg}
61011110011,00001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtss {Mod}{R_m},{xmmreg}
61100001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtps {Mod}{R_m},{xmmreg}
61211110011,00001111,01010011,{Mod}{xmmreg}{R_m}:rcpss {Mod}{R_m},{xmmreg}
61300001111,01010011,{Mod}{xmmreg}{R_m}:rcpps {Mod}{R_m},{xmmreg}
Ulrich Drepperee67b642008-01-03 08:45:10 +0000[diff] [blame]61401100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg}
61500001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
61601100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg}
61700001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
61801100110,00001111,01010110,{Mod}{xmmreg}{R_m}:orpd {Mod}{R_m},{xmmreg}
61900001111,01010110,{Mod}{xmmreg}{R_m}:orps {Mod}{R_m},{xmmreg}
62001100110,00001111,01010111,{Mod}{xmmreg}{R_m}:xorpd {Mod}{R_m},{xmmreg}
62100001111,01010111,{Mod}{xmmreg}{R_m}:xorps {Mod}{R_m},{xmmreg}
62211110010,00001111,01011000,{Mod}{xmmreg}{R_m}:addsd {Mod}{R_m},{xmmreg}
62311110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg}
62401100110,00001111,01011000,{Mod}{xmmreg}{R_m}:addpd {Mod}{R_m},{xmmreg}
62500001111,01011000,{Mod}{xmmreg}{R_m}:addps {Mod}{R_m},{xmmreg}
62611110010,00001111,01011001,{Mod}{xmmreg}{R_m}:mulsd {Mod}{R_m},{xmmreg}
62711110011,00001111,01011001,{Mod}{xmmreg}{R_m}:mulss {Mod}{R_m},{xmmreg}
62801100110,00001111,01011001,{Mod}{xmmreg}{R_m}:mulpd {Mod}{R_m},{xmmreg}
62900001111,01011001,{Mod}{xmmreg}{R_m}:mulps {Mod}{R_m},{xmmreg}
63011110010,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtsd2ss {Mod}{R_m},{xmmreg}
63111110011,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtss2sd {Mod}{R_m},{xmmreg}
63201100110,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtpd2ps {Mod}{R_m},{xmmreg}
63300001111,01011010,{Mod}{xmmreg}{R_m}:cvtps2pd {Mod}{R_m},{xmmreg}
63401100110,00001111,01011011,{Mod}{xmmreg}{R_m}:cvtps2dq {Mod}{R_m},{xmmreg}
63511110011,00001111,01011011,{Mod}{xmmreg}{R_m}:cvttps2dq {Mod}{R_m},{xmmreg}
63600001111,01011011,{Mod}{xmmreg}{R_m}:cvtdq2ps {Mod}{R_m},{xmmreg}
63711110010,00001111,01011100,{Mod}{xmmreg}{R_m}:subsd {Mod}{R_m},{xmmreg}
63811110011,00001111,01011100,{Mod}{xmmreg}{R_m}:subss {Mod}{R_m},{xmmreg}
63901100110,00001111,01011100,{Mod}{xmmreg}{R_m}:subpd {Mod}{R_m},{xmmreg}
64000001111,01011100,{Mod}{xmmreg}{R_m}:subps {Mod}{R_m},{xmmreg}
64111110010,00001111,01011101,{Mod}{xmmreg}{R_m}:minsd {Mod}{R_m},{xmmreg}
64211110011,00001111,01011101,{Mod}{xmmreg}{R_m}:minss {Mod}{R_m},{xmmreg}
64301100110,00001111,01011101,{Mod}{xmmreg}{R_m}:minpd {Mod}{R_m},{xmmreg}
64400001111,01011101,{Mod}{xmmreg}{R_m}:minps {Mod}{R_m},{xmmreg}
64511110010,00001111,01011110,{Mod}{xmmreg}{R_m}:divsd {Mod}{R_m},{xmmreg}
64611110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg}
64701100110,00001111,01011110,{Mod}{xmmreg}{R_m}:divpd {Mod}{R_m},{xmmreg}
64800001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg}
64911110010,00001111,01011111,{Mod}{xmmreg}{R_m}:maxsd {Mod}{R_m},{xmmreg}
65011110011,00001111,01011111,{Mod}{xmmreg}{R_m}:maxss {Mod}{R_m},{xmmreg}
65101100110,00001111,01011111,{Mod}{xmmreg}{R_m}:maxpd {Mod}{R_m},{xmmreg}
65200001111,01011111,{Mod}{xmmreg}{R_m}:maxps {Mod}{R_m},{xmmreg}
Ulrich Drepperfea4e9d2008-01-04 03:21:38 +0000[diff] [blame]65301100110,00001111,01100000,{Mod}{xmmreg}{R_m}:punpcklbw {Mod}{R_m},{xmmreg}
65400001111,01100000,{MOD}{mmxreg}{R_M}:punpcklbw {MOD}{R_M},{mmxreg}
65501100110,00001111,01100001,{Mod}{xmmreg}{R_m}:punpcklwd {Mod}{R_m},{xmmreg}
65600001111,01100001,{MOD}{mmxreg}{R_M}:punpcklwd {MOD}{R_M},{mmxreg}
65701100110,00001111,01100010,{Mod}{xmmreg}{R_m}:punpckldq {Mod}{R_m},{xmmreg}
65800001111,01100010,{MOD}{mmxreg}{R_M}:punpckldq {MOD}{R_M},{mmxreg}
65901100110,00001111,01100011,{Mod}{xmmreg}{R_m}:packsswb {Mod}{R_m},{xmmreg}
66000001111,01100011,{MOD}{mmxreg}{R_M}:packsswb {MOD}{R_M},{mmxreg}
66101100110,00001111,01100100,{Mod}{xmmreg}{R_m}:pcmpgtb {Mod}{R_m},{xmmreg}
66200001111,01100100,{MOD}{mmxreg}{R_M}:pcmpgtb {MOD}{R_M},{mmxreg}
66301100110,00001111,01100101,{Mod}{xmmreg}{R_m}:pcmpgtw {Mod}{R_m},{xmmreg}
66400001111,01100101,{MOD}{mmxreg}{R_M}:pcmpgtw {MOD}{R_M},{mmxreg}
66501100110,00001111,01100110,{Mod}{xmmreg}{R_m}:pcmpgtd {Mod}{R_m},{xmmreg}
66600001111,01100110,{MOD}{mmxreg}{R_M}:pcmpgtd {MOD}{R_M},{mmxreg}
66701100110,00001111,01100111,{Mod}{xmmreg}{R_m}:packuswb {Mod}{R_m},{xmmreg}
66800001111,01100111,{MOD}{mmxreg}{R_M}:packuswb {MOD}{R_M},{mmxreg}
66901100110,00001111,01101000,{Mod}{xmmreg}{R_m}:punpckhbw {Mod}{R_m},{xmmreg}
67000001111,01101000,{MOD}{mmxreg}{R_M}:punpckhbw {MOD}{R_M},{mmxreg}
67101100110,00001111,01101001,{Mod}{xmmreg}{R_m}:punpckhwd {Mod}{R_m},{xmmreg}
67200001111,01101001,{MOD}{mmxreg}{R_M}:punpckhwd {MOD}{R_M},{mmxreg}
67301100110,00001111,01101010,{Mod}{xmmreg}{R_m}:punpckhdq {Mod}{R_m},{xmmreg}
67400001111,01101010,{MOD}{mmxreg}{R_M}:punpckhdq {MOD}{R_M},{mmxreg}
67501100110,00001111,01101011,{Mod}{xmmreg}{R_m}:packssdw {Mod}{R_m},{xmmreg}
67600001111,01101011,{MOD}{mmxreg}{R_M}:packssdw {MOD}{R_M},{mmxreg}
67701100110,00001111,01101100,{Mod}{xmmreg}{R_m}:punpcklqdq {Mod}{R_m},{xmmreg}
67801100110,00001111,01101101,{Mod}{xmmreg}{R_m}:punpckhqdq {Mod}{R_m},{xmmreg}
67901100110,00001111,01101110,{mod}{xmmreg}{r_m}:movd {mod}{r_m},{xmmreg}
68000001111,01101110,{mod}{mmxreg}{r_m}:movd {mod}{r_m},{mmxreg}
68101100110,00001111,01101111,{Mod}{xmmreg}{R_m}:movdqa {Mod}{R_m},{xmmreg}
68211110011,00001111,01101111,{Mod}{xmmreg}{R_m}:movdqu {Mod}{R_m},{xmmreg}
68300001111,01101111,{MOD}{mmxreg}{R_M}:movq {MOD}{R_M},{mmxreg}
68401100110,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshufd {imm8},{Mod}{R_m},{xmmreg}
68511110010,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshuflw {imm8},{Mod}{R_m},{xmmreg}
68611110011,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshufhw {imm8},{Mod}{R_m},{xmmreg}
68700001111,01110000,{MOD}{mmxreg}{R_M},{imm8}:pshufw {imm8},{MOD}{R_M},{mmxreg}
68801100110,00001111,01110100,{Mod}{xmmreg}{R_m}:pcmpeqb {Mod}{R_m},{xmmreg}
68900001111,01110100,{MOD}{mmxreg}{R_M}:pcmpeqb {MOD}{R_M},{mmxreg}
69001100110,00001111,01110101,{Mod}{xmmreg}{R_m}:pcmpeqw {Mod}{R_m},{xmmreg}
69100001111,01110101,{MOD}{mmxreg}{R_M}:pcmpeqw {MOD}{R_M},{mmxreg}
69201100110,00001111,01110110,{Mod}{xmmreg}{R_m}:pcmpeqd {Mod}{R_m},{xmmreg}
69300001111,01110110,{MOD}{mmxreg}{R_M}:pcmpeqd {MOD}{R_M},{mmxreg}
69401100110,00001111,01111100,{Mod}{xmmreg}{R_m}:haddpd {Mod}{R_m},{xmmreg}
69511110010,00001111,01111100,{Mod}{xmmreg}{R_m}:haddps {Mod}{R_m},{xmmreg}
69601100110,00001111,01111101,{Mod}{xmmreg}{R_m}:hsubpd {Mod}{R_m},{xmmreg}
69711110010,00001111,01111101,{Mod}{xmmreg}{R_m}:hsubps {Mod}{R_m},{xmmreg}
69801100110,00001111,01111110,{mod}{xmmreg}{r_m}:movd {xmmreg},{mod}{r_m}
69911110011,00001111,01111110,{Mod}{xmmreg}{R_m}:movq {Mod}{R_m},{xmmreg}
70000001111,01111110,{mod}{mmxreg}{r_m}:movd {mmxreg},{mod}{r_m}
70101100110,00001111,01111111,{Mod}{xmmreg}{R_m}:movdqa {xmmreg},{Mod}{R_m}
70211110011,00001111,01111111,{Mod}{xmmreg}{R_m}:movdqu {xmmreg},{Mod}{R_m}
70300001111,01111111,{MOD}{mmxreg}{R_M}:movq {mmxreg},{MOD}{R_M}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame^]70400001111,11000011,{mod}{reg}{r_m}:movnti {reg},{mod}{r_m}
70501100110,00001111,11000100,{mod}{xmmreg}{r_m},{imm8}:pinsrw {imm8},{mod}{r_m},{xmmreg}
70600001111,11000100,{mod}{mmxreg}{r_m},{imm8}:pinsrw {imm8},{mod}{r_m},{mmxreg}
70701100110,00001111,11000101,11{reg}{xmmreg},{imm8}:pextrw {imm8},{xmmreg},{reg}
70800001111,11000101,11{reg}{mmxreg},{imm8}:pextrw {imm8},{mmxreg},{reg}
70901100110,00001111,11000110,{Mod}{xmmreg}{R_m},{imm8}:shufpd {imm8},{Mod}{R_m},{xmmreg}
71000001111,11000110,{Mod}{xmmreg}{R_m},{imm8}:shufps {imm8},{Mod}{R_m},{xmmreg}
71101100110,00001111,11010001,{Mod}{xmmreg}{R_m}:psrlw {Mod}{R_m},{xmmreg}
71200001111,11010001,{MOD}{mmxreg}{R_M}:psrlw {MOD}{R_M},{mmxreg}
71301100110,00001111,11010010,{Mod}{xmmreg}{R_m}:psrld {Mod}{R_m},{xmmreg}
71400001111,11010010,{MOD}{mmxreg}{R_M}:psrld {MOD}{R_M},{mmxreg}
71501100110,00001111,11010011,{Mod}{xmmreg}{R_m}:psrlq {Mod}{R_m},{xmmreg}
71600001111,11010011,{MOD}{mmxreg}{R_M}:psrlq {MOD}{R_M},{mmxreg}
71701100110,00001111,11010100,{Mod}{xmmreg}{R_m}:paddq {Mod}{R_m},{xmmreg}
71800001111,11010100,{MOD}{mmxreg}{R_M}:paddq {MOD}{R_M},{mmxreg}
71901100110,00001111,11010101,{Mod}{xmmreg}{R_m}:pmullw {Mod}{R_m},{xmmreg}
72000001111,11010101,{MOD}{mmxreg}{R_M}:pmullw {MOD}{R_M},{mmxreg}
72101100110,00001111,11010110,{Mod}{xmmreg}{R_m}:movq {xmmreg},{Mod}{R_m}
72211110010,00001111,11010110,11{mmxreg}{xmmreg}:movdq2q {xmmreg},{mmxreg}
72311110011,00001111,11010110,11{xmmreg}{mmxreg}:movq2dq {mmxreg},{xmmreg}
72401100110,00001111,11010111,11{reg}{xmmreg}:pmovmskb {xmmreg},{reg}
72500001111,11010111,11{reg}{mmxreg}:pmovmskb {mmxreg},{reg}
72601100110,00001111,11011000,{Mod}{xmmreg}{R_m}:psubusb {Mod}{R_m},{xmmreg}
72700001111,11011000,{MOD}{mmxreg}{R_M}:psubusb {MOD}{R_M},{mmxreg}
72801100110,00001111,11011001,{Mod}{xmmreg}{R_m}:psubusw {Mod}{R_m},{xmmreg}
72900001111,11011001,{MOD}{mmxreg}{R_M}:psubusw {MOD}{R_M},{mmxreg}
73001100110,00001111,11011010,{Mod}{xmmreg}{R_m}:pminub {Mod}{R_m},{xmmreg}
73100001111,11011010,{MOD}{mmxreg}{R_M}:pminub {MOD}{R_M},{mmxreg}
73201100110,00001111,11011100,{Mod}{xmmreg}{R_m}:paddusb {Mod}{R_m},{xmmreg}
73300001111,11011100,{MOD}{mmxreg}{R_M}:paddusb {MOD}{R_M},{mmxreg}
73401100110,00001111,11011101,{Mod}{xmmreg}{R_m}:paddusw {Mod}{R_m},{xmmreg}
73500001111,11011101,{MOD}{mmxreg}{R_M}:paddusw {MOD}{R_M},{mmxreg}
73601100110,00001111,11011110,{Mod}{xmmreg}{R_m}:pmaxub {Mod}{R_m},{xmmreg}
73700001111,11011110,{MOD}{mmxreg}{R_M}:pmaxub {MOD}{R_M},{mmxreg}
73801100110,00001111,11100000,{Mod}{xmmreg}{R_m}:pavgb {Mod}{R_m},{xmmreg}
73900001111,11100000,{MOD}{mmxreg}{R_M}:pavgb {MOD}{R_M},{mmxreg}
74001100110,00001111,11100001,{Mod}{xmmreg}{R_m}:psraw {Mod}{R_m},{xmmreg}
74100001111,11100001,{MOD}{mmxreg}{R_M}:psraw {MOD}{R_M},{mmxreg}
74201100110,00001111,11100010,{Mod}{xmmreg}{R_m}:psrad {Mod}{R_m},{xmmreg}
74300001111,11100010,{MOD}{mmxreg}{R_M}:psrad {MOD}{R_M},{mmxreg}
74401100110,00001111,11100011,{Mod}{xmmreg}{R_m}:pavgw {Mod}{R_m},{xmmreg}
74500001111,11100011,{MOD}{mmxreg}{R_M}:pavgw {MOD}{R_M},{mmxreg}
74601100110,00001111,11100100,{Mod}{xmmreg}{R_m}:pmulhuw {Mod}{R_m},{xmmreg}
74700001111,11100100,{MOD}{mmxreg}{R_M}:pmulhuw {MOD}{R_M},{mmxreg}
74801100110,00001111,11100101,{Mod}{xmmreg}{R_m}:pmulhw {Mod}{R_m},{xmmreg}
74900001111,11100101,{MOD}{mmxreg}{R_M}:pmulhw {MOD}{R_M},{mmxreg}
75001100110,00001111,11100111,{Mod}{xmmreg}{R_m}:movntdq {xmmreg},{Mod}{R_m}
75100001111,11100111,{MOD}{mmxreg}{R_M}:movntq {mmxreg},{MOD}{R_M}
75201100110,00001111,11101000,{Mod}{xmmreg}{R_m}:psubsb {Mod}{R_m},{xmmreg}
75300001111,11101000,{MOD}{mmxreg}{R_M}:psubsb {MOD}{R_M},{mmxreg}
75401100110,00001111,11101001,{Mod}{xmmreg}{R_m}:psubsw {Mod}{R_m},{xmmreg}
75500001111,11101001,{MOD}{mmxreg}{R_M}:psubsw {MOD}{R_M},{mmxreg}
75601100110,00001111,11101010,{Mod}{xmmreg}{R_m}:pminsw {Mod}{R_m},{xmmreg}
75700001111,11101010,{MOD}{mmxreg}{R_M}:pminsw {MOD}{R_M},{mmxreg}
75801100110,00001111,11101100,{Mod}{xmmreg}{R_m}:paddsb {Mod}{R_m},{xmmreg}
75900001111,11101100,{MOD}{mmxreg}{R_M}:paddsb {MOD}{R_M},{mmxreg}
76001100110,00001111,11101101,{Mod}{xmmreg}{R_m}:paddsw {Mod}{R_m},{xmmreg}
76100001111,11101101,{MOD}{mmxreg}{R_M}:paddsw {MOD}{R_M},{mmxreg}
76201100110,00001111,11101110,{Mod}{xmmreg}{R_m}:pmaxsw {Mod}{R_m},{xmmreg}
76300001111,11101110,{MOD}{mmxreg}{R_M}:pmaxsw {MOD}{R_M},{mmxreg}
76411110010,00001111,11110000,{mod}{xmmreg}{r_m}:lddqu {mod}{r_m},{xmmreg}
76501100110,00001111,11110001,{Mod}{xmmreg}{R_m}:psllw {Mod}{R_m},{xmmreg}
76600001111,11110001,{MOD}{mmxreg}{R_M}:psllw {MOD}{R_M},{mmxreg}
76701100110,00001111,11110010,{Mod}{xmmreg}{R_m}:pslld {Mod}{R_m},{xmmreg}
76800001111,11110010,{MOD}{mmxreg}{R_M}:pslld {MOD}{R_M},{mmxreg}
76901100110,00001111,11110011,{Mod}{xmmreg}{R_m}:psllq {Mod}{R_m},{xmmreg}
77000001111,11110011,{MOD}{mmxreg}{R_M}:psllq {MOD}{R_M},{mmxreg}
77101100110,00001111,11110100,{Mod}{xmmreg}{R_m}:pmuludq {Mod}{R_m},{xmmreg}
77200001111,11110100,{MOD}{mmxreg}{R_M}:pmuludq {MOD}{R_M},{mmxreg}
77301100110,00001111,11110110,{Mod}{xmmreg}{R_m}:psadbw {Mod}{R_m},{xmmreg}
77400001111,11110110,{MOD}{mmxreg}{R_M}:psadbw {MOD}{R_M},{mmxreg}
77501100110,00001111,11110111,11{xmmreg1}{xmmreg2}:maskmovdqu {xmmreg2},{xmmreg1}
77600001111,11110111,11{mmxreg1}{mmxreg2}:maskmovq {mmxreg2},{mmxreg1}
77701100110,00001111,11111000,{Mod}{xmmreg}{R_m}:psubb {Mod}{R_m},{xmmreg}
77800001111,11111000,{MOD}{mmxreg}{R_M}:psubb {MOD}{R_M},{mmxreg}
77901100110,00001111,11111001,{Mod}{xmmreg}{R_m}:psubw {Mod}{R_m},{xmmreg}
78000001111,11111001,{MOD}{mmxreg}{R_M}:psubw {MOD}{R_M},{mmxreg}
78101100110,00001111,11111010,{Mod}{xmmreg}{R_m}:psubd {Mod}{R_m},{xmmreg}
78200001111,11111010,{MOD}{mmxreg}{R_M}:psubd {MOD}{R_M},{mmxreg}
78301100110,00001111,11111011,{Mod}{xmmreg}{R_m}:psubq {Mod}{R_m},{xmmreg}
78400001111,11111011,{MOD}{mmxreg}{R_M}:psubq {MOD}{R_M},{mmxreg}
78501100110,00001111,11111100,{Mod}{xmmreg}{R_m}:paddb {Mod}{R_m},{xmmreg}
78600001111,11111100,{MOD}{mmxreg}{R_M}:paddb {MOD}{R_M},{mmxreg}
78701100110,00001111,11111101,{Mod}{xmmreg}{R_m}:paddw {Mod}{R_m},{xmmreg}
78800001111,11111101,{MOD}{mmxreg}{R_M}:paddw {MOD}{R_M},{mmxreg}
78901100110,00001111,11111110,{Mod}{xmmreg}{R_m}:paddd {Mod}{R_m},{xmmreg}
79000001111,11111110,{MOD}{mmxreg}{R_M}:paddd {MOD}{R_M},{mmxreg}
79101100110,00001111,00111000,00000000,{Mod}{xmmreg}{R_m}:pshufb {Mod}{R_m},{xmmreg}
79200001111,00111000,00000000,{MOD}{mmxreg}{R_M}:pshufb {MOD}{R_M},{mmxreg}
79301100110,00001111,00111000,00000001,{Mod}{xmmreg}{R_m}:phaddw {Mod}{R_m},{xmmreg}
79400001111,00111000,00000001,{MOD}{mmxreg}{R_M}:phaddw {MOD}{R_M},{mmxreg}
79501100110,00001111,00111000,00000010,{Mod}{xmmreg}{R_m}:phaddd {Mod}{R_m},{xmmreg}
79600001111,00111000,00000010,{MOD}{mmxreg}{R_M}:phaddd {MOD}{R_M},{mmxreg}
79701100110,00001111,00111000,00000011,{Mod}{xmmreg}{R_m}:phaddsw {Mod}{R_m},{xmmreg}
79800001111,00111000,00000011,{MOD}{mmxreg}{R_M}:phaddsw {MOD}{R_M},{mmxreg}
79901100110,00001111,00111000,00000100,{Mod}{xmmreg}{R_m}:pmaddubsw {Mod}{R_m},{xmmreg}
80000001111,00111000,00000100,{MOD}{mmxreg}{R_M}:pmaddubsw {MOD}{R_M},{mmxreg}
80101100110,00001111,00111000,00000101,{Mod}{xmmreg}{R_m}:phsubw {Mod}{R_m},{xmmreg}
80200001111,00111000,00000101,{MOD}{mmxreg}{R_M}:phsubw {MOD}{R_M},{mmxreg}
80301100110,00001111,00111000,00000110,{Mod}{xmmreg}{R_m}:phsubd {Mod}{R_m},{xmmreg}
80400001111,00111000,00000110,{MOD}{mmxreg}{R_M}:phsubd {MOD}{R_M},{mmxreg}
80501100110,00001111,00111000,00000111,{Mod}{xmmreg}{R_m}:phsubsw {Mod}{R_m},{xmmreg}
80600001111,00111000,00000111,{MOD}{mmxreg}{R_M}:phsubsw {MOD}{R_M},{mmxreg}
80701100110,00001111,00111000,00001000,{Mod}{xmmreg}{R_m}:psignb {Mod}{R_m},{xmmreg}
80800001111,00111000,00001000,{MOD}{mmxreg}{R_M}:psignb {MOD}{R_M},{mmxreg}
80901100110,00001111,00111000,00001001,{Mod}{xmmreg}{R_m}:psignw {Mod}{R_m},{xmmreg}
81000001111,00111000,00001001,{MOD}{mmxreg}{R_M}:psignw {MOD}{R_M},{mmxreg}
81101100110,00001111,00111000,00001010,{Mod}{xmmreg}{R_m}:psignd {Mod}{R_m},{xmmreg}
81200001111,00111000,00001010,{MOD}{mmxreg}{R_M}:psignd {MOD}{R_M},{mmxreg}
81301100110,00001111,00111000,00001011,{Mod}{xmmreg}{R_m}:pmulhrsw {Mod}{R_m},{xmmreg}
81400001111,00111000,00001011,{MOD}{mmxreg}{R_M}:pmulhrsw {MOD}{R_M},{mmxreg}
81501100110,00001111,00111000,00011100,{Mod}{xmmreg}{R_m}:pabsb {Mod}{R_m},{xmmreg}
81600001111,00111000,00011100,{MOD}{mmxreg}{R_M}:pabsb {MOD}{R_M},{mmxreg}
81701100110,00001111,00111000,00011101,{Mod}{xmmreg}{R_m}:pabsw {Mod}{R_m},{xmmreg}
81800001111,00111000,00011101,{MOD}{mmxreg}{R_M}:pabsw {MOD}{R_M},{mmxreg}
81901100110,00001111,00111000,00011110,{Mod}{xmmreg}{R_m}:pabsd {Mod}{R_m},{xmmreg}
82000001111,00111000,00011110,{MOD}{mmxreg}{R_M}:pabsd {MOD}{R_M},{mmxreg}
82101100110,00001111,00111010,00001111,{Mod}{xmmreg}{R_m},{imm8}:palignr {imm8},{Mod}{R_m},{xmmreg}
82200001111,00111010,00001111,{MOD}{mmxreg}{R_M},{imm8}:palignr {imm8},{MOD}{R_M},{mmxreg}
82301100110,00001111,11000111,{mod}110{r_m}:vmclear {mod}{r_m}
82411110011,00001111,11000111,{mod}110{r_m}:vmxon {mod}{r_m}
82500001111,11000111,{mod}110{r_m}:vmptrld {mod}{r_m}
82600001111,11000111,{mod}111{r_m}:vmptrst {mod}{r_m}
82701100110,00001111,01110001,11010{xmmreg},{imm8}:psrlw {imm8},{xmmreg}
82800001111,01110001,11010{mmxreg},{imm8}:psrlw {imm8},{mmxreg}
82901100110,00001111,01110001,11100{xmmreg},{imm8}:psraw {imm8},{xmmreg}
83000001111,01110001,11100{mmxreg},{imm8}:psraw {imm8},{mmxreg}
83101100110,00001111,01110001,11110{xmmreg},{imm8}:psllw {imm8},{xmmreg}
83200001111,01110001,11110{mmxreg},{imm8}:psllw {imm8},{mmxreg}
83301100110,00001111,01110010,11010{xmmreg},{imm8}:psrld {imm8},{xmmreg}
83400001111,01110010,11010{mmxreg},{imm8}:psrld {imm8},{mmxreg}
83501100110,00001111,01110010,11100{xmmreg},{imm8}:psrad {imm8},{xmmreg}
83600001111,01110010,11100{mmxreg},{imm8}:psrad {imm8},{mmxreg}
83701100110,00001111,01110010,11110{xmmreg},{imm8}:pslld {imm8},{xmmreg}
83800001111,01110010,11110{mmxreg},{imm8}:pslld {imm8},{mmxreg}
83901100110,00001111,01110011,11010{xmmreg},{imm8}:psrlq {imm8},{xmmreg}
84000001111,01110011,11010{mmxreg},{imm8}:psrlq {imm8},{mmxreg}
84101100110,00001111,01110011,11011{xmmreg},{imm8}:psrldq {imm8},{xmmreg}
84201100110,00001111,01110011,11110{xmmreg},{imm8}:psllq {imm8},{xmmreg}
84300001111,01110011,11110{mmxreg},{imm8}:psllq {imm8},{mmxreg}
84401100110,00001111,01110011,11111{xmmreg},{imm8}:pslldq {imm8},{xmmreg}
84500001111,10101110,11101000:lfence
84600001111,10101110,11110000:mfence
84700001111,10101110,11111000:sfence
84800001111,10101110,{mod}111{r_m}:clflush {mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]849# ORDER:
850dnl Many previous entries depend on this being last.
851000{sreg2}111:pop {sreg2}
852# ORDER END: