blob: 2fd414dab3d33f1825004a9381dd2089e9a376f9 [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
Wu Fengguang020abdb2010-04-19 13:13:06 +080029#define _GNU_SOURCE
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080030#include <unistd.h>
Wu Fengguang020abdb2010-04-19 13:13:06 +080031#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <err.h>
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080035#include <arpa/inet.h>
36#include "intel_gpu_tools.h"
37
Wu Fengguang020abdb2010-04-19 13:13:06 +080038static uint32_t devid;
39
40
41#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
42#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
43#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
44#define BIT(reg, n) BITS(reg, n, n)
45
46#define min_t(type, x, y) ({ \
47 type __min1 = (x); \
48 type __min2 = (y); \
49 __min1 < __min2 ? __min1: __min2; })
50
51#define OPNAME(names, index) \
52 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
53
54#define dump_reg(reg, desc) \
55 do { \
56 dword = INREG(reg); \
57 printf("%-21s 0x%08x %s\n", # reg, dword, desc); \
58 } while (0)
59
60
61static char *pixel_clock[] = {
62 [0] = "25.2 / 1.001 MHz",
63 [1] = "25.2 MHz",
64 [2] = "27 MHz",
65 [3] = "27 * 1.001 MHz",
66 [4] = "54 MHz",
67 [5] = "54 * 1.001 MHz",
68 [6] = "74.25 / 1.001 MHz",
69 [7] = "74.25 MHz",
70 [8] = "148.5 / 1.001 MHz",
71 [9] = "148.5 MHz",
72 [10] = "Reserved",
73};
74
75static char *power_state[] = {
76 [0] = "D0",
77 [1] = "D1",
78 [2] = "D2",
79 [3] = "D3",
80};
81
82static char *stream_type[] = {
83 [0] = "default samples",
84 [1] = "one bit stream",
85 [2] = "DST stream",
86 [3] = "MLP stream",
87 [4] = "Reserved",
88};
89
90static char *dip_port[] = {
91 [0] = "Reserved",
92 [1] = "Digital Port B",
93 [2] = "Digital Port C",
94 [3] = "Digital Port D",
95};
96
97static char *dip_index[] = {
98 [0] = "Audio DIP",
99 [1] = "ACP DIP",
100 [2] = "ISRC1 DIP",
101 [3] = "ISRC2 DIP",
102 [4] = "Reserved",
103};
104
105static char *dip_trans[] = {
106 [0] = "disabled",
107 [1] = "reserved",
108 [2] = "send once",
109 [3] = "best effort",
110};
111
112static char *video_dip_index[] = {
113 [0] = "AVI DIP",
114 [1] = "Vendor-specific DIP",
115 [2] = "Reserved",
116 [3] = "Source Product Description DIP",
117};
118
119static char *video_dip_trans[] = {
120 [0] = "send once",
121 [1] = "send every vsync",
122 [2] = "send at least every other vsync",
123 [3] = "reserved",
124};
125
126static char *trans_to_port_sel[] = {
127 [0] = "no port",
128 [1] = "Digital Port B",
129 [2] = "Digital Port B",
130 [3] = "Digital Port B",
131 [4] = "Digital Port B",
132 [5 ... 7] = "reserved",
133};
134
135static char *transcoder_select[] = {
136 [0] = "Transcoder A",
137 [1] = "Transcoder B",
138 [2] = "Transcoder C",
139 [3] = "reserved",
140};
141
142static char *dp_port_width[] = {
143 [0] = "x1 mode",
144 [1] = "x2 mode",
Wu Fengguangcf4c12f2011-11-12 11:12:46 +0800145 [2] = "reserved",
146 [3] = "x4 mode",
147 [4 ... 7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800148};
149
150static void do_self_tests(void)
151{
152 if (BIT(1, 0) != 1)
153 exit(1);
154 if (BIT(0x80000000, 31) != 1)
155 exit(2);
156 if (BITS(0xc0000000, 31, 30) != 3)
157 exit(3);
158}
159
160/*
161 * EagleLake registers
162 */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800163#define AUD_CONFIG 0x62000
164#define AUD_DEBUG 0x62010
165#define AUD_VID_DID 0x62020
166#define AUD_RID 0x62024
167#define AUD_SUBN_CNT 0x62028
168#define AUD_FUNC_GRP 0x62040
169#define AUD_SUBN_CNT2 0x62044
170#define AUD_GRP_CAP 0x62048
171#define AUD_PWRST 0x6204c
172#define AUD_SUPPWR 0x62050
173#define AUD_SID 0x62054
174#define AUD_OUT_CWCAP 0x62070
175#define AUD_OUT_PCMSIZE 0x62074
176#define AUD_OUT_STR 0x62078
177#define AUD_OUT_DIG_CNVT 0x6207c
178#define AUD_OUT_CH_STR 0x62080
179#define AUD_OUT_STR_DESC 0x62084
180#define AUD_PINW_CAP 0x620a0
181#define AUD_PIN_CAP 0x620a4
182#define AUD_PINW_CONNLNG 0x620a8
183#define AUD_PINW_CONNLST 0x620ac
184#define AUD_PINW_CNTR 0x620b0
185#define AUD_PINW_UNSOLRESP 0x620b8
186#define AUD_CNTL_ST 0x620b4
187#define AUD_PINW_CONFIG 0x620bc
188#define AUD_HDMIW_STATUS 0x620d4
189#define AUD_HDMIW_HDMIEDID 0x6210c
190#define AUD_HDMIW_INFOFR 0x62118
191#define AUD_CONV_CHCNT 0x62120
192#define AUD_CTS_ENABLE 0x62128
193
194#define VIDEO_DIP_CTL 0x61170
195#define VIDEO_DIP_ENABLE (1<<31)
196#define VIDEO_DIP_ENABLE_AVI (1<<21)
197#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
198#define VIDEO_DIP_ENABLE_SPD (1<<24)
199#define VIDEO_DIP_BUF_AVI (0<<19)
200#define VIDEO_DIP_BUF_VENDOR (1<<19)
201#define VIDEO_DIP_BUF_SPD (3<<19)
202#define VIDEO_DIP_TRANS_ONCE (0<<16)
203#define VIDEO_DIP_TRANS_1 (1<<16)
204#define VIDEO_DIP_TRANS_2 (2<<16)
205
206#define AUDIO_HOTPLUG_EN (1<<24)
207
208
Wu Fengguang020abdb2010-04-19 13:13:06 +0800209static void dump_eaglelake(void)
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800210{
211 uint32_t dword;
212 int i;
213
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800214 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
215
216 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
217 dump_reg(SDVOB, "Digital Display Port B Control Register");
218 dump_reg(SDVOC, "Digital Display Port C Control Register");
219 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
220
221 dump_reg(AUD_CONFIG, "Audio Configuration");
222 dump_reg(AUD_DEBUG, "Audio Debug");
223 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
224 dump_reg(AUD_RID, "Audio Revision ID");
225 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
226 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
227 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
228 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
229 dump_reg(AUD_PWRST, "Audio Power State");
230 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
231 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
232 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
233 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
234 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
235 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
236 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
237 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
238 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
239 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
240 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
241 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
242 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
243 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
244 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
245 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
246 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
247 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
248 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
249 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
250 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
251
252 printf("\nDetails:\n\n");
253
254 dword = INREG(AUD_VID_DID);
255 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
256 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
257
258 dword = INREG(AUD_RID);
259 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
260 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
261 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
262 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
263
264 dword = INREG(SDVOB);
265 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
266 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
267 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
268 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
269 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
270
271 dword = INREG(SDVOC);
272 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
273 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
274 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
275 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
276 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
277
278 dword = INREG(PORT_HOTPLUG_EN);
279 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
280 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
281 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
282 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
283 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
284 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
285 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
286 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
287
288 dword = INREG(VIDEO_DIP_CTL);
289 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
290 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
291 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
292 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
293 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
294 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
295 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
296 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
297 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
298 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
299 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
300 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
301 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
302
303 dword = INREG(AUD_CONFIG);
304 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
305 OPNAME(pixel_clock, BITS(dword, 19, 16)));
306 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
307 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
308 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
309
310 dword = INREG(AUD_DEBUG);
311 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
312
313 dword = INREG(AUD_SUBN_CNT);
314 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
315 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
316
317 dword = INREG(AUD_SUBN_CNT2);
318 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
319 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
320
321 dword = INREG(AUD_FUNC_GRP);
322 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
323 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
324
325 dword = INREG(AUD_GRP_CAP);
326 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
327 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
328 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
329
330 dword = INREG(AUD_PWRST);
331 printf("AUD_PWRST device power state\t\t%s\n",
332 power_state[BITS(dword, 5, 4)]);
333 printf("AUD_PWRST device power state setting\t%s\n",
334 power_state[BITS(dword, 1, 0)]);
335
336 dword = INREG(AUD_SUPPWR);
337 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
338 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
339 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
340 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
341
342 dword = INREG(AUD_OUT_CWCAP);
343 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
344 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
345 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
346 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
347 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
348 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
349 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
350 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
351 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
352 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
353 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
354 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
355 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
356 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
357
358 dword = INREG(AUD_OUT_DIG_CNVT);
359 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
360 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
361 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
362 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
363 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
364 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
365 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
366 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
367 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
368
369 dword = INREG(AUD_OUT_CH_STR);
370 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
Wu Fengguang5032f682011-11-12 11:12:41 +0800371 printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800372
373 dword = INREG(AUD_OUT_STR_DESC);
Wu Fengguang5032f682011-11-12 11:12:41 +0800374 printf("AUD_OUT_STR_DESC stream channels\t%lu\n", BITS(dword, 3, 0) + 1);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800375
376 dword = INREG(AUD_PINW_CAP);
377 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
378 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
Wu Fengguang5032f682011-11-12 11:12:41 +0800379 printf("AUD_PINW_CAP channel count\t\t%lu\n",
380 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800381 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
382 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
383 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
384 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
385 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
386 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
387 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
388 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
389 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
390 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
391 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
392
393
394 dword = INREG(AUD_PIN_CAP);
395 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
396 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
397 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
398 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
399
400 dword = INREG(AUD_PINW_CNTR);
401 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
402 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
403 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
404 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
405 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
406 BITS(dword, 2, 0),
407 OPNAME(stream_type, BITS(dword, 2, 0)));
408
409 dword = INREG(AUD_PINW_UNSOLRESP);
410 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
411
412 dword = INREG(AUD_CNTL_ST);
413 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
414 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
415 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
416 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
417 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
418 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
419 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
420 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
421 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
422 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
423 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
424 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
425 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
426 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
427 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
428
429 dword = INREG(AUD_HDMIW_STATUS);
430 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
431 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
432 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
433 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
434
435 dword = INREG(AUD_CONV_CHCNT);
436 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
437 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
438
439 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
440 for (i = 0; i < 8; i++) {
441 OUTREG(AUD_CONV_CHCNT, i);
442 dword = INREG(AUD_CONV_CHCNT);
443 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
444 }
445
446 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
447 dword = INREG(AUD_CNTL_ST);
448 dword &= ~BITMASK(20, 18);
449 dword &= ~BITMASK(3, 0);
450 OUTREG(AUD_CNTL_ST, dword);
451 for (i = 0; i < 8; i++)
452 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
453 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800454}
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800455
Wu Fengguang020abdb2010-04-19 13:13:06 +0800456#undef AUD_RID
457#undef AUD_VID_DID
458#undef AUD_PWRST
459#undef AUD_OUT_CH_STR
460#undef AUD_HDMIW_STATUS
461
462/*
463 * IronLake registers
464 */
465#define AUD_CONFIG_A 0xE2000
466#define AUD_CONFIG_B 0xE2100
467#define AUD_CTS_ENABLE_A 0xE2028
468#define AUD_CTS_ENABLE_B 0xE2128
469#define AUD_MISC_CTRL_A 0xE2010
470#define AUD_MISC_CTRL_B 0xE2110
471#define AUD_VID_DID 0xE2020
472#define AUD_RID 0xE2024
473#define AUD_PWRST 0xE204C
474#define AUD_PORT_EN_HD_CFG 0xE207C
475#define AUD_OUT_DIG_CNVT_A 0xE2080
476#define AUD_OUT_DIG_CNVT_B 0xE2180
477#define AUD_OUT_CH_STR 0xE2088
478#define AUD_OUT_STR_DESC_A 0xE2084
479#define AUD_OUT_STR_DESC_B 0xE2184
480#define AUD_PINW_CONNLNG_LIST 0xE20A8
481#define AUD_PINW_CONNLNG_SEL 0xE20AC
482#define AUD_CNTL_ST_A 0xE20B4
483#define AUD_CNTL_ST_B 0xE21B4
484#define AUD_CNTL_ST2 0xE20C0
485#define AUD_HDMIW_STATUS 0xE20D4
486#define AUD_HDMIW_HDMIEDID_A 0xE2050
487#define AUD_HDMIW_HDMIEDID_B 0xE2150
488#define AUD_HDMIW_INFOFR_A 0xE2054
489#define AUD_HDMIW_INFOFR_B 0xE2154
490
491static void dump_ironlake(void)
492{
493 uint32_t dword;
494 int i;
495
496 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
497 dump_reg(HDMIC, "HDMI Port C Control");
498 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800499 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
500 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
501 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
502 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800503 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
504 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
505 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
506 dump_reg(AUD_RID, "Audio Revision ID");
507 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
508 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800509 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
510 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800511 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800512 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
513 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800514 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
515 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800516 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
517 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800518 dump_reg(AUD_CNTL_ST2, "Audio Control State 2");
519 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800520 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
521 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
522 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
523 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800524
525 printf("\nDetails:\n\n");
526
527 dword = INREG(AUD_VID_DID);
528 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
529 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
530
531 dword = INREG(AUD_RID);
532 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
533 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
534 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
535 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
536
537 dword = INREG(HDMIB);
538 printf("HDMIB HDMIB_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
539 printf("HDMIB Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
540 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800541 printf("HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800542 printf("HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
543 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
544
545 dword = INREG(HDMIC);
546 printf("HDMIC HDMIC_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
547 printf("HDMIC Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
548 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800549 printf("HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800550 printf("HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
551 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
552
553 dword = INREG(HDMID);
554 printf("HDMID HDMID_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
555 printf("HDMID Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
556 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
557 printf("HDMID Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
558 printf("HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
559 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
560
561 dword = INREG(AUD_CONFIG_A);
562 printf("AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
563 OPNAME(pixel_clock, BITS(dword, 19, 16)));
564 dword = INREG(AUD_CONFIG_B);
565 printf("AUD_CONFIG_B Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
566 OPNAME(pixel_clock, BITS(dword, 19, 16)));
567
568 dword = INREG(AUD_CTS_ENABLE_A);
569 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
570 printf("AUD_CTS_ENABLE_A CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
571 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
572 dword = INREG(AUD_CTS_ENABLE_B);
573 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
574 printf("AUD_CTS_ENABLE_B CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
575 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
576
577 dword = INREG(AUD_MISC_CTRL_A);
578 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
579 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
580 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
581 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
582 dword = INREG(AUD_MISC_CTRL_B);
583 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
584 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
585 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
586 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
587
588 dword = INREG(AUD_PWRST);
589 printf("AUD_PWRST Function_Group_Device_Power_State_Current\t%s\n", power_state[BITS(dword, 23, 22)]);
590 printf("AUD_PWRST Function_Group_Device_Power_State_Set \t%s\n", power_state[BITS(dword, 21, 20)]);
591 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
592 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
593 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
594 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
595 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
596 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
597 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
598 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
599 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
600 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
601
602 dword = INREG(AUD_PORT_EN_HD_CFG);
603 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
604 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
605 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
606 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
607 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12));
608 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13));
609 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14));
610 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16));
611 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17));
612 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18));
613
614 dword = INREG(AUD_OUT_DIG_CNVT_A);
615 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
616 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
617 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
618 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800619 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800620 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
621 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
622 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
623 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800624 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800625
626 dword = INREG(AUD_OUT_DIG_CNVT_B);
627 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
628 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
629 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
630 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800631 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800632 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
633 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
634 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
635 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800636 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800637
638 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
639 for (i = 0; i < 8; i++) {
640 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
641 dword = INREG(AUD_OUT_CH_STR);
642 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
643 1 + BITS(dword, 3, 0),
644 1 + BITS(dword, 7, 4),
645 1 + BITS(dword, 15, 12),
646 1 + BITS(dword, 23, 20));
647 }
648
649 dword = INREG(AUD_OUT_STR_DESC_A);
650 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800651 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800652 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
653 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
654
655 dword = INREG(AUD_OUT_STR_DESC_B);
656 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800657 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800658 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
659 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
660
661 dword = INREG(AUD_PINW_CONNLNG_SEL);
662 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
663 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
664 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
665
666 dword = INREG(AUD_CNTL_ST_A);
667 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
668 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
669 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800670 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800671 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
672 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
673 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
674 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
675 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
676
677 dword = INREG(AUD_CNTL_ST_B);
678 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
679 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
680 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800681 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800682 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
683 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
684 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
685 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
686 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
687
688 dword = INREG(AUD_CNTL_ST2);
689 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1));
690 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
691 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5));
692 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
693 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9));
694 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
695
696 dword = INREG(AUD_HDMIW_STATUS);
697 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
698 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
699 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
700 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
701 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
702 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 29));
703
704 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
705 dword = INREG(AUD_CNTL_ST_A);
706 dword &= ~BITMASK(9, 5);
707 OUTREG(AUD_CNTL_ST_A, dword);
708 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
709 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
710 printf("\n");
711
712 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
713 dword = INREG(AUD_CNTL_ST_B);
714 dword &= ~BITMASK(9, 5);
715 OUTREG(AUD_CNTL_ST_B, dword);
716 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
717 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
718 printf("\n");
719
720 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
721 dword = INREG(AUD_CNTL_ST_A);
722 dword &= ~BITMASK(20, 18);
723 dword &= ~BITMASK(3, 0);
724 OUTREG(AUD_CNTL_ST_A, dword);
725 for (i = 0; i < 8; i++)
726 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
727 printf("\n");
728
729 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
730 dword = INREG(AUD_CNTL_ST_B);
731 dword &= ~BITMASK(20, 18);
732 dword &= ~BITMASK(3, 0);
733 OUTREG(AUD_CNTL_ST_B, dword);
734 for (i = 0; i < 8; i++)
735 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
736 printf("\n");
737
738}
739
740
741#undef AUD_CONFIG_A
742#undef AUD_MISC_CTRL_A
743#undef AUD_VID_DID
744#undef AUD_RID
745#undef AUD_CTS_ENABLE_A
746#undef AUD_PWRST
747#undef AUD_HDMIW_HDMIEDID_A
748#undef AUD_HDMIW_INFOFR_A
749#undef AUD_PORT_EN_HD_CFG
750#undef AUD_OUT_DIG_CNVT_A
751#undef AUD_OUT_STR_DESC_A
752#undef AUD_OUT_CH_STR
753#undef AUD_PINW_CONNLNG_LIST
754#undef AUD_CNTL_ST_A
755#undef AUD_HDMIW_STATUS
756#undef AUD_CONFIG_B
757#undef AUD_MISC_CTRL_B
758#undef AUD_CTS_ENABLE_B
759#undef AUD_HDMIW_HDMIEDID_B
760#undef AUD_HDMIW_INFOFR_B
761#undef AUD_OUT_DIG_CNVT_B
762#undef AUD_OUT_STR_DESC_B
763#undef AUD_CNTL_ST_B
764
765/*
766 * CougarPoint registers
767 */
Wu Fengguang97d20312011-11-12 11:12:45 +0800768#define DP_CTL_B 0xE4100
Wu Fengguang020abdb2010-04-19 13:13:06 +0800769#define DP_CTL_C 0xE4200
770#define DP_AUX_CTL_C 0xE4210
771#define DP_AUX_TST_C 0xE4228
772#define SPORT_DDI_CRC_C 0xE4250
773#define SPORT_DDI_CRC_R 0xE4264
774#define DP_CTL_D 0xE4300
775#define DP_AUX_CTL_D 0xE4310
776#define DP_AUX_TST_D 0xE4328
777#define SPORT_DDI_CRC_CTL_D 0xE4350
778#define AUD_CONFIG_A 0xE5000
779#define AUD_MISC_CTRL_A 0xE5010
780#define AUD_VID_DID 0xE5020
781#define AUD_RID 0xE5024
782#define AUD_CTS_ENABLE_A 0xE5028
783#define AUD_PWRST 0xE504C
784#define AUD_HDMIW_HDMIEDID_A 0xE5050
785#define AUD_HDMIW_INFOFR_A 0xE5054
786#define AUD_PORT_EN_HD_CFG 0xE507C
787#define AUD_OUT_DIG_CNVT_A 0xE5080
788#define AUD_OUT_STR_DESC_A 0xE5084
789#define AUD_OUT_CH_STR 0xE5088
790#define AUD_PINW_CONNLNG_LIST 0xE50A8
791#define AUD_PINW_CONNLNG_SELA 0xE50AC
792#define AUD_CNTL_ST_A 0xE50B4
793#define AUD_CNTRL_ST2 0xE50C0
794#define AUD_CNTRL_ST3 0xE50C4
795#define AUD_HDMIW_STATUS 0xE50D4
796#define AUD_CONFIG_B 0xE5100
797#define AUD_MISC_CTRL_B 0xE5110
798#define AUD_CTS_ENABLE_B 0xE5128
799#define AUD_HDMIW_HDMIEDID_B 0xE5150
800#define AUD_HDMIW_INFOFR_B 0xE5154
801#define AUD_OUT_DIG_CNVT_B 0xE5180
802#define AUD_OUT_STR_DESC_B 0xE5184
803#define AUD_CNTL_ST_B 0xE51B4
804#define AUD_CONFIG_C 0xE5200
805#define AUD_MISC_CTRL_C 0xE5210
806#define AUD_CTS_ENABLE_C 0xE5228
807#define AUD_HDMIW_HDMIEDID_C 0xE5250
808#define AUD_HDMIW_INFOFR_C 0xE5254
809#define AUD_OUT_DIG_CNVT_C 0xE5280
810#define AUD_OUT_STR_DESC_C 0xE5284
811#define AUD_CNTL_ST_C 0xE52B4
812#define AUD_CONFIG_D 0xE5300
813#define AUD_MISC_CTRL_D 0xE5310
814#define AUD_CTS_ENABLE_D 0xE5328
815#define AUD_HDMIW_HDMIEDID_D 0xE5350
816#define AUD_HDMIW_INFOFR_D 0xE5354
817#define AUD_OUT_DIG_CNVT_D 0xE5380
818#define AUD_OUT_STR_DESC_D 0xE5384
819#define AUD_CNTL_ST_D 0xE53B4
820
821
822static void dump_cpt(void)
823{
824 uint32_t dword;
825 int i;
826
827 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
828 dump_reg(HDMIC, "HDMI Port C Control");
829 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguang97d20312011-11-12 11:12:45 +0800830 dump_reg(DP_CTL_B, "DisplayPort B Control");
831 dump_reg(DP_CTL_C, "DisplayPort C Control");
832 dump_reg(DP_CTL_D, "DisplayPort D Control");
833 dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control");
834 dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control");
835 dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800836 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
837 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
838 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
839 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
840 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
841 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800842 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
843 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
844 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
845 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
846 dump_reg(AUD_RID, "Audio Revision ID");
847 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
848 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800849 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
850 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
851 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800852 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800853 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
854 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
855 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800856 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
857 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800858 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
859 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
860 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800861 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
862 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
863 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800864 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
865 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
866 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
867 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
868 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
869 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800870
871 printf("\nDetails:\n\n");
872
873 dword = INREG(AUD_VID_DID);
874 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
875 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
876
877 dword = INREG(AUD_RID);
878 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
879 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
880 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
881 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
882
883 dword = INREG(HDMIB);
884 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
885 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
886 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
887 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
888 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
889 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
890 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
891 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
892
893 dword = INREG(HDMIC);
894 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
895 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
896 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
897 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
898 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
899 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
900 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
901 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
902
903 dword = INREG(HDMID);
904 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
905 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
906 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
907 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
908 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
909 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
910 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
911 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
912
Wu Fengguang97d20312011-11-12 11:12:45 +0800913 dword = INREG(DP_CTL_B);
914 printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
915 printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800916 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800917 printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
918 printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
919 printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800920
Wu Fengguang97d20312011-11-12 11:12:45 +0800921 dword = INREG(DP_CTL_C);
922 printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
923 printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800924 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800925 printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
926 printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
927 printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800928
Wu Fengguang97d20312011-11-12 11:12:45 +0800929 dword = INREG(DP_CTL_D);
930 printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
931 printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800932 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +0800933 printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
934 printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
935 printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800936
937 dword = INREG(AUD_CONFIG_A);
938 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
939 OPNAME(pixel_clock, BITS(dword, 19, 16)));
940 dword = INREG(AUD_CONFIG_B);
941 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
942 OPNAME(pixel_clock, BITS(dword, 19, 16)));
943 dword = INREG(AUD_CONFIG_C);
944 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
945 OPNAME(pixel_clock, BITS(dword, 19, 16)));
946
947 dword = INREG(AUD_CTS_ENABLE_A);
948 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
949 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
950 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
951 dword = INREG(AUD_CTS_ENABLE_B);
952 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
953 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
954 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
955 dword = INREG(AUD_CTS_ENABLE_C);
956 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
957 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
958 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
959
960 dword = INREG(AUD_MISC_CTRL_A);
961 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
962 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
963 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
964 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
965 dword = INREG(AUD_MISC_CTRL_B);
966 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
967 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
968 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
969 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
970 dword = INREG(AUD_MISC_CTRL_C);
971 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
972 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
973 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
974 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
975
976 dword = INREG(AUD_PWRST);
977 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
978 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
979 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
980 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
981 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
982 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
983 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
984 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
985 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
986 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
987 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
988 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
989 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
990 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
991
992 dword = INREG(AUD_PORT_EN_HD_CFG);
993 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
994 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
995 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
996 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
997 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
998 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
999 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
1000 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
1001 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
1002 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
1003 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
1004 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
1005
1006 dword = INREG(AUD_OUT_DIG_CNVT_A);
1007 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1008 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1009 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1010 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001011 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001012 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1013 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1014 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1015 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1016 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1017
1018 dword = INREG(AUD_OUT_DIG_CNVT_B);
1019 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1020 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1021 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1022 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001023 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001024 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1025 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1026 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1027 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1028 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1029
1030 dword = INREG(AUD_OUT_DIG_CNVT_C);
1031 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1032 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1033 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1034 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001035 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001036 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1037 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1038 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1039 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1040 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1041
1042 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1043 for (i = 0; i < 8; i++) {
1044 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1045 dword = INREG(AUD_OUT_CH_STR);
1046 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1047 1 + BITS(dword, 3, 0),
1048 1 + BITS(dword, 7, 4),
1049 1 + BITS(dword, 15, 12),
1050 1 + BITS(dword, 23, 20));
1051 }
1052
1053 dword = INREG(AUD_OUT_STR_DESC_A);
1054 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001055 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001056 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
1057 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1058
1059 dword = INREG(AUD_OUT_STR_DESC_B);
1060 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001061 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001062 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
1063 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1064
1065 dword = INREG(AUD_OUT_STR_DESC_C);
1066 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001067 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001068 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
1069 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1070
1071 dword = INREG(AUD_PINW_CONNLNG_SEL);
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001072 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
1073 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
1074 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001075
1076 dword = INREG(AUD_CNTL_ST_A);
1077 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1078 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001079 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1080 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001081 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1082 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1083 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1084 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1085 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1086
1087 dword = INREG(AUD_CNTL_ST_B);
1088 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1089 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001090 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1091 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001092 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1093 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1094 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1095 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1096 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1097
1098 dword = INREG(AUD_CNTL_ST_C);
1099 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1100 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001101 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1102 printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001103 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1104 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1105 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1106 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1107 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1108
1109 dword = INREG(AUD_CNTRL_ST2);
1110 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1111 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1112 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1113 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1114 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1115 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
1116
1117 dword = INREG(AUD_CNTRL_ST3);
1118 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3));
1119 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1120 BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]);
1121 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7));
1122 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1123 BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]);
1124 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11));
1125 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1126 BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]);
1127
1128 dword = INREG(AUD_HDMIW_STATUS);
1129 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1130 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1131 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1132 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1133 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1134 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1135 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1136 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
1137
1138 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1139 dword = INREG(AUD_CNTL_ST_A);
1140 dword &= ~BITMASK(9, 5);
1141 OUTREG(AUD_CNTL_ST_A, dword);
1142 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1143 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1144 printf("\n");
1145
1146 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1147 dword = INREG(AUD_CNTL_ST_B);
1148 dword &= ~BITMASK(9, 5);
1149 OUTREG(AUD_CNTL_ST_B, dword);
1150 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1151 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1152 printf("\n");
1153
1154 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1155 dword = INREG(AUD_CNTL_ST_C);
1156 dword &= ~BITMASK(9, 5);
1157 OUTREG(AUD_CNTL_ST_C, dword);
1158 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1159 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1160 printf("\n");
1161
1162 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1163 dword = INREG(AUD_CNTL_ST_A);
1164 dword &= ~BITMASK(20, 18);
1165 dword &= ~BITMASK(3, 0);
1166 OUTREG(AUD_CNTL_ST_A, dword);
1167 for (i = 0; i < 8; i++)
1168 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1169 printf("\n");
1170
1171 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1172 dword = INREG(AUD_CNTL_ST_B);
1173 dword &= ~BITMASK(20, 18);
1174 dword &= ~BITMASK(3, 0);
1175 OUTREG(AUD_CNTL_ST_B, dword);
1176 for (i = 0; i < 8; i++)
1177 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1178 printf("\n");
1179
1180 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1181 dword = INREG(AUD_CNTL_ST_C);
1182 dword &= ~BITMASK(20, 18);
1183 dword &= ~BITMASK(3, 0);
1184 OUTREG(AUD_CNTL_ST_C, dword);
1185 for (i = 0; i < 8; i++)
1186 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1187 printf("\n");
1188
1189}
1190
1191int main(int argc, char **argv)
1192{
1193 struct pci_device *pci_dev;
1194
1195 pci_dev = intel_get_pci_device();
1196 devid = pci_dev->device_id; /* XXX not true when mapping! */
1197
1198 do_self_tests();
1199
1200 if (argc == 2)
1201 intel_map_file(argv[1]);
1202 else
1203 intel_get_mmio(pci_dev);
1204
Wu Fengguang63e3c372011-11-12 11:12:44 +08001205 if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
Wu Fengguang020abdb2010-04-19 13:13:06 +08001206 intel_check_pch();
1207 dump_cpt();
Chris Wilson3c5c8ba2011-02-01 13:35:36 +00001208 } else if (IS_GEN5(devid))
Wu Fengguang020abdb2010-04-19 13:13:06 +08001209 dump_ironlake();
1210 else
1211 dump_eaglelake();
1212
1213 return 0;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001214}