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Alex Deucher09361392015-04-20 12:04:22 -04001/*
2 * Copyright © 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef _AMDGPU_INTERNAL_H_
25#define _AMDGPU_INTERNAL_H_
26
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <assert.h>
32#include <pthread.h>
33#include "xf86atomic.h"
34#include "amdgpu.h"
35#include "util_double_list.h"
36
37#define AMDGPU_CS_MAX_RINGS 8
monk.liu2f2c8ac2015-04-23 13:18:59 +080038/* do not use below macro if b is not power of 2 aligned value */
Jack Xiao74547792015-05-07 16:07:03 +080039#define __round_mask(x, y) ((__typeof__(x))((y)-1))
40#define ROUND_UP(x, y) ((((x)-1) | __round_mask(x, y))+1)
41#define ROUND_DOWN(x, y) ((x) & ~__round_mask(x, y))
Alex Deucher09361392015-04-20 12:04:22 -040042
Jammy Zhou241cf6d2015-05-13 01:14:11 +080043#define AMDGPU_INVALID_VA_ADDRESS 0xffffffffffffffff
44
Alex Deucher09361392015-04-20 12:04:22 -040045struct amdgpu_bo_va_hole {
46 struct list_head list;
47 uint64_t offset;
48 uint64_t size;
49};
50
51struct amdgpu_bo_va_mgr {
Ken Wang322d02d2015-05-21 17:21:21 +080052 atomic_t refcount;
Alex Deucher09361392015-04-20 12:04:22 -040053 /* the start virtual address */
54 uint64_t va_offset;
Jammy Zhou241cf6d2015-05-13 01:14:11 +080055 uint64_t va_max;
Alex Deucher09361392015-04-20 12:04:22 -040056 struct list_head va_holes;
57 pthread_mutex_t bo_va_mutex;
58 uint32_t va_alignment;
59};
60
61struct amdgpu_device {
62 atomic_t refcount;
63 int fd;
64 int flink_fd;
65 unsigned major_version;
66 unsigned minor_version;
67
68 /** List of buffer handles. Protected by bo_table_mutex. */
69 struct util_hash_table *bo_handles;
70 /** List of buffer GEM flink names. Protected by bo_table_mutex. */
71 struct util_hash_table *bo_flink_names;
Alex Deucher09361392015-04-20 12:04:22 -040072 /** This protects all hash tables. */
73 pthread_mutex_t bo_table_mutex;
Alex Deucher09361392015-04-20 12:04:22 -040074 struct drm_amdgpu_info_device dev_info;
75 struct amdgpu_gpu_info info;
Ken Wang322d02d2015-05-21 17:21:21 +080076 struct amdgpu_bo_va_mgr *vamgr;
Alex Deucher09361392015-04-20 12:04:22 -040077};
78
79struct amdgpu_bo {
80 atomic_t refcount;
81 struct amdgpu_device *dev;
82
83 uint64_t alloc_size;
84 uint64_t virtual_mc_base_address;
85
86 uint32_t handle;
87 uint32_t flink_name;
88
89 pthread_mutex_t cpu_access_mutex;
90 void *cpu_ptr;
91 int cpu_map_count;
92};
93
Christian König6dc2eaf2015-04-22 14:52:34 +020094struct amdgpu_bo_list {
95 struct amdgpu_device *dev;
96
97 uint32_t handle;
98};
99
Alex Deucher09361392015-04-20 12:04:22 -0400100/*
101 * There are three mutexes.
102 * To avoid deadlock, only hold the mutexes in this order:
103 * sequence_mutex -> pendings_mutex -> pool_mutex.
104*/
105struct amdgpu_context {
Christian König9c2afff2015-04-22 12:21:13 +0200106 struct amdgpu_device *dev;
Alex Deucher09361392015-04-20 12:04:22 -0400107 /** Mutex for accessing fences and to maintain command submissions
108 and pending lists in good sequence. */
109 pthread_mutex_t sequence_mutex;
110 /** Buffer for user fences */
111 struct amdgpu_ib *fence_ib;
112 /** The newest expired fence for the ring of the ip blocks. */
113 uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
114 /** Mutex for accessing pendings list. */
115 pthread_mutex_t pendings_mutex;
116 /** Pending IBs. */
117 struct list_head pendings[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
118 /** Freed IBs not yet in pool */
119 struct list_head freed;
120 /** Mutex for accessing free ib pool. */
121 pthread_mutex_t pool_mutex;
122 /** Internal free IB pools. */
123 struct list_head ib_pools[AMDGPU_CS_IB_SIZE_NUM];
124 /* context id*/
125 uint32_t id;
126};
127
128struct amdgpu_ib {
Christian König9c2afff2015-04-22 12:21:13 +0200129 amdgpu_context_handle context;
Alex Deucher09361392015-04-20 12:04:22 -0400130 struct list_head list_node;
131 amdgpu_bo_handle buf_handle;
132 void *cpu;
133 uint64_t virtual_mc_base_address;
134 enum amdgpu_cs_ib_size ib_size;
135 uint64_t cs_handle;
136};
137
138/**
139 * Functions.
140 */
141
142void amdgpu_device_free_internal(amdgpu_device_handle dev);
143
144void amdgpu_bo_free_internal(amdgpu_bo_handle bo);
145
Ken Wang322d02d2015-05-21 17:21:21 +0800146struct amdgpu_bo_va_mgr* amdgpu_vamgr_get_global(struct amdgpu_device *dev);
147
148void amdgpu_vamgr_reference(struct amdgpu_bo_va_mgr **dst, struct amdgpu_bo_va_mgr *src);
Alex Deucher09361392015-04-20 12:04:22 -0400149
150uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr,
Ken Wang322d02d2015-05-21 17:21:21 +0800151 uint64_t size, uint64_t alignment);
Alex Deucher09361392015-04-20 12:04:22 -0400152
Ken Wang322d02d2015-05-21 17:21:21 +0800153void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va,
154 uint64_t size);
Alex Deucher09361392015-04-20 12:04:22 -0400155
156int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
157
158uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
159
160/**
161 * Inline functions.
162 */
163
164/**
165 * Increment src and decrement dst as if we were updating references
166 * for an assignment between 2 pointers of some objects.
167 *
168 * \return true if dst is 0
169 */
170static inline bool update_references(atomic_t *dst, atomic_t *src)
171{
172 if (dst != src) {
173 /* bump src first */
174 if (src) {
175 assert(atomic_read(src) > 0);
176 atomic_inc(src);
177 }
178 if (dst) {
179 assert(atomic_read(dst) > 0);
180 return atomic_dec_and_test(dst);
181 }
182 }
183 return false;
184}
185
186/**
187 * Assignment between two amdgpu_bo pointers with reference counting.
188 *
189 * Usage:
190 * struct amdgpu_bo *dst = ... , *src = ...;
191 *
192 * dst = src;
193 * // No reference counting. Only use this when you need to move
194 * // a reference from one pointer to another.
195 *
196 * amdgpu_bo_reference(&dst, src);
197 * // Reference counters are updated. dst is decremented and src is
198 * // incremented. dst is freed if its reference counter is 0.
199 */
200static inline void amdgpu_bo_reference(struct amdgpu_bo **dst,
201 struct amdgpu_bo *src)
202{
203 if (update_references(&(*dst)->refcount, &src->refcount))
204 amdgpu_bo_free_internal(*dst);
205 *dst = src;
206}
207
208/**
209 * Assignment between two amdgpu_device pointers with reference counting.
210 *
211 * Usage:
212 * struct amdgpu_device *dst = ... , *src = ...;
213 *
214 * dst = src;
215 * // No reference counting. Only use this when you need to move
216 * // a reference from one pointer to another.
217 *
218 * amdgpu_device_reference(&dst, src);
219 * // Reference counters are updated. dst is decremented and src is
220 * // incremented. dst is freed if its reference counter is 0.
221 */
222void amdgpu_device_reference(struct amdgpu_device **dst,
223 struct amdgpu_device *src);
224#endif