Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1 | /************************************************************************** |
| 2 | * |
| 3 | * Copyright © 2007 Red Hat Inc. |
Eric Anholt | c9ce2ed | 2012-03-09 16:08:23 -0800 | [diff] [blame] | 4 | * Copyright © 2007-2012 Intel Corporation |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 5 | * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA |
| 6 | * All Rights Reserved. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 20 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 21 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 22 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * The above copyright notice and this permission notice (including the |
| 25 | * next paragraph) shall be included in all copies or substantial portions |
| 26 | * of the Software. |
| 27 | * |
| 28 | * |
| 29 | **************************************************************************/ |
| 30 | /* |
| 31 | * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> |
| 32 | * Keith Whitwell <keithw-at-tungstengraphics-dot-com> |
| 33 | * Eric Anholt <eric@anholt.net> |
| 34 | * Dave Airlie <airlied@linux.ie> |
| 35 | */ |
| 36 | |
Eric Anholt | 368b392 | 2008-09-10 13:54:34 -0700 | [diff] [blame] | 37 | #ifdef HAVE_CONFIG_H |
| 38 | #include "config.h" |
| 39 | #endif |
| 40 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 41 | #include <xf86drm.h> |
Pauli Nieminen | 21105bc | 2010-03-10 13:35:59 +0200 | [diff] [blame] | 42 | #include <xf86atomic.h> |
Jesse Barnes | 276c07d | 2008-11-13 13:52:04 -0800 | [diff] [blame] | 43 | #include <fcntl.h> |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 44 | #include <stdio.h> |
| 45 | #include <stdlib.h> |
| 46 | #include <string.h> |
| 47 | #include <unistd.h> |
| 48 | #include <assert.h> |
Eric Anholt | 6df7b07 | 2008-06-12 23:22:26 -0700 | [diff] [blame] | 49 | #include <pthread.h> |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 50 | #include <sys/ioctl.h> |
| 51 | #include <sys/mman.h> |
Jesse Barnes | 276c07d | 2008-11-13 13:52:04 -0800 | [diff] [blame] | 52 | #include <sys/stat.h> |
| 53 | #include <sys/types.h> |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 54 | #include <stdbool.h> |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 55 | |
| 56 | #include "errno.h" |
Eric Anholt | 72abe98 | 2009-02-18 13:06:35 -0800 | [diff] [blame] | 57 | #include "libdrm_lists.h" |
Eric Anholt | c485742 | 2008-06-03 10:20:49 -0700 | [diff] [blame] | 58 | #include "intel_bufmgr.h" |
Eric Anholt | 738e36a | 2008-09-05 10:35:32 +0100 | [diff] [blame] | 59 | #include "intel_bufmgr_priv.h" |
Eric Anholt | cbdd627 | 2009-01-27 17:16:11 -0800 | [diff] [blame] | 60 | #include "intel_chipset.h" |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 61 | #include "intel_aub.h" |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 62 | #include "string.h" |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 63 | |
| 64 | #include "i915_drm.h" |
| 65 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 66 | #ifdef HAVE_VALGRIND |
| 67 | #include <valgrind.h> |
| 68 | #include <memcheck.h> |
| 69 | #define VG(x) x |
| 70 | #else |
| 71 | #define VG(x) |
| 72 | #endif |
| 73 | |
| 74 | #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s))) |
| 75 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 76 | #define DBG(...) do { \ |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 77 | if (bufmgr_gem->bufmgr.debug) \ |
| 78 | fprintf(stderr, __VA_ARGS__); \ |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 79 | } while (0) |
| 80 | |
Eric Anholt | 0ec768e | 2010-06-04 17:09:11 -0700 | [diff] [blame] | 81 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) |
| 82 | |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 83 | typedef struct _drm_intel_bo_gem drm_intel_bo_gem; |
Keith Packard | a919ff5 | 2008-06-05 15:58:09 -0700 | [diff] [blame] | 84 | |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 85 | struct drm_intel_gem_bo_bucket { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 86 | drmMMListHead head; |
| 87 | unsigned long size; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 90 | typedef struct _drm_intel_bufmgr_gem { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 91 | drm_intel_bufmgr bufmgr; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 92 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 93 | int fd; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 94 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 95 | int max_relocs; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 96 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 97 | pthread_mutex_t lock; |
Eric Anholt | 6df7b07 | 2008-06-12 23:22:26 -0700 | [diff] [blame] | 98 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 99 | struct drm_i915_gem_exec_object *exec_objects; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 100 | struct drm_i915_gem_exec_object2 *exec2_objects; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 101 | drm_intel_bo **exec_bos; |
| 102 | int exec_size; |
| 103 | int exec_count; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 104 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 105 | /** Array of lists of cached gem objects of power-of-two sizes */ |
Eric Anholt | 0ec768e | 2010-06-04 17:09:11 -0700 | [diff] [blame] | 106 | struct drm_intel_gem_bo_bucket cache_bucket[14 * 4]; |
| 107 | int num_buckets; |
Chris Wilson | f16b416 | 2010-06-21 15:21:48 +0100 | [diff] [blame] | 108 | time_t time; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 109 | |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 110 | drmMMListHead named; |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 111 | drmMMListHead vma_cache; |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 112 | int vma_count, vma_open, vma_max; |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 113 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 114 | uint64_t gtt_size; |
| 115 | int available_fences; |
| 116 | int pci_device; |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 117 | int gen; |
Chris Wilson | 3624577 | 2010-10-29 10:49:54 +0100 | [diff] [blame] | 118 | unsigned int has_bsd : 1; |
| 119 | unsigned int has_blt : 1; |
| 120 | unsigned int has_relaxed_fencing : 1; |
Eugeni Dodonov | 151cdcf | 2012-01-17 15:20:19 -0200 | [diff] [blame] | 121 | unsigned int has_llc : 1; |
Ben Widawsky | 971c080 | 2012-06-05 11:30:48 -0700 | [diff] [blame] | 122 | unsigned int has_wait_timeout : 1; |
Chris Wilson | 3624577 | 2010-10-29 10:49:54 +0100 | [diff] [blame] | 123 | unsigned int bo_reuse : 1; |
Kenneth Graunke | 6e642db | 2011-10-11 14:38:34 -0700 | [diff] [blame] | 124 | unsigned int no_exec : 1; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 125 | bool fenced_relocs; |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 126 | |
| 127 | FILE *aub_file; |
| 128 | uint32_t aub_offset; |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 129 | } drm_intel_bufmgr_gem; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 130 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 131 | #define DRM_INTEL_RELOC_FENCE (1<<0) |
| 132 | |
| 133 | typedef struct _drm_intel_reloc_target_info { |
| 134 | drm_intel_bo *bo; |
| 135 | int flags; |
| 136 | } drm_intel_reloc_target; |
| 137 | |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 138 | struct _drm_intel_bo_gem { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 139 | drm_intel_bo bo; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 140 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 141 | atomic_t refcount; |
| 142 | uint32_t gem_handle; |
| 143 | const char *name; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 144 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 145 | /** |
| 146 | * Kenel-assigned global name for this object |
| 147 | */ |
| 148 | unsigned int global_name; |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 149 | drmMMListHead name_list; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 150 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 151 | /** |
| 152 | * Index of the buffer within the validation list while preparing a |
| 153 | * batchbuffer execution. |
| 154 | */ |
| 155 | int validate_index; |
Keith Packard | 18f091d | 2008-12-15 15:08:12 -0800 | [diff] [blame] | 156 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 157 | /** |
| 158 | * Current tiling mode |
| 159 | */ |
| 160 | uint32_t tiling_mode; |
| 161 | uint32_t swizzle_mode; |
Chris Wilson | 056aa9b | 2010-06-21 14:31:29 +0100 | [diff] [blame] | 162 | unsigned long stride; |
Eric Anholt | 3f3c5be | 2009-07-09 17:49:46 -0700 | [diff] [blame] | 163 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 164 | time_t free_time; |
Keith Packard | 329e086 | 2008-06-05 16:05:35 -0700 | [diff] [blame] | 165 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 166 | /** Array passed to the DRM containing relocation information. */ |
| 167 | struct drm_i915_gem_relocation_entry *relocs; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 168 | /** |
| 169 | * Array of info structs corresponding to relocs[i].target_handle etc |
| 170 | */ |
| 171 | drm_intel_reloc_target *reloc_target_info; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 172 | /** Number of entries in relocs */ |
| 173 | int reloc_count; |
| 174 | /** Mapped address for the buffer, saved across map/unmap cycles */ |
| 175 | void *mem_virtual; |
| 176 | /** GTT virtual address for the buffer, saved across map/unmap cycles */ |
| 177 | void *gtt_virtual; |
Chris Wilson | c549a77 | 2011-12-05 10:14:34 +0000 | [diff] [blame] | 178 | int map_count; |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 179 | drmMMListHead vma_list; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 180 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 181 | /** BO cache list */ |
| 182 | drmMMListHead head; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 183 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 184 | /** |
| 185 | * Boolean of whether this BO and its children have been included in |
| 186 | * the current drm_intel_bufmgr_check_aperture_space() total. |
| 187 | */ |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 188 | bool included_in_check_aperture; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 189 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 190 | /** |
| 191 | * Boolean of whether this buffer has been used as a relocation |
| 192 | * target and had its size accounted for, and thus can't have any |
| 193 | * further relocations added to it. |
| 194 | */ |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 195 | bool used_as_reloc_target; |
Keith Packard | 5b5ce30 | 2009-05-11 13:42:12 -0700 | [diff] [blame] | 196 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 197 | /** |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 198 | * Boolean of whether we have encountered an error whilst building the relocation tree. |
| 199 | */ |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 200 | bool has_error; |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 201 | |
| 202 | /** |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 203 | * Boolean of whether this buffer can be re-used |
| 204 | */ |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 205 | bool reusable; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 206 | |
| 207 | /** |
| 208 | * Size in bytes of this buffer and its relocation descendents. |
| 209 | * |
| 210 | * Used to avoid costly tree walking in |
| 211 | * drm_intel_bufmgr_check_aperture in the common case. |
| 212 | */ |
| 213 | int reloc_tree_size; |
| 214 | |
| 215 | /** |
| 216 | * Number of potential fence registers required by this buffer and its |
| 217 | * relocations. |
| 218 | */ |
| 219 | int reloc_tree_fences; |
Eric Anholt | 4cb01ee | 2011-10-28 13:12:16 -0700 | [diff] [blame] | 220 | |
| 221 | /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */ |
| 222 | bool mapped_cpu_write; |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 223 | |
| 224 | uint32_t aub_offset; |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 225 | |
| 226 | drm_intel_aub_annotation *aub_annotations; |
| 227 | unsigned aub_annotation_count; |
Keith Packard | a919ff5 | 2008-06-05 15:58:09 -0700 | [diff] [blame] | 228 | }; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 229 | |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 230 | static unsigned int |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 231 | drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count); |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 232 | |
| 233 | static unsigned int |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 234 | drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count); |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 235 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 236 | static int |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 237 | drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, |
| 238 | uint32_t * swizzle_mode); |
Keith Packard | 18f091d | 2008-12-15 15:08:12 -0800 | [diff] [blame] | 239 | |
| 240 | static int |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 241 | drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo, |
| 242 | uint32_t tiling_mode, |
| 243 | uint32_t stride); |
Keith Packard | 18f091d | 2008-12-15 15:08:12 -0800 | [diff] [blame] | 244 | |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 245 | static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo, |
| 246 | time_t time); |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 247 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 248 | static void drm_intel_gem_bo_unreference(drm_intel_bo *bo); |
Keith Packard | 18f091d | 2008-12-15 15:08:12 -0800 | [diff] [blame] | 249 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 250 | static void drm_intel_gem_bo_free(drm_intel_bo *bo); |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 251 | |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 252 | static unsigned long |
| 253 | drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size, |
| 254 | uint32_t *tiling_mode) |
| 255 | { |
| 256 | unsigned long min_size, max_size; |
| 257 | unsigned long i; |
| 258 | |
| 259 | if (*tiling_mode == I915_TILING_NONE) |
| 260 | return size; |
| 261 | |
| 262 | /* 965+ just need multiples of page size for tiling */ |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 263 | if (bufmgr_gem->gen >= 4) |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 264 | return ROUND_UP_TO(size, 4096); |
| 265 | |
| 266 | /* Older chips need powers of two, of at least 512k or 1M */ |
Eric Anholt | acbaff2 | 2010-03-02 15:24:50 -0800 | [diff] [blame] | 267 | if (bufmgr_gem->gen == 3) { |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 268 | min_size = 1024*1024; |
| 269 | max_size = 128*1024*1024; |
| 270 | } else { |
| 271 | min_size = 512*1024; |
| 272 | max_size = 64*1024*1024; |
| 273 | } |
| 274 | |
| 275 | if (size > max_size) { |
| 276 | *tiling_mode = I915_TILING_NONE; |
| 277 | return size; |
| 278 | } |
| 279 | |
Chris Wilson | 3624577 | 2010-10-29 10:49:54 +0100 | [diff] [blame] | 280 | /* Do we need to allocate every page for the fence? */ |
| 281 | if (bufmgr_gem->has_relaxed_fencing) |
| 282 | return ROUND_UP_TO(size, 4096); |
| 283 | |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 284 | for (i = min_size; i < size; i <<= 1) |
| 285 | ; |
| 286 | |
| 287 | return i; |
| 288 | } |
| 289 | |
| 290 | /* |
| 291 | * Round a given pitch up to the minimum required for X tiling on a |
| 292 | * given chip. We use 512 as the minimum to allow for a later tiling |
| 293 | * change. |
| 294 | */ |
| 295 | static unsigned long |
| 296 | drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, |
Chris Wilson | 726210f | 2010-06-24 11:38:00 +0100 | [diff] [blame] | 297 | unsigned long pitch, uint32_t *tiling_mode) |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 298 | { |
Eric Anholt | 1d4d1e6 | 2010-03-04 16:09:40 -0800 | [diff] [blame] | 299 | unsigned long tile_width; |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 300 | unsigned long i; |
| 301 | |
Eric Anholt | 7c697b1 | 2010-03-17 10:05:55 -0700 | [diff] [blame] | 302 | /* If untiled, then just align it so that we can do rendering |
| 303 | * to it with the 3D engine. |
| 304 | */ |
Chris Wilson | 726210f | 2010-06-24 11:38:00 +0100 | [diff] [blame] | 305 | if (*tiling_mode == I915_TILING_NONE) |
Eric Anholt | 7c697b1 | 2010-03-17 10:05:55 -0700 | [diff] [blame] | 306 | return ALIGN(pitch, 64); |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 307 | |
Daniel Vetter | 194aa1b | 2011-09-22 22:20:53 +0200 | [diff] [blame] | 308 | if (*tiling_mode == I915_TILING_X |
Eric Anholt | 078bc5b | 2011-12-20 13:10:36 -0800 | [diff] [blame] | 309 | || (IS_915(bufmgr_gem->pci_device) |
| 310 | && *tiling_mode == I915_TILING_Y)) |
Eric Anholt | 1d4d1e6 | 2010-03-04 16:09:40 -0800 | [diff] [blame] | 311 | tile_width = 512; |
| 312 | else |
| 313 | tile_width = 128; |
| 314 | |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 315 | /* 965 is flexible */ |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 316 | if (bufmgr_gem->gen >= 4) |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 317 | return ROUND_UP_TO(pitch, tile_width); |
| 318 | |
Chris Wilson | 726210f | 2010-06-24 11:38:00 +0100 | [diff] [blame] | 319 | /* The older hardware has a maximum pitch of 8192 with tiled |
| 320 | * surfaces, so fallback to untiled if it's too large. |
| 321 | */ |
| 322 | if (pitch > 8192) { |
| 323 | *tiling_mode = I915_TILING_NONE; |
| 324 | return ALIGN(pitch, 64); |
| 325 | } |
| 326 | |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 327 | /* Pre-965 needs power of two tile width */ |
| 328 | for (i = tile_width; i < pitch; i <<= 1) |
| 329 | ; |
| 330 | |
| 331 | return i; |
| 332 | } |
| 333 | |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 334 | static struct drm_intel_gem_bo_bucket * |
| 335 | drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem, |
| 336 | unsigned long size) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 337 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 338 | int i; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 339 | |
Eric Anholt | 0ec768e | 2010-06-04 17:09:11 -0700 | [diff] [blame] | 340 | for (i = 0; i < bufmgr_gem->num_buckets; i++) { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 341 | struct drm_intel_gem_bo_bucket *bucket = |
| 342 | &bufmgr_gem->cache_bucket[i]; |
| 343 | if (bucket->size >= size) { |
| 344 | return bucket; |
| 345 | } |
Eric Anholt | 78fa590 | 2009-07-06 11:55:28 -0700 | [diff] [blame] | 346 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 347 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 348 | return NULL; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 349 | } |
| 350 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 351 | static void |
| 352 | drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 353 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 354 | int i, j; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 355 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 356 | for (i = 0; i < bufmgr_gem->exec_count; i++) { |
| 357 | drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; |
| 358 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 359 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 360 | if (bo_gem->relocs == NULL) { |
| 361 | DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle, |
| 362 | bo_gem->name); |
| 363 | continue; |
| 364 | } |
| 365 | |
| 366 | for (j = 0; j < bo_gem->reloc_count; j++) { |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 367 | drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 368 | drm_intel_bo_gem *target_gem = |
| 369 | (drm_intel_bo_gem *) target_bo; |
| 370 | |
| 371 | DBG("%2d: %d (%s)@0x%08llx -> " |
| 372 | "%d (%s)@0x%08lx + 0x%08x\n", |
| 373 | i, |
| 374 | bo_gem->gem_handle, bo_gem->name, |
| 375 | (unsigned long long)bo_gem->relocs[j].offset, |
| 376 | target_gem->gem_handle, |
| 377 | target_gem->name, |
| 378 | target_bo->offset, |
| 379 | bo_gem->relocs[j].delta); |
| 380 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 381 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 382 | } |
| 383 | |
Chris Wilson | 9fec2a8 | 2009-12-02 10:42:51 +0000 | [diff] [blame] | 384 | static inline void |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 385 | drm_intel_gem_bo_reference(drm_intel_bo *bo) |
| 386 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 387 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 388 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 389 | atomic_inc(&bo_gem->refcount); |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 390 | } |
| 391 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 392 | /** |
| 393 | * Adds the given buffer to the list of buffers to be validated (moved into the |
| 394 | * appropriate memory type) with the next batch submission. |
| 395 | * |
| 396 | * If a buffer is validated multiple times in a batch submission, it ends up |
| 397 | * with the intersection of the memory type flags and the union of the |
| 398 | * access flags. |
| 399 | */ |
| 400 | static void |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 401 | drm_intel_add_validate_buffer(drm_intel_bo *bo) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 402 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 403 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 404 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 405 | int index; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 406 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 407 | if (bo_gem->validate_index != -1) |
| 408 | return; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 409 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 410 | /* Extend the array of validation entries as necessary. */ |
| 411 | if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) { |
| 412 | int new_size = bufmgr_gem->exec_size * 2; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 413 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 414 | if (new_size == 0) |
| 415 | new_size = 5; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 416 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 417 | bufmgr_gem->exec_objects = |
| 418 | realloc(bufmgr_gem->exec_objects, |
| 419 | sizeof(*bufmgr_gem->exec_objects) * new_size); |
| 420 | bufmgr_gem->exec_bos = |
| 421 | realloc(bufmgr_gem->exec_bos, |
| 422 | sizeof(*bufmgr_gem->exec_bos) * new_size); |
| 423 | bufmgr_gem->exec_size = new_size; |
| 424 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 425 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 426 | index = bufmgr_gem->exec_count; |
| 427 | bo_gem->validate_index = index; |
| 428 | /* Fill in array entry */ |
| 429 | bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle; |
| 430 | bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count; |
| 431 | bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs; |
| 432 | bufmgr_gem->exec_objects[index].alignment = 0; |
| 433 | bufmgr_gem->exec_objects[index].offset = 0; |
| 434 | bufmgr_gem->exec_bos[index] = bo; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 435 | bufmgr_gem->exec_count++; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 436 | } |
| 437 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 438 | static void |
| 439 | drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence) |
| 440 | { |
| 441 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; |
| 442 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; |
| 443 | int index; |
| 444 | |
Eric Anholt | 4710286 | 2010-03-03 10:07:27 -0800 | [diff] [blame] | 445 | if (bo_gem->validate_index != -1) { |
| 446 | if (need_fence) |
| 447 | bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= |
| 448 | EXEC_OBJECT_NEEDS_FENCE; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 449 | return; |
Eric Anholt | 4710286 | 2010-03-03 10:07:27 -0800 | [diff] [blame] | 450 | } |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 451 | |
| 452 | /* Extend the array of validation entries as necessary. */ |
| 453 | if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) { |
| 454 | int new_size = bufmgr_gem->exec_size * 2; |
| 455 | |
| 456 | if (new_size == 0) |
| 457 | new_size = 5; |
| 458 | |
| 459 | bufmgr_gem->exec2_objects = |
| 460 | realloc(bufmgr_gem->exec2_objects, |
| 461 | sizeof(*bufmgr_gem->exec2_objects) * new_size); |
| 462 | bufmgr_gem->exec_bos = |
| 463 | realloc(bufmgr_gem->exec_bos, |
| 464 | sizeof(*bufmgr_gem->exec_bos) * new_size); |
| 465 | bufmgr_gem->exec_size = new_size; |
| 466 | } |
| 467 | |
| 468 | index = bufmgr_gem->exec_count; |
| 469 | bo_gem->validate_index = index; |
| 470 | /* Fill in array entry */ |
| 471 | bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle; |
| 472 | bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count; |
| 473 | bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs; |
| 474 | bufmgr_gem->exec2_objects[index].alignment = 0; |
| 475 | bufmgr_gem->exec2_objects[index].offset = 0; |
| 476 | bufmgr_gem->exec_bos[index] = bo; |
| 477 | bufmgr_gem->exec2_objects[index].flags = 0; |
| 478 | bufmgr_gem->exec2_objects[index].rsvd1 = 0; |
| 479 | bufmgr_gem->exec2_objects[index].rsvd2 = 0; |
| 480 | if (need_fence) { |
| 481 | bufmgr_gem->exec2_objects[index].flags |= |
| 482 | EXEC_OBJECT_NEEDS_FENCE; |
| 483 | } |
| 484 | bufmgr_gem->exec_count++; |
| 485 | } |
| 486 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 487 | #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \ |
| 488 | sizeof(uint32_t)) |
| 489 | |
Chris Wilson | e22fb79 | 2009-11-30 22:14:30 +0000 | [diff] [blame] | 490 | static void |
| 491 | drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem, |
| 492 | drm_intel_bo_gem *bo_gem) |
| 493 | { |
| 494 | int size; |
| 495 | |
| 496 | assert(!bo_gem->used_as_reloc_target); |
| 497 | |
| 498 | /* The older chipsets are far-less flexible in terms of tiling, |
| 499 | * and require tiled buffer to be size aligned in the aperture. |
| 500 | * This means that in the worst possible case we will need a hole |
| 501 | * twice as large as the object in order for it to fit into the |
| 502 | * aperture. Optimal packing is for wimps. |
| 503 | */ |
| 504 | size = bo_gem->bo.size; |
Chris Wilson | 51b8950 | 2010-11-22 09:50:06 +0000 | [diff] [blame] | 505 | if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) { |
| 506 | int min_size; |
| 507 | |
| 508 | if (bufmgr_gem->has_relaxed_fencing) { |
| 509 | if (bufmgr_gem->gen == 3) |
| 510 | min_size = 1024*1024; |
| 511 | else |
| 512 | min_size = 512*1024; |
| 513 | |
| 514 | while (min_size < size) |
| 515 | min_size *= 2; |
| 516 | } else |
| 517 | min_size = size; |
| 518 | |
| 519 | /* Account for worst-case alignment. */ |
| 520 | size = 2 * min_size; |
| 521 | } |
Chris Wilson | e22fb79 | 2009-11-30 22:14:30 +0000 | [diff] [blame] | 522 | |
| 523 | bo_gem->reloc_tree_size = size; |
| 524 | } |
| 525 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 526 | static int |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 527 | drm_intel_setup_reloc_list(drm_intel_bo *bo) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 528 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 529 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 530 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 531 | unsigned int max_relocs = bufmgr_gem->max_relocs; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 532 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 533 | if (bo->size / 4 < max_relocs) |
| 534 | max_relocs = bo->size / 4; |
Eric Anholt | 3c9bd06 | 2009-10-05 16:35:32 -0700 | [diff] [blame] | 535 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 536 | bo_gem->relocs = malloc(max_relocs * |
| 537 | sizeof(struct drm_i915_gem_relocation_entry)); |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 538 | bo_gem->reloc_target_info = malloc(max_relocs * |
Chris Wilson | 3506173 | 2010-04-11 18:40:38 +0100 | [diff] [blame] | 539 | sizeof(drm_intel_reloc_target)); |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 540 | if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) { |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 541 | bo_gem->has_error = true; |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 542 | |
| 543 | free (bo_gem->relocs); |
| 544 | bo_gem->relocs = NULL; |
| 545 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 546 | free (bo_gem->reloc_target_info); |
| 547 | bo_gem->reloc_target_info = NULL; |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 548 | |
| 549 | return 1; |
| 550 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 551 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 552 | return 0; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 553 | } |
| 554 | |
Eric Anholt | 8214a65 | 2009-08-27 18:32:07 -0700 | [diff] [blame] | 555 | static int |
| 556 | drm_intel_gem_bo_busy(drm_intel_bo *bo) |
| 557 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 558 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 559 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 560 | struct drm_i915_gem_busy busy; |
| 561 | int ret; |
Eric Anholt | 8214a65 | 2009-08-27 18:32:07 -0700 | [diff] [blame] | 562 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 563 | VG_CLEAR(busy); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 564 | busy.handle = bo_gem->gem_handle; |
Eric Anholt | 8214a65 | 2009-08-27 18:32:07 -0700 | [diff] [blame] | 565 | |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 566 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy); |
Eric Anholt | 8214a65 | 2009-08-27 18:32:07 -0700 | [diff] [blame] | 567 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 568 | return (ret == 0 && busy.busy); |
Eric Anholt | 8214a65 | 2009-08-27 18:32:07 -0700 | [diff] [blame] | 569 | } |
| 570 | |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 571 | static int |
Chris Wilson | 83a35b6 | 2009-11-11 13:04:38 +0000 | [diff] [blame] | 572 | drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem, |
| 573 | drm_intel_bo_gem *bo_gem, int state) |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 574 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 575 | struct drm_i915_gem_madvise madv; |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 576 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 577 | VG_CLEAR(madv); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 578 | madv.handle = bo_gem->gem_handle; |
| 579 | madv.madv = state; |
| 580 | madv.retained = 1; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 581 | drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv); |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 582 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 583 | return madv.retained; |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 584 | } |
| 585 | |
Chris Wilson | 83a35b6 | 2009-11-11 13:04:38 +0000 | [diff] [blame] | 586 | static int |
| 587 | drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv) |
| 588 | { |
| 589 | return drm_intel_gem_bo_madvise_internal |
| 590 | ((drm_intel_bufmgr_gem *) bo->bufmgr, |
| 591 | (drm_intel_bo_gem *) bo, |
| 592 | madv); |
| 593 | } |
| 594 | |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 595 | /* drop the oldest entries that have been purged by the kernel */ |
| 596 | static void |
| 597 | drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem, |
| 598 | struct drm_intel_gem_bo_bucket *bucket) |
| 599 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 600 | while (!DRMLISTEMPTY(&bucket->head)) { |
| 601 | drm_intel_bo_gem *bo_gem; |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 602 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 603 | bo_gem = DRMLISTENTRY(drm_intel_bo_gem, |
| 604 | bucket->head.next, head); |
Chris Wilson | 83a35b6 | 2009-11-11 13:04:38 +0000 | [diff] [blame] | 605 | if (drm_intel_gem_bo_madvise_internal |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 606 | (bufmgr_gem, bo_gem, I915_MADV_DONTNEED)) |
| 607 | break; |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 608 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 609 | DRMLISTDEL(&bo_gem->head); |
| 610 | drm_intel_gem_bo_free(&bo_gem->bo); |
| 611 | } |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 612 | } |
| 613 | |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 614 | static drm_intel_bo * |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 615 | drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, |
| 616 | const char *name, |
| 617 | unsigned long size, |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 618 | unsigned long flags, |
| 619 | uint32_t tiling_mode, |
| 620 | unsigned long stride) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 621 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 622 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; |
| 623 | drm_intel_bo_gem *bo_gem; |
| 624 | unsigned int page_size = getpagesize(); |
| 625 | int ret; |
| 626 | struct drm_intel_gem_bo_bucket *bucket; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 627 | bool alloc_from_cache; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 628 | unsigned long bo_size; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 629 | bool for_render = false; |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 630 | |
| 631 | if (flags & BO_ALLOC_FOR_RENDER) |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 632 | for_render = true; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 633 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 634 | /* Round the allocated size up to a power of two number of pages. */ |
| 635 | bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 636 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 637 | /* If we don't have caching at this size, don't actually round the |
| 638 | * allocation up. |
| 639 | */ |
| 640 | if (bucket == NULL) { |
| 641 | bo_size = size; |
| 642 | if (bo_size < page_size) |
| 643 | bo_size = page_size; |
Eric Anholt | 72abe98 | 2009-02-18 13:06:35 -0800 | [diff] [blame] | 644 | } else { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 645 | bo_size = bucket->size; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 646 | } |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 647 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 648 | pthread_mutex_lock(&bufmgr_gem->lock); |
| 649 | /* Get a buffer out of the cache if available */ |
| 650 | retry: |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 651 | alloc_from_cache = false; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 652 | if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) { |
| 653 | if (for_render) { |
| 654 | /* Allocate new render-target BOs from the tail (MRU) |
| 655 | * of the list, as it will likely be hot in the GPU |
| 656 | * cache and in the aperture for us. |
| 657 | */ |
| 658 | bo_gem = DRMLISTENTRY(drm_intel_bo_gem, |
| 659 | bucket->head.prev, head); |
| 660 | DRMLISTDEL(&bo_gem->head); |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 661 | alloc_from_cache = true; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 662 | } else { |
| 663 | /* For non-render-target BOs (where we're probably |
| 664 | * going to map it first thing in order to fill it |
| 665 | * with data), check if the last BO in the cache is |
| 666 | * unbusy, and only reuse in that case. Otherwise, |
| 667 | * allocating a new buffer is probably faster than |
| 668 | * waiting for the GPU to finish. |
| 669 | */ |
| 670 | bo_gem = DRMLISTENTRY(drm_intel_bo_gem, |
| 671 | bucket->head.next, head); |
| 672 | if (!drm_intel_gem_bo_busy(&bo_gem->bo)) { |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 673 | alloc_from_cache = true; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 674 | DRMLISTDEL(&bo_gem->head); |
| 675 | } |
| 676 | } |
| 677 | |
| 678 | if (alloc_from_cache) { |
Chris Wilson | 83a35b6 | 2009-11-11 13:04:38 +0000 | [diff] [blame] | 679 | if (!drm_intel_gem_bo_madvise_internal |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 680 | (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) { |
| 681 | drm_intel_gem_bo_free(&bo_gem->bo); |
| 682 | drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem, |
| 683 | bucket); |
| 684 | goto retry; |
| 685 | } |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 686 | |
| 687 | if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo, |
| 688 | tiling_mode, |
| 689 | stride)) { |
| 690 | drm_intel_gem_bo_free(&bo_gem->bo); |
| 691 | goto retry; |
| 692 | } |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 693 | } |
Chris Wilson | 0fb215a | 2009-10-02 04:31:34 +0100 | [diff] [blame] | 694 | } |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 695 | pthread_mutex_unlock(&bufmgr_gem->lock); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 696 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 697 | if (!alloc_from_cache) { |
| 698 | struct drm_i915_gem_create create; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 699 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 700 | bo_gem = calloc(1, sizeof(*bo_gem)); |
| 701 | if (!bo_gem) |
| 702 | return NULL; |
Keith Packard | a919ff5 | 2008-06-05 15:58:09 -0700 | [diff] [blame] | 703 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 704 | bo_gem->bo.size = bo_size; |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 705 | |
| 706 | VG_CLEAR(create); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 707 | create.size = bo_size; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 708 | |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 709 | ret = drmIoctl(bufmgr_gem->fd, |
| 710 | DRM_IOCTL_I915_GEM_CREATE, |
| 711 | &create); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 712 | bo_gem->gem_handle = create.handle; |
| 713 | bo_gem->bo.handle = bo_gem->gem_handle; |
| 714 | if (ret != 0) { |
| 715 | free(bo_gem); |
| 716 | return NULL; |
| 717 | } |
| 718 | bo_gem->bo.bufmgr = bufmgr; |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 719 | |
| 720 | bo_gem->tiling_mode = I915_TILING_NONE; |
| 721 | bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
| 722 | bo_gem->stride = 0; |
| 723 | |
| 724 | if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo, |
| 725 | tiling_mode, |
| 726 | stride)) { |
| 727 | drm_intel_gem_bo_free(&bo_gem->bo); |
| 728 | return NULL; |
| 729 | } |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 730 | |
| 731 | DRMINITLISTHEAD(&bo_gem->name_list); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 732 | DRMINITLISTHEAD(&bo_gem->vma_list); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 733 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 734 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 735 | bo_gem->name = name; |
| 736 | atomic_set(&bo_gem->refcount, 1); |
| 737 | bo_gem->validate_index = -1; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 738 | bo_gem->reloc_tree_fences = 0; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 739 | bo_gem->used_as_reloc_target = false; |
| 740 | bo_gem->has_error = false; |
| 741 | bo_gem->reusable = true; |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 742 | bo_gem->aub_annotations = NULL; |
| 743 | bo_gem->aub_annotation_count = 0; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 744 | |
Chris Wilson | e22fb79 | 2009-11-30 22:14:30 +0000 | [diff] [blame] | 745 | drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); |
| 746 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 747 | DBG("bo_create: buf %d (%s) %ldb\n", |
| 748 | bo_gem->gem_handle, bo_gem->name, size); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 749 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 750 | return &bo_gem->bo; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 751 | } |
| 752 | |
Eric Anholt | 72abe98 | 2009-02-18 13:06:35 -0800 | [diff] [blame] | 753 | static drm_intel_bo * |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 754 | drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, |
| 755 | const char *name, |
| 756 | unsigned long size, |
| 757 | unsigned int alignment) |
Eric Anholt | 72abe98 | 2009-02-18 13:06:35 -0800 | [diff] [blame] | 758 | { |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 759 | return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 760 | BO_ALLOC_FOR_RENDER, |
| 761 | I915_TILING_NONE, 0); |
Eric Anholt | 72abe98 | 2009-02-18 13:06:35 -0800 | [diff] [blame] | 762 | } |
| 763 | |
| 764 | static drm_intel_bo * |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 765 | drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, |
| 766 | const char *name, |
| 767 | unsigned long size, |
| 768 | unsigned int alignment) |
Eric Anholt | 72abe98 | 2009-02-18 13:06:35 -0800 | [diff] [blame] | 769 | { |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 770 | return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0, |
| 771 | I915_TILING_NONE, 0); |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | static drm_intel_bo * |
| 775 | drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, |
| 776 | int x, int y, int cpp, uint32_t *tiling_mode, |
| 777 | unsigned long *pitch, unsigned long flags) |
| 778 | { |
| 779 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; |
Chris Wilson | e65caeb | 2010-06-09 10:08:41 +0100 | [diff] [blame] | 780 | unsigned long size, stride; |
| 781 | uint32_t tiling; |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 782 | |
Chris Wilson | e65caeb | 2010-06-09 10:08:41 +0100 | [diff] [blame] | 783 | do { |
Daniel Vetter | 9a71ed9 | 2011-02-22 18:53:56 +0100 | [diff] [blame] | 784 | unsigned long aligned_y, height_alignment; |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 785 | |
Chris Wilson | e65caeb | 2010-06-09 10:08:41 +0100 | [diff] [blame] | 786 | tiling = *tiling_mode; |
| 787 | |
| 788 | /* If we're tiled, our allocations are in 8 or 32-row blocks, |
| 789 | * so failure to align our height means that we won't allocate |
| 790 | * enough pages. |
| 791 | * |
| 792 | * If we're untiled, we still have to align to 2 rows high |
| 793 | * because the data port accesses 2x2 blocks even if the |
| 794 | * bottom row isn't to be rendered, so failure to align means |
| 795 | * we could walk off the end of the GTT and fault. This is |
| 796 | * documented on 965, and may be the case on older chipsets |
| 797 | * too so we try to be careful. |
| 798 | */ |
| 799 | aligned_y = y; |
Daniel Vetter | 9a71ed9 | 2011-02-22 18:53:56 +0100 | [diff] [blame] | 800 | height_alignment = 2; |
| 801 | |
Eric Anholt | 078bc5b | 2011-12-20 13:10:36 -0800 | [diff] [blame] | 802 | if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE) |
Daniel Vetter | 06ebbf7 | 2011-03-26 15:04:04 +0100 | [diff] [blame] | 803 | height_alignment = 16; |
Daniel Vetter | 194aa1b | 2011-09-22 22:20:53 +0200 | [diff] [blame] | 804 | else if (tiling == I915_TILING_X |
Eric Anholt | 078bc5b | 2011-12-20 13:10:36 -0800 | [diff] [blame] | 805 | || (IS_915(bufmgr_gem->pci_device) |
| 806 | && tiling == I915_TILING_Y)) |
Daniel Vetter | 9a71ed9 | 2011-02-22 18:53:56 +0100 | [diff] [blame] | 807 | height_alignment = 8; |
Chris Wilson | e65caeb | 2010-06-09 10:08:41 +0100 | [diff] [blame] | 808 | else if (tiling == I915_TILING_Y) |
Daniel Vetter | 9a71ed9 | 2011-02-22 18:53:56 +0100 | [diff] [blame] | 809 | height_alignment = 32; |
Daniel Vetter | 9a71ed9 | 2011-02-22 18:53:56 +0100 | [diff] [blame] | 810 | aligned_y = ALIGN(y, height_alignment); |
Chris Wilson | e65caeb | 2010-06-09 10:08:41 +0100 | [diff] [blame] | 811 | |
| 812 | stride = x * cpp; |
Chris Wilson | 726210f | 2010-06-24 11:38:00 +0100 | [diff] [blame] | 813 | stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode); |
Chris Wilson | e65caeb | 2010-06-09 10:08:41 +0100 | [diff] [blame] | 814 | size = stride * aligned_y; |
| 815 | size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode); |
| 816 | } while (*tiling_mode != tiling); |
Chris Wilson | 6ea2bda | 2010-06-22 13:03:52 +0100 | [diff] [blame] | 817 | *pitch = stride; |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 818 | |
Chris Wilson | 6ea2bda | 2010-06-22 13:03:52 +0100 | [diff] [blame] | 819 | if (tiling == I915_TILING_NONE) |
Chris Wilson | 5eec286 | 2010-06-21 14:20:56 +0100 | [diff] [blame] | 820 | stride = 0; |
| 821 | |
Chris Wilson | 6ea2bda | 2010-06-22 13:03:52 +0100 | [diff] [blame] | 822 | return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags, |
| 823 | tiling, stride); |
Eric Anholt | 72abe98 | 2009-02-18 13:06:35 -0800 | [diff] [blame] | 824 | } |
| 825 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 826 | /** |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 827 | * Returns a drm_intel_bo wrapping the given buffer object handle. |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 828 | * |
| 829 | * This can be used when one application needs to pass a buffer object |
| 830 | * to another. |
| 831 | */ |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 832 | drm_intel_bo * |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 833 | drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, |
| 834 | const char *name, |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 835 | unsigned int handle) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 836 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 837 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; |
| 838 | drm_intel_bo_gem *bo_gem; |
| 839 | int ret; |
| 840 | struct drm_gem_open open_arg; |
| 841 | struct drm_i915_gem_get_tiling get_tiling; |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 842 | drmMMListHead *list; |
| 843 | |
| 844 | /* At the moment most applications only have a few named bo. |
| 845 | * For instance, in a DRI client only the render buffers passed |
| 846 | * between X and the client are named. And since X returns the |
| 847 | * alternating names for the front/back buffer a linear search |
| 848 | * provides a sufficiently fast match. |
| 849 | */ |
| 850 | for (list = bufmgr_gem->named.next; |
| 851 | list != &bufmgr_gem->named; |
| 852 | list = list->next) { |
| 853 | bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list); |
| 854 | if (bo_gem->global_name == handle) { |
| 855 | drm_intel_gem_bo_reference(&bo_gem->bo); |
| 856 | return &bo_gem->bo; |
| 857 | } |
| 858 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 859 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 860 | bo_gem = calloc(1, sizeof(*bo_gem)); |
| 861 | if (!bo_gem) |
| 862 | return NULL; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 863 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 864 | VG_CLEAR(open_arg); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 865 | open_arg.name = handle; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 866 | ret = drmIoctl(bufmgr_gem->fd, |
| 867 | DRM_IOCTL_GEM_OPEN, |
| 868 | &open_arg); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 869 | if (ret != 0) { |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 870 | DBG("Couldn't reference %s handle 0x%08x: %s\n", |
| 871 | name, handle, strerror(errno)); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 872 | free(bo_gem); |
| 873 | return NULL; |
| 874 | } |
| 875 | bo_gem->bo.size = open_arg.size; |
| 876 | bo_gem->bo.offset = 0; |
| 877 | bo_gem->bo.virtual = NULL; |
| 878 | bo_gem->bo.bufmgr = bufmgr; |
| 879 | bo_gem->name = name; |
| 880 | atomic_set(&bo_gem->refcount, 1); |
| 881 | bo_gem->validate_index = -1; |
| 882 | bo_gem->gem_handle = open_arg.handle; |
Chris Wilson | 53581b6 | 2011-02-14 09:27:05 +0000 | [diff] [blame] | 883 | bo_gem->bo.handle = open_arg.handle; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 884 | bo_gem->global_name = handle; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 885 | bo_gem->reusable = false; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 886 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 887 | VG_CLEAR(get_tiling); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 888 | get_tiling.handle = bo_gem->gem_handle; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 889 | ret = drmIoctl(bufmgr_gem->fd, |
| 890 | DRM_IOCTL_I915_GEM_GET_TILING, |
| 891 | &get_tiling); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 892 | if (ret != 0) { |
| 893 | drm_intel_gem_bo_unreference(&bo_gem->bo); |
| 894 | return NULL; |
| 895 | } |
| 896 | bo_gem->tiling_mode = get_tiling.tiling_mode; |
| 897 | bo_gem->swizzle_mode = get_tiling.swizzle_mode; |
Chris Wilson | 056aa9b | 2010-06-21 14:31:29 +0100 | [diff] [blame] | 898 | /* XXX stride is unknown */ |
Chris Wilson | e22fb79 | 2009-11-30 22:14:30 +0000 | [diff] [blame] | 899 | drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); |
Keith Packard | 18f091d | 2008-12-15 15:08:12 -0800 | [diff] [blame] | 900 | |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 901 | DRMINITLISTHEAD(&bo_gem->vma_list); |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 902 | DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 903 | DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 904 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 905 | return &bo_gem->bo; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 906 | } |
| 907 | |
| 908 | static void |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 909 | drm_intel_gem_bo_free(drm_intel_bo *bo) |
Eric Anholt | 500c81d | 2008-06-06 17:13:16 -0700 | [diff] [blame] | 910 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 911 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 912 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 913 | struct drm_gem_close close; |
| 914 | int ret; |
Eric Anholt | 500c81d | 2008-06-06 17:13:16 -0700 | [diff] [blame] | 915 | |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 916 | DRMLISTDEL(&bo_gem->vma_list); |
| 917 | if (bo_gem->mem_virtual) { |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 918 | VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0)); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 919 | munmap(bo_gem->mem_virtual, bo_gem->bo.size); |
| 920 | bufmgr_gem->vma_count--; |
| 921 | } |
| 922 | if (bo_gem->gtt_virtual) { |
| 923 | munmap(bo_gem->gtt_virtual, bo_gem->bo.size); |
| 924 | bufmgr_gem->vma_count--; |
| 925 | } |
| 926 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 927 | /* Close this object */ |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 928 | VG_CLEAR(close); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 929 | close.handle = bo_gem->gem_handle; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 930 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 931 | if (ret != 0) { |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 932 | DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n", |
| 933 | bo_gem->gem_handle, bo_gem->name, strerror(errno)); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 934 | } |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 935 | free(bo_gem->aub_annotations); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 936 | free(bo); |
Eric Anholt | 500c81d | 2008-06-06 17:13:16 -0700 | [diff] [blame] | 937 | } |
| 938 | |
Chris Wilson | 23eeb7e | 2012-02-09 10:29:22 +0000 | [diff] [blame] | 939 | static void |
| 940 | drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo) |
| 941 | { |
| 942 | #if HAVE_VALGRIND |
| 943 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 944 | |
| 945 | if (bo_gem->mem_virtual) |
| 946 | VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size); |
| 947 | |
| 948 | if (bo_gem->gtt_virtual) |
| 949 | VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size); |
| 950 | #endif |
| 951 | } |
| 952 | |
Eric Anholt | 3f3c5be | 2009-07-09 17:49:46 -0700 | [diff] [blame] | 953 | /** Frees all cached buffers significantly older than @time. */ |
| 954 | static void |
| 955 | drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time) |
| 956 | { |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 957 | int i; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 958 | |
Chris Wilson | f16b416 | 2010-06-21 15:21:48 +0100 | [diff] [blame] | 959 | if (bufmgr_gem->time == time) |
| 960 | return; |
| 961 | |
Eric Anholt | 0ec768e | 2010-06-04 17:09:11 -0700 | [diff] [blame] | 962 | for (i = 0; i < bufmgr_gem->num_buckets; i++) { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 963 | struct drm_intel_gem_bo_bucket *bucket = |
| 964 | &bufmgr_gem->cache_bucket[i]; |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 965 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 966 | while (!DRMLISTEMPTY(&bucket->head)) { |
| 967 | drm_intel_bo_gem *bo_gem; |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 968 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 969 | bo_gem = DRMLISTENTRY(drm_intel_bo_gem, |
| 970 | bucket->head.next, head); |
| 971 | if (time - bo_gem->free_time <= 1) |
| 972 | break; |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 973 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 974 | DRMLISTDEL(&bo_gem->head); |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 975 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 976 | drm_intel_gem_bo_free(&bo_gem->bo); |
| 977 | } |
| 978 | } |
Chris Wilson | f16b416 | 2010-06-21 15:21:48 +0100 | [diff] [blame] | 979 | |
| 980 | bufmgr_gem->time = time; |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 981 | } |
| 982 | |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 983 | static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem) |
| 984 | { |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 985 | int limit; |
| 986 | |
| 987 | DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__, |
| 988 | bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 989 | |
| 990 | if (bufmgr_gem->vma_max < 0) |
| 991 | return; |
| 992 | |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 993 | /* We may need to evict a few entries in order to create new mmaps */ |
| 994 | limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open; |
| 995 | if (limit < 0) |
| 996 | limit = 0; |
| 997 | |
| 998 | while (bufmgr_gem->vma_count > limit) { |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 999 | drm_intel_bo_gem *bo_gem; |
| 1000 | |
| 1001 | bo_gem = DRMLISTENTRY(drm_intel_bo_gem, |
| 1002 | bufmgr_gem->vma_cache.next, |
| 1003 | vma_list); |
| 1004 | assert(bo_gem->map_count == 0); |
Chris Wilson | 0ab2251 | 2011-12-14 08:20:10 +0000 | [diff] [blame] | 1005 | DRMLISTDELINIT(&bo_gem->vma_list); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1006 | |
| 1007 | if (bo_gem->mem_virtual) { |
| 1008 | munmap(bo_gem->mem_virtual, bo_gem->bo.size); |
| 1009 | bo_gem->mem_virtual = NULL; |
| 1010 | bufmgr_gem->vma_count--; |
| 1011 | } |
| 1012 | if (bo_gem->gtt_virtual) { |
| 1013 | munmap(bo_gem->gtt_virtual, bo_gem->bo.size); |
| 1014 | bo_gem->gtt_virtual = NULL; |
| 1015 | bufmgr_gem->vma_count--; |
| 1016 | } |
| 1017 | } |
| 1018 | } |
| 1019 | |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1020 | static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem, |
| 1021 | drm_intel_bo_gem *bo_gem) |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1022 | { |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1023 | bufmgr_gem->vma_open--; |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1024 | DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache); |
| 1025 | if (bo_gem->mem_virtual) |
| 1026 | bufmgr_gem->vma_count++; |
| 1027 | if (bo_gem->gtt_virtual) |
| 1028 | bufmgr_gem->vma_count++; |
| 1029 | drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); |
| 1030 | } |
| 1031 | |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1032 | static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem, |
| 1033 | drm_intel_bo_gem *bo_gem) |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1034 | { |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1035 | bufmgr_gem->vma_open++; |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1036 | DRMLISTDEL(&bo_gem->vma_list); |
| 1037 | if (bo_gem->mem_virtual) |
| 1038 | bufmgr_gem->vma_count--; |
| 1039 | if (bo_gem->gtt_virtual) |
| 1040 | bufmgr_gem->vma_count--; |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1041 | drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1042 | } |
| 1043 | |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 1044 | static void |
| 1045 | drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 1046 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1047 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1048 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1049 | struct drm_intel_gem_bo_bucket *bucket; |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 1050 | int i; |
Chris Wilson | 04495ee | 2009-10-02 04:39:22 +0100 | [diff] [blame] | 1051 | |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 1052 | /* Unreference all the target buffers */ |
| 1053 | for (i = 0; i < bo_gem->reloc_count; i++) { |
Eric Anholt | 4f7704a | 2010-06-10 08:58:08 -0700 | [diff] [blame] | 1054 | if (bo_gem->reloc_target_info[i].bo != bo) { |
| 1055 | drm_intel_gem_bo_unreference_locked_timed(bo_gem-> |
| 1056 | reloc_target_info[i].bo, |
| 1057 | time); |
| 1058 | } |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1059 | } |
Chris Wilson | b666f41 | 2009-11-30 23:07:19 +0000 | [diff] [blame] | 1060 | bo_gem->reloc_count = 0; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 1061 | bo_gem->used_as_reloc_target = false; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1062 | |
| 1063 | DBG("bo_unreference final: %d (%s)\n", |
| 1064 | bo_gem->gem_handle, bo_gem->name); |
| 1065 | |
Chris Wilson | 57473c7 | 2009-12-02 13:36:22 +0000 | [diff] [blame] | 1066 | /* release memory associated with this object */ |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1067 | if (bo_gem->reloc_target_info) { |
| 1068 | free(bo_gem->reloc_target_info); |
| 1069 | bo_gem->reloc_target_info = NULL; |
Chris Wilson | 57473c7 | 2009-12-02 13:36:22 +0000 | [diff] [blame] | 1070 | } |
| 1071 | if (bo_gem->relocs) { |
| 1072 | free(bo_gem->relocs); |
| 1073 | bo_gem->relocs = NULL; |
| 1074 | } |
| 1075 | |
Chris Wilson | 5c5332b | 2011-12-05 10:39:49 +0000 | [diff] [blame] | 1076 | /* Clear any left-over mappings */ |
| 1077 | if (bo_gem->map_count) { |
| 1078 | DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count); |
| 1079 | bo_gem->map_count = 0; |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1080 | drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); |
Chris Wilson | 23eeb7e | 2012-02-09 10:29:22 +0000 | [diff] [blame] | 1081 | drm_intel_gem_bo_mark_mmaps_incoherent(bo); |
Chris Wilson | 5c5332b | 2011-12-05 10:39:49 +0000 | [diff] [blame] | 1082 | } |
Chris Wilson | 5c5332b | 2011-12-05 10:39:49 +0000 | [diff] [blame] | 1083 | |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 1084 | DRMLISTDEL(&bo_gem->name_list); |
| 1085 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1086 | bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size); |
| 1087 | /* Put the buffer into our internal cache for reuse if we can. */ |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1088 | if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL && |
Chris Wilson | 60aa803 | 2009-11-30 20:02:05 +0000 | [diff] [blame] | 1089 | drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem, |
| 1090 | I915_MADV_DONTNEED)) { |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 1091 | bo_gem->free_time = time; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1092 | |
| 1093 | bo_gem->name = NULL; |
| 1094 | bo_gem->validate_index = -1; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1095 | |
| 1096 | DRMLISTADDTAIL(&bo_gem->head, &bucket->head); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1097 | } else { |
| 1098 | drm_intel_gem_bo_free(bo); |
| 1099 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1100 | } |
| 1101 | |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 1102 | static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo, |
| 1103 | time_t time) |
| 1104 | { |
| 1105 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1106 | |
| 1107 | assert(atomic_read(&bo_gem->refcount) > 0); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1108 | if (atomic_dec_and_test(&bo_gem->refcount)) |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 1109 | drm_intel_gem_bo_unreference_final(bo, time); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1110 | } |
| 1111 | |
| 1112 | static void drm_intel_gem_bo_unreference(drm_intel_bo *bo) |
| 1113 | { |
| 1114 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1115 | |
| 1116 | assert(atomic_read(&bo_gem->refcount) > 0); |
| 1117 | if (atomic_dec_and_test(&bo_gem->refcount)) { |
| 1118 | drm_intel_bufmgr_gem *bufmgr_gem = |
| 1119 | (drm_intel_bufmgr_gem *) bo->bufmgr; |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 1120 | struct timespec time; |
| 1121 | |
| 1122 | clock_gettime(CLOCK_MONOTONIC, &time); |
| 1123 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1124 | pthread_mutex_lock(&bufmgr_gem->lock); |
Eric Anholt | 0d7ad7e | 2009-10-20 14:19:38 -0700 | [diff] [blame] | 1125 | drm_intel_gem_bo_unreference_final(bo, time.tv_sec); |
Chris Wilson | f16b416 | 2010-06-21 15:21:48 +0100 | [diff] [blame] | 1126 | drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1127 | pthread_mutex_unlock(&bufmgr_gem->lock); |
| 1128 | } |
| 1129 | } |
| 1130 | |
| 1131 | static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) |
| 1132 | { |
| 1133 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1134 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1135 | struct drm_i915_gem_set_domain set_domain; |
| 1136 | int ret; |
| 1137 | |
Chris Wilson | a3305b0 | 2010-05-13 08:24:28 +0100 | [diff] [blame] | 1138 | pthread_mutex_lock(&bufmgr_gem->lock); |
| 1139 | |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1140 | if (bo_gem->map_count++ == 0) |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1141 | drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1142 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1143 | if (!bo_gem->mem_virtual) { |
| 1144 | struct drm_i915_gem_mmap mmap_arg; |
Carl Worth | afd245d | 2009-04-29 14:43:55 -0700 | [diff] [blame] | 1145 | |
Chris Wilson | 015286f | 2011-12-11 17:35:06 +0000 | [diff] [blame] | 1146 | DBG("bo_map: %d (%s), map_count=%d\n", |
| 1147 | bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1148 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1149 | VG_CLEAR(mmap_arg); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1150 | mmap_arg.handle = bo_gem->gem_handle; |
| 1151 | mmap_arg.offset = 0; |
| 1152 | mmap_arg.size = bo->size; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 1153 | ret = drmIoctl(bufmgr_gem->fd, |
| 1154 | DRM_IOCTL_I915_GEM_MMAP, |
| 1155 | &mmap_arg); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1156 | if (ret != 0) { |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 1157 | ret = -errno; |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 1158 | DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", |
| 1159 | __FILE__, __LINE__, bo_gem->gem_handle, |
| 1160 | bo_gem->name, strerror(errno)); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1161 | if (--bo_gem->map_count == 0) |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1162 | drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); |
Chris Wilson | a3305b0 | 2010-05-13 08:24:28 +0100 | [diff] [blame] | 1163 | pthread_mutex_unlock(&bufmgr_gem->lock); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1164 | return ret; |
| 1165 | } |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1166 | VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1)); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1167 | bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr; |
| 1168 | } |
| 1169 | DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, |
| 1170 | bo_gem->mem_virtual); |
| 1171 | bo->virtual = bo_gem->mem_virtual; |
| 1172 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1173 | VG_CLEAR(set_domain); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1174 | set_domain.handle = bo_gem->gem_handle; |
| 1175 | set_domain.read_domains = I915_GEM_DOMAIN_CPU; |
| 1176 | if (write_enable) |
| 1177 | set_domain.write_domain = I915_GEM_DOMAIN_CPU; |
| 1178 | else |
| 1179 | set_domain.write_domain = 0; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 1180 | ret = drmIoctl(bufmgr_gem->fd, |
| 1181 | DRM_IOCTL_I915_GEM_SET_DOMAIN, |
| 1182 | &set_domain); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1183 | if (ret != 0) { |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 1184 | DBG("%s:%d: Error setting to CPU domain %d: %s\n", |
| 1185 | __FILE__, __LINE__, bo_gem->gem_handle, |
| 1186 | strerror(errno)); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1187 | } |
| 1188 | |
Eric Anholt | 4cb01ee | 2011-10-28 13:12:16 -0700 | [diff] [blame] | 1189 | if (write_enable) |
| 1190 | bo_gem->mapped_cpu_write = true; |
| 1191 | |
Chris Wilson | 23eeb7e | 2012-02-09 10:29:22 +0000 | [diff] [blame] | 1192 | drm_intel_gem_bo_mark_mmaps_incoherent(bo); |
| 1193 | VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size)); |
Chris Wilson | a3305b0 | 2010-05-13 08:24:28 +0100 | [diff] [blame] | 1194 | pthread_mutex_unlock(&bufmgr_gem->lock); |
| 1195 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1196 | return 0; |
| 1197 | } |
| 1198 | |
Eric Anholt | 99c7337 | 2012-02-10 04:12:15 -0800 | [diff] [blame] | 1199 | static int |
| 1200 | map_gtt(drm_intel_bo *bo) |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1201 | { |
| 1202 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1203 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1204 | int ret; |
| 1205 | |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1206 | if (bo_gem->map_count++ == 0) |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1207 | drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1208 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1209 | /* Get a mapping of the buffer if we haven't before. */ |
| 1210 | if (bo_gem->gtt_virtual == NULL) { |
| 1211 | struct drm_i915_gem_mmap_gtt mmap_arg; |
| 1212 | |
Chris Wilson | 015286f | 2011-12-11 17:35:06 +0000 | [diff] [blame] | 1213 | DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n", |
| 1214 | bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1215 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1216 | VG_CLEAR(mmap_arg); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1217 | mmap_arg.handle = bo_gem->gem_handle; |
| 1218 | |
| 1219 | /* Get the fake offset back... */ |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 1220 | ret = drmIoctl(bufmgr_gem->fd, |
| 1221 | DRM_IOCTL_I915_GEM_MMAP_GTT, |
| 1222 | &mmap_arg); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1223 | if (ret != 0) { |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 1224 | ret = -errno; |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 1225 | DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n", |
| 1226 | __FILE__, __LINE__, |
| 1227 | bo_gem->gem_handle, bo_gem->name, |
| 1228 | strerror(errno)); |
Chris Wilson | c5f0ed1 | 2011-12-13 10:30:54 +0000 | [diff] [blame] | 1229 | if (--bo_gem->map_count == 0) |
| 1230 | drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1231 | return ret; |
| 1232 | } |
| 1233 | |
| 1234 | /* and mmap it */ |
| 1235 | bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE, |
| 1236 | MAP_SHARED, bufmgr_gem->fd, |
| 1237 | mmap_arg.offset); |
| 1238 | if (bo_gem->gtt_virtual == MAP_FAILED) { |
Chris Wilson | 08371bc | 2009-12-08 22:35:24 +0000 | [diff] [blame] | 1239 | bo_gem->gtt_virtual = NULL; |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 1240 | ret = -errno; |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 1241 | DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", |
| 1242 | __FILE__, __LINE__, |
| 1243 | bo_gem->gem_handle, bo_gem->name, |
| 1244 | strerror(errno)); |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1245 | if (--bo_gem->map_count == 0) |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1246 | drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 1247 | return ret; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1248 | } |
| 1249 | } |
| 1250 | |
| 1251 | bo->virtual = bo_gem->gtt_virtual; |
| 1252 | |
| 1253 | DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, |
| 1254 | bo_gem->gtt_virtual); |
| 1255 | |
Eric Anholt | 99c7337 | 2012-02-10 04:12:15 -0800 | [diff] [blame] | 1256 | return 0; |
| 1257 | } |
| 1258 | |
| 1259 | int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) |
| 1260 | { |
| 1261 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1262 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1263 | struct drm_i915_gem_set_domain set_domain; |
| 1264 | int ret; |
| 1265 | |
| 1266 | pthread_mutex_lock(&bufmgr_gem->lock); |
| 1267 | |
| 1268 | ret = map_gtt(bo); |
| 1269 | if (ret) { |
| 1270 | pthread_mutex_unlock(&bufmgr_gem->lock); |
| 1271 | return ret; |
| 1272 | } |
| 1273 | |
| 1274 | /* Now move it to the GTT domain so that the GPU and CPU |
| 1275 | * caches are flushed and the GPU isn't actively using the |
| 1276 | * buffer. |
| 1277 | * |
| 1278 | * The pagefault handler does this domain change for us when |
| 1279 | * it has unbound the BO from the GTT, but it's up to us to |
| 1280 | * tell it when we're about to use things if we had done |
| 1281 | * rendering and it still happens to be bound to the GTT. |
| 1282 | */ |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1283 | VG_CLEAR(set_domain); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1284 | set_domain.handle = bo_gem->gem_handle; |
| 1285 | set_domain.read_domains = I915_GEM_DOMAIN_GTT; |
| 1286 | set_domain.write_domain = I915_GEM_DOMAIN_GTT; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 1287 | ret = drmIoctl(bufmgr_gem->fd, |
| 1288 | DRM_IOCTL_I915_GEM_SET_DOMAIN, |
| 1289 | &set_domain); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1290 | if (ret != 0) { |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 1291 | DBG("%s:%d: Error setting domain %d: %s\n", |
| 1292 | __FILE__, __LINE__, bo_gem->gem_handle, |
| 1293 | strerror(errno)); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1294 | } |
| 1295 | |
Chris Wilson | 23eeb7e | 2012-02-09 10:29:22 +0000 | [diff] [blame] | 1296 | drm_intel_gem_bo_mark_mmaps_incoherent(bo); |
| 1297 | VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size)); |
Chris Wilson | a3305b0 | 2010-05-13 08:24:28 +0100 | [diff] [blame] | 1298 | pthread_mutex_unlock(&bufmgr_gem->lock); |
| 1299 | |
Chris Wilson | c3ddfea | 2010-06-29 20:12:44 +0100 | [diff] [blame] | 1300 | return 0; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1301 | } |
| 1302 | |
Eric Anholt | 99c7337 | 2012-02-10 04:12:15 -0800 | [diff] [blame] | 1303 | /** |
| 1304 | * Performs a mapping of the buffer object like the normal GTT |
| 1305 | * mapping, but avoids waiting for the GPU to be done reading from or |
| 1306 | * rendering to the buffer. |
| 1307 | * |
| 1308 | * This is used in the implementation of GL_ARB_map_buffer_range: The |
| 1309 | * user asks to create a buffer, then does a mapping, fills some |
| 1310 | * space, runs a drawing command, then asks to map it again without |
| 1311 | * synchronizing because it guarantees that it won't write over the |
| 1312 | * data that the GPU is busy using (or, more specifically, that if it |
| 1313 | * does write over the data, it acknowledges that rendering is |
| 1314 | * undefined). |
| 1315 | */ |
| 1316 | |
| 1317 | int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo) |
| 1318 | { |
| 1319 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1320 | int ret; |
| 1321 | |
| 1322 | /* If the CPU cache isn't coherent with the GTT, then use a |
| 1323 | * regular synchronized mapping. The problem is that we don't |
| 1324 | * track where the buffer was last used on the CPU side in |
| 1325 | * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so |
| 1326 | * we would potentially corrupt the buffer even when the user |
| 1327 | * does reasonable things. |
| 1328 | */ |
| 1329 | if (!bufmgr_gem->has_llc) |
| 1330 | return drm_intel_gem_bo_map_gtt(bo); |
| 1331 | |
| 1332 | pthread_mutex_lock(&bufmgr_gem->lock); |
| 1333 | ret = map_gtt(bo); |
| 1334 | pthread_mutex_unlock(&bufmgr_gem->lock); |
| 1335 | |
| 1336 | return ret; |
| 1337 | } |
| 1338 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1339 | static int drm_intel_gem_bo_unmap(drm_intel_bo *bo) |
| 1340 | { |
| 1341 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1342 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Eric Anholt | 4cb01ee | 2011-10-28 13:12:16 -0700 | [diff] [blame] | 1343 | int ret = 0; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1344 | |
| 1345 | if (bo == NULL) |
| 1346 | return 0; |
| 1347 | |
Chris Wilson | a3305b0 | 2010-05-13 08:24:28 +0100 | [diff] [blame] | 1348 | pthread_mutex_lock(&bufmgr_gem->lock); |
| 1349 | |
Chris Wilson | 015286f | 2011-12-11 17:35:06 +0000 | [diff] [blame] | 1350 | if (bo_gem->map_count <= 0) { |
| 1351 | DBG("attempted to unmap an unmapped bo\n"); |
| 1352 | pthread_mutex_unlock(&bufmgr_gem->lock); |
| 1353 | /* Preserve the old behaviour of just treating this as a |
| 1354 | * no-op rather than reporting the error. |
| 1355 | */ |
| 1356 | return 0; |
| 1357 | } |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 1358 | |
Eric Anholt | 4cb01ee | 2011-10-28 13:12:16 -0700 | [diff] [blame] | 1359 | if (bo_gem->mapped_cpu_write) { |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1360 | struct drm_i915_gem_sw_finish sw_finish; |
| 1361 | |
Eric Anholt | 4cb01ee | 2011-10-28 13:12:16 -0700 | [diff] [blame] | 1362 | /* Cause a flush to happen if the buffer's pinned for |
| 1363 | * scanout, so the results show up in a timely manner. |
| 1364 | * Unlike GTT set domains, this only does work if the |
| 1365 | * buffer should be scanout-related. |
| 1366 | */ |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1367 | VG_CLEAR(sw_finish); |
Eric Anholt | 4cb01ee | 2011-10-28 13:12:16 -0700 | [diff] [blame] | 1368 | sw_finish.handle = bo_gem->gem_handle; |
| 1369 | ret = drmIoctl(bufmgr_gem->fd, |
| 1370 | DRM_IOCTL_I915_GEM_SW_FINISH, |
| 1371 | &sw_finish); |
| 1372 | ret = ret == -1 ? -errno : 0; |
| 1373 | |
| 1374 | bo_gem->mapped_cpu_write = false; |
| 1375 | } |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1376 | |
Chris Wilson | c549a77 | 2011-12-05 10:14:34 +0000 | [diff] [blame] | 1377 | /* We need to unmap after every innovation as we cannot track |
| 1378 | * an open vma for every bo as that will exhaasut the system |
| 1379 | * limits and cause later failures. |
| 1380 | */ |
| 1381 | if (--bo_gem->map_count == 0) { |
Chris Wilson | dd9a5b4 | 2011-12-06 13:12:37 +0000 | [diff] [blame] | 1382 | drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); |
Chris Wilson | 23eeb7e | 2012-02-09 10:29:22 +0000 | [diff] [blame] | 1383 | drm_intel_gem_bo_mark_mmaps_incoherent(bo); |
Chris Wilson | c549a77 | 2011-12-05 10:14:34 +0000 | [diff] [blame] | 1384 | bo->virtual = NULL; |
| 1385 | } |
Chris Wilson | a3305b0 | 2010-05-13 08:24:28 +0100 | [diff] [blame] | 1386 | pthread_mutex_unlock(&bufmgr_gem->lock); |
Chris Wilson | 3e21e3b | 2010-03-04 21:17:48 +0000 | [diff] [blame] | 1387 | |
| 1388 | return ret; |
Carl Worth | afd245d | 2009-04-29 14:43:55 -0700 | [diff] [blame] | 1389 | } |
| 1390 | |
Eric Anholt | d0ae683 | 2011-10-28 13:13:08 -0700 | [diff] [blame] | 1391 | int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo) |
| 1392 | { |
| 1393 | return drm_intel_gem_bo_unmap(bo); |
| 1394 | } |
| 1395 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1396 | static int |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1397 | drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset, |
| 1398 | unsigned long size, const void *data) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1399 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1400 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1401 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1402 | struct drm_i915_gem_pwrite pwrite; |
| 1403 | int ret; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1404 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1405 | VG_CLEAR(pwrite); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1406 | pwrite.handle = bo_gem->gem_handle; |
| 1407 | pwrite.offset = offset; |
| 1408 | pwrite.size = size; |
| 1409 | pwrite.data_ptr = (uint64_t) (uintptr_t) data; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 1410 | ret = drmIoctl(bufmgr_gem->fd, |
| 1411 | DRM_IOCTL_I915_GEM_PWRITE, |
| 1412 | &pwrite); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1413 | if (ret != 0) { |
Chris Wilson | 3e21e3b | 2010-03-04 21:17:48 +0000 | [diff] [blame] | 1414 | ret = -errno; |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 1415 | DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n", |
| 1416 | __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, |
| 1417 | (int)size, strerror(errno)); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1418 | } |
Chris Wilson | 3e21e3b | 2010-03-04 21:17:48 +0000 | [diff] [blame] | 1419 | |
| 1420 | return ret; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1421 | } |
| 1422 | |
| 1423 | static int |
| 1424 | drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id) |
| 1425 | { |
| 1426 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; |
| 1427 | struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id; |
| 1428 | int ret; |
| 1429 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1430 | VG_CLEAR(get_pipe_from_crtc_id); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1431 | get_pipe_from_crtc_id.crtc_id = crtc_id; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 1432 | ret = drmIoctl(bufmgr_gem->fd, |
| 1433 | DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID, |
| 1434 | &get_pipe_from_crtc_id); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1435 | if (ret != 0) { |
| 1436 | /* We return -1 here to signal that we don't |
| 1437 | * know which pipe is associated with this crtc. |
| 1438 | * This lets the caller know that this information |
| 1439 | * isn't available; using the wrong pipe for |
| 1440 | * vblank waiting can cause the chipset to lock up |
| 1441 | */ |
| 1442 | return -1; |
| 1443 | } |
| 1444 | |
| 1445 | return get_pipe_from_crtc_id.pipe; |
| 1446 | } |
| 1447 | |
| 1448 | static int |
| 1449 | drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, |
| 1450 | unsigned long size, void *data) |
| 1451 | { |
| 1452 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1453 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1454 | struct drm_i915_gem_pread pread; |
| 1455 | int ret; |
| 1456 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1457 | VG_CLEAR(pread); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1458 | pread.handle = bo_gem->gem_handle; |
| 1459 | pread.offset = offset; |
| 1460 | pread.size = size; |
| 1461 | pread.data_ptr = (uint64_t) (uintptr_t) data; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 1462 | ret = drmIoctl(bufmgr_gem->fd, |
| 1463 | DRM_IOCTL_I915_GEM_PREAD, |
| 1464 | &pread); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1465 | if (ret != 0) { |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 1466 | ret = -errno; |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 1467 | DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n", |
| 1468 | __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, |
| 1469 | (int)size, strerror(errno)); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1470 | } |
Chris Wilson | 3e21e3b | 2010-03-04 21:17:48 +0000 | [diff] [blame] | 1471 | |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 1472 | return ret; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1473 | } |
| 1474 | |
Eric Anholt | 877b2ce | 2010-11-09 13:51:45 -0800 | [diff] [blame] | 1475 | /** Waits for all GPU rendering with the object to have completed. */ |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1476 | static void |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 1477 | drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1478 | { |
Eric Anholt | 877b2ce | 2010-11-09 13:51:45 -0800 | [diff] [blame] | 1479 | drm_intel_gem_bo_start_gtt_access(bo, 1); |
Eric Anholt | 6fb1ad7 | 2008-11-13 11:44:22 -0800 | [diff] [blame] | 1480 | } |
| 1481 | |
| 1482 | /** |
Ben Widawsky | 971c080 | 2012-06-05 11:30:48 -0700 | [diff] [blame] | 1483 | * Waits on a BO for the given amount of time. |
| 1484 | * |
| 1485 | * @bo: buffer object to wait for |
| 1486 | * @timeout_ns: amount of time to wait in nanoseconds. |
| 1487 | * If value is less than 0, an infinite wait will occur. |
| 1488 | * |
| 1489 | * Returns 0 if the wait was successful ie. the last batch referencing the |
| 1490 | * object has completed within the allotted time. Otherwise some negative return |
| 1491 | * value describes the error. Of particular interest is -ETIME when the wait has |
| 1492 | * failed to yield the desired result. |
| 1493 | * |
| 1494 | * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows |
| 1495 | * the operation to give up after a certain amount of time. Another subtle |
| 1496 | * difference is the internal locking semantics are different (this variant does |
| 1497 | * not hold the lock for the duration of the wait). This makes the wait subject |
| 1498 | * to a larger userspace race window. |
| 1499 | * |
| 1500 | * The implementation shall wait until the object is no longer actively |
| 1501 | * referenced within a batch buffer at the time of the call. The wait will |
| 1502 | * not guarantee that the buffer is re-issued via another thread, or an flinked |
| 1503 | * handle. Userspace must make sure this race does not occur if such precision |
| 1504 | * is important. |
| 1505 | */ |
| 1506 | int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns) |
| 1507 | { |
| 1508 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1509 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1510 | struct drm_i915_gem_wait wait; |
| 1511 | int ret; |
| 1512 | |
| 1513 | if (!bufmgr_gem->has_wait_timeout) { |
| 1514 | DBG("%s:%d: Timed wait is not supported. Falling back to " |
| 1515 | "infinite wait\n", __FILE__, __LINE__); |
| 1516 | if (timeout_ns) { |
| 1517 | drm_intel_gem_bo_wait_rendering(bo); |
| 1518 | return 0; |
| 1519 | } else { |
| 1520 | return drm_intel_gem_bo_busy(bo) ? -ETIME : 0; |
| 1521 | } |
| 1522 | } |
| 1523 | |
| 1524 | wait.bo_handle = bo_gem->gem_handle; |
| 1525 | wait.timeout_ns = timeout_ns; |
| 1526 | wait.flags = 0; |
| 1527 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait); |
| 1528 | if (ret == -1) |
| 1529 | return -errno; |
| 1530 | |
| 1531 | return ret; |
| 1532 | } |
| 1533 | |
| 1534 | /** |
Eric Anholt | 6fb1ad7 | 2008-11-13 11:44:22 -0800 | [diff] [blame] | 1535 | * Sets the object to the GTT read and possibly write domain, used by the X |
| 1536 | * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt(). |
| 1537 | * |
| 1538 | * In combination with drm_intel_gem_bo_pin() and manual fence management, we |
| 1539 | * can do tiled pixmaps this way. |
| 1540 | */ |
| 1541 | void |
| 1542 | drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable) |
| 1543 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1544 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1545 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1546 | struct drm_i915_gem_set_domain set_domain; |
| 1547 | int ret; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1548 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 1549 | VG_CLEAR(set_domain); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1550 | set_domain.handle = bo_gem->gem_handle; |
| 1551 | set_domain.read_domains = I915_GEM_DOMAIN_GTT; |
| 1552 | set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 1553 | ret = drmIoctl(bufmgr_gem->fd, |
| 1554 | DRM_IOCTL_I915_GEM_SET_DOMAIN, |
| 1555 | &set_domain); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1556 | if (ret != 0) { |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 1557 | DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n", |
| 1558 | __FILE__, __LINE__, bo_gem->gem_handle, |
| 1559 | set_domain.read_domains, set_domain.write_domain, |
| 1560 | strerror(errno)); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1561 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1562 | } |
| 1563 | |
| 1564 | static void |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 1565 | drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1566 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1567 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; |
| 1568 | int i; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1569 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1570 | free(bufmgr_gem->exec2_objects); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1571 | free(bufmgr_gem->exec_objects); |
| 1572 | free(bufmgr_gem->exec_bos); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1573 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1574 | pthread_mutex_destroy(&bufmgr_gem->lock); |
Eric Anholt | 6df7b07 | 2008-06-12 23:22:26 -0700 | [diff] [blame] | 1575 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1576 | /* Free any cached buffer objects we were going to reuse */ |
Eric Anholt | 0ec768e | 2010-06-04 17:09:11 -0700 | [diff] [blame] | 1577 | for (i = 0; i < bufmgr_gem->num_buckets; i++) { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1578 | struct drm_intel_gem_bo_bucket *bucket = |
| 1579 | &bufmgr_gem->cache_bucket[i]; |
| 1580 | drm_intel_bo_gem *bo_gem; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1581 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1582 | while (!DRMLISTEMPTY(&bucket->head)) { |
| 1583 | bo_gem = DRMLISTENTRY(drm_intel_bo_gem, |
| 1584 | bucket->head.next, head); |
| 1585 | DRMLISTDEL(&bo_gem->head); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1586 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1587 | drm_intel_gem_bo_free(&bo_gem->bo); |
| 1588 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1589 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1590 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1591 | free(bufmgr); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1592 | } |
| 1593 | |
| 1594 | /** |
| 1595 | * Adds the target buffer to the validation list and adds the relocation |
| 1596 | * to the reloc_buffer's relocation list. |
| 1597 | * |
| 1598 | * The relocation entry at the given offset must already contain the |
| 1599 | * precomputed relocation value, because the kernel will optimize out |
| 1600 | * the relocation entry write when the buffer hasn't moved from the |
| 1601 | * last known offset in target_bo. |
| 1602 | */ |
| 1603 | static int |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1604 | do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, |
| 1605 | drm_intel_bo *target_bo, uint32_t target_offset, |
| 1606 | uint32_t read_domains, uint32_t write_domain, |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 1607 | bool need_fence) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1608 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1609 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1610 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1611 | drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 1612 | bool fenced_command; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1613 | |
Chris Wilson | 9707733 | 2009-12-01 23:01:34 +0000 | [diff] [blame] | 1614 | if (bo_gem->has_error) |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 1615 | return -ENOMEM; |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 1616 | |
| 1617 | if (target_bo_gem->has_error) { |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 1618 | bo_gem->has_error = true; |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 1619 | return -ENOMEM; |
| 1620 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1621 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1622 | /* We never use HW fences for rendering on 965+ */ |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 1623 | if (bufmgr_gem->gen >= 4) |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 1624 | need_fence = false; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1625 | |
Chris Wilson | 537703f | 2010-12-07 20:34:22 +0000 | [diff] [blame] | 1626 | fenced_command = need_fence; |
| 1627 | if (target_bo_gem->tiling_mode == I915_TILING_NONE) |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 1628 | need_fence = false; |
Chris Wilson | 537703f | 2010-12-07 20:34:22 +0000 | [diff] [blame] | 1629 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1630 | /* Create a new relocation list if needed */ |
Chris Wilson | 9707733 | 2009-12-01 23:01:34 +0000 | [diff] [blame] | 1631 | if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo)) |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 1632 | return -ENOMEM; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1633 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1634 | /* Check overflow */ |
| 1635 | assert(bo_gem->reloc_count < bufmgr_gem->max_relocs); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1636 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1637 | /* Check args */ |
| 1638 | assert(offset <= bo->size - 4); |
| 1639 | assert((write_domain & (write_domain - 1)) == 0); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1640 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1641 | /* Make sure that we're not adding a reloc to something whose size has |
| 1642 | * already been accounted for. |
| 1643 | */ |
| 1644 | assert(!bo_gem->used_as_reloc_target); |
Eric Anholt | f179137 | 2010-06-07 14:22:36 -0700 | [diff] [blame] | 1645 | if (target_bo_gem != bo_gem) { |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 1646 | target_bo_gem->used_as_reloc_target = true; |
Eric Anholt | f179137 | 2010-06-07 14:22:36 -0700 | [diff] [blame] | 1647 | bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size; |
| 1648 | } |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 1649 | /* An object needing a fence is a tiled buffer, so it won't have |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1650 | * relocs to other buffers. |
| 1651 | */ |
| 1652 | if (need_fence) |
| 1653 | target_bo_gem->reloc_tree_fences = 1; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1654 | bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 1655 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1656 | bo_gem->relocs[bo_gem->reloc_count].offset = offset; |
| 1657 | bo_gem->relocs[bo_gem->reloc_count].delta = target_offset; |
| 1658 | bo_gem->relocs[bo_gem->reloc_count].target_handle = |
| 1659 | target_bo_gem->gem_handle; |
| 1660 | bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains; |
| 1661 | bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain; |
| 1662 | bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1663 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1664 | bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo; |
Eric Anholt | 4f7704a | 2010-06-10 08:58:08 -0700 | [diff] [blame] | 1665 | if (target_bo != bo) |
| 1666 | drm_intel_gem_bo_reference(target_bo); |
Chris Wilson | af3d282 | 2010-12-03 10:48:12 +0000 | [diff] [blame] | 1667 | if (fenced_command) |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1668 | bo_gem->reloc_target_info[bo_gem->reloc_count].flags = |
| 1669 | DRM_INTEL_RELOC_FENCE; |
| 1670 | else |
| 1671 | bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1672 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1673 | bo_gem->reloc_count++; |
Eric Anholt | 6df7b07 | 2008-06-12 23:22:26 -0700 | [diff] [blame] | 1674 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1675 | return 0; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1676 | } |
| 1677 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1678 | static int |
| 1679 | drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, |
| 1680 | drm_intel_bo *target_bo, uint32_t target_offset, |
| 1681 | uint32_t read_domains, uint32_t write_domain) |
| 1682 | { |
| 1683 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; |
| 1684 | |
| 1685 | return do_bo_emit_reloc(bo, offset, target_bo, target_offset, |
| 1686 | read_domains, write_domain, |
| 1687 | !bufmgr_gem->fenced_relocs); |
| 1688 | } |
| 1689 | |
| 1690 | static int |
| 1691 | drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, |
| 1692 | drm_intel_bo *target_bo, |
| 1693 | uint32_t target_offset, |
| 1694 | uint32_t read_domains, uint32_t write_domain) |
| 1695 | { |
| 1696 | return do_bo_emit_reloc(bo, offset, target_bo, target_offset, |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 1697 | read_domains, write_domain, true); |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1698 | } |
| 1699 | |
Eric Anholt | 515cea6 | 2011-10-21 18:48:20 -0700 | [diff] [blame] | 1700 | int |
| 1701 | drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo) |
| 1702 | { |
| 1703 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1704 | |
| 1705 | return bo_gem->reloc_count; |
| 1706 | } |
| 1707 | |
| 1708 | /** |
| 1709 | * Removes existing relocation entries in the BO after "start". |
| 1710 | * |
| 1711 | * This allows a user to avoid a two-step process for state setup with |
| 1712 | * counting up all the buffer objects and doing a |
| 1713 | * drm_intel_bufmgr_check_aperture_space() before emitting any of the |
| 1714 | * relocations for the state setup. Instead, save the state of the |
| 1715 | * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the |
| 1716 | * state, and then check if it still fits in the aperture. |
| 1717 | * |
| 1718 | * Any further drm_intel_bufmgr_check_aperture_space() queries |
| 1719 | * involving this buffer in the tree are undefined after this call. |
| 1720 | */ |
| 1721 | void |
| 1722 | drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start) |
| 1723 | { |
| 1724 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1725 | int i; |
| 1726 | struct timespec time; |
| 1727 | |
| 1728 | clock_gettime(CLOCK_MONOTONIC, &time); |
| 1729 | |
| 1730 | assert(bo_gem->reloc_count >= start); |
| 1731 | /* Unreference the cleared target buffers */ |
| 1732 | for (i = start; i < bo_gem->reloc_count; i++) { |
| 1733 | if (bo_gem->reloc_target_info[i].bo != bo) { |
| 1734 | drm_intel_gem_bo_unreference_locked_timed(bo_gem-> |
| 1735 | reloc_target_info[i].bo, |
| 1736 | time.tv_sec); |
| 1737 | } |
| 1738 | } |
| 1739 | bo_gem->reloc_count = start; |
| 1740 | } |
| 1741 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1742 | /** |
| 1743 | * Walk the tree of relocations rooted at BO and accumulate the list of |
| 1744 | * validations to be performed and update the relocation buffers with |
| 1745 | * index values into the validation list. |
| 1746 | */ |
| 1747 | static void |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 1748 | drm_intel_gem_bo_process_reloc(drm_intel_bo *bo) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1749 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1750 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1751 | int i; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1752 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1753 | if (bo_gem->relocs == NULL) |
| 1754 | return; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1755 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1756 | for (i = 0; i < bo_gem->reloc_count; i++) { |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1757 | drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1758 | |
Eric Anholt | f179137 | 2010-06-07 14:22:36 -0700 | [diff] [blame] | 1759 | if (target_bo == bo) |
| 1760 | continue; |
| 1761 | |
Chris Wilson | 23eeb7e | 2012-02-09 10:29:22 +0000 | [diff] [blame] | 1762 | drm_intel_gem_bo_mark_mmaps_incoherent(bo); |
| 1763 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1764 | /* Continue walking the tree depth-first. */ |
| 1765 | drm_intel_gem_bo_process_reloc(target_bo); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1766 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1767 | /* Add the target to the validate list */ |
| 1768 | drm_intel_add_validate_buffer(target_bo); |
| 1769 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1770 | } |
| 1771 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1772 | static void |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1773 | drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo) |
| 1774 | { |
| 1775 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; |
| 1776 | int i; |
| 1777 | |
| 1778 | if (bo_gem->relocs == NULL) |
| 1779 | return; |
| 1780 | |
| 1781 | for (i = 0; i < bo_gem->reloc_count; i++) { |
| 1782 | drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo; |
| 1783 | int need_fence; |
| 1784 | |
Eric Anholt | f179137 | 2010-06-07 14:22:36 -0700 | [diff] [blame] | 1785 | if (target_bo == bo) |
| 1786 | continue; |
| 1787 | |
Chris Wilson | 23eeb7e | 2012-02-09 10:29:22 +0000 | [diff] [blame] | 1788 | drm_intel_gem_bo_mark_mmaps_incoherent(bo); |
| 1789 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1790 | /* Continue walking the tree depth-first. */ |
| 1791 | drm_intel_gem_bo_process_reloc2(target_bo); |
| 1792 | |
| 1793 | need_fence = (bo_gem->reloc_target_info[i].flags & |
| 1794 | DRM_INTEL_RELOC_FENCE); |
| 1795 | |
| 1796 | /* Add the target to the validate list */ |
| 1797 | drm_intel_add_validate_buffer2(target_bo, need_fence); |
| 1798 | } |
| 1799 | } |
| 1800 | |
| 1801 | |
| 1802 | static void |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1803 | drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1804 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1805 | int i; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1806 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1807 | for (i = 0; i < bufmgr_gem->exec_count; i++) { |
| 1808 | drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; |
| 1809 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1810 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 1811 | /* Update the buffer offset */ |
| 1812 | if (bufmgr_gem->exec_objects[i].offset != bo->offset) { |
| 1813 | DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n", |
| 1814 | bo_gem->gem_handle, bo_gem->name, bo->offset, |
| 1815 | (unsigned long long)bufmgr_gem->exec_objects[i]. |
| 1816 | offset); |
| 1817 | bo->offset = bufmgr_gem->exec_objects[i].offset; |
| 1818 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1819 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 1820 | } |
| 1821 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 1822 | static void |
| 1823 | drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem) |
| 1824 | { |
| 1825 | int i; |
| 1826 | |
| 1827 | for (i = 0; i < bufmgr_gem->exec_count; i++) { |
| 1828 | drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; |
| 1829 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; |
| 1830 | |
| 1831 | /* Update the buffer offset */ |
| 1832 | if (bufmgr_gem->exec2_objects[i].offset != bo->offset) { |
| 1833 | DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n", |
| 1834 | bo_gem->gem_handle, bo_gem->name, bo->offset, |
| 1835 | (unsigned long long)bufmgr_gem->exec2_objects[i].offset); |
| 1836 | bo->offset = bufmgr_gem->exec2_objects[i].offset; |
| 1837 | } |
| 1838 | } |
| 1839 | } |
| 1840 | |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 1841 | static void |
| 1842 | aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data) |
| 1843 | { |
| 1844 | fwrite(&data, 1, 4, bufmgr_gem->aub_file); |
| 1845 | } |
| 1846 | |
| 1847 | static void |
| 1848 | aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size) |
| 1849 | { |
| 1850 | fwrite(data, 1, size, bufmgr_gem->aub_file); |
| 1851 | } |
| 1852 | |
| 1853 | static void |
| 1854 | aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size) |
| 1855 | { |
| 1856 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1857 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1858 | uint32_t *data; |
| 1859 | unsigned int i; |
| 1860 | |
| 1861 | data = malloc(bo->size); |
| 1862 | drm_intel_bo_get_subdata(bo, offset, size, data); |
| 1863 | |
| 1864 | /* Easy mode: write out bo with no relocations */ |
| 1865 | if (!bo_gem->reloc_count) { |
| 1866 | aub_out_data(bufmgr_gem, data, size); |
| 1867 | free(data); |
| 1868 | return; |
| 1869 | } |
| 1870 | |
| 1871 | /* Otherwise, handle the relocations while writing. */ |
| 1872 | for (i = 0; i < size / 4; i++) { |
| 1873 | int r; |
| 1874 | for (r = 0; r < bo_gem->reloc_count; r++) { |
| 1875 | struct drm_i915_gem_relocation_entry *reloc; |
| 1876 | drm_intel_reloc_target *info; |
| 1877 | |
| 1878 | reloc = &bo_gem->relocs[r]; |
| 1879 | info = &bo_gem->reloc_target_info[r]; |
| 1880 | |
| 1881 | if (reloc->offset == offset + i * 4) { |
| 1882 | drm_intel_bo_gem *target_gem; |
| 1883 | uint32_t val; |
| 1884 | |
| 1885 | target_gem = (drm_intel_bo_gem *)info->bo; |
| 1886 | |
| 1887 | val = reloc->delta; |
| 1888 | val += target_gem->aub_offset; |
| 1889 | |
| 1890 | aub_out(bufmgr_gem, val); |
| 1891 | data[i] = val; |
| 1892 | break; |
| 1893 | } |
| 1894 | } |
| 1895 | if (r == bo_gem->reloc_count) { |
| 1896 | /* no relocation, just the data */ |
| 1897 | aub_out(bufmgr_gem, data[i]); |
| 1898 | } |
| 1899 | } |
| 1900 | |
| 1901 | free(data); |
| 1902 | } |
| 1903 | |
| 1904 | static void |
| 1905 | aub_bo_get_address(drm_intel_bo *bo) |
| 1906 | { |
| 1907 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1908 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1909 | |
| 1910 | /* Give the object a graphics address in the AUB file. We |
| 1911 | * don't just use the GEM object address because we do AUB |
| 1912 | * dumping before execution -- we want to successfully log |
| 1913 | * when the hardware might hang, and we might even want to aub |
| 1914 | * capture for a driver trying to execute on a different |
| 1915 | * generation of hardware by disabling the actual kernel exec |
| 1916 | * call. |
| 1917 | */ |
| 1918 | bo_gem->aub_offset = bufmgr_gem->aub_offset; |
| 1919 | bufmgr_gem->aub_offset += bo->size; |
| 1920 | /* XXX: Handle aperture overflow. */ |
| 1921 | assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024); |
| 1922 | } |
| 1923 | |
| 1924 | static void |
| 1925 | aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype, |
| 1926 | uint32_t offset, uint32_t size) |
| 1927 | { |
| 1928 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 1929 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1930 | |
| 1931 | aub_out(bufmgr_gem, |
| 1932 | CMD_AUB_TRACE_HEADER_BLOCK | |
| 1933 | (5 - 2)); |
| 1934 | aub_out(bufmgr_gem, |
| 1935 | AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE); |
| 1936 | aub_out(bufmgr_gem, subtype); |
| 1937 | aub_out(bufmgr_gem, bo_gem->aub_offset + offset); |
| 1938 | aub_out(bufmgr_gem, size); |
| 1939 | aub_write_bo_data(bo, offset, size); |
| 1940 | } |
| 1941 | |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 1942 | /** |
| 1943 | * Break up large objects into multiple writes. Otherwise a 128kb VBO |
| 1944 | * would overflow the 16 bits of size field in the packet header and |
| 1945 | * everything goes badly after that. |
| 1946 | */ |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 1947 | static void |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 1948 | aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype, |
| 1949 | uint32_t offset, uint32_t size) |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 1950 | { |
| 1951 | uint32_t block_size; |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 1952 | uint32_t sub_offset; |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 1953 | |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 1954 | for (sub_offset = 0; sub_offset < size; sub_offset += block_size) { |
| 1955 | block_size = size - sub_offset; |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 1956 | |
| 1957 | if (block_size > 8 * 4096) |
| 1958 | block_size = 8 * 4096; |
| 1959 | |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 1960 | aub_write_trace_block(bo, type, subtype, offset + sub_offset, |
| 1961 | block_size); |
| 1962 | } |
| 1963 | } |
| 1964 | |
| 1965 | static void |
| 1966 | aub_write_bo(drm_intel_bo *bo) |
| 1967 | { |
| 1968 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 1969 | uint32_t offset = 0; |
| 1970 | unsigned i; |
| 1971 | |
| 1972 | aub_bo_get_address(bo); |
| 1973 | |
| 1974 | /* Write out each annotated section separately. */ |
| 1975 | for (i = 0; i < bo_gem->aub_annotation_count; ++i) { |
| 1976 | drm_intel_aub_annotation *annotation = |
| 1977 | &bo_gem->aub_annotations[i]; |
| 1978 | uint32_t ending_offset = annotation->ending_offset; |
| 1979 | if (ending_offset > bo->size) |
| 1980 | ending_offset = bo->size; |
| 1981 | if (ending_offset > offset) { |
| 1982 | aub_write_large_trace_block(bo, annotation->type, |
| 1983 | annotation->subtype, |
| 1984 | offset, |
| 1985 | ending_offset - offset); |
| 1986 | offset = ending_offset; |
| 1987 | } |
| 1988 | } |
| 1989 | |
| 1990 | /* Write out any remaining unannotated data */ |
| 1991 | if (offset < bo->size) { |
| 1992 | aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0, |
| 1993 | offset, bo->size - offset); |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 1994 | } |
| 1995 | } |
| 1996 | |
| 1997 | /* |
| 1998 | * Make a ringbuffer on fly and dump it |
| 1999 | */ |
| 2000 | static void |
| 2001 | aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem, |
| 2002 | uint32_t batch_buffer, int ring_flag) |
| 2003 | { |
| 2004 | uint32_t ringbuffer[4096]; |
| 2005 | int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */ |
| 2006 | int ring_count = 0; |
| 2007 | |
| 2008 | if (ring_flag == I915_EXEC_BSD) |
| 2009 | ring = AUB_TRACE_TYPE_RING_PRB1; |
| 2010 | |
| 2011 | /* Make a ring buffer to execute our batchbuffer. */ |
| 2012 | memset(ringbuffer, 0, sizeof(ringbuffer)); |
| 2013 | ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START; |
| 2014 | ringbuffer[ring_count++] = batch_buffer; |
| 2015 | |
| 2016 | /* Write out the ring. This appears to trigger execution of |
| 2017 | * the ring in the simulator. |
| 2018 | */ |
| 2019 | aub_out(bufmgr_gem, |
| 2020 | CMD_AUB_TRACE_HEADER_BLOCK | |
| 2021 | (5 - 2)); |
| 2022 | aub_out(bufmgr_gem, |
| 2023 | AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE); |
| 2024 | aub_out(bufmgr_gem, 0); /* general/surface subtype */ |
| 2025 | aub_out(bufmgr_gem, bufmgr_gem->aub_offset); |
| 2026 | aub_out(bufmgr_gem, ring_count * 4); |
| 2027 | |
| 2028 | /* FIXME: Need some flush operations here? */ |
| 2029 | aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4); |
| 2030 | |
| 2031 | /* Update offset pointer */ |
| 2032 | bufmgr_gem->aub_offset += 4096; |
| 2033 | } |
| 2034 | |
| 2035 | void |
| 2036 | drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, |
| 2037 | int x1, int y1, int width, int height, |
| 2038 | enum aub_dump_bmp_format format, |
| 2039 | int pitch, int offset) |
| 2040 | { |
| 2041 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 2042 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; |
| 2043 | uint32_t cpp; |
| 2044 | |
| 2045 | switch (format) { |
| 2046 | case AUB_DUMP_BMP_FORMAT_8BIT: |
| 2047 | cpp = 1; |
| 2048 | break; |
| 2049 | case AUB_DUMP_BMP_FORMAT_ARGB_4444: |
| 2050 | cpp = 2; |
| 2051 | break; |
| 2052 | case AUB_DUMP_BMP_FORMAT_ARGB_0888: |
| 2053 | case AUB_DUMP_BMP_FORMAT_ARGB_8888: |
| 2054 | cpp = 4; |
| 2055 | break; |
| 2056 | default: |
| 2057 | printf("Unknown AUB dump format %d\n", format); |
| 2058 | return; |
| 2059 | } |
| 2060 | |
| 2061 | if (!bufmgr_gem->aub_file) |
| 2062 | return; |
| 2063 | |
| 2064 | aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4); |
| 2065 | aub_out(bufmgr_gem, (y1 << 16) | x1); |
| 2066 | aub_out(bufmgr_gem, |
| 2067 | (format << 24) | |
| 2068 | (cpp << 19) | |
| 2069 | pitch / 4); |
| 2070 | aub_out(bufmgr_gem, (height << 16) | width); |
| 2071 | aub_out(bufmgr_gem, bo_gem->aub_offset + offset); |
| 2072 | aub_out(bufmgr_gem, |
| 2073 | ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) | |
| 2074 | ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0)); |
| 2075 | } |
| 2076 | |
| 2077 | static void |
| 2078 | aub_exec(drm_intel_bo *bo, int ring_flag, int used) |
| 2079 | { |
| 2080 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 2081 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2082 | int i; |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 2083 | bool batch_buffer_needs_annotations; |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 2084 | |
| 2085 | if (!bufmgr_gem->aub_file) |
| 2086 | return; |
| 2087 | |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 2088 | /* If batch buffer is not annotated, annotate it the best we |
| 2089 | * can. |
| 2090 | */ |
| 2091 | batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0; |
| 2092 | if (batch_buffer_needs_annotations) { |
| 2093 | drm_intel_aub_annotation annotations[2] = { |
| 2094 | { AUB_TRACE_TYPE_BATCH, 0, used }, |
| 2095 | { AUB_TRACE_TYPE_NOTYPE, 0, bo->size } |
| 2096 | }; |
| 2097 | drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2); |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 2098 | } |
| 2099 | |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 2100 | /* Write out all buffers to AUB memory */ |
| 2101 | for (i = 0; i < bufmgr_gem->exec_count; i++) { |
| 2102 | aub_write_bo(bufmgr_gem->exec_bos[i]); |
| 2103 | } |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 2104 | |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 2105 | /* Remove any annotations we added */ |
| 2106 | if (batch_buffer_needs_annotations) |
| 2107 | drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0); |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 2108 | |
| 2109 | /* Dump ring buffer */ |
| 2110 | aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag); |
| 2111 | |
| 2112 | fflush(bufmgr_gem->aub_file); |
| 2113 | |
| 2114 | /* |
| 2115 | * One frame has been dumped. So reset the aub_offset for the next frame. |
| 2116 | * |
| 2117 | * FIXME: Can we do this? |
| 2118 | */ |
| 2119 | bufmgr_gem->aub_offset = 0x10000; |
| 2120 | } |
| 2121 | |
Eric Anholt | f9d98be | 2008-09-08 08:51:40 -0700 | [diff] [blame] | 2122 | static int |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2123 | drm_intel_gem_bo_exec(drm_intel_bo *bo, int used, |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2124 | drm_clip_rect_t * cliprects, int num_cliprects, int DR4) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2125 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2126 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 2127 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2128 | struct drm_i915_gem_execbuffer execbuf; |
| 2129 | int ret, i; |
Eric Anholt | f9d98be | 2008-09-08 08:51:40 -0700 | [diff] [blame] | 2130 | |
Chris Wilson | 792fed1 | 2009-12-02 13:12:39 +0000 | [diff] [blame] | 2131 | if (bo_gem->has_error) |
| 2132 | return -ENOMEM; |
| 2133 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2134 | pthread_mutex_lock(&bufmgr_gem->lock); |
| 2135 | /* Update indices and set up the validate list. */ |
| 2136 | drm_intel_gem_bo_process_reloc(bo); |
Eric Anholt | f9d98be | 2008-09-08 08:51:40 -0700 | [diff] [blame] | 2137 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2138 | /* Add the batch buffer to the validation list. There are no |
| 2139 | * relocations pointing to it. |
| 2140 | */ |
| 2141 | drm_intel_add_validate_buffer(bo); |
Eric Anholt | f9d98be | 2008-09-08 08:51:40 -0700 | [diff] [blame] | 2142 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 2143 | VG_CLEAR(execbuf); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2144 | execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects; |
| 2145 | execbuf.buffer_count = bufmgr_gem->exec_count; |
| 2146 | execbuf.batch_start_offset = 0; |
| 2147 | execbuf.batch_len = used; |
| 2148 | execbuf.cliprects_ptr = (uintptr_t) cliprects; |
| 2149 | execbuf.num_cliprects = num_cliprects; |
| 2150 | execbuf.DR1 = 0; |
| 2151 | execbuf.DR4 = DR4; |
Eric Anholt | f9d98be | 2008-09-08 08:51:40 -0700 | [diff] [blame] | 2152 | |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 2153 | ret = drmIoctl(bufmgr_gem->fd, |
| 2154 | DRM_IOCTL_I915_GEM_EXECBUFFER, |
| 2155 | &execbuf); |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 2156 | if (ret != 0) { |
| 2157 | ret = -errno; |
| 2158 | if (errno == ENOSPC) { |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 2159 | DBG("Execbuffer fails to pin. " |
| 2160 | "Estimate: %u. Actual: %u. Available: %u\n", |
| 2161 | drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos, |
| 2162 | bufmgr_gem-> |
| 2163 | exec_count), |
| 2164 | drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos, |
| 2165 | bufmgr_gem-> |
| 2166 | exec_count), |
| 2167 | (unsigned int)bufmgr_gem->gtt_size); |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 2168 | } |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2169 | } |
| 2170 | drm_intel_update_buffer_offsets(bufmgr_gem); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2171 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2172 | if (bufmgr_gem->bufmgr.debug) |
| 2173 | drm_intel_gem_dump_validation_list(bufmgr_gem); |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2174 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2175 | for (i = 0; i < bufmgr_gem->exec_count; i++) { |
| 2176 | drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; |
| 2177 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2178 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2179 | /* Disconnect the buffer from the validate list */ |
| 2180 | bo_gem->validate_index = -1; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2181 | bufmgr_gem->exec_bos[i] = NULL; |
| 2182 | } |
| 2183 | bufmgr_gem->exec_count = 0; |
| 2184 | pthread_mutex_unlock(&bufmgr_gem->lock); |
Eric Anholt | f9d98be | 2008-09-08 08:51:40 -0700 | [diff] [blame] | 2185 | |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 2186 | return ret; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2187 | } |
| 2188 | |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2189 | static int |
Ben Widawsky | 3ed3871 | 2012-03-18 18:28:28 -0700 | [diff] [blame] | 2190 | do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx, |
| 2191 | drm_clip_rect_t *cliprects, int num_cliprects, int DR4, |
| 2192 | unsigned int flags) |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2193 | { |
| 2194 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; |
| 2195 | struct drm_i915_gem_execbuffer2 execbuf; |
Kenneth Graunke | 6e642db | 2011-10-11 14:38:34 -0700 | [diff] [blame] | 2196 | int ret = 0; |
| 2197 | int i; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2198 | |
Chris Wilson | 0184bb1 | 2010-12-19 13:01:15 +0000 | [diff] [blame] | 2199 | switch (flags & 0x7) { |
Chris Wilson | 057fab3 | 2010-10-26 11:35:11 +0100 | [diff] [blame] | 2200 | default: |
Zou Nan hai | 66375fd | 2010-06-02 10:07:37 +0800 | [diff] [blame] | 2201 | return -EINVAL; |
Chris Wilson | 057fab3 | 2010-10-26 11:35:11 +0100 | [diff] [blame] | 2202 | case I915_EXEC_BLT: |
| 2203 | if (!bufmgr_gem->has_blt) |
| 2204 | return -EINVAL; |
| 2205 | break; |
| 2206 | case I915_EXEC_BSD: |
| 2207 | if (!bufmgr_gem->has_bsd) |
| 2208 | return -EINVAL; |
| 2209 | break; |
| 2210 | case I915_EXEC_RENDER: |
| 2211 | case I915_EXEC_DEFAULT: |
| 2212 | break; |
| 2213 | } |
Zou Nan hai | 66375fd | 2010-06-02 10:07:37 +0800 | [diff] [blame] | 2214 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2215 | pthread_mutex_lock(&bufmgr_gem->lock); |
| 2216 | /* Update indices and set up the validate list. */ |
| 2217 | drm_intel_gem_bo_process_reloc2(bo); |
| 2218 | |
| 2219 | /* Add the batch buffer to the validation list. There are no relocations |
| 2220 | * pointing to it. |
| 2221 | */ |
| 2222 | drm_intel_add_validate_buffer2(bo, 0); |
| 2223 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 2224 | VG_CLEAR(execbuf); |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2225 | execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects; |
| 2226 | execbuf.buffer_count = bufmgr_gem->exec_count; |
| 2227 | execbuf.batch_start_offset = 0; |
| 2228 | execbuf.batch_len = used; |
| 2229 | execbuf.cliprects_ptr = (uintptr_t)cliprects; |
| 2230 | execbuf.num_cliprects = num_cliprects; |
| 2231 | execbuf.DR1 = 0; |
| 2232 | execbuf.DR4 = DR4; |
Chris Wilson | 0184bb1 | 2010-12-19 13:01:15 +0000 | [diff] [blame] | 2233 | execbuf.flags = flags; |
Ben Widawsky | 3ed3871 | 2012-03-18 18:28:28 -0700 | [diff] [blame] | 2234 | if (ctx == NULL) |
| 2235 | i915_execbuffer2_set_context_id(execbuf, 0); |
| 2236 | else |
| 2237 | i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id); |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2238 | execbuf.rsvd2 = 0; |
| 2239 | |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 2240 | aub_exec(bo, flags, used); |
| 2241 | |
Kenneth Graunke | 6e642db | 2011-10-11 14:38:34 -0700 | [diff] [blame] | 2242 | if (bufmgr_gem->no_exec) |
| 2243 | goto skip_execution; |
| 2244 | |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 2245 | ret = drmIoctl(bufmgr_gem->fd, |
| 2246 | DRM_IOCTL_I915_GEM_EXECBUFFER2, |
| 2247 | &execbuf); |
Chris Wilson | 3e21e3b | 2010-03-04 21:17:48 +0000 | [diff] [blame] | 2248 | if (ret != 0) { |
| 2249 | ret = -errno; |
Chris Wilson | 13e8270 | 2010-06-21 15:38:06 +0100 | [diff] [blame] | 2250 | if (ret == -ENOSPC) { |
Chris Wilson | 9621486 | 2010-10-01 16:50:09 +0100 | [diff] [blame] | 2251 | DBG("Execbuffer fails to pin. " |
| 2252 | "Estimate: %u. Actual: %u. Available: %u\n", |
| 2253 | drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos, |
| 2254 | bufmgr_gem->exec_count), |
| 2255 | drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos, |
| 2256 | bufmgr_gem->exec_count), |
| 2257 | (unsigned int) bufmgr_gem->gtt_size); |
Chris Wilson | 3e21e3b | 2010-03-04 21:17:48 +0000 | [diff] [blame] | 2258 | } |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2259 | } |
| 2260 | drm_intel_update_buffer_offsets2(bufmgr_gem); |
| 2261 | |
Kenneth Graunke | 6e642db | 2011-10-11 14:38:34 -0700 | [diff] [blame] | 2262 | skip_execution: |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2263 | if (bufmgr_gem->bufmgr.debug) |
| 2264 | drm_intel_gem_dump_validation_list(bufmgr_gem); |
| 2265 | |
| 2266 | for (i = 0; i < bufmgr_gem->exec_count; i++) { |
| 2267 | drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; |
| 2268 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; |
| 2269 | |
| 2270 | /* Disconnect the buffer from the validate list */ |
| 2271 | bo_gem->validate_index = -1; |
| 2272 | bufmgr_gem->exec_bos[i] = NULL; |
| 2273 | } |
| 2274 | bufmgr_gem->exec_count = 0; |
| 2275 | pthread_mutex_unlock(&bufmgr_gem->lock); |
| 2276 | |
Chris Wilson | 3e21e3b | 2010-03-04 21:17:48 +0000 | [diff] [blame] | 2277 | return ret; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2278 | } |
| 2279 | |
| 2280 | static int |
Zou Nan hai | 66375fd | 2010-06-02 10:07:37 +0800 | [diff] [blame] | 2281 | drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used, |
| 2282 | drm_clip_rect_t *cliprects, int num_cliprects, |
| 2283 | int DR4) |
| 2284 | { |
Ben Widawsky | 3ed3871 | 2012-03-18 18:28:28 -0700 | [diff] [blame] | 2285 | return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, |
| 2286 | I915_EXEC_RENDER); |
| 2287 | } |
| 2288 | |
| 2289 | static int |
| 2290 | drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, |
| 2291 | drm_clip_rect_t *cliprects, int num_cliprects, int DR4, |
| 2292 | unsigned int flags) |
| 2293 | { |
| 2294 | return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, |
| 2295 | flags); |
| 2296 | } |
| 2297 | |
| 2298 | int |
| 2299 | drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, |
| 2300 | int used, unsigned int flags) |
| 2301 | { |
| 2302 | return do_exec2(bo, used, ctx, NULL, 0, 0, flags); |
Zou Nan hai | 66375fd | 2010-06-02 10:07:37 +0800 | [diff] [blame] | 2303 | } |
| 2304 | |
| 2305 | static int |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2306 | drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment) |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2307 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2308 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 2309 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2310 | struct drm_i915_gem_pin pin; |
| 2311 | int ret; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2312 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 2313 | VG_CLEAR(pin); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2314 | pin.handle = bo_gem->gem_handle; |
| 2315 | pin.alignment = alignment; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2316 | |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 2317 | ret = drmIoctl(bufmgr_gem->fd, |
| 2318 | DRM_IOCTL_I915_GEM_PIN, |
| 2319 | &pin); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2320 | if (ret != 0) |
| 2321 | return -errno; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2322 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2323 | bo->offset = pin.offset; |
| 2324 | return 0; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2325 | } |
| 2326 | |
| 2327 | static int |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2328 | drm_intel_gem_bo_unpin(drm_intel_bo *bo) |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2329 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2330 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 2331 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2332 | struct drm_i915_gem_unpin unpin; |
| 2333 | int ret; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2334 | |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 2335 | VG_CLEAR(unpin); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2336 | unpin.handle = bo_gem->gem_handle; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2337 | |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 2338 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2339 | if (ret != 0) |
| 2340 | return -errno; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2341 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2342 | return 0; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2343 | } |
| 2344 | |
| 2345 | static int |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 2346 | drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo, |
| 2347 | uint32_t tiling_mode, |
| 2348 | uint32_t stride) |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2349 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2350 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 2351 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2352 | struct drm_i915_gem_set_tiling set_tiling; |
| 2353 | int ret; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2354 | |
Chris Wilson | aba3502 | 2010-06-22 13:00:22 +0100 | [diff] [blame] | 2355 | if (bo_gem->global_name == 0 && |
| 2356 | tiling_mode == bo_gem->tiling_mode && |
Chris Wilson | 056aa9b | 2010-06-21 14:31:29 +0100 | [diff] [blame] | 2357 | stride == bo_gem->stride) |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2358 | return 0; |
Keith Packard | 18f091d | 2008-12-15 15:08:12 -0800 | [diff] [blame] | 2359 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2360 | memset(&set_tiling, 0, sizeof(set_tiling)); |
Chris Wilson | 8ffd2e1 | 2009-12-01 13:08:04 +0000 | [diff] [blame] | 2361 | do { |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 2362 | /* set_tiling is slightly broken and overwrites the |
| 2363 | * input on the error path, so we have to open code |
| 2364 | * rmIoctl. |
| 2365 | */ |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 2366 | set_tiling.handle = bo_gem->gem_handle; |
| 2367 | set_tiling.tiling_mode = tiling_mode; |
Chris Wilson | 4f0f871 | 2010-02-10 09:45:13 +0000 | [diff] [blame] | 2368 | set_tiling.stride = stride; |
| 2369 | |
Chris Wilson | 8ffd2e1 | 2009-12-01 13:08:04 +0000 | [diff] [blame] | 2370 | ret = ioctl(bufmgr_gem->fd, |
| 2371 | DRM_IOCTL_I915_GEM_SET_TILING, |
| 2372 | &set_tiling); |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 2373 | } while (ret == -1 && (errno == EINTR || errno == EAGAIN)); |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 2374 | if (ret == -1) |
| 2375 | return -errno; |
| 2376 | |
| 2377 | bo_gem->tiling_mode = set_tiling.tiling_mode; |
| 2378 | bo_gem->swizzle_mode = set_tiling.swizzle_mode; |
Chris Wilson | aba3502 | 2010-06-22 13:00:22 +0100 | [diff] [blame] | 2379 | bo_gem->stride = set_tiling.stride; |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 2380 | return 0; |
| 2381 | } |
| 2382 | |
| 2383 | static int |
| 2384 | drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, |
| 2385 | uint32_t stride) |
| 2386 | { |
| 2387 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 2388 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2389 | int ret; |
| 2390 | |
Chris Wilson | cd34cbe | 2010-06-22 11:07:26 +0100 | [diff] [blame] | 2391 | /* Linear buffers have no stride. By ensuring that we only ever use |
| 2392 | * stride 0 with linear buffers, we simplify our code. |
| 2393 | */ |
Chris Wilson | c7bbaca | 2010-06-22 11:15:56 +0100 | [diff] [blame] | 2394 | if (*tiling_mode == I915_TILING_NONE) |
Chris Wilson | cd34cbe | 2010-06-22 11:07:26 +0100 | [diff] [blame] | 2395 | stride = 0; |
| 2396 | |
Chris Wilson | 1db22ff | 2010-06-21 14:27:23 +0100 | [diff] [blame] | 2397 | ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride); |
| 2398 | if (ret == 0) |
Chris Wilson | fcf3e61 | 2010-05-24 18:35:41 +0100 | [diff] [blame] | 2399 | drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); |
Chris Wilson | e22fb79 | 2009-11-30 22:14:30 +0000 | [diff] [blame] | 2400 | |
Keith Packard | 18f091d | 2008-12-15 15:08:12 -0800 | [diff] [blame] | 2401 | *tiling_mode = bo_gem->tiling_mode; |
Chris Wilson | fcf3e61 | 2010-05-24 18:35:41 +0100 | [diff] [blame] | 2402 | return ret; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2403 | } |
| 2404 | |
| 2405 | static int |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2406 | drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, |
| 2407 | uint32_t * swizzle_mode) |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2408 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2409 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Eric Anholt | 9933838 | 2008-10-14 13:18:11 -0700 | [diff] [blame] | 2410 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2411 | *tiling_mode = bo_gem->tiling_mode; |
| 2412 | *swizzle_mode = bo_gem->swizzle_mode; |
| 2413 | return 0; |
Eric Anholt | 9933838 | 2008-10-14 13:18:11 -0700 | [diff] [blame] | 2414 | } |
| 2415 | |
Dave Airlie | ff65de9 | 2012-07-15 00:22:46 +0000 | [diff] [blame] | 2416 | drm_intel_bo * |
| 2417 | drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size) |
| 2418 | { |
| 2419 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; |
| 2420 | int ret; |
| 2421 | uint32_t handle; |
| 2422 | drm_intel_bo_gem *bo_gem; |
| 2423 | struct drm_i915_gem_get_tiling get_tiling; |
| 2424 | |
| 2425 | ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle); |
| 2426 | if (ret) { |
| 2427 | fprintf(stderr,"ret is %d %d\n", ret, errno); |
| 2428 | return NULL; |
| 2429 | } |
| 2430 | |
| 2431 | bo_gem = calloc(1, sizeof(*bo_gem)); |
| 2432 | if (!bo_gem) |
| 2433 | return NULL; |
| 2434 | |
| 2435 | bo_gem->bo.size = size; |
| 2436 | bo_gem->bo.handle = handle; |
| 2437 | bo_gem->bo.bufmgr = bufmgr; |
| 2438 | |
| 2439 | bo_gem->gem_handle = handle; |
| 2440 | |
| 2441 | atomic_set(&bo_gem->refcount, 1); |
| 2442 | |
| 2443 | bo_gem->name = "prime"; |
| 2444 | bo_gem->validate_index = -1; |
| 2445 | bo_gem->reloc_tree_fences = 0; |
| 2446 | bo_gem->used_as_reloc_target = false; |
| 2447 | bo_gem->has_error = false; |
| 2448 | bo_gem->reusable = false; |
| 2449 | |
| 2450 | DRMINITLISTHEAD(&bo_gem->name_list); |
| 2451 | DRMINITLISTHEAD(&bo_gem->vma_list); |
| 2452 | |
| 2453 | VG_CLEAR(get_tiling); |
| 2454 | get_tiling.handle = bo_gem->gem_handle; |
| 2455 | ret = drmIoctl(bufmgr_gem->fd, |
| 2456 | DRM_IOCTL_I915_GEM_GET_TILING, |
| 2457 | &get_tiling); |
| 2458 | if (ret != 0) { |
| 2459 | drm_intel_gem_bo_unreference(&bo_gem->bo); |
| 2460 | return NULL; |
| 2461 | } |
| 2462 | bo_gem->tiling_mode = get_tiling.tiling_mode; |
| 2463 | bo_gem->swizzle_mode = get_tiling.swizzle_mode; |
| 2464 | /* XXX stride is unknown */ |
| 2465 | drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); |
| 2466 | |
| 2467 | return &bo_gem->bo; |
| 2468 | } |
| 2469 | |
| 2470 | int |
| 2471 | drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd) |
| 2472 | { |
| 2473 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 2474 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2475 | |
| 2476 | return drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle, DRM_CLOEXEC, prime_fd); |
| 2477 | } |
| 2478 | |
Eric Anholt | 9933838 | 2008-10-14 13:18:11 -0700 | [diff] [blame] | 2479 | static int |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2480 | drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name) |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2481 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2482 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; |
| 2483 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2484 | int ret; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2485 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2486 | if (!bo_gem->global_name) { |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 2487 | struct drm_gem_flink flink; |
| 2488 | |
| 2489 | VG_CLEAR(flink); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2490 | flink.handle = bo_gem->gem_handle; |
| 2491 | |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 2492 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2493 | if (ret != 0) |
| 2494 | return -errno; |
Chris Wilson | 90b23cc | 2012-02-09 10:23:10 +0000 | [diff] [blame] | 2495 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2496 | bo_gem->global_name = flink.name; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 2497 | bo_gem->reusable = false; |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 2498 | |
| 2499 | DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2500 | } |
| 2501 | |
| 2502 | *name = bo_gem->global_name; |
| 2503 | return 0; |
Keith Packard | 8e41ce1 | 2008-08-04 00:34:08 -0700 | [diff] [blame] | 2504 | } |
| 2505 | |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2506 | /** |
| 2507 | * Enables unlimited caching of buffer objects for reuse. |
| 2508 | * |
| 2509 | * This is potentially very memory expensive, as the cache at each bucket |
| 2510 | * size is only bounded by how many buffers of that size we've managed to have |
| 2511 | * in flight at once. |
| 2512 | */ |
| 2513 | void |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2514 | drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2515 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2516 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2517 | |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 2518 | bufmgr_gem->bo_reuse = true; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2519 | } |
| 2520 | |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2521 | /** |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2522 | * Enable use of fenced reloc type. |
| 2523 | * |
| 2524 | * New code should enable this to avoid unnecessary fence register |
| 2525 | * allocation. If this option is not enabled, all relocs will have fence |
| 2526 | * register allocated. |
| 2527 | */ |
| 2528 | void |
| 2529 | drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr) |
| 2530 | { |
Eric Anholt | 766fa79 | 2010-03-02 16:04:14 -0800 | [diff] [blame] | 2531 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2532 | |
Eric Anholt | 766fa79 | 2010-03-02 16:04:14 -0800 | [diff] [blame] | 2533 | if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2) |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 2534 | bufmgr_gem->fenced_relocs = true; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2535 | } |
| 2536 | |
| 2537 | /** |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2538 | * Return the additional aperture space required by the tree of buffer objects |
| 2539 | * rooted at bo. |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2540 | */ |
| 2541 | static int |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2542 | drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2543 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2544 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2545 | int i; |
| 2546 | int total = 0; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2547 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2548 | if (bo == NULL || bo_gem->included_in_check_aperture) |
| 2549 | return 0; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2550 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2551 | total += bo->size; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 2552 | bo_gem->included_in_check_aperture = true; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2553 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2554 | for (i = 0; i < bo_gem->reloc_count; i++) |
| 2555 | total += |
| 2556 | drm_intel_gem_bo_get_aperture_space(bo_gem-> |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2557 | reloc_target_info[i].bo); |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2558 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2559 | return total; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2560 | } |
| 2561 | |
| 2562 | /** |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2563 | * Count the number of buffers in this list that need a fence reg |
| 2564 | * |
| 2565 | * If the count is greater than the number of available regs, we'll have |
| 2566 | * to ask the caller to resubmit a batch with fewer tiled buffers. |
| 2567 | * |
Eric Anholt | 9209c9a | 2009-01-27 16:54:11 -0800 | [diff] [blame] | 2568 | * This function over-counts if the same buffer is used multiple times. |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2569 | */ |
| 2570 | static unsigned int |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2571 | drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count) |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2572 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2573 | int i; |
| 2574 | unsigned int total = 0; |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2575 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2576 | for (i = 0; i < count; i++) { |
| 2577 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i]; |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2578 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2579 | if (bo_gem == NULL) |
| 2580 | continue; |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2581 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2582 | total += bo_gem->reloc_tree_fences; |
| 2583 | } |
| 2584 | return total; |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2585 | } |
| 2586 | |
| 2587 | /** |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2588 | * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready |
| 2589 | * for the next drm_intel_bufmgr_check_aperture_space() call. |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2590 | */ |
| 2591 | static void |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2592 | drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo) |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2593 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2594 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2595 | int i; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2596 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2597 | if (bo == NULL || !bo_gem->included_in_check_aperture) |
| 2598 | return; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2599 | |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 2600 | bo_gem->included_in_check_aperture = false; |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2601 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2602 | for (i = 0; i < bo_gem->reloc_count; i++) |
| 2603 | drm_intel_gem_bo_clear_aperture_space_flag(bo_gem-> |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2604 | reloc_target_info[i].bo); |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2605 | } |
| 2606 | |
| 2607 | /** |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 2608 | * Return a conservative estimate for the amount of aperture required |
| 2609 | * for a collection of buffers. This may double-count some buffers. |
| 2610 | */ |
| 2611 | static unsigned int |
| 2612 | drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count) |
| 2613 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2614 | int i; |
| 2615 | unsigned int total = 0; |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 2616 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2617 | for (i = 0; i < count; i++) { |
| 2618 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i]; |
| 2619 | if (bo_gem != NULL) |
| 2620 | total += bo_gem->reloc_tree_size; |
| 2621 | } |
| 2622 | return total; |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 2623 | } |
| 2624 | |
| 2625 | /** |
| 2626 | * Return the amount of aperture needed for a collection of buffers. |
| 2627 | * This avoids double counting any buffers, at the cost of looking |
| 2628 | * at every buffer in the set. |
| 2629 | */ |
| 2630 | static unsigned int |
| 2631 | drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count) |
| 2632 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2633 | int i; |
| 2634 | unsigned int total = 0; |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 2635 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2636 | for (i = 0; i < count; i++) { |
| 2637 | total += drm_intel_gem_bo_get_aperture_space(bo_array[i]); |
| 2638 | /* For the first buffer object in the array, we get an |
| 2639 | * accurate count back for its reloc_tree size (since nothing |
| 2640 | * had been flagged as being counted yet). We can save that |
| 2641 | * value out as a more conservative reloc_tree_size that |
| 2642 | * avoids double-counting target buffers. Since the first |
| 2643 | * buffer happens to usually be the batch buffer in our |
| 2644 | * callers, this can pull us back from doing the tree |
| 2645 | * walk on every new batch emit. |
| 2646 | */ |
| 2647 | if (i == 0) { |
| 2648 | drm_intel_bo_gem *bo_gem = |
| 2649 | (drm_intel_bo_gem *) bo_array[i]; |
| 2650 | bo_gem->reloc_tree_size = total; |
| 2651 | } |
Eric Anholt | 7ce8d4c | 2009-02-27 13:46:31 -0800 | [diff] [blame] | 2652 | } |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 2653 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2654 | for (i = 0; i < count; i++) |
| 2655 | drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]); |
| 2656 | return total; |
Keith Packard | b13f4e1 | 2008-11-21 01:49:39 -0800 | [diff] [blame] | 2657 | } |
| 2658 | |
| 2659 | /** |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2660 | * Return -1 if the batchbuffer should be flushed before attempting to |
| 2661 | * emit rendering referencing the buffers pointed to by bo_array. |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2662 | * |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2663 | * This is required because if we try to emit a batchbuffer with relocations |
| 2664 | * to a tree of buffers that won't simultaneously fit in the aperture, |
| 2665 | * the rendering will return an error at a point where the software is not |
| 2666 | * prepared to recover from it. |
| 2667 | * |
| 2668 | * However, we also want to emit the batchbuffer significantly before we reach |
| 2669 | * the limit, as a series of batchbuffers each of which references buffers |
| 2670 | * covering almost all of the aperture means that at each emit we end up |
| 2671 | * waiting to evict a buffer from the last rendering, and we get synchronous |
| 2672 | * performance. By emitting smaller batchbuffers, we eat some CPU overhead to |
| 2673 | * get better parallelism. |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2674 | */ |
| 2675 | static int |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2676 | drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2677 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2678 | drm_intel_bufmgr_gem *bufmgr_gem = |
| 2679 | (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr; |
| 2680 | unsigned int total = 0; |
| 2681 | unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4; |
| 2682 | int total_fences; |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2683 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2684 | /* Check for fence reg constraints if necessary */ |
| 2685 | if (bufmgr_gem->available_fences) { |
| 2686 | total_fences = drm_intel_gem_total_fences(bo_array, count); |
| 2687 | if (total_fences > bufmgr_gem->available_fences) |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 2688 | return -ENOSPC; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2689 | } |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2690 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2691 | total = drm_intel_gem_estimate_batch_space(bo_array, count); |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 2692 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2693 | if (total > threshold) |
| 2694 | total = drm_intel_gem_compute_batch_space(bo_array, count); |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 2695 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2696 | if (total > threshold) { |
| 2697 | DBG("check_space: overflowed available aperture, " |
| 2698 | "%dkb vs %dkb\n", |
| 2699 | total / 1024, (int)bufmgr_gem->gtt_size / 1024); |
Chris Wilson | acb4aa6 | 2009-12-02 12:40:26 +0000 | [diff] [blame] | 2700 | return -ENOSPC; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2701 | } else { |
| 2702 | DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024, |
| 2703 | (int)bufmgr_gem->gtt_size / 1024); |
| 2704 | return 0; |
| 2705 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2706 | } |
| 2707 | |
Keith Packard | 5b5ce30 | 2009-05-11 13:42:12 -0700 | [diff] [blame] | 2708 | /* |
| 2709 | * Disable buffer reuse for objects which are shared with the kernel |
| 2710 | * as scanout buffers |
| 2711 | */ |
| 2712 | static int |
| 2713 | drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo) |
| 2714 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2715 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
Keith Packard | 5b5ce30 | 2009-05-11 13:42:12 -0700 | [diff] [blame] | 2716 | |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 2717 | bo_gem->reusable = false; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2718 | return 0; |
Keith Packard | 5b5ce30 | 2009-05-11 13:42:12 -0700 | [diff] [blame] | 2719 | } |
| 2720 | |
Eric Anholt | 769b105 | 2009-10-01 19:09:26 -0700 | [diff] [blame] | 2721 | static int |
Chris Wilson | 07e7589 | 2010-05-11 08:54:06 +0100 | [diff] [blame] | 2722 | drm_intel_gem_bo_is_reusable(drm_intel_bo *bo) |
| 2723 | { |
| 2724 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2725 | |
| 2726 | return bo_gem->reusable; |
| 2727 | } |
| 2728 | |
| 2729 | static int |
Eric Anholt | 66d2714 | 2009-10-20 13:20:55 -0700 | [diff] [blame] | 2730 | _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) |
Eric Anholt | 769b105 | 2009-10-01 19:09:26 -0700 | [diff] [blame] | 2731 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2732 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2733 | int i; |
Eric Anholt | 769b105 | 2009-10-01 19:09:26 -0700 | [diff] [blame] | 2734 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2735 | for (i = 0; i < bo_gem->reloc_count; i++) { |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2736 | if (bo_gem->reloc_target_info[i].bo == target_bo) |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2737 | return 1; |
Eric Anholt | 4f7704a | 2010-06-10 08:58:08 -0700 | [diff] [blame] | 2738 | if (bo == bo_gem->reloc_target_info[i].bo) |
| 2739 | continue; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 2740 | if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo, |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 2741 | target_bo)) |
| 2742 | return 1; |
| 2743 | } |
| 2744 | |
Eric Anholt | 769b105 | 2009-10-01 19:09:26 -0700 | [diff] [blame] | 2745 | return 0; |
Eric Anholt | 769b105 | 2009-10-01 19:09:26 -0700 | [diff] [blame] | 2746 | } |
| 2747 | |
Eric Anholt | 66d2714 | 2009-10-20 13:20:55 -0700 | [diff] [blame] | 2748 | /** Return true if target_bo is referenced by bo's relocation tree. */ |
| 2749 | static int |
| 2750 | drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) |
| 2751 | { |
| 2752 | drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo; |
| 2753 | |
| 2754 | if (bo == NULL || target_bo == NULL) |
| 2755 | return 0; |
| 2756 | if (target_bo_gem->used_as_reloc_target) |
| 2757 | return _drm_intel_gem_bo_references(bo, target_bo); |
| 2758 | return 0; |
| 2759 | } |
| 2760 | |
Eric Anholt | 0ec768e | 2010-06-04 17:09:11 -0700 | [diff] [blame] | 2761 | static void |
| 2762 | add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size) |
| 2763 | { |
| 2764 | unsigned int i = bufmgr_gem->num_buckets; |
| 2765 | |
| 2766 | assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket)); |
| 2767 | |
| 2768 | DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head); |
| 2769 | bufmgr_gem->cache_bucket[i].size = size; |
| 2770 | bufmgr_gem->num_buckets++; |
| 2771 | } |
| 2772 | |
| 2773 | static void |
| 2774 | init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem) |
| 2775 | { |
| 2776 | unsigned long size, cache_max_size = 64 * 1024 * 1024; |
| 2777 | |
| 2778 | /* OK, so power of two buckets was too wasteful of memory. |
| 2779 | * Give 3 other sizes between each power of two, to hopefully |
| 2780 | * cover things accurately enough. (The alternative is |
| 2781 | * probably to just go for exact matching of sizes, and assume |
| 2782 | * that for things like composited window resize the tiled |
| 2783 | * width/height alignment and rounding of sizes to pages will |
| 2784 | * get us useful cache hit rates anyway) |
| 2785 | */ |
| 2786 | add_bucket(bufmgr_gem, 4096); |
| 2787 | add_bucket(bufmgr_gem, 4096 * 2); |
| 2788 | add_bucket(bufmgr_gem, 4096 * 3); |
| 2789 | |
| 2790 | /* Initialize the linked lists for BO reuse cache. */ |
| 2791 | for (size = 4 * 4096; size <= cache_max_size; size *= 2) { |
| 2792 | add_bucket(bufmgr_gem, size); |
| 2793 | |
| 2794 | add_bucket(bufmgr_gem, size + size * 1 / 4); |
| 2795 | add_bucket(bufmgr_gem, size + size * 2 / 4); |
| 2796 | add_bucket(bufmgr_gem, size + size * 3 / 4); |
| 2797 | } |
| 2798 | } |
| 2799 | |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 2800 | void |
| 2801 | drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit) |
| 2802 | { |
| 2803 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; |
| 2804 | |
| 2805 | bufmgr_gem->vma_max = limit; |
| 2806 | |
| 2807 | drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); |
| 2808 | } |
| 2809 | |
Eric Anholt | 769b105 | 2009-10-01 19:09:26 -0700 | [diff] [blame] | 2810 | /** |
Kenneth Graunke | 6e642db | 2011-10-11 14:38:34 -0700 | [diff] [blame] | 2811 | * Get the PCI ID for the device. This can be overridden by setting the |
| 2812 | * INTEL_DEVID_OVERRIDE environment variable to the desired ID. |
| 2813 | */ |
| 2814 | static int |
| 2815 | get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem) |
| 2816 | { |
| 2817 | char *devid_override; |
| 2818 | int devid; |
| 2819 | int ret; |
| 2820 | drm_i915_getparam_t gp; |
| 2821 | |
| 2822 | if (geteuid() == getuid()) { |
| 2823 | devid_override = getenv("INTEL_DEVID_OVERRIDE"); |
| 2824 | if (devid_override) { |
| 2825 | bufmgr_gem->no_exec = true; |
| 2826 | return strtod(devid_override, NULL); |
| 2827 | } |
| 2828 | } |
| 2829 | |
Eric Anholt | 5de5b74 | 2012-03-13 16:49:53 -0700 | [diff] [blame] | 2830 | VG_CLEAR(devid); |
Kenneth Graunke | 6e642db | 2011-10-11 14:38:34 -0700 | [diff] [blame] | 2831 | VG_CLEAR(gp); |
| 2832 | gp.param = I915_PARAM_CHIPSET_ID; |
| 2833 | gp.value = &devid; |
| 2834 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); |
| 2835 | if (ret) { |
| 2836 | fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno); |
| 2837 | fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); |
| 2838 | } |
| 2839 | return devid; |
| 2840 | } |
| 2841 | |
| 2842 | int |
| 2843 | drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr) |
| 2844 | { |
| 2845 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; |
| 2846 | |
| 2847 | return bufmgr_gem->pci_device; |
| 2848 | } |
| 2849 | |
| 2850 | /** |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 2851 | * Sets up AUB dumping. |
| 2852 | * |
| 2853 | * This is a trace file format that can be used with the simulator. |
| 2854 | * Packets are emitted in a format somewhat like GPU command packets. |
| 2855 | * You can set up a GTT and upload your objects into the referenced |
| 2856 | * space, then send off batchbuffers and get BMPs out the other end. |
| 2857 | */ |
| 2858 | void |
| 2859 | drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) |
| 2860 | { |
| 2861 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; |
| 2862 | int entry = 0x200003; |
| 2863 | int i; |
| 2864 | int gtt_size = 0x10000; |
| 2865 | |
| 2866 | if (!enable) { |
| 2867 | if (bufmgr_gem->aub_file) { |
| 2868 | fclose(bufmgr_gem->aub_file); |
| 2869 | bufmgr_gem->aub_file = NULL; |
| 2870 | } |
| 2871 | } |
| 2872 | |
| 2873 | if (geteuid() != getuid()) |
| 2874 | return; |
| 2875 | |
| 2876 | bufmgr_gem->aub_file = fopen("intel.aub", "w+"); |
| 2877 | if (!bufmgr_gem->aub_file) |
| 2878 | return; |
| 2879 | |
| 2880 | /* Start allocating objects from just after the GTT. */ |
| 2881 | bufmgr_gem->aub_offset = gtt_size; |
| 2882 | |
| 2883 | /* Start with a (required) version packet. */ |
| 2884 | aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2)); |
| 2885 | aub_out(bufmgr_gem, |
| 2886 | (4 << AUB_HEADER_MAJOR_SHIFT) | |
| 2887 | (0 << AUB_HEADER_MINOR_SHIFT)); |
| 2888 | for (i = 0; i < 8; i++) { |
| 2889 | aub_out(bufmgr_gem, 0); /* app name */ |
| 2890 | } |
| 2891 | aub_out(bufmgr_gem, 0); /* timestamp */ |
| 2892 | aub_out(bufmgr_gem, 0); /* timestamp */ |
| 2893 | aub_out(bufmgr_gem, 0); /* comment len */ |
| 2894 | |
| 2895 | /* Set up the GTT. The max we can handle is 256M */ |
| 2896 | aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | (5 - 2)); |
| 2897 | aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE); |
| 2898 | aub_out(bufmgr_gem, 0); /* subtype */ |
| 2899 | aub_out(bufmgr_gem, 0); /* offset */ |
| 2900 | aub_out(bufmgr_gem, gtt_size); /* size */ |
| 2901 | for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) { |
| 2902 | aub_out(bufmgr_gem, entry); |
| 2903 | } |
| 2904 | } |
| 2905 | |
Ben Widawsky | f7210fa | 2012-01-13 11:31:52 -0800 | [diff] [blame] | 2906 | drm_intel_context * |
| 2907 | drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr) |
| 2908 | { |
| 2909 | drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; |
| 2910 | struct drm_i915_gem_context_create create; |
Ben Widawsky | f7210fa | 2012-01-13 11:31:52 -0800 | [diff] [blame] | 2911 | drm_intel_context *context = NULL; |
Damien Lespiau | c10b08d | 2012-07-26 17:50:09 +0100 | [diff] [blame^] | 2912 | int ret; |
Ben Widawsky | f7210fa | 2012-01-13 11:31:52 -0800 | [diff] [blame] | 2913 | |
| 2914 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create); |
| 2915 | if (ret != 0) { |
Kenneth Graunke | 992e2af | 2012-07-12 13:41:11 -0700 | [diff] [blame] | 2916 | DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", |
| 2917 | strerror(errno)); |
Ben Widawsky | f7210fa | 2012-01-13 11:31:52 -0800 | [diff] [blame] | 2918 | return NULL; |
| 2919 | } |
| 2920 | |
| 2921 | context = calloc(1, sizeof(*context)); |
| 2922 | context->ctx_id = create.ctx_id; |
| 2923 | context->bufmgr = bufmgr; |
| 2924 | |
| 2925 | return context; |
| 2926 | } |
| 2927 | |
| 2928 | void |
| 2929 | drm_intel_gem_context_destroy(drm_intel_context *ctx) |
| 2930 | { |
| 2931 | drm_intel_bufmgr_gem *bufmgr_gem; |
| 2932 | struct drm_i915_gem_context_destroy destroy; |
| 2933 | int ret; |
| 2934 | |
| 2935 | if (ctx == NULL) |
| 2936 | return; |
| 2937 | |
| 2938 | bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr; |
| 2939 | destroy.ctx_id = ctx->ctx_id; |
| 2940 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, |
| 2941 | &destroy); |
| 2942 | if (ret != 0) |
| 2943 | fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n", |
| 2944 | strerror(errno)); |
| 2945 | |
| 2946 | free(ctx); |
| 2947 | } |
| 2948 | |
| 2949 | |
Eric Anholt | 4db16a9 | 2011-10-11 15:59:03 -0700 | [diff] [blame] | 2950 | /** |
Paul Berry | da02f72 | 2012-05-04 12:41:00 -0700 | [diff] [blame] | 2951 | * Annotate the given bo for use in aub dumping. |
| 2952 | * |
| 2953 | * \param annotations is an array of drm_intel_aub_annotation objects |
| 2954 | * describing the type of data in various sections of the bo. Each |
| 2955 | * element of the array specifies the type and subtype of a section of |
| 2956 | * the bo, and the past-the-end offset of that section. The elements |
| 2957 | * of \c annotations must be sorted so that ending_offset is |
| 2958 | * increasing. |
| 2959 | * |
| 2960 | * \param count is the number of elements in the \c annotations array. |
| 2961 | * If \c count is zero, then \c annotations will not be dereferenced. |
| 2962 | * |
| 2963 | * Annotations are copied into a private data structure, so caller may |
| 2964 | * re-use the memory pointed to by \c annotations after the call |
| 2965 | * returns. |
| 2966 | * |
| 2967 | * Annotations are stored for the lifetime of the bo; to reset to the |
| 2968 | * default state (no annotations), call this function with a \c count |
| 2969 | * of zero. |
| 2970 | */ |
| 2971 | void |
| 2972 | drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo, |
| 2973 | drm_intel_aub_annotation *annotations, |
| 2974 | unsigned count) |
| 2975 | { |
| 2976 | drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; |
| 2977 | unsigned size = sizeof(*annotations) * count; |
| 2978 | drm_intel_aub_annotation *new_annotations = |
| 2979 | count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL; |
| 2980 | if (new_annotations == NULL) { |
| 2981 | free(bo_gem->aub_annotations); |
| 2982 | bo_gem->aub_annotations = NULL; |
| 2983 | bo_gem->aub_annotation_count = 0; |
| 2984 | return; |
| 2985 | } |
| 2986 | memcpy(new_annotations, annotations, size); |
| 2987 | bo_gem->aub_annotations = new_annotations; |
| 2988 | bo_gem->aub_annotation_count = count; |
| 2989 | } |
| 2990 | |
| 2991 | /** |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2992 | * Initializes the GEM buffer manager, which uses the kernel to allocate, map, |
| 2993 | * and manage map buffer objections. |
| 2994 | * |
| 2995 | * \param fd File descriptor of the opened DRM device. |
| 2996 | */ |
Eric Anholt | 4b98264 | 2008-10-30 09:33:07 -0700 | [diff] [blame] | 2997 | drm_intel_bufmgr * |
| 2998 | drm_intel_bufmgr_gem_init(int fd, int batch_size) |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 2999 | { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3000 | drm_intel_bufmgr_gem *bufmgr_gem; |
| 3001 | struct drm_i915_gem_get_aperture aperture; |
| 3002 | drm_i915_getparam_t gp; |
Daniel Vetter | 630dd26 | 2011-09-22 22:20:09 +0200 | [diff] [blame] | 3003 | int ret, tmp; |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 3004 | bool exec2 = false; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 3005 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3006 | bufmgr_gem = calloc(1, sizeof(*bufmgr_gem)); |
Dave Airlie | 973d8d6 | 2010-02-02 10:57:12 +1000 | [diff] [blame] | 3007 | if (bufmgr_gem == NULL) |
| 3008 | return NULL; |
| 3009 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3010 | bufmgr_gem->fd = fd; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 3011 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3012 | if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) { |
| 3013 | free(bufmgr_gem); |
| 3014 | return NULL; |
| 3015 | } |
Eric Anholt | 6df7b07 | 2008-06-12 23:22:26 -0700 | [diff] [blame] | 3016 | |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 3017 | ret = drmIoctl(bufmgr_gem->fd, |
| 3018 | DRM_IOCTL_I915_GEM_GET_APERTURE, |
| 3019 | &aperture); |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 3020 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3021 | if (ret == 0) |
| 3022 | bufmgr_gem->gtt_size = aperture.aper_available_size; |
| 3023 | else { |
| 3024 | fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n", |
| 3025 | strerror(errno)); |
| 3026 | bufmgr_gem->gtt_size = 128 * 1024 * 1024; |
| 3027 | fprintf(stderr, "Assuming %dkB available aperture size.\n" |
| 3028 | "May lead to reduced performance or incorrect " |
| 3029 | "rendering.\n", |
| 3030 | (int)bufmgr_gem->gtt_size / 1024); |
| 3031 | } |
Eric Anholt | 0e86731 | 2008-10-21 00:10:54 -0700 | [diff] [blame] | 3032 | |
Kenneth Graunke | 6e642db | 2011-10-11 14:38:34 -0700 | [diff] [blame] | 3033 | bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem); |
Jesse Barnes | 2fa5f28 | 2009-01-23 14:13:45 -0800 | [diff] [blame] | 3034 | |
Eric Anholt | 078bc5b | 2011-12-20 13:10:36 -0800 | [diff] [blame] | 3035 | if (IS_GEN2(bufmgr_gem->pci_device)) |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 3036 | bufmgr_gem->gen = 2; |
Eric Anholt | 078bc5b | 2011-12-20 13:10:36 -0800 | [diff] [blame] | 3037 | else if (IS_GEN3(bufmgr_gem->pci_device)) |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 3038 | bufmgr_gem->gen = 3; |
Eric Anholt | 078bc5b | 2011-12-20 13:10:36 -0800 | [diff] [blame] | 3039 | else if (IS_GEN4(bufmgr_gem->pci_device)) |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 3040 | bufmgr_gem->gen = 4; |
Chad Versace | 592ac67 | 2012-01-27 10:02:16 -0800 | [diff] [blame] | 3041 | else if (IS_GEN5(bufmgr_gem->pci_device)) |
| 3042 | bufmgr_gem->gen = 5; |
| 3043 | else if (IS_GEN6(bufmgr_gem->pci_device)) |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 3044 | bufmgr_gem->gen = 6; |
Chad Versace | 592ac67 | 2012-01-27 10:02:16 -0800 | [diff] [blame] | 3045 | else if (IS_GEN7(bufmgr_gem->pci_device)) |
| 3046 | bufmgr_gem->gen = 7; |
| 3047 | else |
| 3048 | assert(0); |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 3049 | |
Eric Anholt | 078bc5b | 2011-12-20 13:10:36 -0800 | [diff] [blame] | 3050 | if (IS_GEN3(bufmgr_gem->pci_device) && |
| 3051 | bufmgr_gem->gtt_size > 256*1024*1024) { |
Daniel Vetter | 36cff1c | 2011-12-04 12:51:45 +0100 | [diff] [blame] | 3052 | /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't |
| 3053 | * be used for tiled blits. To simplify the accounting, just |
| 3054 | * substract the unmappable part (fixed to 256MB on all known |
| 3055 | * gen3 devices) if the kernel advertises it. */ |
| 3056 | bufmgr_gem->gtt_size -= 256*1024*1024; |
| 3057 | } |
| 3058 | |
Eric Anholt | 5de5b74 | 2012-03-13 16:49:53 -0700 | [diff] [blame] | 3059 | VG_CLEAR(gp); |
Daniel Vetter | 630dd26 | 2011-09-22 22:20:09 +0200 | [diff] [blame] | 3060 | gp.value = &tmp; |
| 3061 | |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 3062 | gp.param = I915_PARAM_HAS_EXECBUF2; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 3063 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 3064 | if (!ret) |
Eric Anholt | 2c2bdb3 | 2011-10-21 16:53:16 -0700 | [diff] [blame] | 3065 | exec2 = true; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 3066 | |
Zou Nan hai | 66375fd | 2010-06-02 10:07:37 +0800 | [diff] [blame] | 3067 | gp.param = I915_PARAM_HAS_BSD; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 3068 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); |
Chris Wilson | 057fab3 | 2010-10-26 11:35:11 +0100 | [diff] [blame] | 3069 | bufmgr_gem->has_bsd = ret == 0; |
| 3070 | |
| 3071 | gp.param = I915_PARAM_HAS_BLT; |
| 3072 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); |
| 3073 | bufmgr_gem->has_blt = ret == 0; |
Zou Nan hai | 66375fd | 2010-06-02 10:07:37 +0800 | [diff] [blame] | 3074 | |
Chris Wilson | 3624577 | 2010-10-29 10:49:54 +0100 | [diff] [blame] | 3075 | gp.param = I915_PARAM_HAS_RELAXED_FENCING; |
| 3076 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); |
| 3077 | bufmgr_gem->has_relaxed_fencing = ret == 0; |
| 3078 | |
Ben Widawsky | 971c080 | 2012-06-05 11:30:48 -0700 | [diff] [blame] | 3079 | gp.param = I915_PARAM_HAS_WAIT_TIMEOUT; |
| 3080 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); |
| 3081 | bufmgr_gem->has_wait_timeout = ret == 0; |
| 3082 | |
Eugeni Dodonov | 151cdcf | 2012-01-17 15:20:19 -0200 | [diff] [blame] | 3083 | gp.param = I915_PARAM_HAS_LLC; |
| 3084 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); |
Eric Anholt | 3a88848 | 2012-02-27 17:26:05 -0800 | [diff] [blame] | 3085 | if (ret != 0) { |
Eugeni Dodonov | 151cdcf | 2012-01-17 15:20:19 -0200 | [diff] [blame] | 3086 | /* Kernel does not supports HAS_LLC query, fallback to GPU |
| 3087 | * generation detection and assume that we have LLC on GEN6/7 |
| 3088 | */ |
| 3089 | bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) | |
| 3090 | IS_GEN7(bufmgr_gem->pci_device)); |
| 3091 | } else |
| 3092 | bufmgr_gem->has_llc = ret == 0; |
| 3093 | |
Eric Anholt | a1f9ea7 | 2010-03-02 08:49:36 -0800 | [diff] [blame] | 3094 | if (bufmgr_gem->gen < 4) { |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3095 | gp.param = I915_PARAM_NUM_FENCES_AVAIL; |
| 3096 | gp.value = &bufmgr_gem->available_fences; |
Chris Wilson | 6299722 | 2010-09-25 21:32:59 +0100 | [diff] [blame] | 3097 | ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3098 | if (ret) { |
| 3099 | fprintf(stderr, "get fences failed: %d [%d]\n", ret, |
| 3100 | errno); |
| 3101 | fprintf(stderr, "param: %d, val: %d\n", gp.param, |
| 3102 | *gp.value); |
| 3103 | bufmgr_gem->available_fences = 0; |
Chris Wilson | fdcde59 | 2010-02-09 08:32:54 +0000 | [diff] [blame] | 3104 | } else { |
| 3105 | /* XXX The kernel reports the total number of fences, |
| 3106 | * including any that may be pinned. |
| 3107 | * |
| 3108 | * We presume that there will be at least one pinned |
| 3109 | * fence for the scanout buffer, but there may be more |
| 3110 | * than one scanout and the user may be manually |
| 3111 | * pinning buffers. Let's move to execbuffer2 and |
| 3112 | * thereby forget the insanity of using fences... |
| 3113 | */ |
| 3114 | bufmgr_gem->available_fences -= 2; |
| 3115 | if (bufmgr_gem->available_fences < 0) |
| 3116 | bufmgr_gem->available_fences = 0; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3117 | } |
| 3118 | } |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 3119 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3120 | /* Let's go with one relocation per every 2 dwords (but round down a bit |
| 3121 | * since a power of two will mean an extra page allocation for the reloc |
| 3122 | * buffer). |
| 3123 | * |
| 3124 | * Every 4 was too few for the blender benchmark. |
| 3125 | */ |
| 3126 | bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2; |
Eric Anholt | 769b105 | 2009-10-01 19:09:26 -0700 | [diff] [blame] | 3127 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3128 | bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc; |
| 3129 | bufmgr_gem->bufmgr.bo_alloc_for_render = |
| 3130 | drm_intel_gem_bo_alloc_for_render; |
Jesse Barnes | 3a7dfcd | 2009-10-06 14:34:06 -0700 | [diff] [blame] | 3131 | bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3132 | bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference; |
| 3133 | bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference; |
| 3134 | bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map; |
| 3135 | bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap; |
| 3136 | bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata; |
| 3137 | bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata; |
| 3138 | bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering; |
| 3139 | bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 3140 | bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3141 | bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin; |
| 3142 | bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin; |
| 3143 | bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling; |
| 3144 | bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling; |
| 3145 | bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink; |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 3146 | /* Use the new one if available */ |
Zou Nan hai | 66375fd | 2010-06-02 10:07:37 +0800 | [diff] [blame] | 3147 | if (exec2) { |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 3148 | bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2; |
Albert Damen | 49447a9 | 2010-11-07 15:54:32 +0100 | [diff] [blame] | 3149 | bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2; |
Zou Nan hai | 66375fd | 2010-06-02 10:07:37 +0800 | [diff] [blame] | 3150 | } else |
Jesse Barnes | b509640 | 2009-09-15 11:02:58 -0700 | [diff] [blame] | 3151 | bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3152 | bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy; |
Chris Wilson | 83a35b6 | 2009-11-11 13:04:38 +0000 | [diff] [blame] | 3153 | bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3154 | bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy; |
| 3155 | bufmgr_gem->bufmgr.debug = 0; |
| 3156 | bufmgr_gem->bufmgr.check_aperture_space = |
| 3157 | drm_intel_gem_check_aperture_space; |
| 3158 | bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse; |
Chris Wilson | 07e7589 | 2010-05-11 08:54:06 +0100 | [diff] [blame] | 3159 | bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable; |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3160 | bufmgr_gem->bufmgr.get_pipe_from_crtc_id = |
| 3161 | drm_intel_gem_get_pipe_from_crtc_id; |
| 3162 | bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 3163 | |
Chris Wilson | 36d4939 | 2011-02-14 09:39:06 +0000 | [diff] [blame] | 3164 | DRMINITLISTHEAD(&bufmgr_gem->named); |
Eric Anholt | 0ec768e | 2010-06-04 17:09:11 -0700 | [diff] [blame] | 3165 | init_cache_buckets(bufmgr_gem); |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3166 | |
Chris Wilson | e4b60f2 | 2011-12-05 21:29:05 +0000 | [diff] [blame] | 3167 | DRMINITLISTHEAD(&bufmgr_gem->vma_cache); |
| 3168 | bufmgr_gem->vma_max = -1; /* unlimited by default */ |
| 3169 | |
Eric Anholt | d70d605 | 2009-10-06 12:40:42 -0700 | [diff] [blame] | 3170 | return &bufmgr_gem->bufmgr; |
Eric Anholt | 6a9eb08 | 2008-06-03 09:27:37 -0700 | [diff] [blame] | 3171 | } |