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Greg Clayton64c84432011-01-21 22:02:52 +00001//===-- EmulateInstruction.h ------------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Greg Clayton17f5afe2011-02-05 02:56:16 +000010#include "lldb/Core/EmulateInstruction.h"
Greg Clayton64c84432011-01-21 22:02:52 +000011
Greg Clayton888a7332011-04-26 04:39:08 +000012#include "lldb/Core/Address.h"
Greg Clayton64c84432011-01-21 22:02:52 +000013#include "lldb/Core/DataExtractor.h"
Caroline Tice080bf612011-04-05 18:46:00 +000014#include "lldb/Core/Error.h"
Greg Clayton52fd9842011-02-02 02:24:04 +000015#include "lldb/Core/PluginManager.h"
Greg Clayton061b79d2011-05-09 20:18:18 +000016#include "lldb/Core/RegisterValue.h"
17#include "lldb/Core/StreamFile.h"
Greg Clayton64c84432011-01-21 22:02:52 +000018#include "lldb/Core/StreamString.h"
Greg Claytoncd548032011-02-01 01:31:41 +000019#include "lldb/Host/Endian.h"
Greg Claytonc07d4512011-04-26 23:48:45 +000020#include "lldb/Symbol/UnwindPlan.h"
Caroline Tice080bf612011-04-05 18:46:00 +000021#include "lldb/Target/Process.h"
22#include "lldb/Target/RegisterContext.h"
Greg Clayton888a7332011-04-26 04:39:08 +000023#include "lldb/Target/Target.h"
Caroline Tice080bf612011-04-05 18:46:00 +000024#include "lldb/Target/Thread.h"
25
Greg Clayton64c84432011-01-21 22:02:52 +000026using namespace lldb;
27using namespace lldb_private;
28
Greg Clayton52fd9842011-02-02 02:24:04 +000029EmulateInstruction*
Greg Clayton888a7332011-04-26 04:39:08 +000030EmulateInstruction::FindPlugin (const ArchSpec &arch, InstructionType supported_inst_type, const char *plugin_name)
Greg Clayton52fd9842011-02-02 02:24:04 +000031{
32 EmulateInstructionCreateInstance create_callback = NULL;
33 if (plugin_name)
34 {
Greg Clayton0e191602013-05-10 21:47:16 +000035 ConstString const_plugin_name (plugin_name);
36 create_callback = PluginManager::GetEmulateInstructionCreateCallbackForPluginName (const_plugin_name);
Greg Clayton52fd9842011-02-02 02:24:04 +000037 if (create_callback)
38 {
Greg Clayton888a7332011-04-26 04:39:08 +000039 EmulateInstruction *emulate_insn_ptr = create_callback(arch, supported_inst_type);
Caroline Tice080bf612011-04-05 18:46:00 +000040 if (emulate_insn_ptr)
41 return emulate_insn_ptr;
Greg Clayton52fd9842011-02-02 02:24:04 +000042 }
43 }
44 else
45 {
46 for (uint32_t idx = 0; (create_callback = PluginManager::GetEmulateInstructionCreateCallbackAtIndex(idx)) != NULL; ++idx)
47 {
Greg Clayton888a7332011-04-26 04:39:08 +000048 EmulateInstruction *emulate_insn_ptr = create_callback(arch, supported_inst_type);
Caroline Tice080bf612011-04-05 18:46:00 +000049 if (emulate_insn_ptr)
50 return emulate_insn_ptr;
Greg Clayton52fd9842011-02-02 02:24:04 +000051 }
52 }
53 return NULL;
54}
Greg Clayton64c84432011-01-21 22:02:52 +000055
Greg Clayton888a7332011-04-26 04:39:08 +000056EmulateInstruction::EmulateInstruction (const ArchSpec &arch) :
Caroline Tice080bf612011-04-05 18:46:00 +000057 m_arch (arch),
58 m_baton (NULL),
59 m_read_mem_callback (&ReadMemoryDefault),
60 m_write_mem_callback (&WriteMemoryDefault),
61 m_read_reg_callback (&ReadRegisterDefault),
62 m_write_reg_callback (&WriteRegisterDefault),
Greg Clayton3063c952011-04-29 22:50:31 +000063 m_addr (LLDB_INVALID_ADDRESS)
Caroline Tice080bf612011-04-05 18:46:00 +000064{
65 ::memset (&m_opcode, 0, sizeof (m_opcode));
66}
67
Greg Claytonc07d4512011-04-26 23:48:45 +000068
Greg Clayton061b79d2011-05-09 20:18:18 +000069bool
70EmulateInstruction::ReadRegister (const RegisterInfo *reg_info, RegisterValue& reg_value)
71{
72 if (m_read_reg_callback)
73 return m_read_reg_callback (this, m_baton, reg_info, reg_value);
74 return false;
75}
76
77bool
78EmulateInstruction::ReadRegister (uint32_t reg_kind, uint32_t reg_num, RegisterValue& reg_value)
Greg Clayton64c84432011-01-21 22:02:52 +000079{
Greg Claytonc07d4512011-04-26 23:48:45 +000080 RegisterInfo reg_info;
81 if (GetRegisterInfo(reg_kind, reg_num, reg_info))
Greg Clayton061b79d2011-05-09 20:18:18 +000082 return ReadRegister (&reg_info, reg_value);
83 return false;
84}
85
86uint64_t
87EmulateInstruction::ReadRegisterUnsigned (uint32_t reg_kind,
88 uint32_t reg_num,
89 uint64_t fail_value,
90 bool *success_ptr)
91{
92 RegisterValue reg_value;
93 if (ReadRegister (reg_kind, reg_num, reg_value))
94 return reg_value.GetAsUInt64(fail_value, success_ptr);
Greg Claytonc07d4512011-04-26 23:48:45 +000095 if (success_ptr)
96 *success_ptr = false;
97 return fail_value;
98}
99
100uint64_t
Greg Clayton061b79d2011-05-09 20:18:18 +0000101EmulateInstruction::ReadRegisterUnsigned (const RegisterInfo *reg_info,
102 uint64_t fail_value,
103 bool *success_ptr)
Greg Claytonc07d4512011-04-26 23:48:45 +0000104{
Greg Clayton061b79d2011-05-09 20:18:18 +0000105 RegisterValue reg_value;
106 if (ReadRegister (reg_info, reg_value))
107 return reg_value.GetAsUInt64(fail_value, success_ptr);
Greg Clayton64c84432011-01-21 22:02:52 +0000108 if (success_ptr)
Greg Clayton061b79d2011-05-09 20:18:18 +0000109 *success_ptr = false;
110 return fail_value;
Greg Clayton64c84432011-01-21 22:02:52 +0000111}
112
113bool
Greg Clayton061b79d2011-05-09 20:18:18 +0000114EmulateInstruction::WriteRegister (const Context &context,
115 const RegisterInfo *reg_info,
116 const RegisterValue& reg_value)
Greg Clayton64c84432011-01-21 22:02:52 +0000117{
Greg Clayton061b79d2011-05-09 20:18:18 +0000118 if (m_write_reg_callback)
119 return m_write_reg_callback (this, m_baton, context, reg_info, reg_value);
Greg Claytonc07d4512011-04-26 23:48:45 +0000120 return false;
121}
122
123bool
Greg Clayton061b79d2011-05-09 20:18:18 +0000124EmulateInstruction::WriteRegister (const Context &context,
125 uint32_t reg_kind,
126 uint32_t reg_num,
127 const RegisterValue& reg_value)
Greg Claytonc07d4512011-04-26 23:48:45 +0000128{
Greg Clayton061b79d2011-05-09 20:18:18 +0000129 RegisterInfo reg_info;
130 if (GetRegisterInfo(reg_kind, reg_num, reg_info))
131 return WriteRegister (context, &reg_info, reg_value);
132 return false;
133}
134
135
136bool
137EmulateInstruction::WriteRegisterUnsigned (const Context &context,
138 uint32_t reg_kind,
139 uint32_t reg_num,
140 uint64_t uint_value)
141{
142
143 RegisterInfo reg_info;
144 if (GetRegisterInfo(reg_kind, reg_num, reg_info))
145 {
146 RegisterValue reg_value;
147 if (reg_value.SetUInt(uint_value, reg_info.byte_size))
148 return WriteRegister (context, &reg_info, reg_value);
149 }
150 return false;
151}
152
153bool
154EmulateInstruction::WriteRegisterUnsigned (const Context &context,
155 const RegisterInfo *reg_info,
156 uint64_t uint_value)
157{
158
159 if (reg_info)
160 {
161 RegisterValue reg_value;
162 if (reg_value.SetUInt(uint_value, reg_info->byte_size))
163 return WriteRegister (context, reg_info, reg_value);
164 }
165 return false;
166}
167
168size_t
169EmulateInstruction::ReadMemory (const Context &context,
170 lldb::addr_t addr,
171 void *dst,
172 size_t dst_len)
173{
174 if (m_read_mem_callback)
175 return m_read_mem_callback (this, m_baton, context, addr, dst, dst_len) == dst_len;
176 return false;
Greg Clayton64c84432011-01-21 22:02:52 +0000177}
178
179uint64_t
180EmulateInstruction::ReadMemoryUnsigned (const Context &context, lldb::addr_t addr, size_t byte_size, uint64_t fail_value, bool *success_ptr)
181{
182 uint64_t uval64 = 0;
183 bool success = false;
184 if (byte_size <= 8)
185 {
186 uint8_t buf[sizeof(uint64_t)];
Greg Clayton888a7332011-04-26 04:39:08 +0000187 size_t bytes_read = m_read_mem_callback (this, m_baton, context, addr, buf, byte_size);
Greg Clayton64c84432011-01-21 22:02:52 +0000188 if (bytes_read == byte_size)
189 {
Greg Clayton36da2aa2013-01-25 18:06:21 +0000190 lldb::offset_t offset = 0;
Greg Clayton888a7332011-04-26 04:39:08 +0000191 DataExtractor data (buf, byte_size, GetByteOrder(), GetAddressByteSize());
Greg Clayton64c84432011-01-21 22:02:52 +0000192 uval64 = data.GetMaxU64 (&offset, byte_size);
193 success = true;
194 }
195 }
196
197 if (success_ptr)
198 *success_ptr = success;
199
200 if (!success)
201 uval64 = fail_value;
202 return uval64;
203}
204
205
206bool
207EmulateInstruction::WriteMemoryUnsigned (const Context &context,
208 lldb::addr_t addr,
209 uint64_t uval,
210 size_t uval_byte_size)
211{
212 StreamString strm(Stream::eBinary, GetAddressByteSize(), GetByteOrder());
213 strm.PutMaxHex64 (uval, uval_byte_size);
214
Greg Clayton888a7332011-04-26 04:39:08 +0000215 size_t bytes_written = m_write_mem_callback (this, m_baton, context, addr, strm.GetData(), uval_byte_size);
Greg Clayton64c84432011-01-21 22:02:52 +0000216 if (bytes_written == uval_byte_size)
217 return true;
218 return false;
219}
Caroline Tice080bf612011-04-05 18:46:00 +0000220
Greg Clayton061b79d2011-05-09 20:18:18 +0000221bool
222EmulateInstruction::WriteMemory (const Context &context,
223 lldb::addr_t addr,
224 const void *src,
225 size_t src_len)
226{
227 if (m_write_mem_callback)
228 return m_write_mem_callback (this, m_baton, context, addr, src, src_len) == src_len;
229 return false;
230}
231
Caroline Tice080bf612011-04-05 18:46:00 +0000232
233void
234EmulateInstruction::SetBaton (void *baton)
235{
236 m_baton = baton;
237}
238
239void
Greg Clayton061b79d2011-05-09 20:18:18 +0000240EmulateInstruction::SetCallbacks (ReadMemoryCallback read_mem_callback,
241 WriteMemoryCallback write_mem_callback,
242 ReadRegisterCallback read_reg_callback,
243 WriteRegisterCallback write_reg_callback)
Caroline Tice080bf612011-04-05 18:46:00 +0000244{
245 m_read_mem_callback = read_mem_callback;
246 m_write_mem_callback = write_mem_callback;
247 m_read_reg_callback = read_reg_callback;
248 m_write_reg_callback = write_reg_callback;
249}
250
251void
Greg Clayton061b79d2011-05-09 20:18:18 +0000252EmulateInstruction::SetReadMemCallback (ReadMemoryCallback read_mem_callback)
Caroline Tice080bf612011-04-05 18:46:00 +0000253{
254 m_read_mem_callback = read_mem_callback;
255}
256
257
258void
Greg Clayton061b79d2011-05-09 20:18:18 +0000259EmulateInstruction::SetWriteMemCallback (WriteMemoryCallback write_mem_callback)
Caroline Tice080bf612011-04-05 18:46:00 +0000260{
261 m_write_mem_callback = write_mem_callback;
262}
263
264
265void
Greg Clayton061b79d2011-05-09 20:18:18 +0000266EmulateInstruction::SetReadRegCallback (ReadRegisterCallback read_reg_callback)
Caroline Tice080bf612011-04-05 18:46:00 +0000267{
268 m_read_reg_callback = read_reg_callback;
269}
270
271
272void
Greg Clayton061b79d2011-05-09 20:18:18 +0000273EmulateInstruction::SetWriteRegCallback (WriteRegisterCallback write_reg_callback)
Caroline Tice080bf612011-04-05 18:46:00 +0000274{
275 m_write_reg_callback = write_reg_callback;
276}
277
278
279
280//
281// Read & Write Memory and Registers callback functions.
282//
283
284size_t
Greg Clayton888a7332011-04-26 04:39:08 +0000285EmulateInstruction::ReadMemoryFrame (EmulateInstruction *instruction,
286 void *baton,
Caroline Ticeea69d6d2011-04-05 20:18:48 +0000287 const Context &context,
288 lldb::addr_t addr,
289 void *dst,
Greg Clayton289afcb2012-02-18 05:35:26 +0000290 size_t dst_len)
Caroline Tice080bf612011-04-05 18:46:00 +0000291{
Greg Clayton289afcb2012-02-18 05:35:26 +0000292 if (!baton || dst == NULL || dst_len == 0)
Caroline Tice080bf612011-04-05 18:46:00 +0000293 return 0;
Greg Clayton289afcb2012-02-18 05:35:26 +0000294
Caroline Ticeea69d6d2011-04-05 20:18:48 +0000295 StackFrame *frame = (StackFrame *) baton;
296
Greg Clayton289afcb2012-02-18 05:35:26 +0000297 ProcessSP process_sp (frame->CalculateProcess());
298 if (process_sp)
299 {
300 Error error;
301 return process_sp->ReadMemory (addr, dst, dst_len, error);
302 }
303 return 0;
Caroline Tice080bf612011-04-05 18:46:00 +0000304}
305
306size_t
Greg Clayton888a7332011-04-26 04:39:08 +0000307EmulateInstruction::WriteMemoryFrame (EmulateInstruction *instruction,
308 void *baton,
Caroline Ticeea69d6d2011-04-05 20:18:48 +0000309 const Context &context,
310 lldb::addr_t addr,
Greg Clayton289afcb2012-02-18 05:35:26 +0000311 const void *src,
312 size_t src_len)
Caroline Tice080bf612011-04-05 18:46:00 +0000313{
Greg Clayton289afcb2012-02-18 05:35:26 +0000314 if (!baton || src == NULL || src_len == 0)
Caroline Tice080bf612011-04-05 18:46:00 +0000315 return 0;
316
Caroline Ticeea69d6d2011-04-05 20:18:48 +0000317 StackFrame *frame = (StackFrame *) baton;
318
Greg Clayton289afcb2012-02-18 05:35:26 +0000319 ProcessSP process_sp (frame->CalculateProcess());
320 if (process_sp)
Caroline Tice080bf612011-04-05 18:46:00 +0000321 {
Greg Clayton289afcb2012-02-18 05:35:26 +0000322 Error error;
323 return process_sp->WriteMemory (addr, src, src_len, error);
Caroline Tice080bf612011-04-05 18:46:00 +0000324 }
325
326 return 0;
327}
328
329bool
Greg Clayton888a7332011-04-26 04:39:08 +0000330EmulateInstruction::ReadRegisterFrame (EmulateInstruction *instruction,
331 void *baton,
Greg Clayton061b79d2011-05-09 20:18:18 +0000332 const RegisterInfo *reg_info,
333 RegisterValue &reg_value)
Caroline Tice080bf612011-04-05 18:46:00 +0000334{
Caroline Ticeea69d6d2011-04-05 20:18:48 +0000335 if (!baton)
Caroline Tice080bf612011-04-05 18:46:00 +0000336 return false;
337
Caroline Ticeea69d6d2011-04-05 20:18:48 +0000338 StackFrame *frame = (StackFrame *) baton;
Greg Clayton061b79d2011-05-09 20:18:18 +0000339 return frame->GetRegisterContext()->ReadRegister (reg_info, reg_value);
Caroline Tice080bf612011-04-05 18:46:00 +0000340}
341
342bool
Greg Clayton888a7332011-04-26 04:39:08 +0000343EmulateInstruction::WriteRegisterFrame (EmulateInstruction *instruction,
344 void *baton,
Caroline Ticeea69d6d2011-04-05 20:18:48 +0000345 const Context &context,
Greg Clayton061b79d2011-05-09 20:18:18 +0000346 const RegisterInfo *reg_info,
347 const RegisterValue &reg_value)
Caroline Tice080bf612011-04-05 18:46:00 +0000348{
Caroline Ticeea69d6d2011-04-05 20:18:48 +0000349 if (!baton)
350 return false;
351
352 StackFrame *frame = (StackFrame *) baton;
Greg Clayton061b79d2011-05-09 20:18:18 +0000353 return frame->GetRegisterContext()->WriteRegister (reg_info, reg_value);
Caroline Tice080bf612011-04-05 18:46:00 +0000354}
355
356size_t
Greg Clayton888a7332011-04-26 04:39:08 +0000357EmulateInstruction::ReadMemoryDefault (EmulateInstruction *instruction,
358 void *baton,
Caroline Tice080bf612011-04-05 18:46:00 +0000359 const Context &context,
360 lldb::addr_t addr,
361 void *dst,
362 size_t length)
363{
Greg Clayton75906e42011-05-11 18:39:18 +0000364 StreamFile strm (stdout, false);
Daniel Malea5f35a4b2012-11-29 21:49:15 +0000365 strm.Printf (" Read from Memory (address = 0x%" PRIx64 ", length = %" PRIu64 ", context = ", addr, (uint64_t)length);
Greg Clayton75906e42011-05-11 18:39:18 +0000366 context.Dump (strm, instruction);
367 strm.EOL();
Caroline Tice080bf612011-04-05 18:46:00 +0000368 *((uint64_t *) dst) = 0xdeadbeef;
369 return length;
370}
371
372size_t
Greg Clayton888a7332011-04-26 04:39:08 +0000373EmulateInstruction::WriteMemoryDefault (EmulateInstruction *instruction,
374 void *baton,
Caroline Tice080bf612011-04-05 18:46:00 +0000375 const Context &context,
376 lldb::addr_t addr,
377 const void *dst,
378 size_t length)
379{
Greg Clayton75906e42011-05-11 18:39:18 +0000380 StreamFile strm (stdout, false);
Daniel Malea5f35a4b2012-11-29 21:49:15 +0000381 strm.Printf (" Write to Memory (address = 0x%" PRIx64 ", length = %" PRIu64 ", context = ", addr, (uint64_t)length);
Greg Clayton75906e42011-05-11 18:39:18 +0000382 context.Dump (strm, instruction);
383 strm.EOL();
Caroline Tice080bf612011-04-05 18:46:00 +0000384 return length;
385}
386
387bool
Greg Clayton888a7332011-04-26 04:39:08 +0000388EmulateInstruction::ReadRegisterDefault (EmulateInstruction *instruction,
389 void *baton,
Greg Clayton061b79d2011-05-09 20:18:18 +0000390 const RegisterInfo *reg_info,
391 RegisterValue &reg_value)
Caroline Tice080bf612011-04-05 18:46:00 +0000392{
Greg Clayton75906e42011-05-11 18:39:18 +0000393 StreamFile strm (stdout, false);
394 strm.Printf (" Read Register (%s)\n", reg_info->name);
Greg Claytonc07d4512011-04-26 23:48:45 +0000395 uint32_t reg_kind, reg_num;
396 if (GetBestRegisterKindAndNumber (reg_info, reg_kind, reg_num))
Greg Clayton061b79d2011-05-09 20:18:18 +0000397 reg_value.SetUInt64((uint64_t)reg_kind << 24 | reg_num);
Greg Claytonc07d4512011-04-26 23:48:45 +0000398 else
Greg Clayton061b79d2011-05-09 20:18:18 +0000399 reg_value.SetUInt64(0);
Greg Claytonc07d4512011-04-26 23:48:45 +0000400
Caroline Tice080bf612011-04-05 18:46:00 +0000401 return true;
402}
403
404bool
Greg Clayton888a7332011-04-26 04:39:08 +0000405EmulateInstruction::WriteRegisterDefault (EmulateInstruction *instruction,
406 void *baton,
Caroline Tice080bf612011-04-05 18:46:00 +0000407 const Context &context,
Greg Clayton061b79d2011-05-09 20:18:18 +0000408 const RegisterInfo *reg_info,
409 const RegisterValue &reg_value)
Caroline Tice080bf612011-04-05 18:46:00 +0000410{
Greg Clayton061b79d2011-05-09 20:18:18 +0000411 StreamFile strm (stdout, false);
412 strm.Printf (" Write to Register (name = %s, value = " , reg_info->name);
Greg Clayton997b1e82011-05-15 04:12:07 +0000413 reg_value.Dump(&strm, reg_info, false, false, eFormatDefault);
Greg Clayton061b79d2011-05-09 20:18:18 +0000414 strm.PutCString (", context = ");
Greg Clayton75906e42011-05-11 18:39:18 +0000415 context.Dump (strm, instruction);
416 strm.EOL();
Caroline Tice080bf612011-04-05 18:46:00 +0000417 return true;
418}
419
420void
Greg Clayton75906e42011-05-11 18:39:18 +0000421EmulateInstruction::Context::Dump (Stream &strm,
Greg Claytonc07d4512011-04-26 23:48:45 +0000422 EmulateInstruction *instruction) const
Caroline Tice080bf612011-04-05 18:46:00 +0000423{
Greg Claytonc07d4512011-04-26 23:48:45 +0000424 switch (type)
Caroline Tice080bf612011-04-05 18:46:00 +0000425 {
426 case eContextReadOpcode:
Greg Clayton75906e42011-05-11 18:39:18 +0000427 strm.PutCString ("reading opcode");
Caroline Tice080bf612011-04-05 18:46:00 +0000428 break;
429
430 case eContextImmediate:
Greg Clayton75906e42011-05-11 18:39:18 +0000431 strm.PutCString ("immediate");
Caroline Tice080bf612011-04-05 18:46:00 +0000432 break;
433
434 case eContextPushRegisterOnStack:
Greg Clayton75906e42011-05-11 18:39:18 +0000435 strm.PutCString ("push register");
Caroline Tice080bf612011-04-05 18:46:00 +0000436 break;
437
438 case eContextPopRegisterOffStack:
Greg Clayton75906e42011-05-11 18:39:18 +0000439 strm.PutCString ("pop register");
Caroline Tice080bf612011-04-05 18:46:00 +0000440 break;
441
442 case eContextAdjustStackPointer:
Greg Clayton75906e42011-05-11 18:39:18 +0000443 strm.PutCString ("adjust sp");
Caroline Tice080bf612011-04-05 18:46:00 +0000444 break;
445
Greg Clayton65611552011-06-04 01:26:29 +0000446 case eContextSetFramePointer:
447 strm.PutCString ("set frame pointer");
448 break;
449
Caroline Tice080bf612011-04-05 18:46:00 +0000450 case eContextAdjustBaseRegister:
Greg Clayton75906e42011-05-11 18:39:18 +0000451 strm.PutCString ("adjusting (writing value back to) a base register");
Caroline Tice080bf612011-04-05 18:46:00 +0000452 break;
453
454 case eContextRegisterPlusOffset:
Greg Clayton75906e42011-05-11 18:39:18 +0000455 strm.PutCString ("register + offset");
Caroline Tice080bf612011-04-05 18:46:00 +0000456 break;
457
458 case eContextRegisterStore:
Greg Clayton75906e42011-05-11 18:39:18 +0000459 strm.PutCString ("store register");
Caroline Tice080bf612011-04-05 18:46:00 +0000460 break;
461
462 case eContextRegisterLoad:
Greg Clayton75906e42011-05-11 18:39:18 +0000463 strm.PutCString ("load register");
Caroline Tice080bf612011-04-05 18:46:00 +0000464 break;
465
466 case eContextRelativeBranchImmediate:
Greg Clayton75906e42011-05-11 18:39:18 +0000467 strm.PutCString ("relative branch immediate");
Caroline Tice080bf612011-04-05 18:46:00 +0000468 break;
469
470 case eContextAbsoluteBranchRegister:
Greg Clayton75906e42011-05-11 18:39:18 +0000471 strm.PutCString ("absolute branch register");
Caroline Tice080bf612011-04-05 18:46:00 +0000472 break;
473
474 case eContextSupervisorCall:
Greg Clayton75906e42011-05-11 18:39:18 +0000475 strm.PutCString ("supervisor call");
Caroline Tice080bf612011-04-05 18:46:00 +0000476 break;
477
478 case eContextTableBranchReadMemory:
Greg Clayton75906e42011-05-11 18:39:18 +0000479 strm.PutCString ("table branch read memory");
Caroline Tice080bf612011-04-05 18:46:00 +0000480 break;
481
482 case eContextWriteRegisterRandomBits:
Greg Clayton75906e42011-05-11 18:39:18 +0000483 strm.PutCString ("write random bits to a register");
Caroline Tice080bf612011-04-05 18:46:00 +0000484 break;
485
486 case eContextWriteMemoryRandomBits:
Greg Clayton75906e42011-05-11 18:39:18 +0000487 strm.PutCString ("write random bits to a memory address");
Caroline Tice080bf612011-04-05 18:46:00 +0000488 break;
489
Greg Claytonc07d4512011-04-26 23:48:45 +0000490 case eContextArithmetic:
Greg Clayton75906e42011-05-11 18:39:18 +0000491 strm.PutCString ("arithmetic");
Caroline Tice080bf612011-04-05 18:46:00 +0000492 break;
493
494 case eContextReturnFromException:
Greg Clayton75906e42011-05-11 18:39:18 +0000495 strm.PutCString ("return from exception");
Caroline Tice080bf612011-04-05 18:46:00 +0000496 break;
497
498 default:
Greg Clayton75906e42011-05-11 18:39:18 +0000499 strm.PutCString ("unrecognized context.");
Caroline Tice080bf612011-04-05 18:46:00 +0000500 break;
501 }
502
Greg Claytonc07d4512011-04-26 23:48:45 +0000503 switch (info_type)
Caroline Tice080bf612011-04-05 18:46:00 +0000504 {
Greg Claytonc07d4512011-04-26 23:48:45 +0000505 case eInfoTypeRegisterPlusOffset:
Caroline Tice080bf612011-04-05 18:46:00 +0000506 {
Daniel Malea5f35a4b2012-11-29 21:49:15 +0000507 strm.Printf (" (reg_plus_offset = %s%+" PRId64 ")",
Greg Clayton75906e42011-05-11 18:39:18 +0000508 info.RegisterPlusOffset.reg.name,
509 info.RegisterPlusOffset.signed_offset);
Caroline Tice080bf612011-04-05 18:46:00 +0000510 }
Greg Claytonc07d4512011-04-26 23:48:45 +0000511 break;
512
513 case eInfoTypeRegisterPlusIndirectOffset:
Caroline Tice080bf612011-04-05 18:46:00 +0000514 {
Greg Clayton75906e42011-05-11 18:39:18 +0000515 strm.Printf (" (reg_plus_reg = %s + %s)",
516 info.RegisterPlusIndirectOffset.base_reg.name,
517 info.RegisterPlusIndirectOffset.offset_reg.name);
Caroline Tice080bf612011-04-05 18:46:00 +0000518 }
Greg Claytonc07d4512011-04-26 23:48:45 +0000519 break;
520
521 case eInfoTypeRegisterToRegisterPlusOffset:
Caroline Tice080bf612011-04-05 18:46:00 +0000522 {
Daniel Malea5f35a4b2012-11-29 21:49:15 +0000523 strm.Printf (" (base_and_imm_offset = %s%+" PRId64 ", data_reg = %s)",
Greg Clayton75906e42011-05-11 18:39:18 +0000524 info.RegisterToRegisterPlusOffset.base_reg.name,
525 info.RegisterToRegisterPlusOffset.offset,
526 info.RegisterToRegisterPlusOffset.data_reg.name);
Caroline Tice080bf612011-04-05 18:46:00 +0000527 }
Greg Claytonc07d4512011-04-26 23:48:45 +0000528 break;
529
530 case eInfoTypeRegisterToRegisterPlusIndirectOffset:
Caroline Tice080bf612011-04-05 18:46:00 +0000531 {
Greg Clayton75906e42011-05-11 18:39:18 +0000532 strm.Printf (" (base_and_reg_offset = %s + %s, data_reg = %s)",
533 info.RegisterToRegisterPlusIndirectOffset.base_reg.name,
534 info.RegisterToRegisterPlusIndirectOffset.offset_reg.name,
535 info.RegisterToRegisterPlusIndirectOffset.data_reg.name);
Caroline Tice080bf612011-04-05 18:46:00 +0000536 }
Greg Claytonc07d4512011-04-26 23:48:45 +0000537 break;
538
539 case eInfoTypeRegisterRegisterOperands:
540 {
Greg Clayton75906e42011-05-11 18:39:18 +0000541 strm.Printf (" (register to register binary op: %s and %s)",
542 info.RegisterRegisterOperands.operand1.name,
543 info.RegisterRegisterOperands.operand2.name);
Greg Claytonc07d4512011-04-26 23:48:45 +0000544 }
545 break;
546
547 case eInfoTypeOffset:
Daniel Malea5f35a4b2012-11-29 21:49:15 +0000548 strm.Printf (" (signed_offset = %+" PRId64 ")", info.signed_offset);
Greg Claytonc07d4512011-04-26 23:48:45 +0000549 break;
Caroline Tice080bf612011-04-05 18:46:00 +0000550
Greg Claytonc07d4512011-04-26 23:48:45 +0000551 case eInfoTypeRegister:
Greg Clayton75906e42011-05-11 18:39:18 +0000552 strm.Printf (" (reg = %s)", info.reg.name);
Greg Claytonc07d4512011-04-26 23:48:45 +0000553 break;
554
555 case eInfoTypeImmediate:
Daniel Malea5f35a4b2012-11-29 21:49:15 +0000556 strm.Printf (" (unsigned_immediate = %" PRIu64 " (0x%16.16" PRIx64 "))",
Greg Clayton75906e42011-05-11 18:39:18 +0000557 info.unsigned_immediate,
558 info.unsigned_immediate);
Greg Claytonc07d4512011-04-26 23:48:45 +0000559 break;
Caroline Tice080bf612011-04-05 18:46:00 +0000560
Greg Claytonc07d4512011-04-26 23:48:45 +0000561 case eInfoTypeImmediateSigned:
Daniel Malea5f35a4b2012-11-29 21:49:15 +0000562 strm.Printf (" (signed_immediate = %+" PRId64 " (0x%16.16" PRIx64 "))",
Greg Clayton75906e42011-05-11 18:39:18 +0000563 info.signed_immediate,
564 info.signed_immediate);
Greg Claytonc07d4512011-04-26 23:48:45 +0000565 break;
566
567 case eInfoTypeAddress:
Daniel Malea5f35a4b2012-11-29 21:49:15 +0000568 strm.Printf (" (address = 0x%" PRIx64 ")", info.address);
Greg Claytonc07d4512011-04-26 23:48:45 +0000569 break;
570
571 case eInfoTypeISAAndImmediate:
Greg Clayton75906e42011-05-11 18:39:18 +0000572 strm.Printf (" (isa = %u, unsigned_immediate = %u (0x%8.8x))",
573 info.ISAAndImmediate.isa,
574 info.ISAAndImmediate.unsigned_data32,
575 info.ISAAndImmediate.unsigned_data32);
Greg Claytonc07d4512011-04-26 23:48:45 +0000576 break;
577
578 case eInfoTypeISAAndImmediateSigned:
Greg Clayton75906e42011-05-11 18:39:18 +0000579 strm.Printf (" (isa = %u, signed_immediate = %i (0x%8.8x))",
580 info.ISAAndImmediateSigned.isa,
581 info.ISAAndImmediateSigned.signed_data32,
582 info.ISAAndImmediateSigned.signed_data32);
Greg Claytonc07d4512011-04-26 23:48:45 +0000583 break;
584
585 case eInfoTypeISA:
Greg Clayton75906e42011-05-11 18:39:18 +0000586 strm.Printf (" (isa = %u)", info.isa);
Greg Claytonc07d4512011-04-26 23:48:45 +0000587 break;
588
589 case eInfoTypeNoArgs:
Greg Claytonc07d4512011-04-26 23:48:45 +0000590 break;
Caroline Tice080bf612011-04-05 18:46:00 +0000591 }
592}
593
Greg Clayton888a7332011-04-26 04:39:08 +0000594bool
595EmulateInstruction::SetInstruction (const Opcode &opcode, const Address &inst_addr, Target *target)
Caroline Tice080bf612011-04-05 18:46:00 +0000596{
Greg Clayton888a7332011-04-26 04:39:08 +0000597 m_opcode = opcode;
Greg Clayton3063c952011-04-29 22:50:31 +0000598 m_addr = LLDB_INVALID_ADDRESS;
Greg Clayton888a7332011-04-26 04:39:08 +0000599 if (inst_addr.IsValid())
Caroline Tice080bf612011-04-05 18:46:00 +0000600 {
Greg Clayton888a7332011-04-26 04:39:08 +0000601 if (target)
Greg Clayton3063c952011-04-29 22:50:31 +0000602 m_addr = inst_addr.GetLoadAddress (target);
603 if (m_addr == LLDB_INVALID_ADDRESS)
604 m_addr = inst_addr.GetFileAddress ();
Caroline Tice080bf612011-04-05 18:46:00 +0000605 }
Greg Clayton888a7332011-04-26 04:39:08 +0000606 return true;
Caroline Tice080bf612011-04-05 18:46:00 +0000607}
608
Greg Claytonc07d4512011-04-26 23:48:45 +0000609bool
Greg Clayton061b79d2011-05-09 20:18:18 +0000610EmulateInstruction::GetBestRegisterKindAndNumber (const RegisterInfo *reg_info,
Greg Claytonc07d4512011-04-26 23:48:45 +0000611 uint32_t &reg_kind,
612 uint32_t &reg_num)
Greg Clayton888a7332011-04-26 04:39:08 +0000613{
Greg Claytonc07d4512011-04-26 23:48:45 +0000614 // Generic and DWARF should be the two most popular register kinds when
615 // emulating instructions since they are the most platform agnostic...
Greg Clayton061b79d2011-05-09 20:18:18 +0000616 reg_num = reg_info->kinds[eRegisterKindGeneric];
Greg Claytonc07d4512011-04-26 23:48:45 +0000617 if (reg_num != LLDB_INVALID_REGNUM)
Greg Clayton888a7332011-04-26 04:39:08 +0000618 {
Greg Claytonc07d4512011-04-26 23:48:45 +0000619 reg_kind = eRegisterKindGeneric;
620 return true;
Greg Clayton888a7332011-04-26 04:39:08 +0000621 }
Greg Clayton888a7332011-04-26 04:39:08 +0000622
Greg Clayton061b79d2011-05-09 20:18:18 +0000623 reg_num = reg_info->kinds[eRegisterKindDWARF];
Greg Claytonc07d4512011-04-26 23:48:45 +0000624 if (reg_num != LLDB_INVALID_REGNUM)
Greg Clayton888a7332011-04-26 04:39:08 +0000625 {
Greg Claytonc07d4512011-04-26 23:48:45 +0000626 reg_kind = eRegisterKindDWARF;
627 return true;
628 }
Greg Clayton888a7332011-04-26 04:39:08 +0000629
Greg Clayton061b79d2011-05-09 20:18:18 +0000630 reg_num = reg_info->kinds[eRegisterKindLLDB];
Greg Claytonc07d4512011-04-26 23:48:45 +0000631 if (reg_num != LLDB_INVALID_REGNUM)
632 {
633 reg_kind = eRegisterKindLLDB;
634 return true;
Greg Clayton888a7332011-04-26 04:39:08 +0000635 }
Greg Claytonc07d4512011-04-26 23:48:45 +0000636
Greg Clayton061b79d2011-05-09 20:18:18 +0000637 reg_num = reg_info->kinds[eRegisterKindGCC];
Greg Claytonc07d4512011-04-26 23:48:45 +0000638 if (reg_num != LLDB_INVALID_REGNUM)
639 {
640 reg_kind = eRegisterKindGCC;
641 return true;
642 }
643
Greg Clayton061b79d2011-05-09 20:18:18 +0000644 reg_num = reg_info->kinds[eRegisterKindGDB];
Greg Claytonc07d4512011-04-26 23:48:45 +0000645 if (reg_num != LLDB_INVALID_REGNUM)
646 {
647 reg_kind = eRegisterKindGDB;
648 return true;
649 }
650 return false;
651}
652
653uint32_t
654EmulateInstruction::GetInternalRegisterNumber (RegisterContext *reg_ctx, const RegisterInfo &reg_info)
655{
656 uint32_t reg_kind, reg_num;
Greg Clayton061b79d2011-05-09 20:18:18 +0000657 if (reg_ctx && GetBestRegisterKindAndNumber (&reg_info, reg_kind, reg_num))
Greg Claytonc07d4512011-04-26 23:48:45 +0000658 return reg_ctx->ConvertRegisterKindToRegisterNumber (reg_kind, reg_num);
659 return LLDB_INVALID_REGNUM;
660}
661
662
663bool
664EmulateInstruction::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan)
665{
666 unwind_plan.Clear();
667 return false;
Greg Clayton888a7332011-04-26 04:39:08 +0000668}
669
Caroline Tice080bf612011-04-05 18:46:00 +0000670