Misha Brukman | 2a8350a | 2005-02-05 02:24:26 +0000 | [diff] [blame] | 1 | //===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===// |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | //3.3: |
| 14 | //Memory |
| 15 | //Branch |
| 16 | //Operate |
| 17 | //Floating-point |
| 18 | //PALcode |
| 19 | |
Andrew Lenharth | 4907d22 | 2005-10-20 00:28:31 +0000 | [diff] [blame] | 20 | def u8imm : Operand<i64>; |
| 21 | def s14imm : Operand<i64>; |
| 22 | def s16imm : Operand<i64>; |
| 23 | def s21imm : Operand<i64>; |
Andrew Lenharth | f3f951a | 2005-07-22 20:50:29 +0000 | [diff] [blame] | 24 | def s64imm : Operand<i64>; |
Andrew Lenharth | f81173f | 2006-10-31 16:49:55 +0000 | [diff] [blame] | 25 | def u64imm : Operand<i64>; |
Andrew Lenharth | f3f951a | 2005-07-22 20:50:29 +0000 | [diff] [blame] | 26 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 27 | //===----------------------------------------------------------------------===// |
| 28 | // Instruction format superclass |
| 29 | //===----------------------------------------------------------------------===// |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 30 | // Alpha instruction baseline |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 31 | class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction { |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 32 | field bits<32> Inst; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 33 | let Namespace = "Alpha"; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 34 | let AsmString = asmstr; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 35 | let Inst{31-26} = op; |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 36 | let Itinerary = itin; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 37 | } |
| 38 | |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 39 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 40 | //3.3.1 |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 41 | class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 42 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | 9fa4d4c | 2005-12-24 03:41:56 +0000 | [diff] [blame] | 43 | let Pattern = pattern; |
Andrew Lenharth | b671860 | 2005-12-24 07:34:33 +0000 | [diff] [blame] | 44 | let isStore = store; |
| 45 | let isLoad = load; |
Andrew Lenharth | cd1544e | 2006-01-26 03:22:07 +0000 | [diff] [blame] | 46 | let Defs = [R28]; //We may use this for frame index calculations, so reserve it here |
Andrew Lenharth | 9fa4d4c | 2005-12-24 03:41:56 +0000 | [diff] [blame] | 47 | |
| 48 | bits<5> Ra; |
| 49 | bits<16> disp; |
| 50 | bits<5> Rb; |
| 51 | |
| 52 | let Inst{25-21} = Ra; |
| 53 | let Inst{20-16} = Rb; |
| 54 | let Inst{15-0} = disp; |
| 55 | } |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 56 | class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin> |
| 57 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | 51b8d54 | 2005-11-11 16:47:30 +0000 | [diff] [blame] | 58 | bits<5> Ra; |
Andrew Lenharth | 51b8d54 | 2005-11-11 16:47:30 +0000 | [diff] [blame] | 59 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 60 | let OutOperandList = (ops GPRC:$RA); |
| 61 | let InOperandList = (ops); |
Andrew Lenharth | 51b8d54 | 2005-11-11 16:47:30 +0000 | [diff] [blame] | 62 | let Inst{25-21} = Ra; |
Andrew Lenharth | 739027e | 2006-01-16 21:22:38 +0000 | [diff] [blame] | 63 | let Inst{20-16} = 0; |
Andrew Lenharth | 51b8d54 | 2005-11-11 16:47:30 +0000 | [diff] [blame] | 64 | let Inst{15-0} = fc; |
| 65 | } |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 66 | |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 67 | class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin> |
| 68 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | f3f951a | 2005-07-22 20:50:29 +0000 | [diff] [blame] | 69 | bits<5> Ra; |
| 70 | bits<5> Rb; |
| 71 | bits<14> disp; |
| 72 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 73 | let OutOperandList = (ops); |
| 74 | let InOperandList = OL; |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 75 | |
Andrew Lenharth | f3f951a | 2005-07-22 20:50:29 +0000 | [diff] [blame] | 76 | let Inst{25-21} = Ra; |
| 77 | let Inst{20-16} = Rb; |
| 78 | let Inst{15-14} = TB; |
| 79 | let Inst{13-0} = disp; |
| 80 | } |
Andrew Lenharth | f2b806a | 2006-06-12 18:09:24 +0000 | [diff] [blame] | 81 | class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 82 | : InstAlpha<opcode, asmstr, itin> { |
| 83 | let Pattern=pattern; |
| 84 | bits<5> Ra; |
| 85 | bits<5> Rb; |
| 86 | bits<14> disp; |
| 87 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 88 | let OutOperandList = (ops); |
| 89 | let InOperandList = OL; |
Andrew Lenharth | f2b806a | 2006-06-12 18:09:24 +0000 | [diff] [blame] | 90 | |
| 91 | let Inst{25-21} = Ra; |
| 92 | let Inst{20-16} = Rb; |
| 93 | let Inst{15-14} = TB; |
| 94 | let Inst{13-0} = disp; |
| 95 | } |
Andrew Lenharth | f3f951a | 2005-07-22 20:50:29 +0000 | [diff] [blame] | 96 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 97 | //3.3.2 |
Andrew Lenharth | eececba | 2005-12-25 17:36:48 +0000 | [diff] [blame] | 98 | def target : Operand<OtherVT> {} |
Andrew Lenharth | f81173f | 2006-10-31 16:49:55 +0000 | [diff] [blame] | 99 | |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 100 | let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { |
Andrew Lenharth | f81173f | 2006-10-31 16:49:55 +0000 | [diff] [blame] | 101 | class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> |
| 102 | : InstAlpha<opcode, asmstr, itin> { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 103 | let OutOperandList = (ops); |
| 104 | let InOperandList = OL; |
Andrew Lenharth | f81173f | 2006-10-31 16:49:55 +0000 | [diff] [blame] | 105 | bits<64> Opc; //dummy |
| 106 | bits<5> Ra; |
| 107 | bits<21> disp; |
| 108 | |
| 109 | let Inst{25-21} = Ra; |
| 110 | let Inst{20-0} = disp; |
| 111 | } |
| 112 | } |
| 113 | |
Andrew Lenharth | cfb2815 | 2005-12-06 20:40:34 +0000 | [diff] [blame] | 114 | let isBranch = 1, isTerminator = 1 in |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 115 | class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 116 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | eececba | 2005-12-25 17:36:48 +0000 | [diff] [blame] | 117 | let Pattern = pattern; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 118 | let OutOperandList = (ops); |
| 119 | let InOperandList = (ops target:$DISP); |
Andrew Lenharth | eececba | 2005-12-25 17:36:48 +0000 | [diff] [blame] | 120 | bits<5> Ra; |
Andrew Lenharth | 756fbeb | 2005-10-22 22:06:58 +0000 | [diff] [blame] | 121 | bits<21> disp; |
| 122 | |
| 123 | let Inst{25-21} = Ra; |
| 124 | let Inst{20-0} = disp; |
| 125 | } |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 126 | |
| 127 | //3.3.3 |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 128 | class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 129 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | 4907d22 | 2005-10-20 00:28:31 +0000 | [diff] [blame] | 130 | let Pattern = pattern; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 131 | let OutOperandList = (outs GPRC:$RC); |
| 132 | let InOperandList = (ins GPRC:$RA, GPRC:$RB); |
Andrew Lenharth | 4907d22 | 2005-10-20 00:28:31 +0000 | [diff] [blame] | 133 | |
Andrew Lenharth | f3f951a | 2005-07-22 20:50:29 +0000 | [diff] [blame] | 134 | bits<5> Rc; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 135 | bits<5> Ra; |
| 136 | bits<5> Rb; |
Andrew Lenharth | f3f951a | 2005-07-22 20:50:29 +0000 | [diff] [blame] | 137 | bits<7> Function = fun; |
| 138 | |
| 139 | let Inst{25-21} = Ra; |
| 140 | let Inst{20-16} = Rb; |
| 141 | let Inst{15-13} = 0; |
| 142 | let Inst{12} = 0; |
| 143 | let Inst{11-5} = Function; |
| 144 | let Inst{4-0} = Rc; |
| 145 | } |
| 146 | |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 147 | class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 148 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | 964b6aa | 2005-10-20 19:39:24 +0000 | [diff] [blame] | 149 | let Pattern = pattern; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 150 | let OutOperandList = (outs GPRC:$RC); |
| 151 | let InOperandList = (ins GPRC:$RB); |
Andrew Lenharth | 964b6aa | 2005-10-20 19:39:24 +0000 | [diff] [blame] | 152 | |
| 153 | bits<5> Rc; |
| 154 | bits<5> Rb; |
| 155 | bits<7> Function = fun; |
| 156 | |
Andrew Lenharth | 756fbeb | 2005-10-22 22:06:58 +0000 | [diff] [blame] | 157 | let Inst{25-21} = 31; |
Andrew Lenharth | 964b6aa | 2005-10-20 19:39:24 +0000 | [diff] [blame] | 158 | let Inst{20-16} = Rb; |
| 159 | let Inst{15-13} = 0; |
| 160 | let Inst{12} = 0; |
| 161 | let Inst{11-5} = Function; |
| 162 | let Inst{4-0} = Rc; |
| 163 | } |
| 164 | |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 165 | class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 166 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | 5de36f9 | 2005-12-05 23:19:44 +0000 | [diff] [blame] | 167 | let Pattern = pattern; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 168 | let OutOperandList = (outs GPRC:$RDEST); |
| 169 | let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE); |
Andrew Lenharth | 15b7823 | 2007-04-17 04:07:59 +0000 | [diff] [blame] | 170 | let Constraints = "$RFALSE = $RDEST"; |
| 171 | let DisableEncoding = "$RFALSE"; |
Andrew Lenharth | 5de36f9 | 2005-12-05 23:19:44 +0000 | [diff] [blame] | 172 | |
| 173 | bits<5> Rc; |
Andrew Lenharth | 5de36f9 | 2005-12-05 23:19:44 +0000 | [diff] [blame] | 174 | bits<5> Ra; |
Andrew Lenharth | 15b7823 | 2007-04-17 04:07:59 +0000 | [diff] [blame] | 175 | bits<5> Rb; |
Andrew Lenharth | 5de36f9 | 2005-12-05 23:19:44 +0000 | [diff] [blame] | 176 | bits<7> Function = fun; |
| 177 | |
Andrew Lenharth | 15b7823 | 2007-04-17 04:07:59 +0000 | [diff] [blame] | 178 | // let isTwoAddress = 1; |
Andrew Lenharth | 5de36f9 | 2005-12-05 23:19:44 +0000 | [diff] [blame] | 179 | let Inst{25-21} = Ra; |
| 180 | let Inst{20-16} = Rb; |
| 181 | let Inst{15-13} = 0; |
| 182 | let Inst{12} = 0; |
| 183 | let Inst{11-5} = Function; |
| 184 | let Inst{4-0} = Rc; |
| 185 | } |
| 186 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 187 | |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 188 | class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 189 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | 4907d22 | 2005-10-20 00:28:31 +0000 | [diff] [blame] | 190 | let Pattern = pattern; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 191 | let OutOperandList = (outs GPRC:$RC); |
| 192 | let InOperandList = (ins GPRC:$RA, u8imm:$L); |
Andrew Lenharth | 4907d22 | 2005-10-20 00:28:31 +0000 | [diff] [blame] | 193 | |
Andrew Lenharth | f3f951a | 2005-07-22 20:50:29 +0000 | [diff] [blame] | 194 | bits<5> Rc; |
| 195 | bits<5> Ra; |
| 196 | bits<8> LIT; |
| 197 | bits<7> Function = fun; |
| 198 | |
| 199 | let Inst{25-21} = Ra; |
| 200 | let Inst{20-13} = LIT; |
| 201 | let Inst{12} = 1; |
| 202 | let Inst{11-5} = Function; |
| 203 | let Inst{4-0} = Rc; |
| 204 | } |
| 205 | |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 206 | class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 207 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | 77f0885 | 2006-02-01 19:37:33 +0000 | [diff] [blame] | 208 | let Pattern = pattern; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 209 | let OutOperandList = (outs GPRC:$RDEST); |
| 210 | let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE); |
Andrew Lenharth | 15b7823 | 2007-04-17 04:07:59 +0000 | [diff] [blame] | 211 | let Constraints = "$RFALSE = $RDEST"; |
| 212 | let DisableEncoding = "$RFALSE"; |
| 213 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 214 | bits<5> Rc; |
Andrew Lenharth | 1f347a3 | 2005-10-20 23:58:36 +0000 | [diff] [blame] | 215 | bits<5> Ra; |
Andrew Lenharth | 15b7823 | 2007-04-17 04:07:59 +0000 | [diff] [blame] | 216 | bits<8> LIT; |
Andrew Lenharth | 1f347a3 | 2005-10-20 23:58:36 +0000 | [diff] [blame] | 217 | bits<7> Function = fun; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 218 | |
Andrew Lenharth | 15b7823 | 2007-04-17 04:07:59 +0000 | [diff] [blame] | 219 | // let isTwoAddress = 1; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 220 | let Inst{25-21} = Ra; |
| 221 | let Inst{20-13} = LIT; |
| 222 | let Inst{12} = 1; |
| 223 | let Inst{11-5} = Function; |
| 224 | let Inst{4-0} = Rc; |
| 225 | } |
| 226 | |
| 227 | //3.3.4 |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 228 | class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 229 | : InstAlpha<opcode, asmstr, itin> { |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 230 | let Pattern = pattern; |
| 231 | |
Andrew Lenharth | 98169be | 2005-07-28 18:14:47 +0000 | [diff] [blame] | 232 | bits<5> Fc; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 233 | bits<5> Fa; |
| 234 | bits<5> Fb; |
Andrew Lenharth | 3e98fde | 2005-01-26 21:54:09 +0000 | [diff] [blame] | 235 | bits<11> Function = fun; |
Andrew Lenharth | 98169be | 2005-07-28 18:14:47 +0000 | [diff] [blame] | 236 | |
| 237 | let Inst{25-21} = Fa; |
| 238 | let Inst{20-16} = Fb; |
| 239 | let Inst{15-5} = Function; |
| 240 | let Inst{4-0} = Fc; |
| 241 | } |
| 242 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 243 | //3.3.5 |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 244 | class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> |
| 245 | : InstAlpha<opcode, asmstr, itin> { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 246 | let OutOperandList = (ops); |
| 247 | let InOperandList = OL; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 248 | bits<26> Function; |
| 249 | |
| 250 | let Inst{25-0} = Function; |
| 251 | } |
| 252 | |
| 253 | |
| 254 | // Pseudo instructions. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 255 | class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin> |
Andrew Lenharth | 017c556 | 2006-03-09 17:16:45 +0000 | [diff] [blame] | 256 | : InstAlpha<0, nm, itin> { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 257 | let OutOperandList = OOL; |
| 258 | let InOperandList = IOL; |
Andrew Lenharth | 50b3784 | 2005-11-22 04:20:06 +0000 | [diff] [blame] | 259 | let Pattern = pattern; |
| 260 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 261 | } |