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Misha Brukman2a8350a2005-02-05 02:24:26 +00001//===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
Andrew Lenharth304d0f32005-01-22 23:41:55 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Andrew Lenharth304d0f32005-01-22 23:41:55 +00007//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//3.3:
14//Memory
15//Branch
16//Operate
17//Floating-point
18//PALcode
19
Andrew Lenharth4907d222005-10-20 00:28:31 +000020def u8imm : Operand<i64>;
21def s14imm : Operand<i64>;
22def s16imm : Operand<i64>;
23def s21imm : Operand<i64>;
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000024def s64imm : Operand<i64>;
Andrew Lenharthf81173f2006-10-31 16:49:55 +000025def u64imm : Operand<i64>;
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000026
Andrew Lenharth304d0f32005-01-22 23:41:55 +000027//===----------------------------------------------------------------------===//
28// Instruction format superclass
29//===----------------------------------------------------------------------===//
Andrew Lenharth5cefc5e2005-11-09 19:17:08 +000030// Alpha instruction baseline
Andrew Lenharth017c5562006-03-09 17:16:45 +000031class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
Andrew Lenharth304d0f32005-01-22 23:41:55 +000032 field bits<32> Inst;
Andrew Lenharth304d0f32005-01-22 23:41:55 +000033 let Namespace = "Alpha";
Andrew Lenharth304d0f32005-01-22 23:41:55 +000034 let AsmString = asmstr;
Andrew Lenharth304d0f32005-01-22 23:41:55 +000035 let Inst{31-26} = op;
Andrew Lenharth017c5562006-03-09 17:16:45 +000036 let Itinerary = itin;
Andrew Lenharth304d0f32005-01-22 23:41:55 +000037}
38
Andrew Lenharth5cefc5e2005-11-09 19:17:08 +000039
Andrew Lenharth304d0f32005-01-22 23:41:55 +000040//3.3.1
Andrew Lenharth017c5562006-03-09 17:16:45 +000041class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
42 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth9fa4d4c2005-12-24 03:41:56 +000043 let Pattern = pattern;
Andrew Lenharthb6718602005-12-24 07:34:33 +000044 let isStore = store;
45 let isLoad = load;
Andrew Lenharthcd1544e2006-01-26 03:22:07 +000046 let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
Andrew Lenharth9fa4d4c2005-12-24 03:41:56 +000047
48 bits<5> Ra;
49 bits<16> disp;
50 bits<5> Rb;
51
52 let Inst{25-21} = Ra;
53 let Inst{20-16} = Rb;
54 let Inst{15-0} = disp;
55}
Andrew Lenharth017c5562006-03-09 17:16:45 +000056class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin>
57 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth51b8d542005-11-11 16:47:30 +000058 bits<5> Ra;
Andrew Lenharth51b8d542005-11-11 16:47:30 +000059
Evan Cheng64d80e32007-07-19 01:14:50 +000060 let OutOperandList = (ops GPRC:$RA);
61 let InOperandList = (ops);
Andrew Lenharth51b8d542005-11-11 16:47:30 +000062 let Inst{25-21} = Ra;
Andrew Lenharth739027e2006-01-16 21:22:38 +000063 let Inst{20-16} = 0;
Andrew Lenharth51b8d542005-11-11 16:47:30 +000064 let Inst{15-0} = fc;
65}
Andrew Lenharth304d0f32005-01-22 23:41:55 +000066
Andrew Lenharth017c5562006-03-09 17:16:45 +000067class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
68 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000069 bits<5> Ra;
70 bits<5> Rb;
71 bits<14> disp;
72
Evan Cheng64d80e32007-07-19 01:14:50 +000073 let OutOperandList = (ops);
74 let InOperandList = OL;
Andrew Lenharth017c5562006-03-09 17:16:45 +000075
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000076 let Inst{25-21} = Ra;
77 let Inst{20-16} = Rb;
78 let Inst{15-14} = TB;
79 let Inst{13-0} = disp;
80}
Andrew Lenharthf2b806a2006-06-12 18:09:24 +000081class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin>
82 : InstAlpha<opcode, asmstr, itin> {
83 let Pattern=pattern;
84 bits<5> Ra;
85 bits<5> Rb;
86 bits<14> disp;
87
Evan Cheng64d80e32007-07-19 01:14:50 +000088 let OutOperandList = (ops);
89 let InOperandList = OL;
Andrew Lenharthf2b806a2006-06-12 18:09:24 +000090
91 let Inst{25-21} = Ra;
92 let Inst{20-16} = Rb;
93 let Inst{15-14} = TB;
94 let Inst{13-0} = disp;
95}
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000096
Andrew Lenharth304d0f32005-01-22 23:41:55 +000097//3.3.2
Andrew Lenhartheececba2005-12-25 17:36:48 +000098def target : Operand<OtherVT> {}
Andrew Lenharthf81173f2006-10-31 16:49:55 +000099
Evan Chengffbacca2007-07-21 00:34:19 +0000100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
Andrew Lenharthf81173f2006-10-31 16:49:55 +0000101class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
102 : InstAlpha<opcode, asmstr, itin> {
Evan Cheng64d80e32007-07-19 01:14:50 +0000103 let OutOperandList = (ops);
104 let InOperandList = OL;
Andrew Lenharthf81173f2006-10-31 16:49:55 +0000105 bits<64> Opc; //dummy
106 bits<5> Ra;
107 bits<21> disp;
108
109 let Inst{25-21} = Ra;
110 let Inst{20-0} = disp;
111}
112}
113
Andrew Lenharthcfb28152005-12-06 20:40:34 +0000114let isBranch = 1, isTerminator = 1 in
Andrew Lenharth017c5562006-03-09 17:16:45 +0000115class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin>
116 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenhartheececba2005-12-25 17:36:48 +0000117 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000118 let OutOperandList = (ops);
119 let InOperandList = (ops target:$DISP);
Andrew Lenhartheececba2005-12-25 17:36:48 +0000120 bits<5> Ra;
Andrew Lenharth756fbeb2005-10-22 22:06:58 +0000121 bits<21> disp;
122
123 let Inst{25-21} = Ra;
124 let Inst{20-0} = disp;
125}
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000126
127//3.3.3
Andrew Lenharth017c5562006-03-09 17:16:45 +0000128class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
129 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth4907d222005-10-20 00:28:31 +0000130 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000131 let OutOperandList = (outs GPRC:$RC);
132 let InOperandList = (ins GPRC:$RA, GPRC:$RB);
Andrew Lenharth4907d222005-10-20 00:28:31 +0000133
Andrew Lenharthf3f951a2005-07-22 20:50:29 +0000134 bits<5> Rc;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000135 bits<5> Ra;
136 bits<5> Rb;
Andrew Lenharthf3f951a2005-07-22 20:50:29 +0000137 bits<7> Function = fun;
138
139 let Inst{25-21} = Ra;
140 let Inst{20-16} = Rb;
141 let Inst{15-13} = 0;
142 let Inst{12} = 0;
143 let Inst{11-5} = Function;
144 let Inst{4-0} = Rc;
145}
146
Andrew Lenharth017c5562006-03-09 17:16:45 +0000147class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
148 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth964b6aa2005-10-20 19:39:24 +0000149 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000150 let OutOperandList = (outs GPRC:$RC);
151 let InOperandList = (ins GPRC:$RB);
Andrew Lenharth964b6aa2005-10-20 19:39:24 +0000152
153 bits<5> Rc;
154 bits<5> Rb;
155 bits<7> Function = fun;
156
Andrew Lenharth756fbeb2005-10-22 22:06:58 +0000157 let Inst{25-21} = 31;
Andrew Lenharth964b6aa2005-10-20 19:39:24 +0000158 let Inst{20-16} = Rb;
159 let Inst{15-13} = 0;
160 let Inst{12} = 0;
161 let Inst{11-5} = Function;
162 let Inst{4-0} = Rc;
163}
164
Andrew Lenharth017c5562006-03-09 17:16:45 +0000165class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
166 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000167 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000168 let OutOperandList = (outs GPRC:$RDEST);
169 let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
Andrew Lenharth15b78232007-04-17 04:07:59 +0000170 let Constraints = "$RFALSE = $RDEST";
171 let DisableEncoding = "$RFALSE";
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000172
173 bits<5> Rc;
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000174 bits<5> Ra;
Andrew Lenharth15b78232007-04-17 04:07:59 +0000175 bits<5> Rb;
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000176 bits<7> Function = fun;
177
Andrew Lenharth15b78232007-04-17 04:07:59 +0000178// let isTwoAddress = 1;
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000179 let Inst{25-21} = Ra;
180 let Inst{20-16} = Rb;
181 let Inst{15-13} = 0;
182 let Inst{12} = 0;
183 let Inst{11-5} = Function;
184 let Inst{4-0} = Rc;
185}
186
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000187
Andrew Lenharth017c5562006-03-09 17:16:45 +0000188class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
189 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth4907d222005-10-20 00:28:31 +0000190 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000191 let OutOperandList = (outs GPRC:$RC);
192 let InOperandList = (ins GPRC:$RA, u8imm:$L);
Andrew Lenharth4907d222005-10-20 00:28:31 +0000193
Andrew Lenharthf3f951a2005-07-22 20:50:29 +0000194 bits<5> Rc;
195 bits<5> Ra;
196 bits<8> LIT;
197 bits<7> Function = fun;
198
199 let Inst{25-21} = Ra;
200 let Inst{20-13} = LIT;
201 let Inst{12} = 1;
202 let Inst{11-5} = Function;
203 let Inst{4-0} = Rc;
204}
205
Andrew Lenharth017c5562006-03-09 17:16:45 +0000206class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
207 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth77f08852006-02-01 19:37:33 +0000208 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000209 let OutOperandList = (outs GPRC:$RDEST);
210 let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
Andrew Lenharth15b78232007-04-17 04:07:59 +0000211 let Constraints = "$RFALSE = $RDEST";
212 let DisableEncoding = "$RFALSE";
213
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000214 bits<5> Rc;
Andrew Lenharth1f347a32005-10-20 23:58:36 +0000215 bits<5> Ra;
Andrew Lenharth15b78232007-04-17 04:07:59 +0000216 bits<8> LIT;
Andrew Lenharth1f347a32005-10-20 23:58:36 +0000217 bits<7> Function = fun;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000218
Andrew Lenharth15b78232007-04-17 04:07:59 +0000219// let isTwoAddress = 1;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000220 let Inst{25-21} = Ra;
221 let Inst{20-13} = LIT;
222 let Inst{12} = 1;
223 let Inst{11-5} = Function;
224 let Inst{4-0} = Rc;
225}
226
227//3.3.4
Andrew Lenharth017c5562006-03-09 17:16:45 +0000228class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
229 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth5cefc5e2005-11-09 19:17:08 +0000230 let Pattern = pattern;
231
Andrew Lenharth98169be2005-07-28 18:14:47 +0000232 bits<5> Fc;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000233 bits<5> Fa;
234 bits<5> Fb;
Andrew Lenharth3e98fde2005-01-26 21:54:09 +0000235 bits<11> Function = fun;
Andrew Lenharth98169be2005-07-28 18:14:47 +0000236
237 let Inst{25-21} = Fa;
238 let Inst{20-16} = Fb;
239 let Inst{15-5} = Function;
240 let Inst{4-0} = Fc;
241}
242
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000243//3.3.5
Andrew Lenharth017c5562006-03-09 17:16:45 +0000244class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
245 : InstAlpha<opcode, asmstr, itin> {
Evan Cheng64d80e32007-07-19 01:14:50 +0000246 let OutOperandList = (ops);
247 let InOperandList = OL;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000248 bits<26> Function;
249
250 let Inst{25-0} = Function;
251}
252
253
254// Pseudo instructions.
Evan Cheng64d80e32007-07-19 01:14:50 +0000255class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin>
Andrew Lenharth017c5562006-03-09 17:16:45 +0000256 : InstAlpha<0, nm, itin> {
Evan Cheng64d80e32007-07-19 01:14:50 +0000257 let OutOperandList = OOL;
258 let InOperandList = IOL;
Andrew Lenharth50b37842005-11-22 04:20:06 +0000259 let Pattern = pattern;
260
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000261}