Misha Brukman | cf2b9ac | 2002-11-22 22:43:47 +0000 | [diff] [blame] | 1 | //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 2 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 7 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 9 | // |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 10 | // This file contains the X86 implementation of the MRegisterInfo class. This |
| 11 | // file is responsible for the frame pointer elimination optimization on X86. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 15 | #include "X86.h" |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 16 | #include "X86RegisterInfo.h" |
Misha Brukman | cf2b9ac | 2002-11-22 22:43:47 +0000 | [diff] [blame] | 17 | #include "X86InstrBuilder.h" |
Evan Cheng | e8bd0a3 | 2006-06-06 23:30:24 +0000 | [diff] [blame] | 18 | #include "X86MachineFunctionInfo.h" |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 19 | #include "X86Subtarget.h" |
Evan Cheng | e8bd0a3 | 2006-06-06 23:30:24 +0000 | [diff] [blame] | 20 | #include "X86TargetMachine.h" |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 21 | #include "llvm/Constants.h" |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 22 | #include "llvm/Function.h" |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 23 | #include "llvm/Type.h" |
Chris Lattner | c8c377d | 2003-07-29 05:14:16 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/ValueTypes.h" |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | 198ab64 | 2002-12-15 20:06:35 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineFunction.h" |
Chris Lattner | aa09b75 | 2002-12-28 21:08:28 +0000 | [diff] [blame] | 27 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 28 | #include "llvm/CodeGen/MachineLocation.h" |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/SSARegMap.h" |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 30 | #include "llvm/Target/TargetAsmInfo.h" |
Chris Lattner | f158da2 | 2003-01-16 02:20:12 +0000 | [diff] [blame] | 31 | #include "llvm/Target/TargetFrameInfo.h" |
Evan Cheng | 51cdcd1 | 2006-12-07 01:21:59 +0000 | [diff] [blame] | 32 | #include "llvm/Target/TargetInstrInfo.h" |
Misha Brukman | 83eaa0b | 2004-06-21 21:10:24 +0000 | [diff] [blame] | 33 | #include "llvm/Target/TargetMachine.h" |
Chris Lattner | 0cf0c37 | 2004-07-11 04:17:10 +0000 | [diff] [blame] | 34 | #include "llvm/Target/TargetOptions.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 35 | #include "llvm/Support/CommandLine.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 36 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 37 | #include "llvm/ADT/STLExtras.h" |
Chris Lattner | 300d0ed | 2004-02-14 06:00:36 +0000 | [diff] [blame] | 38 | using namespace llvm; |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 39 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 40 | namespace { |
| 41 | cl::opt<bool> |
Chris Lattner | a7660be | 2004-02-17 06:30:34 +0000 | [diff] [blame] | 42 | NoFusing("disable-spill-fusing", |
| 43 | cl::desc("Disable fusing of spill code into instructions")); |
Chris Lattner | ee0919b | 2004-02-17 08:03:47 +0000 | [diff] [blame] | 44 | cl::opt<bool> |
| 45 | PrintFailedFusing("print-failed-fuse-candidates", |
| 46 | cl::desc("Print instructions that the allocator wants to" |
| 47 | " fuse, but the X86 backend currently can't"), |
| 48 | cl::Hidden); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 49 | } |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 50 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 51 | X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, |
| 52 | const TargetInstrInfo &tii) |
| 53 | : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP), |
| 54 | TM(tm), TII(tii) { |
| 55 | // Cache some information. |
| 56 | const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); |
| 57 | Is64Bit = Subtarget->is64Bit(); |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 58 | StackAlign = TM.getFrameInfo()->getStackAlignment(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 59 | if (Is64Bit) { |
| 60 | SlotSize = 8; |
| 61 | StackPtr = X86::RSP; |
| 62 | FramePtr = X86::RBP; |
| 63 | } else { |
| 64 | SlotSize = 4; |
| 65 | StackPtr = X86::ESP; |
| 66 | FramePtr = X86::EBP; |
| 67 | } |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 68 | |
| 69 | SmallVector<unsigned,16> AmbEntries; |
| 70 | static const unsigned OpTbl2Addr[][2] = { |
| 71 | { X86::ADC32ri, X86::ADC32mi }, |
| 72 | { X86::ADC32ri8, X86::ADC32mi8 }, |
| 73 | { X86::ADC32rr, X86::ADC32mr }, |
| 74 | { X86::ADC64ri32, X86::ADC64mi32 }, |
| 75 | { X86::ADC64ri8, X86::ADC64mi8 }, |
| 76 | { X86::ADC64rr, X86::ADC64mr }, |
| 77 | { X86::ADD16ri, X86::ADD16mi }, |
| 78 | { X86::ADD16ri8, X86::ADD16mi8 }, |
| 79 | { X86::ADD16rr, X86::ADD16mr }, |
| 80 | { X86::ADD32ri, X86::ADD32mi }, |
| 81 | { X86::ADD32ri8, X86::ADD32mi8 }, |
| 82 | { X86::ADD32rr, X86::ADD32mr }, |
| 83 | { X86::ADD64ri32, X86::ADD64mi32 }, |
| 84 | { X86::ADD64ri8, X86::ADD64mi8 }, |
| 85 | { X86::ADD64rr, X86::ADD64mr }, |
| 86 | { X86::ADD8ri, X86::ADD8mi }, |
| 87 | { X86::ADD8rr, X86::ADD8mr }, |
| 88 | { X86::AND16ri, X86::AND16mi }, |
| 89 | { X86::AND16ri8, X86::AND16mi8 }, |
| 90 | { X86::AND16rr, X86::AND16mr }, |
| 91 | { X86::AND32ri, X86::AND32mi }, |
| 92 | { X86::AND32ri8, X86::AND32mi8 }, |
| 93 | { X86::AND32rr, X86::AND32mr }, |
| 94 | { X86::AND64ri32, X86::AND64mi32 }, |
| 95 | { X86::AND64ri8, X86::AND64mi8 }, |
| 96 | { X86::AND64rr, X86::AND64mr }, |
| 97 | { X86::AND8ri, X86::AND8mi }, |
| 98 | { X86::AND8rr, X86::AND8mr }, |
| 99 | { X86::DEC16r, X86::DEC16m }, |
| 100 | { X86::DEC32r, X86::DEC32m }, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 101 | { X86::DEC64_16r, X86::DEC64_16m }, |
| 102 | { X86::DEC64_32r, X86::DEC64_32m }, |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 103 | { X86::DEC64r, X86::DEC64m }, |
| 104 | { X86::DEC8r, X86::DEC8m }, |
| 105 | { X86::INC16r, X86::INC16m }, |
| 106 | { X86::INC32r, X86::INC32m }, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 107 | { X86::INC64_16r, X86::INC64_16m }, |
| 108 | { X86::INC64_32r, X86::INC64_32m }, |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 109 | { X86::INC64r, X86::INC64m }, |
| 110 | { X86::INC8r, X86::INC8m }, |
| 111 | { X86::NEG16r, X86::NEG16m }, |
| 112 | { X86::NEG32r, X86::NEG32m }, |
| 113 | { X86::NEG64r, X86::NEG64m }, |
| 114 | { X86::NEG8r, X86::NEG8m }, |
| 115 | { X86::NOT16r, X86::NOT16m }, |
| 116 | { X86::NOT32r, X86::NOT32m }, |
| 117 | { X86::NOT64r, X86::NOT64m }, |
| 118 | { X86::NOT8r, X86::NOT8m }, |
| 119 | { X86::OR16ri, X86::OR16mi }, |
| 120 | { X86::OR16ri8, X86::OR16mi8 }, |
| 121 | { X86::OR16rr, X86::OR16mr }, |
| 122 | { X86::OR32ri, X86::OR32mi }, |
| 123 | { X86::OR32ri8, X86::OR32mi8 }, |
| 124 | { X86::OR32rr, X86::OR32mr }, |
| 125 | { X86::OR64ri32, X86::OR64mi32 }, |
| 126 | { X86::OR64ri8, X86::OR64mi8 }, |
| 127 | { X86::OR64rr, X86::OR64mr }, |
| 128 | { X86::OR8ri, X86::OR8mi }, |
| 129 | { X86::OR8rr, X86::OR8mr }, |
| 130 | { X86::ROL16r1, X86::ROL16m1 }, |
| 131 | { X86::ROL16rCL, X86::ROL16mCL }, |
| 132 | { X86::ROL16ri, X86::ROL16mi }, |
| 133 | { X86::ROL32r1, X86::ROL32m1 }, |
| 134 | { X86::ROL32rCL, X86::ROL32mCL }, |
| 135 | { X86::ROL32ri, X86::ROL32mi }, |
| 136 | { X86::ROL64r1, X86::ROL64m1 }, |
| 137 | { X86::ROL64rCL, X86::ROL64mCL }, |
| 138 | { X86::ROL64ri, X86::ROL64mi }, |
| 139 | { X86::ROL8r1, X86::ROL8m1 }, |
| 140 | { X86::ROL8rCL, X86::ROL8mCL }, |
| 141 | { X86::ROL8ri, X86::ROL8mi }, |
| 142 | { X86::ROR16r1, X86::ROR16m1 }, |
| 143 | { X86::ROR16rCL, X86::ROR16mCL }, |
| 144 | { X86::ROR16ri, X86::ROR16mi }, |
| 145 | { X86::ROR32r1, X86::ROR32m1 }, |
| 146 | { X86::ROR32rCL, X86::ROR32mCL }, |
| 147 | { X86::ROR32ri, X86::ROR32mi }, |
| 148 | { X86::ROR64r1, X86::ROR64m1 }, |
| 149 | { X86::ROR64rCL, X86::ROR64mCL }, |
| 150 | { X86::ROR64ri, X86::ROR64mi }, |
| 151 | { X86::ROR8r1, X86::ROR8m1 }, |
| 152 | { X86::ROR8rCL, X86::ROR8mCL }, |
| 153 | { X86::ROR8ri, X86::ROR8mi }, |
| 154 | { X86::SAR16r1, X86::SAR16m1 }, |
| 155 | { X86::SAR16rCL, X86::SAR16mCL }, |
| 156 | { X86::SAR16ri, X86::SAR16mi }, |
| 157 | { X86::SAR32r1, X86::SAR32m1 }, |
| 158 | { X86::SAR32rCL, X86::SAR32mCL }, |
| 159 | { X86::SAR32ri, X86::SAR32mi }, |
| 160 | { X86::SAR64r1, X86::SAR64m1 }, |
| 161 | { X86::SAR64rCL, X86::SAR64mCL }, |
| 162 | { X86::SAR64ri, X86::SAR64mi }, |
| 163 | { X86::SAR8r1, X86::SAR8m1 }, |
| 164 | { X86::SAR8rCL, X86::SAR8mCL }, |
| 165 | { X86::SAR8ri, X86::SAR8mi }, |
| 166 | { X86::SBB32ri, X86::SBB32mi }, |
| 167 | { X86::SBB32ri8, X86::SBB32mi8 }, |
| 168 | { X86::SBB32rr, X86::SBB32mr }, |
| 169 | { X86::SBB64ri32, X86::SBB64mi32 }, |
| 170 | { X86::SBB64ri8, X86::SBB64mi8 }, |
| 171 | { X86::SBB64rr, X86::SBB64mr }, |
| 172 | { X86::SHL16r1, X86::SHL16m1 }, |
| 173 | { X86::SHL16rCL, X86::SHL16mCL }, |
| 174 | { X86::SHL16ri, X86::SHL16mi }, |
| 175 | { X86::SHL32r1, X86::SHL32m1 }, |
| 176 | { X86::SHL32rCL, X86::SHL32mCL }, |
| 177 | { X86::SHL32ri, X86::SHL32mi }, |
| 178 | { X86::SHL64r1, X86::SHL64m1 }, |
| 179 | { X86::SHL64rCL, X86::SHL64mCL }, |
| 180 | { X86::SHL64ri, X86::SHL64mi }, |
| 181 | { X86::SHL8r1, X86::SHL8m1 }, |
| 182 | { X86::SHL8rCL, X86::SHL8mCL }, |
| 183 | { X86::SHL8ri, X86::SHL8mi }, |
| 184 | { X86::SHLD16rrCL, X86::SHLD16mrCL }, |
| 185 | { X86::SHLD16rri8, X86::SHLD16mri8 }, |
| 186 | { X86::SHLD32rrCL, X86::SHLD32mrCL }, |
| 187 | { X86::SHLD32rri8, X86::SHLD32mri8 }, |
| 188 | { X86::SHLD64rrCL, X86::SHLD64mrCL }, |
| 189 | { X86::SHLD64rri8, X86::SHLD64mri8 }, |
| 190 | { X86::SHR16r1, X86::SHR16m1 }, |
| 191 | { X86::SHR16rCL, X86::SHR16mCL }, |
| 192 | { X86::SHR16ri, X86::SHR16mi }, |
| 193 | { X86::SHR32r1, X86::SHR32m1 }, |
| 194 | { X86::SHR32rCL, X86::SHR32mCL }, |
| 195 | { X86::SHR32ri, X86::SHR32mi }, |
| 196 | { X86::SHR64r1, X86::SHR64m1 }, |
| 197 | { X86::SHR64rCL, X86::SHR64mCL }, |
| 198 | { X86::SHR64ri, X86::SHR64mi }, |
| 199 | { X86::SHR8r1, X86::SHR8m1 }, |
| 200 | { X86::SHR8rCL, X86::SHR8mCL }, |
| 201 | { X86::SHR8ri, X86::SHR8mi }, |
| 202 | { X86::SHRD16rrCL, X86::SHRD16mrCL }, |
| 203 | { X86::SHRD16rri8, X86::SHRD16mri8 }, |
| 204 | { X86::SHRD32rrCL, X86::SHRD32mrCL }, |
| 205 | { X86::SHRD32rri8, X86::SHRD32mri8 }, |
| 206 | { X86::SHRD64rrCL, X86::SHRD64mrCL }, |
| 207 | { X86::SHRD64rri8, X86::SHRD64mri8 }, |
| 208 | { X86::SUB16ri, X86::SUB16mi }, |
| 209 | { X86::SUB16ri8, X86::SUB16mi8 }, |
| 210 | { X86::SUB16rr, X86::SUB16mr }, |
| 211 | { X86::SUB32ri, X86::SUB32mi }, |
| 212 | { X86::SUB32ri8, X86::SUB32mi8 }, |
| 213 | { X86::SUB32rr, X86::SUB32mr }, |
| 214 | { X86::SUB64ri32, X86::SUB64mi32 }, |
| 215 | { X86::SUB64ri8, X86::SUB64mi8 }, |
| 216 | { X86::SUB64rr, X86::SUB64mr }, |
| 217 | { X86::SUB8ri, X86::SUB8mi }, |
| 218 | { X86::SUB8rr, X86::SUB8mr }, |
| 219 | { X86::XOR16ri, X86::XOR16mi }, |
| 220 | { X86::XOR16ri8, X86::XOR16mi8 }, |
| 221 | { X86::XOR16rr, X86::XOR16mr }, |
| 222 | { X86::XOR32ri, X86::XOR32mi }, |
| 223 | { X86::XOR32ri8, X86::XOR32mi8 }, |
| 224 | { X86::XOR32rr, X86::XOR32mr }, |
| 225 | { X86::XOR64ri32, X86::XOR64mi32 }, |
| 226 | { X86::XOR64ri8, X86::XOR64mi8 }, |
| 227 | { X86::XOR64rr, X86::XOR64mr }, |
| 228 | { X86::XOR8ri, X86::XOR8mi }, |
| 229 | { X86::XOR8rr, X86::XOR8mr } |
| 230 | }; |
| 231 | |
| 232 | for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { |
| 233 | unsigned RegOp = OpTbl2Addr[i][0]; |
| 234 | unsigned MemOp = OpTbl2Addr[i][1]; |
| 235 | if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 236 | assert(false && "Duplicated entries?"); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 237 | unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store |
| 238 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 239 | std::make_pair(RegOp, AuxInfo)))) |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 240 | AmbEntries.push_back(MemOp); |
| 241 | } |
| 242 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 243 | // If the third value is 1, then it's folding either a load or a store. |
| 244 | static const unsigned OpTbl0[][3] = { |
| 245 | { X86::CALL32r, X86::CALL32m, 1 }, |
| 246 | { X86::CALL64r, X86::CALL64m, 1 }, |
| 247 | { X86::CMP16ri, X86::CMP16mi, 1 }, |
| 248 | { X86::CMP16ri8, X86::CMP16mi8, 1 }, |
| 249 | { X86::CMP32ri, X86::CMP32mi, 1 }, |
| 250 | { X86::CMP32ri8, X86::CMP32mi8, 1 }, |
| 251 | { X86::CMP64ri32, X86::CMP64mi32, 1 }, |
| 252 | { X86::CMP64ri8, X86::CMP64mi8, 1 }, |
| 253 | { X86::CMP8ri, X86::CMP8mi, 1 }, |
| 254 | { X86::DIV16r, X86::DIV16m, 1 }, |
| 255 | { X86::DIV32r, X86::DIV32m, 1 }, |
| 256 | { X86::DIV64r, X86::DIV64m, 1 }, |
| 257 | { X86::DIV8r, X86::DIV8m, 1 }, |
| 258 | { X86::FsMOVAPDrr, X86::MOVSDmr, 0 }, |
| 259 | { X86::FsMOVAPSrr, X86::MOVSSmr, 0 }, |
| 260 | { X86::IDIV16r, X86::IDIV16m, 1 }, |
| 261 | { X86::IDIV32r, X86::IDIV32m, 1 }, |
| 262 | { X86::IDIV64r, X86::IDIV64m, 1 }, |
| 263 | { X86::IDIV8r, X86::IDIV8m, 1 }, |
| 264 | { X86::IMUL16r, X86::IMUL16m, 1 }, |
| 265 | { X86::IMUL32r, X86::IMUL32m, 1 }, |
| 266 | { X86::IMUL64r, X86::IMUL64m, 1 }, |
| 267 | { X86::IMUL8r, X86::IMUL8m, 1 }, |
| 268 | { X86::JMP32r, X86::JMP32m, 1 }, |
| 269 | { X86::JMP64r, X86::JMP64m, 1 }, |
| 270 | { X86::MOV16ri, X86::MOV16mi, 0 }, |
| 271 | { X86::MOV16rr, X86::MOV16mr, 0 }, |
Evan Cheng | f4a9c69 | 2007-10-12 08:38:01 +0000 | [diff] [blame] | 272 | { X86::MOV16to16_, X86::MOV16_mr, 0 }, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 273 | { X86::MOV32ri, X86::MOV32mi, 0 }, |
| 274 | { X86::MOV32rr, X86::MOV32mr, 0 }, |
Evan Cheng | f4a9c69 | 2007-10-12 08:38:01 +0000 | [diff] [blame] | 275 | { X86::MOV32to32_, X86::MOV32_mr, 0 }, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 276 | { X86::MOV64ri32, X86::MOV64mi32, 0 }, |
| 277 | { X86::MOV64rr, X86::MOV64mr, 0 }, |
| 278 | { X86::MOV8ri, X86::MOV8mi, 0 }, |
| 279 | { X86::MOV8rr, X86::MOV8mr, 0 }, |
| 280 | { X86::MOVAPDrr, X86::MOVAPDmr, 0 }, |
| 281 | { X86::MOVAPSrr, X86::MOVAPSmr, 0 }, |
| 282 | { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 }, |
Evan Cheng | 0c5a507 | 2007-12-14 20:08:14 +0000 | [diff] [blame] | 283 | { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 }, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 284 | { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 }, |
| 285 | { X86::MOVSDrr, X86::MOVSDmr, 0 }, |
| 286 | { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 }, |
| 287 | { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 }, |
| 288 | { X86::MOVSSrr, X86::MOVSSmr, 0 }, |
| 289 | { X86::MOVUPDrr, X86::MOVUPDmr, 0 }, |
| 290 | { X86::MOVUPSrr, X86::MOVUPSmr, 0 }, |
| 291 | { X86::MUL16r, X86::MUL16m, 1 }, |
| 292 | { X86::MUL32r, X86::MUL32m, 1 }, |
| 293 | { X86::MUL64r, X86::MUL64m, 1 }, |
| 294 | { X86::MUL8r, X86::MUL8m, 1 }, |
| 295 | { X86::SETAEr, X86::SETAEm, 0 }, |
| 296 | { X86::SETAr, X86::SETAm, 0 }, |
| 297 | { X86::SETBEr, X86::SETBEm, 0 }, |
| 298 | { X86::SETBr, X86::SETBm, 0 }, |
| 299 | { X86::SETEr, X86::SETEm, 0 }, |
| 300 | { X86::SETGEr, X86::SETGEm, 0 }, |
| 301 | { X86::SETGr, X86::SETGm, 0 }, |
| 302 | { X86::SETLEr, X86::SETLEm, 0 }, |
| 303 | { X86::SETLr, X86::SETLm, 0 }, |
| 304 | { X86::SETNEr, X86::SETNEm, 0 }, |
| 305 | { X86::SETNPr, X86::SETNPm, 0 }, |
| 306 | { X86::SETNSr, X86::SETNSm, 0 }, |
| 307 | { X86::SETPr, X86::SETPm, 0 }, |
| 308 | { X86::SETSr, X86::SETSm, 0 }, |
| 309 | { X86::TAILJMPr, X86::TAILJMPm, 1 }, |
| 310 | { X86::TEST16ri, X86::TEST16mi, 1 }, |
| 311 | { X86::TEST32ri, X86::TEST32mi, 1 }, |
| 312 | { X86::TEST64ri32, X86::TEST64mi32, 1 }, |
| 313 | { X86::TEST8ri, X86::TEST8mi, 1 }, |
| 314 | { X86::XCHG16rr, X86::XCHG16mr, 0 }, |
| 315 | { X86::XCHG32rr, X86::XCHG32mr, 0 }, |
| 316 | { X86::XCHG64rr, X86::XCHG64mr, 0 }, |
| 317 | { X86::XCHG8rr, X86::XCHG8mr, 0 } |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 318 | }; |
| 319 | |
| 320 | for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { |
| 321 | unsigned RegOp = OpTbl0[i][0]; |
| 322 | unsigned MemOp = OpTbl0[i][1]; |
| 323 | if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 324 | assert(false && "Duplicated entries?"); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 325 | unsigned FoldedLoad = OpTbl0[i][2]; |
| 326 | // Index 0, folded load or store. |
| 327 | unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); |
Evan Cheng | f7c9695 | 2007-10-19 23:50:58 +0000 | [diff] [blame] | 328 | if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) |
| 329 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 330 | std::make_pair(RegOp, AuxInfo)))) |
Evan Cheng | f7c9695 | 2007-10-19 23:50:58 +0000 | [diff] [blame] | 331 | AmbEntries.push_back(MemOp); |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 332 | } |
| 333 | |
| 334 | static const unsigned OpTbl1[][2] = { |
| 335 | { X86::CMP16rr, X86::CMP16rm }, |
| 336 | { X86::CMP32rr, X86::CMP32rm }, |
| 337 | { X86::CMP64rr, X86::CMP64rm }, |
| 338 | { X86::CMP8rr, X86::CMP8rm }, |
| 339 | { X86::CVTSD2SSrr, X86::CVTSD2SSrm }, |
| 340 | { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm }, |
| 341 | { X86::CVTSI2SDrr, X86::CVTSI2SDrm }, |
| 342 | { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm }, |
| 343 | { X86::CVTSI2SSrr, X86::CVTSI2SSrm }, |
| 344 | { X86::CVTSS2SDrr, X86::CVTSS2SDrm }, |
| 345 | { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm }, |
| 346 | { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm }, |
| 347 | { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm }, |
| 348 | { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm }, |
| 349 | { X86::FsMOVAPDrr, X86::MOVSDrm }, |
| 350 | { X86::FsMOVAPSrr, X86::MOVSSrm }, |
| 351 | { X86::IMUL16rri, X86::IMUL16rmi }, |
| 352 | { X86::IMUL16rri8, X86::IMUL16rmi8 }, |
| 353 | { X86::IMUL32rri, X86::IMUL32rmi }, |
| 354 | { X86::IMUL32rri8, X86::IMUL32rmi8 }, |
| 355 | { X86::IMUL64rri32, X86::IMUL64rmi32 }, |
| 356 | { X86::IMUL64rri8, X86::IMUL64rmi8 }, |
| 357 | { X86::Int_CMPSDrr, X86::Int_CMPSDrm }, |
| 358 | { X86::Int_CMPSSrr, X86::Int_CMPSSrm }, |
| 359 | { X86::Int_COMISDrr, X86::Int_COMISDrm }, |
| 360 | { X86::Int_COMISSrr, X86::Int_COMISSrm }, |
| 361 | { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm }, |
| 362 | { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm }, |
| 363 | { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm }, |
| 364 | { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm }, |
| 365 | { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm }, |
| 366 | { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm }, |
| 367 | { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm }, |
| 368 | { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm }, |
| 369 | { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm }, |
| 370 | { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm }, |
| 371 | { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm }, |
| 372 | { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm }, |
| 373 | { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm }, |
| 374 | { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm }, |
| 375 | { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm }, |
| 376 | { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm }, |
| 377 | { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm }, |
| 378 | { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm }, |
| 379 | { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm }, |
| 380 | { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm }, |
| 381 | { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm }, |
| 382 | { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm }, |
| 383 | { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm }, |
| 384 | { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm }, |
| 385 | { X86::MOV16rr, X86::MOV16rm }, |
Evan Cheng | f4a9c69 | 2007-10-12 08:38:01 +0000 | [diff] [blame] | 386 | { X86::MOV16to16_, X86::MOV16_rm }, |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 387 | { X86::MOV32rr, X86::MOV32rm }, |
Evan Cheng | f4a9c69 | 2007-10-12 08:38:01 +0000 | [diff] [blame] | 388 | { X86::MOV32to32_, X86::MOV32_rm }, |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 389 | { X86::MOV64rr, X86::MOV64rm }, |
Evan Cheng | 0c5a507 | 2007-12-14 20:08:14 +0000 | [diff] [blame] | 390 | { X86::MOV64toPQIrr, X86::MOVQI2PQIrm }, |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 391 | { X86::MOV64toSDrr, X86::MOV64toSDrm }, |
| 392 | { X86::MOV8rr, X86::MOV8rm }, |
| 393 | { X86::MOVAPDrr, X86::MOVAPDrm }, |
| 394 | { X86::MOVAPSrr, X86::MOVAPSrm }, |
| 395 | { X86::MOVDDUPrr, X86::MOVDDUPrm }, |
| 396 | { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm }, |
| 397 | { X86::MOVDI2SSrr, X86::MOVDI2SSrm }, |
| 398 | { X86::MOVSD2PDrr, X86::MOVSD2PDrm }, |
| 399 | { X86::MOVSDrr, X86::MOVSDrm }, |
| 400 | { X86::MOVSHDUPrr, X86::MOVSHDUPrm }, |
| 401 | { X86::MOVSLDUPrr, X86::MOVSLDUPrm }, |
| 402 | { X86::MOVSS2PSrr, X86::MOVSS2PSrm }, |
| 403 | { X86::MOVSSrr, X86::MOVSSrm }, |
| 404 | { X86::MOVSX16rr8, X86::MOVSX16rm8 }, |
| 405 | { X86::MOVSX32rr16, X86::MOVSX32rm16 }, |
| 406 | { X86::MOVSX32rr8, X86::MOVSX32rm8 }, |
| 407 | { X86::MOVSX64rr16, X86::MOVSX64rm16 }, |
| 408 | { X86::MOVSX64rr32, X86::MOVSX64rm32 }, |
| 409 | { X86::MOVSX64rr8, X86::MOVSX64rm8 }, |
| 410 | { X86::MOVUPDrr, X86::MOVUPDrm }, |
| 411 | { X86::MOVUPSrr, X86::MOVUPSrm }, |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 412 | { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm }, |
| 413 | { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm }, |
| 414 | { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm }, |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 415 | { X86::MOVZX16rr8, X86::MOVZX16rm8 }, |
| 416 | { X86::MOVZX32rr16, X86::MOVZX32rm16 }, |
| 417 | { X86::MOVZX32rr8, X86::MOVZX32rm8 }, |
| 418 | { X86::MOVZX64rr16, X86::MOVZX64rm16 }, |
| 419 | { X86::MOVZX64rr8, X86::MOVZX64rm8 }, |
| 420 | { X86::PSHUFDri, X86::PSHUFDmi }, |
| 421 | { X86::PSHUFHWri, X86::PSHUFHWmi }, |
| 422 | { X86::PSHUFLWri, X86::PSHUFLWmi }, |
| 423 | { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 }, |
| 424 | { X86::RCPPSr, X86::RCPPSm }, |
| 425 | { X86::RCPPSr_Int, X86::RCPPSm_Int }, |
| 426 | { X86::RSQRTPSr, X86::RSQRTPSm }, |
| 427 | { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int }, |
| 428 | { X86::RSQRTSSr, X86::RSQRTSSm }, |
| 429 | { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int }, |
| 430 | { X86::SQRTPDr, X86::SQRTPDm }, |
| 431 | { X86::SQRTPDr_Int, X86::SQRTPDm_Int }, |
| 432 | { X86::SQRTPSr, X86::SQRTPSm }, |
| 433 | { X86::SQRTPSr_Int, X86::SQRTPSm_Int }, |
| 434 | { X86::SQRTSDr, X86::SQRTSDm }, |
| 435 | { X86::SQRTSDr_Int, X86::SQRTSDm_Int }, |
| 436 | { X86::SQRTSSr, X86::SQRTSSm }, |
| 437 | { X86::SQRTSSr_Int, X86::SQRTSSm_Int }, |
| 438 | { X86::TEST16rr, X86::TEST16rm }, |
| 439 | { X86::TEST32rr, X86::TEST32rm }, |
| 440 | { X86::TEST64rr, X86::TEST64rm }, |
| 441 | { X86::TEST8rr, X86::TEST8rm }, |
| 442 | // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 |
| 443 | { X86::UCOMISDrr, X86::UCOMISDrm }, |
| 444 | { X86::UCOMISSrr, X86::UCOMISSrm }, |
| 445 | { X86::XCHG16rr, X86::XCHG16rm }, |
| 446 | { X86::XCHG32rr, X86::XCHG32rm }, |
| 447 | { X86::XCHG64rr, X86::XCHG64rm }, |
| 448 | { X86::XCHG8rr, X86::XCHG8rm } |
| 449 | }; |
| 450 | |
| 451 | for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { |
| 452 | unsigned RegOp = OpTbl1[i][0]; |
| 453 | unsigned MemOp = OpTbl1[i][1]; |
| 454 | if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 455 | assert(false && "Duplicated entries?"); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 456 | unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load |
Evan Cheng | f7c9695 | 2007-10-19 23:50:58 +0000 | [diff] [blame] | 457 | if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) |
| 458 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 459 | std::make_pair(RegOp, AuxInfo)))) |
Evan Cheng | f7c9695 | 2007-10-19 23:50:58 +0000 | [diff] [blame] | 460 | AmbEntries.push_back(MemOp); |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 461 | } |
| 462 | |
| 463 | static const unsigned OpTbl2[][2] = { |
| 464 | { X86::ADC32rr, X86::ADC32rm }, |
| 465 | { X86::ADC64rr, X86::ADC64rm }, |
| 466 | { X86::ADD16rr, X86::ADD16rm }, |
| 467 | { X86::ADD32rr, X86::ADD32rm }, |
| 468 | { X86::ADD64rr, X86::ADD64rm }, |
| 469 | { X86::ADD8rr, X86::ADD8rm }, |
| 470 | { X86::ADDPDrr, X86::ADDPDrm }, |
| 471 | { X86::ADDPSrr, X86::ADDPSrm }, |
| 472 | { X86::ADDSDrr, X86::ADDSDrm }, |
| 473 | { X86::ADDSSrr, X86::ADDSSrm }, |
| 474 | { X86::ADDSUBPDrr, X86::ADDSUBPDrm }, |
| 475 | { X86::ADDSUBPSrr, X86::ADDSUBPSrm }, |
| 476 | { X86::AND16rr, X86::AND16rm }, |
| 477 | { X86::AND32rr, X86::AND32rm }, |
| 478 | { X86::AND64rr, X86::AND64rm }, |
| 479 | { X86::AND8rr, X86::AND8rm }, |
| 480 | { X86::ANDNPDrr, X86::ANDNPDrm }, |
| 481 | { X86::ANDNPSrr, X86::ANDNPSrm }, |
| 482 | { X86::ANDPDrr, X86::ANDPDrm }, |
| 483 | { X86::ANDPSrr, X86::ANDPSrm }, |
| 484 | { X86::CMOVA16rr, X86::CMOVA16rm }, |
| 485 | { X86::CMOVA32rr, X86::CMOVA32rm }, |
| 486 | { X86::CMOVA64rr, X86::CMOVA64rm }, |
| 487 | { X86::CMOVAE16rr, X86::CMOVAE16rm }, |
| 488 | { X86::CMOVAE32rr, X86::CMOVAE32rm }, |
| 489 | { X86::CMOVAE64rr, X86::CMOVAE64rm }, |
| 490 | { X86::CMOVB16rr, X86::CMOVB16rm }, |
| 491 | { X86::CMOVB32rr, X86::CMOVB32rm }, |
| 492 | { X86::CMOVB64rr, X86::CMOVB64rm }, |
| 493 | { X86::CMOVBE16rr, X86::CMOVBE16rm }, |
| 494 | { X86::CMOVBE32rr, X86::CMOVBE32rm }, |
| 495 | { X86::CMOVBE64rr, X86::CMOVBE64rm }, |
| 496 | { X86::CMOVE16rr, X86::CMOVE16rm }, |
| 497 | { X86::CMOVE32rr, X86::CMOVE32rm }, |
| 498 | { X86::CMOVE64rr, X86::CMOVE64rm }, |
| 499 | { X86::CMOVG16rr, X86::CMOVG16rm }, |
| 500 | { X86::CMOVG32rr, X86::CMOVG32rm }, |
| 501 | { X86::CMOVG64rr, X86::CMOVG64rm }, |
| 502 | { X86::CMOVGE16rr, X86::CMOVGE16rm }, |
| 503 | { X86::CMOVGE32rr, X86::CMOVGE32rm }, |
| 504 | { X86::CMOVGE64rr, X86::CMOVGE64rm }, |
| 505 | { X86::CMOVL16rr, X86::CMOVL16rm }, |
| 506 | { X86::CMOVL32rr, X86::CMOVL32rm }, |
| 507 | { X86::CMOVL64rr, X86::CMOVL64rm }, |
| 508 | { X86::CMOVLE16rr, X86::CMOVLE16rm }, |
| 509 | { X86::CMOVLE32rr, X86::CMOVLE32rm }, |
| 510 | { X86::CMOVLE64rr, X86::CMOVLE64rm }, |
| 511 | { X86::CMOVNE16rr, X86::CMOVNE16rm }, |
| 512 | { X86::CMOVNE32rr, X86::CMOVNE32rm }, |
| 513 | { X86::CMOVNE64rr, X86::CMOVNE64rm }, |
| 514 | { X86::CMOVNP16rr, X86::CMOVNP16rm }, |
| 515 | { X86::CMOVNP32rr, X86::CMOVNP32rm }, |
| 516 | { X86::CMOVNP64rr, X86::CMOVNP64rm }, |
| 517 | { X86::CMOVNS16rr, X86::CMOVNS16rm }, |
| 518 | { X86::CMOVNS32rr, X86::CMOVNS32rm }, |
| 519 | { X86::CMOVNS64rr, X86::CMOVNS64rm }, |
| 520 | { X86::CMOVP16rr, X86::CMOVP16rm }, |
| 521 | { X86::CMOVP32rr, X86::CMOVP32rm }, |
| 522 | { X86::CMOVP64rr, X86::CMOVP64rm }, |
| 523 | { X86::CMOVS16rr, X86::CMOVS16rm }, |
| 524 | { X86::CMOVS32rr, X86::CMOVS32rm }, |
| 525 | { X86::CMOVS64rr, X86::CMOVS64rm }, |
| 526 | { X86::CMPPDrri, X86::CMPPDrmi }, |
| 527 | { X86::CMPPSrri, X86::CMPPSrmi }, |
| 528 | { X86::CMPSDrr, X86::CMPSDrm }, |
| 529 | { X86::CMPSSrr, X86::CMPSSrm }, |
| 530 | { X86::DIVPDrr, X86::DIVPDrm }, |
| 531 | { X86::DIVPSrr, X86::DIVPSrm }, |
| 532 | { X86::DIVSDrr, X86::DIVSDrm }, |
| 533 | { X86::DIVSSrr, X86::DIVSSrm }, |
| 534 | { X86::HADDPDrr, X86::HADDPDrm }, |
| 535 | { X86::HADDPSrr, X86::HADDPSrm }, |
| 536 | { X86::HSUBPDrr, X86::HSUBPDrm }, |
| 537 | { X86::HSUBPSrr, X86::HSUBPSrm }, |
| 538 | { X86::IMUL16rr, X86::IMUL16rm }, |
| 539 | { X86::IMUL32rr, X86::IMUL32rm }, |
| 540 | { X86::IMUL64rr, X86::IMUL64rm }, |
| 541 | { X86::MAXPDrr, X86::MAXPDrm }, |
| 542 | { X86::MAXPDrr_Int, X86::MAXPDrm_Int }, |
| 543 | { X86::MAXPSrr, X86::MAXPSrm }, |
| 544 | { X86::MAXPSrr_Int, X86::MAXPSrm_Int }, |
| 545 | { X86::MAXSDrr, X86::MAXSDrm }, |
| 546 | { X86::MAXSDrr_Int, X86::MAXSDrm_Int }, |
| 547 | { X86::MAXSSrr, X86::MAXSSrm }, |
| 548 | { X86::MAXSSrr_Int, X86::MAXSSrm_Int }, |
| 549 | { X86::MINPDrr, X86::MINPDrm }, |
| 550 | { X86::MINPDrr_Int, X86::MINPDrm_Int }, |
| 551 | { X86::MINPSrr, X86::MINPSrm }, |
| 552 | { X86::MINPSrr_Int, X86::MINPSrm_Int }, |
| 553 | { X86::MINSDrr, X86::MINSDrm }, |
| 554 | { X86::MINSDrr_Int, X86::MINSDrm_Int }, |
| 555 | { X86::MINSSrr, X86::MINSSrm }, |
| 556 | { X86::MINSSrr_Int, X86::MINSSrm_Int }, |
| 557 | { X86::MULPDrr, X86::MULPDrm }, |
| 558 | { X86::MULPSrr, X86::MULPSrm }, |
| 559 | { X86::MULSDrr, X86::MULSDrm }, |
| 560 | { X86::MULSSrr, X86::MULSSrm }, |
| 561 | { X86::OR16rr, X86::OR16rm }, |
| 562 | { X86::OR32rr, X86::OR32rm }, |
| 563 | { X86::OR64rr, X86::OR64rm }, |
| 564 | { X86::OR8rr, X86::OR8rm }, |
| 565 | { X86::ORPDrr, X86::ORPDrm }, |
| 566 | { X86::ORPSrr, X86::ORPSrm }, |
| 567 | { X86::PACKSSDWrr, X86::PACKSSDWrm }, |
| 568 | { X86::PACKSSWBrr, X86::PACKSSWBrm }, |
| 569 | { X86::PACKUSWBrr, X86::PACKUSWBrm }, |
| 570 | { X86::PADDBrr, X86::PADDBrm }, |
| 571 | { X86::PADDDrr, X86::PADDDrm }, |
| 572 | { X86::PADDQrr, X86::PADDQrm }, |
| 573 | { X86::PADDSBrr, X86::PADDSBrm }, |
| 574 | { X86::PADDSWrr, X86::PADDSWrm }, |
| 575 | { X86::PADDWrr, X86::PADDWrm }, |
| 576 | { X86::PANDNrr, X86::PANDNrm }, |
| 577 | { X86::PANDrr, X86::PANDrm }, |
| 578 | { X86::PAVGBrr, X86::PAVGBrm }, |
| 579 | { X86::PAVGWrr, X86::PAVGWrm }, |
| 580 | { X86::PCMPEQBrr, X86::PCMPEQBrm }, |
| 581 | { X86::PCMPEQDrr, X86::PCMPEQDrm }, |
| 582 | { X86::PCMPEQWrr, X86::PCMPEQWrm }, |
| 583 | { X86::PCMPGTBrr, X86::PCMPGTBrm }, |
| 584 | { X86::PCMPGTDrr, X86::PCMPGTDrm }, |
| 585 | { X86::PCMPGTWrr, X86::PCMPGTWrm }, |
| 586 | { X86::PINSRWrri, X86::PINSRWrmi }, |
| 587 | { X86::PMADDWDrr, X86::PMADDWDrm }, |
| 588 | { X86::PMAXSWrr, X86::PMAXSWrm }, |
| 589 | { X86::PMAXUBrr, X86::PMAXUBrm }, |
| 590 | { X86::PMINSWrr, X86::PMINSWrm }, |
| 591 | { X86::PMINUBrr, X86::PMINUBrm }, |
| 592 | { X86::PMULHUWrr, X86::PMULHUWrm }, |
| 593 | { X86::PMULHWrr, X86::PMULHWrm }, |
| 594 | { X86::PMULLWrr, X86::PMULLWrm }, |
| 595 | { X86::PMULUDQrr, X86::PMULUDQrm }, |
| 596 | { X86::PORrr, X86::PORrm }, |
| 597 | { X86::PSADBWrr, X86::PSADBWrm }, |
| 598 | { X86::PSLLDrr, X86::PSLLDrm }, |
| 599 | { X86::PSLLQrr, X86::PSLLQrm }, |
| 600 | { X86::PSLLWrr, X86::PSLLWrm }, |
| 601 | { X86::PSRADrr, X86::PSRADrm }, |
| 602 | { X86::PSRAWrr, X86::PSRAWrm }, |
| 603 | { X86::PSRLDrr, X86::PSRLDrm }, |
| 604 | { X86::PSRLQrr, X86::PSRLQrm }, |
| 605 | { X86::PSRLWrr, X86::PSRLWrm }, |
| 606 | { X86::PSUBBrr, X86::PSUBBrm }, |
| 607 | { X86::PSUBDrr, X86::PSUBDrm }, |
| 608 | { X86::PSUBSBrr, X86::PSUBSBrm }, |
| 609 | { X86::PSUBSWrr, X86::PSUBSWrm }, |
| 610 | { X86::PSUBWrr, X86::PSUBWrm }, |
| 611 | { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm }, |
| 612 | { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm }, |
| 613 | { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm }, |
| 614 | { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm }, |
| 615 | { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm }, |
| 616 | { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm }, |
| 617 | { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm }, |
| 618 | { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm }, |
| 619 | { X86::PXORrr, X86::PXORrm }, |
| 620 | { X86::SBB32rr, X86::SBB32rm }, |
| 621 | { X86::SBB64rr, X86::SBB64rm }, |
| 622 | { X86::SHUFPDrri, X86::SHUFPDrmi }, |
| 623 | { X86::SHUFPSrri, X86::SHUFPSrmi }, |
| 624 | { X86::SUB16rr, X86::SUB16rm }, |
| 625 | { X86::SUB32rr, X86::SUB32rm }, |
| 626 | { X86::SUB64rr, X86::SUB64rm }, |
| 627 | { X86::SUB8rr, X86::SUB8rm }, |
| 628 | { X86::SUBPDrr, X86::SUBPDrm }, |
| 629 | { X86::SUBPSrr, X86::SUBPSrm }, |
| 630 | { X86::SUBSDrr, X86::SUBSDrm }, |
| 631 | { X86::SUBSSrr, X86::SUBSSrm }, |
| 632 | // FIXME: TEST*rr -> swapped operand of TEST*mr. |
| 633 | { X86::UNPCKHPDrr, X86::UNPCKHPDrm }, |
| 634 | { X86::UNPCKHPSrr, X86::UNPCKHPSrm }, |
| 635 | { X86::UNPCKLPDrr, X86::UNPCKLPDrm }, |
| 636 | { X86::UNPCKLPSrr, X86::UNPCKLPSrm }, |
| 637 | { X86::XOR16rr, X86::XOR16rm }, |
| 638 | { X86::XOR32rr, X86::XOR32rm }, |
| 639 | { X86::XOR64rr, X86::XOR64rm }, |
| 640 | { X86::XOR8rr, X86::XOR8rm }, |
| 641 | { X86::XORPDrr, X86::XORPDrm }, |
| 642 | { X86::XORPSrr, X86::XORPSrm } |
| 643 | }; |
| 644 | |
| 645 | for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { |
| 646 | unsigned RegOp = OpTbl2[i][0]; |
| 647 | unsigned MemOp = OpTbl2[i][1]; |
| 648 | if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 649 | assert(false && "Duplicated entries?"); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 650 | unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load |
| 651 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 652 | std::make_pair(RegOp, AuxInfo)))) |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 653 | AmbEntries.push_back(MemOp); |
| 654 | } |
| 655 | |
| 656 | // Remove ambiguous entries. |
Evan Cheng | f7c9695 | 2007-10-19 23:50:58 +0000 | [diff] [blame] | 657 | assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 658 | } |
Chris Lattner | 7ad3e06 | 2003-08-03 15:48:14 +0000 | [diff] [blame] | 659 | |
Dale Johannesen | 483ec21 | 2007-11-07 00:25:05 +0000 | [diff] [blame] | 660 | // getDwarfRegNum - This function maps LLVM register identifiers to the |
| 661 | // Dwarf specific numbering, used in debug info and exception tables. |
Dale Johannesen | 4542edc | 2007-11-07 21:48:35 +0000 | [diff] [blame] | 662 | |
Dale Johannesen | b97aec6 | 2007-11-13 19:13:01 +0000 | [diff] [blame] | 663 | int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { |
Dale Johannesen | 483ec21 | 2007-11-07 00:25:05 +0000 | [diff] [blame] | 664 | const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 665 | unsigned Flavour = DWARFFlavour::X86_64; |
Dale Johannesen | 7a42f24 | 2007-11-09 18:07:11 +0000 | [diff] [blame] | 666 | if (!Subtarget->is64Bit()) { |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 667 | if (Subtarget->isTargetDarwin()) { |
| 668 | Flavour = DWARFFlavour::X86_32_Darwin; |
| 669 | } else if (Subtarget->isTargetCygMing()) { |
| 670 | // Unsupported by now, just quick fallback |
| 671 | Flavour = DWARFFlavour::X86_32_ELF; |
| 672 | } else { |
| 673 | Flavour = DWARFFlavour::X86_32_ELF; |
Dale Johannesen | 7a42f24 | 2007-11-09 18:07:11 +0000 | [diff] [blame] | 674 | } |
Dale Johannesen | 483ec21 | 2007-11-07 00:25:05 +0000 | [diff] [blame] | 675 | } |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 676 | |
| 677 | return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour); |
Dale Johannesen | 483ec21 | 2007-11-07 00:25:05 +0000 | [diff] [blame] | 678 | } |
| 679 | |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 680 | // getX86RegNum - This function maps LLVM register identifiers to their X86 |
| 681 | // specific numbering, which is used in various places encoding instructions. |
| 682 | // |
| 683 | unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { |
| 684 | switch(RegNo) { |
| 685 | case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; |
| 686 | case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; |
| 687 | case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; |
| 688 | case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; |
| 689 | case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: |
| 690 | return N86::ESP; |
| 691 | case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: |
| 692 | return N86::EBP; |
| 693 | case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: |
| 694 | return N86::ESI; |
| 695 | case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: |
| 696 | return N86::EDI; |
| 697 | |
| 698 | case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: |
| 699 | return N86::EAX; |
| 700 | case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: |
| 701 | return N86::ECX; |
| 702 | case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: |
| 703 | return N86::EDX; |
| 704 | case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: |
| 705 | return N86::EBX; |
| 706 | case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: |
| 707 | return N86::ESP; |
| 708 | case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: |
| 709 | return N86::EBP; |
| 710 | case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: |
| 711 | return N86::ESI; |
| 712 | case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: |
| 713 | return N86::EDI; |
| 714 | |
| 715 | case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3: |
| 716 | case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7: |
| 717 | return RegNo-X86::ST0; |
| 718 | |
Nate Begeman | 6e041c2 | 2007-12-11 18:06:14 +0000 | [diff] [blame] | 719 | case X86::XMM0: case X86::XMM8: case X86::MM0: |
Evan Cheng | e7c8754 | 2007-11-13 17:54:34 +0000 | [diff] [blame] | 720 | return 0; |
Nate Begeman | 6e041c2 | 2007-12-11 18:06:14 +0000 | [diff] [blame] | 721 | case X86::XMM1: case X86::XMM9: case X86::MM1: |
Evan Cheng | e7c8754 | 2007-11-13 17:54:34 +0000 | [diff] [blame] | 722 | return 1; |
Nate Begeman | 6e041c2 | 2007-12-11 18:06:14 +0000 | [diff] [blame] | 723 | case X86::XMM2: case X86::XMM10: case X86::MM2: |
Evan Cheng | e7c8754 | 2007-11-13 17:54:34 +0000 | [diff] [blame] | 724 | return 2; |
Nate Begeman | 6e041c2 | 2007-12-11 18:06:14 +0000 | [diff] [blame] | 725 | case X86::XMM3: case X86::XMM11: case X86::MM3: |
Evan Cheng | e7c8754 | 2007-11-13 17:54:34 +0000 | [diff] [blame] | 726 | return 3; |
Nate Begeman | 6e041c2 | 2007-12-11 18:06:14 +0000 | [diff] [blame] | 727 | case X86::XMM4: case X86::XMM12: case X86::MM4: |
Evan Cheng | e7c8754 | 2007-11-13 17:54:34 +0000 | [diff] [blame] | 728 | return 4; |
Nate Begeman | 6e041c2 | 2007-12-11 18:06:14 +0000 | [diff] [blame] | 729 | case X86::XMM5: case X86::XMM13: case X86::MM5: |
Evan Cheng | e7c8754 | 2007-11-13 17:54:34 +0000 | [diff] [blame] | 730 | return 5; |
Nate Begeman | 6e041c2 | 2007-12-11 18:06:14 +0000 | [diff] [blame] | 731 | case X86::XMM6: case X86::XMM14: case X86::MM6: |
Evan Cheng | e7c8754 | 2007-11-13 17:54:34 +0000 | [diff] [blame] | 732 | return 6; |
Nate Begeman | 6e041c2 | 2007-12-11 18:06:14 +0000 | [diff] [blame] | 733 | case X86::XMM7: case X86::XMM15: case X86::MM7: |
Evan Cheng | e7c8754 | 2007-11-13 17:54:34 +0000 | [diff] [blame] | 734 | return 7; |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 735 | |
| 736 | default: |
| 737 | assert(isVirtualRegister(RegNo) && "Unknown physical register!"); |
| 738 | assert(0 && "Register allocator hasn't allocated reg correctly yet!"); |
| 739 | return 0; |
| 740 | } |
| 741 | } |
| 742 | |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 743 | bool X86RegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 744 | MachineBasicBlock::iterator MI, |
| 745 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 746 | if (CSI.empty()) |
| 747 | return false; |
| 748 | |
| 749 | MachineFunction &MF = *MBB.getParent(); |
| 750 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
| 751 | X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize); |
| 752 | unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r; |
| 753 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 754 | unsigned Reg = CSI[i-1].getReg(); |
| 755 | // Add the callee-saved register as live-in. It's killed at the spill. |
| 756 | MBB.addLiveIn(Reg); |
| 757 | BuildMI(MBB, MI, TII.get(Opc)).addReg(Reg); |
| 758 | } |
| 759 | return true; |
| 760 | } |
| 761 | |
| 762 | bool X86RegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 763 | MachineBasicBlock::iterator MI, |
| 764 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 765 | if (CSI.empty()) |
| 766 | return false; |
| 767 | |
| 768 | unsigned Opc = Is64Bit ? X86::POP64r : X86::POP32r; |
| 769 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 770 | unsigned Reg = CSI[i].getReg(); |
| 771 | BuildMI(MBB, MI, TII.get(Opc), Reg); |
| 772 | } |
| 773 | return true; |
| 774 | } |
| 775 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 776 | static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB, |
| 777 | MachineOperand &MO) { |
| 778 | if (MO.isRegister()) |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 779 | MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(), |
| 780 | false, false, MO.getSubReg()); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 781 | else if (MO.isImmediate()) |
| 782 | MIB = MIB.addImm(MO.getImm()); |
| 783 | else if (MO.isFrameIndex()) |
| 784 | MIB = MIB.addFrameIndex(MO.getFrameIndex()); |
| 785 | else if (MO.isGlobalAddress()) |
| 786 | MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset()); |
| 787 | else if (MO.isConstantPoolIndex()) |
| 788 | MIB = MIB.addConstantPoolIndex(MO.getConstantPoolIndex(), MO.getOffset()); |
| 789 | else if (MO.isJumpTableIndex()) |
| 790 | MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex()); |
| 791 | else if (MO.isExternalSymbol()) |
| 792 | MIB = MIB.addExternalSymbol(MO.getSymbolName()); |
| 793 | else |
| 794 | assert(0 && "Unknown operand for X86InstrAddOperand!"); |
| 795 | |
| 796 | return MIB; |
| 797 | } |
| 798 | |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 799 | static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, |
| 800 | unsigned StackAlign) { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 801 | unsigned Opc = 0; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 802 | if (RC == &X86::GR64RegClass) { |
| 803 | Opc = X86::MOV64mr; |
| 804 | } else if (RC == &X86::GR32RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 805 | Opc = X86::MOV32mr; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 806 | } else if (RC == &X86::GR16RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 807 | Opc = X86::MOV16mr; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 808 | } else if (RC == &X86::GR8RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 809 | Opc = X86::MOV8mr; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 810 | } else if (RC == &X86::GR32_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 811 | Opc = X86::MOV32_mr; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 812 | } else if (RC == &X86::GR16_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 813 | Opc = X86::MOV16_mr; |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 814 | } else if (RC == &X86::RFP80RegClass) { |
| 815 | Opc = X86::ST_FpP80m; // pops |
Dale Johannesen | ca8035e | 2007-09-17 20:15:38 +0000 | [diff] [blame] | 816 | } else if (RC == &X86::RFP64RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 817 | Opc = X86::ST_Fp64m; |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 818 | } else if (RC == &X86::RFP32RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 819 | Opc = X86::ST_Fp32m; |
Evan Cheng | 19ade3b | 2006-02-16 21:20:26 +0000 | [diff] [blame] | 820 | } else if (RC == &X86::FR32RegClass) { |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 821 | Opc = X86::MOVSSmr; |
Evan Cheng | 19ade3b | 2006-02-16 21:20:26 +0000 | [diff] [blame] | 822 | } else if (RC == &X86::FR64RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 823 | Opc = X86::MOVSDmr; |
Evan Cheng | 2246f84 | 2006-03-18 01:23:20 +0000 | [diff] [blame] | 824 | } else if (RC == &X86::VR128RegClass) { |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 825 | // FIXME: Use movaps once we are capable of selectively |
| 826 | // aligning functions that spill SSE registers on 16-byte boundaries. |
| 827 | Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr; |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 828 | } else if (RC == &X86::VR64RegClass) { |
Bill Wendling | c9c9d2d | 2007-04-03 06:18:31 +0000 | [diff] [blame] | 829 | Opc = X86::MMX_MOVQ64mr; |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 830 | } else { |
| 831 | assert(0 && "Unknown regclass"); |
| 832 | abort(); |
| 833 | } |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 834 | |
| 835 | return Opc; |
| 836 | } |
| 837 | |
| 838 | void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| 839 | MachineBasicBlock::iterator MI, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 840 | unsigned SrcReg, bool isKill, int FrameIdx, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 841 | const TargetRegisterClass *RC) const { |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 842 | unsigned Opc = getStoreRegOpcode(RC, StackAlign); |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 843 | addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 844 | .addReg(SrcReg, false, false, isKill); |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 845 | } |
| 846 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 847 | void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 848 | bool isKill, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 849 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 850 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 851 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 852 | unsigned Opc = getStoreRegOpcode(RC, StackAlign); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 853 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc)); |
| 854 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) |
| 855 | MIB = X86InstrAddOperand(MIB, Addr[i]); |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 856 | MIB.addReg(SrcReg, false, false, isKill); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 857 | NewMIs.push_back(MIB); |
| 858 | } |
| 859 | |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 860 | static unsigned getLoadRegOpcode(const TargetRegisterClass *RC, |
| 861 | unsigned StackAlign) { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 862 | unsigned Opc = 0; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 863 | if (RC == &X86::GR64RegClass) { |
| 864 | Opc = X86::MOV64rm; |
| 865 | } else if (RC == &X86::GR32RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 866 | Opc = X86::MOV32rm; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 867 | } else if (RC == &X86::GR16RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 868 | Opc = X86::MOV16rm; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 869 | } else if (RC == &X86::GR8RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 870 | Opc = X86::MOV8rm; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 871 | } else if (RC == &X86::GR32_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 872 | Opc = X86::MOV32_rm; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 873 | } else if (RC == &X86::GR16_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 874 | Opc = X86::MOV16_rm; |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 875 | } else if (RC == &X86::RFP80RegClass) { |
| 876 | Opc = X86::LD_Fp80m; |
Dale Johannesen | ca8035e | 2007-09-17 20:15:38 +0000 | [diff] [blame] | 877 | } else if (RC == &X86::RFP64RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 878 | Opc = X86::LD_Fp64m; |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 879 | } else if (RC == &X86::RFP32RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 880 | Opc = X86::LD_Fp32m; |
Evan Cheng | 19ade3b | 2006-02-16 21:20:26 +0000 | [diff] [blame] | 881 | } else if (RC == &X86::FR32RegClass) { |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 882 | Opc = X86::MOVSSrm; |
Evan Cheng | 19ade3b | 2006-02-16 21:20:26 +0000 | [diff] [blame] | 883 | } else if (RC == &X86::FR64RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 884 | Opc = X86::MOVSDrm; |
Evan Cheng | 2246f84 | 2006-03-18 01:23:20 +0000 | [diff] [blame] | 885 | } else if (RC == &X86::VR128RegClass) { |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 886 | // FIXME: Use movaps once we are capable of selectively |
| 887 | // aligning functions that spill SSE registers on 16-byte boundaries. |
| 888 | Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm; |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 889 | } else if (RC == &X86::VR64RegClass) { |
Bill Wendling | c9c9d2d | 2007-04-03 06:18:31 +0000 | [diff] [blame] | 890 | Opc = X86::MMX_MOVQ64rm; |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 891 | } else { |
| 892 | assert(0 && "Unknown regclass"); |
| 893 | abort(); |
| 894 | } |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 895 | |
| 896 | return Opc; |
| 897 | } |
| 898 | |
| 899 | void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 900 | MachineBasicBlock::iterator MI, |
| 901 | unsigned DestReg, int FrameIdx, |
| 902 | const TargetRegisterClass *RC) const{ |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 903 | unsigned Opc = getLoadRegOpcode(RC, StackAlign); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 904 | addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx); |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 905 | } |
| 906 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 907 | void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 908 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 909 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 910 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 911 | unsigned Opc = getLoadRegOpcode(RC, StackAlign); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 912 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); |
| 913 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) |
| 914 | MIB = X86InstrAddOperand(MIB, Addr[i]); |
| 915 | NewMIs.push_back(MIB); |
| 916 | } |
| 917 | |
Chris Lattner | 01d0efb | 2004-08-15 22:15:11 +0000 | [diff] [blame] | 918 | void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 919 | MachineBasicBlock::iterator MI, |
| 920 | unsigned DestReg, unsigned SrcReg, |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 921 | const TargetRegisterClass *DestRC, |
| 922 | const TargetRegisterClass *SrcRC) const { |
| 923 | if (DestRC != SrcRC) { |
Evan Cheng | ff11026 | 2007-09-26 21:31:07 +0000 | [diff] [blame] | 924 | // Moving EFLAGS to / from another register requires a push and a pop. |
| 925 | if (SrcRC == &X86::CCRRegClass) { |
| 926 | assert(SrcReg == X86::EFLAGS); |
| 927 | if (DestRC == &X86::GR64RegClass) { |
| 928 | BuildMI(MBB, MI, TII.get(X86::PUSHFQ)); |
| 929 | BuildMI(MBB, MI, TII.get(X86::POP64r), DestReg); |
| 930 | return; |
| 931 | } else if (DestRC == &X86::GR32RegClass) { |
| 932 | BuildMI(MBB, MI, TII.get(X86::PUSHFD)); |
| 933 | BuildMI(MBB, MI, TII.get(X86::POP32r), DestReg); |
| 934 | return; |
| 935 | } |
| 936 | } else if (DestRC == &X86::CCRRegClass) { |
| 937 | assert(DestReg == X86::EFLAGS); |
| 938 | if (SrcRC == &X86::GR64RegClass) { |
| 939 | BuildMI(MBB, MI, TII.get(X86::PUSH64r)).addReg(SrcReg); |
| 940 | BuildMI(MBB, MI, TII.get(X86::POPFQ)); |
| 941 | return; |
| 942 | } else if (SrcRC == &X86::GR32RegClass) { |
| 943 | BuildMI(MBB, MI, TII.get(X86::PUSH32r)).addReg(SrcReg); |
| 944 | BuildMI(MBB, MI, TII.get(X86::POPFD)); |
| 945 | return; |
| 946 | } |
| 947 | } |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 948 | cerr << "Not yet supported!"; |
| 949 | abort(); |
| 950 | } |
| 951 | |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 952 | unsigned Opc; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 953 | if (DestRC == &X86::GR64RegClass) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 954 | Opc = X86::MOV64rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 955 | } else if (DestRC == &X86::GR32RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 956 | Opc = X86::MOV32rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 957 | } else if (DestRC == &X86::GR16RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 958 | Opc = X86::MOV16rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 959 | } else if (DestRC == &X86::GR8RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 960 | Opc = X86::MOV8rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 961 | } else if (DestRC == &X86::GR32_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 962 | Opc = X86::MOV32_rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 963 | } else if (DestRC == &X86::GR16_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 964 | Opc = X86::MOV16_rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 965 | } else if (DestRC == &X86::RFP32RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 966 | Opc = X86::MOV_Fp3232; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 967 | } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 968 | Opc = X86::MOV_Fp6464; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 969 | } else if (DestRC == &X86::RFP80RegClass) { |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 970 | Opc = X86::MOV_Fp8080; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 971 | } else if (DestRC == &X86::FR32RegClass) { |
Evan Cheng | fe5cb19 | 2006-02-16 22:45:17 +0000 | [diff] [blame] | 972 | Opc = X86::FsMOVAPSrr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 973 | } else if (DestRC == &X86::FR64RegClass) { |
Evan Cheng | fe5cb19 | 2006-02-16 22:45:17 +0000 | [diff] [blame] | 974 | Opc = X86::FsMOVAPDrr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 975 | } else if (DestRC == &X86::VR128RegClass) { |
Evan Cheng | a964ccd | 2006-04-10 07:21:31 +0000 | [diff] [blame] | 976 | Opc = X86::MOVAPSrr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 977 | } else if (DestRC == &X86::VR64RegClass) { |
Bill Wendling | c9c9d2d | 2007-04-03 06:18:31 +0000 | [diff] [blame] | 978 | Opc = X86::MMX_MOVQ64rr; |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 979 | } else { |
| 980 | assert(0 && "Unknown regclass"); |
| 981 | abort(); |
| 982 | } |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 983 | BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg); |
Misha Brukman | 2b46e8e | 2002-12-13 09:54:12 +0000 | [diff] [blame] | 984 | } |
| 985 | |
Evan Cheng | ff11026 | 2007-09-26 21:31:07 +0000 | [diff] [blame] | 986 | const TargetRegisterClass * |
| 987 | X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { |
| 988 | if (RC == &X86::CCRRegClass) |
Evan Cheng | 3f2d9ec | 2007-09-27 21:50:05 +0000 | [diff] [blame] | 989 | if (Is64Bit) |
| 990 | return &X86::GR64RegClass; |
| 991 | else |
| 992 | return &X86::GR32RegClass; |
Evan Cheng | ff11026 | 2007-09-26 21:31:07 +0000 | [diff] [blame] | 993 | return NULL; |
| 994 | } |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 995 | |
| 996 | void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB, |
| 997 | MachineBasicBlock::iterator I, |
| 998 | unsigned DestReg, |
| 999 | const MachineInstr *Orig) const { |
Evan Cheng | b0869ed | 2007-09-10 20:48:53 +0000 | [diff] [blame] | 1000 | // MOV32r0 etc. are implemented with xor which clobbers condition code. |
| 1001 | // Re-materialize them as movri instructions to avoid side effects. |
| 1002 | switch (Orig->getOpcode()) { |
| 1003 | case X86::MOV8r0: |
| 1004 | BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0); |
| 1005 | break; |
| 1006 | case X86::MOV16r0: |
| 1007 | BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0); |
| 1008 | break; |
| 1009 | case X86::MOV32r0: |
| 1010 | BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0); |
| 1011 | break; |
| 1012 | case X86::MOV64r0: |
| 1013 | BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0); |
| 1014 | break; |
| 1015 | default: { |
| 1016 | MachineInstr *MI = Orig->clone(); |
| 1017 | MI->getOperand(0).setReg(DestReg); |
| 1018 | MBB.insert(I, MI); |
| 1019 | break; |
| 1020 | } |
| 1021 | } |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 1022 | } |
| 1023 | |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1024 | static MachineInstr *FuseTwoAddrInst(unsigned Opcode, |
| 1025 | SmallVector<MachineOperand,4> &MOs, |
| 1026 | MachineInstr *MI, const TargetInstrInfo &TII) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1027 | // Create the base instruction with the memory operand as the first part. |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1028 | MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true); |
| 1029 | MachineInstrBuilder MIB(NewMI); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1030 | unsigned NumAddrOps = MOs.size(); |
| 1031 | for (unsigned i = 0; i != NumAddrOps; ++i) |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1032 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1033 | if (NumAddrOps < 4) // FrameIndex only |
| 1034 | MIB.addImm(1).addReg(0).addImm(0); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1035 | |
| 1036 | // Loop over the rest of the ri operands, converting them over. |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1037 | unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1038 | for (unsigned i = 0; i != NumOps; ++i) { |
Evan Cheng | 6f34b43 | 2006-09-08 21:08:13 +0000 | [diff] [blame] | 1039 | MachineOperand &MO = MI->getOperand(i+2); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1040 | MIB = X86InstrAddOperand(MIB, MO); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1041 | } |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1042 | for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { |
| 1043 | MachineOperand &MO = MI->getOperand(i); |
| 1044 | MIB = X86InstrAddOperand(MIB, MO); |
| 1045 | } |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1046 | return MIB; |
Alkis Evlogimenos | 89b0214 | 2004-02-17 08:49:20 +0000 | [diff] [blame] | 1047 | } |
| 1048 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1049 | static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1050 | SmallVector<MachineOperand,4> &MOs, |
| 1051 | MachineInstr *MI, const TargetInstrInfo &TII) { |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1052 | MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true); |
| 1053 | MachineInstrBuilder MIB(NewMI); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1054 | |
| 1055 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 1056 | MachineOperand &MO = MI->getOperand(i); |
| 1057 | if (i == OpNo) { |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 1058 | assert(MO.isRegister() && "Expected to fold into reg operand!"); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1059 | unsigned NumAddrOps = MOs.size(); |
| 1060 | for (unsigned i = 0; i != NumAddrOps; ++i) |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1061 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1062 | if (NumAddrOps < 4) // FrameIndex only |
| 1063 | MIB.addImm(1).addReg(0).addImm(0); |
| 1064 | } else { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1065 | MIB = X86InstrAddOperand(MIB, MO); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1066 | } |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1067 | } |
| 1068 | return MIB; |
Chris Lattner | 7c035b7 | 2004-02-17 05:35:13 +0000 | [diff] [blame] | 1069 | } |
| 1070 | |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1071 | static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, |
| 1072 | SmallVector<MachineOperand,4> &MOs, |
Evan Cheng | 8586b95 | 2006-03-17 02:36:22 +0000 | [diff] [blame] | 1073 | MachineInstr *MI) { |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1074 | MachineInstrBuilder MIB = BuildMI(TII.get(Opcode)); |
| 1075 | |
| 1076 | unsigned NumAddrOps = MOs.size(); |
| 1077 | for (unsigned i = 0; i != NumAddrOps; ++i) |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1078 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1079 | if (NumAddrOps < 4) // FrameIndex only |
| 1080 | MIB.addImm(1).addReg(0).addImm(0); |
| 1081 | return MIB.addImm(0); |
Evan Cheng | 8586b95 | 2006-03-17 02:36:22 +0000 | [diff] [blame] | 1082 | } |
| 1083 | |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1084 | MachineInstr* |
| 1085 | X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, |
| 1086 | SmallVector<MachineOperand,4> &MOs) const { |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1087 | const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1088 | bool isTwoAddrFold = false; |
Evan Cheng | 171d09e | 2006-11-10 01:28:43 +0000 | [diff] [blame] | 1089 | unsigned NumOps = TII.getNumOperands(MI->getOpcode()); |
| 1090 | bool isTwoAddr = NumOps > 1 && |
Evan Cheng | 51cdcd1 | 2006-12-07 01:21:59 +0000 | [diff] [blame] | 1091 | MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1; |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1092 | |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1093 | MachineInstr *NewMI = NULL; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1094 | // Folding a memory location into the two-address part of a two-address |
| 1095 | // instruction is different than folding it other places. It requires |
| 1096 | // replacing the *two* registers with the memory location. |
Evan Cheng | 171d09e | 2006-11-10 01:28:43 +0000 | [diff] [blame] | 1097 | if (isTwoAddr && NumOps >= 2 && i < 2 && |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 1098 | MI->getOperand(0).isRegister() && |
| 1099 | MI->getOperand(1).isRegister() && |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1100 | MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1101 | OpcodeTablePtr = &RegOp2MemOpTable2Addr; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1102 | isTwoAddrFold = true; |
| 1103 | } else if (i == 0) { // If operand 0 |
| 1104 | if (MI->getOpcode() == X86::MOV16r0) |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1105 | NewMI = MakeM0Inst(TII, X86::MOV16mi, MOs, MI); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1106 | else if (MI->getOpcode() == X86::MOV32r0) |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1107 | NewMI = MakeM0Inst(TII, X86::MOV32mi, MOs, MI); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1108 | else if (MI->getOpcode() == X86::MOV64r0) |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1109 | NewMI = MakeM0Inst(TII, X86::MOV64mi32, MOs, MI); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1110 | else if (MI->getOpcode() == X86::MOV8r0) |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1111 | NewMI = MakeM0Inst(TII, X86::MOV8mi, MOs, MI); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1112 | if (NewMI) { |
| 1113 | NewMI->copyKillDeadInfo(MI); |
| 1114 | return NewMI; |
| 1115 | } |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1116 | |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1117 | OpcodeTablePtr = &RegOp2MemOpTable0; |
Chris Lattner | 7c035b7 | 2004-02-17 05:35:13 +0000 | [diff] [blame] | 1118 | } else if (i == 1) { |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1119 | OpcodeTablePtr = &RegOp2MemOpTable1; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1120 | } else if (i == 2) { |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1121 | OpcodeTablePtr = &RegOp2MemOpTable2; |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1122 | } |
| 1123 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1124 | // If table selected... |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1125 | if (OpcodeTablePtr) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1126 | // Find the Opcode to fuse |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1127 | DenseMap<unsigned*, unsigned>::iterator I = |
| 1128 | OpcodeTablePtr->find((unsigned*)MI->getOpcode()); |
| 1129 | if (I != OpcodeTablePtr->end()) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1130 | if (isTwoAddrFold) |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1131 | NewMI = FuseTwoAddrInst(I->second, MOs, MI, TII); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1132 | else |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1133 | NewMI = FuseInst(I->second, i, MOs, MI, TII); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1134 | NewMI->copyKillDeadInfo(MI); |
| 1135 | return NewMI; |
Chris Lattner | 7c035b7 | 2004-02-17 05:35:13 +0000 | [diff] [blame] | 1136 | } |
Alkis Evlogimenos | b499866 | 2004-02-17 04:33:18 +0000 | [diff] [blame] | 1137 | } |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1138 | |
| 1139 | // No fusion |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 1140 | if (PrintFailedFusing) |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 1141 | cerr << "We failed to fuse (" |
| 1142 | << ((i == 1) ? "r" : "s") << "): " << *MI; |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 1143 | return NULL; |
Alkis Evlogimenos | b499866 | 2004-02-17 04:33:18 +0000 | [diff] [blame] | 1144 | } |
| 1145 | |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1146 | |
Evan Cheng | e62f97c | 2007-12-01 02:07:52 +0000 | [diff] [blame] | 1147 | MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 1148 | SmallVectorImpl<unsigned> &Ops, |
Evan Cheng | e62f97c | 2007-12-01 02:07:52 +0000 | [diff] [blame] | 1149 | int FrameIndex) const { |
| 1150 | // Check switch flag |
| 1151 | if (NoFusing) return NULL; |
| 1152 | |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 1153 | if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { |
| 1154 | unsigned NewOpc = 0; |
| 1155 | switch (MI->getOpcode()) { |
| 1156 | default: return NULL; |
| 1157 | case X86::TEST8rr: NewOpc = X86::CMP8ri; break; |
| 1158 | case X86::TEST16rr: NewOpc = X86::CMP16ri; break; |
| 1159 | case X86::TEST32rr: NewOpc = X86::CMP32ri; break; |
| 1160 | case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; |
| 1161 | } |
| 1162 | // Change to CMPXXri r, 0 first. |
| 1163 | MI->setInstrDescriptor(TII.get(NewOpc)); |
| 1164 | MI->getOperand(1).ChangeToImmediate(0); |
| 1165 | } else if (Ops.size() != 1) |
Evan Cheng | e62f97c | 2007-12-01 02:07:52 +0000 | [diff] [blame] | 1166 | return NULL; |
| 1167 | |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 1168 | SmallVector<MachineOperand,4> MOs; |
| 1169 | MOs.push_back(MachineOperand::CreateFrameIndex(FrameIndex)); |
| 1170 | return foldMemoryOperand(MI, Ops[0], MOs); |
Evan Cheng | e62f97c | 2007-12-01 02:07:52 +0000 | [diff] [blame] | 1171 | } |
| 1172 | |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 1173 | MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, |
| 1174 | SmallVectorImpl<unsigned> &Ops, |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1175 | MachineInstr *LoadMI) const { |
| 1176 | // Check switch flag |
| 1177 | if (NoFusing) return NULL; |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 1178 | |
| 1179 | if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { |
| 1180 | unsigned NewOpc = 0; |
| 1181 | switch (MI->getOpcode()) { |
| 1182 | default: return NULL; |
| 1183 | case X86::TEST8rr: NewOpc = X86::CMP8ri; break; |
| 1184 | case X86::TEST16rr: NewOpc = X86::CMP16ri; break; |
| 1185 | case X86::TEST32rr: NewOpc = X86::CMP32ri; break; |
| 1186 | case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; |
| 1187 | } |
| 1188 | // Change to CMPXXri r, 0 first. |
| 1189 | MI->setInstrDescriptor(TII.get(NewOpc)); |
| 1190 | MI->getOperand(1).ChangeToImmediate(0); |
| 1191 | } else if (Ops.size() != 1) |
| 1192 | return NULL; |
| 1193 | |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1194 | SmallVector<MachineOperand,4> MOs; |
| 1195 | unsigned NumOps = TII.getNumOperands(LoadMI->getOpcode()); |
| 1196 | for (unsigned i = NumOps - 4; i != NumOps; ++i) |
| 1197 | MOs.push_back(LoadMI->getOperand(i)); |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 1198 | return foldMemoryOperand(MI, Ops[0], MOs); |
Evan Cheng | e62f97c | 2007-12-01 02:07:52 +0000 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 1202 | bool X86RegisterInfo::canFoldMemoryOperand(MachineInstr *MI, |
| 1203 | SmallVectorImpl<unsigned> &Ops) const { |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1204 | // Check switch flag |
| 1205 | if (NoFusing) return 0; |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 1206 | |
| 1207 | if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { |
| 1208 | switch (MI->getOpcode()) { |
| 1209 | default: return false; |
| 1210 | case X86::TEST8rr: |
| 1211 | case X86::TEST16rr: |
| 1212 | case X86::TEST32rr: |
| 1213 | case X86::TEST64rr: |
| 1214 | return true; |
| 1215 | } |
| 1216 | } |
| 1217 | |
| 1218 | if (Ops.size() != 1) |
| 1219 | return false; |
| 1220 | |
| 1221 | unsigned OpNum = Ops[0]; |
| 1222 | unsigned Opc = MI->getOpcode(); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1223 | unsigned NumOps = TII.getNumOperands(Opc); |
| 1224 | bool isTwoAddr = NumOps > 1 && |
| 1225 | TII.getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1; |
| 1226 | |
| 1227 | // Folding a memory location into the two-address part of a two-address |
| 1228 | // instruction is different than folding it other places. It requires |
| 1229 | // replacing the *two* registers with the memory location. |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 1230 | const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1231 | if (isTwoAddr && NumOps >= 2 && OpNum < 2) { |
| 1232 | OpcodeTablePtr = &RegOp2MemOpTable2Addr; |
| 1233 | } else if (OpNum == 0) { // If operand 0 |
| 1234 | switch (Opc) { |
| 1235 | case X86::MOV16r0: |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1236 | case X86::MOV32r0: |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1237 | case X86::MOV64r0: |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1238 | case X86::MOV8r0: |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 1239 | return true; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1240 | default: break; |
| 1241 | } |
| 1242 | OpcodeTablePtr = &RegOp2MemOpTable0; |
| 1243 | } else if (OpNum == 1) { |
| 1244 | OpcodeTablePtr = &RegOp2MemOpTable1; |
| 1245 | } else if (OpNum == 2) { |
| 1246 | OpcodeTablePtr = &RegOp2MemOpTable2; |
| 1247 | } |
| 1248 | |
| 1249 | if (OpcodeTablePtr) { |
| 1250 | // Find the Opcode to fuse |
| 1251 | DenseMap<unsigned*, unsigned>::iterator I = |
| 1252 | OpcodeTablePtr->find((unsigned*)Opc); |
| 1253 | if (I != OpcodeTablePtr->end()) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 1254 | return true; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1255 | } |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 1256 | return false; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1257 | } |
| 1258 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1259 | bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, |
Evan Cheng | 106e802 | 2007-10-13 02:35:06 +0000 | [diff] [blame] | 1260 | unsigned Reg, bool UnfoldLoad, bool UnfoldStore, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 1261 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1262 | DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = |
| 1263 | MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); |
| 1264 | if (I == MemOp2RegOpTable.end()) |
| 1265 | return false; |
| 1266 | unsigned Opc = I->second.first; |
| 1267 | unsigned Index = I->second.second & 0xf; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1268 | bool FoldedLoad = I->second.second & (1 << 4); |
| 1269 | bool FoldedStore = I->second.second & (1 << 5); |
| 1270 | if (UnfoldLoad && !FoldedLoad) |
Evan Cheng | 106e802 | 2007-10-13 02:35:06 +0000 | [diff] [blame] | 1271 | return false; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1272 | UnfoldLoad &= FoldedLoad; |
| 1273 | if (UnfoldStore && !FoldedStore) |
Evan Cheng | 106e802 | 2007-10-13 02:35:06 +0000 | [diff] [blame] | 1274 | return false; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1275 | UnfoldStore &= FoldedStore; |
Evan Cheng | 106e802 | 2007-10-13 02:35:06 +0000 | [diff] [blame] | 1276 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1277 | const TargetInstrDescriptor &TID = TII.get(Opc); |
| 1278 | const TargetOperandInfo &TOI = TID.OpInfo[Index]; |
| 1279 | const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS) |
| 1280 | ? TII.getPointerRegClass() : getRegClass(TOI.RegClass); |
| 1281 | SmallVector<MachineOperand,4> AddrOps; |
| 1282 | SmallVector<MachineOperand,2> BeforeOps; |
| 1283 | SmallVector<MachineOperand,2> AfterOps; |
| 1284 | SmallVector<MachineOperand,4> ImpOps; |
| 1285 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 1286 | MachineOperand &Op = MI->getOperand(i); |
| 1287 | if (i >= Index && i < Index+4) |
| 1288 | AddrOps.push_back(Op); |
| 1289 | else if (Op.isRegister() && Op.isImplicit()) |
| 1290 | ImpOps.push_back(Op); |
| 1291 | else if (i < Index) |
| 1292 | BeforeOps.push_back(Op); |
| 1293 | else if (i > Index) |
| 1294 | AfterOps.push_back(Op); |
| 1295 | } |
| 1296 | |
| 1297 | // Emit the load instruction. |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1298 | if (UnfoldLoad) { |
Evan Cheng | 106e802 | 2007-10-13 02:35:06 +0000 | [diff] [blame] | 1299 | loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1300 | if (UnfoldStore) { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1301 | // Address operands cannot be marked isKill. |
| 1302 | for (unsigned i = 1; i != 5; ++i) { |
| 1303 | MachineOperand &MO = NewMIs[0]->getOperand(i); |
| 1304 | if (MO.isRegister()) |
| 1305 | MO.unsetIsKill(); |
| 1306 | } |
| 1307 | } |
| 1308 | } |
| 1309 | |
| 1310 | // Emit the data processing instruction. |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1311 | MachineInstr *DataMI = new MachineInstr(TID, true); |
Evan Cheng | 106e802 | 2007-10-13 02:35:06 +0000 | [diff] [blame] | 1312 | MachineInstrBuilder MIB(DataMI); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1313 | |
| 1314 | if (FoldedStore) |
Evan Cheng | 106e802 | 2007-10-13 02:35:06 +0000 | [diff] [blame] | 1315 | MIB.addReg(Reg, true); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1316 | for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) |
| 1317 | MIB = X86InstrAddOperand(MIB, BeforeOps[i]); |
Evan Cheng | 42b08be | 2007-10-22 03:03:20 +0000 | [diff] [blame] | 1318 | if (FoldedLoad) |
| 1319 | MIB.addReg(Reg); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1320 | for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) |
| 1321 | MIB = X86InstrAddOperand(MIB, AfterOps[i]); |
Evan Cheng | 106e802 | 2007-10-13 02:35:06 +0000 | [diff] [blame] | 1322 | for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { |
| 1323 | MachineOperand &MO = ImpOps[i]; |
| 1324 | MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead()); |
| 1325 | } |
Evan Cheng | e62f97c | 2007-12-01 02:07:52 +0000 | [diff] [blame] | 1326 | // Change CMP32ri r, 0 back to TEST32rr r, r, etc. |
| 1327 | unsigned NewOpc = 0; |
| 1328 | switch (DataMI->getOpcode()) { |
| 1329 | default: break; |
| 1330 | case X86::CMP64ri32: |
| 1331 | case X86::CMP32ri: |
| 1332 | case X86::CMP16ri: |
| 1333 | case X86::CMP8ri: { |
| 1334 | MachineOperand &MO0 = DataMI->getOperand(0); |
| 1335 | MachineOperand &MO1 = DataMI->getOperand(1); |
| 1336 | if (MO1.getImm() == 0) { |
| 1337 | switch (DataMI->getOpcode()) { |
| 1338 | default: break; |
| 1339 | case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; |
| 1340 | case X86::CMP32ri: NewOpc = X86::TEST32rr; break; |
| 1341 | case X86::CMP16ri: NewOpc = X86::TEST16rr; break; |
| 1342 | case X86::CMP8ri: NewOpc = X86::TEST8rr; break; |
| 1343 | } |
| 1344 | DataMI->setInstrDescriptor(TII.get(NewOpc)); |
| 1345 | MO1.ChangeToRegister(MO0.getReg(), false); |
| 1346 | } |
| 1347 | } |
| 1348 | } |
| 1349 | NewMIs.push_back(DataMI); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1350 | |
| 1351 | // Emit the store instruction. |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1352 | if (UnfoldStore) { |
| 1353 | const TargetOperandInfo &DstTOI = TID.OpInfo[0]; |
| 1354 | const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS) |
| 1355 | ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass); |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 1356 | storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs); |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1357 | } |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1358 | |
| 1359 | return true; |
| 1360 | } |
| 1361 | |
| 1362 | |
| 1363 | bool |
| 1364 | X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 1365 | SmallVectorImpl<SDNode*> &NewNodes) const { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1366 | if (!N->isTargetOpcode()) |
| 1367 | return false; |
| 1368 | |
| 1369 | DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = |
| 1370 | MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode()); |
| 1371 | if (I == MemOp2RegOpTable.end()) |
| 1372 | return false; |
| 1373 | unsigned Opc = I->second.first; |
| 1374 | unsigned Index = I->second.second & 0xf; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1375 | bool FoldedLoad = I->second.second & (1 << 4); |
| 1376 | bool FoldedStore = I->second.second & (1 << 5); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1377 | const TargetInstrDescriptor &TID = TII.get(Opc); |
| 1378 | const TargetOperandInfo &TOI = TID.OpInfo[Index]; |
| 1379 | const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS) |
| 1380 | ? TII.getPointerRegClass() : getRegClass(TOI.RegClass); |
| 1381 | std::vector<SDOperand> AddrOps; |
| 1382 | std::vector<SDOperand> BeforeOps; |
| 1383 | std::vector<SDOperand> AfterOps; |
| 1384 | unsigned NumOps = N->getNumOperands(); |
| 1385 | for (unsigned i = 0; i != NumOps-1; ++i) { |
| 1386 | SDOperand Op = N->getOperand(i); |
| 1387 | if (i >= Index && i < Index+4) |
| 1388 | AddrOps.push_back(Op); |
| 1389 | else if (i < Index) |
| 1390 | BeforeOps.push_back(Op); |
| 1391 | else if (i > Index) |
| 1392 | AfterOps.push_back(Op); |
| 1393 | } |
| 1394 | SDOperand Chain = N->getOperand(NumOps-1); |
| 1395 | AddrOps.push_back(Chain); |
| 1396 | |
| 1397 | // Emit the load instruction. |
| 1398 | SDNode *Load = 0; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1399 | if (FoldedLoad) { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1400 | MVT::ValueType VT = *RC->vt_begin(); |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 1401 | Load = DAG.getTargetNode(getLoadRegOpcode(RC, StackAlign), VT, MVT::Other, |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1402 | &AddrOps[0], AddrOps.size()); |
| 1403 | NewNodes.push_back(Load); |
| 1404 | } |
| 1405 | |
| 1406 | // Emit the data processing instruction. |
| 1407 | std::vector<MVT::ValueType> VTs; |
| 1408 | const TargetRegisterClass *DstRC = 0; |
| 1409 | if (TID.numDefs > 0) { |
| 1410 | const TargetOperandInfo &DstTOI = TID.OpInfo[0]; |
| 1411 | DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS) |
| 1412 | ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass); |
| 1413 | VTs.push_back(*DstRC->vt_begin()); |
| 1414 | } |
| 1415 | for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { |
| 1416 | MVT::ValueType VT = N->getValueType(i); |
| 1417 | if (VT != MVT::Other && i >= TID.numDefs) |
| 1418 | VTs.push_back(VT); |
| 1419 | } |
| 1420 | if (Load) |
| 1421 | BeforeOps.push_back(SDOperand(Load, 0)); |
| 1422 | std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); |
| 1423 | SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size()); |
| 1424 | NewNodes.push_back(NewNode); |
| 1425 | |
| 1426 | // Emit the store instruction. |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1427 | if (FoldedStore) { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1428 | AddrOps.pop_back(); |
| 1429 | AddrOps.push_back(SDOperand(NewNode, 0)); |
| 1430 | AddrOps.push_back(Chain); |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 1431 | SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, StackAlign), |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1432 | MVT::Other, &AddrOps[0], AddrOps.size()); |
| 1433 | NewNodes.push_back(Store); |
| 1434 | } |
| 1435 | |
| 1436 | return true; |
| 1437 | } |
| 1438 | |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 1439 | unsigned X86RegisterInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, |
| 1440 | bool UnfoldLoad, bool UnfoldStore) const { |
| 1441 | DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = |
| 1442 | MemOp2RegOpTable.find((unsigned*)Opc); |
| 1443 | if (I == MemOp2RegOpTable.end()) |
| 1444 | return 0; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1445 | bool FoldedLoad = I->second.second & (1 << 4); |
| 1446 | bool FoldedStore = I->second.second & (1 << 5); |
| 1447 | if (UnfoldLoad && !FoldedLoad) |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 1448 | return 0; |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1449 | if (UnfoldStore && !FoldedStore) |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 1450 | return 0; |
| 1451 | return I->second.first; |
| 1452 | } |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1453 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1454 | const unsigned * |
| 1455 | X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 1456 | static const unsigned CalleeSavedRegs32Bit[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 1457 | X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 |
| 1458 | }; |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1459 | |
| 1460 | static const unsigned CalleeSavedRegs32EHRet[] = { |
| 1461 | X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 |
| 1462 | }; |
| 1463 | |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 1464 | static const unsigned CalleeSavedRegs64Bit[] = { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1465 | X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 |
| 1466 | }; |
| 1467 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1468 | if (Is64Bit) |
| 1469 | return CalleeSavedRegs64Bit; |
| 1470 | else { |
| 1471 | if (MF) { |
| 1472 | MachineFrameInfo *MFI = MF->getFrameInfo(); |
| 1473 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
| 1474 | if (MMI && MMI->callsEHReturn()) |
| 1475 | return CalleeSavedRegs32EHRet; |
| 1476 | } |
| 1477 | return CalleeSavedRegs32Bit; |
| 1478 | } |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 1479 | } |
| 1480 | |
| 1481 | const TargetRegisterClass* const* |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1482 | X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 1483 | static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 1484 | &X86::GR32RegClass, &X86::GR32RegClass, |
| 1485 | &X86::GR32RegClass, &X86::GR32RegClass, 0 |
| 1486 | }; |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1487 | static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = { |
| 1488 | &X86::GR32RegClass, &X86::GR32RegClass, |
| 1489 | &X86::GR32RegClass, &X86::GR32RegClass, |
| 1490 | &X86::GR32RegClass, &X86::GR32RegClass, 0 |
| 1491 | }; |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 1492 | static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1493 | &X86::GR64RegClass, &X86::GR64RegClass, |
| 1494 | &X86::GR64RegClass, &X86::GR64RegClass, |
| 1495 | &X86::GR64RegClass, &X86::GR64RegClass, 0 |
| 1496 | }; |
| 1497 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1498 | if (Is64Bit) |
| 1499 | return CalleeSavedRegClasses64Bit; |
| 1500 | else { |
| 1501 | if (MF) { |
| 1502 | MachineFrameInfo *MFI = MF->getFrameInfo(); |
| 1503 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
| 1504 | if (MMI && MMI->callsEHReturn()) |
| 1505 | return CalleeSavedRegClasses32EHRet; |
| 1506 | } |
| 1507 | return CalleeSavedRegClasses32Bit; |
| 1508 | } |
| 1509 | |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 1510 | } |
| 1511 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 1512 | BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 1513 | BitVector Reserved(getNumRegs()); |
| 1514 | Reserved.set(X86::RSP); |
| 1515 | Reserved.set(X86::ESP); |
| 1516 | Reserved.set(X86::SP); |
| 1517 | Reserved.set(X86::SPL); |
| 1518 | if (hasFP(MF)) { |
| 1519 | Reserved.set(X86::RBP); |
| 1520 | Reserved.set(X86::EBP); |
| 1521 | Reserved.set(X86::BP); |
| 1522 | Reserved.set(X86::BPL); |
| 1523 | } |
| 1524 | return Reserved; |
| 1525 | } |
| 1526 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1527 | //===----------------------------------------------------------------------===// |
| 1528 | // Stack Frame Processing methods |
| 1529 | //===----------------------------------------------------------------------===// |
| 1530 | |
| 1531 | // hasFP - Return true if the specified function should have a dedicated frame |
| 1532 | // pointer register. This is true if the function has variable sized allocas or |
| 1533 | // if frame pointer elimination is disabled. |
| 1534 | // |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 1535 | bool X86RegisterInfo::hasFP(const MachineFunction &MF) const { |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1536 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1537 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
| 1538 | |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 1539 | return (NoFramePointerElim || |
Evan Cheng | 7e7bbf8 | 2007-07-19 00:42:05 +0000 | [diff] [blame] | 1540 | MFI->hasVarSizedObjects() || |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1541 | MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() || |
| 1542 | (MMI && MMI->callsUnwindInit())); |
Misha Brukman | 03c6faf | 2002-12-03 23:11:21 +0000 | [diff] [blame] | 1543 | } |
Misha Brukman | 2adb395 | 2002-12-04 23:57:03 +0000 | [diff] [blame] | 1544 | |
Evan Cheng | 7e7bbf8 | 2007-07-19 00:42:05 +0000 | [diff] [blame] | 1545 | bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { |
| 1546 | return !MF.getFrameInfo()->hasVarSizedObjects(); |
| 1547 | } |
| 1548 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1549 | void X86RegisterInfo:: |
| 1550 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 1551 | MachineBasicBlock::iterator I) const { |
Evan Cheng | 7e7bbf8 | 2007-07-19 00:42:05 +0000 | [diff] [blame] | 1552 | if (!hasReservedCallFrame(MF)) { |
| 1553 | // If the stack pointer can be changed after prologue, turn the |
| 1554 | // adjcallstackup instruction into a 'sub ESP, <amt>' and the |
| 1555 | // adjcallstackdown instruction into 'add ESP, <amt>' |
| 1556 | // TODO: consider using push / pop instead of sub + store / add |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1557 | MachineInstr *Old = I; |
Chris Lattner | 6180780 | 2007-04-25 04:25:10 +0000 | [diff] [blame] | 1558 | uint64_t Amount = Old->getOperand(0).getImm(); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1559 | if (Amount != 0) { |
Chris Lattner | f158da2 | 2003-01-16 02:20:12 +0000 | [diff] [blame] | 1560 | // We need to keep the stack aligned properly. To do this, we round the |
| 1561 | // amount of space needed for the outgoing arguments up to the next |
| 1562 | // alignment boundary. |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 1563 | Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; |
Chris Lattner | f158da2 | 2003-01-16 02:20:12 +0000 | [diff] [blame] | 1564 | |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 1565 | MachineInstr *New = 0; |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1566 | if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1567 | New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1568 | .addReg(StackPtr).addImm(Amount); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1569 | } else { |
Jeff Cohen | 00b16889 | 2005-07-27 06:12:32 +0000 | [diff] [blame] | 1570 | assert(Old->getOpcode() == X86::ADJCALLSTACKUP); |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 1571 | // factor out the amount the callee already popped. |
Chris Lattner | 6180780 | 2007-04-25 04:25:10 +0000 | [diff] [blame] | 1572 | uint64_t CalleeAmt = Old->getOperand(1).getImm(); |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 1573 | Amount -= CalleeAmt; |
Chris Lattner | d77525d | 2006-02-03 18:20:04 +0000 | [diff] [blame] | 1574 | if (Amount) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1575 | unsigned Opc = (Amount < 128) ? |
| 1576 | (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : |
| 1577 | (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); |
Evan Cheng | c498b02 | 2007-11-14 07:59:08 +0000 | [diff] [blame] | 1578 | New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount); |
Chris Lattner | d77525d | 2006-02-03 18:20:04 +0000 | [diff] [blame] | 1579 | } |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1580 | } |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1581 | |
| 1582 | // Replace the pseudo instruction with a new instruction... |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 1583 | if (New) MBB.insert(I, New); |
| 1584 | } |
| 1585 | } else if (I->getOpcode() == X86::ADJCALLSTACKUP) { |
| 1586 | // If we are performing frame pointer elimination and if the callee pops |
| 1587 | // something off the stack pointer, add it back. We do this until we have |
| 1588 | // more advanced stack pointer tracking ability. |
Chris Lattner | 6180780 | 2007-04-25 04:25:10 +0000 | [diff] [blame] | 1589 | if (uint64_t CalleeAmt = I->getOperand(1).getImm()) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1590 | unsigned Opc = (CalleeAmt < 128) ? |
| 1591 | (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : |
| 1592 | (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); |
Jeff Cohen | 00b16889 | 2005-07-27 06:12:32 +0000 | [diff] [blame] | 1593 | MachineInstr *New = |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1594 | BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt); |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1595 | MBB.insert(I, New); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1596 | } |
| 1597 | } |
| 1598 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1599 | MBB.erase(I); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1600 | } |
| 1601 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 1602 | void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 1603 | int SPAdj, RegScavenger *RS) const{ |
| 1604 | assert(SPAdj == 0 && "Unexpected"); |
| 1605 | |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 1606 | unsigned i = 0; |
Alkis Evlogimenos | c0b9dc5 | 2004-02-12 02:27:10 +0000 | [diff] [blame] | 1607 | MachineInstr &MI = *II; |
Nate Begeman | f8be5e9 | 2004-08-14 22:05:10 +0000 | [diff] [blame] | 1608 | MachineFunction &MF = *MI.getParent()->getParent(); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1609 | while (!MI.getOperand(i).isFrameIndex()) { |
| 1610 | ++i; |
| 1611 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 1612 | } |
| 1613 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1614 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 1615 | // This must be part of a four operand memory reference. Replace the |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1616 | // FrameIndex with base register with EBP. Add an offset to the offset. |
| 1617 | MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false); |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 1618 | |
| 1619 | // Now add the frame object offset to the offset from EBP. |
Chris Lattner | 6180780 | 2007-04-25 04:25:10 +0000 | [diff] [blame] | 1620 | int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + |
| 1621 | MI.getOperand(i+3).getImm()+SlotSize; |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1622 | |
Chris Lattner | d5b7c47 | 2003-10-14 18:52:41 +0000 | [diff] [blame] | 1623 | if (!hasFP(MF)) |
| 1624 | Offset += MF.getFrameInfo()->getStackSize(); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1625 | else { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1626 | Offset += SlotSize; // Skip the saved EBP |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1627 | // Skip the RETADDR move area |
| 1628 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
| 1629 | int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); |
| 1630 | if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta; |
| 1631 | } |
| 1632 | |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 1633 | MI.getOperand(i+3).ChangeToImmediate(Offset); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1634 | } |
| 1635 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1636 | void |
| 1637 | X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{ |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1638 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
| 1639 | int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); |
| 1640 | if (TailCallReturnAddrDelta < 0) { |
| 1641 | // create RETURNADDR area |
| 1642 | // arg |
| 1643 | // arg |
| 1644 | // RETADDR |
| 1645 | // { ... |
| 1646 | // RETADDR area |
| 1647 | // ... |
| 1648 | // } |
| 1649 | // [EBP] |
| 1650 | MF.getFrameInfo()-> |
| 1651 | CreateFixedObject(-TailCallReturnAddrDelta, |
| 1652 | (-1*SlotSize)+TailCallReturnAddrDelta); |
| 1653 | } |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1654 | if (hasFP(MF)) { |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1655 | assert((TailCallReturnAddrDelta <= 0) && |
| 1656 | "The Delta should always be zero or negative"); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1657 | // Create a frame entry for the EBP register that must be saved. |
Chris Lattner | 7c6eefa | 2007-04-25 17:23:53 +0000 | [diff] [blame] | 1658 | int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1659 | (int)SlotSize * -2+ |
| 1660 | TailCallReturnAddrDelta); |
Chris Lattner | 96c3d2e | 2004-02-15 00:15:37 +0000 | [diff] [blame] | 1661 | assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && |
| 1662 | "Slot for EBP register must be last in order to be found!"); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1663 | } |
| 1664 | } |
| 1665 | |
Evan Cheng | a24dddd | 2007-04-26 01:09:28 +0000 | [diff] [blame] | 1666 | /// emitSPUpdate - Emit a series of instructions to increment / decrement the |
| 1667 | /// stack pointer by a constant value. |
| 1668 | static |
| 1669 | void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
| 1670 | unsigned StackPtr, int64_t NumBytes, bool Is64Bit, |
| 1671 | const TargetInstrInfo &TII) { |
| 1672 | bool isSub = NumBytes < 0; |
| 1673 | uint64_t Offset = isSub ? -NumBytes : NumBytes; |
| 1674 | unsigned Opc = isSub |
| 1675 | ? ((Offset < 128) ? |
| 1676 | (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : |
| 1677 | (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri)) |
| 1678 | : ((Offset < 128) ? |
| 1679 | (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : |
| 1680 | (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri)); |
| 1681 | uint64_t Chunk = (1LL << 31) - 1; |
| 1682 | |
| 1683 | while (Offset) { |
| 1684 | uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; |
| 1685 | BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal); |
| 1686 | Offset -= ThisVal; |
| 1687 | } |
| 1688 | } |
| 1689 | |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame] | 1690 | // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator. |
| 1691 | static |
| 1692 | void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
| 1693 | unsigned StackPtr, uint64_t *NumBytes = NULL) { |
Chris Lattner | eac9385 | 2007-10-07 21:53:12 +0000 | [diff] [blame] | 1694 | if (MBBI == MBB.begin()) return; |
| 1695 | |
| 1696 | MachineBasicBlock::iterator PI = prior(MBBI); |
| 1697 | unsigned Opc = PI->getOpcode(); |
| 1698 | if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || |
| 1699 | Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && |
| 1700 | PI->getOperand(0).getReg() == StackPtr) { |
| 1701 | if (NumBytes) |
| 1702 | *NumBytes += PI->getOperand(2).getImm(); |
| 1703 | MBB.erase(PI); |
| 1704 | } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || |
| 1705 | Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && |
| 1706 | PI->getOperand(0).getReg() == StackPtr) { |
| 1707 | if (NumBytes) |
| 1708 | *NumBytes -= PI->getOperand(2).getImm(); |
| 1709 | MBB.erase(PI); |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame] | 1710 | } |
| 1711 | } |
| 1712 | |
Anton Korobeynikov | 2508372 | 2007-10-06 16:39:43 +0000 | [diff] [blame] | 1713 | // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator. |
| 1714 | static |
Chris Lattner | eac9385 | 2007-10-07 21:53:12 +0000 | [diff] [blame] | 1715 | void mergeSPUpdatesDown(MachineBasicBlock &MBB, |
| 1716 | MachineBasicBlock::iterator &MBBI, |
Anton Korobeynikov | 2508372 | 2007-10-06 16:39:43 +0000 | [diff] [blame] | 1717 | unsigned StackPtr, uint64_t *NumBytes = NULL) { |
Chris Lattner | f443ba7 | 2007-10-07 22:00:31 +0000 | [diff] [blame] | 1718 | return; |
| 1719 | |
Chris Lattner | eac9385 | 2007-10-07 21:53:12 +0000 | [diff] [blame] | 1720 | if (MBBI == MBB.end()) return; |
| 1721 | |
| 1722 | MachineBasicBlock::iterator NI = next(MBBI); |
| 1723 | if (NI == MBB.end()) return; |
| 1724 | |
| 1725 | unsigned Opc = NI->getOpcode(); |
| 1726 | if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || |
| 1727 | Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && |
| 1728 | NI->getOperand(0).getReg() == StackPtr) { |
| 1729 | if (NumBytes) |
| 1730 | *NumBytes -= NI->getOperand(2).getImm(); |
| 1731 | MBB.erase(NI); |
| 1732 | MBBI = NI; |
| 1733 | } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || |
| 1734 | Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && |
| 1735 | NI->getOperand(0).getReg() == StackPtr) { |
| 1736 | if (NumBytes) |
| 1737 | *NumBytes += NI->getOperand(2).getImm(); |
| 1738 | MBB.erase(NI); |
| 1739 | MBBI = NI; |
Anton Korobeynikov | 2508372 | 2007-10-06 16:39:43 +0000 | [diff] [blame] | 1740 | } |
| 1741 | } |
| 1742 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1743 | /// mergeSPUpdates - Checks the instruction before/after the passed |
| 1744 | /// instruction. If it is an ADD/SUB instruction it is deleted |
| 1745 | /// argument and the stack adjustment is returned as a positive value for ADD |
| 1746 | /// and a negative for SUB. |
| 1747 | static int mergeSPUpdates(MachineBasicBlock &MBB, |
| 1748 | MachineBasicBlock::iterator &MBBI, |
| 1749 | unsigned StackPtr, |
| 1750 | bool doMergeWithPrevious) { |
| 1751 | |
| 1752 | if ((doMergeWithPrevious && MBBI == MBB.begin()) || |
| 1753 | (!doMergeWithPrevious && MBBI == MBB.end())) |
| 1754 | return 0; |
| 1755 | |
| 1756 | int Offset = 0; |
| 1757 | |
| 1758 | MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI; |
| 1759 | MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI); |
| 1760 | unsigned Opc = PI->getOpcode(); |
| 1761 | if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || |
| 1762 | Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && |
| 1763 | PI->getOperand(0).getReg() == StackPtr){ |
| 1764 | Offset += PI->getOperand(2).getImm(); |
| 1765 | MBB.erase(PI); |
| 1766 | if (!doMergeWithPrevious) MBBI = NI; |
| 1767 | } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || |
| 1768 | Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && |
| 1769 | PI->getOperand(0).getReg() == StackPtr) { |
| 1770 | Offset -= PI->getOperand(2).getImm(); |
| 1771 | MBB.erase(PI); |
| 1772 | if (!doMergeWithPrevious) MBBI = NI; |
| 1773 | } |
| 1774 | |
| 1775 | return Offset; |
| 1776 | } |
| 1777 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1778 | void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { |
Chris Lattner | 198ab64 | 2002-12-15 20:06:35 +0000 | [diff] [blame] | 1779 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
Chris Lattner | eafa423 | 2003-01-15 22:57:35 +0000 | [diff] [blame] | 1780 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 1781 | const Function* Fn = MF.getFunction(); |
| 1782 | const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>(); |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1783 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1784 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
| 1785 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1786 | |
Jim Laskey | 072200c | 2007-01-29 18:51:14 +0000 | [diff] [blame] | 1787 | // Prepare for frame info. |
Dan Gohman | 5e6e93e | 2007-09-24 16:44:26 +0000 | [diff] [blame] | 1788 | unsigned FrameLabelId = 0; |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1789 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1790 | // Get the number of bytes to allocate from the FrameInfo. |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1791 | uint64_t StackSize = MFI->getStackSize(); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1792 | // Add RETADDR move area to callee saved frame size. |
| 1793 | int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); |
| 1794 | if (TailCallReturnAddrDelta < 0) |
| 1795 | X86FI->setCalleeSavedFrameSize( |
| 1796 | X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta)); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1797 | uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); |
Evan Cheng | d9245ca | 2006-04-14 07:26:43 +0000 | [diff] [blame] | 1798 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1799 | // Insert stack pointer adjustment for later moving of return addr. Only |
| 1800 | // applies to tail call optimized functions where the callee argument stack |
| 1801 | // size is bigger than the callers. |
| 1802 | if (TailCallReturnAddrDelta < 0) { |
| 1803 | BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri), |
| 1804 | StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta); |
| 1805 | } |
| 1806 | |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1807 | if (hasFP(MF)) { |
| 1808 | // Get the offset of the stack slot for the EBP register... which is |
| 1809 | // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. |
| 1810 | // Update the frame offset adjustment. |
| 1811 | MFI->setOffsetAdjustment(SlotSize-NumBytes); |
| 1812 | |
| 1813 | // Save EBP into the appropriate stack slot... |
| 1814 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) |
| 1815 | .addReg(FramePtr); |
| 1816 | NumBytes -= SlotSize; |
| 1817 | |
| 1818 | if (MMI && MMI->needsFrameInfo()) { |
| 1819 | // Mark effective beginning of when frame pointer becomes valid. |
| 1820 | FrameLabelId = MMI->NextLabelID(); |
| 1821 | BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId); |
| 1822 | } |
| 1823 | |
| 1824 | // Update EBP with the new base value... |
| 1825 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) |
| 1826 | .addReg(StackPtr); |
| 1827 | } |
| 1828 | |
| 1829 | unsigned ReadyLabelId = 0; |
| 1830 | if (MMI && MMI->needsFrameInfo()) { |
| 1831 | // Mark effective beginning of when frame pointer is ready. |
| 1832 | ReadyLabelId = MMI->NextLabelID(); |
| 1833 | BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId); |
| 1834 | } |
| 1835 | |
| 1836 | // Skip the callee-saved push instructions. |
| 1837 | while (MBBI != MBB.end() && |
| 1838 | (MBBI->getOpcode() == X86::PUSH32r || |
| 1839 | MBBI->getOpcode() == X86::PUSH64r)) |
| 1840 | ++MBBI; |
| 1841 | |
Evan Cheng | d9245ca | 2006-04-14 07:26:43 +0000 | [diff] [blame] | 1842 | if (NumBytes) { // adjust stack pointer: ESP -= numbytes |
Anton Korobeynikov | 317848f | 2007-01-03 11:43:14 +0000 | [diff] [blame] | 1843 | if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) { |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1844 | // Check, whether EAX is livein for this function |
| 1845 | bool isEAXAlive = false; |
| 1846 | for (MachineFunction::livein_iterator II = MF.livein_begin(), |
| 1847 | EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) { |
| 1848 | unsigned Reg = II->first; |
| 1849 | isEAXAlive = (Reg == X86::EAX || Reg == X86::AX || |
| 1850 | Reg == X86::AH || Reg == X86::AL); |
| 1851 | } |
| 1852 | |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1853 | // Function prologue calls _alloca to probe the stack when allocating |
| 1854 | // more than 4k bytes in one go. Touching the stack at 4K increments is |
| 1855 | // necessary to ensure that the guard pages used by the OS virtual memory |
| 1856 | // manager are allocated in correct sequence. |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1857 | if (!isEAXAlive) { |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1858 | BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes); |
| 1859 | BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) |
| 1860 | .addExternalSymbol("_alloca"); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1861 | } else { |
| 1862 | // Save EAX |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1863 | BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1864 | // Allocate NumBytes-4 bytes on stack. We'll also use 4 already |
| 1865 | // allocated bytes for EAX. |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1866 | BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4); |
| 1867 | BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) |
| 1868 | .addExternalSymbol("_alloca"); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1869 | // Restore EAX |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1870 | MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX), |
| 1871 | StackPtr, NumBytes-4); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1872 | MBB.insert(MBBI, MI); |
| 1873 | } |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1874 | } else { |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1875 | // If there is an SUB32ri of ESP immediately before this instruction, |
| 1876 | // merge the two. This can be the case when tail call elimination is |
| 1877 | // enabled and the callee has more arguments then the caller. |
| 1878 | NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true); |
Anton Korobeynikov | 2508372 | 2007-10-06 16:39:43 +0000 | [diff] [blame] | 1879 | // If there is an ADD32ri or SUB32ri of ESP immediately after this |
Evan Cheng | 9b8c674 | 2007-07-17 21:26:42 +0000 | [diff] [blame] | 1880 | // instruction, merge the two instructions. |
Anton Korobeynikov | 2508372 | 2007-10-06 16:39:43 +0000 | [diff] [blame] | 1881 | mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes); |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame] | 1882 | |
Evan Cheng | 9b8c674 | 2007-07-17 21:26:42 +0000 | [diff] [blame] | 1883 | if (NumBytes) |
| 1884 | emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII); |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1885 | } |
Evan Cheng | d9245ca | 2006-04-14 07:26:43 +0000 | [diff] [blame] | 1886 | } |
| 1887 | |
Jim Laskey | e078d1a | 2007-01-29 23:20:22 +0000 | [diff] [blame] | 1888 | if (MMI && MMI->needsFrameInfo()) { |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1889 | std::vector<MachineMove> &Moves = MMI->getFrameMoves(); |
Dan Gohman | 8248294 | 2007-09-27 23:12:31 +0000 | [diff] [blame] | 1890 | const TargetData *TD = MF.getTarget().getTargetData(); |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1891 | |
| 1892 | // Calculate amount of bytes used for return address storing |
| 1893 | int stackGrowth = |
| 1894 | (MF.getTarget().getFrameInfo()->getStackGrowthDirection() == |
| 1895 | TargetFrameInfo::StackGrowsUp ? |
Dan Gohman | 8248294 | 2007-09-27 23:12:31 +0000 | [diff] [blame] | 1896 | TD->getPointerSize() : -TD->getPointerSize()); |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1897 | |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1898 | if (StackSize) { |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1899 | // Show update of SP. |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1900 | if (hasFP(MF)) { |
| 1901 | // Adjust SP |
| 1902 | MachineLocation SPDst(MachineLocation::VirtualFP); |
| 1903 | MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth); |
| 1904 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
| 1905 | } else { |
| 1906 | MachineLocation SPDst(MachineLocation::VirtualFP); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1907 | MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth); |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1908 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
| 1909 | } |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1910 | } else { |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1911 | //FIXME: Verify & implement for FP |
| 1912 | MachineLocation SPDst(StackPtr); |
| 1913 | MachineLocation SPSrc(StackPtr, stackGrowth); |
| 1914 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1915 | } |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1916 | |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1917 | // Add callee saved registers to move list. |
| 1918 | const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); |
Anton Korobeynikov | d97b8cd | 2007-07-24 21:07:39 +0000 | [diff] [blame] | 1919 | |
| 1920 | // FIXME: This is dirty hack. The code itself is pretty mess right now. |
| 1921 | // It should be rewritten from scratch and generalized sometimes. |
| 1922 | |
| 1923 | // Determine maximum offset (minumum due to stack growth) |
| 1924 | int64_t MaxOffset = 0; |
| 1925 | for (unsigned I = 0, E = CSI.size(); I!=E; ++I) |
| 1926 | MaxOffset = std::min(MaxOffset, |
| 1927 | MFI->getObjectOffset(CSI[I].getFrameIdx())); |
| 1928 | |
| 1929 | // Calculate offsets |
Anton Korobeynikov | 8d9d74e | 2007-10-26 09:13:24 +0000 | [diff] [blame] | 1930 | int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth; |
Anton Korobeynikov | d97b8cd | 2007-07-24 21:07:39 +0000 | [diff] [blame] | 1931 | for (unsigned I = 0, E = CSI.size(); I!=E; ++I) { |
Chris Lattner | ea84c5e | 2007-04-25 04:30:24 +0000 | [diff] [blame] | 1932 | int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1933 | unsigned Reg = CSI[I].getReg(); |
Anton Korobeynikov | 8d9d74e | 2007-10-26 09:13:24 +0000 | [diff] [blame] | 1934 | Offset = (MaxOffset-Offset+saveAreaOffset); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1935 | MachineLocation CSDst(MachineLocation::VirtualFP, Offset); |
| 1936 | MachineLocation CSSrc(Reg); |
| 1937 | Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); |
| 1938 | } |
| 1939 | |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1940 | if (hasFP(MF)) { |
| 1941 | // Save FP |
| 1942 | MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth); |
| 1943 | MachineLocation FPSrc(FramePtr); |
| 1944 | Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); |
| 1945 | } |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1946 | |
| 1947 | MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr); |
| 1948 | MachineLocation FPSrc(MachineLocation::VirtualFP); |
| 1949 | Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); |
| 1950 | } |
| 1951 | |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 1952 | // If it's main() on Cygwin\Mingw32 we should align stack as well |
| 1953 | if (Fn->hasExternalLinkage() && Fn->getName() == "main" && |
Anton Korobeynikov | 317848f | 2007-01-03 11:43:14 +0000 | [diff] [blame] | 1954 | Subtarget->isTargetCygMing()) { |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1955 | BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP) |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 1956 | .addReg(X86::ESP).addImm(-StackAlign); |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1957 | |
| 1958 | // Probe the stack |
Evan Cheng | db807ed | 2007-11-05 07:30:01 +0000 | [diff] [blame] | 1959 | BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1960 | BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca"); |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 1961 | } |
Misha Brukman | 2adb395 | 2002-12-04 23:57:03 +0000 | [diff] [blame] | 1962 | } |
| 1963 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1964 | void X86RegisterInfo::emitEpilogue(MachineFunction &MF, |
| 1965 | MachineBasicBlock &MBB) const { |
Chris Lattner | aa09b75 | 2002-12-28 21:08:28 +0000 | [diff] [blame] | 1966 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Anton Korobeynikov | 29be848 | 2007-09-26 00:13:34 +0000 | [diff] [blame] | 1967 | const Function* Fn = MF.getFunction(); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1968 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
Anton Korobeynikov | 29be848 | 2007-09-26 00:13:34 +0000 | [diff] [blame] | 1969 | const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>(); |
Alkis Evlogimenos | f81af21 | 2004-02-14 01:18:34 +0000 | [diff] [blame] | 1970 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1971 | unsigned RetOpcode = MBBI->getOpcode(); |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 1972 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1973 | switch (RetOpcode) { |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 1974 | case X86::RET: |
| 1975 | case X86::RETI: |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1976 | case X86::TCRETURNdi: |
| 1977 | case X86::TCRETURNri: |
| 1978 | case X86::TCRETURNri64: |
| 1979 | case X86::TCRETURNdi64: |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1980 | case X86::EH_RETURN: |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 1981 | case X86::TAILJMPd: |
| 1982 | case X86::TAILJMPr: |
| 1983 | case X86::TAILJMPm: break; // These are ok |
| 1984 | default: |
| 1985 | assert(0 && "Can only insert epilog into returning blocks"); |
| 1986 | } |
Misha Brukman | 2adb395 | 2002-12-04 23:57:03 +0000 | [diff] [blame] | 1987 | |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1988 | // Get the number of bytes to allocate from the FrameInfo |
| 1989 | uint64_t StackSize = MFI->getStackSize(); |
| 1990 | unsigned CSSize = X86FI->getCalleeSavedFrameSize(); |
| 1991 | uint64_t NumBytes = StackSize - CSSize; |
| 1992 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1993 | if (hasFP(MF)) { |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1994 | // pop EBP. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1995 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1996 | NumBytes -= SlotSize; |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1997 | } |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1998 | |
Evan Cheng | f27795d | 2007-07-17 18:03:34 +0000 | [diff] [blame] | 1999 | // Skip the callee-saved pop instructions. |
| 2000 | while (MBBI != MBB.begin()) { |
Evan Cheng | fcc8793 | 2007-07-26 17:45:41 +0000 | [diff] [blame] | 2001 | MachineBasicBlock::iterator PI = prior(MBBI); |
| 2002 | unsigned Opc = PI->getOpcode(); |
| 2003 | if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc)) |
Evan Cheng | f27795d | 2007-07-17 18:03:34 +0000 | [diff] [blame] | 2004 | break; |
| 2005 | --MBBI; |
| 2006 | } |
| 2007 | |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame] | 2008 | // If there is an ADD32ri or SUB32ri of ESP immediately before this |
| 2009 | // instruction, merge the two instructions. |
| 2010 | if (NumBytes || MFI->hasVarSizedObjects()) |
| 2011 | mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); |
Evan Cheng | 5b3332c | 2007-07-17 18:40:47 +0000 | [diff] [blame] | 2012 | |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame] | 2013 | // If dynamic alloca is used, then reset esp to point to the last callee-saved |
| 2014 | // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we |
| 2015 | // aligned stack in the prologue, - revert stack changes back. Note: we're |
| 2016 | // assuming, that frame pointer was forced for main() |
Anton Korobeynikov | 29be848 | 2007-09-26 00:13:34 +0000 | [diff] [blame] | 2017 | if (MFI->hasVarSizedObjects() || |
| 2018 | (Fn->hasExternalLinkage() && Fn->getName() == "main" && |
| 2019 | Subtarget->isTargetCygMing())) { |
Evan Cheng | 3c46eef | 2007-07-18 21:26:06 +0000 | [diff] [blame] | 2020 | unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; |
| 2021 | if (CSSize) { |
| 2022 | MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr), |
| 2023 | FramePtr, -CSSize); |
| 2024 | MBB.insert(MBBI, MI); |
| 2025 | } else |
| 2026 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr). |
| 2027 | addReg(FramePtr); |
| 2028 | |
| 2029 | NumBytes = 0; |
| 2030 | } |
| 2031 | |
| 2032 | // adjust stack pointer back: ESP += numbytes |
| 2033 | if (NumBytes) |
| 2034 | emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII); |
| 2035 | |
Evan Cheng | 5b3332c | 2007-07-17 18:40:47 +0000 | [diff] [blame] | 2036 | // We're returning from function via eh_return. |
| 2037 | if (RetOpcode == X86::EH_RETURN) { |
| 2038 | MBBI = prior(MBB.end()); |
| 2039 | MachineOperand &DestAddr = MBBI->getOperand(0); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 2040 | assert(DestAddr.isRegister() && "Offset should be in register!"); |
Evan Cheng | 5b3332c | 2007-07-17 18:40:47 +0000 | [diff] [blame] | 2041 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr). |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 2042 | addReg(DestAddr.getReg()); |
| 2043 | // Tail call return: adjust the stack pointer and jump to callee |
| 2044 | } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || |
| 2045 | RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) { |
| 2046 | MBBI = prior(MBB.end()); |
| 2047 | MachineOperand &JumpTarget = MBBI->getOperand(0); |
| 2048 | MachineOperand &StackAdjust = MBBI->getOperand(1); |
| 2049 | assert( StackAdjust.isImmediate() && "Expecting immediate value."); |
| 2050 | |
| 2051 | // Adjust stack pointer. |
| 2052 | int StackAdj = StackAdjust.getImm(); |
| 2053 | int MaxTCDelta = X86FI->getTCReturnAddrDelta(); |
| 2054 | int Offset = 0; |
| 2055 | assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive"); |
| 2056 | // Incoporate the retaddr area. |
| 2057 | Offset = StackAdj-MaxTCDelta; |
| 2058 | assert(Offset >= 0 && "Offset should never be negative"); |
| 2059 | if (Offset) { |
| 2060 | // Check for possible merge with preceeding ADD instruction. |
| 2061 | Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true); |
| 2062 | emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII); |
| 2063 | } |
| 2064 | // Jump to label or value in register. |
| 2065 | if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64) |
| 2066 | BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)). |
| 2067 | addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); |
| 2068 | else if (RetOpcode== X86::TCRETURNri64) { |
| 2069 | BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); |
| 2070 | } else |
| 2071 | BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg()); |
| 2072 | // Delete the pseudo instruction TCRETURN. |
| 2073 | MBB.erase(MBBI); |
| 2074 | } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && |
| 2075 | (X86FI->getTCReturnAddrDelta() < 0)) { |
| 2076 | // Add the return addr area delta back since we are not tail calling. |
| 2077 | int delta = -1*X86FI->getTCReturnAddrDelta(); |
| 2078 | MBBI = prior(MBB.end()); |
| 2079 | // Check for possible merge with preceeding ADD instruction. |
| 2080 | delta += mergeSPUpdates(MBB, MBBI, StackPtr, true); |
| 2081 | emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII); |
Evan Cheng | 5b3332c | 2007-07-17 18:40:47 +0000 | [diff] [blame] | 2082 | } |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 2083 | } |
| 2084 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 2085 | unsigned X86RegisterInfo::getRARegister() const { |
Anton Korobeynikov | 038082d | 2007-05-02 08:46:03 +0000 | [diff] [blame] | 2086 | if (Is64Bit) |
| 2087 | return X86::RIP; // Should have dwarf #16 |
| 2088 | else |
| 2089 | return X86::EIP; // Should have dwarf #8 |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 2090 | } |
| 2091 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 2092 | unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2093 | return hasFP(MF) ? FramePtr : StackPtr; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 2094 | } |
| 2095 | |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 2096 | void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) |
| 2097 | const { |
Anton Korobeynikov | 0ff3ca4 | 2007-05-12 22:36:25 +0000 | [diff] [blame] | 2098 | // Calculate amount of bytes used for return address storing |
| 2099 | int stackGrowth = (Is64Bit ? -8 : -4); |
| 2100 | |
| 2101 | // Initial state of the frame pointer is esp+4. |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 2102 | MachineLocation Dst(MachineLocation::VirtualFP); |
Anton Korobeynikov | 0ff3ca4 | 2007-05-12 22:36:25 +0000 | [diff] [blame] | 2103 | MachineLocation Src(StackPtr, stackGrowth); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 2104 | Moves.push_back(MachineMove(0, Dst, Src)); |
Anton Korobeynikov | 0ff3ca4 | 2007-05-12 22:36:25 +0000 | [diff] [blame] | 2105 | |
| 2106 | // Add return address to move list |
| 2107 | MachineLocation CSDst(StackPtr, stackGrowth); |
| 2108 | MachineLocation CSSrc(getRARegister()); |
| 2109 | Moves.push_back(MachineMove(0, CSDst, CSSrc)); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 2110 | } |
| 2111 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 2112 | unsigned X86RegisterInfo::getEHExceptionRegister() const { |
| 2113 | assert(0 && "What is the exception register"); |
| 2114 | return 0; |
| 2115 | } |
| 2116 | |
| 2117 | unsigned X86RegisterInfo::getEHHandlerRegister() const { |
| 2118 | assert(0 && "What is the exception handler register"); |
| 2119 | return 0; |
| 2120 | } |
| 2121 | |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2122 | namespace llvm { |
| 2123 | unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) { |
| 2124 | switch (VT) { |
| 2125 | default: return Reg; |
| 2126 | case MVT::i8: |
| 2127 | if (High) { |
| 2128 | switch (Reg) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2129 | default: return 0; |
| 2130 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2131 | return X86::AH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2132 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2133 | return X86::DH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2134 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2135 | return X86::CH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2136 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2137 | return X86::BH; |
| 2138 | } |
| 2139 | } else { |
| 2140 | switch (Reg) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2141 | default: return 0; |
| 2142 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2143 | return X86::AL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2144 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2145 | return X86::DL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2146 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2147 | return X86::CL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2148 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2149 | return X86::BL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2150 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
| 2151 | return X86::SIL; |
| 2152 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
| 2153 | return X86::DIL; |
| 2154 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
| 2155 | return X86::BPL; |
| 2156 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
| 2157 | return X86::SPL; |
| 2158 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 2159 | return X86::R8B; |
| 2160 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 2161 | return X86::R9B; |
| 2162 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 2163 | return X86::R10B; |
| 2164 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 2165 | return X86::R11B; |
| 2166 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 2167 | return X86::R12B; |
| 2168 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 2169 | return X86::R13B; |
| 2170 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 2171 | return X86::R14B; |
| 2172 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 2173 | return X86::R15B; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2174 | } |
| 2175 | } |
| 2176 | case MVT::i16: |
| 2177 | switch (Reg) { |
| 2178 | default: return Reg; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2179 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2180 | return X86::AX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2181 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2182 | return X86::DX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2183 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2184 | return X86::CX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2185 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2186 | return X86::BX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2187 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2188 | return X86::SI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2189 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2190 | return X86::DI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2191 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2192 | return X86::BP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2193 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2194 | return X86::SP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2195 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 2196 | return X86::R8W; |
| 2197 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 2198 | return X86::R9W; |
| 2199 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 2200 | return X86::R10W; |
| 2201 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 2202 | return X86::R11W; |
| 2203 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 2204 | return X86::R12W; |
| 2205 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 2206 | return X86::R13W; |
| 2207 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 2208 | return X86::R14W; |
| 2209 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 2210 | return X86::R15W; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2211 | } |
| 2212 | case MVT::i32: |
| 2213 | switch (Reg) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2214 | default: return Reg; |
| 2215 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2216 | return X86::EAX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2217 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2218 | return X86::EDX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2219 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2220 | return X86::ECX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2221 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2222 | return X86::EBX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2223 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2224 | return X86::ESI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2225 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2226 | return X86::EDI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2227 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2228 | return X86::EBP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2229 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2230 | return X86::ESP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2231 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 2232 | return X86::R8D; |
| 2233 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 2234 | return X86::R9D; |
| 2235 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 2236 | return X86::R10D; |
| 2237 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 2238 | return X86::R11D; |
| 2239 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 2240 | return X86::R12D; |
| 2241 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 2242 | return X86::R13D; |
| 2243 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 2244 | return X86::R14D; |
| 2245 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 2246 | return X86::R15D; |
| 2247 | } |
| 2248 | case MVT::i64: |
| 2249 | switch (Reg) { |
| 2250 | default: return Reg; |
| 2251 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
| 2252 | return X86::RAX; |
| 2253 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
| 2254 | return X86::RDX; |
| 2255 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
| 2256 | return X86::RCX; |
| 2257 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
| 2258 | return X86::RBX; |
| 2259 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
| 2260 | return X86::RSI; |
| 2261 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
| 2262 | return X86::RDI; |
| 2263 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
| 2264 | return X86::RBP; |
| 2265 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
| 2266 | return X86::RSP; |
| 2267 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 2268 | return X86::R8; |
| 2269 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 2270 | return X86::R9; |
| 2271 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 2272 | return X86::R10; |
| 2273 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 2274 | return X86::R11; |
| 2275 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 2276 | return X86::R12; |
| 2277 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 2278 | return X86::R13; |
| 2279 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 2280 | return X86::R14; |
| 2281 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 2282 | return X86::R15; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 2283 | } |
| 2284 | } |
| 2285 | |
| 2286 | return Reg; |
| 2287 | } |
| 2288 | } |
| 2289 | |
Chris Lattner | 7ad3e06 | 2003-08-03 15:48:14 +0000 | [diff] [blame] | 2290 | #include "X86GenRegisterInfo.inc" |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 2291 | |