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gerrit-public.fairphone.software / platform / external / llvm / 736fed9ff71ae677a7c947ac80ebb42a527de0dc / . / lib / Target / ARM / ARM.td
blob: 8851fbbf248156e3498410c09ff37e6ebe63911d [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
Evan Cheng301aaf52008-11-24 07:34:46 +0000[diff] [blame]17include "llvm/Target/Target.td"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget features.
21//
22
23def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
24 "ARM v4T">;
25def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
26 "ARM v5T">;
27def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
28 "ARM v5TE, v5TEj, v5TExp">;
29def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
30 "ARM v6">;
Anton Korobeynikov48000e92009-06-08 21:20:36 +0000[diff] [blame]31def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
32 "ARM v6t2">;
Anton Korobeynikov1bf0f082009-05-23 19:51:43 +0000[diff] [blame]33def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
34 "ARM v7A">;
35def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
Anton Korobeynikovf2e14752009-05-29 23:41:08 +0000[diff] [blame]36 "Enable VFP2 instructions">;
Anton Korobeynikov1bf0f082009-05-23 19:51:43 +0000[diff] [blame]37def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
Anton Korobeynikovf2e14752009-05-29 23:41:08 +0000[diff] [blame]38 "Enable VFP3 instructions">;
Anton Korobeynikov1bf0f082009-05-23 19:51:43 +0000[diff] [blame]39def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
Anton Korobeynikovf2e14752009-05-29 23:41:08 +0000[diff] [blame]40 "Enable NEON instructions">;
41def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
42 "Enable Thumb2 instructions">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]43
44//===----------------------------------------------------------------------===//
45// ARM Processors supported.
46//
47
Evan Cheng88e78d22009-06-19 01:51:50 +0000[diff] [blame]48include "ARMSchedule.td"
49
50class ProcNoItin<string Name, list<SubtargetFeature> Features>
51 : Processor<Name, GenericItineraries, Features>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]52
53// V4 Processors.
Evan Cheng88e78d22009-06-19 01:51:50 +0000[diff] [blame]54def : ProcNoItin<"generic", []>;
55def : ProcNoItin<"arm8", []>;
56def : ProcNoItin<"arm810", []>;
57def : ProcNoItin<"strongarm", []>;
58def : ProcNoItin<"strongarm110", []>;
59def : ProcNoItin<"strongarm1100", []>;
60def : ProcNoItin<"strongarm1110", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]61
62// V4T Processors.
Evan Cheng88e78d22009-06-19 01:51:50 +0000[diff] [blame]63def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
64def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
65def : ProcNoItin<"arm710t", [ArchV4T]>;
66def : ProcNoItin<"arm720t", [ArchV4T]>;
67def : ProcNoItin<"arm9", [ArchV4T]>;
68def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
69def : ProcNoItin<"arm920", [ArchV4T]>;
70def : ProcNoItin<"arm920t", [ArchV4T]>;
71def : ProcNoItin<"arm922t", [ArchV4T]>;
72def : ProcNoItin<"arm940t", [ArchV4T]>;
73def : ProcNoItin<"ep9312", [ArchV4T]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]74
75// V5T Processors.
Evan Cheng88e78d22009-06-19 01:51:50 +0000[diff] [blame]76def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
77def : ProcNoItin<"arm1020t", [ArchV5T]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]78
79// V5TE Processors.
Evan Cheng88e78d22009-06-19 01:51:50 +0000[diff] [blame]80def : ProcNoItin<"arm9e", [ArchV5TE]>;
81def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
82def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
83def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
84def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
85def : ProcNoItin<"arm10e", [ArchV5TE]>;
86def : ProcNoItin<"arm1020e", [ArchV5TE]>;
87def : ProcNoItin<"arm1022e", [ArchV5TE]>;
88def : ProcNoItin<"xscale", [ArchV5TE]>;
89def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]90
91// V6 Processors.
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]92def : ProcNoItin<"arm1136j-s", [ArchV6]>;
93def : ProcNoItin<"arm1136jf-s", [ArchV6, FeatureVFP2]>;
94def : ProcNoItin<"arm1176jz-s", [ArchV6]>;
95def : ProcNoItin<"arm1176jzf-s", [ArchV6, FeatureVFP2]>;
96def : ProcNoItin<"mpcorenovfp", [ArchV6]>;
97def : ProcNoItin<"mpcore", [ArchV6, FeatureVFP2]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]98
Anton Korobeynikov48000e92009-06-08 21:20:36 +0000[diff] [blame]99// V6T2 Processors.
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]100def : ProcNoItin<"arm1156t2-s", [ArchV6T2, FeatureThumb2]>;
101def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
Anton Korobeynikovf2e14752009-05-29 23:41:08 +0000[diff] [blame]102
Anton Korobeynikov48000e92009-06-08 21:20:36 +0000[diff] [blame]103// V7 Processors.
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]104def : Processor<"cortex-a8", CortexA8Itineraries,
David Goodwin736fed92009-10-01 22:19:57 +0000[diff] [blame^]105 [ArchV7A, FeatureThumb2, FeatureNEON]>;
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame]106def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
Anton Korobeynikov1bf0f082009-05-23 19:51:43 +0000[diff] [blame]107
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]108//===----------------------------------------------------------------------===//
109// Register File Description
110//===----------------------------------------------------------------------===//
111
112include "ARMRegisterInfo.td"
113
Bob Wilsonfd451172009-04-17 19:07:39 +0000[diff] [blame]114include "ARMCallingConv.td"
115
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]116//===----------------------------------------------------------------------===//
117// Instruction Descriptions
118//===----------------------------------------------------------------------===//
119
120include "ARMInstrInfo.td"
121
122def ARMInstrInfo : InstrInfo {
123 // Define how we want to layout our target-specific information field.
124 let TSFlagsFields = ["AddrModeBits",
125 "SizeFlag",
126 "IndexModeBits",
Evan Cheng9aa4cd32009-07-08 01:46:35 +0000[diff] [blame]127 "Form",
128 "isUnaryDataProc"];
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]129 let TSFlagsShifts = [0,
130 4,
131 7,
Evan Chenga7b3e7c2007-08-07 01:37:15 +0000[diff] [blame]132 9,
Evan Cheng9aa4cd32009-07-08 01:46:35 +0000[diff] [blame]133 15];
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]134}
135
136//===----------------------------------------------------------------------===//
137// Declare the target which we are implementing
138//===----------------------------------------------------------------------===//
139
140def ARM : Target {
141 // Pull in Instruction Info:
142 let InstructionSet = ARMInstrInfo;
143}