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gerrit-public.fairphone.software / platform / external / llvm / 036ebfd87434bc30a0e51f4b9a3d55ab49ee5509 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: eefb9e84b17c779c4c3cf7a0f836ac90c85ceff8 [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]29#include "llvm/Support/CommandLine.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]30#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]31#include "llvm/Support/MathExtras.h"
Nick Lewycky476b2422010-12-19 20:43:38 +0000[diff] [blame]32#include <cctype>
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]33using namespace llvm;
34
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]35/// We are in the process of implementing a new TypeLegalization action
36/// - the promotion of vector elements. This feature is disabled by default
37/// and only enabled using this flag.
38static cl::opt<bool>
Nadav Rotem8fb06b32011-10-16 20:31:33 +0000[diff] [blame]39AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true),
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]40 cl::desc("Allow promotion of integer vector element types"));
41
Rafael Espindola9a580232009-02-27 13:37:18 +0000[diff] [blame]42namespace llvm {
43TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
44 bool isLocal = GV->hasLocalLinkage();
45 bool isDeclaration = GV->isDeclaration();
46 // FIXME: what should we do for protected and internal visibility?
47 // For variables, is internal different from hidden?
48 bool isHidden = GV->hasHiddenVisibility();
49
50 if (reloc == Reloc::PIC_) {
51 if (isLocal || isHidden)
52 return TLSModel::LocalDynamic;
53 else
54 return TLSModel::GeneralDynamic;
55 } else {
56 if (!isDeclaration || isHidden)
57 return TLSModel::LocalExec;
58 else
59 return TLSModel::InitialExec;
60 }
61}
62}
63
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]64/// InitLibcallNames - Set default libcall names.
65///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]66static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]67 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]68 Names[RTLIB::SHL_I32] = "__ashlsi3";
69 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]70 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]71 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]72 Names[RTLIB::SRL_I32] = "__lshrsi3";
73 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]74 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]75 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]76 Names[RTLIB::SRA_I32] = "__ashrsi3";
77 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]78 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]79 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]80 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]81 Names[RTLIB::MUL_I32] = "__mulsi3";
82 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]83 Names[RTLIB::MUL_I128] = "__multi3";
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]84 Names[RTLIB::MULO_I32] = "__mulosi4";
85 Names[RTLIB::MULO_I64] = "__mulodi4";
86 Names[RTLIB::MULO_I128] = "__muloti4";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]87 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]88 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]89 Names[RTLIB::SDIV_I32] = "__divsi3";
90 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]91 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]92 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]93 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]94 Names[RTLIB::UDIV_I32] = "__udivsi3";
95 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]96 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]97 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]98 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]99 Names[RTLIB::SREM_I32] = "__modsi3";
100 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]101 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]102 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]103 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]104 Names[RTLIB::UREM_I32] = "__umodsi3";
105 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]106 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng8e23e812011-04-01 00:42:02 +0000[diff] [blame]107
108 // These are generally not available.
109 Names[RTLIB::SDIVREM_I8] = 0;
110 Names[RTLIB::SDIVREM_I16] = 0;
111 Names[RTLIB::SDIVREM_I32] = 0;
112 Names[RTLIB::SDIVREM_I64] = 0;
113 Names[RTLIB::SDIVREM_I128] = 0;
114 Names[RTLIB::UDIVREM_I8] = 0;
115 Names[RTLIB::UDIVREM_I16] = 0;
116 Names[RTLIB::UDIVREM_I32] = 0;
117 Names[RTLIB::UDIVREM_I64] = 0;
118 Names[RTLIB::UDIVREM_I128] = 0;
119
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]120 Names[RTLIB::NEG_I32] = "__negsi2";
121 Names[RTLIB::NEG_I64] = "__negdi2";
122 Names[RTLIB::ADD_F32] = "__addsf3";
123 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]124 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]125 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]126 Names[RTLIB::SUB_F32] = "__subsf3";
127 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]128 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]129 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]130 Names[RTLIB::MUL_F32] = "__mulsf3";
131 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]132 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]133 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]134 Names[RTLIB::DIV_F32] = "__divsf3";
135 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]136 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]137 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]138 Names[RTLIB::REM_F32] = "fmodf";
139 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]140 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]141 Names[RTLIB::REM_PPCF128] = "fmodl";
Cameron Zwarich33390842011-07-08 21:39:21 +0000[diff] [blame]142 Names[RTLIB::FMA_F32] = "fmaf";
143 Names[RTLIB::FMA_F64] = "fma";
144 Names[RTLIB::FMA_F80] = "fmal";
145 Names[RTLIB::FMA_PPCF128] = "fmal";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]146 Names[RTLIB::POWI_F32] = "__powisf2";
147 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]148 Names[RTLIB::POWI_F80] = "__powixf2";
149 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]150 Names[RTLIB::SQRT_F32] = "sqrtf";
151 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]152 Names[RTLIB::SQRT_F80] = "sqrtl";
153 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]154 Names[RTLIB::LOG_F32] = "logf";
155 Names[RTLIB::LOG_F64] = "log";
156 Names[RTLIB::LOG_F80] = "logl";
157 Names[RTLIB::LOG_PPCF128] = "logl";
158 Names[RTLIB::LOG2_F32] = "log2f";
159 Names[RTLIB::LOG2_F64] = "log2";
160 Names[RTLIB::LOG2_F80] = "log2l";
161 Names[RTLIB::LOG2_PPCF128] = "log2l";
162 Names[RTLIB::LOG10_F32] = "log10f";
163 Names[RTLIB::LOG10_F64] = "log10";
164 Names[RTLIB::LOG10_F80] = "log10l";
165 Names[RTLIB::LOG10_PPCF128] = "log10l";
166 Names[RTLIB::EXP_F32] = "expf";
167 Names[RTLIB::EXP_F64] = "exp";
168 Names[RTLIB::EXP_F80] = "expl";
169 Names[RTLIB::EXP_PPCF128] = "expl";
170 Names[RTLIB::EXP2_F32] = "exp2f";
171 Names[RTLIB::EXP2_F64] = "exp2";
172 Names[RTLIB::EXP2_F80] = "exp2l";
173 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]174 Names[RTLIB::SIN_F32] = "sinf";
175 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]176 Names[RTLIB::SIN_F80] = "sinl";
177 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]178 Names[RTLIB::COS_F32] = "cosf";
179 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]180 Names[RTLIB::COS_F80] = "cosl";
181 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]182 Names[RTLIB::POW_F32] = "powf";
183 Names[RTLIB::POW_F64] = "pow";
184 Names[RTLIB::POW_F80] = "powl";
185 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]186 Names[RTLIB::CEIL_F32] = "ceilf";
187 Names[RTLIB::CEIL_F64] = "ceil";
188 Names[RTLIB::CEIL_F80] = "ceill";
189 Names[RTLIB::CEIL_PPCF128] = "ceill";
190 Names[RTLIB::TRUNC_F32] = "truncf";
191 Names[RTLIB::TRUNC_F64] = "trunc";
192 Names[RTLIB::TRUNC_F80] = "truncl";
193 Names[RTLIB::TRUNC_PPCF128] = "truncl";
194 Names[RTLIB::RINT_F32] = "rintf";
195 Names[RTLIB::RINT_F64] = "rint";
196 Names[RTLIB::RINT_F80] = "rintl";
197 Names[RTLIB::RINT_PPCF128] = "rintl";
198 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
199 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
200 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
201 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
202 Names[RTLIB::FLOOR_F32] = "floorf";
203 Names[RTLIB::FLOOR_F64] = "floor";
204 Names[RTLIB::FLOOR_F80] = "floorl";
205 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]206 Names[RTLIB::COPYSIGN_F32] = "copysignf";
207 Names[RTLIB::COPYSIGN_F64] = "copysign";
208 Names[RTLIB::COPYSIGN_F80] = "copysignl";
209 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]210 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]211 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
212 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]213 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]214 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
215 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
216 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
217 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]218 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
219 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]220 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
221 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]222 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]223 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
224 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]225 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
226 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]227 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]228 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]229 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]230 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]231 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]232 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]233 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]234 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
235 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]236 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
237 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]238 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]239 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
240 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]241 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
242 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]243 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]244 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
245 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]246 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]247 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]248 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]249 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]250 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
251 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]252 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
253 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]254 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
255 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]256 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
257 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]258 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
259 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
260 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
261 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]262 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
263 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]264 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
265 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]266 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
267 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]268 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
269 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
270 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
271 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
272 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
273 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]274 Names[RTLIB::OEQ_F32] = "__eqsf2";
275 Names[RTLIB::OEQ_F64] = "__eqdf2";
276 Names[RTLIB::UNE_F32] = "__nesf2";
277 Names[RTLIB::UNE_F64] = "__nedf2";
278 Names[RTLIB::OGE_F32] = "__gesf2";
279 Names[RTLIB::OGE_F64] = "__gedf2";
280 Names[RTLIB::OLT_F32] = "__ltsf2";
281 Names[RTLIB::OLT_F64] = "__ltdf2";
282 Names[RTLIB::OLE_F32] = "__lesf2";
283 Names[RTLIB::OLE_F64] = "__ledf2";
284 Names[RTLIB::OGT_F32] = "__gtsf2";
285 Names[RTLIB::OGT_F64] = "__gtdf2";
286 Names[RTLIB::UO_F32] = "__unordsf2";
287 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]288 Names[RTLIB::O_F32] = "__unordsf2";
289 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]290 Names[RTLIB::MEMCPY] = "memcpy";
291 Names[RTLIB::MEMMOVE] = "memmove";
292 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]293 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]294 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
295 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
296 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
297 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]298 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
299 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
300 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
301 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]302 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
303 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
304 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
305 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
306 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
307 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
308 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
309 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
310 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
311 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
312 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
313 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
314 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
315 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
316 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
317 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
318 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
319 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
Jim Grosbach312b7c92011-10-14 15:53:48 +0000[diff] [blame]320 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]321 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
322 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
323 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
324 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
325 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]326}
327
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]328/// InitLibcallCallingConvs - Set default libcall CallingConvs.
329///
330static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
331 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
332 CCs[i] = CallingConv::C;
333 }
334}
335
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]336/// getFPEXT - Return the FPEXT_*_* value for the given types, or
337/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]338RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]339 if (OpVT == MVT::f32) {
340 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]341 return FPEXT_F32_F64;
342 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]343
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]344 return UNKNOWN_LIBCALL;
345}
346
347/// getFPROUND - Return the FPROUND_*_* value for the given types, or
348/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]349RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]350 if (RetVT == MVT::f32) {
351 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]352 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]353 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]354 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]355 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]356 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]357 } else if (RetVT == MVT::f64) {
358 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]359 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]360 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]361 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]362 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]363
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]364 return UNKNOWN_LIBCALL;
365}
366
367/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
368/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]369RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]370 if (OpVT == MVT::f32) {
371 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]372 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]374 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]375 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]377 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]378 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]379 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]380 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]381 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]382 if (RetVT == MVT::i8)
383 return FPTOSINT_F64_I8;
384 if (RetVT == MVT::i16)
385 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]386 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]387 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]388 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]389 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]390 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]391 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]392 } else if (OpVT == MVT::f80) {
393 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]394 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]395 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]396 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]397 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]398 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]399 } else if (OpVT == MVT::ppcf128) {
400 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]401 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]402 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]403 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]404 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]405 return FPTOSINT_PPCF128_I128;
406 }
407 return UNKNOWN_LIBCALL;
408}
409
410/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
411/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]412RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]413 if (OpVT == MVT::f32) {
414 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]415 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]416 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]417 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]418 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]419 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]420 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]421 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]422 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]423 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]424 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]425 if (RetVT == MVT::i8)
426 return FPTOUINT_F64_I8;
427 if (RetVT == MVT::i16)
428 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]429 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]430 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]431 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]432 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]433 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]434 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]435 } else if (OpVT == MVT::f80) {
436 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]437 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]438 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]439 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]440 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]441 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]442 } else if (OpVT == MVT::ppcf128) {
443 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]444 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]445 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]446 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]447 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]448 return FPTOUINT_PPCF128_I128;
449 }
450 return UNKNOWN_LIBCALL;
451}
452
453/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
454/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]455RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]456 if (OpVT == MVT::i32) {
457 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]458 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]459 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]460 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]461 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]462 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]463 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]464 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]465 } else if (OpVT == MVT::i64) {
466 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]467 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]468 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]469 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]470 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]471 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]472 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]473 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]474 } else if (OpVT == MVT::i128) {
475 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]476 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]477 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]478 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]479 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]480 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]481 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]482 return SINTTOFP_I128_PPCF128;
483 }
484 return UNKNOWN_LIBCALL;
485}
486
487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]490 if (OpVT == MVT::i32) {
491 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]492 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]493 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]494 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]495 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]496 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]497 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]498 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]499 } else if (OpVT == MVT::i64) {
500 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]501 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]502 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]503 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]504 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]505 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]506 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]507 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]508 } else if (OpVT == MVT::i128) {
509 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]510 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]511 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]512 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]513 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]514 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]515 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]516 return UINTTOFP_I128_PPCF128;
517 }
518 return UNKNOWN_LIBCALL;
519}
520
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]521/// InitCmpLibcallCCs - Set default comparison libcall CC.
522///
523static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
524 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
525 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
526 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
527 CCs[RTLIB::UNE_F32] = ISD::SETNE;
528 CCs[RTLIB::UNE_F64] = ISD::SETNE;
529 CCs[RTLIB::OGE_F32] = ISD::SETGE;
530 CCs[RTLIB::OGE_F64] = ISD::SETGE;
531 CCs[RTLIB::OLT_F32] = ISD::SETLT;
532 CCs[RTLIB::OLT_F64] = ISD::SETLT;
533 CCs[RTLIB::OLE_F32] = ISD::SETLE;
534 CCs[RTLIB::OLE_F64] = ISD::SETLE;
535 CCs[RTLIB::OGT_F32] = ISD::SETGT;
536 CCs[RTLIB::OGT_F64] = ISD::SETGT;
537 CCs[RTLIB::UO_F32] = ISD::SETNE;
538 CCs[RTLIB::UO_F64] = ISD::SETNE;
539 CCs[RTLIB::O_F32] = ISD::SETEQ;
540 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]541}
542
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]543/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]544TargetLowering::TargetLowering(const TargetMachine &tm,
545 const TargetLoweringObjectFile *tlof)
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]546 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
547 mayPromoteElements(AllowPromoteIntElem) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]548 // All operations default to being supported.
549 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]550 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]551 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]552 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]553 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]554
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]555 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]556 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]557 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]558 for (unsigned IM = (unsigned)ISD::PRE_INC;
559 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]560 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
561 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]562 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]563
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]564 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]565 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]567 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]568
569 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]570 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]571
572 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]573 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]574 // to optimize expansions for certain constants.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]575 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]576 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
577 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
578 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]579
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]580 // These library functions default to expand.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]581 setOperationAction(ISD::FLOG , MVT::f16, Expand);
582 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
583 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
584 setOperationAction(ISD::FEXP , MVT::f16, Expand);
585 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
586 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
587 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
588 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
589 setOperationAction(ISD::FRINT, MVT::f16, Expand);
590 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Owen Anderson4a4fdf32011-12-08 19:32:14 +0000[diff] [blame]591 setOperationAction(ISD::FLOG , MVT::f32, Expand);
592 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
593 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
594 setOperationAction(ISD::FEXP , MVT::f32, Expand);
595 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
596 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
597 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
598 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
599 setOperationAction(ISD::FRINT, MVT::f32, Expand);
600 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]601 setOperationAction(ISD::FLOG , MVT::f64, Expand);
602 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
603 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
604 setOperationAction(ISD::FEXP , MVT::f64, Expand);
605 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
606 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
607 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
608 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
609 setOperationAction(ISD::FRINT, MVT::f64, Expand);
610 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]611
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]612 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]613 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]614
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]615 IsLittleEndian = TD->isLittleEndian();
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]616 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]617 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]618 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]619 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng05219282011-01-06 06:52:41 +0000[diff] [blame]620 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
621 = maxStoresPerMemmoveOptSize = 4;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]622 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]623 UseUnderscoreSetJmp = false;
624 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]625 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]626 IntDivIsCheap = false;
627 Pow2DivIsCheap = false;
Chris Lattnerde189be2010-11-30 18:12:52 +0000[diff] [blame]628 JumpIsExpensive = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]629 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]630 ExceptionPointerRegister = 0;
631 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]632 BooleanContents = UndefinedBooleanContent;
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]633 BooleanVectorContents = UndefinedBooleanContent;
Dan Gohman8c2d2702011-10-24 17:45:02 +0000[diff] [blame]634 SchedPreferenceInfo = Sched::ILP;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]635 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]636 JumpBufAlignment = 0;
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000[diff] [blame]637 MinFunctionAlignment = 0;
638 PrefFunctionAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]639 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]640 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]641 ShouldFoldAtomicFences = false;
Eli Friedman26689ac2011-08-03 21:06:02 +0000[diff] [blame]642 InsertFencesForAtomic = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]643
644 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]645 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]646 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]647}
648
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]649TargetLowering::~TargetLowering() {
650 delete &TLOF;
651}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]652
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]653MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
654 return MVT::getIntegerVT(8*TD->getPointerSize());
655}
656
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]657/// canOpTrap - Returns true if the operation can trap for the value type.
658/// VT must be a legal type.
659bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
660 assert(isTypeLegal(VT));
661 switch (Op) {
662 default:
663 return false;
664 case ISD::FDIV:
665 case ISD::FREM:
666 case ISD::SDIV:
667 case ISD::UDIV:
668 case ISD::SREM:
669 case ISD::UREM:
670 return true;
671 }
672}
673
674
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]675static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]676 unsigned &NumIntermediates,
677 EVT &RegisterVT,
678 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]679 // Figure out the right, legal destination reg to copy into.
680 unsigned NumElts = VT.getVectorNumElements();
681 MVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]682
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]683 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]684
685 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]686 // could break down into LHS/RHS like LegalizeDAG does.
687 if (!isPowerOf2_32(NumElts)) {
688 NumVectorRegs = NumElts;
689 NumElts = 1;
690 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]691
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]692 // Divide the input until we get to a supported size. This will always
693 // end with a scalar if the target doesn't support vectors.
694 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
695 NumElts >>= 1;
696 NumVectorRegs <<= 1;
697 }
698
699 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]700
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]701 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
702 if (!TLI->isTypeLegal(NewVT))
703 NewVT = EltTy;
704 IntermediateVT = NewVT;
705
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]706 unsigned NewVTSize = NewVT.getSizeInBits();
707
708 // Convert sizes such as i33 to i64.
709 if (!isPowerOf2_32(NewVTSize))
710 NewVTSize = NextPowerOf2(NewVTSize);
711
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]712 EVT DestVT = TLI->getRegisterType(NewVT);
713 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]714 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]715 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]716
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]717 // Otherwise, promotion or legal types use the same number of registers as
718 // the vector decimated to the appropriate level.
719 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]720}
721
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]722/// isLegalRC - Return true if the value types that can be represented by the
723/// specified register class are all legal.
724bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
725 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
726 I != E; ++I) {
727 if (isTypeLegal(*I))
728 return true;
729 }
730 return false;
731}
732
733/// hasLegalSuperRegRegClasses - Return true if the specified register class
734/// has one or more super-reg register classes that are legal.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]735bool
736TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]737 if (*RC->superregclasses_begin() == 0)
738 return false;
739 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
740 E = RC->superregclasses_end(); I != E; ++I) {
741 const TargetRegisterClass *RRC = *I;
742 if (isLegalRC(RRC))
743 return true;
744 }
745 return false;
746}
747
748/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]749/// of the register class for the specified type and its associated "cost".
750std::pair<const TargetRegisterClass*, uint8_t>
751TargetLowering::findRepresentativeClass(EVT VT) const {
752 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
753 if (!RC)
754 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]755 const TargetRegisterClass *BestRC = RC;
756 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
757 E = RC->superregclasses_end(); I != E; ++I) {
758 const TargetRegisterClass *RRC = *I;
759 if (RRC->isASubClass() || !isLegalRC(RRC))
760 continue;
761 if (!hasLegalSuperRegRegClasses(RRC))
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]762 return std::make_pair(RRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]763 BestRC = RRC;
764 }
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]765 return std::make_pair(BestRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]766}
767
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]768
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]769/// computeRegisterProperties - Once all of the register classes are added,
770/// this allows us to compute derived properties we expose.
771void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]772 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]773 "Too many value types for ValueTypeActions to hold!");
774
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]775 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]776 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]777 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]778 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]779 }
780 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]781 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]782
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]783 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]784 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]785 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]786 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]787
788 // Every integer value type larger than this largest register takes twice as
789 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]790 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]791 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
792 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]793 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]794 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]795 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
796 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]797 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]798 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]799
800 // Inspect all of the ValueType's smaller than the largest integer
801 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]802 unsigned LegalIntReg = LargestIntReg;
803 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]804 IntReg >= (unsigned)MVT::i1; --IntReg) {
805 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]806 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]807 LegalIntReg = IntReg;
808 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]809 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]810 (MVT::SimpleValueType)LegalIntReg;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]811 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]812 }
813 }
814
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]815 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]816 if (!isTypeLegal(MVT::ppcf128)) {
817 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
818 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
819 TransformToType[MVT::ppcf128] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]820 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]821 }
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]822
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]823 // Decide how to handle f64. If the target does not have native f64 support,
824 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]825 if (!isTypeLegal(MVT::f64)) {
826 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
827 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
828 TransformToType[MVT::f64] = MVT::i64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]829 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]830 }
831
832 // Decide how to handle f32. If the target does not have native support for
833 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]834 if (!isTypeLegal(MVT::f32)) {
835 if (isTypeLegal(MVT::f64)) {
836 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
837 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
838 TransformToType[MVT::f32] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]839 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]840 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]841 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
842 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
843 TransformToType[MVT::f32] = MVT::i32;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]844 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]845 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]846 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]847
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]848 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]849 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
850 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]851 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]852 if (isTypeLegal(VT)) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]853
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]854 // Determine if there is a legal wider type. If so, we should promote to
855 // that wider vector type.
856 EVT EltVT = VT.getVectorElementType();
857 unsigned NElts = VT.getVectorNumElements();
858 if (NElts != 1) {
859 bool IsLegalWiderType = false;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]860 // If we allow the promotion of vector elements using a flag,
861 // then return TypePromoteInteger on vector elements.
862 // First try to promote the elements of integer vectors. If no legal
863 // promotion was found, fallback to the widen-vector method.
864 if (mayPromoteElements)
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]865 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
866 EVT SVT = (MVT::SimpleValueType)nVT;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]867 // Promote vectors of integers to vectors with the same number
868 // of elements, with a wider element type.
869 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
870 && SVT.getVectorNumElements() == NElts &&
871 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
872 TransformToType[i] = SVT;
873 RegisterTypeForVT[i] = SVT;
874 NumRegistersForVT[i] = 1;
875 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
876 IsLegalWiderType = true;
877 break;
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]878 }
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]879 }
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]880
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]881 if (IsLegalWiderType) continue;
882
883 // Try to widen the vector.
884 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
885 EVT SVT = (MVT::SimpleValueType)nVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]886 if (SVT.getVectorElementType() == EltVT &&
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]887 SVT.getVectorNumElements() > NElts &&
Dale Johannesene93d99c2010-10-20 21:32:10 +0000[diff] [blame]888 isTypeLegal(SVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]889 TransformToType[i] = SVT;
890 RegisterTypeForVT[i] = SVT;
891 NumRegistersForVT[i] = 1;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]892 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]893 IsLegalWiderType = true;
894 break;
895 }
896 }
897 if (IsLegalWiderType) continue;
898 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]899
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]900 MVT IntermediateVT;
901 EVT RegisterVT;
902 unsigned NumIntermediates;
903 NumRegistersForVT[i] =
904 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
905 RegisterVT, this);
906 RegisterTypeForVT[i] = RegisterVT;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]907
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]908 EVT NVT = VT.getPow2VectorType();
909 if (NVT == VT) {
910 // Type is already a power of 2. The default action is to split.
911 TransformToType[i] = MVT::Other;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]912 unsigned NumElts = VT.getVectorNumElements();
913 ValueTypeActions.setTypeAction(VT,
914 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]915 } else {
916 TransformToType[i] = NVT;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]917 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]918 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]919 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]920
921 // Determine the 'representative' register class for each value type.
922 // An representative register class is the largest (meaning one which is
923 // not a sub-register class / subreg register class) legal register class for
924 // a group of value types. For example, on i386, i8, i16, and i32
925 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]926 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]927 const TargetRegisterClass* RRC;
928 uint8_t Cost;
929 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
930 RepRegClassForVT[i] = RRC;
931 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]932 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]933}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]934
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]935const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
936 return NULL;
937}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]938
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]939
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]940EVT TargetLowering::getSetCCResultType(EVT VT) const {
941 assert(!VT.isVector() && "No default SetCC type for vectors!");
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]942 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]943}
944
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]945MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
946 return MVT::i32; // return the default value
947}
948
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]949/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]950/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
951/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
952/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]953///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]954/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]955/// register. It also returns the VT and quantity of the intermediate values
956/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]957///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]958unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]959 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]960 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]961 EVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]962 unsigned NumElts = VT.getVectorNumElements();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]963
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]964 // If there is a wider vector type with the same element type as this one,
965 // we should widen to that legal vector type. This handles things like
966 // <2 x float> -> <4 x float>.
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]967 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]968 RegisterVT = getTypeToTransformTo(Context, VT);
969 if (isTypeLegal(RegisterVT)) {
970 IntermediateVT = RegisterVT;
971 NumIntermediates = 1;
972 return 1;
973 }
974 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]975
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]976 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]977 EVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]978
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]979 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]980
981 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]982 // could break down into LHS/RHS like LegalizeDAG does.
983 if (!isPowerOf2_32(NumElts)) {
984 NumVectorRegs = NumElts;
985 NumElts = 1;
986 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]987
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]988 // Divide the input until we get to a supported size. This will always
989 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]990 while (NumElts > 1 && !isTypeLegal(
991 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]992 NumElts >>= 1;
993 NumVectorRegs <<= 1;
994 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]995
996 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]997
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]998 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]999 if (!isTypeLegal(NewVT))
1000 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]1001 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1002
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1003 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]1004 RegisterVT = DestVT;
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1005 unsigned NewVTSize = NewVT.getSizeInBits();
1006
1007 // Convert sizes such as i33 to i64.
1008 if (!isPowerOf2_32(NewVTSize))
1009 NewVTSize = NextPowerOf2(NewVTSize);
1010
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]1011 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1012 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1013
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]1014 // Otherwise, promotion or legal types use the same number of registers as
1015 // the vector decimated to the appropriate level.
1016 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1017}
1018
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1019/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1020/// type of the given function. This does not require a DAG or a return value,
1021/// and is suitable for use before any DAGs for the function are constructed.
1022/// TODO: Move this out of TargetLowering.cpp.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1023void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1024 SmallVectorImpl<ISD::OutputArg> &Outs,
1025 const TargetLowering &TLI,
1026 SmallVectorImpl<uint64_t> *Offsets) {
1027 SmallVector<EVT, 4> ValueVTs;
1028 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1029 unsigned NumValues = ValueVTs.size();
1030 if (NumValues == 0) return;
1031 unsigned Offset = 0;
1032
1033 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1034 EVT VT = ValueVTs[j];
1035 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1036
1037 if (attr & Attribute::SExt)
1038 ExtendKind = ISD::SIGN_EXTEND;
1039 else if (attr & Attribute::ZExt)
1040 ExtendKind = ISD::ZERO_EXTEND;
1041
1042 // FIXME: C calling convention requires the return type to be promoted to
1043 // at least 32-bit. But this is not necessary for non-C calling
1044 // conventions. The frontend should mark functions whose return values
1045 // require promoting with signext or zeroext attributes.
1046 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1047 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1048 if (VT.bitsLT(MinVT))
1049 VT = MinVT;
1050 }
1051
1052 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1053 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1054 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1055 PartVT.getTypeForEVT(ReturnType->getContext()));
1056
1057 // 'inreg' on function refers to return value
1058 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1059 if (attr & Attribute::InReg)
1060 Flags.setInReg();
1061
1062 // Propagate extension type if any
1063 if (attr & Attribute::SExt)
1064 Flags.setSExt();
1065 else if (attr & Attribute::ZExt)
1066 Flags.setZExt();
1067
1068 for (unsigned i = 0; i < NumParts; ++i) {
1069 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1070 if (Offsets) {
1071 Offsets->push_back(Offset);
1072 Offset += PartSize;
1073 }
1074 }
1075 }
1076}
1077
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1078/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1079/// function arguments in the caller parameter area. This is the actual
1080/// alignment, not its logarithm.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1081unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1082 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1083}
1084
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1085/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1086/// current function. The returned value is a member of the
1087/// MachineJumpTableInfo::JTEntryKind enum.
1088unsigned TargetLowering::getJumpTableEncoding() const {
1089 // In non-pic modes, just use the address of a block.
1090 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1091 return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1092
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1093 // In PIC mode, if the target supports a GPRel32 directive, use it.
1094 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1095 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1096
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1097 // Otherwise, use a label difference.
1098 return MachineJumpTableInfo::EK_LabelDifference32;
1099}
1100
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1101SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1102 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1103 // If our PIC model is GP relative, use the global offset table as the base.
1104 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]1105 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1106 return Table;
1107}
1108
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1109/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1110/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1111/// MCExpr.
1112const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1113TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1114 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1115 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1116 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1117}
1118
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1119bool
1120TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1121 // Assume that everything is safe in static mode.
1122 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1123 return true;
1124
1125 // In dynamic-no-pic mode, assume that known defined values are safe.
1126 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1127 GA &&
1128 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1129 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1130 return true;
1131
1132 // Otherwise assume nothing is safe.
1133 return false;
1134}
1135
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1136//===----------------------------------------------------------------------===//
1137// Optimization Methods
1138//===----------------------------------------------------------------------===//
1139
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1140/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1141/// specified instruction is a constant integer. If so, check to see if there
1142/// are any bits set in the constant that are not demanded. If so, shrink the
1143/// constant and return true.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1144bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1145 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1146 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1147
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1148 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1149 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1150 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1151 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1152 case ISD::AND:
1153 case ISD::OR: {
1154 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1155 if (!C) return false;
1156
1157 if (Op.getOpcode() == ISD::XOR &&
1158 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1159 return false;
1160
1161 // if we can expand it to have all bits set, do it
1162 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1163 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1164 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1165 DAG.getConstant(Demanded &
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1166 C->getAPIntValue(),
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1167 VT));
1168 return CombineTo(Op, New);
1169 }
1170
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1171 break;
1172 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1173 }
1174
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1175 return false;
1176}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1177
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1178/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1179/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1180/// cast, but it could be generalized for targets with other types of
1181/// implicit widening casts.
1182bool
1183TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1184 unsigned BitWidth,
1185 const APInt &Demanded,
1186 DebugLoc dl) {
1187 assert(Op.getNumOperands() == 2 &&
1188 "ShrinkDemandedOp only supports binary operators!");
1189 assert(Op.getNode()->getNumValues() == 1 &&
1190 "ShrinkDemandedOp only supports nodes with one result!");
1191
1192 // Don't do this if the node has another user, which may require the
1193 // full value.
1194 if (!Op.getNode()->hasOneUse())
1195 return false;
1196
1197 // Search for the smallest integer type with free casts to and from
1198 // Op's type. For expedience, just check power-of-2 integer types.
1199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1200 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1201 if (!isPowerOf2_32(SmallVTBits))
1202 SmallVTBits = NextPowerOf2(SmallVTBits);
1203 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1204 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1205 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1206 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1207 // We found a type with free casts.
1208 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1209 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1210 Op.getNode()->getOperand(0)),
1211 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1212 Op.getNode()->getOperand(1)));
1213 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1214 return CombineTo(Op, Z);
1215 }
1216 }
1217 return false;
1218}
1219
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1220/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Chad Rosier8c1ec5a2011-06-11 02:27:46 +0000[diff] [blame]1221/// DemandedMask bits of the result of Op are ever used downstream. If we can
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1222/// use this information to simplify Op, create a new simplified DAG node and
1223/// return true, returning the original and new nodes in Old and New. Otherwise,
1224/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1225/// the expression (used to simplify the caller). The KnownZero/One bits may
1226/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1227bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1228 const APInt &DemandedMask,
1229 APInt &KnownZero,
1230 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1231 TargetLoweringOpt &TLO,
1232 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1233 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1234 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1235 "Mask size mismatches value type size!");
1236 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1237 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1238
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1239 // Don't know anything.
1240 KnownZero = KnownOne = APInt(BitWidth, 0);
1241
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1242 // Other users may use these bits.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1243 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1244 if (Depth != 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1245 // If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1246 // simplify things downstream.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1247 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1248 return false;
1249 }
1250 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1251 // just set the NewMask to all bits.
1252 NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1253 } else if (DemandedMask == 0) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1254 // Not demanding any bits from Op.
1255 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1256 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1257 return false;
1258 } else if (Depth == 6) { // Limit search depth.
1259 return false;
1260 }
1261
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1262 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1263 switch (Op.getOpcode()) {
1264 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1265 // We know all of the bits for a constant!
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1266 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1267 KnownZero = ~KnownOne;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1268 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1269 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1270 // If the RHS is a constant, check to see if the LHS would be zero without
1271 // using the bits from the RHS. Below, we use knowledge about the RHS to
1272 // simplify the LHS, here we're using information from the LHS to simplify
1273 // the RHS.
1274 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1275 APInt LHSZero, LHSOne;
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1276 // Do not increment Depth here; that can cause an infinite loop.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1277 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1278 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1279 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1280 return TLO.CombineTo(Op, Op.getOperand(0));
1281 // If any of the set bits in the RHS are known zero on the LHS, shrink
1282 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1283 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1284 return true;
1285 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1286
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1287 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1288 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1289 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1290 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1291 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1292 KnownZero2, KnownOne2, TLO, Depth+1))
1293 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1294 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1295
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1296 // If all of the demanded bits are known one on one side, return the other.
1297 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1298 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1299 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1300 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1301 return TLO.CombineTo(Op, Op.getOperand(1));
1302 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1303 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1304 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1305 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1306 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1307 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1308 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1309 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1310 return true;
1311
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1312 // Output known-1 bits are only known if set in both the LHS & RHS.
1313 KnownOne &= KnownOne2;
1314 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1315 KnownZero |= KnownZero2;
1316 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1317 case ISD::OR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1318 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1319 KnownOne, TLO, Depth+1))
1320 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1321 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1322 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1323 KnownZero2, KnownOne2, TLO, Depth+1))
1324 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1325 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1326
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1327 // If all of the demanded bits are known zero on one side, return the other.
1328 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1329 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1330 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1331 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1332 return TLO.CombineTo(Op, Op.getOperand(1));
1333 // If all of the potentially set bits on one side are known to be set on
1334 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1335 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1336 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1337 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1338 return TLO.CombineTo(Op, Op.getOperand(1));
1339 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1340 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1341 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1342 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1343 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1344 return true;
1345
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1346 // Output known-0 bits are only known if clear in both the LHS & RHS.
1347 KnownZero &= KnownZero2;
1348 // Output known-1 are known to be set if set in either the LHS | RHS.
1349 KnownOne |= KnownOne2;
1350 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1351 case ISD::XOR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1352 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1353 KnownOne, TLO, Depth+1))
1354 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1355 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1356 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1357 KnownOne2, TLO, Depth+1))
1358 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1359 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1360
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1361 // If all of the demanded bits are known zero on one side, return the other.
1362 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1363 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1364 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1365 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1366 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1367 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1368 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1369 return true;
1370
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1371 // If all of the unknown bits are known to be zero on one side or the other
1372 // (but not both) turn this into an *inclusive* or.
1373 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1374 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1375 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1376 Op.getOperand(0),
1377 Op.getOperand(1)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1378
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1379 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1380 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1381 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1382 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1383
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1384 // If all of the demanded bits on one side are known, and all of the set
1385 // bits on that side are also known to be set on the other side, turn this
1386 // into an AND, as we know the bits will be cleared.
1387 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1388 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1389 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1390 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1391 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1392 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1393 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1394 }
1395 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1396
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1397 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1398 // for XOR, we prefer to force bits to 1 if they will make a -1.
1399 // if we can't force bits, try to shrink constant
1400 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1401 APInt Expanded = C->getAPIntValue() | (~NewMask);
1402 // if we can expand it to have all bits set, do it
1403 if (Expanded.isAllOnesValue()) {
1404 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1405 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1406 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1407 TLO.DAG.getConstant(Expanded, VT));
1408 return TLO.CombineTo(Op, New);
1409 }
1410 // if it already has all the bits set, nothing to change
1411 // but don't shrink either!
1412 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1413 return true;
1414 }
1415 }
1416
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1417 KnownZero = KnownZeroOut;
1418 KnownOne = KnownOneOut;
1419 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1420 case ISD::SELECT:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1421 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1422 KnownOne, TLO, Depth+1))
1423 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1424 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1425 KnownOne2, TLO, Depth+1))
1426 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1427 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1428 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1429
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1430 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1431 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1432 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1433
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1434 // Only known if known in both the LHS and RHS.
1435 KnownOne &= KnownOne2;
1436 KnownZero &= KnownZero2;
1437 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1438 case ISD::SELECT_CC:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1439 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1440 KnownOne, TLO, Depth+1))
1441 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1442 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1443 KnownOne2, TLO, Depth+1))
1444 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1445 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1446 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1447
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1448 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1449 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1450 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1451
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1452 // Only known if known in both the LHS and RHS.
1453 KnownOne &= KnownOne2;
1454 KnownZero &= KnownZero2;
1455 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1456 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1457 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1458 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1459 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1460
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1461 // If the shift count is an invalid immediate, don't do anything.
1462 if (ShAmt >= BitWidth)
1463 break;
1464
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1465 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1466 // single shift. We can do this if the bottom bits (which are shifted
1467 // out) are never demanded.
1468 if (InOp.getOpcode() == ISD::SRL &&
1469 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1470 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1471 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1472 unsigned Opc = ISD::SHL;
1473 int Diff = ShAmt-C1;
1474 if (Diff < 0) {
1475 Diff = -Diff;
1476 Opc = ISD::SRL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1477 }
1478
1479 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1480 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1481 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1482 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1483 InOp.getOperand(0), NewSA));
1484 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1485 }
1486
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1487 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1488 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1489 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1490
1491 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1492 // are not demanded. This will likely allow the anyext to be folded away.
1493 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1494 SDValue InnerOp = InOp.getNode()->getOperand(0);
1495 EVT InnerVT = InnerOp.getValueType();
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1496 unsigned InnerBits = InnerVT.getSizeInBits();
1497 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1498 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]1499 EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1500 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1501 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1502 SDValue NarrowShl =
1503 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1504 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1505 return
1506 TLO.CombineTo(Op,
1507 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1508 NarrowShl));
1509 }
1510 }
1511
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1512 KnownZero <<= SA->getZExtValue();
1513 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1514 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1515 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1516 }
1517 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1518 case ISD::SRL:
1519 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1520 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1521 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1522 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1523 SDValue InOp = Op.getOperand(0);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1524
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1525 // If the shift count is an invalid immediate, don't do anything.
1526 if (ShAmt >= BitWidth)
1527 break;
1528
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1529 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1530 // single shift. We can do this if the top bits (which are shifted out)
1531 // are never demanded.
1532 if (InOp.getOpcode() == ISD::SHL &&
1533 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1534 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1535 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1536 unsigned Opc = ISD::SRL;
1537 int Diff = ShAmt-C1;
1538 if (Diff < 0) {
1539 Diff = -Diff;
1540 Opc = ISD::SHL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1541 }
1542
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1543 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1544 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1545 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1546 InOp.getOperand(0), NewSA));
1547 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1548 }
1549
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1550 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1551 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1552 KnownZero, KnownOne, TLO, Depth+1))
1553 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1554 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1555 KnownZero = KnownZero.lshr(ShAmt);
1556 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1557
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1558 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1559 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1560 }
1561 break;
1562 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1563 // If this is an arithmetic shift right and only the low-bit is set, we can
1564 // always convert this into a logical shr, even if the shift amount is
1565 // variable. The low bit of the shift cannot be an input sign bit unless
1566 // the shift amount is >= the size of the datatype, which is undefined.
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1567 if (NewMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1568 return TLO.CombineTo(Op,
1569 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1570 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1571
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1572 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1573 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1574 unsigned ShAmt = SA->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1575
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1576 // If the shift count is an invalid immediate, don't do anything.
1577 if (ShAmt >= BitWidth)
1578 break;
1579
1580 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1581
1582 // If any of the demanded bits are produced by the sign extension, we also
1583 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1584 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1585 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1586 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1587
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1588 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1589 KnownZero, KnownOne, TLO, Depth+1))
1590 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1591 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1592 KnownZero = KnownZero.lshr(ShAmt);
1593 KnownOne = KnownOne.lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1594
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1595 // Handle the sign bit, adjusted to where it is now in the mask.
1596 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1597
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1598 // If the input sign bit is known to be zero, or if none of the top bits
1599 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1600 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1601 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1602 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1603 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1604 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1605 KnownOne |= HighBits;
1606 }
1607 }
1608 break;
1609 case ISD::SIGN_EXTEND_INREG: {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1610 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1611
1612 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1613 // If we only care about the highest bit, don't bother shifting right.
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1614 if (MsbMask == DemandedMask) {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1615 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1616 SDValue InOp = Op.getOperand(0);
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1617
1618 // Compute the correct shift amount type, which must be getShiftAmountTy
1619 // for scalar types after legalization.
1620 EVT ShiftAmtTy = Op.getValueType();
1621 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1622 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1623
1624 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1625 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1626 Op.getValueType(), InOp, ShiftAmt));
1627 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1628
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1629 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1630 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1631 APInt NewBits =
1632 APInt::getHighBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1633 BitWidth - ExVT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1634
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1635 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1636 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1637 return TLO.CombineTo(Op, Op.getOperand(0));
1638
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1639 APInt InSignBit =
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1640 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1641 APInt InputDemandedBits =
1642 APInt::getLowBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1643 ExVT.getScalarType().getSizeInBits()) &
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1644 NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1645
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1646 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1647 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1648 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1649
1650 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1651 KnownZero, KnownOne, TLO, Depth+1))
1652 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1653 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1654
1655 // If the sign bit of the input is known set or clear, then we know the
1656 // top bits of the result.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1657
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1658 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1659 if (KnownZero.intersects(InSignBit))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1660 return TLO.CombineTo(Op,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1661 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1662
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1663 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1664 KnownOne |= NewBits;
1665 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1666 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1667 KnownZero &= ~NewBits;
1668 KnownOne &= ~NewBits;
1669 }
1670 break;
1671 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1672 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1673 unsigned OperandBitWidth =
1674 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1675 APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1676
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1677 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1678 APInt NewBits =
1679 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1680 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1681 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1682 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1683 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1684
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1685 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1686 KnownZero, KnownOne, TLO, Depth+1))
1687 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1688 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1689 KnownZero = KnownZero.zext(BitWidth);
1690 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1691 KnownZero |= NewBits;
1692 break;
1693 }
1694 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1695 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1696 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1697 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1698 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1699 APInt NewBits = ~InMask & NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1700
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1701 // If none of the top bits are demanded, convert this into an any_extend.
1702 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1703 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1704 Op.getValueType(),
1705 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1706
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1707 // Since some of the sign extended bits are demanded, we know that the sign
1708 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1709 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1710 InDemandedBits |= InSignBit;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1711 InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1712
1713 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1714 KnownOne, TLO, Depth+1))
1715 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1716 KnownZero = KnownZero.zext(BitWidth);
1717 KnownOne = KnownOne.zext(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1718
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1719 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1720 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1721 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1722 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1723 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1724
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1725 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1726 if (KnownOne.intersects(InSignBit)) {
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1727 KnownOne |= NewBits;
1728 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1729 } else { // Otherwise, top bits aren't known.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1730 assert((KnownOne & NewBits) == 0);
1731 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1732 }
1733 break;
1734 }
1735 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1736 unsigned OperandBitWidth =
1737 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1738 APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1739 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1740 KnownZero, KnownOne, TLO, Depth+1))
1741 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1742 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1743 KnownZero = KnownZero.zext(BitWidth);
1744 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1745 break;
1746 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1747 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1748 // Simplify the input, using demanded bit information, and compute the known
1749 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1750 unsigned OperandBitWidth =
1751 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1752 APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1753 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1754 KnownZero, KnownOne, TLO, Depth+1))
1755 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1756 KnownZero = KnownZero.trunc(BitWidth);
1757 KnownOne = KnownOne.trunc(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1758
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1759 // If the input is only used by this truncate, see if we can shrink it based
1760 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1761 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1762 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1763 switch (In.getOpcode()) {
1764 default: break;
1765 case ISD::SRL:
1766 // Shrink SRL by a constant if none of the high bits shifted in are
1767 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1768 if (TLO.LegalTypes() &&
1769 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1770 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1771 // undesirable.
1772 break;
1773 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1774 if (!ShAmt)
1775 break;
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1776 SDValue Shift = In.getOperand(1);
1777 if (TLO.LegalTypes()) {
1778 uint64_t ShVal = ShAmt->getZExtValue();
1779 Shift =
1780 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1781 }
1782
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1783 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1784 OperandBitWidth - BitWidth);
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1785 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1786
1787 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1788 // None of the shifted in bits are needed. Add a truncate of the
1789 // shift input, then shift it.
1790 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1791 Op.getValueType(),
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1792 In.getOperand(0));
1793 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1794 Op.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1795 NewTrunc,
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1796 Shift));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1797 }
1798 break;
1799 }
1800 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1801
1802 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1803 break;
1804 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1805 case ISD::AssertZext: {
Owen Anderson7ab15f62011-09-03 00:26:49 +0000[diff] [blame]1806 // AssertZext demands all of the high bits, plus any of the low bits
1807 // demanded by its users.
1808 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1809 APInt InMask = APInt::getLowBitsSet(BitWidth,
1810 VT.getSizeInBits());
1811 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1812 KnownZero, KnownOne, TLO, Depth+1))
1813 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1814 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1815
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1816 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1817 break;
1818 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1819 case ISD::BITCAST:
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1820 // If this is an FP->Int bitcast and if the sign bit is the only
1821 // thing demanded, turn this into a FGETSIGN.
Eli Friedmanca072a32011-12-15 02:07:20 +0000[diff] [blame]1822 if (!TLO.LegalOperations() &&
1823 !Op.getValueType().isVector() &&
Eli Friedman0948f0a2011-11-09 22:25:12 +0000[diff] [blame]1824 !Op.getOperand(0).getValueType().isVector() &&
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1825 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1826 Op.getOperand(0).getValueType().isFloatingPoint()) {
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1827 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1828 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1829 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1830 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1831 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1832 // place. We expect the SHL to be eliminated by other optimizations.
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1833 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1834 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1835 if (!OpVTLegal && OpVTSizeInBits > 32)
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1836 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1837 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Stuart Hastingsbdce3722011-06-01 14:04:17 +0000[diff] [blame]1838 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Stuart Hastings3dfc4b122011-05-19 18:48:20 +0000[diff] [blame]1839 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1840 Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1841 Sign, ShAmt));
1842 }
1843 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1844 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1845 case ISD::ADD:
1846 case ISD::MUL:
1847 case ISD::SUB: {
1848 // Add, Sub, and Mul don't demand any bits in positions beyond that
1849 // of the highest bit demanded of them.
1850 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1851 BitWidth - NewMask.countLeadingZeros());
1852 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1853 KnownOne2, TLO, Depth+1))
1854 return true;
1855 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1856 KnownOne2, TLO, Depth+1))
1857 return true;
1858 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1859 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1860 return true;
1861 }
1862 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1863 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1864 // Just use ComputeMaskedBits to compute output bits.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1865 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1866 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1867 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1868
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1869 // If we know the value of all of the demanded bits, return this as a
1870 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1871 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1872 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1873
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1874 return false;
1875}
1876
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1877/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1878/// in Mask are known to be either zero or one and return them in the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1879/// KnownZero/KnownOne bitsets.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1880void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1881 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1882 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1883 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1884 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1885 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1886 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1887 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1888 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1889 "Should use MaskedValueIsZero if you don't know whether Op"
1890 " is a target node!");
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1891 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1892}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1893
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1894/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1895/// targets that want to expose additional information about sign bits to the
1896/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1897unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1898 unsigned Depth) const {
1899 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1900 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1901 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1902 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1903 "Should use ComputeNumSignBits if you don't know whether Op"
1904 " is a target node!");
1905 return 1;
1906}
1907
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1908/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1909/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1910/// determine which bit is set.
1911///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1912static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1913 // A left-shift of a constant one will have exactly one bit set, because
1914 // shifting the bit off the end is undefined.
1915 if (Val.getOpcode() == ISD::SHL)
1916 if (ConstantSDNode *C =
1917 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1918 if (C->getAPIntValue() == 1)
1919 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1920
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1921 // Similarly, a right-shift of a constant sign-bit will have exactly
1922 // one bit set.
1923 if (Val.getOpcode() == ISD::SRL)
1924 if (ConstantSDNode *C =
1925 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1926 if (C->getAPIntValue().isSignBit())
1927 return true;
1928
1929 // More could be done here, though the above checks are enough
1930 // to handle some common cases.
1931
1932 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1933 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1934 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1935 APInt KnownZero, KnownOne;
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1936 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1937 return (KnownZero.countPopulation() == BitWidth - 1) &&
1938 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1939}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1940
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1941/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1942/// and cc. If it is unable to simplify it, return a null SDValue.
1943SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1944TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1945 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1946 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1947 SelectionDAG &DAG = DCI.DAG;
1948
1949 // These setcc operations always fold.
1950 switch (Cond) {
1951 default: break;
1952 case ISD::SETFALSE:
1953 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1954 case ISD::SETTRUE:
1955 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1956 }
1957
Chris Lattner7a2bdde2011-04-15 05:18:47 +0000[diff] [blame]1958 // Ensure that the constant occurs on the RHS, and fold constant
1959 // comparisons.
1960 if (isa<ConstantSDNode>(N0.getNode()))
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1961 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]1962
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1963 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1964 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1965
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1966 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1967 // equality comparison, then we're just comparing whether X itself is
1968 // zero.
1969 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1970 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1971 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1972 const APInt &ShAmt
1973 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1974 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1975 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1976 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1977 // (srl (ctlz x), 5) == 0 -> X != 0
1978 // (srl (ctlz x), 5) != 1 -> X != 0
1979 Cond = ISD::SETNE;
1980 } else {
1981 // (srl (ctlz x), 5) != 0 -> X == 0
1982 // (srl (ctlz x), 5) == 1 -> X == 0
1983 Cond = ISD::SETEQ;
1984 }
1985 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1986 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1987 Zero, Cond);
1988 }
1989 }
1990
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1991 SDValue CTPOP = N0;
1992 // Look through truncs that don't change the value of a ctpop.
1993 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1994 CTPOP = N0.getOperand(0);
1995
1996 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramerc9b6a3e2011-01-17 18:00:28 +0000[diff] [blame]1997 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1998 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1999 EVT CTVT = CTPOP.getValueType();
2000 SDValue CTOp = CTPOP.getOperand(0);
2001
2002 // (ctpop x) u< 2 -> (x & x-1) == 0
2003 // (ctpop x) u> 1 -> (x & x-1) != 0
2004 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
2005 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
2006 DAG.getConstant(1, CTVT));
2007 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
2008 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
2009 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
2010 }
2011
2012 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
2013 }
2014
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]2015 // (zext x) == C --> x == (trunc C)
2016 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
2017 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2018 unsigned MinBits = N0.getValueSizeInBits();
2019 SDValue PreZExt;
2020 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2021 // ZExt
2022 MinBits = N0->getOperand(0).getValueSizeInBits();
2023 PreZExt = N0->getOperand(0);
2024 } else if (N0->getOpcode() == ISD::AND) {
2025 // DAGCombine turns costly ZExts into ANDs
2026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2027 if ((C->getAPIntValue()+1).isPowerOf2()) {
2028 MinBits = C->getAPIntValue().countTrailingOnes();
2029 PreZExt = N0->getOperand(0);
2030 }
2031 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2032 // ZEXTLOAD
2033 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2034 MinBits = LN0->getMemoryVT().getSizeInBits();
2035 PreZExt = N0;
2036 }
2037 }
2038
2039 // Make sure we're not loosing bits from the constant.
2040 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2041 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2042 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2043 // Will get folded away.
2044 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2045 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2046 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2047 }
2048 }
2049 }
2050
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2051 // If the LHS is '(and load, const)', the RHS is 0,
2052 // the test is for equality or unsigned, and all 1 bits of the const are
2053 // in the same partial word, see if we can shorten the load.
2054 if (DCI.isBeforeLegalize() &&
2055 N0.getOpcode() == ISD::AND && C1 == 0 &&
2056 N0.getNode()->hasOneUse() &&
2057 isa<LoadSDNode>(N0.getOperand(0)) &&
2058 N0.getOperand(0).getNode()->hasOneUse() &&
2059 isa<ConstantSDNode>(N0.getOperand(1))) {
2060 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2061 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2062 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2063 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2064 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2065 unsigned maskWidth = origWidth;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2066 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2067 // 8 bits, but have to be careful...
2068 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2069 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2070 const APInt &Mask =
2071 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2072 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2073 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2074 for (unsigned offset=0; offset<origWidth/width; offset++) {
2075 if ((newMask & Mask) == Mask) {
2076 if (!TD->isLittleEndian())
2077 bestOffset = (origWidth/width - offset - 1) * (width/8);
2078 else
2079 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2080 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2081 bestWidth = width;
2082 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2083 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2084 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2085 }
2086 }
2087 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2088 if (bestWidth) {
Chris Lattnerc0c7fca2011-04-14 04:12:47 +0000[diff] [blame]2089 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2090 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2091 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2092 SDValue Ptr = Lod->getBasePtr();
2093 if (bestOffset != 0)
2094 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2095 DAG.getConstant(bestOffset, PtrType));
2096 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2097 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattnerecf42c42010-09-21 16:36:31 +0000[diff] [blame]2098 Lod->getPointerInfo().getWithOffset(bestOffset),
Pete Cooperd752e0f2011-11-08 18:42:53 +0000[diff] [blame]2099 false, false, false, NewAlign);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2100 return DAG.getSetCC(dl, VT,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2101 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2102 DAG.getConstant(bestMask.trunc(bestWidth),
2103 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2104 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2105 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2106 }
2107 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2108
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2109 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2110 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2111 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2112
2113 // If the comparison constant has bits in the upper part, the
2114 // zero-extended value could never match.
2115 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2116 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2117 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2118 case ISD::SETUGT:
2119 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2120 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2121 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2122 case ISD::SETULE:
2123 case ISD::SETNE: return DAG.getConstant(1, VT);
2124 case ISD::SETGT:
2125 case ISD::SETGE:
2126 // True if the sign bit of C1 is set.
2127 return DAG.getConstant(C1.isNegative(), VT);
2128 case ISD::SETLT:
2129 case ISD::SETLE:
2130 // True if the sign bit of C1 isn't set.
2131 return DAG.getConstant(C1.isNonNegative(), VT);
2132 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]2133 break;
2134 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2135 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2136
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2137 // Otherwise, we can perform the comparison with the low bits.
2138 switch (Cond) {
2139 case ISD::SETEQ:
2140 case ISD::SETNE:
2141 case ISD::SETUGT:
2142 case ISD::SETUGE:
2143 case ISD::SETULT:
2144 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2145 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2146 if (DCI.isBeforeLegalizeOps() ||
2147 (isOperationLegal(ISD::SETCC, newVT) &&
2148 getCondCodeAction(Cond, newVT)==Legal))
2149 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]2150 DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2151 Cond);
2152 break;
2153 }
2154 default:
2155 break; // todo, be more careful with signed comparisons
2156 }
2157 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2158 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2159 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2160 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2161 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2162 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2163
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]2164 // If the constant doesn't fit into the number of bits for the source of
2165 // the sign extension, it is impossible for both sides to be equal.
2166 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2167 return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2168
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2169 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2170 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2171 if (Op0Ty == ExtSrcTy) {
2172 ZextOp = N0.getOperand(0);
2173 } else {
2174 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2175 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2176 DAG.getConstant(Imm, Op0Ty));
2177 }
2178 if (!DCI.isCalledByLegalizer())
2179 DCI.AddToWorklist(ZextOp.getNode());
2180 // Otherwise, make this a use of a zext.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2181 return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2182 DAG.getConstant(C1 & APInt::getLowBitsSet(
2183 ExtDstTyBits,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2184 ExtSrcTyBits),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2185 ExtDstTy),
2186 Cond);
2187 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2188 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2189 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2190 if (N0.getOpcode() == ISD::SETCC &&
2191 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2192 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2193 if (TrueWhenTrue)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2194 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2195 // Invert the condition.
2196 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2197 CC = ISD::getSetCCInverse(CC,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2198 N0.getOperand(0).getValueType().isInteger());
2199 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2200 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2201
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2202 if ((N0.getOpcode() == ISD::XOR ||
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2203 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2204 N0.getOperand(0).getOpcode() == ISD::XOR &&
2205 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2206 isa<ConstantSDNode>(N0.getOperand(1)) &&
2207 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2208 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2209 // can only do this if the top bits are known zero.
2210 unsigned BitWidth = N0.getValueSizeInBits();
2211 if (DAG.MaskedValueIsZero(N0,
2212 APInt::getHighBitsSet(BitWidth,
2213 BitWidth-1))) {
2214 // Okay, get the un-inverted input value.
2215 SDValue Val;
2216 if (N0.getOpcode() == ISD::XOR)
2217 Val = N0.getOperand(0);
2218 else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2219 assert(N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2220 N0.getOperand(0).getOpcode() == ISD::XOR);
2221 // ((X^1)&1)^1 -> X & 1
2222 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2223 N0.getOperand(0).getOperand(0),
2224 N0.getOperand(1));
2225 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2226
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2227 return DAG.getSetCC(dl, VT, Val, N1,
2228 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2229 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2230 } else if (N1C->getAPIntValue() == 1 &&
2231 (VT == MVT::i1 ||
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]2232 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2233 SDValue Op0 = N0;
2234 if (Op0.getOpcode() == ISD::TRUNCATE)
2235 Op0 = Op0.getOperand(0);
2236
2237 if ((Op0.getOpcode() == ISD::XOR) &&
2238 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2239 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2240 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2241 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2242 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2243 Cond);
2244 } else if (Op0.getOpcode() == ISD::AND &&
2245 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2246 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2247 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2248 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2249 Op0 = DAG.getNode(ISD::AND, dl, VT,
2250 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2251 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2252 else if (Op0.getValueType().bitsLT(VT))
2253 Op0 = DAG.getNode(ISD::AND, dl, VT,
2254 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2255 DAG.getConstant(1, VT));
2256
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2257 return DAG.getSetCC(dl, VT, Op0,
2258 DAG.getConstant(0, Op0.getValueType()),
2259 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2260 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2261 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2262 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2263
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2264 APInt MinVal, MaxVal;
2265 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2266 if (ISD::isSignedIntSetCC(Cond)) {
2267 MinVal = APInt::getSignedMinValue(OperandBitSize);
2268 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2269 } else {
2270 MinVal = APInt::getMinValue(OperandBitSize);
2271 MaxVal = APInt::getMaxValue(OperandBitSize);
2272 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2273
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2274 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2275 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2276 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2277 // X >= C0 --> X > (C0-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2278 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2279 DAG.getConstant(C1-1, N1.getValueType()),
2280 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2281 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2282
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2283 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2284 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2285 // X <= C0 --> X < (C0+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2286 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2287 DAG.getConstant(C1+1, N1.getValueType()),
2288 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2289 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2290
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2291 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2292 return DAG.getConstant(0, VT); // X < MIN --> false
2293 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2294 return DAG.getConstant(1, VT); // X >= MIN --> true
2295 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2296 return DAG.getConstant(0, VT); // X > MAX --> false
2297 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2298 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2299
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2300 // Canonicalize setgt X, Min --> setne X, Min
2301 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2302 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2303 // Canonicalize setlt X, Max --> setne X, Max
2304 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2305 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2306
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2307 // If we have setult X, 1, turn it into seteq X, 0
2308 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2309 return DAG.getSetCC(dl, VT, N0,
2310 DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2311 ISD::SETEQ);
2312 // If we have setugt X, Max-1, turn it into seteq X, Max
2313 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2314 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2315 DAG.getConstant(MaxVal, N0.getValueType()),
2316 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2317
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2318 // If we have "setcc X, C0", check to see if we can shrink the immediate
2319 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2320
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2321 // SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2322 if (Cond == ISD::SETUGT &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2323 C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2324 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2325 DAG.getConstant(0, N1.getValueType()),
2326 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2327
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2328 // SETULT X, SINTMIN -> SETGT X, -1
2329 if (Cond == ISD::SETULT &&
2330 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2331 SDValue ConstMinusOne =
2332 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2333 N1.getValueType());
2334 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2335 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2336
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2337 // Fold bit comparisons when we can.
2338 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2339 (VT == N0.getValueType() ||
2340 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2341 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2342 if (ConstantSDNode *AndRHS =
2343 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2344 EVT ShiftTy = DCI.isBeforeLegalize() ?
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2345 getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2346 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2347 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2348 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2349 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2350 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2351 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2352 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2353 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2354 // (X & 8) == 8 --> (X & 8) >> 3
2355 // Perform the xform if C1 is a single bit.
2356 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2357 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2358 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2359 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2360 }
2361 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2362 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2363 }
2364
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2365 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2366 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2367 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2368 if (O.getNode()) return O;
2369 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2370 // If the RHS of an FP comparison is a constant, simplify it away in
2371 // some cases.
2372 if (CFP->getValueAPF().isNaN()) {
2373 // If an operand is known to be a nan, we can fold it.
2374 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2375 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2376 case 0: // Known false.
2377 return DAG.getConstant(0, VT);
2378 case 1: // Known true.
2379 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2380 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2381 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2382 }
2383 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2384
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2385 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2386 // constant if knowing that the operand is non-nan is enough. We prefer to
2387 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2388 // materialize 0.0.
2389 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2390 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2391
2392 // If the condition is not legal, see if we can find an equivalent one
2393 // which is legal.
2394 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2395 // If the comparison was an awkward floating-point == or != and one of
2396 // the comparison operands is infinity or negative infinity, convert the
2397 // condition to a less-awkward <= or >=.
2398 if (CFP->getValueAPF().isInfinity()) {
2399 if (CFP->getValueAPF().isNegative()) {
2400 if (Cond == ISD::SETOEQ &&
2401 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2402 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2403 if (Cond == ISD::SETUEQ &&
2404 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2405 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2406 if (Cond == ISD::SETUNE &&
2407 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2408 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2409 if (Cond == ISD::SETONE &&
2410 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2411 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2412 } else {
2413 if (Cond == ISD::SETOEQ &&
2414 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2415 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2416 if (Cond == ISD::SETUEQ &&
2417 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2418 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2419 if (Cond == ISD::SETUNE &&
2420 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2421 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2422 if (Cond == ISD::SETONE &&
2423 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2424 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2425 }
2426 }
2427 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2428 }
2429
2430 if (N0 == N1) {
2431 // We can always fold X == X for integer setcc's.
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2432 if (N0.getValueType().isInteger()) {
2433 switch (getBooleanContents(N0.getValueType().isVector())) {
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2434 case UndefinedBooleanContent:
2435 case ZeroOrOneBooleanContent:
2436 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2437 case ZeroOrNegativeOneBooleanContent:
2438 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
2439 }
2440 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2441 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2442 if (UOF == 2) // FP operators that are undefined on NaNs.
2443 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2444 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2445 return DAG.getConstant(UOF, VT);
2446 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2447 // if it is not already.
2448 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2449 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2450 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2451 }
2452
2453 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2454 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2455 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2456 N0.getOpcode() == ISD::XOR) {
2457 // Simplify (X+Y) == (X+Z) --> Y == Z
2458 if (N0.getOpcode() == N1.getOpcode()) {
2459 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2460 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2461 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2462 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2463 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2464 // If X op Y == Y op X, try other combinations.
2465 if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2466 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2467 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2468 if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2469 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2470 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2471 }
2472 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2473
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2474 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2475 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2476 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2477 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2478 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2479 DAG.getConstant(RHSC->getAPIntValue()-
2480 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2481 N0.getValueType()), Cond);
2482 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2483
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2484 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2485 if (N0.getOpcode() == ISD::XOR)
2486 // If we know that all of the inverted bits are zero, don't bother
2487 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2488 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2489 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2490 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2491 DAG.getConstant(LHSR->getAPIntValue() ^
2492 RHSC->getAPIntValue(),
2493 N0.getValueType()),
2494 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2495 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2496
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2497 // Turn (C1-X) == C2 --> X == C1-C2
2498 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2499 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2500 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2501 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2502 DAG.getConstant(SUBC->getAPIntValue() -
2503 RHSC->getAPIntValue(),
2504 N0.getValueType()),
2505 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2506 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2507 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2508 }
2509
2510 // Simplify (X+Z) == X --> Z == 0
2511 if (N0.getOperand(0) == N1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2512 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2513 DAG.getConstant(0, N0.getValueType()), Cond);
2514 if (N0.getOperand(1) == N1) {
2515 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2516 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2517 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2518 else if (N0.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2519 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2520 // (Z-X) == X --> Z == X<<1
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2521 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2522 N1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2523 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2524 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2525 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2526 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2527 }
2528 }
2529 }
2530
2531 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2532 N1.getOpcode() == ISD::XOR) {
2533 // Simplify X == (X+Z) --> Z == 0
2534 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2535 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2536 DAG.getConstant(0, N1.getValueType()), Cond);
2537 } else if (N1.getOperand(1) == N0) {
2538 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2539 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2540 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2541 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2542 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2543 // X == (Z-X) --> X<<1 == Z
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2544 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2545 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2546 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2547 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2548 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2549 }
2550 }
2551 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2552
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2553 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2554 // Note that where y is variable and is known to have at most
2555 // one bit set (for example, if it is z&1) we cannot do this;
2556 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2557 if (N0.getOpcode() == ISD::AND)
2558 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2559 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2560 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2561 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2562 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2563 }
2564 }
2565 if (N1.getOpcode() == ISD::AND)
2566 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2567 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2568 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2569 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2570 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2571 }
2572 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2573 }
2574
2575 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2576 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2577 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2578 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2579 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2580 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2581 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2582 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2583 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2584 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2585 break;
2586 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2587 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2588 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2589 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2590 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2591 Temp = DAG.getNOT(dl, N0, MVT::i1);
2592 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2593 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2594 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2595 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2596 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2597 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2598 Temp = DAG.getNOT(dl, N1, MVT::i1);
2599 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2600 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2601 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2602 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2603 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2604 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2605 Temp = DAG.getNOT(dl, N0, MVT::i1);
2606 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2607 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2608 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2609 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2610 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2611 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2612 Temp = DAG.getNOT(dl, N1, MVT::i1);
2613 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2614 break;
2615 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2616 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2617 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2618 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2619 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2620 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2621 }
2622 return N0;
2623 }
2624
2625 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2626 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2627}
2628
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2629/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2630/// node is a GlobalAddress + offset.
Chris Lattner0a9481f2011-02-13 22:25:43 +0000[diff] [blame]2631bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2632 int64_t &Offset) const {
2633 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2634 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2635 GA = GASD->getGlobal();
2636 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2637 return true;
2638 }
2639
2640 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2641 SDValue N1 = N->getOperand(0);
2642 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2643 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2644 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2645 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2646 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2647 return true;
2648 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2649 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2650 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2651 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2652 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2653 return true;
2654 }
2655 }
2656 }
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2657
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2658 return false;
2659}
2660
2661
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2662SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2663PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2664 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2665 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2666}
2667
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2668//===----------------------------------------------------------------------===//
2669// Inline Assembler Implementation Methods
2670//===----------------------------------------------------------------------===//
2671
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2672
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2673TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2674TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2675 if (Constraint.size() == 1) {
2676 switch (Constraint[0]) {
2677 default: break;
2678 case 'r': return C_RegisterClass;
2679 case 'm': // memory
2680 case 'o': // offsetable
2681 case 'V': // not offsetable
2682 return C_Memory;
2683 case 'i': // Simple Integer or Relocatable Constant
2684 case 'n': // Simple Integer
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2685 case 'E': // Floating Point Constant
2686 case 'F': // Floating Point Constant
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2687 case 's': // Relocatable Constant
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2688 case 'p': // Address.
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2689 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2690 case 'I': // Target registers.
2691 case 'J':
2692 case 'K':
2693 case 'L':
2694 case 'M':
2695 case 'N':
2696 case 'O':
2697 case 'P':
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2698 case '<':
2699 case '>':
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2700 return C_Other;
2701 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2702 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2703
2704 if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2705 Constraint[Constraint.size()-1] == '}')
2706 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2707 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2708}
2709
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2710/// LowerXConstraint - try to replace an X constraint, which matches anything,
2711/// with another that has more specific requirements based on the type of the
2712/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2713const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2714 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2715 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2716 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2717 return "f"; // works for many targets
2718 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2719}
2720
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2721/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2722/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2723void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2724 std::string &Constraint,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2725 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2726 SelectionDAG &DAG) const {
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2727
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2728 if (Constraint.length() > 1) return;
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2729
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2730 char ConstraintLetter = Constraint[0];
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2731 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2732 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2733 case 'X': // Allows any operand; labels (basic block) use this.
2734 if (Op.getOpcode() == ISD::BasicBlock) {
2735 Ops.push_back(Op);
2736 return;
2737 }
2738 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2739 case 'i': // Simple Integer or Relocatable Constant
2740 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2741 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2742 // These operands are interested in values of the form (GV+C), where C may
2743 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2744 // is possible and fine if either GV or C are missing.
2745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2746 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2747
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2748 // If we have "(add GV, C)", pull out GV/C
2749 if (Op.getOpcode() == ISD::ADD) {
2750 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2751 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2752 if (C == 0 || GA == 0) {
2753 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2754 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2755 }
2756 if (C == 0 || GA == 0)
2757 C = 0, GA = 0;
2758 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2759
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2760 // If we find a valid operand, map to the TargetXXX version so that the
2761 // value itself doesn't get selected.
2762 if (GA) { // Either &GV or &GV+C
2763 if (ConstraintLetter != 'n') {
2764 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2765 if (C) Offs += C->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2766 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2767 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2768 Op.getValueType(), Offs));
2769 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2770 }
2771 }
2772 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2773 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2774 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2775 // gcc prints these as sign extended. Sign extend value to 64 bits
2776 // now; without this it would get ZExt'd later in
2777 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2778 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2779 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2780 return;
2781 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2782 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2783 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2784 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2785 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2786}
2787
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2788std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2789getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2790 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2791 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2792 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2793 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2794
2795 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2796 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2797
2798 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2799 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2800 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2801 E = RI->regclass_end(); RCI != E; ++RCI) {
2802 const TargetRegisterClass *RC = *RCI;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2803
2804 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2805 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Jakob Stoklund Olesen22e8a362011-10-12 01:24:51 +0000[diff] [blame]2806 if (!isLegalRC(RC))
2807 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2808
2809 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2810 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2811 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2812 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2813 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2814 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2815
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2816 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2817}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2818
2819//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2820// Constraint Selection.
2821
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2822/// isMatchingInputConstraint - Return true of this is an input operand that is
2823/// a matching constraint like "4".
2824bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2825 assert(!ConstraintCode.empty() && "No known constraint!");
2826 return isdigit(ConstraintCode[0]);
2827}
2828
2829/// getMatchedOperand - If this is an input matching constraint, this method
2830/// returns the output operand it matches.
2831unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2832 assert(!ConstraintCode.empty() && "No known constraint!");
2833 return atoi(ConstraintCode.c_str());
2834}
2835
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2836
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2837/// ParseConstraints - Split up the constraint string from the inline
2838/// assembly value into the specific constraints and their prefixes,
2839/// and also tie in the associated operand values.
2840/// If this returns an empty vector, and if the constraint string itself
2841/// isn't empty, there was an error parsing.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2842TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2843 ImmutableCallSite CS) const {
2844 /// ConstraintOperands - Information about all of the constraints.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2845 AsmOperandInfoVector ConstraintOperands;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2846 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2847 unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2848
2849 // Do a prepass over the constraints, canonicalizing them, and building up the
2850 // ConstraintOperands list.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2851 InlineAsm::ConstraintInfoVector
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2852 ConstraintInfos = IA->ParseConstraints();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2853
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2854 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2855 unsigned ResNo = 0; // ResNo - The result number of the next output.
2856
2857 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2858 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2859 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2860
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2861 // Update multiple alternative constraint count.
2862 if (OpInfo.multipleAlternatives.size() > maCount)
2863 maCount = OpInfo.multipleAlternatives.size();
2864
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2865 OpInfo.ConstraintVT = MVT::Other;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2866
2867 // Compute the value type for each operand.
2868 switch (OpInfo.Type) {
2869 case InlineAsm::isOutput:
2870 // Indirect outputs just consume an argument.
2871 if (OpInfo.isIndirect) {
2872 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2873 break;
2874 }
2875
2876 // The return value of the call is this value. As such, there is no
2877 // corresponding argument.
2878 assert(!CS.getType()->isVoidTy() &&
2879 "Bad inline asm!");
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2880 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2881 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2882 } else {
2883 assert(ResNo == 0 && "Asm only has one result!");
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2884 OpInfo.ConstraintVT = getValueType(CS.getType());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2885 }
2886 ++ResNo;
2887 break;
2888 case InlineAsm::isInput:
2889 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2890 break;
2891 case InlineAsm::isClobber:
2892 // Nothing to do.
2893 break;
2894 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2895
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2896 if (OpInfo.CallOperandVal) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2897 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2898 if (OpInfo.isIndirect) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2899 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2900 if (!PtrTy)
2901 report_fatal_error("Indirect operand for inline asm not a pointer!");
2902 OpTy = PtrTy->getElementType();
2903 }
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2904
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2905 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2906 if (StructType *STy = dyn_cast<StructType>(OpTy))
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2907 if (STy->getNumElements() == 1)
2908 OpTy = STy->getElementType(0);
2909
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2910 // If OpTy is not a single value, it may be a struct/union that we
2911 // can tile with integers.
2912 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2913 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2914 switch (BitSize) {
2915 default: break;
2916 case 1:
2917 case 8:
2918 case 16:
2919 case 32:
2920 case 64:
2921 case 128:
Dale Johannesen71365d32010-11-09 01:15:07 +0000[diff] [blame]2922 OpInfo.ConstraintVT =
2923 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2924 break;
2925 }
2926 } else if (dyn_cast<PointerType>(OpTy)) {
2927 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2928 } else {
2929 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2930 }
2931 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2932 }
2933
2934 // If we have multiple alternative constraints, select the best alternative.
2935 if (ConstraintInfos.size()) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2936 if (maCount) {
2937 unsigned bestMAIndex = 0;
2938 int bestWeight = -1;
2939 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2940 int weight = -1;
2941 unsigned maIndex;
2942 // Compute the sums of the weights for each alternative, keeping track
2943 // of the best (highest weight) one so far.
2944 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2945 int weightSum = 0;
2946 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2947 cIndex != eIndex; ++cIndex) {
2948 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2949 if (OpInfo.Type == InlineAsm::isClobber)
2950 continue;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2951
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2952 // If this is an output operand with a matching input operand,
2953 // look up the matching input. If their types mismatch, e.g. one
2954 // is an integer, the other is floating point, or their sizes are
2955 // different, flag it as an maCantMatch.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2956 if (OpInfo.hasMatchingInput()) {
2957 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2958 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2959 if ((OpInfo.ConstraintVT.isInteger() !=
2960 Input.ConstraintVT.isInteger()) ||
2961 (OpInfo.ConstraintVT.getSizeInBits() !=
2962 Input.ConstraintVT.getSizeInBits())) {
2963 weightSum = -1; // Can't match.
2964 break;
2965 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2966 }
2967 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2968 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2969 if (weight == -1) {
2970 weightSum = -1;
2971 break;
2972 }
2973 weightSum += weight;
2974 }
2975 // Update best.
2976 if (weightSum > bestWeight) {
2977 bestWeight = weightSum;
2978 bestMAIndex = maIndex;
2979 }
2980 }
2981
2982 // Now select chosen alternative in each constraint.
2983 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2984 cIndex != eIndex; ++cIndex) {
2985 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2986 if (cInfo.Type == InlineAsm::isClobber)
2987 continue;
2988 cInfo.selectAlternative(bestMAIndex);
2989 }
2990 }
2991 }
2992
2993 // Check and hook up tied operands, choose constraint code to use.
2994 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2995 cIndex != eIndex; ++cIndex) {
2996 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2997
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2998 // If this is an output operand with a matching input operand, look up the
2999 // matching input. If their types mismatch, e.g. one is an integer, the
3000 // other is floating point, or their sizes are different, flag it as an
3001 // error.
3002 if (OpInfo.hasMatchingInput()) {
3003 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3004
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3005 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]3006 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3007 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
3008 std::pair<unsigned, const TargetRegisterClass*> InputRC =
3009 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3010 if ((OpInfo.ConstraintVT.isInteger() !=
3011 Input.ConstraintVT.isInteger()) ||
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]3012 (MatchRC.second != InputRC.second)) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3013 report_fatal_error("Unsupported asm: input constraint"
3014 " with a matching output constraint of"
3015 " incompatible type!");
3016 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3017 }
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3018
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3019 }
3020 }
3021
3022 return ConstraintOperands;
3023}
3024
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]3025
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3026/// getConstraintGenerality - Return an integer indicating how general CT
3027/// is.
3028static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3029 switch (CT) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3030 case TargetLowering::C_Other:
3031 case TargetLowering::C_Unknown:
3032 return 0;
3033 case TargetLowering::C_Register:
3034 return 1;
3035 case TargetLowering::C_RegisterClass:
3036 return 2;
3037 case TargetLowering::C_Memory:
3038 return 3;
3039 }
Chandler Carruth732f05c2012-01-10 18:08:01 +0000[diff] [blame]3040 llvm_unreachable("Invalid constraint type");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3041}
3042
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3043/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3044/// This object must already have been set up with the operand type
3045/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3046TargetLowering::ConstraintWeight
3047 TargetLowering::getMultipleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3048 AsmOperandInfo &info, int maIndex) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3049 InlineAsm::ConstraintCodeVector *rCodes;
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3050 if (maIndex >= (int)info.multipleAlternatives.size())
3051 rCodes = &info.Codes;
3052 else
3053 rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3054 ConstraintWeight BestWeight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3055
3056 // Loop over the options, keeping track of the most general one.
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3057 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3058 ConstraintWeight weight =
3059 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3060 if (weight > BestWeight)
3061 BestWeight = weight;
3062 }
3063
3064 return BestWeight;
3065}
3066
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3067/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3068/// This object must already have been set up with the operand type
3069/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3070TargetLowering::ConstraintWeight
3071 TargetLowering::getSingleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3072 AsmOperandInfo &info, const char *constraint) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3073 ConstraintWeight weight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3074 Value *CallOperandVal = info.CallOperandVal;
3075 // If we don't have a value, we can't do a match,
3076 // but allow it at the lowest weight.
3077 if (CallOperandVal == NULL)
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3078 return CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3079 // Look at the constraint type.
3080 switch (*constraint) {
3081 case 'i': // immediate integer.
3082 case 'n': // immediate integer with a known value.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3083 if (isa<ConstantInt>(CallOperandVal))
3084 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3085 break;
3086 case 's': // non-explicit intregal immediate.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3087 if (isa<GlobalValue>(CallOperandVal))
3088 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3089 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3090 case 'E': // immediate float if host format.
3091 case 'F': // immediate float.
3092 if (isa<ConstantFP>(CallOperandVal))
3093 weight = CW_Constant;
3094 break;
3095 case '<': // memory operand with autodecrement.
3096 case '>': // memory operand with autoincrement.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3097 case 'm': // memory operand.
3098 case 'o': // offsettable memory operand
3099 case 'V': // non-offsettable memory operand
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3100 weight = CW_Memory;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3101 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3102 case 'r': // general register.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3103 case 'g': // general register, memory operand or immediate integer.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3104 // note: Clang converts "g" to "imr".
3105 if (CallOperandVal->getType()->isIntegerTy())
3106 weight = CW_Register;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3107 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3108 case 'X': // any operand.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3109 default:
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3110 weight = CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3111 break;
3112 }
3113 return weight;
3114}
3115
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3116/// ChooseConstraint - If there are multiple different constraints that we
3117/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]3118/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3119/// Other -> immediates and magic values
3120/// Register -> one specific register
3121/// RegisterClass -> a group of regs
3122/// Memory -> memory
3123/// Ideally, we would pick the most specific constraint possible: if we have
3124/// something that fits into a register, we would pick it. The problem here
3125/// is that if we have something that could either be in a register or in
3126/// memory that use of the register could cause selection of *other*
3127/// operands to fail: they might only succeed if we pick memory. Because of
3128/// this the heuristic we use is:
3129///
3130/// 1) If there is an 'other' constraint, and if the operand is valid for
3131/// that constraint, use it. This makes us take advantage of 'i'
3132/// constraints when available.
3133/// 2) Otherwise, pick the most general constraint present. This prefers
3134/// 'm' over 'r', for example.
3135///
3136static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3137 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3138 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3139 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3140 unsigned BestIdx = 0;
3141 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3142 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3143
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3144 // Loop over the options, keeping track of the most general one.
3145 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3146 TargetLowering::ConstraintType CType =
3147 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3148
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3149 // If this is an 'other' constraint, see if the operand is valid for it.
3150 // For example, on X86 we might have an 'rI' constraint. If the operand
3151 // is an integer in the range [0..31] we want to use I (saving a load
3152 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3153 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3154 assert(OpInfo.Codes[i].size() == 1 &&
3155 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3156 std::vector<SDValue> ResultOps;
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]3157 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3158 ResultOps, *DAG);
3159 if (!ResultOps.empty()) {
3160 BestType = CType;
3161 BestIdx = i;
3162 break;
3163 }
3164 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3165
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3166 // Things with matching constraints can only be registers, per gcc
3167 // documentation. This mainly affects "g" constraints.
3168 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3169 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3170
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3171 // This constraint letter is more general than the previous one, use it.
3172 int Generality = getConstraintGenerality(CType);
3173 if (Generality > BestGenerality) {
3174 BestType = CType;
3175 BestIdx = i;
3176 BestGenerality = Generality;
3177 }
3178 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3179
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3180 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3181 OpInfo.ConstraintType = BestType;
3182}
3183
3184/// ComputeConstraintToUse - Determines the constraint code and constraint
3185/// type to use for the specific AsmOperandInfo, setting
3186/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3187void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3188 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3189 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3190 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3191
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3192 // Single-letter constraints ('r') are very common.
3193 if (OpInfo.Codes.size() == 1) {
3194 OpInfo.ConstraintCode = OpInfo.Codes[0];
3195 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3196 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3197 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3198 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3199
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3200 // 'X' matches anything.
3201 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3202 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3203 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]3204 // the result, which is not what we want to look at; leave them alone.
3205 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3206 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3207 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3208 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3209 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3210
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3211 // Otherwise, try to resolve it to something we know about by looking at
3212 // the actual operand type.
3213 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3214 OpInfo.ConstraintCode = Repl;
3215 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3216 }
3217 }
3218}
3219
3220//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3221// Loop Strength Reduction hooks
3222//===----------------------------------------------------------------------===//
3223
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3224/// isLegalAddressingMode - Return true if the addressing mode represented
3225/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3226bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3227 Type *Ty) const {
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3228 // The default implementation of this implements a conservative RISCy, r+r and
3229 // r+i addr mode.
3230
3231 // Allows a sign-extended 16-bit immediate field.
3232 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3233 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3234
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3235 // No global is ever allowed as a base.
3236 if (AM.BaseGV)
3237 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3238
3239 // Only support r+r,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3240 switch (AM.Scale) {
3241 case 0: // "r+i" or just "i", depending on HasBaseReg.
3242 break;
3243 case 1:
3244 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3245 return false;
3246 // Otherwise we have r+r or r+i.
3247 break;
3248 case 2:
3249 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3250 return false;
3251 // Allow 2*r as r+r.
3252 break;
3253 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3254
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3255 return true;
3256}
3257
Benjamin Kramer9c640302011-07-08 10:31:30 +0000[diff] [blame]3258/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3259/// with the multiplicative inverse of the constant.
3260SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3261 SelectionDAG &DAG) const {
3262 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3263 APInt d = C->getAPIntValue();
3264 assert(d != 0 && "Division by zero!");
3265
3266 // Shift the value upfront if it is even, so the LSB is one.
3267 unsigned ShAmt = d.countTrailingZeros();
3268 if (ShAmt) {
3269 // TODO: For UDIV use SRL instead of SRA.
3270 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3271 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3272 d = d.ashr(ShAmt);
3273 }
3274
3275 // Calculate the multiplicative inverse, using Newton's method.
3276 APInt t, xn = d;
3277 while ((t = d*xn) != 1)
3278 xn *= APInt(d.getBitWidth(), 2) - t;
3279
3280 Op2 = DAG.getConstant(xn, Op1.getValueType());
3281 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3282}
3283
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3284/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3285/// return a DAG expression to select that will generate the same value by
3286/// multiplying by a magic number. See:
3287/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3288SDValue TargetLowering::
3289BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3290 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3291 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3292 DebugLoc dl= N->getDebugLoc();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3293
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3294 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3295 // FIXME: We should be more aggressive here.
3296 if (!isTypeLegal(VT))
3297 return SDValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3298
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3299 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]3300 APInt::ms magics = d.magic();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3301
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3302 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3303 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3304 SDValue Q;
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3305 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3306 isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3307 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3308 DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3309 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3310 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3311 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3312 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3313 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3314 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3315 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3316 // If d > 0 and m < 0, add the numerator
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3317 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3318 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3319 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3320 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3321 }
3322 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3323 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3324 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3325 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3326 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3327 }
3328 // Shift right algebraic if shift value is nonzero
3329 if (magics.s > 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3330 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3331 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3332 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3333 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3334 }
3335 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3336 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3337 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3338 getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3339 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3340 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3341 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3342}
3343
3344/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3345/// return a DAG expression to select that will generate the same value by
3346/// multiplying by a magic number. See:
3347/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3348SDValue TargetLowering::
3349BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3350 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3351 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3352 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3353
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3354 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3355 // FIXME: We should be more aggressive here.
3356 if (!isTypeLegal(VT))
3357 return SDValue();
3358
3359 // FIXME: We should use a narrower constant when the upper
3360 // bits are known to be zero.
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3361 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3362 APInt::mu magics = N1C.magicu();
3363
3364 SDValue Q = N->getOperand(0);
3365
3366 // If the divisor is even, we can avoid using the expensive fixup by shifting
3367 // the divided value upfront.
3368 if (magics.a != 0 && !N1C[0]) {
3369 unsigned Shift = N1C.countTrailingZeros();
3370 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3371 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3372 if (Created)
3373 Created->push_back(Q.getNode());
3374
3375 // Get magic number for the shifted divisor.
3376 magics = N1C.lshr(Shift).magicu(Shift);
3377 assert(magics.a == 0 && "Should use cheap fixup now");
3378 }
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3379
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3380 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3381 // FIXME: We should support doing a MUL in a wider type
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3382 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3383 isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3384 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3385 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3386 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3387 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3388 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3389 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3390 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3391 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3392 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3393
3394 if (magics.a == 0) {
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3395 assert(magics.s < N1C.getBitWidth() &&
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3396 "We shouldn't generate an undefined shift!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3397 return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3398 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3399 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3400 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3401 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3402 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3403 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3404 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3405 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3406 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3407 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3408 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3409 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3410 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3411 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3412 }
3413}