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Misha Brukman2a8350a2005-02-05 02:24:26 +00001//===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
Andrew Lenharth304d0f32005-01-22 23:41:55 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Andrew Lenharth304d0f32005-01-22 23:41:55 +00007//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//3.3:
14//Memory
15//Branch
16//Operate
17//Floating-point
18//PALcode
19
Andrew Lenharth4907d222005-10-20 00:28:31 +000020def u8imm : Operand<i64>;
21def s14imm : Operand<i64>;
22def s16imm : Operand<i64>;
23def s21imm : Operand<i64>;
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000024def s64imm : Operand<i64>;
Andrew Lenharthf81173f2006-10-31 16:49:55 +000025def u64imm : Operand<i64>;
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000026
Andrew Lenharth304d0f32005-01-22 23:41:55 +000027//===----------------------------------------------------------------------===//
28// Instruction format superclass
29//===----------------------------------------------------------------------===//
Andrew Lenharth5cefc5e2005-11-09 19:17:08 +000030// Alpha instruction baseline
Andrew Lenharth017c5562006-03-09 17:16:45 +000031class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
Andrew Lenharth304d0f32005-01-22 23:41:55 +000032 field bits<32> Inst;
Andrew Lenharth304d0f32005-01-22 23:41:55 +000033 let Namespace = "Alpha";
Andrew Lenharth304d0f32005-01-22 23:41:55 +000034 let AsmString = asmstr;
Andrew Lenharth304d0f32005-01-22 23:41:55 +000035 let Inst{31-26} = op;
Andrew Lenharth017c5562006-03-09 17:16:45 +000036 let Itinerary = itin;
Andrew Lenharth304d0f32005-01-22 23:41:55 +000037}
38
Andrew Lenharth5cefc5e2005-11-09 19:17:08 +000039
Andrew Lenharth304d0f32005-01-22 23:41:55 +000040//3.3.1
Chris Lattnerc8478d82008-01-06 06:44:58 +000041class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
Andrew Lenharth017c5562006-03-09 17:16:45 +000042 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth9fa4d4c2005-12-24 03:41:56 +000043 let Pattern = pattern;
Andrew Lenharthb6718602005-12-24 07:34:33 +000044 let isLoad = load;
Andrew Lenharthcd1544e2006-01-26 03:22:07 +000045 let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
Andrew Lenharth9fa4d4c2005-12-24 03:41:56 +000046
47 bits<5> Ra;
48 bits<16> disp;
49 bits<5> Rb;
50
51 let Inst{25-21} = Ra;
52 let Inst{20-16} = Rb;
53 let Inst{15-0} = disp;
54}
Andrew Lenharth017c5562006-03-09 17:16:45 +000055class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin>
56 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth51b8d542005-11-11 16:47:30 +000057 bits<5> Ra;
Andrew Lenharth51b8d542005-11-11 16:47:30 +000058
Evan Cheng64d80e32007-07-19 01:14:50 +000059 let OutOperandList = (ops GPRC:$RA);
60 let InOperandList = (ops);
Andrew Lenharth51b8d542005-11-11 16:47:30 +000061 let Inst{25-21} = Ra;
Andrew Lenharth739027e2006-01-16 21:22:38 +000062 let Inst{20-16} = 0;
Andrew Lenharth51b8d542005-11-11 16:47:30 +000063 let Inst{15-0} = fc;
64}
Andrew Lenharth304d0f32005-01-22 23:41:55 +000065
Andrew Lenharth017c5562006-03-09 17:16:45 +000066class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
67 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000068 bits<5> Ra;
69 bits<5> Rb;
70 bits<14> disp;
71
Evan Cheng64d80e32007-07-19 01:14:50 +000072 let OutOperandList = (ops);
73 let InOperandList = OL;
Andrew Lenharth017c5562006-03-09 17:16:45 +000074
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000075 let Inst{25-21} = Ra;
76 let Inst{20-16} = Rb;
77 let Inst{15-14} = TB;
78 let Inst{13-0} = disp;
79}
Andrew Lenharthf2b806a2006-06-12 18:09:24 +000080class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin>
81 : InstAlpha<opcode, asmstr, itin> {
82 let Pattern=pattern;
83 bits<5> Ra;
84 bits<5> Rb;
85 bits<14> disp;
86
Evan Cheng64d80e32007-07-19 01:14:50 +000087 let OutOperandList = (ops);
88 let InOperandList = OL;
Andrew Lenharthf2b806a2006-06-12 18:09:24 +000089
90 let Inst{25-21} = Ra;
91 let Inst{20-16} = Rb;
92 let Inst{15-14} = TB;
93 let Inst{13-0} = disp;
94}
Andrew Lenharthf3f951a2005-07-22 20:50:29 +000095
Andrew Lenharth304d0f32005-01-22 23:41:55 +000096//3.3.2
Andrew Lenhartheececba2005-12-25 17:36:48 +000097def target : Operand<OtherVT> {}
Andrew Lenharthf81173f2006-10-31 16:49:55 +000098
Evan Chengffbacca2007-07-21 00:34:19 +000099let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
Andrew Lenharthf81173f2006-10-31 16:49:55 +0000100class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
101 : InstAlpha<opcode, asmstr, itin> {
Evan Cheng64d80e32007-07-19 01:14:50 +0000102 let OutOperandList = (ops);
103 let InOperandList = OL;
Andrew Lenharthf81173f2006-10-31 16:49:55 +0000104 bits<64> Opc; //dummy
105 bits<5> Ra;
106 bits<21> disp;
107
108 let Inst{25-21} = Ra;
109 let Inst{20-0} = disp;
110}
111}
112
Andrew Lenharthcfb28152005-12-06 20:40:34 +0000113let isBranch = 1, isTerminator = 1 in
Andrew Lenharth017c5562006-03-09 17:16:45 +0000114class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin>
115 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenhartheececba2005-12-25 17:36:48 +0000116 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000117 let OutOperandList = (ops);
118 let InOperandList = (ops target:$DISP);
Andrew Lenhartheececba2005-12-25 17:36:48 +0000119 bits<5> Ra;
Andrew Lenharth756fbeb2005-10-22 22:06:58 +0000120 bits<21> disp;
121
122 let Inst{25-21} = Ra;
123 let Inst{20-0} = disp;
124}
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000125
126//3.3.3
Andrew Lenharth017c5562006-03-09 17:16:45 +0000127class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
128 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth4907d222005-10-20 00:28:31 +0000129 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000130 let OutOperandList = (outs GPRC:$RC);
131 let InOperandList = (ins GPRC:$RA, GPRC:$RB);
Andrew Lenharth4907d222005-10-20 00:28:31 +0000132
Andrew Lenharthf3f951a2005-07-22 20:50:29 +0000133 bits<5> Rc;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000134 bits<5> Ra;
135 bits<5> Rb;
Andrew Lenharthf3f951a2005-07-22 20:50:29 +0000136 bits<7> Function = fun;
137
138 let Inst{25-21} = Ra;
139 let Inst{20-16} = Rb;
140 let Inst{15-13} = 0;
141 let Inst{12} = 0;
142 let Inst{11-5} = Function;
143 let Inst{4-0} = Rc;
144}
145
Andrew Lenharth017c5562006-03-09 17:16:45 +0000146class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
147 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth964b6aa2005-10-20 19:39:24 +0000148 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000149 let OutOperandList = (outs GPRC:$RC);
150 let InOperandList = (ins GPRC:$RB);
Andrew Lenharth964b6aa2005-10-20 19:39:24 +0000151
152 bits<5> Rc;
153 bits<5> Rb;
154 bits<7> Function = fun;
155
Andrew Lenharth756fbeb2005-10-22 22:06:58 +0000156 let Inst{25-21} = 31;
Andrew Lenharth964b6aa2005-10-20 19:39:24 +0000157 let Inst{20-16} = Rb;
158 let Inst{15-13} = 0;
159 let Inst{12} = 0;
160 let Inst{11-5} = Function;
161 let Inst{4-0} = Rc;
162}
163
Andrew Lenharth017c5562006-03-09 17:16:45 +0000164class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
165 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000166 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000167 let OutOperandList = (outs GPRC:$RDEST);
168 let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
Andrew Lenharth15b78232007-04-17 04:07:59 +0000169 let Constraints = "$RFALSE = $RDEST";
170 let DisableEncoding = "$RFALSE";
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000171
172 bits<5> Rc;
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000173 bits<5> Ra;
Andrew Lenharth15b78232007-04-17 04:07:59 +0000174 bits<5> Rb;
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000175 bits<7> Function = fun;
176
Andrew Lenharth15b78232007-04-17 04:07:59 +0000177// let isTwoAddress = 1;
Andrew Lenharth5de36f92005-12-05 23:19:44 +0000178 let Inst{25-21} = Ra;
179 let Inst{20-16} = Rb;
180 let Inst{15-13} = 0;
181 let Inst{12} = 0;
182 let Inst{11-5} = Function;
183 let Inst{4-0} = Rc;
184}
185
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000186
Andrew Lenharth017c5562006-03-09 17:16:45 +0000187class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
188 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth4907d222005-10-20 00:28:31 +0000189 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000190 let OutOperandList = (outs GPRC:$RC);
191 let InOperandList = (ins GPRC:$RA, u8imm:$L);
Andrew Lenharth4907d222005-10-20 00:28:31 +0000192
Andrew Lenharthf3f951a2005-07-22 20:50:29 +0000193 bits<5> Rc;
194 bits<5> Ra;
195 bits<8> LIT;
196 bits<7> Function = fun;
197
198 let Inst{25-21} = Ra;
199 let Inst{20-13} = LIT;
200 let Inst{12} = 1;
201 let Inst{11-5} = Function;
202 let Inst{4-0} = Rc;
203}
204
Andrew Lenharth017c5562006-03-09 17:16:45 +0000205class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
206 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth77f08852006-02-01 19:37:33 +0000207 let Pattern = pattern;
Evan Cheng64d80e32007-07-19 01:14:50 +0000208 let OutOperandList = (outs GPRC:$RDEST);
209 let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
Andrew Lenharth15b78232007-04-17 04:07:59 +0000210 let Constraints = "$RFALSE = $RDEST";
211 let DisableEncoding = "$RFALSE";
212
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000213 bits<5> Rc;
Andrew Lenharth1f347a32005-10-20 23:58:36 +0000214 bits<5> Ra;
Andrew Lenharth15b78232007-04-17 04:07:59 +0000215 bits<8> LIT;
Andrew Lenharth1f347a32005-10-20 23:58:36 +0000216 bits<7> Function = fun;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000217
Andrew Lenharth15b78232007-04-17 04:07:59 +0000218// let isTwoAddress = 1;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000219 let Inst{25-21} = Ra;
220 let Inst{20-13} = LIT;
221 let Inst{12} = 1;
222 let Inst{11-5} = Function;
223 let Inst{4-0} = Rc;
224}
225
226//3.3.4
Andrew Lenharth017c5562006-03-09 17:16:45 +0000227class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
228 : InstAlpha<opcode, asmstr, itin> {
Andrew Lenharth5cefc5e2005-11-09 19:17:08 +0000229 let Pattern = pattern;
230
Andrew Lenharth98169be2005-07-28 18:14:47 +0000231 bits<5> Fc;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000232 bits<5> Fa;
233 bits<5> Fb;
Andrew Lenharth3e98fde2005-01-26 21:54:09 +0000234 bits<11> Function = fun;
Andrew Lenharth98169be2005-07-28 18:14:47 +0000235
236 let Inst{25-21} = Fa;
237 let Inst{20-16} = Fb;
238 let Inst{15-5} = Function;
239 let Inst{4-0} = Fc;
240}
241
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000242//3.3.5
Andrew Lenharth017c5562006-03-09 17:16:45 +0000243class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
244 : InstAlpha<opcode, asmstr, itin> {
Evan Cheng64d80e32007-07-19 01:14:50 +0000245 let OutOperandList = (ops);
246 let InOperandList = OL;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000247 bits<26> Function;
248
249 let Inst{25-0} = Function;
250}
251
252
253// Pseudo instructions.
Evan Cheng64d80e32007-07-19 01:14:50 +0000254class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin>
Andrew Lenharth017c5562006-03-09 17:16:45 +0000255 : InstAlpha<0, nm, itin> {
Evan Cheng64d80e32007-07-19 01:14:50 +0000256 let OutOperandList = OOL;
257 let InOperandList = IOL;
Andrew Lenharth50b37842005-11-22 04:20:06 +0000258 let Pattern = pattern;
259
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000260}