Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2020 Collabora Ltd. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors (Collabora): |
| 24 | * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> |
| 25 | */ |
| 26 | |
| 27 | #ifndef __BIFROST_COMPILER_H |
| 28 | #define __BIFROST_COMPILER_H |
| 29 | |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 30 | #include "bifrost.h" |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 31 | #include "compiler/nir/nir.h" |
| 32 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 33 | /* Bifrost opcodes are tricky -- the same op may exist on both FMA and |
| 34 | * ADD with two completely different opcodes, and opcodes can be varying |
| 35 | * length in some cases. Then we have different opcodes for int vs float |
| 36 | * and then sometimes even for different typesizes. Further, virtually |
| 37 | * every op has a number of flags which depend on the op. In constrast |
| 38 | * to Midgard where you have a strict ALU/LDST/TEX division and within |
| 39 | * ALU you have strict int/float and that's it... here it's a *lot* more |
| 40 | * involved. As such, we use something much higher level for our IR, |
| 41 | * encoding "classes" of operations, letting the opcode details get |
| 42 | * sorted out at emit time. |
| 43 | * |
| 44 | * Please keep this list alphabetized. Please use a dictionary if you |
| 45 | * don't know how to do that. |
| 46 | */ |
| 47 | |
| 48 | enum bi_class { |
| 49 | BI_ADD, |
| 50 | BI_ATEST, |
| 51 | BI_BRANCH, |
| 52 | BI_CMP, |
| 53 | BI_BLEND, |
| 54 | BI_BITWISE, |
| 55 | BI_CONVERT, |
| 56 | BI_CSEL, |
| 57 | BI_DISCARD, |
| 58 | BI_FMA, |
| 59 | BI_FREXP, |
| 60 | BI_LOAD, |
| 61 | BI_LOAD_ATTR, |
| 62 | BI_LOAD_VAR, |
| 63 | BI_LOAD_VAR_ADDRESS, |
| 64 | BI_MINMAX, |
| 65 | BI_MOV, |
| 66 | BI_SHIFT, |
| 67 | BI_STORE, |
| 68 | BI_STORE_VAR, |
| 69 | BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */ |
| 70 | BI_TEX, |
| 71 | BI_ROUND, |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 72 | BI_NUM_CLASSES |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 73 | }; |
| 74 | |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 75 | /* Properties of a class... */ |
| 76 | extern unsigned bi_class_props[BI_NUM_CLASSES]; |
| 77 | |
| 78 | /* abs/neg/outmod valid for a float op */ |
| 79 | #define BI_MODS (1 << 0) |
| 80 | |
Alyssa Rosenzweig | 34165c7 | 2020-03-02 20:46:37 -0500 | [diff] [blame] | 81 | /* Generic enough that little class-specific information is required. In other |
| 82 | * words, it acts as a "normal" ALU op, even if the encoding ends up being |
| 83 | * irregular enough to warrant a separate class */ |
| 84 | #define BI_GENERIC (1 << 1) |
| 85 | |
Alyssa Rosenzweig | d69bf8d | 2020-03-02 20:52:36 -0500 | [diff] [blame] | 86 | /* Accepts a bifrost_roundmode */ |
| 87 | #define BI_ROUNDMODE (1 << 2) |
| 88 | |
Alyssa Rosenzweig | 99f3c1f | 2020-03-02 21:53:13 -0500 | [diff] [blame] | 89 | /* Can be scheduled to FMA */ |
| 90 | #define BI_SCHED_FMA (1 << 3) |
| 91 | |
| 92 | /* Can be scheduled to ADD */ |
| 93 | #define BI_SCHED_ADD (1 << 4) |
| 94 | |
| 95 | /* Most ALU ops can do either, actually */ |
| 96 | #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD) |
| 97 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 98 | /* It can't get any worse than csel4... can it? */ |
| 99 | #define BIR_SRC_COUNT 4 |
| 100 | |
Alyssa Rosenzweig | aa2f12d | 2020-03-02 21:19:16 -0500 | [diff] [blame] | 101 | /* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */ |
| 102 | struct bi_load { |
| 103 | /* Note: no indirects here */ |
| 104 | unsigned location; |
| 105 | |
| 106 | /* Only for BI_LD_ATTR. But number of vector channels */ |
| 107 | unsigned channels; |
| 108 | }; |
| 109 | |
Alyssa Rosenzweig | 9643b9d | 2020-03-02 21:48:51 -0500 | [diff] [blame] | 110 | /* BI_LD_VARY */ |
| 111 | struct bi_load_vary { |
| 112 | /* All parameters used here. Indirect location specified in |
| 113 | * src1 and ignoring location, if present. */ |
| 114 | struct bi_load load; |
| 115 | |
| 116 | enum bifrost_interp_mode interp_mode; |
| 117 | bool reuse; |
| 118 | bool flat; |
| 119 | }; |
| 120 | |
Alyssa Rosenzweig | 44ebc27 | 2020-03-03 07:58:05 -0500 | [diff] [blame^] | 121 | /* Opcodes within a class */ |
| 122 | enum bi_minmax_op { |
| 123 | BI_MINMAX_MIN, |
| 124 | BI_MINMAX_MAX |
| 125 | }; |
| 126 | |
| 127 | enum bi_bitwise_op { |
| 128 | BI_BITWISE_AND, |
| 129 | BI_BITWISE_OR, |
| 130 | BI_BITWISE_XOR |
| 131 | }; |
| 132 | |
| 133 | enum bi_round_op { |
| 134 | BI_ROUND_MODE, /* use round mode */ |
| 135 | BI_ROUND_ROUND /* i.e.: fround() */ |
| 136 | }; |
| 137 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 138 | typedef struct { |
| 139 | struct list_head link; /* Must be first */ |
| 140 | enum bi_class type; |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 141 | |
| 142 | /* Indices, see bir_ssa_index etc. Note zero is special cased |
| 143 | * to "no argument" */ |
| 144 | unsigned dest; |
| 145 | unsigned src[BIR_SRC_COUNT]; |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 146 | |
Alyssa Rosenzweig | b5bdd89 | 2020-03-03 07:47:29 -0500 | [diff] [blame] | 147 | /* If one of the sources has BIR_INDEX_CONSTANT... */ |
| 148 | union { |
| 149 | uint64_t u64; |
| 150 | uint32_t u32; |
| 151 | uint16_t u16[2]; |
| 152 | uint8_t u8[4]; |
| 153 | } constant; |
| 154 | |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 155 | /* Floating-point modifiers, type/class permitting. If not |
| 156 | * allowed for the type/class, these are ignored. */ |
| 157 | enum bifrost_outmod outmod; |
| 158 | bool src_abs[BIR_SRC_COUNT]; |
| 159 | bool src_neg[BIR_SRC_COUNT]; |
Alyssa Rosenzweig | d69bf8d | 2020-03-02 20:52:36 -0500 | [diff] [blame] | 160 | |
| 161 | /* Round mode (requires BI_ROUNDMODE) */ |
| 162 | enum bifrost_roundmode roundmode; |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 163 | |
Alyssa Rosenzweig | c42002d | 2020-03-02 22:03:05 -0500 | [diff] [blame] | 164 | /* Destination type. Usually the type of the instruction |
| 165 | * itself, but if sources and destination have different |
| 166 | * types, the type of the destination wins (so f2i would be |
| 167 | * int). Zero if there is no destination. Bitsize included */ |
| 168 | nir_alu_type dest_type; |
| 169 | |
Alyssa Rosenzweig | 44ebc27 | 2020-03-03 07:58:05 -0500 | [diff] [blame^] | 170 | /* A class-specific op from which the actual opcode can be derived |
| 171 | * (along with the above information) */ |
| 172 | |
| 173 | union { |
| 174 | enum bi_minmax_op minmax; |
| 175 | enum bi_bitwise_op bitwise; |
| 176 | enum bi_round_op round; |
| 177 | } op; |
| 178 | |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 179 | /* Union for class-specific information */ |
| 180 | union { |
| 181 | enum bifrost_minmax_mode minmax; |
Alyssa Rosenzweig | aa2f12d | 2020-03-02 21:19:16 -0500 | [diff] [blame] | 182 | struct bi_load load; |
Alyssa Rosenzweig | 9643b9d | 2020-03-02 21:48:51 -0500 | [diff] [blame] | 183 | struct bi_load_vary load_vary; |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 184 | }; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 185 | } bi_instruction; |
| 186 | |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 187 | /* Scheduling takes place in two steps. Step 1 groups instructions within a |
| 188 | * block into distinct clauses (bi_clause). Step 2 schedules instructions |
| 189 | * within a clause into FMA/ADD pairs (bi_bundle). |
| 190 | * |
| 191 | * A bi_bundle contains two paired instruction pointers. If a slot is unfilled, |
| 192 | * leave it NULL; the emitter will fill in a nop. |
| 193 | */ |
| 194 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 195 | typedef struct { |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 196 | bi_instruction *fma; |
| 197 | bi_instruction *add; |
| 198 | } bi_bundle; |
| 199 | |
| 200 | typedef struct { |
| 201 | struct list_head link; |
| 202 | |
| 203 | /* A clause can have 8 instructions in bundled FMA/ADD sense, so there |
| 204 | * can be 8 bundles. But each bundle can have both an FMA and an ADD, |
| 205 | * so a clause can have up to 16 bi_instructions. Whether bundles or |
| 206 | * instructions are used depends on where in scheduling we are. */ |
| 207 | |
| 208 | unsigned instruction_count; |
| 209 | unsigned bundle_count; |
| 210 | |
| 211 | union { |
| 212 | bi_instruction *instructions[16]; |
| 213 | bi_bundle bundles[8]; |
| 214 | }; |
| 215 | } bi_clause; |
| 216 | |
| 217 | typedef struct bi_block { |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 218 | struct list_head link; /* must be first */ |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 219 | unsigned name; /* Just for pretty-printing */ |
| 220 | |
| 221 | /* If true, uses clauses; if false, uses instructions */ |
| 222 | bool scheduled; |
| 223 | |
| 224 | union { |
| 225 | struct list_head instructions; /* pre-schedule, list of bi_instructions */ |
| 226 | struct list_head clauses; /* list of bi_clause */ |
| 227 | }; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 228 | } bi_block; |
| 229 | |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 230 | typedef struct { |
| 231 | nir_shader *nir; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 232 | struct list_head blocks; /* list of bi_block */ |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 233 | } bi_context; |
| 234 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 235 | /* So we can distinguish between SSA/reg/sentinel quickly */ |
| 236 | #define BIR_NO_ARG (0) |
| 237 | #define BIR_IS_REG (1) |
| 238 | |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 239 | /* If high bits are set, instead of SSA/registers, we have specials indexed by |
| 240 | * the low bits if necessary. |
| 241 | * |
| 242 | * Fixed register: do not allocate register, do not collect $200. |
| 243 | * Uniform: access a uniform register given by low bits. |
| 244 | * Constant: access the specified constant |
| 245 | * Zero: special cased to avoid wasting a constant |
| 246 | */ |
| 247 | |
| 248 | #define BIR_INDEX_REGISTER (1 << 31) |
| 249 | #define BIR_INDEX_UNIFORM (1 << 30) |
| 250 | #define BIR_INDEX_CONSTANT (1 << 29) |
| 251 | #define BIR_INDEX_ZERO (1 << 28) |
| 252 | |
| 253 | /* Keep me synced please so we can check src & BIR_SPECIAL */ |
| 254 | |
| 255 | #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \ |
| 256 | (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO) |
| 257 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 258 | static inline unsigned |
| 259 | bir_ssa_index(nir_ssa_def *ssa) |
| 260 | { |
| 261 | /* Off-by-one ensures BIR_NO_ARG is skipped */ |
| 262 | return ((ssa->index + 1) << 1) | 0; |
| 263 | } |
| 264 | |
| 265 | static inline unsigned |
| 266 | bir_src_index(nir_src *src) |
| 267 | { |
| 268 | if (src->is_ssa) |
| 269 | return bir_ssa_index(src->ssa); |
| 270 | else { |
| 271 | assert(!src->reg.indirect); |
| 272 | return (src->reg.reg->index << 1) | BIR_IS_REG; |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | static inline unsigned |
| 277 | bir_dest_index(nir_dest *dst) |
| 278 | { |
| 279 | if (dst->is_ssa) |
| 280 | return bir_ssa_index(&dst->ssa); |
| 281 | else { |
| 282 | assert(!dst->reg.indirect); |
| 283 | return (dst->reg.reg->index << 1) | BIR_IS_REG; |
| 284 | } |
| 285 | } |
| 286 | |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 287 | #endif |