Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2016 Red Hat. |
| 3 | * Copyright © 2016 Bas Nieuwenhuizen |
| 4 | * |
| 5 | * based in part on anv driver which is: |
| 6 | * Copyright © 2015 Intel Corporation |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the "Software"), |
| 10 | * to deal in the Software without restriction, including without limitation |
| 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 12 | * and/or sell copies of the Software, and to permit persons to whom the |
| 13 | * Software is furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the next |
| 16 | * paragraph) shall be included in all copies or substantial portions of the |
| 17 | * Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 24 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 25 | * IN THE SOFTWARE. |
| 26 | */ |
| 27 | |
| 28 | #include "util/mesa-sha1.h" |
| 29 | #include "radv_private.h" |
| 30 | #include "nir/nir.h" |
| 31 | #include "nir/nir_builder.h" |
| 32 | #include "spirv/nir_spirv.h" |
| 33 | |
| 34 | #include <llvm-c/Core.h> |
| 35 | #include <llvm-c/TargetMachine.h> |
| 36 | |
| 37 | #include "sid.h" |
| 38 | #include "r600d_common.h" |
| 39 | #include "ac_binary.h" |
| 40 | #include "ac_llvm_util.h" |
| 41 | #include "ac_nir_to_llvm.h" |
| 42 | #include "vk_format.h" |
| 43 | #include "util/debug.h" |
Timothy Arceri | 304b35b | 2017-03-14 15:50:34 +1100 | [diff] [blame] | 44 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 45 | void radv_shader_variant_destroy(struct radv_device *device, |
| 46 | struct radv_shader_variant *variant); |
| 47 | |
| 48 | static const struct nir_shader_compiler_options nir_options = { |
| 49 | .vertex_id_zero_based = true, |
| 50 | .lower_scmp = true, |
| 51 | .lower_flrp32 = true, |
| 52 | .lower_fsat = true, |
| 53 | .lower_pack_snorm_2x16 = true, |
| 54 | .lower_pack_snorm_4x8 = true, |
| 55 | .lower_pack_unorm_2x16 = true, |
| 56 | .lower_pack_unorm_4x8 = true, |
| 57 | .lower_unpack_snorm_2x16 = true, |
| 58 | .lower_unpack_snorm_4x8 = true, |
| 59 | .lower_unpack_unorm_2x16 = true, |
| 60 | .lower_unpack_unorm_4x8 = true, |
| 61 | .lower_extract_byte = true, |
| 62 | .lower_extract_word = true, |
| 63 | }; |
| 64 | |
| 65 | VkResult radv_CreateShaderModule( |
| 66 | VkDevice _device, |
| 67 | const VkShaderModuleCreateInfo* pCreateInfo, |
| 68 | const VkAllocationCallbacks* pAllocator, |
| 69 | VkShaderModule* pShaderModule) |
| 70 | { |
| 71 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 72 | struct radv_shader_module *module; |
| 73 | |
| 74 | assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO); |
| 75 | assert(pCreateInfo->flags == 0); |
| 76 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame] | 77 | module = vk_alloc2(&device->alloc, pAllocator, |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 78 | sizeof(*module) + pCreateInfo->codeSize, 8, |
| 79 | VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); |
| 80 | if (module == NULL) |
| 81 | return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); |
| 82 | |
| 83 | module->nir = NULL; |
| 84 | module->size = pCreateInfo->codeSize; |
| 85 | memcpy(module->data, pCreateInfo->pCode, module->size); |
| 86 | |
| 87 | _mesa_sha1_compute(module->data, module->size, module->sha1); |
| 88 | |
| 89 | *pShaderModule = radv_shader_module_to_handle(module); |
| 90 | |
| 91 | return VK_SUCCESS; |
| 92 | } |
| 93 | |
| 94 | void radv_DestroyShaderModule( |
| 95 | VkDevice _device, |
| 96 | VkShaderModule _module, |
| 97 | const VkAllocationCallbacks* pAllocator) |
| 98 | { |
| 99 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 100 | RADV_FROM_HANDLE(radv_shader_module, module, _module); |
| 101 | |
| 102 | if (!module) |
| 103 | return; |
| 104 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame] | 105 | vk_free2(&device->alloc, pAllocator, module); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 106 | } |
| 107 | |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 108 | |
| 109 | static void |
| 110 | radv_pipeline_destroy(struct radv_device *device, |
| 111 | struct radv_pipeline *pipeline, |
| 112 | const VkAllocationCallbacks* allocator) |
| 113 | { |
| 114 | for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) |
| 115 | if (pipeline->shaders[i]) |
| 116 | radv_shader_variant_destroy(device, pipeline->shaders[i]); |
| 117 | |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 118 | if (pipeline->gs_copy_shader) |
| 119 | radv_shader_variant_destroy(device, pipeline->gs_copy_shader); |
| 120 | |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 121 | vk_free2(&device->alloc, allocator, pipeline); |
| 122 | } |
| 123 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 124 | void radv_DestroyPipeline( |
| 125 | VkDevice _device, |
| 126 | VkPipeline _pipeline, |
| 127 | const VkAllocationCallbacks* pAllocator) |
| 128 | { |
| 129 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 130 | RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline); |
| 131 | |
| 132 | if (!_pipeline) |
| 133 | return; |
| 134 | |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 135 | radv_pipeline_destroy(device, pipeline, pAllocator); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | |
| 139 | static void |
| 140 | radv_optimize_nir(struct nir_shader *shader) |
| 141 | { |
| 142 | bool progress; |
| 143 | |
| 144 | do { |
| 145 | progress = false; |
| 146 | |
| 147 | NIR_PASS_V(shader, nir_lower_vars_to_ssa); |
| 148 | NIR_PASS_V(shader, nir_lower_alu_to_scalar); |
| 149 | NIR_PASS_V(shader, nir_lower_phis_to_scalar); |
| 150 | |
| 151 | NIR_PASS(progress, shader, nir_copy_prop); |
| 152 | NIR_PASS(progress, shader, nir_opt_remove_phis); |
| 153 | NIR_PASS(progress, shader, nir_opt_dce); |
| 154 | NIR_PASS(progress, shader, nir_opt_dead_cf); |
| 155 | NIR_PASS(progress, shader, nir_opt_cse); |
| 156 | NIR_PASS(progress, shader, nir_opt_peephole_select, 8); |
| 157 | NIR_PASS(progress, shader, nir_opt_algebraic); |
| 158 | NIR_PASS(progress, shader, nir_opt_constant_folding); |
| 159 | NIR_PASS(progress, shader, nir_opt_undef); |
Dave Airlie | 3c9af75 | 2016-11-02 01:23:11 +0000 | [diff] [blame] | 160 | NIR_PASS(progress, shader, nir_opt_conditional_discard); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 161 | } while (progress); |
| 162 | } |
| 163 | |
| 164 | static nir_shader * |
| 165 | radv_shader_compile_to_nir(struct radv_device *device, |
| 166 | struct radv_shader_module *module, |
| 167 | const char *entrypoint_name, |
| 168 | gl_shader_stage stage, |
| 169 | const VkSpecializationInfo *spec_info, |
| 170 | bool dump) |
| 171 | { |
| 172 | if (strcmp(entrypoint_name, "main") != 0) { |
| 173 | radv_finishme("Multiple shaders per module not really supported"); |
| 174 | } |
| 175 | |
| 176 | nir_shader *nir; |
| 177 | nir_function *entry_point; |
| 178 | if (module->nir) { |
| 179 | /* Some things such as our meta clear/blit code will give us a NIR |
| 180 | * shader directly. In that case, we just ignore the SPIR-V entirely |
| 181 | * and just use the NIR shader */ |
| 182 | nir = module->nir; |
| 183 | nir->options = &nir_options; |
| 184 | nir_validate_shader(nir); |
| 185 | |
| 186 | assert(exec_list_length(&nir->functions) == 1); |
| 187 | struct exec_node *node = exec_list_get_head(&nir->functions); |
| 188 | entry_point = exec_node_data(nir_function, node, node); |
| 189 | } else { |
| 190 | uint32_t *spirv = (uint32_t *) module->data; |
| 191 | assert(module->size % 4 == 0); |
| 192 | |
| 193 | uint32_t num_spec_entries = 0; |
| 194 | struct nir_spirv_specialization *spec_entries = NULL; |
| 195 | if (spec_info && spec_info->mapEntryCount > 0) { |
| 196 | num_spec_entries = spec_info->mapEntryCount; |
| 197 | spec_entries = malloc(num_spec_entries * sizeof(*spec_entries)); |
| 198 | for (uint32_t i = 0; i < num_spec_entries; i++) { |
| 199 | VkSpecializationMapEntry entry = spec_info->pMapEntries[i]; |
| 200 | const void *data = spec_info->pData + entry.offset; |
| 201 | assert(data + entry.size <= spec_info->pData + spec_info->dataSize); |
| 202 | |
| 203 | spec_entries[i].id = spec_info->pMapEntries[i].constantID; |
Samuel Iglesias Gonsálvez | cc4ff6c | 2016-11-14 12:08:32 +0100 | [diff] [blame] | 204 | if (spec_info->dataSize == 8) |
| 205 | spec_entries[i].data64 = *(const uint64_t *)data; |
| 206 | else |
| 207 | spec_entries[i].data32 = *(const uint32_t *)data; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 208 | } |
| 209 | } |
Dave Airlie | 44f833a | 2016-12-27 23:28:05 +0000 | [diff] [blame] | 210 | const struct nir_spirv_supported_extensions supported_ext = { |
Bas Nieuwenhuizen | f5f8eb2 | 2017-01-31 21:37:48 +0100 | [diff] [blame] | 211 | .draw_parameters = true, |
Bas Nieuwenhuizen | 5387369 | 2017-02-15 00:55:19 +0100 | [diff] [blame] | 212 | .float64 = true, |
Bas Nieuwenhuizen | 4e6095f | 2017-02-15 01:00:07 +0100 | [diff] [blame] | 213 | .image_read_without_format = true, |
Bas Nieuwenhuizen | 5387369 | 2017-02-15 00:55:19 +0100 | [diff] [blame] | 214 | .image_write_without_format = true, |
Dave Airlie | 44f833a | 2016-12-27 23:28:05 +0000 | [diff] [blame] | 215 | }; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 216 | entry_point = spirv_to_nir(spirv, module->size / 4, |
| 217 | spec_entries, num_spec_entries, |
Dave Airlie | 44f833a | 2016-12-27 23:28:05 +0000 | [diff] [blame] | 218 | stage, entrypoint_name, &supported_ext, &nir_options); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 219 | nir = entry_point->shader; |
| 220 | assert(nir->stage == stage); |
| 221 | nir_validate_shader(nir); |
| 222 | |
| 223 | free(spec_entries); |
| 224 | |
Bas Nieuwenhuizen | 65cbb99 | 2017-01-08 23:17:38 +0100 | [diff] [blame] | 225 | /* We have to lower away local constant initializers right before we |
| 226 | * inline functions. That way they get properly initialized at the top |
| 227 | * of the function and not at the top of its caller. |
| 228 | */ |
Bas Nieuwenhuizen | 8aaca38 | 2017-01-08 23:23:52 +0100 | [diff] [blame] | 229 | NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local); |
| 230 | NIR_PASS_V(nir, nir_lower_returns); |
| 231 | NIR_PASS_V(nir, nir_inline_functions); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 232 | |
| 233 | /* Pick off the single entrypoint that we want */ |
| 234 | foreach_list_typed_safe(nir_function, func, node, &nir->functions) { |
| 235 | if (func != entry_point) |
| 236 | exec_node_remove(&func->node); |
| 237 | } |
| 238 | assert(exec_list_length(&nir->functions) == 1); |
| 239 | entry_point->name = ralloc_strdup(entry_point, "main"); |
| 240 | |
Bas Nieuwenhuizen | 8aaca38 | 2017-01-08 23:23:52 +0100 | [diff] [blame] | 241 | NIR_PASS_V(nir, nir_remove_dead_variables, |
| 242 | nir_var_shader_in | nir_var_shader_out | nir_var_system_value); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 243 | |
Bas Nieuwenhuizen | 65cbb99 | 2017-01-08 23:17:38 +0100 | [diff] [blame] | 244 | /* Now that we've deleted all but the main function, we can go ahead and |
| 245 | * lower the rest of the constant initializers. |
| 246 | */ |
Bas Nieuwenhuizen | 8aaca38 | 2017-01-08 23:23:52 +0100 | [diff] [blame] | 247 | NIR_PASS_V(nir, nir_lower_constant_initializers, ~0); |
| 248 | NIR_PASS_V(nir, nir_lower_system_values); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | /* Vulkan uses the separate-shader linking model */ |
Timothy Arceri | e1af20f | 2016-10-13 11:41:23 +1100 | [diff] [blame] | 252 | nir->info->separate_shader = true; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 253 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 254 | nir_shader_gather_info(nir, entry_point->impl); |
| 255 | |
| 256 | nir_variable_mode indirect_mask = 0; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 257 | indirect_mask |= nir_var_shader_in; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 258 | indirect_mask |= nir_var_local; |
| 259 | |
| 260 | nir_lower_indirect_derefs(nir, indirect_mask); |
| 261 | |
| 262 | static const nir_lower_tex_options tex_options = { |
| 263 | .lower_txp = ~0, |
| 264 | }; |
| 265 | |
| 266 | nir_lower_tex(nir, &tex_options); |
| 267 | |
| 268 | nir_lower_vars_to_ssa(nir); |
| 269 | nir_lower_var_copies(nir); |
| 270 | nir_lower_global_vars_to_local(nir); |
| 271 | nir_remove_dead_variables(nir, nir_var_local); |
| 272 | radv_optimize_nir(nir); |
| 273 | |
| 274 | if (dump) |
| 275 | nir_print_shader(nir, stderr); |
| 276 | |
| 277 | return nir; |
| 278 | } |
| 279 | |
Dave Airlie | f395e34 | 2016-11-22 04:17:49 +0000 | [diff] [blame] | 280 | static const char *radv_get_shader_name(struct radv_shader_variant *var, |
| 281 | gl_shader_stage stage) |
| 282 | { |
| 283 | switch (stage) { |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 284 | case MESA_SHADER_VERTEX: return var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS"; |
| 285 | case MESA_SHADER_GEOMETRY: return "Geometry Shader"; |
Dave Airlie | f395e34 | 2016-11-22 04:17:49 +0000 | [diff] [blame] | 286 | case MESA_SHADER_FRAGMENT: return "Pixel Shader"; |
| 287 | case MESA_SHADER_COMPUTE: return "Compute Shader"; |
| 288 | default: |
| 289 | return "Unknown shader"; |
| 290 | }; |
| 291 | |
| 292 | } |
| 293 | static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline) |
| 294 | { |
Bas Nieuwenhuizen | 8406f79 | 2017-01-16 21:23:48 +0100 | [diff] [blame] | 295 | unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; |
Dave Airlie | f395e34 | 2016-11-22 04:17:49 +0000 | [diff] [blame] | 296 | struct radv_shader_variant *var; |
| 297 | struct ac_shader_config *conf; |
| 298 | int i; |
| 299 | FILE *file = stderr; |
| 300 | unsigned max_simd_waves = 10; |
| 301 | unsigned lds_per_wave = 0; |
| 302 | |
| 303 | for (i = 0; i < MESA_SHADER_STAGES; i++) { |
| 304 | if (!pipeline->shaders[i]) |
| 305 | continue; |
| 306 | var = pipeline->shaders[i]; |
| 307 | |
| 308 | conf = &var->config; |
| 309 | |
| 310 | if (i == MESA_SHADER_FRAGMENT) { |
| 311 | lds_per_wave = conf->lds_size * lds_increment + |
| 312 | align(var->info.fs.num_interp * 48, lds_increment); |
| 313 | } |
| 314 | |
| 315 | if (conf->num_sgprs) { |
Bas Nieuwenhuizen | 8406f79 | 2017-01-16 21:23:48 +0100 | [diff] [blame] | 316 | if (device->physical_device->rad_info.chip_class >= VI) |
Dave Airlie | f395e34 | 2016-11-22 04:17:49 +0000 | [diff] [blame] | 317 | max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs); |
| 318 | else |
| 319 | max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs); |
| 320 | } |
| 321 | |
| 322 | if (conf->num_vgprs) |
| 323 | max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs); |
| 324 | |
| 325 | /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD |
| 326 | * that PS can use. |
| 327 | */ |
| 328 | if (lds_per_wave) |
| 329 | max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave); |
| 330 | |
| 331 | fprintf(file, "\n%s:\n", |
| 332 | radv_get_shader_name(var, i)); |
| 333 | if (i == MESA_SHADER_FRAGMENT) { |
| 334 | fprintf(file, "*** SHADER CONFIG ***\n" |
| 335 | "SPI_PS_INPUT_ADDR = 0x%04x\n" |
| 336 | "SPI_PS_INPUT_ENA = 0x%04x\n", |
| 337 | conf->spi_ps_input_addr, conf->spi_ps_input_ena); |
| 338 | } |
| 339 | fprintf(file, "*** SHADER STATS ***\n" |
| 340 | "SGPRS: %d\n" |
| 341 | "VGPRS: %d\n" |
| 342 | "Spilled SGPRs: %d\n" |
| 343 | "Spilled VGPRs: %d\n" |
| 344 | "Code Size: %d bytes\n" |
| 345 | "LDS: %d blocks\n" |
| 346 | "Scratch: %d bytes per wave\n" |
| 347 | "Max Waves: %d\n" |
| 348 | "********************\n\n\n", |
| 349 | conf->num_sgprs, conf->num_vgprs, |
| 350 | conf->spilled_sgprs, conf->spilled_vgprs, var->code_size, |
| 351 | conf->lds_size, conf->scratch_bytes_per_wave, |
| 352 | max_simd_waves); |
| 353 | } |
| 354 | } |
| 355 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 356 | void radv_shader_variant_destroy(struct radv_device *device, |
| 357 | struct radv_shader_variant *variant) |
| 358 | { |
| 359 | if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1) |
| 360 | return; |
| 361 | |
| 362 | device->ws->buffer_destroy(variant->bo); |
| 363 | free(variant); |
| 364 | } |
| 365 | |
Dave Airlie | 257866a | 2016-12-08 00:03:38 +0000 | [diff] [blame] | 366 | static void radv_fill_shader_variant(struct radv_device *device, |
| 367 | struct radv_shader_variant *variant, |
| 368 | struct ac_shader_binary *binary, |
| 369 | gl_shader_stage stage) |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 370 | { |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 371 | bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0; |
| 372 | unsigned vgpr_comp_cnt = 0; |
| 373 | |
Bas Nieuwenhuizen | c4d7b9c | 2017-01-29 13:53:05 +0100 | [diff] [blame] | 374 | if (scratch_enabled && !device->llvm_supports_spill) |
| 375 | radv_finishme("shader scratch support only available with LLVM 4.0"); |
| 376 | |
| 377 | variant->code_size = binary->code_size; |
Dave Airlie | 257866a | 2016-12-08 00:03:38 +0000 | [diff] [blame] | 378 | |
| 379 | switch (stage) { |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 380 | case MESA_SHADER_VERTEX: |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 381 | case MESA_SHADER_GEOMETRY: |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 382 | variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | |
| 383 | S_00B12C_SCRATCH_EN(scratch_enabled); |
| 384 | vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; |
| 385 | break; |
| 386 | case MESA_SHADER_FRAGMENT: |
| 387 | variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | |
| 388 | S_00B12C_SCRATCH_EN(scratch_enabled); |
| 389 | break; |
| 390 | case MESA_SHADER_COMPUTE: |
| 391 | variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) | |
| 392 | S_00B84C_SCRATCH_EN(scratch_enabled) | |
| 393 | S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) | |
| 394 | S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) | |
| 395 | S_00B84C_TG_SIZE_EN(1) | |
| 396 | S_00B84C_LDS_SIZE(variant->config.lds_size); |
| 397 | break; |
| 398 | default: |
| 399 | unreachable("unsupported shader type"); |
| 400 | break; |
| 401 | } |
| 402 | |
| 403 | variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | |
| 404 | S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | |
| 405 | S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | |
| 406 | S_00B848_DX10_CLAMP(1) | |
| 407 | S_00B848_FLOAT_MODE(variant->config.float_mode); |
| 408 | |
Dave Airlie | 257866a | 2016-12-08 00:03:38 +0000 | [diff] [blame] | 409 | variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256, |
Bas Nieuwenhuizen | 7c282b3 | 2017-03-12 14:12:19 +0100 | [diff] [blame] | 410 | RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 411 | |
| 412 | void *ptr = device->ws->buffer_map(variant->bo); |
Dave Airlie | 257866a | 2016-12-08 00:03:38 +0000 | [diff] [blame] | 413 | memcpy(ptr, binary->code, binary->code_size); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 414 | device->ws->buffer_unmap(variant->bo); |
| 415 | |
Dave Airlie | 257866a | 2016-12-08 00:03:38 +0000 | [diff] [blame] | 416 | |
| 417 | } |
| 418 | |
| 419 | static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device, |
| 420 | struct nir_shader *shader, |
| 421 | struct radv_pipeline_layout *layout, |
| 422 | const union ac_shader_variant_key *key, |
| 423 | void** code_out, |
| 424 | unsigned *code_size_out, |
| 425 | bool dump) |
| 426 | { |
| 427 | struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant)); |
Bas Nieuwenhuizen | 8406f79 | 2017-01-16 21:23:48 +0100 | [diff] [blame] | 428 | enum radeon_family chip_family = device->physical_device->rad_info.family; |
Dave Airlie | 257866a | 2016-12-08 00:03:38 +0000 | [diff] [blame] | 429 | LLVMTargetMachineRef tm; |
| 430 | if (!variant) |
| 431 | return NULL; |
| 432 | |
| 433 | struct ac_nir_compiler_options options = {0}; |
| 434 | options.layout = layout; |
| 435 | if (key) |
| 436 | options.key = *key; |
| 437 | |
| 438 | struct ac_shader_binary binary; |
| 439 | |
Bas Nieuwenhuizen | 8bc39e2 | 2017-01-02 18:57:02 +0100 | [diff] [blame] | 440 | options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH); |
Dave Airlie | 257866a | 2016-12-08 00:03:38 +0000 | [diff] [blame] | 441 | options.family = chip_family; |
Bas Nieuwenhuizen | 8406f79 | 2017-01-16 21:23:48 +0100 | [diff] [blame] | 442 | options.chip_class = device->physical_device->rad_info.chip_class; |
Bas Nieuwenhuizen | c4d7b9c | 2017-01-29 13:53:05 +0100 | [diff] [blame] | 443 | options.supports_spill = device->llvm_supports_spill; |
| 444 | tm = ac_create_target_machine(chip_family, options.supports_spill); |
Dave Airlie | 257866a | 2016-12-08 00:03:38 +0000 | [diff] [blame] | 445 | ac_compile_nir_shader(tm, &binary, &variant->config, |
| 446 | &variant->info, shader, &options, dump); |
| 447 | LLVMDisposeTargetMachine(tm); |
| 448 | |
| 449 | radv_fill_shader_variant(device, variant, &binary, shader->stage); |
| 450 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 451 | if (code_out) { |
| 452 | *code_out = binary.code; |
| 453 | *code_size_out = binary.code_size; |
| 454 | } else |
| 455 | free(binary.code); |
| 456 | free(binary.config); |
| 457 | free(binary.rodata); |
| 458 | free(binary.global_symbol_offsets); |
| 459 | free(binary.relocs); |
| 460 | free(binary.disasm_string); |
| 461 | variant->ref_count = 1; |
| 462 | return variant; |
| 463 | } |
| 464 | |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 465 | static struct radv_shader_variant * |
| 466 | radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline, |
| 467 | struct nir_shader *nir, |
| 468 | void** code_out, |
| 469 | unsigned *code_size_out, |
| 470 | bool dump_shader) |
| 471 | { |
| 472 | struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant)); |
| 473 | enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family; |
| 474 | LLVMTargetMachineRef tm; |
| 475 | if (!variant) |
| 476 | return NULL; |
| 477 | |
| 478 | struct ac_nir_compiler_options options = {0}; |
| 479 | struct ac_shader_binary binary; |
| 480 | options.family = chip_family; |
| 481 | options.chip_class = pipeline->device->physical_device->rad_info.chip_class; |
| 482 | options.supports_spill = pipeline->device->llvm_supports_spill; |
| 483 | tm = ac_create_target_machine(chip_family, options.supports_spill); |
| 484 | ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader); |
| 485 | LLVMDisposeTargetMachine(tm); |
| 486 | |
| 487 | radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX); |
| 488 | |
| 489 | if (code_out) { |
| 490 | *code_out = binary.code; |
| 491 | *code_size_out = binary.code_size; |
| 492 | } else |
| 493 | free(binary.code); |
| 494 | free(binary.config); |
| 495 | free(binary.rodata); |
| 496 | free(binary.global_symbol_offsets); |
| 497 | free(binary.relocs); |
| 498 | free(binary.disasm_string); |
| 499 | variant->ref_count = 1; |
| 500 | return variant; |
| 501 | } |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 502 | |
| 503 | static struct radv_shader_variant * |
| 504 | radv_pipeline_compile(struct radv_pipeline *pipeline, |
| 505 | struct radv_pipeline_cache *cache, |
| 506 | struct radv_shader_module *module, |
| 507 | const char *entrypoint, |
| 508 | gl_shader_stage stage, |
| 509 | const VkSpecializationInfo *spec_info, |
| 510 | struct radv_pipeline_layout *layout, |
Bas Nieuwenhuizen | 8bc39e2 | 2017-01-02 18:57:02 +0100 | [diff] [blame] | 511 | const union ac_shader_variant_key *key) |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 512 | { |
| 513 | unsigned char sha1[20]; |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 514 | unsigned char gs_copy_sha1[20]; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 515 | struct radv_shader_variant *variant; |
| 516 | nir_shader *nir; |
| 517 | void *code = NULL; |
Grigori Goronzy | 0b539ab | 2016-10-12 00:47:19 +0200 | [diff] [blame] | 518 | unsigned code_size = 0; |
Bas Nieuwenhuizen | 8bc39e2 | 2017-01-02 18:57:02 +0100 | [diff] [blame] | 519 | bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 520 | |
| 521 | if (module->nir) |
Timothy Arceri | e1af20f | 2016-10-13 11:41:23 +1100 | [diff] [blame] | 522 | _mesa_sha1_compute(module->nir->info->name, |
| 523 | strlen(module->nir->info->name), |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 524 | module->sha1); |
| 525 | |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 526 | radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0); |
| 527 | if (stage == MESA_SHADER_GEOMETRY) |
| 528 | radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info, |
| 529 | layout, key, 1); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 530 | |
Timothy Arceri | 4ffdab7 | 2017-03-15 12:40:53 +1100 | [diff] [blame] | 531 | variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device, |
| 532 | cache, |
| 533 | sha1); |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 534 | |
Timothy Arceri | 4ffdab7 | 2017-03-15 12:40:53 +1100 | [diff] [blame] | 535 | if (stage == MESA_SHADER_GEOMETRY) { |
| 536 | pipeline->gs_copy_shader = |
| 537 | radv_create_shader_variant_from_pipeline_cache( |
| 538 | pipeline->device, |
| 539 | cache, |
| 540 | gs_copy_sha1); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 541 | } |
Timothy Arceri | 72ab7bb | 2017-03-15 13:07:40 +1100 | [diff] [blame] | 542 | |
| 543 | if (variant && |
| 544 | (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader)) |
Timothy Arceri | 4ffdab7 | 2017-03-15 12:40:53 +1100 | [diff] [blame] | 545 | return variant; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 546 | |
| 547 | nir = radv_shader_compile_to_nir(pipeline->device, |
| 548 | module, entrypoint, stage, |
| 549 | spec_info, dump); |
| 550 | if (nir == NULL) |
| 551 | return NULL; |
| 552 | |
Timothy Arceri | 72ab7bb | 2017-03-15 13:07:40 +1100 | [diff] [blame] | 553 | if (!variant) { |
| 554 | variant = radv_shader_variant_create(pipeline->device, nir, |
| 555 | layout, key, &code, |
| 556 | &code_size, dump); |
| 557 | } |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 558 | |
Timothy Arceri | 72ab7bb | 2017-03-15 13:07:40 +1100 | [diff] [blame] | 559 | if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) { |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 560 | void *gs_copy_code = NULL; |
| 561 | unsigned gs_copy_code_size = 0; |
| 562 | pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader( |
| 563 | pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump); |
| 564 | |
Timothy Arceri | 4ffdab7 | 2017-03-15 12:40:53 +1100 | [diff] [blame] | 565 | if (pipeline->gs_copy_shader) { |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 566 | pipeline->gs_copy_shader = |
Dave Airlie | 10c2b58 | 2017-03-20 13:24:02 +1000 | [diff] [blame] | 567 | radv_pipeline_cache_insert_shader(cache, |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 568 | gs_copy_sha1, |
| 569 | pipeline->gs_copy_shader, |
| 570 | gs_copy_code, |
| 571 | gs_copy_code_size); |
| 572 | } |
| 573 | } |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 574 | if (!module->nir) |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 575 | ralloc_free(nir); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 576 | |
Timothy Arceri | 4ffdab7 | 2017-03-15 12:40:53 +1100 | [diff] [blame] | 577 | if (variant) |
Dave Airlie | 10c2b58 | 2017-03-20 13:24:02 +1000 | [diff] [blame] | 578 | variant = radv_pipeline_cache_insert_shader(cache, sha1, variant, |
| 579 | code, code_size); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 580 | |
| 581 | if (code) |
| 582 | free(code); |
| 583 | return variant; |
| 584 | } |
| 585 | |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 586 | static VkResult |
| 587 | radv_pipeline_scratch_init(struct radv_device *device, |
| 588 | struct radv_pipeline *pipeline) |
| 589 | { |
| 590 | unsigned scratch_bytes_per_wave = 0; |
| 591 | unsigned max_waves = 0; |
| 592 | unsigned min_waves = 1; |
| 593 | |
| 594 | for (int i = 0; i < MESA_SHADER_STAGES; ++i) { |
| 595 | if (pipeline->shaders[i]) { |
| 596 | unsigned max_stage_waves = device->scratch_waves; |
| 597 | |
| 598 | scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave, |
| 599 | pipeline->shaders[i]->config.scratch_bytes_per_wave); |
| 600 | |
| 601 | max_stage_waves = MIN2(max_stage_waves, |
| 602 | 4 * device->physical_device->rad_info.num_good_compute_units * |
| 603 | (256 / pipeline->shaders[i]->config.num_vgprs)); |
| 604 | max_waves = MAX2(max_waves, max_stage_waves); |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | if (pipeline->shaders[MESA_SHADER_COMPUTE]) { |
| 609 | unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] * |
| 610 | pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] * |
| 611 | pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2]; |
| 612 | min_waves = MAX2(min_waves, round_up_u32(group_size, 64)); |
| 613 | } |
| 614 | |
| 615 | if (scratch_bytes_per_wave) |
| 616 | max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave); |
| 617 | |
| 618 | if (scratch_bytes_per_wave && max_waves < min_waves) { |
| 619 | /* Not really true at this moment, but will be true on first |
| 620 | * execution. Avoid having hanging shaders. */ |
| 621 | return VK_ERROR_OUT_OF_DEVICE_MEMORY; |
| 622 | } |
| 623 | pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave; |
| 624 | pipeline->max_waves = max_waves; |
| 625 | return VK_SUCCESS; |
| 626 | } |
| 627 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 628 | static uint32_t si_translate_blend_function(VkBlendOp op) |
| 629 | { |
| 630 | switch (op) { |
| 631 | case VK_BLEND_OP_ADD: |
| 632 | return V_028780_COMB_DST_PLUS_SRC; |
| 633 | case VK_BLEND_OP_SUBTRACT: |
| 634 | return V_028780_COMB_SRC_MINUS_DST; |
| 635 | case VK_BLEND_OP_REVERSE_SUBTRACT: |
| 636 | return V_028780_COMB_DST_MINUS_SRC; |
| 637 | case VK_BLEND_OP_MIN: |
| 638 | return V_028780_COMB_MIN_DST_SRC; |
| 639 | case VK_BLEND_OP_MAX: |
| 640 | return V_028780_COMB_MAX_DST_SRC; |
| 641 | default: |
| 642 | return 0; |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | static uint32_t si_translate_blend_factor(VkBlendFactor factor) |
| 647 | { |
| 648 | switch (factor) { |
| 649 | case VK_BLEND_FACTOR_ZERO: |
| 650 | return V_028780_BLEND_ZERO; |
| 651 | case VK_BLEND_FACTOR_ONE: |
| 652 | return V_028780_BLEND_ONE; |
| 653 | case VK_BLEND_FACTOR_SRC_COLOR: |
| 654 | return V_028780_BLEND_SRC_COLOR; |
| 655 | case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR: |
| 656 | return V_028780_BLEND_ONE_MINUS_SRC_COLOR; |
| 657 | case VK_BLEND_FACTOR_DST_COLOR: |
| 658 | return V_028780_BLEND_DST_COLOR; |
| 659 | case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR: |
| 660 | return V_028780_BLEND_ONE_MINUS_DST_COLOR; |
| 661 | case VK_BLEND_FACTOR_SRC_ALPHA: |
| 662 | return V_028780_BLEND_SRC_ALPHA; |
| 663 | case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA: |
| 664 | return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; |
| 665 | case VK_BLEND_FACTOR_DST_ALPHA: |
| 666 | return V_028780_BLEND_DST_ALPHA; |
| 667 | case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA: |
| 668 | return V_028780_BLEND_ONE_MINUS_DST_ALPHA; |
| 669 | case VK_BLEND_FACTOR_CONSTANT_COLOR: |
| 670 | return V_028780_BLEND_CONSTANT_COLOR; |
| 671 | case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR: |
| 672 | return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; |
| 673 | case VK_BLEND_FACTOR_CONSTANT_ALPHA: |
| 674 | return V_028780_BLEND_CONSTANT_ALPHA; |
| 675 | case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA: |
| 676 | return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; |
| 677 | case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE: |
| 678 | return V_028780_BLEND_SRC_ALPHA_SATURATE; |
| 679 | case VK_BLEND_FACTOR_SRC1_COLOR: |
| 680 | return V_028780_BLEND_SRC1_COLOR; |
| 681 | case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR: |
| 682 | return V_028780_BLEND_INV_SRC1_COLOR; |
| 683 | case VK_BLEND_FACTOR_SRC1_ALPHA: |
| 684 | return V_028780_BLEND_SRC1_ALPHA; |
| 685 | case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA: |
| 686 | return V_028780_BLEND_INV_SRC1_ALPHA; |
| 687 | default: |
| 688 | return 0; |
| 689 | } |
| 690 | } |
| 691 | |
| 692 | static bool is_dual_src(VkBlendFactor factor) |
| 693 | { |
| 694 | switch (factor) { |
| 695 | case VK_BLEND_FACTOR_SRC1_COLOR: |
| 696 | case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR: |
| 697 | case VK_BLEND_FACTOR_SRC1_ALPHA: |
| 698 | case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA: |
| 699 | return true; |
| 700 | default: |
| 701 | return false; |
| 702 | } |
| 703 | } |
| 704 | |
| 705 | static unsigned si_choose_spi_color_format(VkFormat vk_format, |
| 706 | bool blend_enable, |
| 707 | bool blend_need_alpha) |
| 708 | { |
| 709 | const struct vk_format_description *desc = vk_format_description(vk_format); |
| 710 | unsigned format, ntype, swap; |
| 711 | |
| 712 | /* Alpha is needed for alpha-to-coverage. |
| 713 | * Blending may be with or without alpha. |
| 714 | */ |
| 715 | unsigned normal = 0; /* most optimal, may not support blending or export alpha */ |
| 716 | unsigned alpha = 0; /* exports alpha, but may not support blending */ |
| 717 | unsigned blend = 0; /* supports blending, but may not export alpha */ |
| 718 | unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */ |
| 719 | |
| 720 | format = radv_translate_colorformat(vk_format); |
| 721 | ntype = radv_translate_color_numformat(vk_format, desc, |
| 722 | vk_format_get_first_non_void_channel(vk_format)); |
| 723 | swap = radv_translate_colorswap(vk_format, false); |
| 724 | |
| 725 | /* Choose the SPI color formats. These are required values for Stoney/RB+. |
| 726 | * Other chips have multiple choices, though they are not necessarily better. |
| 727 | */ |
| 728 | switch (format) { |
| 729 | case V_028C70_COLOR_5_6_5: |
| 730 | case V_028C70_COLOR_1_5_5_5: |
| 731 | case V_028C70_COLOR_5_5_5_1: |
| 732 | case V_028C70_COLOR_4_4_4_4: |
| 733 | case V_028C70_COLOR_10_11_11: |
| 734 | case V_028C70_COLOR_11_11_10: |
| 735 | case V_028C70_COLOR_8: |
| 736 | case V_028C70_COLOR_8_8: |
| 737 | case V_028C70_COLOR_8_8_8_8: |
| 738 | case V_028C70_COLOR_10_10_10_2: |
| 739 | case V_028C70_COLOR_2_10_10_10: |
| 740 | if (ntype == V_028C70_NUMBER_UINT) |
| 741 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; |
| 742 | else if (ntype == V_028C70_NUMBER_SINT) |
| 743 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; |
| 744 | else |
| 745 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; |
| 746 | break; |
| 747 | |
| 748 | case V_028C70_COLOR_16: |
| 749 | case V_028C70_COLOR_16_16: |
| 750 | case V_028C70_COLOR_16_16_16_16: |
| 751 | if (ntype == V_028C70_NUMBER_UNORM || |
| 752 | ntype == V_028C70_NUMBER_SNORM) { |
| 753 | /* UNORM16 and SNORM16 don't support blending */ |
| 754 | if (ntype == V_028C70_NUMBER_UNORM) |
| 755 | normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR; |
| 756 | else |
| 757 | normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR; |
| 758 | |
| 759 | /* Use 32 bits per channel for blending. */ |
| 760 | if (format == V_028C70_COLOR_16) { |
| 761 | if (swap == V_028C70_SWAP_STD) { /* R */ |
| 762 | blend = V_028714_SPI_SHADER_32_R; |
| 763 | blend_alpha = V_028714_SPI_SHADER_32_AR; |
| 764 | } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ |
| 765 | blend = blend_alpha = V_028714_SPI_SHADER_32_AR; |
| 766 | else |
| 767 | assert(0); |
| 768 | } else if (format == V_028C70_COLOR_16_16) { |
| 769 | if (swap == V_028C70_SWAP_STD) { /* RG */ |
| 770 | blend = V_028714_SPI_SHADER_32_GR; |
| 771 | blend_alpha = V_028714_SPI_SHADER_32_ABGR; |
| 772 | } else if (swap == V_028C70_SWAP_ALT) /* RA */ |
| 773 | blend = blend_alpha = V_028714_SPI_SHADER_32_AR; |
| 774 | else |
| 775 | assert(0); |
| 776 | } else /* 16_16_16_16 */ |
| 777 | blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR; |
| 778 | } else if (ntype == V_028C70_NUMBER_UINT) |
| 779 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; |
| 780 | else if (ntype == V_028C70_NUMBER_SINT) |
| 781 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; |
| 782 | else if (ntype == V_028C70_NUMBER_FLOAT) |
| 783 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; |
| 784 | else |
| 785 | assert(0); |
| 786 | break; |
| 787 | |
| 788 | case V_028C70_COLOR_32: |
| 789 | if (swap == V_028C70_SWAP_STD) { /* R */ |
| 790 | blend = normal = V_028714_SPI_SHADER_32_R; |
| 791 | alpha = blend_alpha = V_028714_SPI_SHADER_32_AR; |
| 792 | } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ |
| 793 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; |
| 794 | else |
| 795 | assert(0); |
| 796 | break; |
| 797 | |
| 798 | case V_028C70_COLOR_32_32: |
| 799 | if (swap == V_028C70_SWAP_STD) { /* RG */ |
| 800 | blend = normal = V_028714_SPI_SHADER_32_GR; |
| 801 | alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR; |
| 802 | } else if (swap == V_028C70_SWAP_ALT) /* RA */ |
| 803 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; |
| 804 | else |
| 805 | assert(0); |
| 806 | break; |
| 807 | |
| 808 | case V_028C70_COLOR_32_32_32_32: |
| 809 | case V_028C70_COLOR_8_24: |
| 810 | case V_028C70_COLOR_24_8: |
| 811 | case V_028C70_COLOR_X24_8_32_FLOAT: |
| 812 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR; |
| 813 | break; |
| 814 | |
| 815 | default: |
| 816 | unreachable("unhandled blend format"); |
| 817 | } |
| 818 | |
| 819 | if (blend_enable && blend_need_alpha) |
| 820 | return blend_alpha; |
| 821 | else if(blend_need_alpha) |
| 822 | return alpha; |
| 823 | else if(blend_enable) |
| 824 | return blend; |
| 825 | else |
| 826 | return normal; |
| 827 | } |
| 828 | |
| 829 | static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format) |
| 830 | { |
| 831 | unsigned i, cb_shader_mask = 0; |
| 832 | |
| 833 | for (i = 0; i < 8; i++) { |
| 834 | switch ((spi_shader_col_format >> (i * 4)) & 0xf) { |
| 835 | case V_028714_SPI_SHADER_ZERO: |
| 836 | break; |
| 837 | case V_028714_SPI_SHADER_32_R: |
| 838 | cb_shader_mask |= 0x1 << (i * 4); |
| 839 | break; |
| 840 | case V_028714_SPI_SHADER_32_GR: |
| 841 | cb_shader_mask |= 0x3 << (i * 4); |
| 842 | break; |
| 843 | case V_028714_SPI_SHADER_32_AR: |
| 844 | cb_shader_mask |= 0x9 << (i * 4); |
| 845 | break; |
| 846 | case V_028714_SPI_SHADER_FP16_ABGR: |
| 847 | case V_028714_SPI_SHADER_UNORM16_ABGR: |
| 848 | case V_028714_SPI_SHADER_SNORM16_ABGR: |
| 849 | case V_028714_SPI_SHADER_UINT16_ABGR: |
| 850 | case V_028714_SPI_SHADER_SINT16_ABGR: |
| 851 | case V_028714_SPI_SHADER_32_ABGR: |
| 852 | cb_shader_mask |= 0xf << (i * 4); |
| 853 | break; |
| 854 | default: |
| 855 | assert(0); |
| 856 | } |
| 857 | } |
| 858 | return cb_shader_mask; |
| 859 | } |
| 860 | |
| 861 | static void |
| 862 | radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline, |
| 863 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 864 | uint32_t blend_enable, |
| 865 | uint32_t blend_need_alpha, |
Dave Airlie | 73592b9 | 2016-11-02 00:33:33 +0000 | [diff] [blame] | 866 | bool single_cb_enable, |
| 867 | bool blend_mrt0_is_dual_src) |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 868 | { |
| 869 | RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); |
| 870 | struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; |
| 871 | struct radv_blend_state *blend = &pipeline->graphics.blend; |
| 872 | unsigned col_format = 0; |
| 873 | |
| 874 | for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) { |
| 875 | struct radv_render_pass_attachment *attachment; |
| 876 | unsigned cf; |
| 877 | |
| 878 | attachment = pass->attachments + subpass->color_attachments[i].attachment; |
| 879 | |
| 880 | cf = si_choose_spi_color_format(attachment->format, |
| 881 | blend_enable & (1 << i), |
| 882 | blend_need_alpha & (1 << i)); |
| 883 | |
| 884 | col_format |= cf << (4 * i); |
| 885 | } |
| 886 | |
| 887 | blend->cb_shader_mask = si_get_cb_shader_mask(col_format); |
| 888 | |
Dave Airlie | 73592b9 | 2016-11-02 00:33:33 +0000 | [diff] [blame] | 889 | if (blend_mrt0_is_dual_src) |
| 890 | col_format |= (col_format & 0xf) << 4; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 891 | blend->spi_shader_col_format = col_format; |
| 892 | } |
| 893 | |
| 894 | static bool |
| 895 | format_is_int8(VkFormat format) |
| 896 | { |
| 897 | const struct vk_format_description *desc = vk_format_description(format); |
| 898 | int channel = vk_format_get_first_non_void_channel(format); |
| 899 | |
| 900 | return channel >= 0 && desc->channel[channel].pure_integer && |
| 901 | desc->channel[channel].size == 8; |
| 902 | } |
| 903 | |
| 904 | unsigned radv_format_meta_fs_key(VkFormat format) |
| 905 | { |
| 906 | unsigned col_format = si_choose_spi_color_format(format, false, false) - 1; |
| 907 | bool is_int8 = format_is_int8(format); |
| 908 | |
| 909 | return col_format + (is_int8 ? 3 : 0); |
| 910 | } |
| 911 | |
| 912 | static unsigned |
| 913 | radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 914 | { |
| 915 | RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); |
| 916 | struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; |
| 917 | unsigned is_int8 = 0; |
| 918 | |
| 919 | for (unsigned i = 0; i < subpass->color_count; ++i) { |
| 920 | struct radv_render_pass_attachment *attachment; |
| 921 | |
| 922 | attachment = pass->attachments + subpass->color_attachments[i].attachment; |
| 923 | |
| 924 | if (format_is_int8(attachment->format)) |
| 925 | is_int8 |= 1 << i; |
| 926 | } |
| 927 | |
| 928 | return is_int8; |
| 929 | } |
| 930 | |
| 931 | static void |
| 932 | radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, |
| 933 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 934 | const struct radv_graphics_pipeline_create_info *extra) |
| 935 | { |
| 936 | const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState; |
| 937 | struct radv_blend_state *blend = &pipeline->graphics.blend; |
| 938 | unsigned mode = V_028808_CB_NORMAL; |
| 939 | uint32_t blend_enable = 0, blend_need_alpha = 0; |
Dave Airlie | 73592b9 | 2016-11-02 00:33:33 +0000 | [diff] [blame] | 940 | bool blend_mrt0_is_dual_src = false; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 941 | int i; |
| 942 | bool single_cb_enable = false; |
Darren Salt | 9b12151 | 2016-10-16 20:32:19 +0100 | [diff] [blame] | 943 | |
| 944 | if (!vkblend) |
| 945 | return; |
| 946 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 947 | if (extra && extra->custom_blend_mode) { |
| 948 | single_cb_enable = true; |
| 949 | mode = extra->custom_blend_mode; |
| 950 | } |
| 951 | blend->cb_color_control = 0; |
| 952 | if (vkblend->logicOpEnable) |
| 953 | blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4)); |
| 954 | else |
| 955 | blend->cb_color_control |= S_028808_ROP3(0xcc); |
| 956 | |
| 957 | blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | |
| 958 | S_028B70_ALPHA_TO_MASK_OFFSET1(2) | |
| 959 | S_028B70_ALPHA_TO_MASK_OFFSET2(2) | |
| 960 | S_028B70_ALPHA_TO_MASK_OFFSET3(2); |
| 961 | |
| 962 | blend->cb_target_mask = 0; |
| 963 | for (i = 0; i < vkblend->attachmentCount; i++) { |
| 964 | const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i]; |
| 965 | unsigned blend_cntl = 0; |
| 966 | VkBlendOp eqRGB = att->colorBlendOp; |
| 967 | VkBlendFactor srcRGB = att->srcColorBlendFactor; |
| 968 | VkBlendFactor dstRGB = att->dstColorBlendFactor; |
| 969 | VkBlendOp eqA = att->alphaBlendOp; |
| 970 | VkBlendFactor srcA = att->srcAlphaBlendFactor; |
| 971 | VkBlendFactor dstA = att->dstAlphaBlendFactor; |
| 972 | |
| 973 | blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); |
| 974 | |
| 975 | if (!att->colorWriteMask) |
| 976 | continue; |
| 977 | |
| 978 | blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i); |
| 979 | if (!att->blendEnable) { |
| 980 | blend->cb_blend_control[i] = blend_cntl; |
| 981 | continue; |
| 982 | } |
| 983 | |
| 984 | if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA)) |
Dave Airlie | 73592b9 | 2016-11-02 00:33:33 +0000 | [diff] [blame] | 985 | if (i == 0) |
| 986 | blend_mrt0_is_dual_src = true; |
| 987 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 988 | if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) { |
| 989 | srcRGB = VK_BLEND_FACTOR_ONE; |
| 990 | dstRGB = VK_BLEND_FACTOR_ONE; |
| 991 | } |
| 992 | if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) { |
| 993 | srcA = VK_BLEND_FACTOR_ONE; |
| 994 | dstA = VK_BLEND_FACTOR_ONE; |
| 995 | } |
| 996 | |
| 997 | blend_cntl |= S_028780_ENABLE(1); |
| 998 | |
| 999 | blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); |
| 1000 | blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); |
| 1001 | blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); |
| 1002 | if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { |
| 1003 | blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); |
| 1004 | blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); |
| 1005 | blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); |
| 1006 | blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); |
| 1007 | } |
| 1008 | blend->cb_blend_control[i] = blend_cntl; |
| 1009 | |
| 1010 | blend_enable |= 1 << i; |
| 1011 | |
| 1012 | if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA || |
| 1013 | dstRGB == VK_BLEND_FACTOR_SRC_ALPHA || |
| 1014 | srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || |
| 1015 | dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || |
| 1016 | srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA || |
| 1017 | dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
| 1018 | blend_need_alpha |= 1 << i; |
| 1019 | } |
| 1020 | for (i = vkblend->attachmentCount; i < 8; i++) |
| 1021 | blend->cb_blend_control[i] = 0; |
| 1022 | |
| 1023 | if (blend->cb_target_mask) |
| 1024 | blend->cb_color_control |= S_028808_MODE(mode); |
| 1025 | else |
| 1026 | blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE); |
| 1027 | |
| 1028 | radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, |
Dave Airlie | 73592b9 | 2016-11-02 00:33:33 +0000 | [diff] [blame] | 1029 | blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1030 | } |
| 1031 | |
| 1032 | static uint32_t si_translate_stencil_op(enum VkStencilOp op) |
| 1033 | { |
| 1034 | switch (op) { |
| 1035 | case VK_STENCIL_OP_KEEP: |
| 1036 | return V_02842C_STENCIL_KEEP; |
| 1037 | case VK_STENCIL_OP_ZERO: |
| 1038 | return V_02842C_STENCIL_ZERO; |
| 1039 | case VK_STENCIL_OP_REPLACE: |
| 1040 | return V_02842C_STENCIL_REPLACE_TEST; |
| 1041 | case VK_STENCIL_OP_INCREMENT_AND_CLAMP: |
| 1042 | return V_02842C_STENCIL_ADD_CLAMP; |
| 1043 | case VK_STENCIL_OP_DECREMENT_AND_CLAMP: |
| 1044 | return V_02842C_STENCIL_SUB_CLAMP; |
| 1045 | case VK_STENCIL_OP_INVERT: |
| 1046 | return V_02842C_STENCIL_INVERT; |
| 1047 | case VK_STENCIL_OP_INCREMENT_AND_WRAP: |
| 1048 | return V_02842C_STENCIL_ADD_WRAP; |
| 1049 | case VK_STENCIL_OP_DECREMENT_AND_WRAP: |
| 1050 | return V_02842C_STENCIL_SUB_WRAP; |
| 1051 | default: |
| 1052 | return 0; |
| 1053 | } |
| 1054 | } |
| 1055 | static void |
| 1056 | radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline, |
| 1057 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 1058 | const struct radv_graphics_pipeline_create_info *extra) |
| 1059 | { |
| 1060 | const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState; |
| 1061 | struct radv_depth_stencil_state *ds = &pipeline->graphics.ds; |
| 1062 | |
| 1063 | memset(ds, 0, sizeof(*ds)); |
| 1064 | if (!vkds) |
| 1065 | return; |
| 1066 | ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) | |
| 1067 | S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) | |
| 1068 | S_028800_ZFUNC(vkds->depthCompareOp) | |
| 1069 | S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0); |
| 1070 | |
| 1071 | if (vkds->stencilTestEnable) { |
| 1072 | ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1); |
| 1073 | ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp); |
| 1074 | ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp)); |
| 1075 | ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp)); |
| 1076 | ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp)); |
| 1077 | |
| 1078 | ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp); |
| 1079 | ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp)); |
| 1080 | ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp)); |
| 1081 | ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp)); |
| 1082 | } |
| 1083 | |
| 1084 | if (extra) { |
| 1085 | |
| 1086 | ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear); |
| 1087 | ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear); |
| 1088 | |
| 1089 | ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize); |
| 1090 | ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace); |
| 1091 | ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace); |
| 1092 | ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear); |
| 1093 | ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear); |
| 1094 | } |
| 1095 | } |
| 1096 | |
| 1097 | static uint32_t si_translate_fill(VkPolygonMode func) |
| 1098 | { |
| 1099 | switch(func) { |
| 1100 | case VK_POLYGON_MODE_FILL: |
| 1101 | return V_028814_X_DRAW_TRIANGLES; |
| 1102 | case VK_POLYGON_MODE_LINE: |
| 1103 | return V_028814_X_DRAW_LINES; |
| 1104 | case VK_POLYGON_MODE_POINT: |
| 1105 | return V_028814_X_DRAW_POINTS; |
| 1106 | default: |
| 1107 | assert(0); |
| 1108 | return V_028814_X_DRAW_POINTS; |
| 1109 | } |
| 1110 | } |
| 1111 | static void |
| 1112 | radv_pipeline_init_raster_state(struct radv_pipeline *pipeline, |
| 1113 | const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 1114 | { |
| 1115 | const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState; |
| 1116 | struct radv_raster_state *raster = &pipeline->graphics.raster; |
| 1117 | |
| 1118 | memset(raster, 0, sizeof(*raster)); |
| 1119 | |
| 1120 | raster->spi_interp_control = |
| 1121 | S_0286D4_FLAT_SHADE_ENA(1) | |
| 1122 | S_0286D4_PNT_SPRITE_ENA(1) | |
| 1123 | S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | |
| 1124 | S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | |
| 1125 | S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | |
| 1126 | S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) | |
| 1127 | S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom |
| 1128 | |
| 1129 | raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1); |
| 1130 | raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) | |
| 1131 | S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions. |
| 1132 | S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) | |
| 1133 | S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) | |
| 1134 | S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) | |
| 1135 | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); |
| 1136 | |
| 1137 | raster->pa_su_vtx_cntl = |
| 1138 | S_028BE4_PIX_CENTER(1) | // TODO verify |
| 1139 | S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) | |
| 1140 | S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH); |
| 1141 | |
| 1142 | raster->pa_su_sc_mode_cntl = |
| 1143 | S_028814_FACE(vkraster->frontFace) | |
| 1144 | S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) | |
| 1145 | S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) | |
| 1146 | S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) | |
| 1147 | S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) | |
| 1148 | S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) | |
| 1149 | S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | |
| 1150 | S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | |
| 1151 | S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0); |
| 1152 | |
| 1153 | } |
| 1154 | |
| 1155 | static void |
| 1156 | radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, |
| 1157 | const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 1158 | { |
| 1159 | const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState; |
| 1160 | struct radv_blend_state *blend = &pipeline->graphics.blend; |
| 1161 | struct radv_multisample_state *ms = &pipeline->graphics.ms; |
Bas Nieuwenhuizen | 8406f79 | 2017-01-16 21:23:48 +0100 | [diff] [blame] | 1162 | unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1163 | int ps_iter_samples = 1; |
| 1164 | uint32_t mask = 0xffff; |
| 1165 | |
| 1166 | ms->num_samples = vkms->rasterizationSamples; |
Dave Airlie | f3a3fea | 2016-11-24 00:18:21 +0000 | [diff] [blame] | 1167 | |
| 1168 | if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) { |
| 1169 | ps_iter_samples = vkms->rasterizationSamples; |
| 1170 | } |
| 1171 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1172 | ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1); |
| 1173 | ms->pa_sc_aa_config = 0; |
| 1174 | ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) | |
| 1175 | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1); |
| 1176 | ms->pa_sc_mode_cntl_1 = |
| 1177 | S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes |
| 1178 | S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) | |
| 1179 | /* always 1: */ |
| 1180 | S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | |
| 1181 | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | |
| 1182 | S_028A4C_TILE_WALK_ORDER_ENABLE(1) | |
| 1183 | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | |
| 1184 | EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | |
| 1185 | EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1); |
| 1186 | |
| 1187 | if (vkms->rasterizationSamples > 1) { |
| 1188 | unsigned log_samples = util_logbase2(vkms->rasterizationSamples); |
| 1189 | unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples)); |
| 1190 | ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1); |
| 1191 | ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */ |
| 1192 | ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) | |
| 1193 | S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) | |
| 1194 | S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | |
| 1195 | S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples); |
| 1196 | ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) | |
| 1197 | S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) | |
| 1198 | S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */ |
| 1199 | ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); |
| 1200 | } |
| 1201 | |
| 1202 | if (vkms->alphaToCoverageEnable) |
| 1203 | blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1); |
| 1204 | |
| 1205 | if (vkms->pSampleMask) { |
| 1206 | mask = vkms->pSampleMask[0] & 0xffff; |
| 1207 | } |
| 1208 | |
| 1209 | ms->pa_sc_aa_mask[0] = mask | (mask << 16); |
| 1210 | ms->pa_sc_aa_mask[1] = mask | (mask << 16); |
| 1211 | } |
| 1212 | |
| 1213 | static uint32_t |
| 1214 | si_translate_prim(enum VkPrimitiveTopology topology) |
| 1215 | { |
| 1216 | switch (topology) { |
| 1217 | case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: |
| 1218 | return V_008958_DI_PT_POINTLIST; |
| 1219 | case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: |
| 1220 | return V_008958_DI_PT_LINELIST; |
| 1221 | case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: |
| 1222 | return V_008958_DI_PT_LINESTRIP; |
| 1223 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: |
| 1224 | return V_008958_DI_PT_TRILIST; |
| 1225 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: |
| 1226 | return V_008958_DI_PT_TRISTRIP; |
| 1227 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: |
| 1228 | return V_008958_DI_PT_TRIFAN; |
| 1229 | case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: |
| 1230 | return V_008958_DI_PT_LINELIST_ADJ; |
| 1231 | case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: |
| 1232 | return V_008958_DI_PT_LINESTRIP_ADJ; |
| 1233 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: |
| 1234 | return V_008958_DI_PT_TRILIST_ADJ; |
| 1235 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: |
| 1236 | return V_008958_DI_PT_TRISTRIP_ADJ; |
| 1237 | case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: |
| 1238 | return V_008958_DI_PT_PATCH; |
| 1239 | default: |
| 1240 | assert(0); |
| 1241 | return 0; |
| 1242 | } |
| 1243 | } |
| 1244 | |
| 1245 | static uint32_t |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 1246 | si_conv_gl_prim_to_gs_out(unsigned gl_prim) |
| 1247 | { |
| 1248 | switch (gl_prim) { |
| 1249 | case 0: /* GL_POINTS */ |
| 1250 | return V_028A6C_OUTPRIM_TYPE_POINTLIST; |
| 1251 | case 1: /* GL_LINES */ |
| 1252 | case 3: /* GL_LINE_STRIP */ |
| 1253 | case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */ |
| 1254 | case 0x8E7A: /* GL_ISOLINES */ |
| 1255 | return V_028A6C_OUTPRIM_TYPE_LINESTRIP; |
| 1256 | |
| 1257 | case 4: /* GL_TRIANGLES */ |
| 1258 | case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */ |
| 1259 | case 5: /* GL_TRIANGLE_STRIP */ |
| 1260 | case 7: /* GL_QUADS */ |
| 1261 | return V_028A6C_OUTPRIM_TYPE_TRISTRIP; |
| 1262 | default: |
| 1263 | assert(0); |
| 1264 | return 0; |
| 1265 | } |
| 1266 | } |
| 1267 | |
| 1268 | static uint32_t |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1269 | si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology) |
| 1270 | { |
| 1271 | switch (topology) { |
| 1272 | case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: |
| 1273 | case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: |
| 1274 | return V_028A6C_OUTPRIM_TYPE_POINTLIST; |
| 1275 | case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: |
| 1276 | case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: |
| 1277 | case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: |
| 1278 | case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: |
| 1279 | return V_028A6C_OUTPRIM_TYPE_LINESTRIP; |
| 1280 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: |
| 1281 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: |
| 1282 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: |
| 1283 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: |
| 1284 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: |
| 1285 | return V_028A6C_OUTPRIM_TYPE_TRISTRIP; |
| 1286 | default: |
| 1287 | assert(0); |
| 1288 | return 0; |
| 1289 | } |
| 1290 | } |
| 1291 | |
| 1292 | static unsigned si_map_swizzle(unsigned swizzle) |
| 1293 | { |
| 1294 | switch (swizzle) { |
| 1295 | case VK_SWIZZLE_Y: |
| 1296 | return V_008F0C_SQ_SEL_Y; |
| 1297 | case VK_SWIZZLE_Z: |
| 1298 | return V_008F0C_SQ_SEL_Z; |
| 1299 | case VK_SWIZZLE_W: |
| 1300 | return V_008F0C_SQ_SEL_W; |
| 1301 | case VK_SWIZZLE_0: |
| 1302 | return V_008F0C_SQ_SEL_0; |
| 1303 | case VK_SWIZZLE_1: |
| 1304 | return V_008F0C_SQ_SEL_1; |
| 1305 | default: /* VK_SWIZZLE_X */ |
| 1306 | return V_008F0C_SQ_SEL_X; |
| 1307 | } |
| 1308 | } |
| 1309 | |
| 1310 | static void |
| 1311 | radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, |
| 1312 | const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 1313 | { |
| 1314 | radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL; |
| 1315 | RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); |
| 1316 | struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; |
| 1317 | |
| 1318 | pipeline->dynamic_state = default_dynamic_state; |
| 1319 | |
| 1320 | if (pCreateInfo->pDynamicState) { |
| 1321 | /* Remove all of the states that are marked as dynamic */ |
| 1322 | uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount; |
| 1323 | for (uint32_t s = 0; s < count; s++) |
| 1324 | states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]); |
| 1325 | } |
| 1326 | |
| 1327 | struct radv_dynamic_state *dynamic = &pipeline->dynamic_state; |
| 1328 | |
Darren Salt | 9b12151 | 2016-10-16 20:32:19 +0100 | [diff] [blame] | 1329 | /* Section 9.2 of the Vulkan 1.0.15 spec says: |
| 1330 | * |
| 1331 | * pViewportState is [...] NULL if the pipeline |
| 1332 | * has rasterization disabled. |
| 1333 | */ |
| 1334 | if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) { |
| 1335 | assert(pCreateInfo->pViewportState); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1336 | |
Darren Salt | 9b12151 | 2016-10-16 20:32:19 +0100 | [diff] [blame] | 1337 | dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount; |
| 1338 | if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) { |
| 1339 | typed_memcpy(dynamic->viewport.viewports, |
| 1340 | pCreateInfo->pViewportState->pViewports, |
| 1341 | pCreateInfo->pViewportState->viewportCount); |
| 1342 | } |
| 1343 | |
| 1344 | dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount; |
| 1345 | if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) { |
| 1346 | typed_memcpy(dynamic->scissor.scissors, |
| 1347 | pCreateInfo->pViewportState->pScissors, |
| 1348 | pCreateInfo->pViewportState->scissorCount); |
| 1349 | } |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1350 | } |
| 1351 | |
| 1352 | if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) { |
| 1353 | assert(pCreateInfo->pRasterizationState); |
| 1354 | dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth; |
| 1355 | } |
| 1356 | |
| 1357 | if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) { |
| 1358 | assert(pCreateInfo->pRasterizationState); |
| 1359 | dynamic->depth_bias.bias = |
| 1360 | pCreateInfo->pRasterizationState->depthBiasConstantFactor; |
| 1361 | dynamic->depth_bias.clamp = |
| 1362 | pCreateInfo->pRasterizationState->depthBiasClamp; |
| 1363 | dynamic->depth_bias.slope = |
| 1364 | pCreateInfo->pRasterizationState->depthBiasSlopeFactor; |
| 1365 | } |
| 1366 | |
Darren Salt | 9b12151 | 2016-10-16 20:32:19 +0100 | [diff] [blame] | 1367 | /* Section 9.2 of the Vulkan 1.0.15 spec says: |
| 1368 | * |
| 1369 | * pColorBlendState is [...] NULL if the pipeline has rasterization |
| 1370 | * disabled or if the subpass of the render pass the pipeline is |
| 1371 | * created against does not use any color attachments. |
| 1372 | */ |
| 1373 | bool uses_color_att = false; |
| 1374 | for (unsigned i = 0; i < subpass->color_count; ++i) { |
| 1375 | if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) { |
| 1376 | uses_color_att = true; |
| 1377 | break; |
| 1378 | } |
| 1379 | } |
| 1380 | |
| 1381 | if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) { |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1382 | assert(pCreateInfo->pColorBlendState); |
| 1383 | typed_memcpy(dynamic->blend_constants, |
| 1384 | pCreateInfo->pColorBlendState->blendConstants, 4); |
| 1385 | } |
| 1386 | |
| 1387 | /* If there is no depthstencil attachment, then don't read |
| 1388 | * pDepthStencilState. The Vulkan spec states that pDepthStencilState may |
| 1389 | * be NULL in this case. Even if pDepthStencilState is non-NULL, there is |
| 1390 | * no need to override the depthstencil defaults in |
| 1391 | * radv_pipeline::dynamic_state when there is no depthstencil attachment. |
| 1392 | * |
Darren Salt | 9b12151 | 2016-10-16 20:32:19 +0100 | [diff] [blame] | 1393 | * Section 9.2 of the Vulkan 1.0.15 spec says: |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1394 | * |
Darren Salt | 9b12151 | 2016-10-16 20:32:19 +0100 | [diff] [blame] | 1395 | * pDepthStencilState is [...] NULL if the pipeline has rasterization |
| 1396 | * disabled or if the subpass of the render pass the pipeline is created |
| 1397 | * against does not use a depth/stencil attachment. |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1398 | */ |
Darren Salt | 9b12151 | 2016-10-16 20:32:19 +0100 | [diff] [blame] | 1399 | if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable && |
| 1400 | subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) { |
| 1401 | assert(pCreateInfo->pDepthStencilState); |
| 1402 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1403 | if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) { |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1404 | dynamic->depth_bounds.min = |
| 1405 | pCreateInfo->pDepthStencilState->minDepthBounds; |
| 1406 | dynamic->depth_bounds.max = |
| 1407 | pCreateInfo->pDepthStencilState->maxDepthBounds; |
| 1408 | } |
| 1409 | |
| 1410 | if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) { |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1411 | dynamic->stencil_compare_mask.front = |
| 1412 | pCreateInfo->pDepthStencilState->front.compareMask; |
| 1413 | dynamic->stencil_compare_mask.back = |
| 1414 | pCreateInfo->pDepthStencilState->back.compareMask; |
| 1415 | } |
| 1416 | |
| 1417 | if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) { |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1418 | dynamic->stencil_write_mask.front = |
| 1419 | pCreateInfo->pDepthStencilState->front.writeMask; |
| 1420 | dynamic->stencil_write_mask.back = |
| 1421 | pCreateInfo->pDepthStencilState->back.writeMask; |
| 1422 | } |
| 1423 | |
| 1424 | if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) { |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1425 | dynamic->stencil_reference.front = |
| 1426 | pCreateInfo->pDepthStencilState->front.reference; |
| 1427 | dynamic->stencil_reference.back = |
| 1428 | pCreateInfo->pDepthStencilState->back.reference; |
| 1429 | } |
| 1430 | } |
| 1431 | |
| 1432 | pipeline->dynamic_state_mask = states; |
| 1433 | } |
| 1434 | |
| 1435 | static union ac_shader_variant_key |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 1436 | radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es) |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1437 | { |
| 1438 | union ac_shader_variant_key key; |
| 1439 | const VkPipelineVertexInputStateCreateInfo *input_state = |
| 1440 | pCreateInfo->pVertexInputState; |
| 1441 | |
| 1442 | memset(&key, 0, sizeof(key)); |
| 1443 | key.vs.instance_rate_inputs = 0; |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 1444 | key.vs.as_es = as_es; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1445 | |
| 1446 | for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) { |
| 1447 | unsigned binding; |
| 1448 | binding = input_state->pVertexAttributeDescriptions[i].binding; |
| 1449 | if (input_state->pVertexBindingDescriptions[binding].inputRate) |
| 1450 | key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location; |
| 1451 | } |
| 1452 | return key; |
| 1453 | } |
| 1454 | |
Dave Airlie | 8f41fe4 | 2017-01-20 10:21:19 +1000 | [diff] [blame] | 1455 | static void |
| 1456 | calculate_gs_ring_sizes(struct radv_pipeline *pipeline) |
| 1457 | { |
| 1458 | struct radv_device *device = pipeline->device; |
| 1459 | unsigned num_se = device->physical_device->rad_info.max_se; |
| 1460 | unsigned wave_size = 64; |
| 1461 | unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */ |
| 1462 | unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */ |
| 1463 | unsigned alignment = 256 * num_se; |
| 1464 | /* The maximum size is 63.999 MB per SE. */ |
| 1465 | unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; |
| 1466 | |
| 1467 | struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; |
| 1468 | struct ac_shader_variant_info *es_info = &pipeline->shaders[MESA_SHADER_VERTEX]->info; |
| 1469 | /* Calculate the minimum size. */ |
| 1470 | unsigned min_esgs_ring_size = align(es_info->vs.esgs_itemsize * gs_vertex_reuse * |
| 1471 | wave_size, alignment); |
| 1472 | /* These are recommended sizes, not minimum sizes. */ |
| 1473 | unsigned esgs_ring_size = max_gs_waves * 2 * wave_size * |
| 1474 | es_info->vs.esgs_itemsize * gs_info->gs.vertices_in; |
| 1475 | unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * |
| 1476 | gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1); |
| 1477 | |
| 1478 | min_esgs_ring_size = align(min_esgs_ring_size, alignment); |
| 1479 | esgs_ring_size = align(esgs_ring_size, alignment); |
| 1480 | gsvs_ring_size = align(gsvs_ring_size, alignment); |
| 1481 | |
| 1482 | pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); |
| 1483 | pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size); |
| 1484 | } |
| 1485 | |
Dave Airlie | 3360dbe | 2017-02-13 07:30:29 +0000 | [diff] [blame] | 1486 | static const struct radv_prim_vertex_count prim_size_table[] = { |
| 1487 | [V_008958_DI_PT_NONE] = {0, 0}, |
| 1488 | [V_008958_DI_PT_POINTLIST] = {1, 1}, |
| 1489 | [V_008958_DI_PT_LINELIST] = {2, 2}, |
| 1490 | [V_008958_DI_PT_LINESTRIP] = {2, 1}, |
| 1491 | [V_008958_DI_PT_TRILIST] = {3, 3}, |
| 1492 | [V_008958_DI_PT_TRIFAN] = {3, 1}, |
| 1493 | [V_008958_DI_PT_TRISTRIP] = {3, 1}, |
| 1494 | [V_008958_DI_PT_LINELIST_ADJ] = {4, 4}, |
| 1495 | [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1}, |
| 1496 | [V_008958_DI_PT_TRILIST_ADJ] = {6, 6}, |
| 1497 | [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2}, |
| 1498 | [V_008958_DI_PT_RECTLIST] = {3, 3}, |
| 1499 | [V_008958_DI_PT_LINELOOP] = {2, 1}, |
| 1500 | [V_008958_DI_PT_POLYGON] = {3, 1}, |
| 1501 | [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0}, |
| 1502 | }; |
| 1503 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1504 | VkResult |
| 1505 | radv_pipeline_init(struct radv_pipeline *pipeline, |
| 1506 | struct radv_device *device, |
| 1507 | struct radv_pipeline_cache *cache, |
| 1508 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 1509 | const struct radv_graphics_pipeline_create_info *extra, |
| 1510 | const VkAllocationCallbacks *alloc) |
| 1511 | { |
| 1512 | struct radv_shader_module fs_m = {0}; |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 1513 | VkResult result; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1514 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1515 | if (alloc == NULL) |
| 1516 | alloc = &device->alloc; |
| 1517 | |
| 1518 | pipeline->device = device; |
| 1519 | pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); |
| 1520 | |
| 1521 | radv_pipeline_init_dynamic_state(pipeline, pCreateInfo); |
| 1522 | const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, }; |
| 1523 | struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, }; |
| 1524 | for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { |
| 1525 | gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1; |
| 1526 | pStages[stage] = &pCreateInfo->pStages[i]; |
| 1527 | modules[stage] = radv_shader_module_from_handle(pStages[stage]->module); |
| 1528 | } |
| 1529 | |
| 1530 | radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra); |
| 1531 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1532 | if (modules[MESA_SHADER_VERTEX]) { |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 1533 | bool as_es = modules[MESA_SHADER_GEOMETRY] != NULL; |
| 1534 | union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1535 | |
| 1536 | pipeline->shaders[MESA_SHADER_VERTEX] = |
| 1537 | radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX], |
| 1538 | pStages[MESA_SHADER_VERTEX]->pName, |
| 1539 | MESA_SHADER_VERTEX, |
| 1540 | pStages[MESA_SHADER_VERTEX]->pSpecializationInfo, |
Bas Nieuwenhuizen | 8bc39e2 | 2017-01-02 18:57:02 +0100 | [diff] [blame] | 1541 | pipeline->layout, &key); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1542 | |
| 1543 | pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX); |
| 1544 | } |
| 1545 | |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 1546 | if (modules[MESA_SHADER_GEOMETRY]) { |
| 1547 | union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false); |
| 1548 | |
| 1549 | pipeline->shaders[MESA_SHADER_GEOMETRY] = |
| 1550 | radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY], |
| 1551 | pStages[MESA_SHADER_GEOMETRY]->pName, |
| 1552 | MESA_SHADER_GEOMETRY, |
| 1553 | pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo, |
| 1554 | pipeline->layout, &key); |
| 1555 | |
| 1556 | pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY); |
Dave Airlie | 8f41fe4 | 2017-01-20 10:21:19 +1000 | [diff] [blame] | 1557 | calculate_gs_ring_sizes(pipeline); |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 1558 | } |
| 1559 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1560 | if (!modules[MESA_SHADER_FRAGMENT]) { |
| 1561 | nir_builder fs_b; |
| 1562 | nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL); |
Timothy Arceri | e1af20f | 2016-10-13 11:41:23 +1100 | [diff] [blame] | 1563 | fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs"); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1564 | fs_m.nir = fs_b.shader; |
| 1565 | modules[MESA_SHADER_FRAGMENT] = &fs_m; |
| 1566 | } |
| 1567 | |
| 1568 | if (modules[MESA_SHADER_FRAGMENT]) { |
| 1569 | union ac_shader_variant_key key; |
| 1570 | key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format; |
| 1571 | key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo); |
| 1572 | |
| 1573 | const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT]; |
| 1574 | |
| 1575 | pipeline->shaders[MESA_SHADER_FRAGMENT] = |
| 1576 | radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT], |
| 1577 | stage ? stage->pName : "main", |
| 1578 | MESA_SHADER_FRAGMENT, |
| 1579 | stage ? stage->pSpecializationInfo : NULL, |
Bas Nieuwenhuizen | 8bc39e2 | 2017-01-02 18:57:02 +0100 | [diff] [blame] | 1580 | pipeline->layout, &key); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1581 | pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT); |
| 1582 | } |
| 1583 | |
| 1584 | if (fs_m.nir) |
| 1585 | ralloc_free(fs_m.nir); |
| 1586 | |
| 1587 | radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra); |
| 1588 | radv_pipeline_init_raster_state(pipeline, pCreateInfo); |
| 1589 | radv_pipeline_init_multisample_state(pipeline, pCreateInfo); |
| 1590 | pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology); |
Dave Airlie | 99936d3 | 2017-01-20 09:55:37 +1000 | [diff] [blame] | 1591 | if (radv_pipeline_has_gs(pipeline)) { |
| 1592 | pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); |
| 1593 | } else { |
| 1594 | pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology); |
| 1595 | } |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1596 | if (extra && extra->use_rectlist) { |
| 1597 | pipeline->graphics.prim = V_008958_DI_PT_RECTLIST; |
| 1598 | pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; |
| 1599 | } |
| 1600 | pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable; |
Dave Airlie | 3360dbe | 2017-02-13 07:30:29 +0000 | [diff] [blame] | 1601 | /* prim vertex count will need TESS changes */ |
| 1602 | pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim]; |
Dave Airlie | b640dfc | 2017-03-28 05:45:00 +1000 | [diff] [blame^] | 1603 | |
| 1604 | /* Ensure that some export memory is always allocated, for two reasons: |
| 1605 | * |
| 1606 | * 1) Correctness: The hardware ignores the EXEC mask if no export |
| 1607 | * memory is allocated, so KILL and alpha test do not work correctly |
| 1608 | * without this. |
| 1609 | * 2) Performance: Every shader needs at least a NULL export, even when |
| 1610 | * it writes no color/depth output. The NULL export instruction |
| 1611 | * stalls without this setting. |
| 1612 | * |
| 1613 | * Don't add this to CB_SHADER_MASK. |
| 1614 | */ |
| 1615 | if (!pipeline->graphics.blend.spi_shader_col_format) { |
| 1616 | struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; |
| 1617 | if (!ps->info.fs.writes_z && |
| 1618 | !ps->info.fs.writes_stencil && |
| 1619 | !ps->info.fs.writes_sample_mask) |
| 1620 | pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; |
| 1621 | } |
Dave Airlie | 3360dbe | 2017-02-13 07:30:29 +0000 | [diff] [blame] | 1622 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1623 | const VkPipelineVertexInputStateCreateInfo *vi_info = |
| 1624 | pCreateInfo->pVertexInputState; |
| 1625 | for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) { |
| 1626 | const VkVertexInputAttributeDescription *desc = |
| 1627 | &vi_info->pVertexAttributeDescriptions[i]; |
| 1628 | unsigned loc = desc->location; |
| 1629 | const struct vk_format_description *format_desc; |
| 1630 | int first_non_void; |
| 1631 | uint32_t num_format, data_format; |
| 1632 | format_desc = vk_format_description(desc->format); |
| 1633 | first_non_void = vk_format_get_first_non_void_channel(desc->format); |
| 1634 | |
| 1635 | num_format = radv_translate_buffer_numformat(format_desc, first_non_void); |
| 1636 | data_format = radv_translate_buffer_dataformat(format_desc, first_non_void); |
| 1637 | |
| 1638 | pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) | |
| 1639 | S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) | |
| 1640 | S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) | |
| 1641 | S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) | |
| 1642 | S_008F0C_NUM_FORMAT(num_format) | |
| 1643 | S_008F0C_DATA_FORMAT(data_format); |
| 1644 | pipeline->va_format_size[loc] = format_desc->block.bits / 8; |
| 1645 | pipeline->va_offset[loc] = desc->offset; |
| 1646 | pipeline->va_binding[loc] = desc->binding; |
| 1647 | pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1); |
| 1648 | } |
| 1649 | |
| 1650 | for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) { |
| 1651 | const VkVertexInputBindingDescription *desc = |
| 1652 | &vi_info->pVertexBindingDescriptions[i]; |
| 1653 | |
| 1654 | pipeline->binding_stride[desc->binding] = desc->stride; |
| 1655 | } |
| 1656 | |
Bas Nieuwenhuizen | 8bc39e2 | 2017-01-02 18:57:02 +0100 | [diff] [blame] | 1657 | if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) { |
Dave Airlie | f395e34 | 2016-11-22 04:17:49 +0000 | [diff] [blame] | 1658 | radv_dump_pipeline_stats(device, pipeline); |
| 1659 | } |
| 1660 | |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 1661 | result = radv_pipeline_scratch_init(device, pipeline); |
| 1662 | return result; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1663 | } |
| 1664 | |
| 1665 | VkResult |
| 1666 | radv_graphics_pipeline_create( |
| 1667 | VkDevice _device, |
| 1668 | VkPipelineCache _cache, |
| 1669 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 1670 | const struct radv_graphics_pipeline_create_info *extra, |
| 1671 | const VkAllocationCallbacks *pAllocator, |
| 1672 | VkPipeline *pPipeline) |
| 1673 | { |
| 1674 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 1675 | RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache); |
| 1676 | struct radv_pipeline *pipeline; |
| 1677 | VkResult result; |
| 1678 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame] | 1679 | pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1680 | VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); |
| 1681 | if (pipeline == NULL) |
| 1682 | return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); |
| 1683 | |
| 1684 | memset(pipeline, 0, sizeof(*pipeline)); |
| 1685 | result = radv_pipeline_init(pipeline, device, cache, |
| 1686 | pCreateInfo, extra, pAllocator); |
| 1687 | if (result != VK_SUCCESS) { |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 1688 | radv_pipeline_destroy(device, pipeline, pAllocator); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1689 | return result; |
| 1690 | } |
| 1691 | |
| 1692 | *pPipeline = radv_pipeline_to_handle(pipeline); |
| 1693 | |
| 1694 | return VK_SUCCESS; |
| 1695 | } |
| 1696 | |
| 1697 | VkResult radv_CreateGraphicsPipelines( |
| 1698 | VkDevice _device, |
| 1699 | VkPipelineCache pipelineCache, |
| 1700 | uint32_t count, |
| 1701 | const VkGraphicsPipelineCreateInfo* pCreateInfos, |
| 1702 | const VkAllocationCallbacks* pAllocator, |
| 1703 | VkPipeline* pPipelines) |
| 1704 | { |
| 1705 | VkResult result = VK_SUCCESS; |
| 1706 | unsigned i = 0; |
| 1707 | |
| 1708 | for (; i < count; i++) { |
Bas Nieuwenhuizen | b2b4f72 | 2016-12-16 23:10:31 +0100 | [diff] [blame] | 1709 | VkResult r; |
| 1710 | r = radv_graphics_pipeline_create(_device, |
| 1711 | pipelineCache, |
| 1712 | &pCreateInfos[i], |
| 1713 | NULL, pAllocator, &pPipelines[i]); |
| 1714 | if (r != VK_SUCCESS) { |
| 1715 | result = r; |
| 1716 | pPipelines[i] = VK_NULL_HANDLE; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1717 | } |
| 1718 | } |
| 1719 | |
Bas Nieuwenhuizen | b2b4f72 | 2016-12-16 23:10:31 +0100 | [diff] [blame] | 1720 | return result; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1721 | } |
| 1722 | |
| 1723 | static VkResult radv_compute_pipeline_create( |
| 1724 | VkDevice _device, |
| 1725 | VkPipelineCache _cache, |
| 1726 | const VkComputePipelineCreateInfo* pCreateInfo, |
| 1727 | const VkAllocationCallbacks* pAllocator, |
| 1728 | VkPipeline* pPipeline) |
| 1729 | { |
| 1730 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 1731 | RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache); |
| 1732 | RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module); |
| 1733 | struct radv_pipeline *pipeline; |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 1734 | VkResult result; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1735 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame] | 1736 | pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1737 | VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); |
| 1738 | if (pipeline == NULL) |
| 1739 | return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); |
| 1740 | |
| 1741 | memset(pipeline, 0, sizeof(*pipeline)); |
| 1742 | pipeline->device = device; |
| 1743 | pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); |
| 1744 | |
| 1745 | pipeline->shaders[MESA_SHADER_COMPUTE] = |
| 1746 | radv_pipeline_compile(pipeline, cache, module, |
| 1747 | pCreateInfo->stage.pName, |
| 1748 | MESA_SHADER_COMPUTE, |
| 1749 | pCreateInfo->stage.pSpecializationInfo, |
Bas Nieuwenhuizen | 8bc39e2 | 2017-01-02 18:57:02 +0100 | [diff] [blame] | 1750 | pipeline->layout, NULL); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1751 | |
Bas Nieuwenhuizen | ccff93e | 2017-01-29 15:20:03 +0100 | [diff] [blame] | 1752 | |
| 1753 | result = radv_pipeline_scratch_init(device, pipeline); |
| 1754 | if (result != VK_SUCCESS) { |
| 1755 | radv_pipeline_destroy(device, pipeline, pAllocator); |
| 1756 | return result; |
| 1757 | } |
| 1758 | |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1759 | *pPipeline = radv_pipeline_to_handle(pipeline); |
Dave Airlie | f395e34 | 2016-11-22 04:17:49 +0000 | [diff] [blame] | 1760 | |
Bas Nieuwenhuizen | 8bc39e2 | 2017-01-02 18:57:02 +0100 | [diff] [blame] | 1761 | if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) { |
Dave Airlie | f395e34 | 2016-11-22 04:17:49 +0000 | [diff] [blame] | 1762 | radv_dump_pipeline_stats(device, pipeline); |
| 1763 | } |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1764 | return VK_SUCCESS; |
| 1765 | } |
| 1766 | VkResult radv_CreateComputePipelines( |
| 1767 | VkDevice _device, |
| 1768 | VkPipelineCache pipelineCache, |
| 1769 | uint32_t count, |
| 1770 | const VkComputePipelineCreateInfo* pCreateInfos, |
| 1771 | const VkAllocationCallbacks* pAllocator, |
| 1772 | VkPipeline* pPipelines) |
| 1773 | { |
| 1774 | VkResult result = VK_SUCCESS; |
| 1775 | |
| 1776 | unsigned i = 0; |
| 1777 | for (; i < count; i++) { |
Bas Nieuwenhuizen | b2b4f72 | 2016-12-16 23:10:31 +0100 | [diff] [blame] | 1778 | VkResult r; |
| 1779 | r = radv_compute_pipeline_create(_device, pipelineCache, |
| 1780 | &pCreateInfos[i], |
| 1781 | pAllocator, &pPipelines[i]); |
| 1782 | if (r != VK_SUCCESS) { |
| 1783 | result = r; |
| 1784 | pPipelines[i] = VK_NULL_HANDLE; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1785 | } |
| 1786 | } |
| 1787 | |
Bas Nieuwenhuizen | b2b4f72 | 2016-12-16 23:10:31 +0100 | [diff] [blame] | 1788 | return result; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1789 | } |