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JB Tsai0c16a0f2015-03-19 14:30:31 +08001/*
2 * Copyright 2015 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_MEDIATEK
JB Tsai0c16a0f2015-03-19 14:30:31 +08008
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -08009// clang-format off
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -070010#include <errno.h>
Luigi Santivetti500928f2018-08-28 10:09:20 +010011#include <fcntl.h>
12#include <poll.h>
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070013#include <stdio.h>
JB Tsai0c16a0f2015-03-19 14:30:31 +080014#include <string.h>
Gurchetan Singhef920532016-08-12 16:38:25 -070015#include <sys/mman.h>
Luigi Santivetti500928f2018-08-28 10:09:20 +010016#include <unistd.h>
JB Tsai0c16a0f2015-03-19 14:30:31 +080017#include <xf86drm.h>
18#include <mediatek_drm.h>
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080019// clang-format on
Gurchetan Singhef920532016-08-12 16:38:25 -070020
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070021#include "drv_priv.h"
JB Tsai0c16a0f2015-03-19 14:30:31 +080022#include "helpers.h"
Gurchetan Singh179687e2016-10-28 10:07:35 -070023#include "util.h"
24
Miguel Casasdea0ccb2018-07-02 09:40:25 -040025#define TILE_TYPE_LINEAR 0
26
Gurchetan Singh469a3aa2017-08-03 18:17:34 -070027struct mediatek_private_map_data {
28 void *cached_addr;
29 void *gem_addr;
Luigi Santivetti500928f2018-08-28 10:09:20 +010030 int prime_fd;
Gurchetan Singh469a3aa2017-08-03 18:17:34 -070031};
32
Gurchetan Singh767c5382018-05-05 00:42:12 +000033static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
Gurchetan Singh71bc6652018-09-17 17:42:05 -070034 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
35 DRM_FORMAT_XRGB8888 };
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070036
Nick Fan01c40142018-10-08 11:53:26 +080037#ifdef MTK_MT8183
Gurchetan Singh39490e92019-05-28 17:49:09 -070038static const uint32_t texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV21,
39 DRM_FORMAT_NV12, DRM_FORMAT_YUYV,
40 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
Nick Fan01c40142018-10-08 11:53:26 +080041#else
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070042static const uint32_t texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_YVU420,
Gurchetan Singh39490e92019-05-28 17:49:09 -070043 DRM_FORMAT_YVU420_ANDROID };
Nick Fan01c40142018-10-08 11:53:26 +080044#endif
Gurchetan Singh179687e2016-10-28 10:07:35 -070045
46static int mediatek_init(struct driver *drv)
47{
Miguel Casasdea0ccb2018-07-02 09:40:25 -040048 struct format_metadata metadata;
49
Gurchetan Singhd3001452017-11-03 17:18:36 -070050 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
51 &LINEAR_METADATA, BO_USE_RENDER_MASK);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070052
Gurchetan Singhd3001452017-11-03 17:18:36 -070053 drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
54 &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070055
Gurchetan Singh71bc6652018-09-17 17:42:05 -070056 /* Android CTS tests require this. */
57 drv_add_combination(drv, DRM_FORMAT_BGR888, &LINEAR_METADATA, BO_USE_SW_MASK);
58
Miguel Casasdea0ccb2018-07-02 09:40:25 -040059 /* Support BO_USE_HW_VIDEO_DECODER for protected content minigbm allocations. */
60 metadata.tiling = TILE_TYPE_LINEAR;
61 metadata.priority = 1;
62 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
63 drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_DECODER);
64 drv_modify_combination(drv, DRM_FORMAT_YVU420_ANDROID, &metadata, BO_USE_HW_VIDEO_DECODER);
65
Nick Fan01c40142018-10-08 11:53:26 +080066#ifdef MTK_MT8183
67 /* Only for MT8183 Camera subsystem */
68 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
69 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
70 drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata,
71 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
72 drv_modify_combination(drv, DRM_FORMAT_YUYV, &metadata,
73 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
74 drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata,
75 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
76 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
Gurchetan Singh39490e92019-05-28 17:49:09 -070077 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
Nick Fan01c40142018-10-08 11:53:26 +080078#endif
79
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070080 return drv_modify_linear_combinations(drv);
Gurchetan Singh179687e2016-10-28 10:07:35 -070081}
JB Tsai0c16a0f2015-03-19 14:30:31 +080082
Fritz Koenig1b9b5b92019-03-19 13:25:45 -070083static int mediatek_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
84 uint32_t format, const uint64_t *modifiers,
85 uint32_t count)
JB Tsai0c16a0f2015-03-19 14:30:31 +080086{
JB Tsai0c16a0f2015-03-19 14:30:31 +080087 int ret;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070088 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070089 uint32_t stride;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070090 struct drm_mtk_gem_create gem_create;
JB Tsai0c16a0f2015-03-19 14:30:31 +080091
Fritz Koenig1b9b5b92019-03-19 13:25:45 -070092 if (!drv_has_modifier(modifiers, count, DRM_FORMAT_MOD_LINEAR)) {
93 errno = EINVAL;
94 drv_log("no usable modifier found\n");
95 return -EINVAL;
96 }
97
Gurchetan Singh6ea14ba2017-02-08 15:09:13 -080098 /*
99 * Since the ARM L1 cache line size is 64 bytes, align to that as a
100 * performance optimization.
101 */
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700102 stride = drv_stride_from_format(format, width, 0);
103 stride = ALIGN(stride, 64);
104 drv_bo_from_format(bo, stride, height, format);
Yuly Novikov96c7a3b2015-12-08 22:48:29 -0500105
JB Tsai0c16a0f2015-03-19 14:30:31 +0800106 memset(&gem_create, 0, sizeof(gem_create));
Gurchetan Singha40ca9e2016-08-29 19:51:45 -0700107 gem_create.size = bo->total_size;
JB Tsai0c16a0f2015-03-19 14:30:31 +0800108
Gurchetan Singh46faf6b2016-08-05 14:40:07 -0700109 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_CREATE, &gem_create);
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -0700110 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700111 drv_log("DRM_IOCTL_MTK_GEM_CREATE failed (size=%llu)\n", gem_create.size);
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700112 return -errno;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -0700113 }
JB Tsai0c16a0f2015-03-19 14:30:31 +0800114
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700115 for (plane = 0; plane < bo->num_planes; plane++)
116 bo->handles[plane].u32 = gem_create.handle;
JB Tsai0c16a0f2015-03-19 14:30:31 +0800117
118 return 0;
119}
120
Fritz Koenig1b9b5b92019-03-19 13:25:45 -0700121static int mediatek_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
122 uint64_t use_flags)
123{
124 uint64_t modifiers[] = { DRM_FORMAT_MOD_LINEAR };
125 return mediatek_bo_create_with_modifiers(bo, width, height, format, modifiers,
126 ARRAY_SIZE(modifiers));
127}
128
Gurchetan Singhee43c302017-11-14 18:20:27 -0800129static void *mediatek_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
Gurchetan Singhef920532016-08-12 16:38:25 -0700130{
Luigi Santivetti500928f2018-08-28 10:09:20 +0100131 int ret, prime_fd;
Gurchetan Singhef920532016-08-12 16:38:25 -0700132 struct drm_mtk_gem_map_off gem_map;
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700133 struct mediatek_private_map_data *priv;
Gurchetan Singhef920532016-08-12 16:38:25 -0700134
135 memset(&gem_map, 0, sizeof(gem_map));
136 gem_map.handle = bo->handles[0].u32;
137
138 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_MAP_OFFSET, &gem_map);
139 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700140 drv_log("DRM_IOCTL_MTK_GEM_MAP_OFFSET failed\n");
Gurchetan Singhef920532016-08-12 16:38:25 -0700141 return MAP_FAILED;
142 }
143
Luigi Santivetti500928f2018-08-28 10:09:20 +0100144 ret = drmPrimeHandleToFD(bo->drv->fd, gem_map.handle, DRM_CLOEXEC, &prime_fd);
145 if (ret) {
146 drv_log("Failed to get a prime fd\n");
147 return MAP_FAILED;
148 }
149
Gurchetan Singhcfb88762017-09-28 17:14:50 -0700150 void *addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
151 gem_map.offset);
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700152
Gurchetan Singhee43c302017-11-14 18:20:27 -0800153 vma->length = bo->total_size;
Gurchetan Singh1a31e602016-10-06 10:58:00 -0700154
Luigi Santivetti500928f2018-08-28 10:09:20 +0100155 priv = calloc(1, sizeof(*priv));
156 priv->prime_fd = prime_fd;
157 vma->priv = priv;
158
Gurchetan Singha1892b22017-09-28 16:40:52 -0700159 if (bo->use_flags & BO_USE_RENDERSCRIPT) {
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700160 priv->cached_addr = calloc(1, bo->total_size);
161 priv->gem_addr = addr;
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700162 addr = priv->cached_addr;
163 }
164
165 return addr;
166}
167
Gurchetan Singhee43c302017-11-14 18:20:27 -0800168static int mediatek_bo_unmap(struct bo *bo, struct vma *vma)
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700169{
Gurchetan Singhee43c302017-11-14 18:20:27 -0800170 if (vma->priv) {
171 struct mediatek_private_map_data *priv = vma->priv;
Luigi Santivettia72f4422018-09-12 16:28:21 +0100172
173 if (priv->cached_addr) {
174 vma->addr = priv->gem_addr;
175 free(priv->cached_addr);
176 }
177
Luigi Santivetti500928f2018-08-28 10:09:20 +0100178 close(priv->prime_fd);
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700179 free(priv);
Gurchetan Singhee43c302017-11-14 18:20:27 -0800180 vma->priv = NULL;
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700181 }
182
Gurchetan Singhee43c302017-11-14 18:20:27 -0800183 return munmap(vma->addr, vma->length);
Gurchetan Singhef920532016-08-12 16:38:25 -0700184}
185
Gurchetan Singhef262d82017-11-28 16:56:17 -0800186static int mediatek_bo_invalidate(struct bo *bo, struct mapping *mapping)
187{
Luigi Santivetti500928f2018-08-28 10:09:20 +0100188 struct mediatek_private_map_data *priv = mapping->vma->priv;
189
190 if (priv) {
191 struct pollfd fds = {
192 .fd = priv->prime_fd,
193 };
194
195 if (mapping->vma->map_flags & BO_MAP_WRITE)
196 fds.events |= POLLOUT;
197
198 if (mapping->vma->map_flags & BO_MAP_READ)
199 fds.events |= POLLIN;
200
201 poll(&fds, 1, -1);
202 if (fds.revents != fds.events)
203 drv_log("poll prime_fd failed\n");
204
205 if (priv->cached_addr)
206 memcpy(priv->cached_addr, priv->gem_addr, bo->total_size);
Gurchetan Singhef262d82017-11-28 16:56:17 -0800207 }
208
209 return 0;
210}
211
Gurchetan Singh47e629b2017-11-02 14:07:18 -0700212static int mediatek_bo_flush(struct bo *bo, struct mapping *mapping)
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700213{
Gurchetan Singh47e629b2017-11-02 14:07:18 -0700214 struct mediatek_private_map_data *priv = mapping->vma->priv;
Luigi Santivetti500928f2018-08-28 10:09:20 +0100215 if (priv && priv->cached_addr && (mapping->vma->map_flags & BO_MAP_WRITE))
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700216 memcpy(priv->gem_addr, priv->cached_addr, bo->total_size);
217
218 return 0;
219}
220
Gurchetan Singh0d44d482019-06-04 19:39:51 -0700221static uint32_t mediatek_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700222{
223 switch (format) {
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800224 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Nick Fan01c40142018-10-08 11:53:26 +0800225#ifdef MTK_MT8183
226 /* Only for MT8183 Camera subsystem requires NV12. */
227 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
228 return DRM_FORMAT_NV12;
229#endif
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700230 /*HACK: See b/28671744 */
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800231 return DRM_FORMAT_XBGR8888;
232 case DRM_FORMAT_FLEX_YCbCr_420_888:
Nick Fan01c40142018-10-08 11:53:26 +0800233#ifdef MTK_MT8183
234 /* Only for MT8183 Camera subsystem requires NV12 */
235 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
Gurchetan Singh39490e92019-05-28 17:49:09 -0700236 return DRM_FORMAT_NV12;
Nick Fan01c40142018-10-08 11:53:26 +0800237#endif
Owen Linbbb69fd2017-06-05 14:33:08 +0800238 return DRM_FORMAT_YVU420;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700239 default:
240 return format;
241 }
242}
243
Gurchetan Singh3e9d3832017-10-31 10:36:25 -0700244const struct backend backend_mediatek = {
JB Tsai0c16a0f2015-03-19 14:30:31 +0800245 .name = "mediatek",
Gurchetan Singh179687e2016-10-28 10:07:35 -0700246 .init = mediatek_init,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700247 .bo_create = mediatek_bo_create,
Fritz Koenig1b9b5b92019-03-19 13:25:45 -0700248 .bo_create_with_modifiers = mediatek_bo_create_with_modifiers,
Gurchetan Singh46faf6b2016-08-05 14:40:07 -0700249 .bo_destroy = drv_gem_bo_destroy,
Gurchetan Singh71611d62017-01-03 16:49:56 -0800250 .bo_import = drv_prime_bo_import,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700251 .bo_map = mediatek_bo_map,
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700252 .bo_unmap = mediatek_bo_unmap,
Gurchetan Singhef262d82017-11-28 16:56:17 -0800253 .bo_invalidate = mediatek_bo_invalidate,
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700254 .bo_flush = mediatek_bo_flush,
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700255 .resolve_format = mediatek_resolve_format,
JB Tsai0c16a0f2015-03-19 14:30:31 +0800256};
257
258#endif