Blame - arch/powerpc/include/asm/fsl_secure_boot.h - platform/external/u-boot

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Ruchika Gupta	7065b7d	2010-12-15 17:02:08 +0000	[diff] [blame]	1	/*
				2	* Copyright 2010-2011 Freescale Semiconductor, Inc.
				3	*
Wolfgang Denk	1a45966	2013-07-08 09:37:19 +0200	[diff] [blame]	4	* SPDX-License-Identifier: GPL-2.0+
Ruchika Gupta	7065b7d	2010-12-15 17:02:08 +0000	[diff] [blame]	5	*/
				6
				7	#ifndef __FSL_SECURE_BOOT_H
				8	#define __FSL_SECURE_BOOT_H
gaurav rana	e04916a	2015-02-27 09:46:17 +0530	[diff] [blame]	9	#include <asm/config_mpc85xx.h>
				10
				11	#ifdef CONFIG_SECURE_BOOT
				12	#define CONFIG_CMD_ESBC_VALIDATE
				13	#define CONFIG_FSL_SEC_MON
				14	#define CONFIG_SHA_PROG_HW_ACCEL
				15	#define CONFIG_DM
				16	#define CONFIG_RSA
				17	#define CONFIG_RSA_FREESCALE_EXP
				18	#ifndef CONFIG_FSL_CAAM
				19	#define CONFIG_FSL_CAAM
				20	#endif
				21	#endif
Ruchika Gupta	7065b7d	2010-12-15 17:02:08 +0000	[diff] [blame]	22
Po Liu	0d2cff2	2013-08-21 14:20:21 +0800	[diff] [blame]	23	#ifdef CONFIG_SECURE_BOOT
Ruchika Gupta	7065b7d	2010-12-15 17:02:08 +0000	[diff] [blame]	24	#if defined(CONFIG_FSL_CORENET)
				25	#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
Aneesh Bansal	f978f7c	2014-03-12 00:07:27 +0530	[diff] [blame]	26	#elif defined(CONFIG_BSC9132QDS)
				27	#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
Aneesh Bansal	b3f0f63	2014-12-12 15:35:04 +0530	[diff] [blame]	28	#elif defined(CONFIG_C29XPCIE)
				29	#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
Ruchika Gupta	7065b7d	2010-12-15 17:02:08 +0000	[diff] [blame]	30	#else
				31	#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
				32	#endif
				33	#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
				34
Aneesh Bansal	ca4819d	2014-03-18 23:40:59 +0530	[diff] [blame]	35	#if defined(CONFIG_B4860QDS) \|\| \
				36	defined(CONFIG_T4240QDS) \|\| \
Aneesh Bansal	2d8db6d	2014-03-18 23:41:14 +0530	[diff] [blame]	37	defined(CONFIG_T2080QDS) \|\| \
Aneesh Bansal	e47c2a6	2014-04-22 15:17:06 +0530	[diff] [blame]	38	defined(CONFIG_T2080RDB) \|\| \
Aneesh Bansal	2d8db6d	2014-03-18 23:41:14 +0530	[diff] [blame]	39	defined(CONFIG_T1040QDS) \|\| \
gaurav rana	e622d9e	2015-03-26 15:52:47 +0530	[diff] [blame]	40	defined(CONFIG_T104xD4QDS) \|\| \
Shengzhou Liu	f605079	2014-11-24 17:11:54 +0800	[diff] [blame]	41	defined(CONFIG_T104xRDB) \|\| \
gaurav rana	e622d9e	2015-03-26 15:52:47 +0530	[diff] [blame]	42	defined(CONFIG_T104xD4RDB) \|\| \
Shengzhou Liu	f605079	2014-11-24 17:11:54 +0800	[diff] [blame]	43	defined(CONFIG_PPC_T1023) \|\| \
				44	defined(CONFIG_PPC_T1024)
Aneesh Bansal	fb4a240	2014-03-18 23:40:26 +0530	[diff] [blame]	45	#define CONFIG_SYS_CPC_REINIT_F
gaurav rana	e04916a	2015-02-27 09:46:17 +0530	[diff] [blame]	46	#define CONFIG_KEY_REVOCATION
Aneesh Bansal	fb4a240	2014-03-18 23:40:26 +0530	[diff] [blame]	47	#undef CONFIG_SYS_INIT_L3_ADDR
				48	#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
				49	#endif
				50
Aneesh Bansal	467a40d	2015-06-16 10:36:00 +0530	[diff] [blame]	51	#if defined(CONFIG_RAMBOOT_PBL)
				52	#undef CONFIG_SYS_INIT_L3_ADDR
				53	#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
				54	#endif
				55
gaurav rana	e04916a	2015-02-27 09:46:17 +0530	[diff] [blame]	56	#if defined(CONFIG_C29XPCIE)
				57	#define CONFIG_KEY_REVOCATION
				58	#endif
				59
				60	#if defined(CONFIG_PPC_P3041) \|\| \
				61	defined(CONFIG_PPC_P4080) \|\| \
				62	defined(CONFIG_PPC_P5020) \|\| \
				63	defined(CONFIG_PPC_P5040) \|\| \
				64	defined(CONFIG_PPC_P2041)
				65	#define CONFIG_FSL_TRUST_ARCH_v1
				66	#endif
				67
Aneesh Bansal	2ed948f	2015-07-31 14:10:03 +0530	[diff] [blame^]	68	#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
gaurav rana	e04916a	2015-02-27 09:46:17 +0530	[diff] [blame]	69	/* The key used for verification of next level images
				70	* is picked up from an Extension Table which has
				71	* been verified by the ISBC (Internal Secure boot Code)
Aneesh Bansal	2ed948f	2015-07-31 14:10:03 +0530	[diff] [blame^]	72	* in boot ROM of the SoC.
				73	* The feature is only applicable in case of NOR boot and is
				74	* not applicable in case of RAMBOOT (NAND, SD, SPI).
gaurav rana	e04916a	2015-02-27 09:46:17 +0530	[diff] [blame]	75	*/
				76	#define CONFIG_FSL_ISBC_KEY_EXT
				77	#endif
				78
gaurav rana	98cb0ef	2015-03-10 14:08:50 +0530	[diff] [blame]	79	#ifndef CONFIG_FIT_SIGNATURE
Aneesh Bansal	5050f6f	2015-06-16 10:36:43 +0530	[diff] [blame]	80	/* If Boot Script is not on NOR and is required to be copied on RAM */
				81	#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
				82	#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
				83	#define CONFIG_BS_HDR_ADDR_FLASH 0x00800000
				84	#define CONFIG_BS_HDR_SIZE 0x00002000
				85	#define CONFIG_BS_ADDR_RAM 0x00012000
				86	#define CONFIG_BS_ADDR_FLASH 0x00802000
				87	#define CONFIG_BS_SIZE 0x00001000
				88
				89	#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
				90	#else
				91
gaurav rana	98cb0ef	2015-03-10 14:08:50 +0530	[diff] [blame]	92	/* The bootscript header address is different for B4860 because the NOR
				93	* mapping is different on B4 due to reduced NOR size.
				94	*/
				95	#if defined(CONFIG_B4860QDS)
				96	#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
				97	#elif defined(CONFIG_FSL_CORENET)
				98	#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
				99	#elif defined(CONFIG_BSC9132QDS)
				100	#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
				101	#elif defined(CONFIG_C29XPCIE)
				102	#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
				103	#else
				104	#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
				105	#endif
				106
Aneesh Bansal	5050f6f	2015-06-16 10:36:43 +0530	[diff] [blame]	107	#endif
				108
gaurav rana	98cb0ef	2015-03-10 14:08:50 +0530	[diff] [blame]	109	#include <config_fsl_secboot.h>
				110	#endif
				111
Ruchika Gupta	7065b7d	2010-12-15 17:02:08 +0000	[diff] [blame]	112	#endif
Po Liu	0d2cff2	2013-08-21 14:20:21 +0800	[diff] [blame]	113	#endif