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Michal Simek76316a32007-03-11 13:42:58 +01001/*
Michal Simek188dc162008-03-28 11:53:02 +01002 * (C) Copyright 2007-2008 Michal Simek
Michal Simek76316a32007-03-11 13:42:58 +01003 *
Michal Simekcb1bc632007-09-24 00:30:42 +02004 * Michal SIMEK <monstr@monstr.eu>
Michal Simek76316a32007-03-11 13:42:58 +01005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
Michal Simek52a822e2008-12-19 13:14:05 +010028#include "../board/xilinx/microblaze-generic/xparameters.h"
Michal Simek76316a32007-03-11 13:42:58 +010029
30#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
Michal Simek1a50f1642007-05-08 14:52:52 +020031#define MICROBLAZE_V5 1
Michal Simek76316a32007-03-11 13:42:58 +010032
33/* uart */
Michal Simekaf7ae1a2008-03-28 12:13:03 +010034#ifdef XILINX_UARTLITE_BASEADDR
Michal Simek853643d2007-09-24 00:41:30 +020035#define CONFIG_XILINX_UARTLITE
Michal Simekaf7ae1a2008-03-28 12:13:03 +010036#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
37#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
Michal Simeke7d591e2008-11-24 11:43:00 +010039#elif XILINX_UART16550_BASEADDR
40#define CONFIG_SYS_NS16550 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_NS16550_SERIAL
Michal Simeke7d591e2008-11-24 11:43:00 +010042#define CONFIG_SYS_NS16550_REG_SIZE -4
Michal Simekaf7ae1a2008-03-28 12:13:03 +010043#define CONFIG_CONS_INDEX 1
Michal Simeke7d591e2008-11-24 11:43:00 +010044#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
Michal Simekaf7ae1a2008-03-28 12:13:03 +010046#define CONFIG_BAUDRATE 115200
Michal Simeke7d591e2008-11-24 11:43:00 +010047
48/* The following table includes the supported baudrates */
49#define CONFIG_SYS_BAUDRATE_TABLE \
50 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
51#else
52#error Undefined uart
Michal Simekaf7ae1a2008-03-28 12:13:03 +010053#endif
Michal Simek76316a32007-03-11 13:42:58 +010054
55/* setting reset address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056/*#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE*/
Michal Simek76316a32007-03-11 13:42:58 +010057
Michal Simek17980492007-03-26 01:39:07 +020058/* ethernet */
Michal Simeke5845e22008-03-28 11:04:01 +010059#ifdef XILINX_EMAC_BASEADDR
60#define CONFIG_XILINX_EMAC 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_ENET
Michal Simeke5845e22008-03-28 11:04:01 +010062#else
63#ifdef XILINX_EMACLITE_BASEADDR
64#define CONFIG_XILINX_EMACLITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_ENET
Michal Simeke5845e22008-03-28 11:04:01 +010066#endif
67#endif
68#undef ET_DEBUG
Michal Simek17980492007-03-26 01:39:07 +020069
Michal Simek76316a32007-03-11 13:42:58 +010070/* gpio */
Michal Simek4c6a6f02008-03-28 11:22:48 +010071#ifdef XILINX_GPIO_BASEADDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_GPIO_0 1
73#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
Michal Simek4c6a6f02008-03-28 11:22:48 +010074#endif
Michal Simek76316a32007-03-11 13:42:58 +010075
76/* interrupt controller */
Michal Simek4d49b282008-05-04 15:42:41 +020077#ifdef XILINX_INTC_BASEADDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_INTC_0 1
79#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
80#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
Michal Simek4d49b282008-05-04 15:42:41 +020081#endif
Michal Simek76316a32007-03-11 13:42:58 +010082
83/* timer */
Michal Simek4d49b282008-05-04 15:42:41 +020084#ifdef XILINX_TIMER_BASEADDR
85#if (XILINX_TIMER_IRQ != -1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_TIMER_0 1
87#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
88#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
Michal Simek17980492007-03-26 01:39:07 +020089#define FREQUENCE XILINX_CLOCK_FREQ
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
Michal Simek4d49b282008-05-04 15:42:41 +020091#endif
92#else
93#ifdef XILINX_CLOCK_FREQ
Michal Simek853643d2007-09-24 00:41:30 +020094#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
Michal Simek4d49b282008-05-04 15:42:41 +020095#else
96#error BAD CLOCK FREQ
97#endif
98#endif
Michal Simek19bf1fb2007-05-07 19:33:51 +020099/* FSL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100/* #define CONFIG_SYS_FSL_2 */
Michal Simek188dc162008-03-28 11:53:02 +0100101/* #define FSL_INTR_2 1 */
Michal Simek19bf1fb2007-05-07 19:33:51 +0200102
Michal Simek76316a32007-03-11 13:42:58 +0100103/*
104 * memory layout - Example
105 * TEXT_BASE = 0x1200_0000;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
107 * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;
Michal Simek76316a32007-03-11 13:42:58 +0100108 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
110 * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
111 * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
Michal Simek76316a32007-03-11 13:42:58 +0100112 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 * 0x1000_0000 CONFIG_SYS_SDRAM_BASE
Michal Simek76316a32007-03-11 13:42:58 +0100114 * FREE
115 * 0x1200_0000 TEXT_BASE
116 * U-BOOT code
117 * 0x1202_0000
118 * FREE
119 *
120 * STACK
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE
Michal Simek17980492007-03-26 01:39:07 +0200122 * MALLOC_AREA 256kB Alloc
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123 * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE
Michal Simek17980492007-03-26 01:39:07 +0200124 * MONITOR_CODE 256kB Env
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
Michal Simek853643d2007-09-24 00:41:30 +0200126 * GLOBAL_DATA 4kB bd, gd
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
Michal Simek76316a32007-03-11 13:42:58 +0100128 */
129
130/* ddr sdram - main memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
132#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
133#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
134#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
Michal Simek76316a32007-03-11 13:42:58 +0100135
136/* global pointer */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */
Michal Simek32556442007-04-21 21:07:22 +0200138/* start of global data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
Michal Simek76316a32007-03-11 13:42:58 +0100140
141/* monitor code */
142#define SIZE 0x40000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_MONITOR_LEN SIZE
144#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
145#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
146#define CONFIG_SYS_MALLOC_LEN SIZE
147#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
Michal Simek76316a32007-03-11 13:42:58 +0100148
149/* stack */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MONITOR_BASE
Michal Simek76316a32007-03-11 13:42:58 +0100151
152/*#define RAMENV */
153#define FLASH
154
155#ifdef FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
157 #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
158 #define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200159 #define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */
161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
162 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
163 #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
Michal Simek76316a32007-03-11 13:42:58 +0100164
165 #ifdef RAMENV
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200166 #define CONFIG_ENV_IS_NOWHERE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200167 #define CONFIG_ENV_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
Michal Simek76316a32007-03-11 13:42:58 +0100169
170 #else /* !RAMENV */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200171 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200172 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200174 #define CONFIG_ENV_SIZE 0x40000
Michal Simek76316a32007-03-11 13:42:58 +0100175 #endif /* !RAMBOOT */
176#else /* !FLASH */
177 /* ENV in RAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178 #define CONFIG_SYS_NO_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200179 #define CONFIG_ENV_IS_NOWHERE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200180 #define CONFIG_ENV_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
182 #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
Michal Simek76316a32007-03-11 13:42:58 +0100183#endif /* !FLASH */
184
Michal Simek853643d2007-09-24 00:41:30 +0200185/* system ace */
186#ifdef XILINX_SYSACE_BASEADDR
187 #define CONFIG_SYSTEMACE
188 /* #define DEBUG_SYSTEMACE */
189 #define SYSTEMACE_CONFIG_FPGA
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 #define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
191 #define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
Michal Simek853643d2007-09-24 00:41:30 +0200192 #define CONFIG_DOS_PARTITION
193#endif
194
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500195/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500196 * BOOTP options
197 */
198#define CONFIG_BOOTP_BOOTFILESIZE
199#define CONFIG_BOOTP_BOOTPATH
200#define CONFIG_BOOTP_GATEWAY
201#define CONFIG_BOOTP_HOSTNAME
Michal Simek76316a32007-03-11 13:42:58 +0100202
Jon Loeliger079a1362007-07-10 10:12:10 -0500203/*
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500204 * Command line configuration.
205 */
206#include <config_cmd_default.h>
207
208#define CONFIG_CMD_ASKENV
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500209#define CONFIG_CMD_CACHE
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500210#define CONFIG_CMD_IRQ
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500211#define CONFIG_CMD_MFSL
Michal Simek4d49b282008-05-04 15:42:41 +0200212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#ifndef CONFIG_SYS_ENET
Michal Simek4d49b282008-05-04 15:42:41 +0200214 #undef CONFIG_CMD_NET
215#else
216 #define CONFIG_CMD_PING
217#endif
Michal Simek853643d2007-09-24 00:41:30 +0200218
219#if defined(CONFIG_SYSTEMACE)
220 #define CONFIG_CMD_EXT2
221 #define CONFIG_CMD_FAT
222#endif
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500223
224#if defined(FLASH)
225 #define CONFIG_CMD_ECHO
226 #define CONFIG_CMD_FLASH
227 #define CONFIG_CMD_IMLS
228 #define CONFIG_CMD_JFFS2
229
230 #if !defined(RAMENV)
231 #define CONFIG_CMD_ENV
232 #define CONFIG_CMD_SAVES
Michal Simek76316a32007-03-11 13:42:58 +0100233 #endif
Michal Simek853643d2007-09-24 00:41:30 +0200234#else
235 #undef CONFIG_CMD_FLASH
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500236#endif
Michal Simek76316a32007-03-11 13:42:58 +0100237
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500238#if defined(CONFIG_CMD_JFFS2)
Michal Simek144876a2007-04-24 23:01:02 +0200239/* JFFS2 partitions */
240#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
241#define MTDIDS_DEFAULT "nor0=ml401-0"
242
243/* default mtd partition table */
244#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
245 "256k(env),3m(kernel),1m(romfs),"\
246 "1m(cramfs),-(jffs2)"
247#endif
248
Michal Simek76316a32007-03-11 13:42:58 +0100249/* Miscellaneous configurable options */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
251#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */
252#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
253#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
254#define CONFIG_SYS_LONGHELP
255#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */
Michal Simek76316a32007-03-11 13:42:58 +0100256
Michal Simek144876a2007-04-24 23:01:02 +0200257#define CONFIG_BOOTDELAY 30
Michal Simek76316a32007-03-11 13:42:58 +0100258#define CONFIG_BOOTARGS "root=romfs"
259#define CONFIG_HOSTNAME "ml401"
Michal Simek853643d2007-09-24 00:41:30 +0200260#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
Michal Simek76316a32007-03-11 13:42:58 +0100261#define CONFIG_IPADDR 192.168.0.3
Michal Simek853643d2007-09-24 00:41:30 +0200262#define CONFIG_SERVERIP 192.168.0.5
263#define CONFIG_GATEWAYIP 192.168.0.1
Michal Simek76316a32007-03-11 13:42:58 +0100264#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
265
266/* architecture dependent code */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_USR_EXCEP /* user exception */
268#define CONFIG_SYS_HZ 1000
Michal Simek76316a32007-03-11 13:42:58 +0100269
Michal Simek144876a2007-04-24 23:01:02 +0200270#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
271
272#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
273 "nor0=ml401-0\0"\
274 "mtdparts=mtdparts=ml401-0:"\
275 "256k(u-boot),256k(env),3m(kernel),"\
276 "1m(romfs),1m(cramfs),-(jffs2)\0"
277
Michal Simek188dc162008-03-28 11:53:02 +0100278#define CONFIG_CMDLINE_EDITING
Michal Simek188dc162008-03-28 11:53:02 +0100279
Michal Simek76316a32007-03-11 13:42:58 +0100280#endif /* __CONFIG_H */