blob: 681185dd84897779504402bc7a3b0de518372cc4 [file] [log] [blame]
wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0x40000000
40
wdenkf4675562002-10-02 14:20:15 +000041#ifdef CONFIG_LCD /* with LCD controller ? */
Wolfgang Denk21f971e2008-07-07 01:22:29 +020042#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
43#define CONFIG_LCD_INFO 1 /* ... and some board info */
wdenk27b207f2003-07-24 23:38:38 +000044#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenkf4675562002-10-02 14:20:15 +000045#endif
46
47#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020048#define CONFIG_SYS_SMC_RXBUFLEN 128
49#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000050#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf4675562002-10-02 14:20:15 +000051
wdenkae3af052003-08-07 22:18:11 +000052#define CONFIG_BOOTCOUNT_LIMIT
53
54#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000055
56#define CONFIG_BOARD_TYPES 1 /* support board types */
57
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010058#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf4675562002-10-02 14:20:15 +000059
60#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000061
62#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000063 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000064 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000066 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010067 "addip=setenv bootargs ${bootargs} " \
68 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
69 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000070 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000072 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010073 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
74 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000075 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020076 "hostname=TQM823L\0" \
77 "bootfile=TQM823L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020078 "fdt_addr=40040000\0" \
79 "kernel_addr=40060000\0" \
80 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020081 "u-boot=TQM823L/u-image.bin\0" \
82 "load=tftp 200000 ${u-boot}\0" \
83 "update=prot off 40000000 +${filesize};" \
84 "era 40000000 +${filesize};" \
85 "cp.b 200000 40000000 ${filesize};" \
86 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000087 ""
88#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000089
90#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000092
93#undef CONFIG_WATCHDOG /* watchdog disabled */
94
wdenka522fa02004-01-04 22:51:12 +000095#if defined(CONFIG_LCD)
wdenkf4675562002-10-02 14:20:15 +000096# undef CONFIG_STATUS_LED /* disturbs display */
97#else
98# define CONFIG_STATUS_LED 1 /* Status LED enabled */
99#endif /* CONFIG_LCD */
100
wdenka522fa02004-01-04 22:51:12 +0000101#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
wdenkf4675562002-10-02 14:20:15 +0000102
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500103/*
104 * BOOTP options
105 */
106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_BOOTFILESIZE
111
wdenkf4675562002-10-02 14:20:15 +0000112
113#define CONFIG_MAC_PARTITION
114#define CONFIG_DOS_PARTITION
115
116#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
117
Jon Loeliger26946902007-07-04 22:30:50 -0500118
119/*
120 * Command line configuration.
121 */
122#include <config_cmd_default.h>
123
124#define CONFIG_CMD_ASKENV
125#define CONFIG_CMD_DATE
126#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200127#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100128#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500129#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200130#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500131#define CONFIG_CMD_NFS
132#define CONFIG_CMD_SNTP
133
wdenk27b207f2003-07-24 23:38:38 +0000134#ifdef CONFIG_SPLASH_SCREEN
Jon Loeliger26946902007-07-04 22:30:50 -0500135 #define CONFIG_CMD_BMP
wdenk27b207f2003-07-24 23:38:38 +0000136#endif
wdenkf4675562002-10-02 14:20:15 +0000137
wdenkf4675562002-10-02 14:20:15 +0000138
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200139#define CONFIG_NETCONSOLE
140
wdenkf4675562002-10-02 14:20:15 +0000141/*
142 * Miscellaneous configurable options
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LONGHELP /* undef to save memory */
145#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk6aff3112002-12-17 01:51:00 +0000146
Wolfgang Denk2751a952006-10-28 02:29:14 +0200147#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
149#ifdef CONFIG_SYS_HUSH_PARSER
150#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk6aff3112002-12-17 01:51:00 +0000151#endif
152
Jon Loeliger26946902007-07-04 22:30:50 -0500153#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000155#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000157#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
159#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
160#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
163#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf4675562002-10-02 14:20:15 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkf4675562002-10-02 14:20:15 +0000170
171/*
172 * Low Level Configuration Settings
173 * (address mappings, register initial values, etc.)
174 * You should know what you are doing if you make changes here.
175 */
176/*-----------------------------------------------------------------------
177 * Internal Memory Mapped Register
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000180
181/*-----------------------------------------------------------------------
182 * Definitions for initial stack pointer and data area (in DPRAM)
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200185#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200187#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000189
190/*-----------------------------------------------------------------------
191 * Start addresses for the final memory configuration
192 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_SDRAM_BASE 0x00000000
196#define CONFIG_SYS_FLASH_BASE 0x40000000
197#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
198#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
199#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000200
201/*
202 * For booting Linux, the board info and command line data
203 * have to be in the first 8 MB of memory, since this is
204 * the maximum mapped by the Linux kernel during initialization.
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000207
208/*-----------------------------------------------------------------------
209 * FLASH organization
210 */
wdenkf4675562002-10-02 14:20:15 +0000211
Martin Krausee318d9e2007-09-27 11:10:08 +0200212/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200214#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
216#define CONFIG_SYS_FLASH_EMPTY_INFO
217#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
218#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
219#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000220
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200221#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200222#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
223#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000224
225/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200226#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
227#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200230
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200231#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
232
wdenkf4675562002-10-02 14:20:15 +0000233/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200234 * Dynamic MTD partition support
235 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100236#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200237#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
238#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200239#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
240
241#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
242 "128k(dtb)," \
243 "1664k(kernel)," \
244 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200245 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200246
247/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000248 * Hardware Information Block
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
251#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
252#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000253
254/*-----------------------------------------------------------------------
255 * Cache Configuration
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500258#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000260#endif
261
262/*-----------------------------------------------------------------------
263 * SYPCR - System Protection Control 11-9
264 * SYPCR can only be written once after reset!
265 *-----------------------------------------------------------------------
266 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
267 */
268#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000270 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
271#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000273#endif
274
275/*-----------------------------------------------------------------------
276 * SIUMCR - SIU Module Configuration 11-6
277 *-----------------------------------------------------------------------
278 * PCMCIA config., multi-function pin tri-state
279 */
280#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000282#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000284#endif /* CONFIG_CAN_DRIVER */
285
286/*-----------------------------------------------------------------------
287 * TBSCR - Time Base Status and Control 11-26
288 *-----------------------------------------------------------------------
289 * Clear Reference Interrupt Status, Timebase freezing enabled
290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000292
293/*-----------------------------------------------------------------------
294 * RTCSC - Real-Time Clock Status and Control Register 11-27
295 *-----------------------------------------------------------------------
296 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000298
299/*-----------------------------------------------------------------------
300 * PISCR - Periodic Interrupt Status and Control 11-31
301 *-----------------------------------------------------------------------
302 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
303 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000305
306/*-----------------------------------------------------------------------
307 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
308 *-----------------------------------------------------------------------
309 * Reset PLL lock status sticky bit, timer expired status bit and timer
310 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000313
314/*-----------------------------------------------------------------------
315 * SCCR - System Clock and reset Control Register 15-27
316 *-----------------------------------------------------------------------
317 * Set clock output, timebase and RTC source and divider,
318 * power management and some other internal clocks
319 */
320#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000322 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
323 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000324
325/*-----------------------------------------------------------------------
326 * PCMCIA stuff
327 *-----------------------------------------------------------------------
328 *
329 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
331#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
332#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
333#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
334#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
335#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
336#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
337#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000338
339/*-----------------------------------------------------------------------
340 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
341 *-----------------------------------------------------------------------
342 */
343
344#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
345
346#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
347#undef CONFIG_IDE_LED /* LED for ide not supported */
348#undef CONFIG_IDE_RESET /* reset for ide not supported */
349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
351#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000356
357/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000359
360/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000362
363/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000365
366/*-----------------------------------------------------------------------
367 *
368 *-----------------------------------------------------------------------
369 *
370 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000372
373/*
374 * Init Memory Controller:
375 *
376 * BR0/1 and OR0/1 (FLASH)
377 */
378
379#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
380#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
381
382/* used to re-map FLASH both when starting from SRAM or FLASH:
383 * restrict access enough to keep SRAM working (if any)
384 * but not too much to meddle with FLASH accesses
385 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
387#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000388
389/*
390 * FLASH timing:
391 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000393 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
396#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
397#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000398
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
400#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
401#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000402
403/*
404 * BR2/3 and OR2/3 (SDRAM)
405 *
406 */
407#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
408#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
409#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
410
411/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000413
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
415#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000416
417#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
419#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000420#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
422#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
423#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
424#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000425 BR_PS_8 | BR_MS_UPMB | BR_V )
426#endif /* CONFIG_CAN_DRIVER */
427
428/*
429 * Memory Periodic Timer Prescaler
430 *
431 * The Divider for PTA (refresh timer) configuration is based on an
432 * example SDRAM configuration (64 MBit, one bank). The adjustment to
433 * the number of chip selects (NCS) and the actually needed refresh
434 * rate is done by setting MPTPR.
435 *
436 * PTA is calculated from
437 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
438 *
439 * gclk CPU clock (not bus clock!)
440 * Trefresh Refresh cycle * 4 (four word bursts used)
441 *
442 * 4096 Rows from SDRAM example configuration
443 * 1000 factor s -> ms
444 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
445 * 4 Number of refresh cycles per period
446 * 64 Refresh cycle in ms per number of rows
447 * --------------------------------------------
448 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
449 *
450 * 50 MHz => 50.000.000 / Divider = 98
451 * 66 Mhz => 66.000.000 / Divider = 129
452 * 80 Mhz => 80.000.000 / Divider = 156
453 */
wdenke9132ea2004-04-24 23:23:30 +0000454
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
456#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000457
458/*
459 * For 16 MBit, refresh rates could be 31.3 us
460 * (= 64 ms / 2K = 125 / quad bursts).
461 * For a simpler initialization, 15.6 us is used instead.
462 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
464 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000465 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
467#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000468
469/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
471#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000472
473/*
474 * MAMR settings for SDRAM
475 */
476
477/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000479 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
480 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
481/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000483 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
484 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
485
Heiko Schocher7026ead2010-02-09 15:50:27 +0100486/* pass open firmware flat tree */
487#define CONFIG_OF_LIBFDT 1
488#define CONFIG_OF_BOARD_SETUP 1
489#define CONFIG_HWCONFIG 1
490
wdenkf4675562002-10-02 14:20:15 +0000491#endif /* __CONFIG_H */