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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <ppc_asm.tmpl>
30#include <asm/processor.h>
31
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
wdenk42d1f032003-10-15 23:53:47 +000034/* --------------------------------------------------------------- */
35
wdenk42d1f032003-10-15 23:53:47 +000036void get_sys_info (sys_info_t * sysInfo)
37{
Kumar Galaf59b55a2007-11-27 23:25:02 -060038 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Andy Fleming66ed6cc2007-04-23 02:37:47 -050039 uint plat_ratio,e500_ratio,half_freqSystemBus;
wdenk42d1f032003-10-15 23:53:47 +000040
41 plat_ratio = (gur->porpllsr) & 0x0000003e;
42 plat_ratio >>= 1;
Andy Fleming66ed6cc2007-04-23 02:37:47 -050043 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
wdenk42d1f032003-10-15 23:53:47 +000044 e500_ratio = (gur->porpllsr) & 0x003f0000;
45 e500_ratio >>= 16;
Andy Fleming66ed6cc2007-04-23 02:37:47 -050046
47 /* Divide before multiply to avoid integer
48 * overflow for processor speeds above 2GHz */
49 half_freqSystemBus = sysInfo->freqSystemBus/2;
50 sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
James Yanga3e77fa2008-02-08 18:05:08 -060051
52 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
Kumar Galad4357932007-12-07 04:59:26 -060053 sysInfo->freqDDRBus = sysInfo->freqSystemBus;
54
55#ifdef CONFIG_DDR_CLK_FREQ
56 {
57 u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
58 if (ddr_ratio != 0x7)
59 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
60 }
61#endif
wdenk42d1f032003-10-15 23:53:47 +000062}
63
Andy Fleming66ed6cc2007-04-23 02:37:47 -050064
wdenk42d1f032003-10-15 23:53:47 +000065int get_clocks (void)
66{
wdenk42d1f032003-10-15 23:53:47 +000067 sys_info_t sys_info;
Timur Tabi88353a92008-04-04 11:15:58 -050068#ifdef CONFIG_MPC8544
69 volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
70#endif
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050071#if defined(CONFIG_CPM2)
Kumar Galaaafeefb2007-11-28 00:36:33 -060072 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +000073 uint sccr, dfbrg;
74
75 /* set VCO = 4 * BRG */
Kumar Galaaafeefb2007-11-28 00:36:33 -060076 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
77 sccr = cpm->im_cpm_intctl.sccr;
wdenk42d1f032003-10-15 23:53:47 +000078 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
79#endif
80 get_sys_info (&sys_info);
81 gd->cpu_clk = sys_info.freqProcessor;
82 gd->bus_clk = sys_info.freqSystemBus;
James Yanga3e77fa2008-02-08 18:05:08 -060083 gd->mem_clk = sys_info.freqDDRBus;
Timur Tabi88353a92008-04-04 11:15:58 -050084
85 /*
86 * The base clock for I2C depends on the actual SOC. Unfortunately,
87 * there is no pattern that can be used to determine the frequency, so
88 * the only choice is to look up the actual SOC number and use the value
89 * for that SOC. This information is taken from application note
90 * AN2919.
91 */
92#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
93 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
Timur Tabi943afa22008-01-09 14:35:26 -060094 gd->i2c1_clk = sys_info.freqSystemBus;
Timur Tabi88353a92008-04-04 11:15:58 -050095#elif defined(CONFIG_MPC8544)
96 /*
97 * On the 8544, the I2C clock is the same as the SEC clock. This can be
98 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
99 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
100 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
101 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
102 */
103 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
104 gd->i2c1_clk = sys_info.freqSystemBus / 3;
105 else
106 gd->i2c1_clk = sys_info.freqSystemBus / 2;
107#else
108 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
109 gd->i2c1_clk = sys_info.freqSystemBus / 2;
110#endif
111 gd->i2c2_clk = gd->i2c1_clk;
Timur Tabi943afa22008-01-09 14:35:26 -0600112
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500113#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000114 gd->vco_out = 2*sys_info.freqSystemBus;
115 gd->cpm_clk = gd->vco_out / 2;
116 gd->scc_clk = gd->vco_out / 4;
117 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
118#endif
119
120 if(gd->cpu_clk != 0) return (0);
121 else return (1);
122}
123
124
125/********************************************
126 * get_bus_freq
127 * return system bus freq in Hz
128 *********************************************/
129ulong get_bus_freq (ulong dummy)
130{
James Yanga3e77fa2008-02-08 18:05:08 -0600131 return gd->bus_clk;
wdenk42d1f032003-10-15 23:53:47 +0000132}
Kumar Galad4357932007-12-07 04:59:26 -0600133
134/********************************************
135 * get_ddr_freq
136 * return ddr bus freq in Hz
137 *********************************************/
138ulong get_ddr_freq (ulong dummy)
139{
James Yanga3e77fa2008-02-08 18:05:08 -0600140 return gd->mem_clk;
Kumar Galad4357932007-12-07 04:59:26 -0600141}