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Tom Warrenefc05ae2011-01-27 10:58:07 +00001/*
Tom Warren52a8b822012-05-22 12:19:25 +00002 * (C) Copyright 2010-2012
Tom Warrenefc05ae2011-01-27 10:58:07 +00003 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Tom Warrenefc05ae2011-01-27 10:58:07 +00006 */
7
Tom Warrenf01b6312012-12-11 13:34:18 +00008#ifndef _TEGRA20_COMMON_H_
9#define _TEGRA20_COMMON_H_
10#include "tegra-common.h"
11
Thierry Reding0d79f4f2013-07-18 12:13:40 -070012/* Cortex-A9 uses a cache line size of 32 bytes */
13#define CONFIG_SYS_CACHELINE_SIZE 32
14
Tom Warrenf01b6312012-12-11 13:34:18 +000015/*
Stephen Warrenc44bb3a2013-02-26 12:28:28 +000016 * Errata configuration
17 */
Stephen Warren53612132013-03-04 13:29:41 +000018#define CONFIG_ARM_ERRATA_716044
Stephen Warrenc44bb3a2013-02-26 12:28:28 +000019#define CONFIG_ARM_ERRATA_742230
20#define CONFIG_ARM_ERRATA_751472
21
22/*
Tom Warrenf01b6312012-12-11 13:34:18 +000023 * NS16550 Configuration
24 */
25#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
Simon Glass649d0ff2012-04-02 13:19:03 +000026
Tom Warrenf01b6312012-12-11 13:34:18 +000027/*
28 * Miscellaneous configurable options
29 */
Tom Warrenf01b6312012-12-11 13:34:18 +000030#define CONFIG_STACKBASE 0x02800000 /* 40MB */
31
32/*-----------------------------------------------------------------------
33 * Physical Memory Map
34 */
Stephen Warren930c5142015-09-23 12:34:01 -060035#define CONFIG_SYS_TEXT_BASE 0x00110000
Tom Warrenf01b6312012-12-11 13:34:18 +000036
37/*
38 * Memory layout for where various images get loaded by boot scripts:
39 *
40 * scriptaddr can be pretty much anywhere that doesn't conflict with something
41 * else. Put it above BOOTMAPSZ to eliminate conflicts.
42 *
Stephen Warrenf940c722014-02-05 09:24:59 -070043 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
44 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
45 *
Tom Warrenf01b6312012-12-11 13:34:18 +000046 * kernel_addr_r must be within the first 128M of RAM in order for the
47 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
48 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
49 * should not overlap that area, or the kernel will have to copy itself
50 * somewhere else before decompression. Similarly, the address of any other
51 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
52 * this up to 16M allows for a sizable kernel to be decompressed below the
53 * compressed load address.
54 *
55 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
56 * the compressed kernel to be up to 16M too.
57 *
58 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
59 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
60 */
Stephen Warren48cfca22015-04-01 15:40:53 -060061#define CONFIG_LOADADDR 0x01000000
Tom Warrenf01b6312012-12-11 13:34:18 +000062#define MEM_LAYOUT_ENV_SETTINGS \
63 "scriptaddr=0x10000000\0" \
Stephen Warrenf940c722014-02-05 09:24:59 -070064 "pxefile_addr_r=0x10100000\0" \
Stephen Warren48cfca22015-04-01 15:40:53 -060065 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
Tom Warrenf01b6312012-12-11 13:34:18 +000066 "fdt_addr_r=0x02000000\0" \
67 "ramdisk_addr_r=0x02100000\0"
68
69/* Defines for SPL */
70#define CONFIG_SPL_TEXT_BASE 0x00108000
71#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
72#define CONFIG_SPL_STACK 0x000ffffc
73
Simon Glassad166172012-10-17 13:24:56 +000074/* Align LCD to 1MB boundary */
75#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
76
Tom Warren29f3e3f2012-09-04 17:00:24 -070077#ifdef CONFIG_TEGRA_LP0
Simon Glass649d0ff2012-04-02 13:19:03 +000078#define TEGRA_LP0_ADDR 0x1C406000
79#define TEGRA_LP0_SIZE 0x2000
80#define TEGRA_LP0_VEC \
Tom Warrenf01b6312012-12-11 13:34:18 +000081 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
Marek Vasut51926d52012-09-23 17:41:25 +020082 "@" __stringify(TEGRA_LP0_ADDR) " "
Simon Glass649d0ff2012-04-02 13:19:03 +000083#else
84#define TEGRA_LP0_VEC
85#endif
86
Simon Glass02910912012-02-27 10:52:51 +000087/*
88 * This parameter affects a TXFILLTUNING field that controls how much data is
89 * sent to the latency fifo before it is sent to the wire. Without this
90 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
91 * packets depending on the buffer address and size.
92 */
93#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
94#define CONFIG_EHCI_IS_TDI
Stephen Warrenf75dc782014-02-10 13:11:53 -070095#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
Simon Glass02910912012-02-27 10:52:51 +000096
Simon Glass0dd84082012-07-29 20:53:30 +000097#define CONFIG_SYS_NAND_SELF_INIT
Lucas Stacha833b952012-10-07 11:29:38 +000098#define CONFIG_SYS_NAND_ONFI_DETECTION
Simon Glass0dd84082012-07-29 20:53:30 +000099
Tom Warrenf01b6312012-12-11 13:34:18 +0000100#endif /* _TEGRA20_COMMON_H_ */