bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 1 | /* |
bart | 86562bd | 2009-02-16 19:43:56 +0000 | [diff] [blame] | 2 | This file is part of drd, a thread error detector. |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 3 | |
sewardj | 03f8d3f | 2012-08-05 15:46:46 +0000 | [diff] [blame] | 4 | Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>. |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or |
| 7 | modify it under the terms of the GNU General Public License as |
| 8 | published by the Free Software Foundation; either version 2 of the |
| 9 | License, or (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, but |
| 12 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 19 | 02111-1307, USA. |
| 20 | |
| 21 | The GNU General Public License is contained in the file COPYING. |
| 22 | */ |
| 23 | |
| 24 | |
| 25 | #include "drd_bitmap.h" |
| 26 | #include "drd_thread_bitmap.h" |
bart | 41b226c | 2009-02-14 16:55:19 +0000 | [diff] [blame] | 27 | #include "drd_vc.h" /* DRD_(vc_snprint)() */ |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 28 | |
| 29 | /* Include several source files here in order to allow the compiler to */ |
| 30 | /* do more inlining. */ |
| 31 | #include "drd_bitmap.c" |
| 32 | #include "drd_load_store.h" |
| 33 | #include "drd_segment.c" |
| 34 | #include "drd_thread.c" |
| 35 | #include "drd_vc.c" |
| 36 | #include "libvex_guest_offsets.h" |
| 37 | |
| 38 | |
| 39 | /* STACK_POINTER_OFFSET: VEX register offset for the stack pointer register. */ |
| 40 | #if defined(VGA_x86) |
| 41 | #define STACK_POINTER_OFFSET OFFSET_x86_ESP |
| 42 | #elif defined(VGA_amd64) |
| 43 | #define STACK_POINTER_OFFSET OFFSET_amd64_RSP |
| 44 | #elif defined(VGA_ppc32) |
sewardj | 4cb6bf7 | 2010-01-01 18:31:41 +0000 | [diff] [blame] | 45 | #define STACK_POINTER_OFFSET OFFSET_ppc32_GPR1 |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 46 | #elif defined(VGA_ppc64) |
sewardj | 4cb6bf7 | 2010-01-01 18:31:41 +0000 | [diff] [blame] | 47 | #define STACK_POINTER_OFFSET OFFSET_ppc64_GPR1 |
| 48 | #elif defined(VGA_arm) |
| 49 | #define STACK_POINTER_OFFSET OFFSET_arm_R13 |
sewardj | b5b8740 | 2011-03-07 16:05:35 +0000 | [diff] [blame] | 50 | #elif defined(VGA_s390x) |
| 51 | #define STACK_POINTER_OFFSET OFFSET_s390x_r15 |
sewardj | 5db1540 | 2012-06-07 09:13:21 +0000 | [diff] [blame] | 52 | #elif defined(VGA_mips32) |
| 53 | #define STACK_POINTER_OFFSET OFFSET_mips32_r29 |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 54 | #else |
| 55 | #error Unknown architecture. |
| 56 | #endif |
| 57 | |
| 58 | |
| 59 | /* Local variables. */ |
| 60 | |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 61 | static Bool s_check_stack_accesses = False; |
| 62 | static Bool s_first_race_only = False; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 63 | |
| 64 | |
| 65 | /* Function definitions. */ |
| 66 | |
| 67 | Bool DRD_(get_check_stack_accesses)() |
| 68 | { |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 69 | return s_check_stack_accesses; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | void DRD_(set_check_stack_accesses)(const Bool c) |
| 73 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 74 | tl_assert(c == False || c == True); |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 75 | s_check_stack_accesses = c; |
| 76 | } |
| 77 | |
| 78 | Bool DRD_(get_first_race_only)() |
| 79 | { |
| 80 | return s_first_race_only; |
| 81 | } |
| 82 | |
| 83 | void DRD_(set_first_race_only)(const Bool fro) |
| 84 | { |
| 85 | tl_assert(fro == False || fro == True); |
| 86 | s_first_race_only = fro; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 87 | } |
| 88 | |
bart | 1335ecc | 2009-02-14 16:10:53 +0000 | [diff] [blame] | 89 | void DRD_(trace_mem_access)(const Addr addr, const SizeT size, |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 90 | const BmAccessTypeT access_type, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 91 | const HWord stored_value_hi, |
| 92 | const HWord stored_value_lo) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 93 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 94 | if (DRD_(is_any_traced)(addr, addr + size)) |
| 95 | { |
bart | 8f822af | 2009-06-08 18:20:42 +0000 | [diff] [blame] | 96 | char* vc; |
| 97 | |
| 98 | vc = DRD_(vc_aprint)(DRD_(thread_get_vc)(DRD_(thread_get_running_tid)())); |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 99 | if (access_type == eStore && size <= sizeof(HWord)) { |
bart | 5cda1b5 | 2011-12-12 19:37:10 +0000 | [diff] [blame] | 100 | DRD_(trace_msg_w_bt)("store 0x%lx size %ld val %ld/0x%lx (thread %d /" |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 101 | " vc %s)", addr, size, stored_value_lo, |
| 102 | stored_value_lo, DRD_(thread_get_running_tid)(), |
| 103 | vc); |
| 104 | } else if (access_type == eStore && size > sizeof(HWord)) { |
| 105 | ULong sv; |
| 106 | |
| 107 | tl_assert(sizeof(HWord) == 4); |
| 108 | sv = ((ULong)stored_value_hi << 32) | stored_value_lo; |
| 109 | DRD_(trace_msg_w_bt)("store 0x%lx size %ld val %lld/0x%llx (thread %d" |
| 110 | " / vc %s)", addr, size, sv, sv, |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 111 | DRD_(thread_get_running_tid)(), vc); |
| 112 | } else { |
| 113 | DRD_(trace_msg_w_bt)("%s 0x%lx size %ld (thread %d / vc %s)", |
| 114 | access_type == eLoad ? "load " |
| 115 | : access_type == eStore ? "store" |
| 116 | : access_type == eStart ? "start" |
| 117 | : access_type == eEnd ? "end " : "????", |
| 118 | addr, size, DRD_(thread_get_running_tid)(), vc); |
| 119 | } |
bart | 8f822af | 2009-06-08 18:20:42 +0000 | [diff] [blame] | 120 | VG_(free)(vc); |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 121 | tl_assert(DRD_(DrdThreadIdToVgThreadId)(DRD_(thread_get_running_tid)()) |
| 122 | == VG_(get_running_tid)()); |
| 123 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 124 | } |
| 125 | |
bart | 0759503 | 2010-08-29 09:51:06 +0000 | [diff] [blame] | 126 | static VG_REGPARM(2) void drd_trace_mem_load(const Addr addr, const SizeT size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 127 | { |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 128 | return DRD_(trace_mem_access)(addr, size, eLoad, 0, 0); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 129 | } |
| 130 | |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 131 | static VG_REGPARM(3) void drd_trace_mem_store(const Addr addr,const SizeT size, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 132 | const HWord stored_value_hi, |
| 133 | const HWord stored_value_lo) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 134 | { |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 135 | return DRD_(trace_mem_access)(addr, size, eStore, stored_value_hi, |
| 136 | stored_value_lo); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | static void drd_report_race(const Addr addr, const SizeT size, |
| 140 | const BmAccessTypeT access_type) |
| 141 | { |
bart | 7a9db0f | 2012-04-01 14:40:16 +0000 | [diff] [blame] | 142 | ThreadId vg_tid; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 143 | |
bart | 7a9db0f | 2012-04-01 14:40:16 +0000 | [diff] [blame] | 144 | vg_tid = VG_(get_running_tid)(); |
bart | 7886dd3 | 2012-04-01 15:06:57 +0000 | [diff] [blame] | 145 | if (!DRD_(get_check_stack_accesses)() |
| 146 | && DRD_(thread_address_on_any_stack)(addr)) { |
bart | 7a9db0f | 2012-04-01 14:40:16 +0000 | [diff] [blame] | 147 | #if 0 |
| 148 | GenericErrInfo GEI = { |
| 149 | .tid = DRD_(thread_get_running_tid)(), |
| 150 | .addr = addr, |
| 151 | }; |
| 152 | VG_(maybe_record_error)(vg_tid, GenericErr, VG_(get_IP)(vg_tid), |
| 153 | "--check-stack-var=no skips checking stack" |
| 154 | " variables shared over threads", |
| 155 | &GEI); |
| 156 | #endif |
| 157 | } else { |
| 158 | DataRaceErrInfo drei = { |
| 159 | .tid = DRD_(thread_get_running_tid)(), |
| 160 | .addr = addr, |
| 161 | .size = size, |
| 162 | .access_type = access_type, |
| 163 | }; |
| 164 | VG_(maybe_record_error)(vg_tid, DataRaceErr, VG_(get_IP)(vg_tid), |
| 165 | "Conflicting access", &drei); |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 166 | |
bart | 7a9db0f | 2012-04-01 14:40:16 +0000 | [diff] [blame] | 167 | if (s_first_race_only) |
| 168 | DRD_(start_suppression)(addr, addr + size, "first race only"); |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 169 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 170 | } |
| 171 | |
bart | 99edb29 | 2009-02-15 15:59:20 +0000 | [diff] [blame] | 172 | VG_REGPARM(2) void DRD_(trace_load)(Addr addr, SizeT size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 173 | { |
| 174 | #ifdef ENABLE_DRD_CONSISTENCY_CHECKS |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 175 | /* The assert below has been commented out because of performance reasons.*/ |
bart | d5bbc61 | 2010-09-02 14:44:17 +0000 | [diff] [blame] | 176 | tl_assert(DRD_(thread_get_running_tid)() |
| 177 | == DRD_(VgThreadIdToDrdThreadId)(VG_(get_running_tid()))); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 178 | #endif |
| 179 | |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 180 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 181 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 182 | || ! DRD_(thread_address_on_stack)(addr)) |
| 183 | && bm_access_load_triggers_conflict(addr, addr + size) |
| 184 | && ! DRD_(is_suppressed)(addr, addr + size)) |
| 185 | { |
| 186 | drd_report_race(addr, size, eLoad); |
| 187 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | static VG_REGPARM(1) void drd_trace_load_1(Addr addr) |
| 191 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 192 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 193 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 194 | || ! DRD_(thread_address_on_stack)(addr)) |
| 195 | && bm_access_load_1_triggers_conflict(addr) |
| 196 | && ! DRD_(is_suppressed)(addr, addr + 1)) |
| 197 | { |
| 198 | drd_report_race(addr, 1, eLoad); |
| 199 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | static VG_REGPARM(1) void drd_trace_load_2(Addr addr) |
| 203 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 204 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 205 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 206 | || ! DRD_(thread_address_on_stack)(addr)) |
| 207 | && bm_access_load_2_triggers_conflict(addr) |
| 208 | && ! DRD_(is_suppressed)(addr, addr + 2)) |
| 209 | { |
| 210 | drd_report_race(addr, 2, eLoad); |
| 211 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | static VG_REGPARM(1) void drd_trace_load_4(Addr addr) |
| 215 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 216 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 217 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 218 | || ! DRD_(thread_address_on_stack)(addr)) |
| 219 | && bm_access_load_4_triggers_conflict(addr) |
| 220 | && ! DRD_(is_suppressed)(addr, addr + 4)) |
| 221 | { |
| 222 | drd_report_race(addr, 4, eLoad); |
| 223 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | static VG_REGPARM(1) void drd_trace_load_8(Addr addr) |
| 227 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 228 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 229 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 230 | || ! DRD_(thread_address_on_stack)(addr)) |
| 231 | && bm_access_load_8_triggers_conflict(addr) |
| 232 | && ! DRD_(is_suppressed)(addr, addr + 8)) |
| 233 | { |
| 234 | drd_report_race(addr, 8, eLoad); |
| 235 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 236 | } |
| 237 | |
bart | 99edb29 | 2009-02-15 15:59:20 +0000 | [diff] [blame] | 238 | VG_REGPARM(2) void DRD_(trace_store)(Addr addr, SizeT size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 239 | { |
| 240 | #ifdef ENABLE_DRD_CONSISTENCY_CHECKS |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 241 | /* The assert below has been commented out because of performance reasons.*/ |
bart | d5bbc61 | 2010-09-02 14:44:17 +0000 | [diff] [blame] | 242 | tl_assert(DRD_(thread_get_running_tid)() |
| 243 | == DRD_(VgThreadIdToDrdThreadId)(VG_(get_running_tid()))); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 244 | #endif |
| 245 | |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 246 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 247 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 248 | || ! DRD_(thread_address_on_stack)(addr)) |
| 249 | && bm_access_store_triggers_conflict(addr, addr + size) |
| 250 | && ! DRD_(is_suppressed)(addr, addr + size)) |
| 251 | { |
| 252 | drd_report_race(addr, size, eStore); |
| 253 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | static VG_REGPARM(1) void drd_trace_store_1(Addr addr) |
| 257 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 258 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 259 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 260 | || ! DRD_(thread_address_on_stack)(addr)) |
| 261 | && bm_access_store_1_triggers_conflict(addr) |
| 262 | && ! DRD_(is_suppressed)(addr, addr + 1)) |
| 263 | { |
| 264 | drd_report_race(addr, 1, eStore); |
| 265 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | static VG_REGPARM(1) void drd_trace_store_2(Addr addr) |
| 269 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 270 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 271 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 272 | || ! DRD_(thread_address_on_stack)(addr)) |
| 273 | && bm_access_store_2_triggers_conflict(addr) |
| 274 | && ! DRD_(is_suppressed)(addr, addr + 2)) |
| 275 | { |
| 276 | drd_report_race(addr, 2, eStore); |
| 277 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | static VG_REGPARM(1) void drd_trace_store_4(Addr addr) |
| 281 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 282 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 283 | && (s_check_stack_accesses |
bart | 71ce132 | 2011-12-11 17:54:17 +0000 | [diff] [blame] | 284 | || !DRD_(thread_address_on_stack)(addr)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 285 | && bm_access_store_4_triggers_conflict(addr) |
bart | 71ce132 | 2011-12-11 17:54:17 +0000 | [diff] [blame] | 286 | && !DRD_(is_suppressed)(addr, addr + 4)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 287 | { |
| 288 | drd_report_race(addr, 4, eStore); |
| 289 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | static VG_REGPARM(1) void drd_trace_store_8(Addr addr) |
| 293 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 294 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 295 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 296 | || ! DRD_(thread_address_on_stack)(addr)) |
| 297 | && bm_access_store_8_triggers_conflict(addr) |
| 298 | && ! DRD_(is_suppressed)(addr, addr + 8)) |
| 299 | { |
| 300 | drd_report_race(addr, 8, eStore); |
| 301 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | /** |
| 305 | * Return true if and only if addr_expr matches the pattern (SP) or |
| 306 | * <offset>(SP). |
| 307 | */ |
| 308 | static Bool is_stack_access(IRSB* const bb, IRExpr* const addr_expr) |
| 309 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 310 | Bool result = False; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 311 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 312 | if (addr_expr->tag == Iex_RdTmp) |
| 313 | { |
| 314 | int i; |
| 315 | for (i = 0; i < bb->stmts_size; i++) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 316 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 317 | if (bb->stmts[i] |
| 318 | && bb->stmts[i]->tag == Ist_WrTmp |
| 319 | && bb->stmts[i]->Ist.WrTmp.tmp == addr_expr->Iex.RdTmp.tmp) |
| 320 | { |
| 321 | IRExpr* e = bb->stmts[i]->Ist.WrTmp.data; |
| 322 | if (e->tag == Iex_Get && e->Iex.Get.offset == STACK_POINTER_OFFSET) |
| 323 | { |
| 324 | result = True; |
| 325 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 326 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 327 | //ppIRExpr(e); |
| 328 | //VG_(printf)(" (%s)\n", result ? "True" : "False"); |
| 329 | break; |
| 330 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 331 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 332 | } |
| 333 | return result; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 334 | } |
| 335 | |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 336 | static const IROp u_widen_irop[5][9] = { |
bart | 9ad8d80 | 2011-12-12 19:54:32 +0000 | [diff] [blame] | 337 | [Ity_I1 - Ity_I1] = { [4] = Iop_1Uto32, [8] = Iop_1Uto64 }, |
| 338 | [Ity_I8 - Ity_I1] = { [4] = Iop_8Uto32, [8] = Iop_8Uto64 }, |
| 339 | [Ity_I16 - Ity_I1] = { [4] = Iop_16Uto32, [8] = Iop_16Uto64 }, |
| 340 | [Ity_I32 - Ity_I1] = { [8] = Iop_32Uto64 }, |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 341 | }; |
| 342 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 343 | /** |
| 344 | * Instrument the client code to trace a memory load (--trace-addr). |
| 345 | */ |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 346 | static IRExpr* instr_trace_mem_load(IRSB* const bb, IRExpr* addr_expr, |
| 347 | const HWord size) |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 348 | { |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 349 | IRTemp tmp; |
| 350 | |
| 351 | tmp = newIRTemp(bb->tyenv, typeOfIRExpr(bb->tyenv, addr_expr)); |
| 352 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, addr_expr)); |
| 353 | addr_expr = IRExpr_RdTmp(tmp); |
| 354 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 355 | addStmtToIRSB(bb, |
| 356 | IRStmt_Dirty( |
| 357 | unsafeIRDirty_0_N(/*regparms*/2, |
| 358 | "drd_trace_mem_load", |
| 359 | VG_(fnptr_to_fnentry) |
| 360 | (drd_trace_mem_load), |
| 361 | mkIRExprVec_2(addr_expr, mkIRExpr_HWord(size))))); |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 362 | |
| 363 | return addr_expr; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 364 | } |
| 365 | |
| 366 | /** |
| 367 | * Instrument the client code to trace a memory store (--trace-addr). |
| 368 | */ |
| 369 | static void instr_trace_mem_store(IRSB* const bb, IRExpr* const addr_expr, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 370 | IRExpr* data_expr_hi, IRExpr* data_expr_lo) |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 371 | { |
| 372 | IRType ty_data_expr; |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 373 | HWord size; |
| 374 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 375 | tl_assert(sizeof(HWord) == 4 || sizeof(HWord) == 8); |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 376 | tl_assert(!data_expr_hi || typeOfIRExpr(bb->tyenv, data_expr_hi) == Ity_I32); |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 377 | |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 378 | ty_data_expr = typeOfIRExpr(bb->tyenv, data_expr_lo); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 379 | size = sizeofIRType(ty_data_expr); |
| 380 | |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 381 | #if 0 |
| 382 | // Test code |
| 383 | if (ty_data_expr == Ity_I32) { |
| 384 | IRTemp tmp = newIRTemp(bb->tyenv, Ity_F32); |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 385 | data_expr_lo = IRExpr_Unop(Iop_ReinterpI32asF32, data_expr_lo); |
| 386 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, data_expr_lo)); |
| 387 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 388 | ty_data_expr = Ity_F32; |
| 389 | } else if (ty_data_expr == Ity_I64) { |
| 390 | IRTemp tmp = newIRTemp(bb->tyenv, Ity_F64); |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 391 | data_expr_lo = IRExpr_Unop(Iop_ReinterpI64asF64, data_expr_lo); |
| 392 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, data_expr_lo)); |
| 393 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 394 | ty_data_expr = Ity_F64; |
| 395 | } |
| 396 | #endif |
| 397 | |
| 398 | if (ty_data_expr == Ity_F32) { |
| 399 | IRTemp tmp = newIRTemp(bb->tyenv, Ity_I32); |
| 400 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, IRExpr_Unop(Iop_ReinterpF32asI32, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 401 | data_expr_lo))); |
| 402 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 403 | ty_data_expr = Ity_I32; |
| 404 | } else if (ty_data_expr == Ity_F64) { |
| 405 | IRTemp tmp = newIRTemp(bb->tyenv, Ity_I64); |
| 406 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, IRExpr_Unop(Iop_ReinterpF64asI64, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 407 | data_expr_lo))); |
| 408 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 409 | ty_data_expr = Ity_I64; |
| 410 | } |
| 411 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 412 | if (size == sizeof(HWord) |
| 413 | && (ty_data_expr == Ity_I32 || ty_data_expr == Ity_I64)) |
| 414 | { |
| 415 | /* No conversion necessary */ |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 416 | } else { |
| 417 | IROp widen_op; |
| 418 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 419 | if (Ity_I1 <= ty_data_expr |
| 420 | && ty_data_expr |
| 421 | < Ity_I1 + sizeof(u_widen_irop)/sizeof(u_widen_irop[0])) |
| 422 | { |
| 423 | widen_op = u_widen_irop[ty_data_expr - Ity_I1][sizeof(HWord)]; |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 424 | if (!widen_op) |
| 425 | widen_op = Iop_INVALID; |
| 426 | } else { |
| 427 | widen_op = Iop_INVALID; |
| 428 | } |
| 429 | if (widen_op != Iop_INVALID) { |
| 430 | IRTemp tmp; |
| 431 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 432 | /* Widen the integer expression to a HWord */ |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 433 | tmp = newIRTemp(bb->tyenv, sizeof(HWord) == 4 ? Ity_I32 : Ity_I64); |
| 434 | addStmtToIRSB(bb, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 435 | IRStmt_WrTmp(tmp, IRExpr_Unop(widen_op, data_expr_lo))); |
| 436 | data_expr_lo = IRExpr_RdTmp(tmp); |
| 437 | } else if (size > sizeof(HWord) && !data_expr_hi |
| 438 | && ty_data_expr == Ity_I64) { |
| 439 | IRTemp tmp; |
| 440 | |
| 441 | tl_assert(sizeof(HWord) == 4); |
| 442 | tl_assert(size == 8); |
| 443 | tmp = newIRTemp(bb->tyenv, Ity_I32); |
| 444 | addStmtToIRSB(bb, |
| 445 | IRStmt_WrTmp(tmp, |
| 446 | IRExpr_Unop(Iop_64HIto32, data_expr_lo))); |
| 447 | data_expr_hi = IRExpr_RdTmp(tmp); |
| 448 | tmp = newIRTemp(bb->tyenv, Ity_I32); |
| 449 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, |
| 450 | IRExpr_Unop(Iop_64to32, data_expr_lo))); |
| 451 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 452 | } else { |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 453 | data_expr_lo = mkIRExpr_HWord(0); |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 454 | } |
| 455 | } |
| 456 | addStmtToIRSB(bb, |
| 457 | IRStmt_Dirty( |
| 458 | unsafeIRDirty_0_N(/*regparms*/3, |
| 459 | "drd_trace_mem_store", |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 460 | VG_(fnptr_to_fnentry)(drd_trace_mem_store), |
| 461 | mkIRExprVec_4(addr_expr, mkIRExpr_HWord(size), |
| 462 | data_expr_hi ? data_expr_hi |
| 463 | : mkIRExpr_HWord(0), data_expr_lo)))); |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 464 | } |
| 465 | |
| 466 | static void instrument_load(IRSB* const bb, IRExpr* const addr_expr, |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 467 | const HWord size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 468 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 469 | IRExpr* size_expr; |
| 470 | IRExpr** argv; |
| 471 | IRDirty* di; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 472 | |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 473 | if (!s_check_stack_accesses && is_stack_access(bb, addr_expr)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 474 | return; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 475 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 476 | switch (size) |
| 477 | { |
| 478 | case 1: |
| 479 | argv = mkIRExprVec_1(addr_expr); |
| 480 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 481 | "drd_trace_load_1", |
| 482 | VG_(fnptr_to_fnentry)(drd_trace_load_1), |
| 483 | argv); |
| 484 | break; |
| 485 | case 2: |
| 486 | argv = mkIRExprVec_1(addr_expr); |
| 487 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 488 | "drd_trace_load_2", |
| 489 | VG_(fnptr_to_fnentry)(drd_trace_load_2), |
| 490 | argv); |
| 491 | break; |
| 492 | case 4: |
| 493 | argv = mkIRExprVec_1(addr_expr); |
| 494 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 495 | "drd_trace_load_4", |
| 496 | VG_(fnptr_to_fnentry)(drd_trace_load_4), |
| 497 | argv); |
| 498 | break; |
| 499 | case 8: |
| 500 | argv = mkIRExprVec_1(addr_expr); |
| 501 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 502 | "drd_trace_load_8", |
| 503 | VG_(fnptr_to_fnentry)(drd_trace_load_8), |
| 504 | argv); |
| 505 | break; |
| 506 | default: |
| 507 | size_expr = mkIRExpr_HWord(size); |
| 508 | argv = mkIRExprVec_2(addr_expr, size_expr); |
| 509 | di = unsafeIRDirty_0_N(/*regparms*/2, |
| 510 | "drd_trace_load", |
| 511 | VG_(fnptr_to_fnentry)(DRD_(trace_load)), |
| 512 | argv); |
| 513 | break; |
| 514 | } |
| 515 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 516 | } |
| 517 | |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 518 | static void instrument_store(IRSB* const bb, IRExpr* addr_expr, |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 519 | IRExpr* const data_expr) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 520 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 521 | IRExpr* size_expr; |
| 522 | IRExpr** argv; |
| 523 | IRDirty* di; |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 524 | HWord size; |
| 525 | |
| 526 | size = sizeofIRType(typeOfIRExpr(bb->tyenv, data_expr)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 527 | |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 528 | if (UNLIKELY(DRD_(any_address_is_traced)())) { |
| 529 | IRTemp tmp = newIRTemp(bb->tyenv, typeOfIRExpr(bb->tyenv, addr_expr)); |
| 530 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, addr_expr)); |
| 531 | addr_expr = IRExpr_RdTmp(tmp); |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 532 | instr_trace_mem_store(bb, addr_expr, NULL, data_expr); |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 533 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 534 | |
bart | 71ce132 | 2011-12-11 17:54:17 +0000 | [diff] [blame] | 535 | if (!s_check_stack_accesses && is_stack_access(bb, addr_expr)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 536 | return; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 537 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 538 | switch (size) |
| 539 | { |
| 540 | case 1: |
| 541 | argv = mkIRExprVec_1(addr_expr); |
| 542 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 543 | "drd_trace_store_1", |
| 544 | VG_(fnptr_to_fnentry)(drd_trace_store_1), |
| 545 | argv); |
| 546 | break; |
| 547 | case 2: |
| 548 | argv = mkIRExprVec_1(addr_expr); |
| 549 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 550 | "drd_trace_store_2", |
| 551 | VG_(fnptr_to_fnentry)(drd_trace_store_2), |
| 552 | argv); |
| 553 | break; |
| 554 | case 4: |
| 555 | argv = mkIRExprVec_1(addr_expr); |
| 556 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 557 | "drd_trace_store_4", |
| 558 | VG_(fnptr_to_fnentry)(drd_trace_store_4), |
| 559 | argv); |
| 560 | break; |
| 561 | case 8: |
| 562 | argv = mkIRExprVec_1(addr_expr); |
| 563 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 564 | "drd_trace_store_8", |
| 565 | VG_(fnptr_to_fnentry)(drd_trace_store_8), |
| 566 | argv); |
| 567 | break; |
| 568 | default: |
| 569 | size_expr = mkIRExpr_HWord(size); |
| 570 | argv = mkIRExprVec_2(addr_expr, size_expr); |
| 571 | di = unsafeIRDirty_0_N(/*regparms*/2, |
| 572 | "drd_trace_store", |
| 573 | VG_(fnptr_to_fnentry)(DRD_(trace_store)), |
| 574 | argv); |
| 575 | break; |
| 576 | } |
| 577 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 578 | } |
| 579 | |
bart | 1335ecc | 2009-02-14 16:10:53 +0000 | [diff] [blame] | 580 | IRSB* DRD_(instrument)(VgCallbackClosure* const closure, |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 581 | IRSB* const bb_in, |
| 582 | VexGuestLayout* const layout, |
bart | 31b983d | 2010-02-21 14:52:59 +0000 | [diff] [blame] | 583 | VexGuestExtents* const vge, |
florian | ca503be | 2012-10-07 21:59:42 +0000 | [diff] [blame] | 584 | VexArchInfo* archinfo_host, |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 585 | IRType const gWordTy, |
| 586 | IRType const hWordTy) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 587 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 588 | IRDirty* di; |
| 589 | Int i; |
| 590 | IRSB* bb; |
| 591 | IRExpr** argv; |
| 592 | Bool instrument = True; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 593 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 594 | /* Set up BB */ |
| 595 | bb = emptyIRSB(); |
| 596 | bb->tyenv = deepCopyIRTypeEnv(bb_in->tyenv); |
| 597 | bb->next = deepCopyIRExpr(bb_in->next); |
| 598 | bb->jumpkind = bb_in->jumpkind; |
sewardj | 291849f | 2012-04-20 23:58:55 +0000 | [diff] [blame] | 599 | bb->offsIP = bb_in->offsIP; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 600 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 601 | for (i = 0; i < bb_in->stmts_used; i++) |
| 602 | { |
| 603 | IRStmt* const st = bb_in->stmts[i]; |
| 604 | tl_assert(st); |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 605 | tl_assert(isFlatIRStmt(st)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 606 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 607 | switch (st->tag) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 608 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 609 | /* Note: the code for not instrumenting the code in .plt */ |
| 610 | /* sections is only necessary on CentOS 3.0 x86 (kernel 2.4.21 */ |
| 611 | /* + glibc 2.3.2 + NPTL 0.60 + binutils 2.14.90.0.4). */ |
| 612 | /* This is because on this platform dynamic library symbols are */ |
| 613 | /* relocated in another way than by later binutils versions. The */ |
| 614 | /* linker e.g. does not generate .got.plt sections on CentOS 3.0. */ |
| 615 | case Ist_IMark: |
sewardj | e3f1e59 | 2009-07-31 09:41:29 +0000 | [diff] [blame] | 616 | instrument = VG_(DebugInfo_sect_kind)(NULL, 0, st->Ist.IMark.addr) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 617 | != Vg_SectPLT; |
| 618 | addStmtToIRSB(bb, st); |
| 619 | break; |
| 620 | |
| 621 | case Ist_MBE: |
| 622 | switch (st->Ist.MBE.event) |
| 623 | { |
| 624 | case Imbe_Fence: |
| 625 | break; /* not interesting */ |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 626 | default: |
| 627 | tl_assert(0); |
| 628 | } |
| 629 | addStmtToIRSB(bb, st); |
| 630 | break; |
| 631 | |
| 632 | case Ist_Store: |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 633 | if (instrument) |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 634 | instrument_store(bb, st->Ist.Store.addr, st->Ist.Store.data); |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 635 | addStmtToIRSB(bb, st); |
| 636 | break; |
| 637 | |
| 638 | case Ist_WrTmp: |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 639 | if (instrument) { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 640 | const IRExpr* const data = st->Ist.WrTmp.data; |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 641 | IRExpr* addr_expr = data->Iex.Load.addr; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 642 | if (data->tag == Iex_Load) { |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 643 | if (UNLIKELY(DRD_(any_address_is_traced)())) { |
| 644 | addr_expr = instr_trace_mem_load(bb, addr_expr, |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 645 | sizeofIRType(data->Iex.Load.ty)); |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 646 | } |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 647 | instrument_load(bb, data->Iex.Load.addr, |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 648 | sizeofIRType(data->Iex.Load.ty)); |
| 649 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 650 | } |
| 651 | addStmtToIRSB(bb, st); |
| 652 | break; |
| 653 | |
| 654 | case Ist_Dirty: |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 655 | if (instrument) { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 656 | IRDirty* d = st->Ist.Dirty.details; |
| 657 | IREffect const mFx = d->mFx; |
| 658 | switch (mFx) { |
| 659 | case Ifx_None: |
| 660 | break; |
| 661 | case Ifx_Read: |
| 662 | case Ifx_Write: |
| 663 | case Ifx_Modify: |
| 664 | tl_assert(d->mAddr); |
| 665 | tl_assert(d->mSize > 0); |
| 666 | argv = mkIRExprVec_2(d->mAddr, mkIRExpr_HWord(d->mSize)); |
| 667 | if (mFx == Ifx_Read || mFx == Ifx_Modify) { |
| 668 | di = unsafeIRDirty_0_N( |
| 669 | /*regparms*/2, |
| 670 | "drd_trace_load", |
| 671 | VG_(fnptr_to_fnentry)(DRD_(trace_load)), |
| 672 | argv); |
| 673 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
| 674 | } |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 675 | if (mFx == Ifx_Write || mFx == Ifx_Modify) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 676 | { |
| 677 | di = unsafeIRDirty_0_N( |
| 678 | /*regparms*/2, |
| 679 | "drd_trace_store", |
| 680 | VG_(fnptr_to_fnentry)(DRD_(trace_store)), |
| 681 | argv); |
| 682 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
| 683 | } |
| 684 | break; |
| 685 | default: |
| 686 | tl_assert(0); |
| 687 | } |
| 688 | } |
| 689 | addStmtToIRSB(bb, st); |
| 690 | break; |
| 691 | |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 692 | case Ist_CAS: |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 693 | if (instrument) { |
bart | a14e328 | 2009-07-11 14:35:59 +0000 | [diff] [blame] | 694 | /* |
| 695 | * Treat compare-and-swap as a read. By handling atomic |
| 696 | * instructions as read instructions no data races are reported |
| 697 | * between conflicting atomic operations nor between atomic |
| 698 | * operations and non-atomic reads. Conflicts between atomic |
| 699 | * operations and non-atomic write operations are still reported |
| 700 | * however. |
| 701 | */ |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 702 | Int dataSize; |
| 703 | IRCAS* cas = st->Ist.CAS.details; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 704 | |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 705 | tl_assert(cas->addr != NULL); |
| 706 | tl_assert(cas->dataLo != NULL); |
| 707 | dataSize = sizeofIRType(typeOfIRExpr(bb->tyenv, cas->dataLo)); |
| 708 | if (cas->dataHi != NULL) |
| 709 | dataSize *= 2; /* since it's a doubleword-CAS */ |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 710 | |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 711 | if (UNLIKELY(DRD_(any_address_is_traced)())) |
| 712 | instr_trace_mem_store(bb, cas->addr, cas->dataHi, cas->dataLo); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 713 | |
| 714 | instrument_load(bb, cas->addr, dataSize); |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 715 | } |
| 716 | addStmtToIRSB(bb, st); |
| 717 | break; |
| 718 | |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 719 | case Ist_LLSC: { |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 720 | /* |
| 721 | * Ignore store-conditionals (except for tracing), and handle |
| 722 | * load-linked's exactly like normal loads. |
| 723 | */ |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 724 | IRType dataTy; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 725 | |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 726 | if (st->Ist.LLSC.storedata == NULL) { |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 727 | /* LL */ |
| 728 | dataTy = typeOfIRTemp(bb_in->tyenv, st->Ist.LLSC.result); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 729 | if (instrument) { |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 730 | IRExpr* addr_expr = st->Ist.LLSC.addr; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 731 | if (UNLIKELY(DRD_(any_address_is_traced)())) |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 732 | addr_expr = instr_trace_mem_load(bb, addr_expr, |
| 733 | sizeofIRType(dataTy)); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 734 | |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame] | 735 | instrument_load(bb, addr_expr, sizeofIRType(dataTy)); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 736 | } |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 737 | } else { |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 738 | /* SC */ |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 739 | instr_trace_mem_store(bb, st->Ist.LLSC.addr, NULL, |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 740 | st->Ist.LLSC.storedata); |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 741 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 742 | addStmtToIRSB(bb, st); |
| 743 | break; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 744 | } |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 745 | |
| 746 | case Ist_NoOp: |
| 747 | case Ist_AbiHint: |
| 748 | case Ist_Put: |
| 749 | case Ist_PutI: |
| 750 | case Ist_Exit: |
| 751 | /* None of these can contain any memory references. */ |
| 752 | addStmtToIRSB(bb, st); |
| 753 | break; |
| 754 | |
| 755 | default: |
| 756 | ppIRStmt(st); |
| 757 | tl_assert(0); |
| 758 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 759 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 760 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 761 | return bb; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 762 | } |
| 763 | |