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weidendoa17f2a32006-03-20 10:27:30 +00001/*--------------------------------------------------------------------*/
2/*--- Cache simulation. ---*/
3/*--- sim.c ---*/
4/*--------------------------------------------------------------------*/
5
6/*
njn9a0cba42007-04-15 22:15:57 +00007 This file is part of Callgrind, a Valgrind tool for call graph
8 profiling programs.
weidendoa17f2a32006-03-20 10:27:30 +00009
weidendo5bba5252010-06-09 22:32:53 +000010 Copyright (C) 2003-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
weidendoa17f2a32006-03-20 10:27:30 +000011
njn9a0cba42007-04-15 22:15:57 +000012 This tool is derived from and contains code from Cachegrind
sewardj9eecbbb2010-05-03 21:37:12 +000013 Copyright (C) 2002-2010 Nicholas Nethercote (njn@valgrind.org)
weidendoa17f2a32006-03-20 10:27:30 +000014
15 This program is free software; you can redistribute it and/or
16 modify it under the terms of the GNU General Public License as
17 published by the Free Software Foundation; either version 2 of the
18 License, or (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful, but
21 WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the Free Software
27 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
28 02111-1307, USA.
29
30 The GNU General Public License is contained in the file COPYING.
31*/
32
33#include "global.h"
34
35
36/* Notes:
37 - simulates a write-allocate cache
38 - (block --> set) hash function uses simple bit selection
39 - handling of references straddling two cache blocks:
40 - counts as only one cache access (not two)
41 - both blocks hit --> one hit
42 - one block hits, the other misses --> one miss
43 - both blocks miss --> one miss (not two)
44*/
45
46/* Cache configuration */
47#include "cg_arch.h"
48
49/* additional structures for cache use info, separated
50 * according usage frequency:
51 * - line_loaded : pointer to cost center of instruction
52 * which loaded the line into cache.
53 * Needed to increment counters when line is evicted.
54 * - line_use : updated on every access
55 */
56typedef struct {
57 UInt count;
58 UInt mask; /* e.g. for 64Byte line size 1bit/2Byte */
59} line_use;
60
61typedef struct {
62 Addr memline, iaddr;
63 line_use* dep_use; /* point to higher-level cacheblock for this memline */
64 ULong* use_base;
65} line_loaded;
66
67/* Cache state */
68typedef struct {
69 char* name;
70 int size; /* bytes */
71 int assoc;
72 int line_size; /* bytes */
73 Bool sectored; /* prefetch nearside cacheline on read */
74 int sets;
75 int sets_min_1;
weidendoa17f2a32006-03-20 10:27:30 +000076 int line_size_bits;
77 int tag_shift;
78 UWord tag_mask;
79 char desc_line[128];
80 UWord* tags;
81
82 /* for cache use */
83 int line_size_mask;
84 int* line_start_mask;
85 int* line_end_mask;
86 line_loaded* loaded;
87 line_use* use;
88} cache_t2;
89
90/*
91 * States of flat caches in our model.
92 * We use a 2-level hierarchy,
93 */
94static cache_t2 I1, D1, L2;
95
96/* Lower bits of cache tags are used as flags for a cache line */
97#define CACHELINE_FLAGMASK (MIN_LINE_SIZE-1)
98#define CACHELINE_DIRTY 1
99
100
101/* Cache simulator Options */
102static Bool clo_simulate_writeback = False;
103static Bool clo_simulate_hwpref = False;
104static Bool clo_simulate_sectors = False;
105static Bool clo_collect_cacheuse = False;
106
weidendo75a5c2d2010-06-09 22:32:58 +0000107/* Following global vars are setup before by setup_bbcc():
weidendoa17f2a32006-03-20 10:27:30 +0000108 *
weidendo75a5c2d2010-06-09 22:32:58 +0000109 * - Addr CLG_(bb_base) (instruction start address of original BB)
110 * - ULong* CLG_(cost_base) (start of cost array for BB)
weidendoa17f2a32006-03-20 10:27:30 +0000111 */
112
weidendo75a5c2d2010-06-09 22:32:58 +0000113Addr CLG_(bb_base);
114ULong* CLG_(cost_base);
115
weidendoa17f2a32006-03-20 10:27:30 +0000116static InstrInfo* current_ii;
117
118/* Cache use offsets */
weidendo0a1951d2009-06-15 00:16:36 +0000119/* The offsets are only correct because all per-instruction event sets get
weidendoa17f2a32006-03-20 10:27:30 +0000120 * the "Use" set added first !
121 */
122static Int off_I1_AcCost = 0;
123static Int off_I1_SpLoss = 1;
124static Int off_D1_AcCost = 0;
125static Int off_D1_SpLoss = 1;
126static Int off_L2_AcCost = 2;
127static Int off_L2_SpLoss = 3;
128
129/* Cache access types */
130typedef enum { Read = 0, Write = CACHELINE_DIRTY } RefType;
131
132/* Result of a reference into a flat cache */
133typedef enum { Hit = 0, Miss, MissDirty } CacheResult;
134
135/* Result of a reference into a hierarchical cache model */
136typedef enum {
137 L1_Hit,
138 L2_Hit,
139 MemAccess,
140 WriteBackMemAccess } CacheModelResult;
141
142typedef CacheModelResult (*simcall_type)(Addr, UChar);
143
144static struct {
145 simcall_type I1_Read;
146 simcall_type D1_Read;
147 simcall_type D1_Write;
148} simulator;
149
150/*------------------------------------------------------------*/
151/*--- Cache Simulator Initialization ---*/
152/*------------------------------------------------------------*/
153
154static void cachesim_clearcache(cache_t2* c)
155{
156 Int i;
157
158 for (i = 0; i < c->sets * c->assoc; i++)
159 c->tags[i] = 0;
160 if (c->use) {
161 for (i = 0; i < c->sets * c->assoc; i++) {
162 c->loaded[i].memline = 0;
163 c->loaded[i].use_base = 0;
164 c->loaded[i].dep_use = 0;
165 c->loaded[i].iaddr = 0;
166 c->use[i].mask = 0;
167 c->use[i].count = 0;
168 c->tags[i] = i % c->assoc; /* init lower bits as pointer */
169 }
170 }
171}
172
173static void cacheuse_initcache(cache_t2* c);
174
175/* By this point, the size/assoc/line_size has been checked. */
176static void cachesim_initcache(cache_t config, cache_t2* c)
177{
178 c->size = config.size;
179 c->assoc = config.assoc;
180 c->line_size = config.line_size;
181 c->sectored = False; // FIXME
182
183 c->sets = (c->size / c->line_size) / c->assoc;
184 c->sets_min_1 = c->sets - 1;
weidendoa17f2a32006-03-20 10:27:30 +0000185 c->line_size_bits = VG_(log2)(c->line_size);
186 c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
187 c->tag_mask = ~((1<<c->tag_shift)-1);
188
189 /* Can bits in tag entries be used for flags?
190 * Should be always true as MIN_LINE_SIZE >= 16 */
191 CLG_ASSERT( (c->tag_mask & CACHELINE_FLAGMASK) == 0);
192
193 if (c->assoc == 1) {
194 VG_(sprintf)(c->desc_line, "%d B, %d B, direct-mapped%s",
195 c->size, c->line_size,
196 c->sectored ? ", sectored":"");
197 } else {
198 VG_(sprintf)(c->desc_line, "%d B, %d B, %d-way associative%s",
199 c->size, c->line_size, c->assoc,
200 c->sectored ? ", sectored":"");
201 }
202
sewardj9c606bd2008-09-18 18:12:50 +0000203 c->tags = (UWord*) CLG_MALLOC("cl.sim.cs_ic.1",
204 sizeof(UWord) * c->sets * c->assoc);
weidendoa17f2a32006-03-20 10:27:30 +0000205 if (clo_collect_cacheuse)
206 cacheuse_initcache(c);
207 else
208 c->use = 0;
209 cachesim_clearcache(c);
210}
211
212
213#if 0
214static void print_cache(cache_t2* c)
215{
216 UInt set, way, i;
217
218 /* Note initialisation and update of 'i'. */
219 for (i = 0, set = 0; set < c->sets; set++) {
220 for (way = 0; way < c->assoc; way++, i++) {
221 VG_(printf)("%8x ", c->tags[i]);
222 }
223 VG_(printf)("\n");
224 }
225}
226#endif
227
228
229/*------------------------------------------------------------*/
230/*--- Write Through Cache Simulation ---*/
231/*------------------------------------------------------------*/
232
233/*
234 * Simple model: L1 & L2 Write Through
235 * Does not distinguish among read and write references
236 *
237 * Simulator functions:
238 * CacheModelResult cachesim_I1_ref(Addr a, UChar size)
239 * CacheModelResult cachesim_D1_ref(Addr a, UChar size)
240 */
241
242static __inline__
243CacheResult cachesim_setref(cache_t2* c, UInt set_no, UWord tag)
244{
245 int i, j;
246 UWord *set;
247
weidendo144b76c2009-01-26 22:56:14 +0000248 set = &(c->tags[set_no * c->assoc]);
weidendoa17f2a32006-03-20 10:27:30 +0000249
250 /* This loop is unrolled for just the first case, which is the most */
251 /* common. We can't unroll any further because it would screw up */
252 /* if we have a direct-mapped (1-way) cache. */
253 if (tag == set[0])
254 return Hit;
255
256 /* If the tag is one other than the MRU, move it into the MRU spot */
257 /* and shuffle the rest down. */
258 for (i = 1; i < c->assoc; i++) {
259 if (tag == set[i]) {
260 for (j = i; j > 0; j--) {
261 set[j] = set[j - 1];
262 }
263 set[0] = tag;
264 return Hit;
265 }
266 }
267
268 /* A miss; install this tag as MRU, shuffle rest down. */
269 for (j = c->assoc - 1; j > 0; j--) {
270 set[j] = set[j - 1];
271 }
272 set[0] = tag;
273
274 return Miss;
275}
276
277static CacheResult cachesim_ref(cache_t2* c, Addr a, UChar size)
278{
279 UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
280 UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
281 UWord tag = a >> c->tag_shift;
282
283 /* Access entirely within line. */
284 if (set1 == set2)
285 return cachesim_setref(c, set1, tag);
286
287 /* Access straddles two lines. */
288 /* Nb: this is a fast way of doing ((set1+1) % c->sets) */
289 else if (((set1 + 1) & (c->sets-1)) == set2) {
weidendo28e2a142006-11-22 21:00:53 +0000290 UWord tag2 = (a+size-1) >> c->tag_shift;
weidendoa17f2a32006-03-20 10:27:30 +0000291
292 /* the call updates cache structures as side effect */
293 CacheResult res1 = cachesim_setref(c, set1, tag);
weidendo28e2a142006-11-22 21:00:53 +0000294 CacheResult res2 = cachesim_setref(c, set2, tag2);
weidendoa17f2a32006-03-20 10:27:30 +0000295 return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit;
296
297 } else {
njn8a7b41b2007-09-23 00:51:24 +0000298 VG_(printf)("addr: %lx size: %u sets: %d %d", a, size, set1, set2);
weidendoa17f2a32006-03-20 10:27:30 +0000299 VG_(tool_panic)("item straddles more than two cache sets");
300 }
301 return Hit;
302}
303
304static
305CacheModelResult cachesim_I1_ref(Addr a, UChar size)
306{
307 if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;
308 if ( cachesim_ref( &L2, a, size) == Hit ) return L2_Hit;
309 return MemAccess;
310}
311
312static
313CacheModelResult cachesim_D1_ref(Addr a, UChar size)
314{
315 if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;
316 if ( cachesim_ref( &L2, a, size) == Hit ) return L2_Hit;
317 return MemAccess;
318}
319
320
321/*------------------------------------------------------------*/
322/*--- Write Back Cache Simulation ---*/
323/*------------------------------------------------------------*/
324
325/*
326 * More complex model: L1 Write-through, L2 Write-back
327 * This needs to distinguish among read and write references.
328 *
329 * Simulator functions:
330 * CacheModelResult cachesim_I1_Read(Addr a, UChar size)
331 * CacheModelResult cachesim_D1_Read(Addr a, UChar size)
332 * CacheModelResult cachesim_D1_Write(Addr a, UChar size)
333 */
334
335/*
336 * With write-back, result can be a miss evicting a dirty line
337 * The dirty state of a cache line is stored in Bit0 of the tag for
338 * this cache line (CACHELINE_DIRTY = 1). By OR'ing the reference
339 * type (Read/Write), the line gets dirty on a write.
340 */
341static __inline__
342CacheResult cachesim_setref_wb(cache_t2* c, RefType ref, UInt set_no, UWord tag)
343{
344 int i, j;
345 UWord *set, tmp_tag;
346
weidendo144b76c2009-01-26 22:56:14 +0000347 set = &(c->tags[set_no * c->assoc]);
weidendoa17f2a32006-03-20 10:27:30 +0000348
349 /* This loop is unrolled for just the first case, which is the most */
350 /* common. We can't unroll any further because it would screw up */
351 /* if we have a direct-mapped (1-way) cache. */
352 if (tag == (set[0] & ~CACHELINE_DIRTY)) {
353 set[0] |= ref;
354 return Hit;
355 }
356 /* If the tag is one other than the MRU, move it into the MRU spot */
357 /* and shuffle the rest down. */
358 for (i = 1; i < c->assoc; i++) {
359 if (tag == (set[i] & ~CACHELINE_DIRTY)) {
360 tmp_tag = set[i] | ref; // update dirty flag
361 for (j = i; j > 0; j--) {
362 set[j] = set[j - 1];
363 }
364 set[0] = tmp_tag;
365 return Hit;
366 }
367 }
368
369 /* A miss; install this tag as MRU, shuffle rest down. */
370 tmp_tag = set[c->assoc - 1];
371 for (j = c->assoc - 1; j > 0; j--) {
372 set[j] = set[j - 1];
373 }
374 set[0] = tag | ref;
375
376 return (tmp_tag & CACHELINE_DIRTY) ? MissDirty : Miss;
377}
378
379
380static __inline__
381CacheResult cachesim_ref_wb(cache_t2* c, RefType ref, Addr a, UChar size)
382{
383 UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
384 UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
385 UWord tag = a & c->tag_mask;
386
387 /* Access entirely within line. */
388 if (set1 == set2)
389 return cachesim_setref_wb(c, ref, set1, tag);
390
391 /* Access straddles two lines. */
392 /* Nb: this is a fast way of doing ((set1+1) % c->sets) */
393 else if (((set1 + 1) & (c->sets-1)) == set2) {
weidendo144b76c2009-01-26 22:56:14 +0000394 UWord tag2 = (a+size-1) & c->tag_mask;
weidendoa17f2a32006-03-20 10:27:30 +0000395
396 /* the call updates cache structures as side effect */
397 CacheResult res1 = cachesim_setref_wb(c, ref, set1, tag);
weidendo28e2a142006-11-22 21:00:53 +0000398 CacheResult res2 = cachesim_setref_wb(c, ref, set2, tag2);
weidendoa17f2a32006-03-20 10:27:30 +0000399
400 if ((res1 == MissDirty) || (res2 == MissDirty)) return MissDirty;
401 return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit;
402
403 } else {
njn8a7b41b2007-09-23 00:51:24 +0000404 VG_(printf)("addr: %lx size: %u sets: %d %d", a, size, set1, set2);
weidendoa17f2a32006-03-20 10:27:30 +0000405 VG_(tool_panic)("item straddles more than two cache sets");
406 }
407 return Hit;
408}
409
410
411static
412CacheModelResult cachesim_I1_Read(Addr a, UChar size)
413{
414 if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;
415 switch( cachesim_ref_wb( &L2, Read, a, size) ) {
416 case Hit: return L2_Hit;
417 case Miss: return MemAccess;
418 default: break;
419 }
420 return WriteBackMemAccess;
421}
422
423static
424CacheModelResult cachesim_D1_Read(Addr a, UChar size)
425{
426 if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;
427 switch( cachesim_ref_wb( &L2, Read, a, size) ) {
428 case Hit: return L2_Hit;
429 case Miss: return MemAccess;
430 default: break;
431 }
432 return WriteBackMemAccess;
433}
434
435static
436CacheModelResult cachesim_D1_Write(Addr a, UChar size)
437{
438 if ( cachesim_ref( &D1, a, size) == Hit ) {
439 /* Even for a L1 hit, the write-trough L1 passes
440 * the write to the L2 to make the L2 line dirty.
441 * But this causes no latency, so return the hit.
442 */
443 cachesim_ref_wb( &L2, Write, a, size);
444 return L1_Hit;
445 }
446 switch( cachesim_ref_wb( &L2, Write, a, size) ) {
447 case Hit: return L2_Hit;
448 case Miss: return MemAccess;
449 default: break;
450 }
451 return WriteBackMemAccess;
452}
453
454
455/*------------------------------------------------------------*/
456/*--- Hardware Prefetch Simulation ---*/
457/*------------------------------------------------------------*/
458
459static ULong prefetch_up = 0;
460static ULong prefetch_down = 0;
461
462#define PF_STREAMS 8
463#define PF_PAGEBITS 12
464
465static UInt pf_lastblock[PF_STREAMS];
466static Int pf_seqblocks[PF_STREAMS];
467
468static
469void prefetch_clear(void)
470{
471 int i;
472 for(i=0;i<PF_STREAMS;i++)
473 pf_lastblock[i] = pf_seqblocks[i] = 0;
474}
475
476/*
477 * HW Prefetch emulation
478 * Start prefetching when detecting sequential access to 3 memory blocks.
479 * One stream can be detected per 4k page.
480 */
481static __inline__
weidendo09ee78e2009-02-24 12:26:53 +0000482void prefetch_L2_doref(Addr a)
weidendoa17f2a32006-03-20 10:27:30 +0000483{
484 UInt stream = (a >> PF_PAGEBITS) % PF_STREAMS;
485 UInt block = ( a >> L2.line_size_bits);
486
487 if (block != pf_lastblock[stream]) {
488 if (pf_seqblocks[stream] == 0) {
489 if (pf_lastblock[stream] +1 == block) pf_seqblocks[stream]++;
490 else if (pf_lastblock[stream] -1 == block) pf_seqblocks[stream]--;
491 }
492 else if (pf_seqblocks[stream] >0) {
493 if (pf_lastblock[stream] +1 == block) {
494 pf_seqblocks[stream]++;
495 if (pf_seqblocks[stream] >= 2) {
496 prefetch_up++;
497 cachesim_ref(&L2, a + 5 * L2.line_size,1);
498 }
499 }
500 else pf_seqblocks[stream] = 0;
501 }
502 else if (pf_seqblocks[stream] <0) {
503 if (pf_lastblock[stream] -1 == block) {
504 pf_seqblocks[stream]--;
505 if (pf_seqblocks[stream] <= -2) {
506 prefetch_down++;
507 cachesim_ref(&L2, a - 5 * L2.line_size,1);
508 }
509 }
510 else pf_seqblocks[stream] = 0;
511 }
512 pf_lastblock[stream] = block;
513 }
514}
515
516/* simple model with hardware prefetch */
517
518static
519CacheModelResult prefetch_I1_ref(Addr a, UChar size)
520{
521 if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;
weidendo09ee78e2009-02-24 12:26:53 +0000522 prefetch_L2_doref(a);
weidendoa17f2a32006-03-20 10:27:30 +0000523 if ( cachesim_ref( &L2, a, size) == Hit ) return L2_Hit;
524 return MemAccess;
525}
526
527static
528CacheModelResult prefetch_D1_ref(Addr a, UChar size)
529{
530 if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;
weidendo09ee78e2009-02-24 12:26:53 +0000531 prefetch_L2_doref(a);
weidendoa17f2a32006-03-20 10:27:30 +0000532 if ( cachesim_ref( &L2, a, size) == Hit ) return L2_Hit;
533 return MemAccess;
534}
535
536
537/* complex model with hardware prefetch */
538
539static
540CacheModelResult prefetch_I1_Read(Addr a, UChar size)
541{
542 if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;
weidendo09ee78e2009-02-24 12:26:53 +0000543 prefetch_L2_doref(a);
weidendoa17f2a32006-03-20 10:27:30 +0000544 switch( cachesim_ref_wb( &L2, Read, a, size) ) {
545 case Hit: return L2_Hit;
546 case Miss: return MemAccess;
547 default: break;
548 }
549 return WriteBackMemAccess;
550}
551
552static
553CacheModelResult prefetch_D1_Read(Addr a, UChar size)
554{
555 if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;
weidendo09ee78e2009-02-24 12:26:53 +0000556 prefetch_L2_doref(a);
weidendoa17f2a32006-03-20 10:27:30 +0000557 switch( cachesim_ref_wb( &L2, Read, a, size) ) {
558 case Hit: return L2_Hit;
559 case Miss: return MemAccess;
560 default: break;
561 }
562 return WriteBackMemAccess;
563}
564
565static
566CacheModelResult prefetch_D1_Write(Addr a, UChar size)
567{
weidendo09ee78e2009-02-24 12:26:53 +0000568 prefetch_L2_doref(a);
weidendoa17f2a32006-03-20 10:27:30 +0000569 if ( cachesim_ref( &D1, a, size) == Hit ) {
570 /* Even for a L1 hit, the write-trough L1 passes
571 * the write to the L2 to make the L2 line dirty.
572 * But this causes no latency, so return the hit.
573 */
574 cachesim_ref_wb( &L2, Write, a, size);
575 return L1_Hit;
576 }
577 switch( cachesim_ref_wb( &L2, Write, a, size) ) {
578 case Hit: return L2_Hit;
579 case Miss: return MemAccess;
580 default: break;
581 }
582 return WriteBackMemAccess;
583}
584
585
586/*------------------------------------------------------------*/
587/*--- Cache Simulation with use metric collection ---*/
588/*------------------------------------------------------------*/
589
590/* can not be combined with write-back or prefetch */
591
592static
593void cacheuse_initcache(cache_t2* c)
594{
595 int i;
596 unsigned int start_mask, start_val;
597 unsigned int end_mask, end_val;
598
sewardj9c606bd2008-09-18 18:12:50 +0000599 c->use = CLG_MALLOC("cl.sim.cu_ic.1",
600 sizeof(line_use) * c->sets * c->assoc);
601 c->loaded = CLG_MALLOC("cl.sim.cu_ic.2",
602 sizeof(line_loaded) * c->sets * c->assoc);
603 c->line_start_mask = CLG_MALLOC("cl.sim.cu_ic.3",
604 sizeof(int) * c->line_size);
605 c->line_end_mask = CLG_MALLOC("cl.sim.cu_ic.4",
606 sizeof(int) * c->line_size);
weidendoa17f2a32006-03-20 10:27:30 +0000607
weidendoa17f2a32006-03-20 10:27:30 +0000608 c->line_size_mask = c->line_size-1;
609
610 /* Meaning of line_start_mask/line_end_mask
611 * Example: for a given cache line, you get an access starting at
612 * byte offset 5, length 4, byte 5 - 8 was touched. For a cache
613 * line size of 32, you have 1 bit per byte in the mask:
614 *
615 * bit31 bit8 bit5 bit 0
616 * | | | |
617 * 11..111111100000 line_start_mask[5]
618 * 00..000111111111 line_end_mask[(5+4)-1]
619 *
620 * use_mask |= line_start_mask[5] && line_end_mask[8]
621 *
622 */
623 start_val = end_val = ~0;
624 if (c->line_size < 32) {
625 int bits_per_byte = 32/c->line_size;
626 start_mask = (1<<bits_per_byte)-1;
627 end_mask = start_mask << (32-bits_per_byte);
628 for(i=0;i<c->line_size;i++) {
629 c->line_start_mask[i] = start_val;
630 start_val = start_val & ~start_mask;
631 start_mask = start_mask << bits_per_byte;
632
633 c->line_end_mask[c->line_size-i-1] = end_val;
634 end_val = end_val & ~end_mask;
635 end_mask = end_mask >> bits_per_byte;
636 }
637 }
638 else {
639 int bytes_per_bit = c->line_size/32;
640 start_mask = 1;
641 end_mask = 1 << 31;
642 for(i=0;i<c->line_size;i++) {
643 c->line_start_mask[i] = start_val;
644 c->line_end_mask[c->line_size-i-1] = end_val;
645 if ( ((i+1)%bytes_per_bit) == 0) {
646 start_val &= ~start_mask;
647 end_val &= ~end_mask;
648 start_mask <<= 1;
649 end_mask >>= 1;
650 }
651 }
652 }
653
654 CLG_DEBUG(6, "Config %s:\n", c->desc_line);
655 for(i=0;i<c->line_size;i++) {
656 CLG_DEBUG(6, " [%2d]: start mask %8x, end mask %8x\n",
657 i, c->line_start_mask[i], c->line_end_mask[i]);
658 }
659
660 /* We use lower tag bits as offset pointers to cache use info.
661 * I.e. some cache parameters don't work.
662 */
weidendo144b76c2009-01-26 22:56:14 +0000663 if ( (1<<c->tag_shift) < c->assoc) {
weidendoa17f2a32006-03-20 10:27:30 +0000664 VG_(message)(Vg_DebugMsg,
sewardj0f33adf2009-07-15 14:51:03 +0000665 "error: Use associativity < %d for cache use statistics!\n",
weidendoa17f2a32006-03-20 10:27:30 +0000666 (1<<c->tag_shift) );
667 VG_(tool_panic)("Unsupported cache configuration");
668 }
669}
670
weidendoa17f2a32006-03-20 10:27:30 +0000671
672/* for I1/D1 caches */
673#define CACHEUSE(L) \
674 \
675static CacheModelResult cacheuse##_##L##_doRead(Addr a, UChar size) \
676{ \
weidendo28e2a142006-11-22 21:00:53 +0000677 UInt set1 = ( a >> L.line_size_bits) & (L.sets_min_1); \
678 UInt set2 = ((a+size-1) >> L.line_size_bits) & (L.sets_min_1); \
679 UWord tag = a & L.tag_mask; \
680 UWord tag2; \
weidendoa17f2a32006-03-20 10:27:30 +0000681 int i, j, idx; \
682 UWord *set, tmp_tag; \
683 UInt use_mask; \
684 \
barta0b6b2c2008-07-07 06:49:24 +0000685 CLG_DEBUG(6,"%s.Acc(Addr %#lx, size %d): Sets [%d/%d]\n", \
weidendoa17f2a32006-03-20 10:27:30 +0000686 L.name, a, size, set1, set2); \
687 \
688 /* First case: word entirely within line. */ \
689 if (set1 == set2) { \
690 \
weidendo144b76c2009-01-26 22:56:14 +0000691 set = &(L.tags[set1 * L.assoc]); \
weidendoa17f2a32006-03-20 10:27:30 +0000692 use_mask = L.line_start_mask[a & L.line_size_mask] & \
693 L.line_end_mask[(a+size-1) & L.line_size_mask]; \
694 \
695 /* This loop is unrolled for just the first case, which is the most */\
696 /* common. We can't unroll any further because it would screw up */\
697 /* if we have a direct-mapped (1-way) cache. */\
698 if (tag == (set[0] & L.tag_mask)) { \
weidendo144b76c2009-01-26 22:56:14 +0000699 idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
weidendoa17f2a32006-03-20 10:27:30 +0000700 L.use[idx].count ++; \
701 L.use[idx].mask |= use_mask; \
barta0b6b2c2008-07-07 06:49:24 +0000702 CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
weidendoa17f2a32006-03-20 10:27:30 +0000703 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
704 use_mask, L.use[idx].mask, L.use[idx].count); \
705 return L1_Hit; \
706 } \
707 /* If the tag is one other than the MRU, move it into the MRU spot */\
708 /* and shuffle the rest down. */\
709 for (i = 1; i < L.assoc; i++) { \
710 if (tag == (set[i] & L.tag_mask)) { \
711 tmp_tag = set[i]; \
712 for (j = i; j > 0; j--) { \
713 set[j] = set[j - 1]; \
714 } \
715 set[0] = tmp_tag; \
weidendo144b76c2009-01-26 22:56:14 +0000716 idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
weidendoa17f2a32006-03-20 10:27:30 +0000717 L.use[idx].count ++; \
718 L.use[idx].mask |= use_mask; \
barta0b6b2c2008-07-07 06:49:24 +0000719 CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
weidendoa17f2a32006-03-20 10:27:30 +0000720 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
721 use_mask, L.use[idx].mask, L.use[idx].count); \
722 return L1_Hit; \
723 } \
724 } \
725 \
726 /* A miss; install this tag as MRU, shuffle rest down. */ \
727 tmp_tag = set[L.assoc - 1] & ~L.tag_mask; \
728 for (j = L.assoc - 1; j > 0; j--) { \
729 set[j] = set[j - 1]; \
730 } \
731 set[0] = tag | tmp_tag; \
weidendo144b76c2009-01-26 22:56:14 +0000732 idx = (set1 * L.assoc) + tmp_tag; \
weidendoa17f2a32006-03-20 10:27:30 +0000733 return update_##L##_use(&L, idx, \
734 use_mask, a &~ L.line_size_mask); \
735 \
736 /* Second case: word straddles two lines. */ \
737 /* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
738 } else if (((set1 + 1) & (L.sets-1)) == set2) { \
739 Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:L2 miss */ \
weidendo144b76c2009-01-26 22:56:14 +0000740 set = &(L.tags[set1 * L.assoc]); \
weidendoa17f2a32006-03-20 10:27:30 +0000741 use_mask = L.line_start_mask[a & L.line_size_mask]; \
742 if (tag == (set[0] & L.tag_mask)) { \
weidendo144b76c2009-01-26 22:56:14 +0000743 idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
weidendoa17f2a32006-03-20 10:27:30 +0000744 L.use[idx].count ++; \
745 L.use[idx].mask |= use_mask; \
barta0b6b2c2008-07-07 06:49:24 +0000746 CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
weidendoa17f2a32006-03-20 10:27:30 +0000747 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
748 use_mask, L.use[idx].mask, L.use[idx].count); \
749 goto block2; \
750 } \
751 for (i = 1; i < L.assoc; i++) { \
752 if (tag == (set[i] & L.tag_mask)) { \
753 tmp_tag = set[i]; \
754 for (j = i; j > 0; j--) { \
755 set[j] = set[j - 1]; \
756 } \
757 set[0] = tmp_tag; \
weidendo144b76c2009-01-26 22:56:14 +0000758 idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
weidendoa17f2a32006-03-20 10:27:30 +0000759 L.use[idx].count ++; \
760 L.use[idx].mask |= use_mask; \
barta0b6b2c2008-07-07 06:49:24 +0000761 CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
weidendoa17f2a32006-03-20 10:27:30 +0000762 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
763 use_mask, L.use[idx].mask, L.use[idx].count); \
764 goto block2; \
765 } \
766 } \
767 tmp_tag = set[L.assoc - 1] & ~L.tag_mask; \
768 for (j = L.assoc - 1; j > 0; j--) { \
769 set[j] = set[j - 1]; \
770 } \
771 set[0] = tag | tmp_tag; \
weidendo144b76c2009-01-26 22:56:14 +0000772 idx = (set1 * L.assoc) + tmp_tag; \
weidendoa17f2a32006-03-20 10:27:30 +0000773 miss1 = update_##L##_use(&L, idx, \
774 use_mask, a &~ L.line_size_mask); \
775block2: \
weidendo144b76c2009-01-26 22:56:14 +0000776 set = &(L.tags[set2 * L.assoc]); \
weidendoa17f2a32006-03-20 10:27:30 +0000777 use_mask = L.line_end_mask[(a+size-1) & L.line_size_mask]; \
weidendo28e2a142006-11-22 21:00:53 +0000778 tag2 = (a+size-1) & L.tag_mask; \
779 if (tag2 == (set[0] & L.tag_mask)) { \
weidendo144b76c2009-01-26 22:56:14 +0000780 idx = (set2 * L.assoc) + (set[0] & ~L.tag_mask); \
weidendoa17f2a32006-03-20 10:27:30 +0000781 L.use[idx].count ++; \
782 L.use[idx].mask |= use_mask; \
barta0b6b2c2008-07-07 06:49:24 +0000783 CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
weidendoa17f2a32006-03-20 10:27:30 +0000784 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
785 use_mask, L.use[idx].mask, L.use[idx].count); \
786 return miss1; \
787 } \
788 for (i = 1; i < L.assoc; i++) { \
weidendo28e2a142006-11-22 21:00:53 +0000789 if (tag2 == (set[i] & L.tag_mask)) { \
weidendoa17f2a32006-03-20 10:27:30 +0000790 tmp_tag = set[i]; \
791 for (j = i; j > 0; j--) { \
792 set[j] = set[j - 1]; \
793 } \
794 set[0] = tmp_tag; \
weidendo144b76c2009-01-26 22:56:14 +0000795 idx = (set2 * L.assoc) + (tmp_tag & ~L.tag_mask); \
weidendoa17f2a32006-03-20 10:27:30 +0000796 L.use[idx].count ++; \
797 L.use[idx].mask |= use_mask; \
barta0b6b2c2008-07-07 06:49:24 +0000798 CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
weidendoa17f2a32006-03-20 10:27:30 +0000799 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
800 use_mask, L.use[idx].mask, L.use[idx].count); \
801 return miss1; \
802 } \
803 } \
804 tmp_tag = set[L.assoc - 1] & ~L.tag_mask; \
805 for (j = L.assoc - 1; j > 0; j--) { \
806 set[j] = set[j - 1]; \
807 } \
weidendo28e2a142006-11-22 21:00:53 +0000808 set[0] = tag2 | tmp_tag; \
weidendo144b76c2009-01-26 22:56:14 +0000809 idx = (set2 * L.assoc) + tmp_tag; \
weidendoa17f2a32006-03-20 10:27:30 +0000810 miss2 = update_##L##_use(&L, idx, \
811 use_mask, (a+size-1) &~ L.line_size_mask); \
812 return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:L2_Hit; \
813 \
814 } else { \
barta0b6b2c2008-07-07 06:49:24 +0000815 VG_(printf)("addr: %#lx size: %u sets: %d %d", a, size, set1, set2); \
weidendoa17f2a32006-03-20 10:27:30 +0000816 VG_(tool_panic)("item straddles more than two cache sets"); \
817 } \
818 return 0; \
819}
820
821
822/* logarithmic bitcounting algorithm, see
823 * http://graphics.stanford.edu/~seander/bithacks.html
824 */
825static __inline__ unsigned int countBits(unsigned int bits)
826{
827 unsigned int c; // store the total here
828 const int S[] = {1, 2, 4, 8, 16}; // Magic Binary Numbers
829 const int B[] = {0x55555555, 0x33333333, 0x0F0F0F0F, 0x00FF00FF, 0x0000FFFF};
830
831 c = bits;
832 c = ((c >> S[0]) & B[0]) + (c & B[0]);
833 c = ((c >> S[1]) & B[1]) + (c & B[1]);
834 c = ((c >> S[2]) & B[2]) + (c & B[2]);
835 c = ((c >> S[3]) & B[3]) + (c & B[3]);
836 c = ((c >> S[4]) & B[4]) + (c & B[4]);
837 return c;
838}
839
840static void update_L2_use(int idx, Addr memline)
841{
842 line_loaded* loaded = &(L2.loaded[idx]);
843 line_use* use = &(L2.use[idx]);
844 int i = ((32 - countBits(use->mask)) * L2.line_size)>>5;
845
barta0b6b2c2008-07-07 06:49:24 +0000846 CLG_DEBUG(2, " L2.miss [%d]: at %#lx accessing memline %#lx\n",
weidendo75a5c2d2010-06-09 22:32:58 +0000847 idx, CLG_(bb_base) + current_ii->instr_offset, memline);
weidendoa17f2a32006-03-20 10:27:30 +0000848 if (use->count>0) {
barta0b6b2c2008-07-07 06:49:24 +0000849 CLG_DEBUG(2, " old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",
weidendoa17f2a32006-03-20 10:27:30 +0000850 use->count, i, use->mask, loaded->memline, loaded->iaddr);
851 CLG_DEBUG(2, " collect: %d, use_base %p\n",
852 CLG_(current_state).collect, loaded->use_base);
853
854 if (CLG_(current_state).collect && loaded->use_base) {
855 (loaded->use_base)[off_L2_AcCost] += 1000 / use->count;
856 (loaded->use_base)[off_L2_SpLoss] += i;
857 }
858 }
859
860 use->count = 0;
861 use->mask = 0;
862
863 loaded->memline = memline;
weidendo75a5c2d2010-06-09 22:32:58 +0000864 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset;
weidendoa17f2a32006-03-20 10:27:30 +0000865 loaded->use_base = (CLG_(current_state).nonskipped) ?
866 CLG_(current_state).nonskipped->skipped :
weidendo75a5c2d2010-06-09 22:32:58 +0000867 CLG_(cost_base) + current_ii->cost_offset;
weidendoa17f2a32006-03-20 10:27:30 +0000868}
869
870static
871CacheModelResult cacheuse_L2_access(Addr memline, line_loaded* l1_loaded)
872{
873 UInt setNo = (memline >> L2.line_size_bits) & (L2.sets_min_1);
weidendo144b76c2009-01-26 22:56:14 +0000874 UWord* set = &(L2.tags[setNo * L2.assoc]);
weidendoa17f2a32006-03-20 10:27:30 +0000875 UWord tag = memline & L2.tag_mask;
876
877 int i, j, idx;
878 UWord tmp_tag;
879
barta0b6b2c2008-07-07 06:49:24 +0000880 CLG_DEBUG(6,"L2.Acc(Memline %#lx): Set %d\n", memline, setNo);
weidendoa17f2a32006-03-20 10:27:30 +0000881
882 if (tag == (set[0] & L2.tag_mask)) {
weidendo144b76c2009-01-26 22:56:14 +0000883 idx = (setNo * L2.assoc) + (set[0] & ~L2.tag_mask);
weidendoa17f2a32006-03-20 10:27:30 +0000884 l1_loaded->dep_use = &(L2.use[idx]);
885
barta0b6b2c2008-07-07 06:49:24 +0000886 CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
weidendoa17f2a32006-03-20 10:27:30 +0000887 idx, L2.loaded[idx].memline, L2.loaded[idx].iaddr,
888 L2.use[idx].mask, L2.use[idx].count);
889 return L2_Hit;
890 }
891 for (i = 1; i < L2.assoc; i++) {
892 if (tag == (set[i] & L2.tag_mask)) {
893 tmp_tag = set[i];
894 for (j = i; j > 0; j--) {
895 set[j] = set[j - 1];
896 }
897 set[0] = tmp_tag;
weidendo144b76c2009-01-26 22:56:14 +0000898 idx = (setNo * L2.assoc) + (tmp_tag & ~L2.tag_mask);
weidendoa17f2a32006-03-20 10:27:30 +0000899 l1_loaded->dep_use = &(L2.use[idx]);
900
barta0b6b2c2008-07-07 06:49:24 +0000901 CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
weidendoa17f2a32006-03-20 10:27:30 +0000902 i, idx, L2.loaded[idx].memline, L2.loaded[idx].iaddr,
903 L2.use[idx].mask, L2.use[idx].count);
904 return L2_Hit;
905 }
906 }
907
908 /* A miss; install this tag as MRU, shuffle rest down. */
909 tmp_tag = set[L2.assoc - 1] & ~L2.tag_mask;
910 for (j = L2.assoc - 1; j > 0; j--) {
911 set[j] = set[j - 1];
912 }
913 set[0] = tag | tmp_tag;
weidendo144b76c2009-01-26 22:56:14 +0000914 idx = (setNo * L2.assoc) + tmp_tag;
weidendoa17f2a32006-03-20 10:27:30 +0000915 l1_loaded->dep_use = &(L2.use[idx]);
916
917 update_L2_use(idx, memline);
918
919 return MemAccess;
920}
921
922
923
924
925#define UPDATE_USE(L) \
926 \
927static CacheModelResult update##_##L##_use(cache_t2* cache, int idx, \
928 UInt mask, Addr memline) \
929{ \
930 line_loaded* loaded = &(cache->loaded[idx]); \
931 line_use* use = &(cache->use[idx]); \
932 int c = ((32 - countBits(use->mask)) * cache->line_size)>>5; \
933 \
barta0b6b2c2008-07-07 06:49:24 +0000934 CLG_DEBUG(2, " %s.miss [%d]: at %#lx accessing memline %#lx (mask %08x)\n", \
weidendo75a5c2d2010-06-09 22:32:58 +0000935 cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \
weidendoa17f2a32006-03-20 10:27:30 +0000936 if (use->count>0) { \
barta0b6b2c2008-07-07 06:49:24 +0000937 CLG_DEBUG(2, " old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",\
weidendoa17f2a32006-03-20 10:27:30 +0000938 use->count, c, use->mask, loaded->memline, loaded->iaddr); \
939 CLG_DEBUG(2, " collect: %d, use_base %p\n", \
940 CLG_(current_state).collect, loaded->use_base); \
941 \
weidendo75a5c2d2010-06-09 22:32:58 +0000942 if (CLG_(current_state).collect && loaded->use_base) { \
weidendoa17f2a32006-03-20 10:27:30 +0000943 (loaded->use_base)[off_##L##_AcCost] += 1000 / use->count; \
944 (loaded->use_base)[off_##L##_SpLoss] += c; \
945 \
946 /* FIXME (?): L1/L2 line sizes must be equal ! */ \
947 loaded->dep_use->mask |= use->mask; \
948 loaded->dep_use->count += use->count; \
949 } \
950 } \
951 \
952 use->count = 1; \
953 use->mask = mask; \
954 loaded->memline = memline; \
weidendo75a5c2d2010-06-09 22:32:58 +0000955 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; \
956 loaded->use_base = (CLG_(current_state).nonskipped) ? \
957 CLG_(current_state).nonskipped->skipped : \
958 CLG_(cost_base) + current_ii->cost_offset; \
weidendoa17f2a32006-03-20 10:27:30 +0000959 \
960 if (memline == 0) return L2_Hit; \
961 return cacheuse_L2_access(memline, loaded); \
962}
963
964UPDATE_USE(I1);
965UPDATE_USE(D1);
966
967CACHEUSE(I1);
968CACHEUSE(D1);
969
970
971static
972void cacheuse_finish(void)
973{
974 int i;
weidendo0a1951d2009-06-15 00:16:36 +0000975 InstrInfo ii = { 0,0,0,0 };
weidendoa17f2a32006-03-20 10:27:30 +0000976
977 if (!CLG_(current_state).collect) return;
978
weidendo75a5c2d2010-06-09 22:32:58 +0000979 CLG_(bb_base) = 0;
weidendoa17f2a32006-03-20 10:27:30 +0000980 current_ii = &ii;
weidendo75a5c2d2010-06-09 22:32:58 +0000981 CLG_(cost_base) = 0;
weidendoa17f2a32006-03-20 10:27:30 +0000982
983 /* update usage counters */
984 if (I1.use)
985 for (i = 0; i < I1.sets * I1.assoc; i++)
986 if (I1.loaded[i].use_base)
987 update_I1_use( &I1, i, 0,0);
988
989 if (D1.use)
990 for (i = 0; i < D1.sets * D1.assoc; i++)
991 if (D1.loaded[i].use_base)
992 update_D1_use( &D1, i, 0,0);
993
994 if (L2.use)
995 for (i = 0; i < L2.sets * L2.assoc; i++)
996 if (L2.loaded[i].use_base)
997 update_L2_use(i, 0);
998}
999
1000
1001
1002/*------------------------------------------------------------*/
1003/*--- Helper functions called by instrumented code ---*/
1004/*------------------------------------------------------------*/
1005
1006
1007static __inline__
1008void inc_costs(CacheModelResult r, ULong* c1, ULong* c2)
1009{
1010 switch(r) {
1011 case WriteBackMemAccess:
1012 if (clo_simulate_writeback) {
1013 c1[3]++;
1014 c2[3]++;
1015 }
1016 // fall through
1017
1018 case MemAccess:
1019 c1[2]++;
1020 c2[2]++;
1021 // fall through
1022
1023 case L2_Hit:
1024 c1[1]++;
1025 c2[1]++;
1026 // fall through
1027
1028 default:
1029 c1[0]++;
1030 c2[0]++;
1031 }
1032}
1033
weidendo0a1951d2009-06-15 00:16:36 +00001034static
1035Char* cacheRes(CacheModelResult r)
1036{
1037 switch(r) {
1038 case L1_Hit: return "L1 Hit ";
1039 case L2_Hit: return "L2 Hit ";
1040 case MemAccess: return "L2 Miss";
1041 case WriteBackMemAccess: return "L2 Miss (dirty)";
1042 default:
1043 tl_assert(0);
1044 }
1045 return "??";
1046}
weidendoa17f2a32006-03-20 10:27:30 +00001047
1048VG_REGPARM(1)
1049static void log_1I0D(InstrInfo* ii)
1050{
1051 CacheModelResult IrRes;
1052
1053 current_ii = ii;
weidendo75a5c2d2010-06-09 22:32:58 +00001054 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
weidendoa17f2a32006-03-20 10:27:30 +00001055
weidendo0a1951d2009-06-15 00:16:36 +00001056 CLG_DEBUG(6, "log_1I0D: Ir %#lx/%u => %s\n",
weidendo75a5c2d2010-06-09 22:32:58 +00001057 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes));
weidendoa17f2a32006-03-20 10:27:30 +00001058
1059 if (CLG_(current_state).collect) {
1060 ULong* cost_Ir;
weidendo0a1951d2009-06-15 00:16:36 +00001061
weidendoa17f2a32006-03-20 10:27:30 +00001062 if (CLG_(current_state).nonskipped)
weidendo5bba5252010-06-09 22:32:53 +00001063 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);
weidendoa17f2a32006-03-20 10:27:30 +00001064 else
weidendo75a5c2d2010-06-09 22:32:58 +00001065 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR];
weidendoa17f2a32006-03-20 10:27:30 +00001066
1067 inc_costs(IrRes, cost_Ir,
weidendo5bba5252010-06-09 22:32:53 +00001068 CLG_(current_state).cost + fullOffset(EG_IR) );
weidendoa17f2a32006-03-20 10:27:30 +00001069 }
1070}
1071
weidendo0a1951d2009-06-15 00:16:36 +00001072VG_REGPARM(2)
1073static void log_2I0D(InstrInfo* ii1, InstrInfo* ii2)
1074{
1075 CacheModelResult Ir1Res, Ir2Res;
1076 ULong *global_cost_Ir;
1077
1078 current_ii = ii1;
weidendo75a5c2d2010-06-09 22:32:58 +00001079 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);
weidendo0a1951d2009-06-15 00:16:36 +00001080 current_ii = ii2;
weidendo75a5c2d2010-06-09 22:32:58 +00001081 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);
weidendo0a1951d2009-06-15 00:16:36 +00001082
1083 CLG_DEBUG(6, "log_2I0D: Ir1 %#lx/%u => %s, Ir2 %#lx/%u => %s\n",
weidendo75a5c2d2010-06-09 22:32:58 +00001084 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),
1085 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) );
weidendo0a1951d2009-06-15 00:16:36 +00001086
1087 if (!CLG_(current_state).collect) return;
1088
weidendo5bba5252010-06-09 22:32:53 +00001089 global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR);
weidendo0a1951d2009-06-15 00:16:36 +00001090 if (CLG_(current_state).nonskipped) {
weidendo5bba5252010-06-09 22:32:53 +00001091 ULong* skipped_cost_Ir =
1092 CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);
1093
weidendo0a1951d2009-06-15 00:16:36 +00001094 inc_costs(Ir1Res, global_cost_Ir, skipped_cost_Ir);
1095 inc_costs(Ir2Res, global_cost_Ir, skipped_cost_Ir);
1096 return;
1097 }
1098
weidendo5bba5252010-06-09 22:32:53 +00001099 inc_costs(Ir1Res, global_cost_Ir,
weidendo75a5c2d2010-06-09 22:32:58 +00001100 CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]);
weidendo5bba5252010-06-09 22:32:53 +00001101 inc_costs(Ir2Res, global_cost_Ir,
weidendo75a5c2d2010-06-09 22:32:58 +00001102 CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]);
weidendo0a1951d2009-06-15 00:16:36 +00001103}
1104
1105VG_REGPARM(3)
1106static void log_3I0D(InstrInfo* ii1, InstrInfo* ii2, InstrInfo* ii3)
1107{
1108 CacheModelResult Ir1Res, Ir2Res, Ir3Res;
1109 ULong *global_cost_Ir;
1110
1111 current_ii = ii1;
weidendo75a5c2d2010-06-09 22:32:58 +00001112 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);
weidendo0a1951d2009-06-15 00:16:36 +00001113 current_ii = ii2;
weidendo75a5c2d2010-06-09 22:32:58 +00001114 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);
weidendo0a1951d2009-06-15 00:16:36 +00001115 current_ii = ii3;
weidendo75a5c2d2010-06-09 22:32:58 +00001116 Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size);
weidendo0a1951d2009-06-15 00:16:36 +00001117
1118 CLG_DEBUG(6, "log_3I0D: Ir1 %#lx/%u => %s, Ir2 %#lx/%u => %s, Ir3 %#lx/%u => %s\n",
weidendo75a5c2d2010-06-09 22:32:58 +00001119 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),
1120 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res),
1121 CLG_(bb_base) + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) );
weidendo0a1951d2009-06-15 00:16:36 +00001122
1123 if (!CLG_(current_state).collect) return;
1124
weidendo5bba5252010-06-09 22:32:53 +00001125 global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR);
weidendo0a1951d2009-06-15 00:16:36 +00001126 if (CLG_(current_state).nonskipped) {
weidendo5bba5252010-06-09 22:32:53 +00001127 ULong* skipped_cost_Ir =
1128 CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);
weidendo0a1951d2009-06-15 00:16:36 +00001129 inc_costs(Ir1Res, global_cost_Ir, skipped_cost_Ir);
1130 inc_costs(Ir2Res, global_cost_Ir, skipped_cost_Ir);
1131 inc_costs(Ir3Res, global_cost_Ir, skipped_cost_Ir);
1132 return;
1133 }
1134
weidendo5bba5252010-06-09 22:32:53 +00001135 inc_costs(Ir1Res, global_cost_Ir,
weidendo75a5c2d2010-06-09 22:32:58 +00001136 CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]);
weidendo5bba5252010-06-09 22:32:53 +00001137 inc_costs(Ir2Res, global_cost_Ir,
weidendo75a5c2d2010-06-09 22:32:58 +00001138 CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]);
weidendo5bba5252010-06-09 22:32:53 +00001139 inc_costs(Ir3Res, global_cost_Ir,
weidendo75a5c2d2010-06-09 22:32:58 +00001140 CLG_(cost_base) + ii3->cost_offset + ii3->eventset->offset[EG_IR]);
weidendo0a1951d2009-06-15 00:16:36 +00001141}
weidendoa17f2a32006-03-20 10:27:30 +00001142
1143/* Instruction doing a read access */
1144
weidendo0a1951d2009-06-15 00:16:36 +00001145VG_REGPARM(3)
1146static void log_1I1Dr(InstrInfo* ii, Addr data_addr, Word data_size)
weidendoa17f2a32006-03-20 10:27:30 +00001147{
1148 CacheModelResult IrRes, DrRes;
1149
1150 current_ii = ii;
weidendo75a5c2d2010-06-09 22:32:58 +00001151 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
weidendo0a1951d2009-06-15 00:16:36 +00001152 DrRes = (*simulator.D1_Read)(data_addr, data_size);
weidendoa17f2a32006-03-20 10:27:30 +00001153
weidendo0a1951d2009-06-15 00:16:36 +00001154 CLG_DEBUG(6, "log_1I1Dr: Ir %#lx/%u => %s, Dr %#lx/%lu => %s\n",
weidendo75a5c2d2010-06-09 22:32:58 +00001155 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes),
weidendo0a1951d2009-06-15 00:16:36 +00001156 data_addr, data_size, cacheRes(DrRes));
weidendoa17f2a32006-03-20 10:27:30 +00001157
1158 if (CLG_(current_state).collect) {
1159 ULong *cost_Ir, *cost_Dr;
1160
1161 if (CLG_(current_state).nonskipped) {
weidendo5bba5252010-06-09 22:32:53 +00001162 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);
1163 cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR);
weidendoa17f2a32006-03-20 10:27:30 +00001164 }
1165 else {
weidendo75a5c2d2010-06-09 22:32:58 +00001166 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR];
1167 cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR];
weidendoa17f2a32006-03-20 10:27:30 +00001168 }
1169
1170 inc_costs(IrRes, cost_Ir,
weidendo5bba5252010-06-09 22:32:53 +00001171 CLG_(current_state).cost + fullOffset(EG_IR) );
weidendoa17f2a32006-03-20 10:27:30 +00001172 inc_costs(DrRes, cost_Dr,
weidendo5bba5252010-06-09 22:32:53 +00001173 CLG_(current_state).cost + fullOffset(EG_DR) );
weidendoa17f2a32006-03-20 10:27:30 +00001174 }
1175}
1176
1177
weidendo0a1951d2009-06-15 00:16:36 +00001178VG_REGPARM(3)
1179static void log_0I1Dr(InstrInfo* ii, Addr data_addr, Word data_size)
weidendoa17f2a32006-03-20 10:27:30 +00001180{
1181 CacheModelResult DrRes;
1182
1183 current_ii = ii;
weidendo0a1951d2009-06-15 00:16:36 +00001184 DrRes = (*simulator.D1_Read)(data_addr, data_size);
weidendoa17f2a32006-03-20 10:27:30 +00001185
weidendo0a1951d2009-06-15 00:16:36 +00001186 CLG_DEBUG(6, "log_0I1Dr: Dr %#lx/%lu => %s\n",
1187 data_addr, data_size, cacheRes(DrRes));
weidendoa17f2a32006-03-20 10:27:30 +00001188
1189 if (CLG_(current_state).collect) {
1190 ULong *cost_Dr;
1191
weidendo5bba5252010-06-09 22:32:53 +00001192 if (CLG_(current_state).nonskipped)
1193 cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR);
1194 else
weidendo75a5c2d2010-06-09 22:32:58 +00001195 cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR];
weidendo0a1951d2009-06-15 00:16:36 +00001196
weidendoa17f2a32006-03-20 10:27:30 +00001197 inc_costs(DrRes, cost_Dr,
weidendo5bba5252010-06-09 22:32:53 +00001198 CLG_(current_state).cost + fullOffset(EG_DR) );
weidendoa17f2a32006-03-20 10:27:30 +00001199 }
1200}
1201
1202
1203/* Instruction doing a write access */
1204
weidendo0a1951d2009-06-15 00:16:36 +00001205VG_REGPARM(3)
1206static void log_1I1Dw(InstrInfo* ii, Addr data_addr, Word data_size)
weidendoa17f2a32006-03-20 10:27:30 +00001207{
1208 CacheModelResult IrRes, DwRes;
1209
1210 current_ii = ii;
weidendo75a5c2d2010-06-09 22:32:58 +00001211 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
weidendo0a1951d2009-06-15 00:16:36 +00001212 DwRes = (*simulator.D1_Write)(data_addr, data_size);
weidendoa17f2a32006-03-20 10:27:30 +00001213
weidendo0a1951d2009-06-15 00:16:36 +00001214 CLG_DEBUG(6, "log_1I1Dw: Ir %#lx/%u => %s, Dw %#lx/%lu => %s\n",
weidendo75a5c2d2010-06-09 22:32:58 +00001215 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes),
weidendo0a1951d2009-06-15 00:16:36 +00001216 data_addr, data_size, cacheRes(DwRes));
weidendoa17f2a32006-03-20 10:27:30 +00001217
1218 if (CLG_(current_state).collect) {
1219 ULong *cost_Ir, *cost_Dw;
1220
1221 if (CLG_(current_state).nonskipped) {
weidendo5bba5252010-06-09 22:32:53 +00001222 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);
1223 cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW);
weidendoa17f2a32006-03-20 10:27:30 +00001224 }
1225 else {
weidendo75a5c2d2010-06-09 22:32:58 +00001226 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR];
1227 cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW];
weidendoa17f2a32006-03-20 10:27:30 +00001228 }
1229
1230 inc_costs(IrRes, cost_Ir,
weidendo5bba5252010-06-09 22:32:53 +00001231 CLG_(current_state).cost + fullOffset(EG_IR) );
weidendoa17f2a32006-03-20 10:27:30 +00001232 inc_costs(DwRes, cost_Dw,
weidendo5bba5252010-06-09 22:32:53 +00001233 CLG_(current_state).cost + fullOffset(EG_DW) );
weidendoa17f2a32006-03-20 10:27:30 +00001234 }
1235}
1236
weidendo0a1951d2009-06-15 00:16:36 +00001237VG_REGPARM(3)
1238static void log_0I1Dw(InstrInfo* ii, Addr data_addr, Word data_size)
weidendoa17f2a32006-03-20 10:27:30 +00001239{
1240 CacheModelResult DwRes;
1241
1242 current_ii = ii;
weidendo0a1951d2009-06-15 00:16:36 +00001243 DwRes = (*simulator.D1_Write)(data_addr, data_size);
weidendoa17f2a32006-03-20 10:27:30 +00001244
weidendo0a1951d2009-06-15 00:16:36 +00001245 CLG_DEBUG(6, "log_0I1Dw: Dw %#lx/%lu => %s\n",
1246 data_addr, data_size, cacheRes(DwRes));
weidendoa17f2a32006-03-20 10:27:30 +00001247
1248 if (CLG_(current_state).collect) {
1249 ULong *cost_Dw;
1250
weidendo5bba5252010-06-09 22:32:53 +00001251 if (CLG_(current_state).nonskipped)
1252 cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW);
1253 else
weidendo75a5c2d2010-06-09 22:32:58 +00001254 cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW];
weidendoa17f2a32006-03-20 10:27:30 +00001255
1256 inc_costs(DwRes, cost_Dw,
weidendo5bba5252010-06-09 22:32:53 +00001257 CLG_(current_state).cost + fullOffset(EG_DW) );
weidendoa17f2a32006-03-20 10:27:30 +00001258 }
1259}
1260
weidendoa17f2a32006-03-20 10:27:30 +00001261
1262
1263/*------------------------------------------------------------*/
1264/*--- Cache configuration ---*/
1265/*------------------------------------------------------------*/
1266
1267#define UNDEFINED_CACHE ((cache_t) { -1, -1, -1 })
1268
1269static cache_t clo_I1_cache = UNDEFINED_CACHE;
1270static cache_t clo_D1_cache = UNDEFINED_CACHE;
1271static cache_t clo_L2_cache = UNDEFINED_CACHE;
1272
1273
1274/* Checks cache config is ok; makes it so if not. */
1275static
1276void check_cache(cache_t* cache, Char *name)
1277{
weidendo144b76c2009-01-26 22:56:14 +00001278 /* Simulator requires line size and set count to be powers of two */
1279 if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
1280 (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
weidendoa17f2a32006-03-20 10:27:30 +00001281 VG_(message)(Vg_UserMsg,
sewardj0f33adf2009-07-15 14:51:03 +00001282 "error: %s set count not a power of two; aborting.\n",
weidendo144b76c2009-01-26 22:56:14 +00001283 name);
weidendoa17f2a32006-03-20 10:27:30 +00001284 }
1285
weidendo144b76c2009-01-26 22:56:14 +00001286 if (-1 == VG_(log2)(cache->line_size)) {
weidendoa17f2a32006-03-20 10:27:30 +00001287 VG_(message)(Vg_UserMsg,
sewardj0f33adf2009-07-15 14:51:03 +00001288 "error: %s line size of %dB not a power of two; aborting.\n",
weidendoa17f2a32006-03-20 10:27:30 +00001289 name, cache->line_size);
1290 VG_(exit)(1);
1291 }
1292
1293 // Then check line size >= 16 -- any smaller and a single instruction could
1294 // straddle three cache lines, which breaks a simulation assertion and is
1295 // stupid anyway.
1296 if (cache->line_size < MIN_LINE_SIZE) {
1297 VG_(message)(Vg_UserMsg,
sewardj0f33adf2009-07-15 14:51:03 +00001298 "error: %s line size of %dB too small; aborting.\n",
weidendoa17f2a32006-03-20 10:27:30 +00001299 name, cache->line_size);
1300 VG_(exit)(1);
1301 }
1302
1303 /* Then check cache size > line size (causes seg faults if not). */
1304 if (cache->size <= cache->line_size) {
1305 VG_(message)(Vg_UserMsg,
sewardj0f33adf2009-07-15 14:51:03 +00001306 "error: %s cache size of %dB <= line size of %dB; aborting.\n",
weidendoa17f2a32006-03-20 10:27:30 +00001307 name, cache->size, cache->line_size);
1308 VG_(exit)(1);
1309 }
1310
1311 /* Then check assoc <= (size / line size) (seg faults otherwise). */
1312 if (cache->assoc > (cache->size / cache->line_size)) {
1313 VG_(message)(Vg_UserMsg,
sewardj0f33adf2009-07-15 14:51:03 +00001314 "warning: %s associativity > (size / line size); aborting.\n", name);
weidendoa17f2a32006-03-20 10:27:30 +00001315 VG_(exit)(1);
1316 }
1317}
1318
1319static
1320void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c)
1321{
1322#define DEFINED(L) (-1 != L.size || -1 != L.assoc || -1 != L.line_size)
1323
1324 Int n_clos = 0;
1325
1326 // Count how many were defined on the command line.
1327 if (DEFINED(clo_I1_cache)) { n_clos++; }
1328 if (DEFINED(clo_D1_cache)) { n_clos++; }
1329 if (DEFINED(clo_L2_cache)) { n_clos++; }
1330
1331 // Set the cache config (using auto-detection, if supported by the
1332 // architecture)
1333 VG_(configure_caches)( I1c, D1c, L2c, (3 == n_clos) );
1334
1335 // Then replace with any defined on the command line.
1336 if (DEFINED(clo_I1_cache)) { *I1c = clo_I1_cache; }
1337 if (DEFINED(clo_D1_cache)) { *D1c = clo_D1_cache; }
1338 if (DEFINED(clo_L2_cache)) { *L2c = clo_L2_cache; }
1339
1340 // Then check values and fix if not acceptable.
1341 check_cache(I1c, "I1");
1342 check_cache(D1c, "D1");
1343 check_cache(L2c, "L2");
1344
1345 if (VG_(clo_verbosity) > 1) {
sewardj0f33adf2009-07-15 14:51:03 +00001346 VG_(message)(Vg_UserMsg, "Cache configuration used:\n");
1347 VG_(message)(Vg_UserMsg, " I1: %dB, %d-way, %dB lines\n",
weidendoa17f2a32006-03-20 10:27:30 +00001348 I1c->size, I1c->assoc, I1c->line_size);
sewardj0f33adf2009-07-15 14:51:03 +00001349 VG_(message)(Vg_UserMsg, " D1: %dB, %d-way, %dB lines\n",
weidendoa17f2a32006-03-20 10:27:30 +00001350 D1c->size, D1c->assoc, D1c->line_size);
sewardj0f33adf2009-07-15 14:51:03 +00001351 VG_(message)(Vg_UserMsg, " L2: %dB, %d-way, %dB lines\n",
weidendoa17f2a32006-03-20 10:27:30 +00001352 L2c->size, L2c->assoc, L2c->line_size);
1353 }
1354#undef CMD_LINE_DEFINED
1355}
1356
1357
1358/* Initialize and clear simulator state */
1359static void cachesim_post_clo_init(void)
1360{
1361 /* Cache configurations. */
1362 cache_t I1c, D1c, L2c;
1363
1364 /* Initialize access handlers */
1365 if (!CLG_(clo).simulate_cache) {
1366 CLG_(cachesim).log_1I0D = 0;
1367 CLG_(cachesim).log_1I0D_name = "(no function)";
weidendo0a1951d2009-06-15 00:16:36 +00001368 CLG_(cachesim).log_2I0D = 0;
1369 CLG_(cachesim).log_2I0D_name = "(no function)";
1370 CLG_(cachesim).log_3I0D = 0;
1371 CLG_(cachesim).log_3I0D_name = "(no function)";
weidendoa17f2a32006-03-20 10:27:30 +00001372
1373 CLG_(cachesim).log_1I1Dr = 0;
weidendoa17f2a32006-03-20 10:27:30 +00001374 CLG_(cachesim).log_1I1Dr_name = "(no function)";
weidendo0a1951d2009-06-15 00:16:36 +00001375 CLG_(cachesim).log_1I1Dw = 0;
weidendoa17f2a32006-03-20 10:27:30 +00001376 CLG_(cachesim).log_1I1Dw_name = "(no function)";
weidendoa17f2a32006-03-20 10:27:30 +00001377
1378 CLG_(cachesim).log_0I1Dr = 0;
weidendoa17f2a32006-03-20 10:27:30 +00001379 CLG_(cachesim).log_0I1Dr_name = "(no function)";
weidendo0a1951d2009-06-15 00:16:36 +00001380 CLG_(cachesim).log_0I1Dw = 0;
weidendoa17f2a32006-03-20 10:27:30 +00001381 CLG_(cachesim).log_0I1Dw_name = "(no function)";
weidendoa17f2a32006-03-20 10:27:30 +00001382 return;
1383 }
1384
1385 /* Configuration of caches only needed with real cache simulation */
1386 configure_caches(&I1c, &D1c, &L2c);
1387
1388 I1.name = "I1";
1389 D1.name = "D1";
1390 L2.name = "L2";
1391
1392 cachesim_initcache(I1c, &I1);
1393 cachesim_initcache(D1c, &D1);
1394 cachesim_initcache(L2c, &L2);
1395
1396 /* the other cache simulators use the standard helpers
1397 * with dispatching via simulator struct */
1398
1399 CLG_(cachesim).log_1I0D = log_1I0D;
1400 CLG_(cachesim).log_1I0D_name = "log_1I0D";
weidendo0a1951d2009-06-15 00:16:36 +00001401 CLG_(cachesim).log_2I0D = log_2I0D;
1402 CLG_(cachesim).log_2I0D_name = "log_2I0D";
1403 CLG_(cachesim).log_3I0D = log_3I0D;
1404 CLG_(cachesim).log_3I0D_name = "log_3I0D";
weidendoa17f2a32006-03-20 10:27:30 +00001405
1406 CLG_(cachesim).log_1I1Dr = log_1I1Dr;
1407 CLG_(cachesim).log_1I1Dw = log_1I1Dw;
weidendoa17f2a32006-03-20 10:27:30 +00001408 CLG_(cachesim).log_1I1Dr_name = "log_1I1Dr";
1409 CLG_(cachesim).log_1I1Dw_name = "log_1I1Dw";
weidendoa17f2a32006-03-20 10:27:30 +00001410
1411 CLG_(cachesim).log_0I1Dr = log_0I1Dr;
1412 CLG_(cachesim).log_0I1Dw = log_0I1Dw;
weidendoa17f2a32006-03-20 10:27:30 +00001413 CLG_(cachesim).log_0I1Dr_name = "log_0I1Dr";
1414 CLG_(cachesim).log_0I1Dw_name = "log_0I1Dw";
weidendoa17f2a32006-03-20 10:27:30 +00001415
1416 if (clo_collect_cacheuse) {
1417
1418 /* Output warning for not supported option combinations */
1419 if (clo_simulate_hwpref) {
1420 VG_(message)(Vg_DebugMsg,
sewardj0f33adf2009-07-15 14:51:03 +00001421 "warning: prefetch simulation can not be "
1422 "used with cache usage\n");
weidendoa17f2a32006-03-20 10:27:30 +00001423 clo_simulate_hwpref = False;
1424 }
1425
1426 if (clo_simulate_writeback) {
1427 VG_(message)(Vg_DebugMsg,
sewardj0f33adf2009-07-15 14:51:03 +00001428 "warning: write-back simulation can not be "
1429 "used with cache usage\n");
weidendoa17f2a32006-03-20 10:27:30 +00001430 clo_simulate_writeback = False;
1431 }
1432
1433 simulator.I1_Read = cacheuse_I1_doRead;
1434 simulator.D1_Read = cacheuse_D1_doRead;
1435 simulator.D1_Write = cacheuse_D1_doRead;
1436 return;
1437 }
1438
1439 if (clo_simulate_hwpref) {
1440 prefetch_clear();
1441
1442 if (clo_simulate_writeback) {
1443 simulator.I1_Read = prefetch_I1_Read;
1444 simulator.D1_Read = prefetch_D1_Read;
1445 simulator.D1_Write = prefetch_D1_Write;
1446 }
1447 else {
1448 simulator.I1_Read = prefetch_I1_ref;
1449 simulator.D1_Read = prefetch_D1_ref;
1450 simulator.D1_Write = prefetch_D1_ref;
1451 }
1452
1453 return;
1454 }
1455
1456 if (clo_simulate_writeback) {
1457 simulator.I1_Read = cachesim_I1_Read;
1458 simulator.D1_Read = cachesim_D1_Read;
1459 simulator.D1_Write = cachesim_D1_Write;
1460 }
1461 else {
1462 simulator.I1_Read = cachesim_I1_ref;
1463 simulator.D1_Read = cachesim_D1_ref;
1464 simulator.D1_Write = cachesim_D1_ref;
1465 }
1466}
1467
1468
1469/* Clear simulator state. Has to be initialized before */
1470static
1471void cachesim_clear(void)
1472{
1473 cachesim_clearcache(&I1);
1474 cachesim_clearcache(&D1);
1475 cachesim_clearcache(&L2);
1476
1477 prefetch_clear();
1478}
1479
1480
1481static void cachesim_getdesc(Char* buf)
1482{
1483 Int p;
1484 p = VG_(sprintf)(buf, "\ndesc: I1 cache: %s\n", I1.desc_line);
1485 p += VG_(sprintf)(buf+p, "desc: D1 cache: %s\n", D1.desc_line);
1486 VG_(sprintf)(buf+p, "desc: L2 cache: %s\n", L2.desc_line);
1487}
1488
1489static
1490void cachesim_print_opts(void)
1491{
1492 VG_(printf)(
1493"\n cache simulator options:\n"
1494" --simulate-cache=no|yes Do cache simulation [no]\n"
1495" --simulate-wb=no|yes Count write-back events [no]\n"
1496" --simulate-hwpref=no|yes Simulate hardware prefetch [no]\n"
1497#if CLG_EXPERIMENTAL
1498" --simulate-sectors=no|yes Simulate sectored behaviour [no]\n"
1499#endif
1500" --cacheuse=no|yes Collect cache block use [no]\n"
1501" --I1=<size>,<assoc>,<line_size> set I1 cache manually\n"
1502" --D1=<size>,<assoc>,<line_size> set D1 cache manually\n"
1503" --L2=<size>,<assoc>,<line_size> set L2 cache manually\n"
1504 );
1505}
1506
njn83df0b62009-02-25 01:01:05 +00001507static void parse_opt ( cache_t* cache, char* opt )
weidendoa17f2a32006-03-20 10:27:30 +00001508{
njn83df0b62009-02-25 01:01:05 +00001509 Long i1, i2, i3;
1510 Char* endptr;
weidendoa17f2a32006-03-20 10:27:30 +00001511
njn83df0b62009-02-25 01:01:05 +00001512 // Option argument looks like "65536,2,64". Extract them.
1513 i1 = VG_(strtoll10)(opt, &endptr); if (*endptr != ',') goto bad;
1514 i2 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != ',') goto bad;
1515 i3 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != '\0') goto bad;
weidendoa17f2a32006-03-20 10:27:30 +00001516
njn83df0b62009-02-25 01:01:05 +00001517 // Check for overflow.
1518 cache->size = (Int)i1;
1519 cache->assoc = (Int)i2;
1520 cache->line_size = (Int)i3;
1521 if (cache->size != i1) goto overflow;
1522 if (cache->assoc != i2) goto overflow;
1523 if (cache->line_size != i3) goto overflow;
weidendoa17f2a32006-03-20 10:27:30 +00001524
1525 return;
1526
njn83df0b62009-02-25 01:01:05 +00001527 overflow:
1528 VG_(message)(Vg_UserMsg,
1529 "one of the cache parameters was too large and overflowed\n");
weidendoa17f2a32006-03-20 10:27:30 +00001530 bad:
njn83df0b62009-02-25 01:01:05 +00001531 // XXX: this omits the "--I1/D1/L2=" part from the message, but that's
1532 // not a big deal.
1533 VG_(err_bad_option)(opt);
weidendoa17f2a32006-03-20 10:27:30 +00001534}
1535
1536/* Check for command line option for cache configuration.
1537 * Return False if unknown and not handled.
1538 *
1539 * Called from CLG_(process_cmd_line_option)() in clo.c
1540 */
1541static Bool cachesim_parse_opt(Char* arg)
1542{
njn83df0b62009-02-25 01:01:05 +00001543 Char* tmp_str;
weidendoa17f2a32006-03-20 10:27:30 +00001544
njn83df0b62009-02-25 01:01:05 +00001545 if VG_BOOL_CLO(arg, "--simulate-wb", clo_simulate_writeback) {}
1546 else if VG_BOOL_CLO(arg, "--simulate-hwpref", clo_simulate_hwpref) {}
1547 else if VG_BOOL_CLO(arg, "--simulate-sectors", clo_simulate_sectors) {}
weidendoa17f2a32006-03-20 10:27:30 +00001548
njn83df0b62009-02-25 01:01:05 +00001549 else if VG_BOOL_CLO(arg, "--cacheuse", clo_collect_cacheuse) {
1550 if (clo_collect_cacheuse) {
1551 /* Use counters only make sense with fine dumping */
1552 CLG_(clo).dump_instr = True;
1553 }
1554 }
weidendoa17f2a32006-03-20 10:27:30 +00001555
njn83df0b62009-02-25 01:01:05 +00001556 else if VG_STR_CLO(arg, "--I1", tmp_str)
1557 parse_opt(&clo_I1_cache, tmp_str);
1558 else if VG_STR_CLO(arg, "--D1", tmp_str)
1559 parse_opt(&clo_D1_cache, tmp_str);
1560 else if VG_STR_CLO(arg, "--L2", tmp_str)
1561 parse_opt(&clo_L2_cache, tmp_str);
weidendoa17f2a32006-03-20 10:27:30 +00001562 else
1563 return False;
1564
1565 return True;
1566}
1567
1568/* Adds commas to ULong, right justifying in a field field_width wide, returns
1569 * the string in buf. */
1570static
1571Int commify(ULong n, int field_width, char* buf)
1572{
1573 int len, n_commas, i, j, new_len, space;
1574
1575 VG_(sprintf)(buf, "%llu", n);
1576 len = VG_(strlen)(buf);
1577 n_commas = (len - 1) / 3;
1578 new_len = len + n_commas;
1579 space = field_width - new_len;
1580
1581 /* Allow for printing a number in a field_width smaller than it's size */
1582 if (space < 0) space = 0;
1583
1584 /* Make j = -1 because we copy the '\0' before doing the numbers in groups
1585 * of three. */
1586 for (j = -1, i = len ; i >= 0; i--) {
1587 buf[i + n_commas + space] = buf[i];
1588
1589 if ((i>0) && (3 == ++j)) {
1590 j = 0;
1591 n_commas--;
1592 buf[i + n_commas + space] = ',';
1593 }
1594 }
1595 /* Right justify in field. */
1596 for (i = 0; i < space; i++) buf[i] = ' ';
1597 return new_len;
1598}
1599
1600static
1601void percentify(Int n, Int ex, Int field_width, char buf[])
1602{
1603 int i, len, space;
1604
1605 VG_(sprintf)(buf, "%d.%d%%", n / ex, n % ex);
1606 len = VG_(strlen)(buf);
1607 space = field_width - len;
1608 if (space < 0) space = 0; /* Allow for v. small field_width */
1609 i = len;
1610
1611 /* Right justify in field */
1612 for ( ; i >= 0; i--) buf[i + space] = buf[i];
1613 for (i = 0; i < space; i++) buf[i] = ' ';
1614}
1615
1616static
1617void cachesim_printstat(void)
1618{
1619 FullCost total = CLG_(total_cost), D_total = 0;
1620 ULong L2_total_m, L2_total_mr, L2_total_mw,
1621 L2_total, L2_total_r, L2_total_w;
1622 char buf1[RESULTS_BUF_LEN],
1623 buf2[RESULTS_BUF_LEN],
1624 buf3[RESULTS_BUF_LEN];
1625 Int l1, l2, l3;
1626 Int p;
1627
1628 if ((VG_(clo_verbosity) >1) && clo_simulate_hwpref) {
sewardj0f33adf2009-07-15 14:51:03 +00001629 VG_(message)(Vg_DebugMsg, "Prefetch Up: %llu\n",
weidendoa17f2a32006-03-20 10:27:30 +00001630 prefetch_up);
sewardj0f33adf2009-07-15 14:51:03 +00001631 VG_(message)(Vg_DebugMsg, "Prefetch Down: %llu\n",
weidendoa17f2a32006-03-20 10:27:30 +00001632 prefetch_down);
sewardj0f33adf2009-07-15 14:51:03 +00001633 VG_(message)(Vg_DebugMsg, "\n");
weidendoa17f2a32006-03-20 10:27:30 +00001634 }
1635
1636 /* I cache results. Use the I_refs value to determine the first column
1637 * width. */
weidendo5bba5252010-06-09 22:32:53 +00001638 l1 = commify(total[fullOffset(EG_IR)], 0, buf1);
sewardj0f33adf2009-07-15 14:51:03 +00001639 VG_(message)(Vg_UserMsg, "I refs: %s\n", buf1);
weidendoa17f2a32006-03-20 10:27:30 +00001640
1641 if (!CLG_(clo).simulate_cache) return;
1642
weidendo5bba5252010-06-09 22:32:53 +00001643 commify(total[fullOffset(EG_IR) +1], l1, buf1);
sewardj0f33adf2009-07-15 14:51:03 +00001644 VG_(message)(Vg_UserMsg, "I1 misses: %s\n", buf1);
weidendoa17f2a32006-03-20 10:27:30 +00001645
weidendo5bba5252010-06-09 22:32:53 +00001646 commify(total[fullOffset(EG_IR) +2], l1, buf1);
sewardj0f33adf2009-07-15 14:51:03 +00001647 VG_(message)(Vg_UserMsg, "L2i misses: %s\n", buf1);
weidendoa17f2a32006-03-20 10:27:30 +00001648
1649 p = 100;
1650
weidendo5bba5252010-06-09 22:32:53 +00001651 if (0 == total[fullOffset(EG_IR)])
1652 total[fullOffset(EG_IR)] = 1;
weidendoa17f2a32006-03-20 10:27:30 +00001653
weidendo5bba5252010-06-09 22:32:53 +00001654 percentify(total[fullOffset(EG_IR)+1] * 100 * p /
1655 total[fullOffset(EG_IR)], p, l1+1, buf1);
sewardj0f33adf2009-07-15 14:51:03 +00001656 VG_(message)(Vg_UserMsg, "I1 miss rate: %s\n", buf1);
weidendoa17f2a32006-03-20 10:27:30 +00001657
weidendo5bba5252010-06-09 22:32:53 +00001658 percentify(total[fullOffset(EG_IR)+2] * 100 * p /
1659 total[fullOffset(EG_IR)], p, l1+1, buf1);
sewardj0f33adf2009-07-15 14:51:03 +00001660 VG_(message)(Vg_UserMsg, "L2i miss rate: %s\n", buf1);
1661 VG_(message)(Vg_UserMsg, "\n");
weidendoa17f2a32006-03-20 10:27:30 +00001662
1663 /* D cache results.
1664 Use the D_refs.rd and D_refs.wr values to determine the
1665 * width of columns 2 & 3. */
1666
1667 D_total = CLG_(get_eventset_cost)( CLG_(sets).full );
1668 CLG_(init_cost)( CLG_(sets).full, D_total);
weidendo5bba5252010-06-09 22:32:53 +00001669 // we only use the first 3 values of D_total, adding up Dr and Dw costs
1670 CLG_(copy_cost)( CLG_(get_event_set)(EG_DR), D_total, total + fullOffset(EG_DR) );
1671 CLG_(add_cost) ( CLG_(get_event_set)(EG_DW), D_total, total + fullOffset(EG_DW) );
weidendoa17f2a32006-03-20 10:27:30 +00001672
1673 commify( D_total[0], l1, buf1);
weidendo5bba5252010-06-09 22:32:53 +00001674 l2 = commify(total[fullOffset(EG_DR)], 0, buf2);
1675 l3 = commify(total[fullOffset(EG_DW)], 0, buf3);
sewardj0f33adf2009-07-15 14:51:03 +00001676 VG_(message)(Vg_UserMsg, "D refs: %s (%s rd + %s wr)\n",
weidendoa17f2a32006-03-20 10:27:30 +00001677 buf1, buf2, buf3);
1678
1679 commify( D_total[1], l1, buf1);
weidendo5bba5252010-06-09 22:32:53 +00001680 commify(total[fullOffset(EG_DR)+1], l2, buf2);
1681 commify(total[fullOffset(EG_DW)+1], l3, buf3);
sewardj0f33adf2009-07-15 14:51:03 +00001682 VG_(message)(Vg_UserMsg, "D1 misses: %s (%s rd + %s wr)\n",
weidendoa17f2a32006-03-20 10:27:30 +00001683 buf1, buf2, buf3);
1684
1685 commify( D_total[2], l1, buf1);
weidendo5bba5252010-06-09 22:32:53 +00001686 commify(total[fullOffset(EG_DR)+2], l2, buf2);
1687 commify(total[fullOffset(EG_DW)+2], l3, buf3);
sewardj0f33adf2009-07-15 14:51:03 +00001688 VG_(message)(Vg_UserMsg, "L2d misses: %s (%s rd + %s wr)\n",
weidendoa17f2a32006-03-20 10:27:30 +00001689 buf1, buf2, buf3);
1690
1691 p = 10;
1692
1693 if (0 == D_total[0]) D_total[0] = 1;
weidendo5bba5252010-06-09 22:32:53 +00001694 if (0 == total[fullOffset(EG_DR)]) total[fullOffset(EG_DR)] = 1;
1695 if (0 == total[fullOffset(EG_DW)]) total[fullOffset(EG_DW)] = 1;
weidendoa17f2a32006-03-20 10:27:30 +00001696
1697 percentify( D_total[1] * 100 * p / D_total[0], p, l1+1, buf1);
weidendo5bba5252010-06-09 22:32:53 +00001698 percentify(total[fullOffset(EG_DR)+1] * 100 * p /
1699 total[fullOffset(EG_DR)], p, l2+1, buf2);
1700 percentify(total[fullOffset(EG_DW)+1] * 100 * p /
1701 total[fullOffset(EG_DW)], p, l3+1, buf3);
sewardj0f33adf2009-07-15 14:51:03 +00001702 VG_(message)(Vg_UserMsg, "D1 miss rate: %s (%s + %s )\n",
1703 buf1, buf2,buf3);
weidendoa17f2a32006-03-20 10:27:30 +00001704
1705 percentify( D_total[2] * 100 * p / D_total[0], p, l1+1, buf1);
weidendo5bba5252010-06-09 22:32:53 +00001706 percentify(total[fullOffset(EG_DR)+2] * 100 * p /
1707 total[fullOffset(EG_DR)], p, l2+1, buf2);
1708 percentify(total[fullOffset(EG_DW)+2] * 100 * p /
1709 total[fullOffset(EG_DW)], p, l3+1, buf3);
sewardj0f33adf2009-07-15 14:51:03 +00001710 VG_(message)(Vg_UserMsg, "L2d miss rate: %s (%s + %s )\n",
1711 buf1, buf2,buf3);
1712 VG_(message)(Vg_UserMsg, "\n");
weidendoa17f2a32006-03-20 10:27:30 +00001713
1714
1715
1716 /* L2 overall results */
1717
1718 L2_total =
weidendo5bba5252010-06-09 22:32:53 +00001719 total[fullOffset(EG_DR) +1] +
1720 total[fullOffset(EG_DW) +1] +
1721 total[fullOffset(EG_IR) +1];
weidendoa17f2a32006-03-20 10:27:30 +00001722 L2_total_r =
weidendo5bba5252010-06-09 22:32:53 +00001723 total[fullOffset(EG_DR) +1] +
1724 total[fullOffset(EG_IR) +1];
1725 L2_total_w = total[fullOffset(EG_DW) +1];
weidendoa17f2a32006-03-20 10:27:30 +00001726 commify(L2_total, l1, buf1);
1727 commify(L2_total_r, l2, buf2);
1728 commify(L2_total_w, l3, buf3);
sewardj0f33adf2009-07-15 14:51:03 +00001729 VG_(message)(Vg_UserMsg, "L2 refs: %s (%s rd + %s wr)\n",
weidendoa17f2a32006-03-20 10:27:30 +00001730 buf1, buf2, buf3);
1731
1732 L2_total_m =
weidendo5bba5252010-06-09 22:32:53 +00001733 total[fullOffset(EG_DR) +2] +
1734 total[fullOffset(EG_DW) +2] +
1735 total[fullOffset(EG_IR) +2];
weidendoa17f2a32006-03-20 10:27:30 +00001736 L2_total_mr =
weidendo5bba5252010-06-09 22:32:53 +00001737 total[fullOffset(EG_DR) +2] +
1738 total[fullOffset(EG_IR) +2];
1739 L2_total_mw = total[fullOffset(EG_DW) +2];
weidendoa17f2a32006-03-20 10:27:30 +00001740 commify(L2_total_m, l1, buf1);
1741 commify(L2_total_mr, l2, buf2);
1742 commify(L2_total_mw, l3, buf3);
sewardj0f33adf2009-07-15 14:51:03 +00001743 VG_(message)(Vg_UserMsg, "L2 misses: %s (%s rd + %s wr)\n",
weidendoa17f2a32006-03-20 10:27:30 +00001744 buf1, buf2, buf3);
1745
1746 percentify(L2_total_m * 100 * p /
weidendo5bba5252010-06-09 22:32:53 +00001747 (total[fullOffset(EG_IR)] + D_total[0]), p, l1+1, buf1);
weidendoa17f2a32006-03-20 10:27:30 +00001748 percentify(L2_total_mr * 100 * p /
weidendo5bba5252010-06-09 22:32:53 +00001749 (total[fullOffset(EG_IR)] + total[fullOffset(EG_DR)]),
weidendoa17f2a32006-03-20 10:27:30 +00001750 p, l2+1, buf2);
1751 percentify(L2_total_mw * 100 * p /
weidendo5bba5252010-06-09 22:32:53 +00001752 total[fullOffset(EG_DW)], p, l3+1, buf3);
sewardj0f33adf2009-07-15 14:51:03 +00001753 VG_(message)(Vg_UserMsg, "L2 miss rate: %s (%s + %s )\n",
weidendoa17f2a32006-03-20 10:27:30 +00001754 buf1, buf2,buf3);
1755}
1756
1757
1758/*------------------------------------------------------------*/
1759/*--- Setup for Event set. ---*/
1760/*------------------------------------------------------------*/
1761
1762struct event_sets CLG_(sets);
1763
weidendo5bba5252010-06-09 22:32:53 +00001764void CLG_(init_eventsets)()
weidendoa17f2a32006-03-20 10:27:30 +00001765{
weidendo5bba5252010-06-09 22:32:53 +00001766 // Event groups from which the event sets are composed
1767 // the "Use" group only is used with "cacheuse" simulation
1768 if (clo_collect_cacheuse)
1769 CLG_(register_event_group4)(EG_USE,
1770 "AcCost1", "SpLoss1", "AcCost2", "SpLoss2");
weidendoa17f2a32006-03-20 10:27:30 +00001771
weidendo5bba5252010-06-09 22:32:53 +00001772 if (!CLG_(clo).simulate_cache)
1773 CLG_(register_event_group)(EG_IR, "Ir");
1774 else if (!clo_simulate_writeback) {
1775 CLG_(register_event_group3)(EG_IR, "Ir", "I1mr", "I2mr");
1776 CLG_(register_event_group3)(EG_DR, "Dr", "D1mr", "D2mr");
1777 CLG_(register_event_group3)(EG_DW, "Dw", "D1mw", "D2mw");
weidendoa17f2a32006-03-20 10:27:30 +00001778 }
weidendo5bba5252010-06-09 22:32:53 +00001779 else { // clo_simulate_writeback
1780 CLG_(register_event_group4)(EG_IR, "Ir", "I1mr", "I2mr", "I2dmr");
1781 CLG_(register_event_group4)(EG_DR, "Dr", "D1mr", "D2mr", "I2dmr");
1782 CLG_(register_event_group4)(EG_DW, "Dw", "D1mw", "D2mw", "I2dmw");
weidendoa17f2a32006-03-20 10:27:30 +00001783 }
weidendo5bba5252010-06-09 22:32:53 +00001784
weidendoaeb86222010-06-09 22:33:02 +00001785 if (CLG_(clo).collect_bus)
1786 CLG_(register_event_group)(EG_BUS, "Ge");
1787
weidendo5bba5252010-06-09 22:32:53 +00001788 if (CLG_(clo).collect_alloc)
1789 CLG_(register_event_group2)(EG_ALLOC, "allocCount", "allocSize");
1790
1791 if (CLG_(clo).collect_systime)
1792 CLG_(register_event_group2)(EG_SYS, "sysCount", "sysTime");
1793
1794 // event set used as base for instruction self cost
1795 CLG_(sets).base = CLG_(get_event_set2)(EG_USE, EG_IR);
1796
1797 // event set comprising all event groups, used for inclusive cost
1798 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).base, EG_DR, EG_DW);
weidendoaeb86222010-06-09 22:33:02 +00001799 CLG_(sets).full = CLG_(add_event_group) (CLG_(sets).full, EG_BUS);
weidendo5bba5252010-06-09 22:32:53 +00001800 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_ALLOC, EG_SYS);
1801
1802 CLG_DEBUGIF(1) {
1803 CLG_DEBUG(1, "EventSets:\n");
1804 CLG_(print_eventset)(-2, CLG_(sets).base);
1805 CLG_(print_eventset)(-2, CLG_(sets).full);
weidendoa17f2a32006-03-20 10:27:30 +00001806 }
weidendoa17f2a32006-03-20 10:27:30 +00001807
weidendo5bba5252010-06-09 22:32:53 +00001808 /* Not-existing events are silently ignored */
1809 CLG_(dumpmap) = CLG_(get_eventmapping)(CLG_(sets).full);
1810 CLG_(append_event)(CLG_(dumpmap), "Ir");
1811 CLG_(append_event)(CLG_(dumpmap), "Dr");
1812 CLG_(append_event)(CLG_(dumpmap), "Dw");
1813 CLG_(append_event)(CLG_(dumpmap), "I1mr");
1814 CLG_(append_event)(CLG_(dumpmap), "D1mr");
1815 CLG_(append_event)(CLG_(dumpmap), "D1mw");
1816 CLG_(append_event)(CLG_(dumpmap), "I2mr");
1817 CLG_(append_event)(CLG_(dumpmap), "D2mr");
1818 CLG_(append_event)(CLG_(dumpmap), "D2mw");
1819 CLG_(append_event)(CLG_(dumpmap), "I2dmr");
1820 CLG_(append_event)(CLG_(dumpmap), "D2dmr");
1821 CLG_(append_event)(CLG_(dumpmap), "D2dmw");
1822 CLG_(append_event)(CLG_(dumpmap), "AcCost1");
1823 CLG_(append_event)(CLG_(dumpmap), "SpLoss1");
1824 CLG_(append_event)(CLG_(dumpmap), "AcCost2");
1825 CLG_(append_event)(CLG_(dumpmap), "SpLoss2");
weidendoaeb86222010-06-09 22:33:02 +00001826 CLG_(append_event)(CLG_(dumpmap), "Ge");
weidendo5bba5252010-06-09 22:32:53 +00001827 CLG_(append_event)(CLG_(dumpmap), "allocCount");
1828 CLG_(append_event)(CLG_(dumpmap), "allocSize");
1829 CLG_(append_event)(CLG_(dumpmap), "sysCount");
1830 CLG_(append_event)(CLG_(dumpmap), "sysTime");
weidendoa17f2a32006-03-20 10:27:30 +00001831}
1832
1833
weidendoa17f2a32006-03-20 10:27:30 +00001834/* this is called at dump time for every instruction executed */
1835static void cachesim_add_icost(SimCost cost, BBCC* bbcc,
1836 InstrInfo* ii, ULong exe_count)
1837{
weidendo5bba5252010-06-09 22:32:53 +00001838 if (!CLG_(clo).simulate_cache)
1839 cost[ fullOffset(EG_IR) ] += exe_count;
weidendoaeb86222010-06-09 22:33:02 +00001840
1841 if (ii->eventset)
weidendo5bba5252010-06-09 22:32:53 +00001842 CLG_(add_and_zero_cost2)( CLG_(sets).full, cost,
1843 ii->eventset, bbcc->cost + ii->cost_offset);
weidendoa17f2a32006-03-20 10:27:30 +00001844}
1845
1846static
weidendoa17f2a32006-03-20 10:27:30 +00001847void cachesim_finish(void)
1848{
1849 if (clo_collect_cacheuse)
1850 cacheuse_finish();
1851}
1852
1853/*------------------------------------------------------------*/
1854/*--- The simulator defined in this file ---*/
1855/*------------------------------------------------------------*/
1856
1857struct cachesim_if CLG_(cachesim) = {
1858 .print_opts = cachesim_print_opts,
1859 .parse_opt = cachesim_parse_opt,
1860 .post_clo_init = cachesim_post_clo_init,
1861 .clear = cachesim_clear,
1862 .getdesc = cachesim_getdesc,
1863 .printstat = cachesim_printstat,
1864 .add_icost = cachesim_add_icost,
weidendoa17f2a32006-03-20 10:27:30 +00001865 .finish = cachesim_finish,
1866
1867 /* these will be set by cachesim_post_clo_init */
1868 .log_1I0D = 0,
weidendo0a1951d2009-06-15 00:16:36 +00001869 .log_2I0D = 0,
1870 .log_3I0D = 0,
weidendoa17f2a32006-03-20 10:27:30 +00001871
1872 .log_1I1Dr = 0,
1873 .log_1I1Dw = 0,
weidendoa17f2a32006-03-20 10:27:30 +00001874
1875 .log_0I1Dr = 0,
1876 .log_0I1Dw = 0,
weidendoa17f2a32006-03-20 10:27:30 +00001877
1878 .log_1I0D_name = "(no function)",
weidendo0a1951d2009-06-15 00:16:36 +00001879 .log_2I0D_name = "(no function)",
1880 .log_3I0D_name = "(no function)",
weidendoa17f2a32006-03-20 10:27:30 +00001881
1882 .log_1I1Dr_name = "(no function)",
1883 .log_1I1Dw_name = "(no function)",
weidendoa17f2a32006-03-20 10:27:30 +00001884
1885 .log_0I1Dr_name = "(no function)",
1886 .log_0I1Dw_name = "(no function)",
weidendoa17f2a32006-03-20 10:27:30 +00001887};
1888
1889
1890/*--------------------------------------------------------------------*/
1891/*--- end ct_sim.c ---*/
1892/*--------------------------------------------------------------------*/
1893