sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin host_x86_defs.c ---*/ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 25e5473 | 2012-08-05 15:36:51 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2012 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 36 | #include "libvex_basictypes.h" |
| 37 | #include "libvex.h" |
sewardj | c4278f4 | 2004-11-26 13:18:19 +0000 | [diff] [blame] | 38 | #include "libvex_trc_values.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 39 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 40 | #include "main_util.h" |
| 41 | #include "host_generic_regs.h" |
| 42 | #include "host_x86_defs.h" |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 43 | |
| 44 | |
| 45 | /* --------- Registers. --------- */ |
| 46 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 47 | void ppHRegX86 ( HReg reg ) |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 48 | { |
| 49 | Int r; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 50 | static const HChar* ireg32_names[8] |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 51 | = { "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi" }; |
| 52 | /* Be generic for all virtual regs. */ |
| 53 | if (hregIsVirtual(reg)) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 54 | ppHReg(reg); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 55 | return; |
| 56 | } |
| 57 | /* But specific for real regs. */ |
| 58 | switch (hregClass(reg)) { |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 59 | case HRcInt32: |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 60 | r = hregNumber(reg); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 61 | vassert(r >= 0 && r < 8); |
| 62 | vex_printf("%s", ireg32_names[r]); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 63 | return; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 64 | case HRcFlt64: |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 65 | r = hregNumber(reg); |
sewardj | d7bd8ac | 2004-10-09 10:06:12 +0000 | [diff] [blame] | 66 | vassert(r >= 0 && r < 6); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 67 | vex_printf("%%fake%d", r); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 68 | return; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 69 | case HRcVec128: |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 70 | r = hregNumber(reg); |
| 71 | vassert(r >= 0 && r < 8); |
| 72 | vex_printf("%%xmm%d", r); |
| 73 | return; |
| 74 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 75 | vpanic("ppHRegX86"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 76 | } |
| 77 | } |
| 78 | |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 79 | HReg hregX86_EAX ( void ) { return mkHReg(0, HRcInt32, False); } |
| 80 | HReg hregX86_ECX ( void ) { return mkHReg(1, HRcInt32, False); } |
| 81 | HReg hregX86_EDX ( void ) { return mkHReg(2, HRcInt32, False); } |
| 82 | HReg hregX86_EBX ( void ) { return mkHReg(3, HRcInt32, False); } |
| 83 | HReg hregX86_ESP ( void ) { return mkHReg(4, HRcInt32, False); } |
| 84 | HReg hregX86_EBP ( void ) { return mkHReg(5, HRcInt32, False); } |
| 85 | HReg hregX86_ESI ( void ) { return mkHReg(6, HRcInt32, False); } |
| 86 | HReg hregX86_EDI ( void ) { return mkHReg(7, HRcInt32, False); } |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 87 | |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 88 | HReg hregX86_FAKE0 ( void ) { return mkHReg(0, HRcFlt64, False); } |
| 89 | HReg hregX86_FAKE1 ( void ) { return mkHReg(1, HRcFlt64, False); } |
| 90 | HReg hregX86_FAKE2 ( void ) { return mkHReg(2, HRcFlt64, False); } |
| 91 | HReg hregX86_FAKE3 ( void ) { return mkHReg(3, HRcFlt64, False); } |
| 92 | HReg hregX86_FAKE4 ( void ) { return mkHReg(4, HRcFlt64, False); } |
| 93 | HReg hregX86_FAKE5 ( void ) { return mkHReg(5, HRcFlt64, False); } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 94 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 95 | HReg hregX86_XMM0 ( void ) { return mkHReg(0, HRcVec128, False); } |
| 96 | HReg hregX86_XMM1 ( void ) { return mkHReg(1, HRcVec128, False); } |
| 97 | HReg hregX86_XMM2 ( void ) { return mkHReg(2, HRcVec128, False); } |
| 98 | HReg hregX86_XMM3 ( void ) { return mkHReg(3, HRcVec128, False); } |
| 99 | HReg hregX86_XMM4 ( void ) { return mkHReg(4, HRcVec128, False); } |
| 100 | HReg hregX86_XMM5 ( void ) { return mkHReg(5, HRcVec128, False); } |
| 101 | HReg hregX86_XMM6 ( void ) { return mkHReg(6, HRcVec128, False); } |
| 102 | HReg hregX86_XMM7 ( void ) { return mkHReg(7, HRcVec128, False); } |
| 103 | |
| 104 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 105 | void getAllocableRegs_X86 ( Int* nregs, HReg** arr ) |
| 106 | { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 107 | *nregs = 20; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 108 | *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); |
sewardj | 0a5f5c8 | 2004-07-07 11:56:35 +0000 | [diff] [blame] | 109 | (*arr)[0] = hregX86_EAX(); |
| 110 | (*arr)[1] = hregX86_EBX(); |
| 111 | (*arr)[2] = hregX86_ECX(); |
| 112 | (*arr)[3] = hregX86_EDX(); |
| 113 | (*arr)[4] = hregX86_ESI(); |
| 114 | (*arr)[5] = hregX86_EDI(); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 115 | (*arr)[6] = hregX86_FAKE0(); |
| 116 | (*arr)[7] = hregX86_FAKE1(); |
| 117 | (*arr)[8] = hregX86_FAKE2(); |
| 118 | (*arr)[9] = hregX86_FAKE3(); |
sewardj | eafde5a | 2004-10-09 01:36:57 +0000 | [diff] [blame] | 119 | (*arr)[10] = hregX86_FAKE4(); |
| 120 | (*arr)[11] = hregX86_FAKE5(); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 121 | (*arr)[12] = hregX86_XMM0(); |
| 122 | (*arr)[13] = hregX86_XMM1(); |
| 123 | (*arr)[14] = hregX86_XMM2(); |
| 124 | (*arr)[15] = hregX86_XMM3(); |
| 125 | (*arr)[16] = hregX86_XMM4(); |
| 126 | (*arr)[17] = hregX86_XMM5(); |
| 127 | (*arr)[18] = hregX86_XMM6(); |
| 128 | (*arr)[19] = hregX86_XMM7(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 129 | } |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 130 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 131 | |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 132 | /* --------- Condition codes, Intel encoding. --------- */ |
| 133 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 134 | const HChar* showX86CondCode ( X86CondCode cond ) |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 135 | { |
| 136 | switch (cond) { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 137 | case Xcc_O: return "o"; |
| 138 | case Xcc_NO: return "no"; |
| 139 | case Xcc_B: return "b"; |
| 140 | case Xcc_NB: return "nb"; |
| 141 | case Xcc_Z: return "z"; |
| 142 | case Xcc_NZ: return "nz"; |
| 143 | case Xcc_BE: return "be"; |
| 144 | case Xcc_NBE: return "nbe"; |
| 145 | case Xcc_S: return "s"; |
| 146 | case Xcc_NS: return "ns"; |
| 147 | case Xcc_P: return "p"; |
| 148 | case Xcc_NP: return "np"; |
| 149 | case Xcc_L: return "l"; |
| 150 | case Xcc_NL: return "nl"; |
| 151 | case Xcc_LE: return "le"; |
| 152 | case Xcc_NLE: return "nle"; |
| 153 | case Xcc_ALWAYS: return "ALWAYS"; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 154 | default: vpanic("ppX86CondCode"); |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 159 | /* --------- X86AMode: memory address expressions. --------- */ |
| 160 | |
| 161 | X86AMode* X86AMode_IR ( UInt imm32, HReg reg ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 162 | X86AMode* am = LibVEX_Alloc(sizeof(X86AMode)); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 163 | am->tag = Xam_IR; |
| 164 | am->Xam.IR.imm = imm32; |
| 165 | am->Xam.IR.reg = reg; |
| 166 | return am; |
| 167 | } |
sewardj | 0e63b52 | 2004-08-25 13:24:44 +0000 | [diff] [blame] | 168 | X86AMode* X86AMode_IRRS ( UInt imm32, HReg base, HReg indEx, Int shift ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 169 | X86AMode* am = LibVEX_Alloc(sizeof(X86AMode)); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 170 | am->tag = Xam_IRRS; |
| 171 | am->Xam.IRRS.imm = imm32; |
| 172 | am->Xam.IRRS.base = base; |
sewardj | 0e63b52 | 2004-08-25 13:24:44 +0000 | [diff] [blame] | 173 | am->Xam.IRRS.index = indEx; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 174 | am->Xam.IRRS.shift = shift; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 175 | vassert(shift >= 0 && shift <= 3); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 176 | return am; |
| 177 | } |
| 178 | |
sewardj | 218e29f | 2004-11-07 18:45:15 +0000 | [diff] [blame] | 179 | X86AMode* dopyX86AMode ( X86AMode* am ) { |
| 180 | switch (am->tag) { |
| 181 | case Xam_IR: |
| 182 | return X86AMode_IR( am->Xam.IR.imm, am->Xam.IR.reg ); |
| 183 | case Xam_IRRS: |
| 184 | return X86AMode_IRRS( am->Xam.IRRS.imm, am->Xam.IRRS.base, |
| 185 | am->Xam.IRRS.index, am->Xam.IRRS.shift ); |
| 186 | default: |
| 187 | vpanic("dopyX86AMode"); |
| 188 | } |
| 189 | } |
| 190 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 191 | void ppX86AMode ( X86AMode* am ) { |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 192 | switch (am->tag) { |
| 193 | case Xam_IR: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 194 | if (am->Xam.IR.imm == 0) |
| 195 | vex_printf("("); |
| 196 | else |
| 197 | vex_printf("0x%x(", am->Xam.IR.imm); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 198 | ppHRegX86(am->Xam.IR.reg); |
| 199 | vex_printf(")"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 200 | return; |
| 201 | case Xam_IRRS: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 202 | vex_printf("0x%x(", am->Xam.IRRS.imm); |
| 203 | ppHRegX86(am->Xam.IRRS.base); |
| 204 | vex_printf(","); |
| 205 | ppHRegX86(am->Xam.IRRS.index); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 206 | vex_printf(",%d)", 1 << am->Xam.IRRS.shift); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 207 | return; |
| 208 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 209 | vpanic("ppX86AMode"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 210 | } |
| 211 | } |
| 212 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 213 | static void addRegUsage_X86AMode ( HRegUsage* u, X86AMode* am ) { |
| 214 | switch (am->tag) { |
| 215 | case Xam_IR: |
| 216 | addHRegUse(u, HRmRead, am->Xam.IR.reg); |
| 217 | return; |
| 218 | case Xam_IRRS: |
| 219 | addHRegUse(u, HRmRead, am->Xam.IRRS.base); |
| 220 | addHRegUse(u, HRmRead, am->Xam.IRRS.index); |
| 221 | return; |
| 222 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 223 | vpanic("addRegUsage_X86AMode"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 224 | } |
| 225 | } |
| 226 | |
| 227 | static void mapRegs_X86AMode ( HRegRemap* m, X86AMode* am ) { |
| 228 | switch (am->tag) { |
| 229 | case Xam_IR: |
| 230 | am->Xam.IR.reg = lookupHRegRemap(m, am->Xam.IR.reg); |
| 231 | return; |
| 232 | case Xam_IRRS: |
| 233 | am->Xam.IRRS.base = lookupHRegRemap(m, am->Xam.IRRS.base); |
| 234 | am->Xam.IRRS.index = lookupHRegRemap(m, am->Xam.IRRS.index); |
| 235 | return; |
| 236 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 237 | vpanic("mapRegs_X86AMode"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 238 | } |
| 239 | } |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 240 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 241 | /* --------- Operand, which can be reg, immediate or memory. --------- */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 242 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 243 | X86RMI* X86RMI_Imm ( UInt imm32 ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 244 | X86RMI* op = LibVEX_Alloc(sizeof(X86RMI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 245 | op->tag = Xrmi_Imm; |
| 246 | op->Xrmi.Imm.imm32 = imm32; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 247 | return op; |
| 248 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 249 | X86RMI* X86RMI_Reg ( HReg reg ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 250 | X86RMI* op = LibVEX_Alloc(sizeof(X86RMI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 251 | op->tag = Xrmi_Reg; |
| 252 | op->Xrmi.Reg.reg = reg; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 253 | return op; |
| 254 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 255 | X86RMI* X86RMI_Mem ( X86AMode* am ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 256 | X86RMI* op = LibVEX_Alloc(sizeof(X86RMI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 257 | op->tag = Xrmi_Mem; |
| 258 | op->Xrmi.Mem.am = am; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 259 | return op; |
| 260 | } |
| 261 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 262 | void ppX86RMI ( X86RMI* op ) { |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 263 | switch (op->tag) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 264 | case Xrmi_Imm: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 265 | vex_printf("$0x%x", op->Xrmi.Imm.imm32); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 266 | return; |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 267 | case Xrmi_Reg: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 268 | ppHRegX86(op->Xrmi.Reg.reg); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 269 | return; |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 270 | case Xrmi_Mem: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 271 | ppX86AMode(op->Xrmi.Mem.am); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 272 | return; |
| 273 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 274 | vpanic("ppX86RMI"); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 275 | } |
| 276 | } |
| 277 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 278 | /* An X86RMI can only be used in a "read" context (what would it mean |
| 279 | to write or modify a literal?) and so we enumerate its registers |
| 280 | accordingly. */ |
| 281 | static void addRegUsage_X86RMI ( HRegUsage* u, X86RMI* op ) { |
| 282 | switch (op->tag) { |
| 283 | case Xrmi_Imm: |
| 284 | return; |
| 285 | case Xrmi_Reg: |
| 286 | addHRegUse(u, HRmRead, op->Xrmi.Reg.reg); |
| 287 | return; |
| 288 | case Xrmi_Mem: |
| 289 | addRegUsage_X86AMode(u, op->Xrmi.Mem.am); |
| 290 | return; |
| 291 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 292 | vpanic("addRegUsage_X86RMI"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 293 | } |
| 294 | } |
| 295 | |
| 296 | static void mapRegs_X86RMI ( HRegRemap* m, X86RMI* op ) { |
| 297 | switch (op->tag) { |
| 298 | case Xrmi_Imm: |
| 299 | return; |
| 300 | case Xrmi_Reg: |
| 301 | op->Xrmi.Reg.reg = lookupHRegRemap(m, op->Xrmi.Reg.reg); |
| 302 | return; |
| 303 | case Xrmi_Mem: |
| 304 | mapRegs_X86AMode(m, op->Xrmi.Mem.am); |
| 305 | return; |
| 306 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 307 | vpanic("mapRegs_X86RMI"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 308 | } |
| 309 | } |
| 310 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 311 | |
| 312 | /* --------- Operand, which can be reg or immediate only. --------- */ |
| 313 | |
| 314 | X86RI* X86RI_Imm ( UInt imm32 ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 315 | X86RI* op = LibVEX_Alloc(sizeof(X86RI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 316 | op->tag = Xri_Imm; |
| 317 | op->Xri.Imm.imm32 = imm32; |
| 318 | return op; |
| 319 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 320 | X86RI* X86RI_Reg ( HReg reg ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 321 | X86RI* op = LibVEX_Alloc(sizeof(X86RI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 322 | op->tag = Xri_Reg; |
| 323 | op->Xri.Reg.reg = reg; |
| 324 | return op; |
| 325 | } |
| 326 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 327 | void ppX86RI ( X86RI* op ) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 328 | switch (op->tag) { |
| 329 | case Xri_Imm: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 330 | vex_printf("$0x%x", op->Xri.Imm.imm32); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 331 | return; |
| 332 | case Xri_Reg: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 333 | ppHRegX86(op->Xri.Reg.reg); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 334 | return; |
| 335 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 336 | vpanic("ppX86RI"); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 337 | } |
| 338 | } |
| 339 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 340 | /* An X86RI can only be used in a "read" context (what would it mean |
| 341 | to write or modify a literal?) and so we enumerate its registers |
| 342 | accordingly. */ |
| 343 | static void addRegUsage_X86RI ( HRegUsage* u, X86RI* op ) { |
| 344 | switch (op->tag) { |
| 345 | case Xri_Imm: |
| 346 | return; |
| 347 | case Xri_Reg: |
| 348 | addHRegUse(u, HRmRead, op->Xri.Reg.reg); |
| 349 | return; |
| 350 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 351 | vpanic("addRegUsage_X86RI"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 352 | } |
| 353 | } |
| 354 | |
| 355 | static void mapRegs_X86RI ( HRegRemap* m, X86RI* op ) { |
| 356 | switch (op->tag) { |
| 357 | case Xri_Imm: |
| 358 | return; |
| 359 | case Xri_Reg: |
| 360 | op->Xri.Reg.reg = lookupHRegRemap(m, op->Xri.Reg.reg); |
| 361 | return; |
| 362 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 363 | vpanic("mapRegs_X86RI"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 364 | } |
| 365 | } |
| 366 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 367 | |
| 368 | /* --------- Operand, which can be reg or memory only. --------- */ |
| 369 | |
| 370 | X86RM* X86RM_Reg ( HReg reg ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 371 | X86RM* op = LibVEX_Alloc(sizeof(X86RM)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 372 | op->tag = Xrm_Reg; |
| 373 | op->Xrm.Reg.reg = reg; |
| 374 | return op; |
| 375 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 376 | X86RM* X86RM_Mem ( X86AMode* am ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 377 | X86RM* op = LibVEX_Alloc(sizeof(X86RM)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 378 | op->tag = Xrm_Mem; |
| 379 | op->Xrm.Mem.am = am; |
| 380 | return op; |
| 381 | } |
| 382 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 383 | void ppX86RM ( X86RM* op ) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 384 | switch (op->tag) { |
| 385 | case Xrm_Mem: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 386 | ppX86AMode(op->Xrm.Mem.am); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 387 | return; |
| 388 | case Xrm_Reg: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 389 | ppHRegX86(op->Xrm.Reg.reg); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 390 | return; |
| 391 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 392 | vpanic("ppX86RM"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 393 | } |
| 394 | } |
| 395 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 396 | /* Because an X86RM can be both a source or destination operand, we |
| 397 | have to supply a mode -- pertaining to the operand as a whole -- |
| 398 | indicating how it's being used. */ |
| 399 | static void addRegUsage_X86RM ( HRegUsage* u, X86RM* op, HRegMode mode ) { |
| 400 | switch (op->tag) { |
| 401 | case Xrm_Mem: |
| 402 | /* Memory is read, written or modified. So we just want to |
| 403 | know the regs read by the amode. */ |
| 404 | addRegUsage_X86AMode(u, op->Xrm.Mem.am); |
| 405 | return; |
| 406 | case Xrm_Reg: |
| 407 | /* reg is read, written or modified. Add it in the |
| 408 | appropriate way. */ |
| 409 | addHRegUse(u, mode, op->Xrm.Reg.reg); |
| 410 | return; |
| 411 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 412 | vpanic("addRegUsage_X86RM"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 413 | } |
| 414 | } |
| 415 | |
| 416 | static void mapRegs_X86RM ( HRegRemap* m, X86RM* op ) |
| 417 | { |
| 418 | switch (op->tag) { |
| 419 | case Xrm_Mem: |
| 420 | mapRegs_X86AMode(m, op->Xrm.Mem.am); |
| 421 | return; |
| 422 | case Xrm_Reg: |
| 423 | op->Xrm.Reg.reg = lookupHRegRemap(m, op->Xrm.Reg.reg); |
| 424 | return; |
| 425 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 426 | vpanic("mapRegs_X86RM"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 427 | } |
| 428 | } |
| 429 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 430 | |
| 431 | /* --------- Instructions. --------- */ |
| 432 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 433 | const HChar* showX86UnaryOp ( X86UnaryOp op ) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 434 | switch (op) { |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 435 | case Xun_NOT: return "not"; |
| 436 | case Xun_NEG: return "neg"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 437 | default: vpanic("showX86UnaryOp"); |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 438 | } |
| 439 | } |
| 440 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 441 | const HChar* showX86AluOp ( X86AluOp op ) { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 442 | switch (op) { |
| 443 | case Xalu_MOV: return "mov"; |
| 444 | case Xalu_CMP: return "cmp"; |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 445 | case Xalu_ADD: return "add"; |
| 446 | case Xalu_SUB: return "sub"; |
| 447 | case Xalu_ADC: return "adc"; |
| 448 | case Xalu_SBB: return "sbb"; |
| 449 | case Xalu_AND: return "and"; |
| 450 | case Xalu_OR: return "or"; |
| 451 | case Xalu_XOR: return "xor"; |
| 452 | case Xalu_MUL: return "mul"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 453 | default: vpanic("showX86AluOp"); |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 454 | } |
| 455 | } |
| 456 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 457 | const HChar* showX86ShiftOp ( X86ShiftOp op ) { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 458 | switch (op) { |
| 459 | case Xsh_SHL: return "shl"; |
| 460 | case Xsh_SHR: return "shr"; |
| 461 | case Xsh_SAR: return "sar"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 462 | default: vpanic("showX86ShiftOp"); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 463 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 464 | } |
| 465 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 466 | const HChar* showX86FpOp ( X86FpOp op ) { |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 467 | switch (op) { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 468 | case Xfp_ADD: return "add"; |
| 469 | case Xfp_SUB: return "sub"; |
| 470 | case Xfp_MUL: return "mul"; |
| 471 | case Xfp_DIV: return "div"; |
sewardj | 8d38778 | 2004-11-11 02:15:15 +0000 | [diff] [blame] | 472 | case Xfp_SCALE: return "scale"; |
| 473 | case Xfp_ATAN: return "atan"; |
| 474 | case Xfp_YL2X: return "yl2x"; |
| 475 | case Xfp_YL2XP1: return "yl2xp1"; |
| 476 | case Xfp_PREM: return "prem"; |
| 477 | case Xfp_PREM1: return "prem1"; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 478 | case Xfp_SQRT: return "sqrt"; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 479 | case Xfp_ABS: return "abs"; |
sewardj | 8d38778 | 2004-11-11 02:15:15 +0000 | [diff] [blame] | 480 | case Xfp_NEG: return "chs"; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 481 | case Xfp_MOV: return "mov"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 482 | case Xfp_SIN: return "sin"; |
| 483 | case Xfp_COS: return "cos"; |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 484 | case Xfp_TAN: return "tan"; |
sewardj | 8d38778 | 2004-11-11 02:15:15 +0000 | [diff] [blame] | 485 | case Xfp_ROUND: return "round"; |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 486 | case Xfp_2XM1: return "2xm1"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 487 | default: vpanic("showX86FpOp"); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 488 | } |
| 489 | } |
| 490 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 491 | const HChar* showX86SseOp ( X86SseOp op ) { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 492 | switch (op) { |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 493 | case Xsse_MOV: return "mov(?!)"; |
| 494 | case Xsse_ADDF: return "add"; |
| 495 | case Xsse_SUBF: return "sub"; |
| 496 | case Xsse_MULF: return "mul"; |
| 497 | case Xsse_DIVF: return "div"; |
| 498 | case Xsse_MAXF: return "max"; |
| 499 | case Xsse_MINF: return "min"; |
| 500 | case Xsse_CMPEQF: return "cmpFeq"; |
| 501 | case Xsse_CMPLTF: return "cmpFlt"; |
| 502 | case Xsse_CMPLEF: return "cmpFle"; |
| 503 | case Xsse_CMPUNF: return "cmpFun"; |
| 504 | case Xsse_RCPF: return "rcp"; |
| 505 | case Xsse_RSQRTF: return "rsqrt"; |
| 506 | case Xsse_SQRTF: return "sqrt"; |
| 507 | case Xsse_AND: return "and"; |
| 508 | case Xsse_OR: return "or"; |
| 509 | case Xsse_XOR: return "xor"; |
| 510 | case Xsse_ANDN: return "andn"; |
| 511 | case Xsse_ADD8: return "paddb"; |
| 512 | case Xsse_ADD16: return "paddw"; |
| 513 | case Xsse_ADD32: return "paddd"; |
| 514 | case Xsse_ADD64: return "paddq"; |
| 515 | case Xsse_QADD8U: return "paddusb"; |
| 516 | case Xsse_QADD16U: return "paddusw"; |
| 517 | case Xsse_QADD8S: return "paddsb"; |
| 518 | case Xsse_QADD16S: return "paddsw"; |
| 519 | case Xsse_SUB8: return "psubb"; |
| 520 | case Xsse_SUB16: return "psubw"; |
| 521 | case Xsse_SUB32: return "psubd"; |
| 522 | case Xsse_SUB64: return "psubq"; |
| 523 | case Xsse_QSUB8U: return "psubusb"; |
| 524 | case Xsse_QSUB16U: return "psubusw"; |
| 525 | case Xsse_QSUB8S: return "psubsb"; |
| 526 | case Xsse_QSUB16S: return "psubsw"; |
| 527 | case Xsse_MUL16: return "pmullw"; |
| 528 | case Xsse_MULHI16U: return "pmulhuw"; |
| 529 | case Xsse_MULHI16S: return "pmulhw"; |
| 530 | case Xsse_AVG8U: return "pavgb"; |
| 531 | case Xsse_AVG16U: return "pavgw"; |
| 532 | case Xsse_MAX16S: return "pmaxw"; |
| 533 | case Xsse_MAX8U: return "pmaxub"; |
| 534 | case Xsse_MIN16S: return "pminw"; |
| 535 | case Xsse_MIN8U: return "pminub"; |
| 536 | case Xsse_CMPEQ8: return "pcmpeqb"; |
| 537 | case Xsse_CMPEQ16: return "pcmpeqw"; |
| 538 | case Xsse_CMPEQ32: return "pcmpeqd"; |
| 539 | case Xsse_CMPGT8S: return "pcmpgtb"; |
| 540 | case Xsse_CMPGT16S: return "pcmpgtw"; |
| 541 | case Xsse_CMPGT32S: return "pcmpgtd"; |
| 542 | case Xsse_SHL16: return "psllw"; |
| 543 | case Xsse_SHL32: return "pslld"; |
| 544 | case Xsse_SHL64: return "psllq"; |
| 545 | case Xsse_SHR16: return "psrlw"; |
| 546 | case Xsse_SHR32: return "psrld"; |
| 547 | case Xsse_SHR64: return "psrlq"; |
| 548 | case Xsse_SAR16: return "psraw"; |
| 549 | case Xsse_SAR32: return "psrad"; |
| 550 | case Xsse_PACKSSD: return "packssdw"; |
| 551 | case Xsse_PACKSSW: return "packsswb"; |
| 552 | case Xsse_PACKUSW: return "packuswb"; |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 553 | case Xsse_UNPCKHB: return "punpckhb"; |
| 554 | case Xsse_UNPCKHW: return "punpckhw"; |
| 555 | case Xsse_UNPCKHD: return "punpckhd"; |
| 556 | case Xsse_UNPCKHQ: return "punpckhq"; |
| 557 | case Xsse_UNPCKLB: return "punpcklb"; |
| 558 | case Xsse_UNPCKLW: return "punpcklw"; |
| 559 | case Xsse_UNPCKLD: return "punpckld"; |
| 560 | case Xsse_UNPCKLQ: return "punpcklq"; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 561 | default: vpanic("showX86SseOp"); |
| 562 | } |
| 563 | } |
| 564 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 565 | X86Instr* X86Instr_Alu32R ( X86AluOp op, X86RMI* src, HReg dst ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 566 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 567 | i->tag = Xin_Alu32R; |
| 568 | i->Xin.Alu32R.op = op; |
| 569 | i->Xin.Alu32R.src = src; |
| 570 | i->Xin.Alu32R.dst = dst; |
| 571 | return i; |
| 572 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 573 | X86Instr* X86Instr_Alu32M ( X86AluOp op, X86RI* src, X86AMode* dst ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 574 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 575 | i->tag = Xin_Alu32M; |
| 576 | i->Xin.Alu32M.op = op; |
| 577 | i->Xin.Alu32M.src = src; |
| 578 | i->Xin.Alu32M.dst = dst; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 579 | vassert(op != Xalu_MUL); |
| 580 | return i; |
| 581 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 582 | X86Instr* X86Instr_Sh32 ( X86ShiftOp op, UInt src, HReg dst ) { |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 583 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 584 | i->tag = Xin_Sh32; |
| 585 | i->Xin.Sh32.op = op; |
| 586 | i->Xin.Sh32.src = src; |
| 587 | i->Xin.Sh32.dst = dst; |
| 588 | return i; |
| 589 | } |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 590 | X86Instr* X86Instr_Test32 ( UInt imm32, X86RM* dst ) { |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 591 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 592 | i->tag = Xin_Test32; |
| 593 | i->Xin.Test32.imm32 = imm32; |
| 594 | i->Xin.Test32.dst = dst; |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 595 | return i; |
| 596 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 597 | X86Instr* X86Instr_Unary32 ( X86UnaryOp op, HReg dst ) { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 598 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 599 | i->tag = Xin_Unary32; |
| 600 | i->Xin.Unary32.op = op; |
| 601 | i->Xin.Unary32.dst = dst; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 602 | return i; |
| 603 | } |
sewardj | 79e04f8 | 2007-03-31 14:30:12 +0000 | [diff] [blame] | 604 | X86Instr* X86Instr_Lea32 ( X86AMode* am, HReg dst ) { |
| 605 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 606 | i->tag = Xin_Lea32; |
| 607 | i->Xin.Lea32.am = am; |
| 608 | i->Xin.Lea32.dst = dst; |
| 609 | return i; |
| 610 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 611 | X86Instr* X86Instr_MulL ( Bool syned, X86RM* src ) { |
sewardj | 597b71b | 2004-07-19 02:51:12 +0000 | [diff] [blame] | 612 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 613 | i->tag = Xin_MulL; |
| 614 | i->Xin.MulL.syned = syned; |
sewardj | 597b71b | 2004-07-19 02:51:12 +0000 | [diff] [blame] | 615 | i->Xin.MulL.src = src; |
| 616 | return i; |
| 617 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 618 | X86Instr* X86Instr_Div ( Bool syned, X86RM* src ) { |
| 619 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 620 | i->tag = Xin_Div; |
| 621 | i->Xin.Div.syned = syned; |
| 622 | i->Xin.Div.src = src; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 623 | return i; |
| 624 | } |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 625 | X86Instr* X86Instr_Sh3232 ( X86ShiftOp op, UInt amt, HReg src, HReg dst ) { |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 626 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 627 | i->tag = Xin_Sh3232; |
| 628 | i->Xin.Sh3232.op = op; |
| 629 | i->Xin.Sh3232.amt = amt; |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 630 | i->Xin.Sh3232.src = src; |
| 631 | i->Xin.Sh3232.dst = dst; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 632 | vassert(op == Xsh_SHL || op == Xsh_SHR); |
| 633 | return i; |
| 634 | } |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 635 | X86Instr* X86Instr_Push( X86RMI* src ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 636 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 637 | i->tag = Xin_Push; |
| 638 | i->Xin.Push.src = src; |
| 639 | return i; |
| 640 | } |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame^] | 641 | X86Instr* X86Instr_Call ( X86CondCode cond, Addr32 target, Int regparms, |
| 642 | RetLoc rloc ) { |
sewardj | 7735254 | 2004-10-30 20:39:01 +0000 | [diff] [blame] | 643 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 644 | i->tag = Xin_Call; |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 645 | i->Xin.Call.cond = cond; |
sewardj | 7735254 | 2004-10-30 20:39:01 +0000 | [diff] [blame] | 646 | i->Xin.Call.target = target; |
| 647 | i->Xin.Call.regparms = regparms; |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame^] | 648 | i->Xin.Call.rloc = rloc; |
sewardj | 7735254 | 2004-10-30 20:39:01 +0000 | [diff] [blame] | 649 | vassert(regparms >= 0 && regparms <= 3); |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame^] | 650 | vassert(rloc != RetLocINVALID); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 651 | return i; |
| 652 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 653 | X86Instr* X86Instr_XDirect ( Addr32 dstGA, X86AMode* amEIP, |
| 654 | X86CondCode cond, Bool toFastEP ) { |
| 655 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 656 | i->tag = Xin_XDirect; |
| 657 | i->Xin.XDirect.dstGA = dstGA; |
| 658 | i->Xin.XDirect.amEIP = amEIP; |
| 659 | i->Xin.XDirect.cond = cond; |
| 660 | i->Xin.XDirect.toFastEP = toFastEP; |
| 661 | return i; |
| 662 | } |
| 663 | X86Instr* X86Instr_XIndir ( HReg dstGA, X86AMode* amEIP, |
| 664 | X86CondCode cond ) { |
| 665 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 666 | i->tag = Xin_XIndir; |
| 667 | i->Xin.XIndir.dstGA = dstGA; |
| 668 | i->Xin.XIndir.amEIP = amEIP; |
| 669 | i->Xin.XIndir.cond = cond; |
| 670 | return i; |
| 671 | } |
| 672 | X86Instr* X86Instr_XAssisted ( HReg dstGA, X86AMode* amEIP, |
| 673 | X86CondCode cond, IRJumpKind jk ) { |
| 674 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 675 | i->tag = Xin_XAssisted; |
| 676 | i->Xin.XAssisted.dstGA = dstGA; |
| 677 | i->Xin.XAssisted.amEIP = amEIP; |
| 678 | i->Xin.XAssisted.cond = cond; |
| 679 | i->Xin.XAssisted.jk = jk; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 680 | return i; |
| 681 | } |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 682 | X86Instr* X86Instr_CMov32 ( X86CondCode cond, X86RM* src, HReg dst ) { |
| 683 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 684 | i->tag = Xin_CMov32; |
| 685 | i->Xin.CMov32.cond = cond; |
| 686 | i->Xin.CMov32.src = src; |
| 687 | i->Xin.CMov32.dst = dst; |
| 688 | vassert(cond != Xcc_ALWAYS); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 689 | return i; |
| 690 | } |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 691 | X86Instr* X86Instr_LoadEX ( UChar szSmall, Bool syned, |
| 692 | X86AMode* src, HReg dst ) { |
| 693 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 694 | i->tag = Xin_LoadEX; |
| 695 | i->Xin.LoadEX.szSmall = szSmall; |
| 696 | i->Xin.LoadEX.syned = syned; |
| 697 | i->Xin.LoadEX.src = src; |
| 698 | i->Xin.LoadEX.dst = dst; |
| 699 | vassert(szSmall == 1 || szSmall == 2); |
| 700 | return i; |
| 701 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 702 | X86Instr* X86Instr_Store ( UChar sz, HReg src, X86AMode* dst ) { |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 703 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 704 | i->tag = Xin_Store; |
| 705 | i->Xin.Store.sz = sz; |
| 706 | i->Xin.Store.src = src; |
| 707 | i->Xin.Store.dst = dst; |
| 708 | vassert(sz == 1 || sz == 2); |
| 709 | return i; |
| 710 | } |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 711 | X86Instr* X86Instr_Set32 ( X86CondCode cond, HReg dst ) { |
| 712 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 713 | i->tag = Xin_Set32; |
| 714 | i->Xin.Set32.cond = cond; |
| 715 | i->Xin.Set32.dst = dst; |
| 716 | return i; |
| 717 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 718 | X86Instr* X86Instr_Bsfr32 ( Bool isFwds, HReg src, HReg dst ) { |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 719 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 720 | i->tag = Xin_Bsfr32; |
| 721 | i->Xin.Bsfr32.isFwds = isFwds; |
| 722 | i->Xin.Bsfr32.src = src; |
| 723 | i->Xin.Bsfr32.dst = dst; |
| 724 | return i; |
| 725 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 726 | X86Instr* X86Instr_MFence ( UInt hwcaps ) { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 727 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 728 | i->tag = Xin_MFence; |
| 729 | i->Xin.MFence.hwcaps = hwcaps; |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 730 | vassert(0 == (hwcaps & ~(VEX_HWCAPS_X86_SSE1 |
| 731 | |VEX_HWCAPS_X86_SSE2 |
| 732 | |VEX_HWCAPS_X86_SSE3 |
| 733 | |VEX_HWCAPS_X86_LZCNT))); |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 734 | return i; |
| 735 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 736 | X86Instr* X86Instr_ACAS ( X86AMode* addr, UChar sz ) { |
| 737 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 738 | i->tag = Xin_ACAS; |
| 739 | i->Xin.ACAS.addr = addr; |
| 740 | i->Xin.ACAS.sz = sz; |
| 741 | vassert(sz == 4 || sz == 2 || sz == 1); |
| 742 | return i; |
| 743 | } |
| 744 | X86Instr* X86Instr_DACAS ( X86AMode* addr ) { |
| 745 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 746 | i->tag = Xin_DACAS; |
| 747 | i->Xin.DACAS.addr = addr; |
| 748 | return i; |
| 749 | } |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 750 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 751 | X86Instr* X86Instr_FpUnary ( X86FpOp op, HReg src, HReg dst ) { |
| 752 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 753 | i->tag = Xin_FpUnary; |
| 754 | i->Xin.FpUnary.op = op; |
| 755 | i->Xin.FpUnary.src = src; |
| 756 | i->Xin.FpUnary.dst = dst; |
| 757 | return i; |
| 758 | } |
| 759 | X86Instr* X86Instr_FpBinary ( X86FpOp op, HReg srcL, HReg srcR, HReg dst ) { |
| 760 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 761 | i->tag = Xin_FpBinary; |
| 762 | i->Xin.FpBinary.op = op; |
| 763 | i->Xin.FpBinary.srcL = srcL; |
| 764 | i->Xin.FpBinary.srcR = srcR; |
| 765 | i->Xin.FpBinary.dst = dst; |
| 766 | return i; |
| 767 | } |
| 768 | X86Instr* X86Instr_FpLdSt ( Bool isLoad, UChar sz, HReg reg, X86AMode* addr ) { |
| 769 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 770 | i->tag = Xin_FpLdSt; |
| 771 | i->Xin.FpLdSt.isLoad = isLoad; |
| 772 | i->Xin.FpLdSt.sz = sz; |
| 773 | i->Xin.FpLdSt.reg = reg; |
| 774 | i->Xin.FpLdSt.addr = addr; |
sewardj | 7fb65eb | 2007-03-25 04:14:58 +0000 | [diff] [blame] | 775 | vassert(sz == 4 || sz == 8 || sz == 10); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 776 | return i; |
| 777 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 778 | X86Instr* X86Instr_FpLdStI ( Bool isLoad, UChar sz, |
| 779 | HReg reg, X86AMode* addr ) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 780 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 781 | i->tag = Xin_FpLdStI; |
| 782 | i->Xin.FpLdStI.isLoad = isLoad; |
| 783 | i->Xin.FpLdStI.sz = sz; |
| 784 | i->Xin.FpLdStI.reg = reg; |
| 785 | i->Xin.FpLdStI.addr = addr; |
| 786 | vassert(sz == 2 || sz == 4 || sz == 8); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 787 | return i; |
| 788 | } |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 789 | X86Instr* X86Instr_Fp64to32 ( HReg src, HReg dst ) { |
| 790 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 791 | i->tag = Xin_Fp64to32; |
| 792 | i->Xin.Fp64to32.src = src; |
| 793 | i->Xin.Fp64to32.dst = dst; |
| 794 | return i; |
| 795 | } |
sewardj | 33124f6 | 2004-08-30 17:54:18 +0000 | [diff] [blame] | 796 | X86Instr* X86Instr_FpCMov ( X86CondCode cond, HReg src, HReg dst ) { |
| 797 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 798 | i->tag = Xin_FpCMov; |
| 799 | i->Xin.FpCMov.cond = cond; |
| 800 | i->Xin.FpCMov.src = src; |
| 801 | i->Xin.FpCMov.dst = dst; |
| 802 | vassert(cond != Xcc_ALWAYS); |
| 803 | return i; |
| 804 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 805 | X86Instr* X86Instr_FpLdCW ( X86AMode* addr ) { |
| 806 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 807 | i->tag = Xin_FpLdCW; |
| 808 | i->Xin.FpLdCW.addr = addr; |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 809 | return i; |
| 810 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 811 | X86Instr* X86Instr_FpStSW_AX ( void ) { |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 812 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 813 | i->tag = Xin_FpStSW_AX; |
| 814 | return i; |
| 815 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 816 | X86Instr* X86Instr_FpCmp ( HReg srcL, HReg srcR, HReg dst ) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 817 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 818 | i->tag = Xin_FpCmp; |
| 819 | i->Xin.FpCmp.srcL = srcL; |
| 820 | i->Xin.FpCmp.srcR = srcR; |
| 821 | i->Xin.FpCmp.dst = dst; |
| 822 | return i; |
| 823 | } |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 824 | X86Instr* X86Instr_SseConst ( UShort con, HReg dst ) { |
| 825 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 826 | i->tag = Xin_SseConst; |
| 827 | i->Xin.SseConst.con = con; |
| 828 | i->Xin.SseConst.dst = dst; |
| 829 | vassert(hregClass(dst) == HRcVec128); |
| 830 | return i; |
| 831 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 832 | X86Instr* X86Instr_SseLdSt ( Bool isLoad, HReg reg, X86AMode* addr ) { |
| 833 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 834 | i->tag = Xin_SseLdSt; |
| 835 | i->Xin.SseLdSt.isLoad = isLoad; |
| 836 | i->Xin.SseLdSt.reg = reg; |
| 837 | i->Xin.SseLdSt.addr = addr; |
| 838 | return i; |
| 839 | } |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 840 | X86Instr* X86Instr_SseLdzLO ( Int sz, HReg reg, X86AMode* addr ) |
| 841 | { |
| 842 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 843 | i->tag = Xin_SseLdzLO; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 844 | i->Xin.SseLdzLO.sz = toUChar(sz); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 845 | i->Xin.SseLdzLO.reg = reg; |
| 846 | i->Xin.SseLdzLO.addr = addr; |
| 847 | vassert(sz == 4 || sz == 8); |
| 848 | return i; |
| 849 | } |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 850 | X86Instr* X86Instr_Sse32Fx4 ( X86SseOp op, HReg src, HReg dst ) { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 851 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 852 | i->tag = Xin_Sse32Fx4; |
| 853 | i->Xin.Sse32Fx4.op = op; |
| 854 | i->Xin.Sse32Fx4.src = src; |
| 855 | i->Xin.Sse32Fx4.dst = dst; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 856 | vassert(op != Xsse_MOV); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 857 | return i; |
| 858 | } |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 859 | X86Instr* X86Instr_Sse32FLo ( X86SseOp op, HReg src, HReg dst ) { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 860 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 861 | i->tag = Xin_Sse32FLo; |
| 862 | i->Xin.Sse32FLo.op = op; |
| 863 | i->Xin.Sse32FLo.src = src; |
| 864 | i->Xin.Sse32FLo.dst = dst; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 865 | vassert(op != Xsse_MOV); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 866 | return i; |
| 867 | } |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 868 | X86Instr* X86Instr_Sse64Fx2 ( X86SseOp op, HReg src, HReg dst ) { |
| 869 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 870 | i->tag = Xin_Sse64Fx2; |
| 871 | i->Xin.Sse64Fx2.op = op; |
| 872 | i->Xin.Sse64Fx2.src = src; |
| 873 | i->Xin.Sse64Fx2.dst = dst; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 874 | vassert(op != Xsse_MOV); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 875 | return i; |
| 876 | } |
| 877 | X86Instr* X86Instr_Sse64FLo ( X86SseOp op, HReg src, HReg dst ) { |
| 878 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 879 | i->tag = Xin_Sse64FLo; |
| 880 | i->Xin.Sse64FLo.op = op; |
| 881 | i->Xin.Sse64FLo.src = src; |
| 882 | i->Xin.Sse64FLo.dst = dst; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 883 | vassert(op != Xsse_MOV); |
| 884 | return i; |
| 885 | } |
| 886 | X86Instr* X86Instr_SseReRg ( X86SseOp op, HReg re, HReg rg ) { |
| 887 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 888 | i->tag = Xin_SseReRg; |
| 889 | i->Xin.SseReRg.op = op; |
| 890 | i->Xin.SseReRg.src = re; |
| 891 | i->Xin.SseReRg.dst = rg; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 892 | return i; |
| 893 | } |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 894 | X86Instr* X86Instr_SseCMov ( X86CondCode cond, HReg src, HReg dst ) { |
| 895 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 896 | i->tag = Xin_SseCMov; |
| 897 | i->Xin.SseCMov.cond = cond; |
| 898 | i->Xin.SseCMov.src = src; |
| 899 | i->Xin.SseCMov.dst = dst; |
| 900 | vassert(cond != Xcc_ALWAYS); |
| 901 | return i; |
| 902 | } |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 903 | X86Instr* X86Instr_SseShuf ( Int order, HReg src, HReg dst ) { |
| 904 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 905 | i->tag = Xin_SseShuf; |
| 906 | i->Xin.SseShuf.order = order; |
| 907 | i->Xin.SseShuf.src = src; |
| 908 | i->Xin.SseShuf.dst = dst; |
| 909 | vassert(order >= 0 && order <= 0xFF); |
| 910 | return i; |
| 911 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 912 | X86Instr* X86Instr_EvCheck ( X86AMode* amCounter, |
| 913 | X86AMode* amFailAddr ) { |
| 914 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 915 | i->tag = Xin_EvCheck; |
| 916 | i->Xin.EvCheck.amCounter = amCounter; |
| 917 | i->Xin.EvCheck.amFailAddr = amFailAddr; |
| 918 | return i; |
| 919 | } |
| 920 | X86Instr* X86Instr_ProfInc ( void ) { |
| 921 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 922 | i->tag = Xin_ProfInc; |
| 923 | return i; |
| 924 | } |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 925 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 926 | void ppX86Instr ( X86Instr* i, Bool mode64 ) { |
| 927 | vassert(mode64 == False); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 928 | switch (i->tag) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 929 | case Xin_Alu32R: |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 930 | vex_printf("%sl ", showX86AluOp(i->Xin.Alu32R.op)); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 931 | ppX86RMI(i->Xin.Alu32R.src); |
| 932 | vex_printf(","); |
| 933 | ppHRegX86(i->Xin.Alu32R.dst); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 934 | return; |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 935 | case Xin_Alu32M: |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 936 | vex_printf("%sl ", showX86AluOp(i->Xin.Alu32M.op)); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 937 | ppX86RI(i->Xin.Alu32M.src); |
| 938 | vex_printf(","); |
| 939 | ppX86AMode(i->Xin.Alu32M.dst); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 940 | return; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 941 | case Xin_Sh32: |
| 942 | vex_printf("%sl ", showX86ShiftOp(i->Xin.Sh32.op)); |
| 943 | if (i->Xin.Sh32.src == 0) |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 944 | vex_printf("%%cl,"); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 945 | else |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 946 | vex_printf("$%d,", (Int)i->Xin.Sh32.src); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 947 | ppHRegX86(i->Xin.Sh32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 948 | return; |
| 949 | case Xin_Test32: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 950 | vex_printf("testl $%d,", (Int)i->Xin.Test32.imm32); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 951 | ppX86RM(i->Xin.Test32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 952 | return; |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 953 | case Xin_Unary32: |
| 954 | vex_printf("%sl ", showX86UnaryOp(i->Xin.Unary32.op)); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 955 | ppHRegX86(i->Xin.Unary32.dst); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 956 | return; |
sewardj | 79e04f8 | 2007-03-31 14:30:12 +0000 | [diff] [blame] | 957 | case Xin_Lea32: |
| 958 | vex_printf("leal "); |
| 959 | ppX86AMode(i->Xin.Lea32.am); |
| 960 | vex_printf(","); |
| 961 | ppHRegX86(i->Xin.Lea32.dst); |
| 962 | return; |
sewardj | 597b71b | 2004-07-19 02:51:12 +0000 | [diff] [blame] | 963 | case Xin_MulL: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 964 | vex_printf("%cmull ", i->Xin.MulL.syned ? 's' : 'u'); |
sewardj | 597b71b | 2004-07-19 02:51:12 +0000 | [diff] [blame] | 965 | ppX86RM(i->Xin.MulL.src); |
| 966 | return; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 967 | case Xin_Div: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 968 | vex_printf("%cdivl ", i->Xin.Div.syned ? 's' : 'u'); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 969 | ppX86RM(i->Xin.Div.src); |
| 970 | return; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 971 | case Xin_Sh3232: |
| 972 | vex_printf("%sdl ", showX86ShiftOp(i->Xin.Sh3232.op)); |
| 973 | if (i->Xin.Sh3232.amt == 0) |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 974 | vex_printf(" %%cl,"); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 975 | else |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 976 | vex_printf(" $%d,", (Int)i->Xin.Sh3232.amt); |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 977 | ppHRegX86(i->Xin.Sh3232.src); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 978 | vex_printf(","); |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 979 | ppHRegX86(i->Xin.Sh3232.dst); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 980 | return; |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 981 | case Xin_Push: |
| 982 | vex_printf("pushl "); |
| 983 | ppX86RMI(i->Xin.Push.src); |
| 984 | return; |
| 985 | case Xin_Call: |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame^] | 986 | vex_printf("call%s[%d,", |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 987 | i->Xin.Call.cond==Xcc_ALWAYS |
| 988 | ? "" : showX86CondCode(i->Xin.Call.cond), |
| 989 | i->Xin.Call.regparms); |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame^] | 990 | ppRetLoc(i->Xin.Call.rloc); |
| 991 | vex_printf("] 0x%x", i->Xin.Call.target); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 992 | break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 993 | case Xin_XDirect: |
| 994 | vex_printf("(xDirect) "); |
| 995 | vex_printf("if (%%eflags.%s) { ", |
| 996 | showX86CondCode(i->Xin.XDirect.cond)); |
| 997 | vex_printf("movl $0x%x,", i->Xin.XDirect.dstGA); |
| 998 | ppX86AMode(i->Xin.XDirect.amEIP); |
| 999 | vex_printf("; "); |
| 1000 | vex_printf("movl $disp_cp_chain_me_to_%sEP,%%edx; call *%%edx }", |
| 1001 | i->Xin.XDirect.toFastEP ? "fast" : "slow"); |
| 1002 | return; |
| 1003 | case Xin_XIndir: |
| 1004 | vex_printf("(xIndir) "); |
| 1005 | vex_printf("if (%%eflags.%s) { movl ", |
| 1006 | showX86CondCode(i->Xin.XIndir.cond)); |
| 1007 | ppHRegX86(i->Xin.XIndir.dstGA); |
| 1008 | vex_printf(","); |
| 1009 | ppX86AMode(i->Xin.XIndir.amEIP); |
| 1010 | vex_printf("; movl $disp_indir,%%edx; jmp *%%edx }"); |
| 1011 | return; |
| 1012 | case Xin_XAssisted: |
| 1013 | vex_printf("(xAssisted) "); |
| 1014 | vex_printf("if (%%eflags.%s) { ", |
| 1015 | showX86CondCode(i->Xin.XAssisted.cond)); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1016 | vex_printf("movl "); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1017 | ppHRegX86(i->Xin.XAssisted.dstGA); |
| 1018 | vex_printf(","); |
| 1019 | ppX86AMode(i->Xin.XAssisted.amEIP); |
| 1020 | vex_printf("; movl $IRJumpKind_to_TRCVAL(%d),%%ebp", |
| 1021 | (Int)i->Xin.XAssisted.jk); |
| 1022 | vex_printf("; movl $disp_assisted,%%edx; jmp *%%edx }"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1023 | return; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 1024 | case Xin_CMov32: |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 1025 | vex_printf("cmov%s ", showX86CondCode(i->Xin.CMov32.cond)); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 1026 | ppX86RM(i->Xin.CMov32.src); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 1027 | vex_printf(","); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 1028 | ppHRegX86(i->Xin.CMov32.dst); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 1029 | return; |
| 1030 | case Xin_LoadEX: |
| 1031 | vex_printf("mov%c%cl ", |
| 1032 | i->Xin.LoadEX.syned ? 's' : 'z', |
| 1033 | i->Xin.LoadEX.szSmall==1 ? 'b' : 'w'); |
| 1034 | ppX86AMode(i->Xin.LoadEX.src); |
| 1035 | vex_printf(","); |
| 1036 | ppHRegX86(i->Xin.LoadEX.dst); |
| 1037 | return; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 1038 | case Xin_Store: |
| 1039 | vex_printf("mov%c ", i->Xin.Store.sz==1 ? 'b' : 'w'); |
| 1040 | ppHRegX86(i->Xin.Store.src); |
| 1041 | vex_printf(","); |
| 1042 | ppX86AMode(i->Xin.Store.dst); |
| 1043 | return; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 1044 | case Xin_Set32: |
| 1045 | vex_printf("setl%s ", showX86CondCode(i->Xin.Set32.cond)); |
| 1046 | ppHRegX86(i->Xin.Set32.dst); |
| 1047 | return; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 1048 | case Xin_Bsfr32: |
| 1049 | vex_printf("bs%cl ", i->Xin.Bsfr32.isFwds ? 'f' : 'r'); |
| 1050 | ppHRegX86(i->Xin.Bsfr32.src); |
| 1051 | vex_printf(","); |
| 1052 | ppHRegX86(i->Xin.Bsfr32.dst); |
| 1053 | return; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 1054 | case Xin_MFence: |
| 1055 | vex_printf("mfence(%s)", |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1056 | LibVEX_ppVexHwCaps(VexArchX86,i->Xin.MFence.hwcaps)); |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 1057 | return; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1058 | case Xin_ACAS: |
| 1059 | vex_printf("lock cmpxchg%c ", |
| 1060 | i->Xin.ACAS.sz==1 ? 'b' |
| 1061 | : i->Xin.ACAS.sz==2 ? 'w' : 'l'); |
| 1062 | vex_printf("{%%eax->%%ebx},"); |
| 1063 | ppX86AMode(i->Xin.ACAS.addr); |
| 1064 | return; |
| 1065 | case Xin_DACAS: |
| 1066 | vex_printf("lock cmpxchg8b {%%edx:%%eax->%%ecx:%%ebx},"); |
| 1067 | ppX86AMode(i->Xin.DACAS.addr); |
| 1068 | return; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1069 | case Xin_FpUnary: |
| 1070 | vex_printf("g%sD ", showX86FpOp(i->Xin.FpUnary.op)); |
| 1071 | ppHRegX86(i->Xin.FpUnary.src); |
| 1072 | vex_printf(","); |
| 1073 | ppHRegX86(i->Xin.FpUnary.dst); |
| 1074 | break; |
| 1075 | case Xin_FpBinary: |
| 1076 | vex_printf("g%sD ", showX86FpOp(i->Xin.FpBinary.op)); |
| 1077 | ppHRegX86(i->Xin.FpBinary.srcL); |
| 1078 | vex_printf(","); |
| 1079 | ppHRegX86(i->Xin.FpBinary.srcR); |
| 1080 | vex_printf(","); |
| 1081 | ppHRegX86(i->Xin.FpBinary.dst); |
| 1082 | break; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 1083 | case Xin_FpLdSt: |
| 1084 | if (i->Xin.FpLdSt.isLoad) { |
sewardj | 7fb65eb | 2007-03-25 04:14:58 +0000 | [diff] [blame] | 1085 | vex_printf("gld%c " , i->Xin.FpLdSt.sz==10 ? 'T' |
| 1086 | : (i->Xin.FpLdSt.sz==8 ? 'D' : 'F')); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 1087 | ppX86AMode(i->Xin.FpLdSt.addr); |
| 1088 | vex_printf(", "); |
| 1089 | ppHRegX86(i->Xin.FpLdSt.reg); |
| 1090 | } else { |
sewardj | 7fb65eb | 2007-03-25 04:14:58 +0000 | [diff] [blame] | 1091 | vex_printf("gst%c " , i->Xin.FpLdSt.sz==10 ? 'T' |
| 1092 | : (i->Xin.FpLdSt.sz==8 ? 'D' : 'F')); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 1093 | ppHRegX86(i->Xin.FpLdSt.reg); |
| 1094 | vex_printf(", "); |
| 1095 | ppX86AMode(i->Xin.FpLdSt.addr); |
| 1096 | } |
| 1097 | return; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 1098 | case Xin_FpLdStI: |
| 1099 | if (i->Xin.FpLdStI.isLoad) { |
| 1100 | vex_printf("gild%s ", i->Xin.FpLdStI.sz==8 ? "ll" : |
| 1101 | i->Xin.FpLdStI.sz==4 ? "l" : "w"); |
| 1102 | ppX86AMode(i->Xin.FpLdStI.addr); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1103 | vex_printf(", "); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 1104 | ppHRegX86(i->Xin.FpLdStI.reg); |
| 1105 | } else { |
| 1106 | vex_printf("gist%s ", i->Xin.FpLdStI.sz==8 ? "ll" : |
| 1107 | i->Xin.FpLdStI.sz==4 ? "l" : "w"); |
| 1108 | ppHRegX86(i->Xin.FpLdStI.reg); |
| 1109 | vex_printf(", "); |
| 1110 | ppX86AMode(i->Xin.FpLdStI.addr); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1111 | } |
| 1112 | return; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 1113 | case Xin_Fp64to32: |
| 1114 | vex_printf("gdtof "); |
| 1115 | ppHRegX86(i->Xin.Fp64to32.src); |
| 1116 | vex_printf(","); |
| 1117 | ppHRegX86(i->Xin.Fp64to32.dst); |
| 1118 | return; |
sewardj | 33124f6 | 2004-08-30 17:54:18 +0000 | [diff] [blame] | 1119 | case Xin_FpCMov: |
| 1120 | vex_printf("gcmov%s ", showX86CondCode(i->Xin.FpCMov.cond)); |
| 1121 | ppHRegX86(i->Xin.FpCMov.src); |
| 1122 | vex_printf(","); |
| 1123 | ppHRegX86(i->Xin.FpCMov.dst); |
| 1124 | return; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1125 | case Xin_FpLdCW: |
| 1126 | vex_printf("fldcw "); |
| 1127 | ppX86AMode(i->Xin.FpLdCW.addr); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 1128 | return; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 1129 | case Xin_FpStSW_AX: |
| 1130 | vex_printf("fstsw %%ax"); |
| 1131 | return; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 1132 | case Xin_FpCmp: |
| 1133 | vex_printf("gcmp "); |
| 1134 | ppHRegX86(i->Xin.FpCmp.srcL); |
| 1135 | vex_printf(","); |
| 1136 | ppHRegX86(i->Xin.FpCmp.srcR); |
| 1137 | vex_printf(","); |
| 1138 | ppHRegX86(i->Xin.FpCmp.dst); |
| 1139 | break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1140 | case Xin_SseConst: |
| 1141 | vex_printf("const $0x%04x,", (Int)i->Xin.SseConst.con); |
| 1142 | ppHRegX86(i->Xin.SseConst.dst); |
| 1143 | break; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1144 | case Xin_SseLdSt: |
| 1145 | vex_printf("movups "); |
| 1146 | if (i->Xin.SseLdSt.isLoad) { |
| 1147 | ppX86AMode(i->Xin.SseLdSt.addr); |
| 1148 | vex_printf(","); |
| 1149 | ppHRegX86(i->Xin.SseLdSt.reg); |
| 1150 | } else { |
| 1151 | ppHRegX86(i->Xin.SseLdSt.reg); |
| 1152 | vex_printf(","); |
| 1153 | ppX86AMode(i->Xin.SseLdSt.addr); |
| 1154 | } |
| 1155 | return; |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 1156 | case Xin_SseLdzLO: |
| 1157 | vex_printf("movs%s ", i->Xin.SseLdzLO.sz==4 ? "s" : "d"); |
| 1158 | ppX86AMode(i->Xin.SseLdzLO.addr); |
| 1159 | vex_printf(","); |
| 1160 | ppHRegX86(i->Xin.SseLdzLO.reg); |
| 1161 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1162 | case Xin_Sse32Fx4: |
| 1163 | vex_printf("%sps ", showX86SseOp(i->Xin.Sse32Fx4.op)); |
| 1164 | ppHRegX86(i->Xin.Sse32Fx4.src); |
| 1165 | vex_printf(","); |
| 1166 | ppHRegX86(i->Xin.Sse32Fx4.dst); |
| 1167 | return; |
| 1168 | case Xin_Sse32FLo: |
| 1169 | vex_printf("%sss ", showX86SseOp(i->Xin.Sse32FLo.op)); |
| 1170 | ppHRegX86(i->Xin.Sse32FLo.src); |
| 1171 | vex_printf(","); |
| 1172 | ppHRegX86(i->Xin.Sse32FLo.dst); |
| 1173 | return; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1174 | case Xin_Sse64Fx2: |
| 1175 | vex_printf("%spd ", showX86SseOp(i->Xin.Sse64Fx2.op)); |
| 1176 | ppHRegX86(i->Xin.Sse64Fx2.src); |
| 1177 | vex_printf(","); |
| 1178 | ppHRegX86(i->Xin.Sse64Fx2.dst); |
| 1179 | return; |
| 1180 | case Xin_Sse64FLo: |
| 1181 | vex_printf("%ssd ", showX86SseOp(i->Xin.Sse64FLo.op)); |
| 1182 | ppHRegX86(i->Xin.Sse64FLo.src); |
| 1183 | vex_printf(","); |
| 1184 | ppHRegX86(i->Xin.Sse64FLo.dst); |
| 1185 | return; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1186 | case Xin_SseReRg: |
| 1187 | vex_printf("%s ", showX86SseOp(i->Xin.SseReRg.op)); |
| 1188 | ppHRegX86(i->Xin.SseReRg.src); |
| 1189 | vex_printf(","); |
| 1190 | ppHRegX86(i->Xin.SseReRg.dst); |
| 1191 | return; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 1192 | case Xin_SseCMov: |
| 1193 | vex_printf("cmov%s ", showX86CondCode(i->Xin.SseCMov.cond)); |
| 1194 | ppHRegX86(i->Xin.SseCMov.src); |
| 1195 | vex_printf(","); |
| 1196 | ppHRegX86(i->Xin.SseCMov.dst); |
| 1197 | return; |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 1198 | case Xin_SseShuf: |
| 1199 | vex_printf("pshufd $0x%x,", i->Xin.SseShuf.order); |
| 1200 | ppHRegX86(i->Xin.SseShuf.src); |
| 1201 | vex_printf(","); |
| 1202 | ppHRegX86(i->Xin.SseShuf.dst); |
| 1203 | return; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1204 | case Xin_EvCheck: |
| 1205 | vex_printf("(evCheck) decl "); |
| 1206 | ppX86AMode(i->Xin.EvCheck.amCounter); |
| 1207 | vex_printf("; jns nofail; jmp *"); |
| 1208 | ppX86AMode(i->Xin.EvCheck.amFailAddr); |
| 1209 | vex_printf("; nofail:"); |
| 1210 | return; |
| 1211 | case Xin_ProfInc: |
| 1212 | vex_printf("(profInc) addl $1,NotKnownYet; " |
| 1213 | "adcl $0,NotKnownYet+4"); |
| 1214 | return; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1215 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1216 | vpanic("ppX86Instr"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1217 | } |
| 1218 | } |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1219 | |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1220 | /* --------- Helpers for register allocation. --------- */ |
| 1221 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1222 | void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i, Bool mode64) |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1223 | { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 1224 | Bool unary; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1225 | vassert(mode64 == False); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1226 | initHRegUsage(u); |
| 1227 | switch (i->tag) { |
| 1228 | case Xin_Alu32R: |
| 1229 | addRegUsage_X86RMI(u, i->Xin.Alu32R.src); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 1230 | if (i->Xin.Alu32R.op == Xalu_MOV) { |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1231 | addHRegUse(u, HRmWrite, i->Xin.Alu32R.dst); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 1232 | return; |
| 1233 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1234 | if (i->Xin.Alu32R.op == Xalu_CMP) { |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1235 | addHRegUse(u, HRmRead, i->Xin.Alu32R.dst); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 1236 | return; |
| 1237 | } |
| 1238 | addHRegUse(u, HRmModify, i->Xin.Alu32R.dst); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1239 | return; |
| 1240 | case Xin_Alu32M: |
| 1241 | addRegUsage_X86RI(u, i->Xin.Alu32M.src); |
| 1242 | addRegUsage_X86AMode(u, i->Xin.Alu32M.dst); |
| 1243 | return; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1244 | case Xin_Sh32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1245 | addHRegUse(u, HRmModify, i->Xin.Sh32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1246 | if (i->Xin.Sh32.src == 0) |
| 1247 | addHRegUse(u, HRmRead, hregX86_ECX()); |
| 1248 | return; |
| 1249 | case Xin_Test32: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 1250 | addRegUsage_X86RM(u, i->Xin.Test32.dst, HRmRead); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1251 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1252 | case Xin_Unary32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1253 | addHRegUse(u, HRmModify, i->Xin.Unary32.dst); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1254 | return; |
sewardj | 79e04f8 | 2007-03-31 14:30:12 +0000 | [diff] [blame] | 1255 | case Xin_Lea32: |
| 1256 | addRegUsage_X86AMode(u, i->Xin.Lea32.am); |
| 1257 | addHRegUse(u, HRmWrite, i->Xin.Lea32.dst); |
| 1258 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1259 | case Xin_MulL: |
| 1260 | addRegUsage_X86RM(u, i->Xin.MulL.src, HRmRead); |
| 1261 | addHRegUse(u, HRmModify, hregX86_EAX()); |
| 1262 | addHRegUse(u, HRmWrite, hregX86_EDX()); |
| 1263 | return; |
| 1264 | case Xin_Div: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1265 | addRegUsage_X86RM(u, i->Xin.Div.src, HRmRead); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1266 | addHRegUse(u, HRmModify, hregX86_EAX()); |
| 1267 | addHRegUse(u, HRmModify, hregX86_EDX()); |
| 1268 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1269 | case Xin_Sh3232: |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 1270 | addHRegUse(u, HRmRead, i->Xin.Sh3232.src); |
| 1271 | addHRegUse(u, HRmModify, i->Xin.Sh3232.dst); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1272 | if (i->Xin.Sh3232.amt == 0) |
| 1273 | addHRegUse(u, HRmRead, hregX86_ECX()); |
| 1274 | return; |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 1275 | case Xin_Push: |
| 1276 | addRegUsage_X86RMI(u, i->Xin.Push.src); |
| 1277 | addHRegUse(u, HRmModify, hregX86_ESP()); |
| 1278 | return; |
| 1279 | case Xin_Call: |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1280 | /* This is a bit subtle. */ |
sewardj | cdcf00b | 2005-02-04 01:40:03 +0000 | [diff] [blame] | 1281 | /* First off, claim it trashes all the caller-saved regs |
| 1282 | which fall within the register allocator's jurisdiction. |
sewardj | 9e341ca | 2009-07-22 11:06:17 +0000 | [diff] [blame] | 1283 | These I believe to be %eax %ecx %edx and all the xmm |
| 1284 | registers. */ |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 1285 | addHRegUse(u, HRmWrite, hregX86_EAX()); |
| 1286 | addHRegUse(u, HRmWrite, hregX86_ECX()); |
| 1287 | addHRegUse(u, HRmWrite, hregX86_EDX()); |
sewardj | 9e341ca | 2009-07-22 11:06:17 +0000 | [diff] [blame] | 1288 | addHRegUse(u, HRmWrite, hregX86_XMM0()); |
| 1289 | addHRegUse(u, HRmWrite, hregX86_XMM1()); |
| 1290 | addHRegUse(u, HRmWrite, hregX86_XMM2()); |
| 1291 | addHRegUse(u, HRmWrite, hregX86_XMM3()); |
| 1292 | addHRegUse(u, HRmWrite, hregX86_XMM4()); |
| 1293 | addHRegUse(u, HRmWrite, hregX86_XMM5()); |
| 1294 | addHRegUse(u, HRmWrite, hregX86_XMM6()); |
| 1295 | addHRegUse(u, HRmWrite, hregX86_XMM7()); |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1296 | /* Now we have to state any parameter-carrying registers |
| 1297 | which might be read. This depends on the regparmness. */ |
sewardj | 7735254 | 2004-10-30 20:39:01 +0000 | [diff] [blame] | 1298 | switch (i->Xin.Call.regparms) { |
| 1299 | case 3: addHRegUse(u, HRmRead, hregX86_ECX()); /*fallthru*/ |
| 1300 | case 2: addHRegUse(u, HRmRead, hregX86_EDX()); /*fallthru*/ |
| 1301 | case 1: addHRegUse(u, HRmRead, hregX86_EAX()); break; |
| 1302 | case 0: break; |
| 1303 | default: vpanic("getRegUsage_X86Instr:Call:regparms"); |
| 1304 | } |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1305 | /* Finally, there is the issue that the insn trashes a |
| 1306 | register because the literal target address has to be |
| 1307 | loaded into a register. Fortunately, for the 0/1/2 |
sewardj | 45c50eb | 2004-11-04 18:25:33 +0000 | [diff] [blame] | 1308 | regparm case, we can use EAX, EDX and ECX respectively, so |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1309 | this does not cause any further damage. For the 3-regparm |
| 1310 | case, we'll have to choose another register arbitrarily -- |
sewardj | 45c50eb | 2004-11-04 18:25:33 +0000 | [diff] [blame] | 1311 | since A, D and C are used for parameters -- and so we might |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1312 | as well choose EDI. */ |
| 1313 | if (i->Xin.Call.regparms == 3) |
| 1314 | addHRegUse(u, HRmWrite, hregX86_EDI()); |
| 1315 | /* Upshot of this is that the assembler really must observe |
| 1316 | the here-stated convention of which register to use as an |
| 1317 | address temporary, depending on the regparmness: 0==EAX, |
sewardj | 45c50eb | 2004-11-04 18:25:33 +0000 | [diff] [blame] | 1318 | 1==EDX, 2==ECX, 3==EDI. */ |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 1319 | return; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1320 | /* XDirect/XIndir/XAssisted are also a bit subtle. They |
| 1321 | conditionally exit the block. Hence we only need to list (1) |
| 1322 | the registers that they read, and (2) the registers that they |
| 1323 | write in the case where the block is not exited. (2) is |
| 1324 | empty, hence only (1) is relevant here. */ |
| 1325 | case Xin_XDirect: |
| 1326 | addRegUsage_X86AMode(u, i->Xin.XDirect.amEIP); |
| 1327 | return; |
| 1328 | case Xin_XIndir: |
| 1329 | addHRegUse(u, HRmRead, i->Xin.XIndir.dstGA); |
| 1330 | addRegUsage_X86AMode(u, i->Xin.XIndir.amEIP); |
| 1331 | return; |
| 1332 | case Xin_XAssisted: |
| 1333 | addHRegUse(u, HRmRead, i->Xin.XAssisted.dstGA); |
| 1334 | addRegUsage_X86AMode(u, i->Xin.XAssisted.amEIP); |
sewardj | 0ec3325 | 2004-07-03 13:30:00 +0000 | [diff] [blame] | 1335 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1336 | case Xin_CMov32: |
| 1337 | addRegUsage_X86RM(u, i->Xin.CMov32.src, HRmRead); |
| 1338 | addHRegUse(u, HRmModify, i->Xin.CMov32.dst); |
| 1339 | return; |
| 1340 | case Xin_LoadEX: |
| 1341 | addRegUsage_X86AMode(u, i->Xin.LoadEX.src); |
| 1342 | addHRegUse(u, HRmWrite, i->Xin.LoadEX.dst); |
| 1343 | return; |
| 1344 | case Xin_Store: |
| 1345 | addHRegUse(u, HRmRead, i->Xin.Store.src); |
| 1346 | addRegUsage_X86AMode(u, i->Xin.Store.dst); |
| 1347 | return; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 1348 | case Xin_Set32: |
| 1349 | addHRegUse(u, HRmWrite, i->Xin.Set32.dst); |
| 1350 | return; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 1351 | case Xin_Bsfr32: |
| 1352 | addHRegUse(u, HRmRead, i->Xin.Bsfr32.src); |
| 1353 | addHRegUse(u, HRmWrite, i->Xin.Bsfr32.dst); |
| 1354 | return; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 1355 | case Xin_MFence: |
| 1356 | return; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1357 | case Xin_ACAS: |
| 1358 | addRegUsage_X86AMode(u, i->Xin.ACAS.addr); |
| 1359 | addHRegUse(u, HRmRead, hregX86_EBX()); |
| 1360 | addHRegUse(u, HRmModify, hregX86_EAX()); |
| 1361 | return; |
| 1362 | case Xin_DACAS: |
| 1363 | addRegUsage_X86AMode(u, i->Xin.DACAS.addr); |
| 1364 | addHRegUse(u, HRmRead, hregX86_ECX()); |
| 1365 | addHRegUse(u, HRmRead, hregX86_EBX()); |
| 1366 | addHRegUse(u, HRmModify, hregX86_EDX()); |
| 1367 | addHRegUse(u, HRmModify, hregX86_EAX()); |
| 1368 | return; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1369 | case Xin_FpUnary: |
| 1370 | addHRegUse(u, HRmRead, i->Xin.FpUnary.src); |
| 1371 | addHRegUse(u, HRmWrite, i->Xin.FpUnary.dst); |
| 1372 | return; |
| 1373 | case Xin_FpBinary: |
| 1374 | addHRegUse(u, HRmRead, i->Xin.FpBinary.srcL); |
| 1375 | addHRegUse(u, HRmRead, i->Xin.FpBinary.srcR); |
| 1376 | addHRegUse(u, HRmWrite, i->Xin.FpBinary.dst); |
| 1377 | return; |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1378 | case Xin_FpLdSt: |
| 1379 | addRegUsage_X86AMode(u, i->Xin.FpLdSt.addr); |
| 1380 | addHRegUse(u, i->Xin.FpLdSt.isLoad ? HRmWrite : HRmRead, |
| 1381 | i->Xin.FpLdSt.reg); |
| 1382 | return; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 1383 | case Xin_FpLdStI: |
| 1384 | addRegUsage_X86AMode(u, i->Xin.FpLdStI.addr); |
| 1385 | addHRegUse(u, i->Xin.FpLdStI.isLoad ? HRmWrite : HRmRead, |
| 1386 | i->Xin.FpLdStI.reg); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1387 | return; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 1388 | case Xin_Fp64to32: |
| 1389 | addHRegUse(u, HRmRead, i->Xin.Fp64to32.src); |
| 1390 | addHRegUse(u, HRmWrite, i->Xin.Fp64to32.dst); |
| 1391 | return; |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 1392 | case Xin_FpCMov: |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 1393 | addHRegUse(u, HRmRead, i->Xin.FpCMov.src); |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 1394 | addHRegUse(u, HRmModify, i->Xin.FpCMov.dst); |
| 1395 | return; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1396 | case Xin_FpLdCW: |
| 1397 | addRegUsage_X86AMode(u, i->Xin.FpLdCW.addr); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 1398 | return; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 1399 | case Xin_FpStSW_AX: |
| 1400 | addHRegUse(u, HRmWrite, hregX86_EAX()); |
| 1401 | return; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 1402 | case Xin_FpCmp: |
| 1403 | addHRegUse(u, HRmRead, i->Xin.FpCmp.srcL); |
| 1404 | addHRegUse(u, HRmRead, i->Xin.FpCmp.srcR); |
| 1405 | addHRegUse(u, HRmWrite, i->Xin.FpCmp.dst); |
| 1406 | addHRegUse(u, HRmWrite, hregX86_EAX()); |
| 1407 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1408 | case Xin_SseLdSt: |
| 1409 | addRegUsage_X86AMode(u, i->Xin.SseLdSt.addr); |
| 1410 | addHRegUse(u, i->Xin.SseLdSt.isLoad ? HRmWrite : HRmRead, |
| 1411 | i->Xin.SseLdSt.reg); |
| 1412 | return; |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 1413 | case Xin_SseLdzLO: |
| 1414 | addRegUsage_X86AMode(u, i->Xin.SseLdzLO.addr); |
| 1415 | addHRegUse(u, HRmWrite, i->Xin.SseLdzLO.reg); |
| 1416 | return; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1417 | case Xin_SseConst: |
| 1418 | addHRegUse(u, HRmWrite, i->Xin.SseConst.dst); |
| 1419 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1420 | case Xin_Sse32Fx4: |
| 1421 | vassert(i->Xin.Sse32Fx4.op != Xsse_MOV); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1422 | unary = toBool( i->Xin.Sse32Fx4.op == Xsse_RCPF |
| 1423 | || i->Xin.Sse32Fx4.op == Xsse_RSQRTF |
| 1424 | || i->Xin.Sse32Fx4.op == Xsse_SQRTF ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 1425 | addHRegUse(u, HRmRead, i->Xin.Sse32Fx4.src); |
| 1426 | addHRegUse(u, unary ? HRmWrite : HRmModify, |
| 1427 | i->Xin.Sse32Fx4.dst); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1428 | return; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1429 | case Xin_Sse32FLo: |
| 1430 | vassert(i->Xin.Sse32FLo.op != Xsse_MOV); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1431 | unary = toBool( i->Xin.Sse32FLo.op == Xsse_RCPF |
| 1432 | || i->Xin.Sse32FLo.op == Xsse_RSQRTF |
| 1433 | || i->Xin.Sse32FLo.op == Xsse_SQRTF ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 1434 | addHRegUse(u, HRmRead, i->Xin.Sse32FLo.src); |
| 1435 | addHRegUse(u, unary ? HRmWrite : HRmModify, |
| 1436 | i->Xin.Sse32FLo.dst); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1437 | return; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1438 | case Xin_Sse64Fx2: |
| 1439 | vassert(i->Xin.Sse64Fx2.op != Xsse_MOV); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1440 | unary = toBool( i->Xin.Sse64Fx2.op == Xsse_RCPF |
| 1441 | || i->Xin.Sse64Fx2.op == Xsse_RSQRTF |
| 1442 | || i->Xin.Sse64Fx2.op == Xsse_SQRTF ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1443 | addHRegUse(u, HRmRead, i->Xin.Sse64Fx2.src); |
| 1444 | addHRegUse(u, unary ? HRmWrite : HRmModify, |
| 1445 | i->Xin.Sse64Fx2.dst); |
| 1446 | return; |
| 1447 | case Xin_Sse64FLo: |
| 1448 | vassert(i->Xin.Sse64FLo.op != Xsse_MOV); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1449 | unary = toBool( i->Xin.Sse64FLo.op == Xsse_RCPF |
| 1450 | || i->Xin.Sse64FLo.op == Xsse_RSQRTF |
| 1451 | || i->Xin.Sse64FLo.op == Xsse_SQRTF ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1452 | addHRegUse(u, HRmRead, i->Xin.Sse64FLo.src); |
| 1453 | addHRegUse(u, unary ? HRmWrite : HRmModify, |
| 1454 | i->Xin.Sse64FLo.dst); |
| 1455 | return; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1456 | case Xin_SseReRg: |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 1457 | if (i->Xin.SseReRg.op == Xsse_XOR |
| 1458 | && i->Xin.SseReRg.src == i->Xin.SseReRg.dst) { |
| 1459 | /* reg-alloc needs to understand 'xor r,r' as a write of r */ |
| 1460 | /* (as opposed to a rite of passage :-) */ |
| 1461 | addHRegUse(u, HRmWrite, i->Xin.SseReRg.dst); |
| 1462 | } else { |
| 1463 | addHRegUse(u, HRmRead, i->Xin.SseReRg.src); |
| 1464 | addHRegUse(u, i->Xin.SseReRg.op == Xsse_MOV |
| 1465 | ? HRmWrite : HRmModify, |
| 1466 | i->Xin.SseReRg.dst); |
| 1467 | } |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1468 | return; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 1469 | case Xin_SseCMov: |
| 1470 | addHRegUse(u, HRmRead, i->Xin.SseCMov.src); |
| 1471 | addHRegUse(u, HRmModify, i->Xin.SseCMov.dst); |
| 1472 | return; |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 1473 | case Xin_SseShuf: |
| 1474 | addHRegUse(u, HRmRead, i->Xin.SseShuf.src); |
| 1475 | addHRegUse(u, HRmWrite, i->Xin.SseShuf.dst); |
| 1476 | return; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1477 | case Xin_EvCheck: |
| 1478 | /* We expect both amodes only to mention %ebp, so this is in |
| 1479 | fact pointless, since %ebp isn't allocatable, but anyway.. */ |
| 1480 | addRegUsage_X86AMode(u, i->Xin.EvCheck.amCounter); |
| 1481 | addRegUsage_X86AMode(u, i->Xin.EvCheck.amFailAddr); |
| 1482 | return; |
| 1483 | case Xin_ProfInc: |
| 1484 | /* does not use any registers. */ |
| 1485 | return; |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1486 | default: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1487 | ppX86Instr(i, False); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1488 | vpanic("getRegUsage_X86Instr"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1489 | } |
| 1490 | } |
| 1491 | |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1492 | /* local helper */ |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1493 | static void mapReg( HRegRemap* m, HReg* r ) |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1494 | { |
| 1495 | *r = lookupHRegRemap(m, *r); |
| 1496 | } |
| 1497 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1498 | void mapRegs_X86Instr ( HRegRemap* m, X86Instr* i, Bool mode64 ) |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1499 | { |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1500 | vassert(mode64 == False); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1501 | switch (i->tag) { |
| 1502 | case Xin_Alu32R: |
| 1503 | mapRegs_X86RMI(m, i->Xin.Alu32R.src); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1504 | mapReg(m, &i->Xin.Alu32R.dst); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1505 | return; |
| 1506 | case Xin_Alu32M: |
| 1507 | mapRegs_X86RI(m, i->Xin.Alu32M.src); |
| 1508 | mapRegs_X86AMode(m, i->Xin.Alu32M.dst); |
| 1509 | return; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1510 | case Xin_Sh32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1511 | mapReg(m, &i->Xin.Sh32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1512 | return; |
| 1513 | case Xin_Test32: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 1514 | mapRegs_X86RM(m, i->Xin.Test32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1515 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1516 | case Xin_Unary32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1517 | mapReg(m, &i->Xin.Unary32.dst); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1518 | return; |
sewardj | 79e04f8 | 2007-03-31 14:30:12 +0000 | [diff] [blame] | 1519 | case Xin_Lea32: |
| 1520 | mapRegs_X86AMode(m, i->Xin.Lea32.am); |
| 1521 | mapReg(m, &i->Xin.Lea32.dst); |
| 1522 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1523 | case Xin_MulL: |
| 1524 | mapRegs_X86RM(m, i->Xin.MulL.src); |
| 1525 | return; |
| 1526 | case Xin_Div: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1527 | mapRegs_X86RM(m, i->Xin.Div.src); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1528 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1529 | case Xin_Sh3232: |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 1530 | mapReg(m, &i->Xin.Sh3232.src); |
| 1531 | mapReg(m, &i->Xin.Sh3232.dst); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1532 | return; |
| 1533 | case Xin_Push: |
| 1534 | mapRegs_X86RMI(m, i->Xin.Push.src); |
| 1535 | return; |
| 1536 | case Xin_Call: |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1537 | return; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1538 | case Xin_XDirect: |
| 1539 | mapRegs_X86AMode(m, i->Xin.XDirect.amEIP); |
| 1540 | return; |
| 1541 | case Xin_XIndir: |
| 1542 | mapReg(m, &i->Xin.XIndir.dstGA); |
| 1543 | mapRegs_X86AMode(m, i->Xin.XIndir.amEIP); |
| 1544 | return; |
| 1545 | case Xin_XAssisted: |
| 1546 | mapReg(m, &i->Xin.XAssisted.dstGA); |
| 1547 | mapRegs_X86AMode(m, i->Xin.XAssisted.amEIP); |
sewardj | 0ec3325 | 2004-07-03 13:30:00 +0000 | [diff] [blame] | 1548 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1549 | case Xin_CMov32: |
| 1550 | mapRegs_X86RM(m, i->Xin.CMov32.src); |
| 1551 | mapReg(m, &i->Xin.CMov32.dst); |
| 1552 | return; |
| 1553 | case Xin_LoadEX: |
| 1554 | mapRegs_X86AMode(m, i->Xin.LoadEX.src); |
| 1555 | mapReg(m, &i->Xin.LoadEX.dst); |
| 1556 | return; |
| 1557 | case Xin_Store: |
| 1558 | mapReg(m, &i->Xin.Store.src); |
| 1559 | mapRegs_X86AMode(m, i->Xin.Store.dst); |
| 1560 | return; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 1561 | case Xin_Set32: |
| 1562 | mapReg(m, &i->Xin.Set32.dst); |
| 1563 | return; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 1564 | case Xin_Bsfr32: |
| 1565 | mapReg(m, &i->Xin.Bsfr32.src); |
| 1566 | mapReg(m, &i->Xin.Bsfr32.dst); |
| 1567 | return; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 1568 | case Xin_MFence: |
| 1569 | return; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1570 | case Xin_ACAS: |
| 1571 | mapRegs_X86AMode(m, i->Xin.ACAS.addr); |
| 1572 | return; |
| 1573 | case Xin_DACAS: |
| 1574 | mapRegs_X86AMode(m, i->Xin.DACAS.addr); |
| 1575 | return; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 1576 | case Xin_FpUnary: |
| 1577 | mapReg(m, &i->Xin.FpUnary.src); |
| 1578 | mapReg(m, &i->Xin.FpUnary.dst); |
| 1579 | return; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1580 | case Xin_FpBinary: |
| 1581 | mapReg(m, &i->Xin.FpBinary.srcL); |
| 1582 | mapReg(m, &i->Xin.FpBinary.srcR); |
| 1583 | mapReg(m, &i->Xin.FpBinary.dst); |
| 1584 | return; |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1585 | case Xin_FpLdSt: |
| 1586 | mapRegs_X86AMode(m, i->Xin.FpLdSt.addr); |
| 1587 | mapReg(m, &i->Xin.FpLdSt.reg); |
| 1588 | return; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 1589 | case Xin_FpLdStI: |
| 1590 | mapRegs_X86AMode(m, i->Xin.FpLdStI.addr); |
| 1591 | mapReg(m, &i->Xin.FpLdStI.reg); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1592 | return; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 1593 | case Xin_Fp64to32: |
| 1594 | mapReg(m, &i->Xin.Fp64to32.src); |
| 1595 | mapReg(m, &i->Xin.Fp64to32.dst); |
| 1596 | return; |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 1597 | case Xin_FpCMov: |
| 1598 | mapReg(m, &i->Xin.FpCMov.src); |
| 1599 | mapReg(m, &i->Xin.FpCMov.dst); |
| 1600 | return; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1601 | case Xin_FpLdCW: |
| 1602 | mapRegs_X86AMode(m, i->Xin.FpLdCW.addr); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 1603 | return; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 1604 | case Xin_FpStSW_AX: |
| 1605 | return; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 1606 | case Xin_FpCmp: |
| 1607 | mapReg(m, &i->Xin.FpCmp.srcL); |
| 1608 | mapReg(m, &i->Xin.FpCmp.srcR); |
| 1609 | mapReg(m, &i->Xin.FpCmp.dst); |
| 1610 | return; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1611 | case Xin_SseConst: |
| 1612 | mapReg(m, &i->Xin.SseConst.dst); |
| 1613 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1614 | case Xin_SseLdSt: |
| 1615 | mapReg(m, &i->Xin.SseLdSt.reg); |
| 1616 | mapRegs_X86AMode(m, i->Xin.SseLdSt.addr); |
| 1617 | break; |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 1618 | case Xin_SseLdzLO: |
| 1619 | mapReg(m, &i->Xin.SseLdzLO.reg); |
| 1620 | mapRegs_X86AMode(m, i->Xin.SseLdzLO.addr); |
| 1621 | break; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1622 | case Xin_Sse32Fx4: |
| 1623 | mapReg(m, &i->Xin.Sse32Fx4.src); |
| 1624 | mapReg(m, &i->Xin.Sse32Fx4.dst); |
| 1625 | return; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1626 | case Xin_Sse32FLo: |
| 1627 | mapReg(m, &i->Xin.Sse32FLo.src); |
| 1628 | mapReg(m, &i->Xin.Sse32FLo.dst); |
| 1629 | return; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1630 | case Xin_Sse64Fx2: |
| 1631 | mapReg(m, &i->Xin.Sse64Fx2.src); |
| 1632 | mapReg(m, &i->Xin.Sse64Fx2.dst); |
| 1633 | return; |
| 1634 | case Xin_Sse64FLo: |
| 1635 | mapReg(m, &i->Xin.Sse64FLo.src); |
| 1636 | mapReg(m, &i->Xin.Sse64FLo.dst); |
| 1637 | return; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1638 | case Xin_SseReRg: |
| 1639 | mapReg(m, &i->Xin.SseReRg.src); |
| 1640 | mapReg(m, &i->Xin.SseReRg.dst); |
| 1641 | return; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 1642 | case Xin_SseCMov: |
| 1643 | mapReg(m, &i->Xin.SseCMov.src); |
| 1644 | mapReg(m, &i->Xin.SseCMov.dst); |
| 1645 | return; |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 1646 | case Xin_SseShuf: |
| 1647 | mapReg(m, &i->Xin.SseShuf.src); |
| 1648 | mapReg(m, &i->Xin.SseShuf.dst); |
| 1649 | return; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1650 | case Xin_EvCheck: |
| 1651 | /* We expect both amodes only to mention %ebp, so this is in |
| 1652 | fact pointless, since %ebp isn't allocatable, but anyway.. */ |
| 1653 | mapRegs_X86AMode(m, i->Xin.EvCheck.amCounter); |
| 1654 | mapRegs_X86AMode(m, i->Xin.EvCheck.amFailAddr); |
| 1655 | return; |
| 1656 | case Xin_ProfInc: |
| 1657 | /* does not use any registers. */ |
| 1658 | return; |
| 1659 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1660 | default: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1661 | ppX86Instr(i, mode64); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1662 | vpanic("mapRegs_X86Instr"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1663 | } |
| 1664 | } |
| 1665 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1666 | /* Figure out if i represents a reg-reg move, and if so assign the |
| 1667 | source and destination to *src and *dst. If in doubt say No. Used |
| 1668 | by the register allocator to do move coalescing. |
| 1669 | */ |
sewardj | a9a0cd2 | 2004-07-03 14:49:41 +0000 | [diff] [blame] | 1670 | Bool isMove_X86Instr ( X86Instr* i, HReg* src, HReg* dst ) |
| 1671 | { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1672 | /* Moves between integer regs */ |
| 1673 | if (i->tag == Xin_Alu32R) { |
| 1674 | if (i->Xin.Alu32R.op != Xalu_MOV) |
| 1675 | return False; |
| 1676 | if (i->Xin.Alu32R.src->tag != Xrmi_Reg) |
| 1677 | return False; |
| 1678 | *src = i->Xin.Alu32R.src->Xrmi.Reg.reg; |
| 1679 | *dst = i->Xin.Alu32R.dst; |
| 1680 | return True; |
| 1681 | } |
| 1682 | /* Moves between FP regs */ |
| 1683 | if (i->tag == Xin_FpUnary) { |
| 1684 | if (i->Xin.FpUnary.op != Xfp_MOV) |
| 1685 | return False; |
| 1686 | *src = i->Xin.FpUnary.src; |
| 1687 | *dst = i->Xin.FpUnary.dst; |
| 1688 | return True; |
| 1689 | } |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 1690 | if (i->tag == Xin_SseReRg) { |
| 1691 | if (i->Xin.SseReRg.op != Xsse_MOV) |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1692 | return False; |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 1693 | *src = i->Xin.SseReRg.src; |
| 1694 | *dst = i->Xin.SseReRg.dst; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1695 | return True; |
| 1696 | } |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1697 | return False; |
sewardj | a9a0cd2 | 2004-07-03 14:49:41 +0000 | [diff] [blame] | 1698 | } |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1699 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1700 | |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1701 | /* Generate x86 spill/reload instructions under the direction of the |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1702 | register allocator. Note it's critical these don't write the |
| 1703 | condition codes. */ |
sewardj | 14731f2 | 2004-07-25 01:24:28 +0000 | [diff] [blame] | 1704 | |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1705 | void genSpill_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 1706 | HReg rreg, Int offsetB, Bool mode64 ) |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1707 | { |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1708 | X86AMode* am; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1709 | vassert(offsetB >= 0); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1710 | vassert(!hregIsVirtual(rreg)); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1711 | vassert(mode64 == False); |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1712 | *i1 = *i2 = NULL; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1713 | am = X86AMode_IR(offsetB, hregX86_EBP()); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1714 | switch (hregClass(rreg)) { |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1715 | case HRcInt32: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1716 | *i1 = X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am ); |
| 1717 | return; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1718 | case HRcFlt64: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1719 | *i1 = X86Instr_FpLdSt ( False/*store*/, 10, rreg, am ); |
| 1720 | return; |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 1721 | case HRcVec128: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1722 | *i1 = X86Instr_SseLdSt ( False/*store*/, rreg, am ); |
| 1723 | return; |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1724 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1725 | ppHRegClass(hregClass(rreg)); |
| 1726 | vpanic("genSpill_X86: unimplemented regclass"); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1727 | } |
| 1728 | } |
| 1729 | |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1730 | void genReload_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 1731 | HReg rreg, Int offsetB, Bool mode64 ) |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1732 | { |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1733 | X86AMode* am; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1734 | vassert(offsetB >= 0); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1735 | vassert(!hregIsVirtual(rreg)); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1736 | vassert(mode64 == False); |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1737 | *i1 = *i2 = NULL; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1738 | am = X86AMode_IR(offsetB, hregX86_EBP()); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1739 | switch (hregClass(rreg)) { |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1740 | case HRcInt32: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1741 | *i1 = X86Instr_Alu32R ( Xalu_MOV, X86RMI_Mem(am), rreg ); |
| 1742 | return; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1743 | case HRcFlt64: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1744 | *i1 = X86Instr_FpLdSt ( True/*load*/, 10, rreg, am ); |
| 1745 | return; |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 1746 | case HRcVec128: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 1747 | *i1 = X86Instr_SseLdSt ( True/*load*/, rreg, am ); |
| 1748 | return; |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1749 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1750 | ppHRegClass(hregClass(rreg)); |
| 1751 | vpanic("genReload_X86: unimplemented regclass"); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1752 | } |
| 1753 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1754 | |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 1755 | /* The given instruction reads the specified vreg exactly once, and |
| 1756 | that vreg is currently located at the given spill offset. If |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 1757 | possible, return a variant of the instruction to one which instead |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 1758 | references the spill slot directly. */ |
| 1759 | |
| 1760 | X86Instr* directReload_X86( X86Instr* i, HReg vreg, Short spill_off ) |
| 1761 | { |
| 1762 | vassert(spill_off >= 0 && spill_off < 10000); /* let's say */ |
| 1763 | |
| 1764 | /* Deal with form: src=RMI_Reg, dst=Reg where src == vreg |
| 1765 | Convert to: src=RMI_Mem, dst=Reg |
| 1766 | */ |
| 1767 | if (i->tag == Xin_Alu32R |
| 1768 | && (i->Xin.Alu32R.op == Xalu_MOV || i->Xin.Alu32R.op == Xalu_OR |
| 1769 | || i->Xin.Alu32R.op == Xalu_XOR) |
| 1770 | && i->Xin.Alu32R.src->tag == Xrmi_Reg |
| 1771 | && i->Xin.Alu32R.src->Xrmi.Reg.reg == vreg) { |
| 1772 | vassert(i->Xin.Alu32R.dst != vreg); |
| 1773 | return X86Instr_Alu32R( |
| 1774 | i->Xin.Alu32R.op, |
| 1775 | X86RMI_Mem( X86AMode_IR( spill_off, hregX86_EBP())), |
| 1776 | i->Xin.Alu32R.dst |
| 1777 | ); |
| 1778 | } |
| 1779 | |
| 1780 | /* Deal with form: src=RMI_Imm, dst=Reg where dst == vreg |
| 1781 | Convert to: src=RI_Imm, dst=Mem |
| 1782 | */ |
| 1783 | if (i->tag == Xin_Alu32R |
| 1784 | && (i->Xin.Alu32R.op == Xalu_CMP) |
| 1785 | && i->Xin.Alu32R.src->tag == Xrmi_Imm |
| 1786 | && i->Xin.Alu32R.dst == vreg) { |
| 1787 | return X86Instr_Alu32M( |
| 1788 | i->Xin.Alu32R.op, |
| 1789 | X86RI_Imm( i->Xin.Alu32R.src->Xrmi.Imm.imm32 ), |
| 1790 | X86AMode_IR( spill_off, hregX86_EBP()) |
| 1791 | ); |
| 1792 | } |
| 1793 | |
| 1794 | /* Deal with form: Push(RMI_Reg) |
| 1795 | Convert to: Push(RMI_Mem) |
| 1796 | */ |
| 1797 | if (i->tag == Xin_Push |
| 1798 | && i->Xin.Push.src->tag == Xrmi_Reg |
| 1799 | && i->Xin.Push.src->Xrmi.Reg.reg == vreg) { |
| 1800 | return X86Instr_Push( |
| 1801 | X86RMI_Mem( X86AMode_IR( spill_off, hregX86_EBP())) |
| 1802 | ); |
| 1803 | } |
| 1804 | |
| 1805 | /* Deal with form: CMov32(src=RM_Reg, dst) where vreg == src |
| 1806 | Convert to CMov32(RM_Mem, dst) */ |
| 1807 | if (i->tag == Xin_CMov32 |
| 1808 | && i->Xin.CMov32.src->tag == Xrm_Reg |
| 1809 | && i->Xin.CMov32.src->Xrm.Reg.reg == vreg) { |
| 1810 | vassert(i->Xin.CMov32.dst != vreg); |
| 1811 | return X86Instr_CMov32( |
| 1812 | i->Xin.CMov32.cond, |
| 1813 | X86RM_Mem( X86AMode_IR( spill_off, hregX86_EBP() )), |
| 1814 | i->Xin.CMov32.dst |
| 1815 | ); |
| 1816 | } |
| 1817 | |
| 1818 | /* Deal with form: Test32(imm,RM_Reg vreg) -> Test32(imm,amode) */ |
| 1819 | if (i->tag == Xin_Test32 |
| 1820 | && i->Xin.Test32.dst->tag == Xrm_Reg |
| 1821 | && i->Xin.Test32.dst->Xrm.Reg.reg == vreg) { |
| 1822 | return X86Instr_Test32( |
| 1823 | i->Xin.Test32.imm32, |
| 1824 | X86RM_Mem( X86AMode_IR( spill_off, hregX86_EBP() ) ) |
| 1825 | ); |
| 1826 | } |
| 1827 | |
| 1828 | return NULL; |
| 1829 | } |
| 1830 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 1831 | |
| 1832 | /* --------- The x86 assembler (bleh.) --------- */ |
| 1833 | |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1834 | static UChar iregNo ( HReg r ) |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1835 | { |
| 1836 | UInt n; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1837 | vassert(hregClass(r) == HRcInt32); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1838 | vassert(!hregIsVirtual(r)); |
| 1839 | n = hregNumber(r); |
| 1840 | vassert(n <= 7); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1841 | return toUChar(n); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1842 | } |
| 1843 | |
sewardj | 140656d | 2004-08-22 02:37:25 +0000 | [diff] [blame] | 1844 | static UInt fregNo ( HReg r ) |
| 1845 | { |
| 1846 | UInt n; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1847 | vassert(hregClass(r) == HRcFlt64); |
sewardj | 140656d | 2004-08-22 02:37:25 +0000 | [diff] [blame] | 1848 | vassert(!hregIsVirtual(r)); |
| 1849 | n = hregNumber(r); |
sewardj | eafde5a | 2004-10-09 01:36:57 +0000 | [diff] [blame] | 1850 | vassert(n <= 5); |
sewardj | 140656d | 2004-08-22 02:37:25 +0000 | [diff] [blame] | 1851 | return n; |
| 1852 | } |
| 1853 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1854 | static UInt vregNo ( HReg r ) |
| 1855 | { |
| 1856 | UInt n; |
| 1857 | vassert(hregClass(r) == HRcVec128); |
| 1858 | vassert(!hregIsVirtual(r)); |
| 1859 | n = hregNumber(r); |
| 1860 | vassert(n <= 7); |
| 1861 | return n; |
| 1862 | } |
| 1863 | |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1864 | static UChar mkModRegRM ( UChar mod, UChar reg, UChar regmem ) |
| 1865 | { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1866 | return toUChar( ((mod & 3) << 6) |
| 1867 | | ((reg & 7) << 3) |
| 1868 | | (regmem & 7) ); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1869 | } |
| 1870 | |
| 1871 | static UChar mkSIB ( Int shift, Int regindex, Int regbase ) |
| 1872 | { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1873 | return toUChar( ((shift & 3) << 6) |
| 1874 | | ((regindex & 7) << 3) |
| 1875 | | (regbase & 7) ); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1876 | } |
| 1877 | |
| 1878 | static UChar* emit32 ( UChar* p, UInt w32 ) |
| 1879 | { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1880 | *p++ = toUChar( w32 & 0x000000FF); |
| 1881 | *p++ = toUChar((w32 >> 8) & 0x000000FF); |
| 1882 | *p++ = toUChar((w32 >> 16) & 0x000000FF); |
| 1883 | *p++ = toUChar((w32 >> 24) & 0x000000FF); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1884 | return p; |
| 1885 | } |
| 1886 | |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1887 | /* Does a sign-extend of the lowest 8 bits give |
| 1888 | the original number? */ |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1889 | static Bool fits8bits ( UInt w32 ) |
| 1890 | { |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1891 | Int i32 = (Int)w32; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1892 | return toBool(i32 == ((i32 << 24) >> 24)); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1893 | } |
| 1894 | |
| 1895 | |
| 1896 | /* Forming mod-reg-rm bytes and scale-index-base bytes. |
| 1897 | |
| 1898 | greg, 0(ereg) | ereg != ESP && ereg != EBP |
| 1899 | = 00 greg ereg |
| 1900 | |
| 1901 | greg, d8(ereg) | ereg != ESP |
| 1902 | = 01 greg ereg, d8 |
| 1903 | |
| 1904 | greg, d32(ereg) | ereg != ESP |
| 1905 | = 10 greg ereg, d32 |
| 1906 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 1907 | greg, d8(%esp) = 01 greg 100, 0x24, d8 |
| 1908 | |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1909 | ----------------------------------------------- |
| 1910 | |
| 1911 | greg, d8(base,index,scale) |
| 1912 | | index != ESP |
| 1913 | = 01 greg 100, scale index base, d8 |
| 1914 | |
| 1915 | greg, d32(base,index,scale) |
| 1916 | | index != ESP |
| 1917 | = 10 greg 100, scale index base, d32 |
| 1918 | */ |
| 1919 | static UChar* doAMode_M ( UChar* p, HReg greg, X86AMode* am ) |
| 1920 | { |
| 1921 | if (am->tag == Xam_IR) { |
| 1922 | if (am->Xam.IR.imm == 0 |
| 1923 | && am->Xam.IR.reg != hregX86_ESP() |
| 1924 | && am->Xam.IR.reg != hregX86_EBP() ) { |
| 1925 | *p++ = mkModRegRM(0, iregNo(greg), iregNo(am->Xam.IR.reg)); |
| 1926 | return p; |
| 1927 | } |
| 1928 | if (fits8bits(am->Xam.IR.imm) |
| 1929 | && am->Xam.IR.reg != hregX86_ESP()) { |
| 1930 | *p++ = mkModRegRM(1, iregNo(greg), iregNo(am->Xam.IR.reg)); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1931 | *p++ = toUChar(am->Xam.IR.imm & 0xFF); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1932 | return p; |
| 1933 | } |
| 1934 | if (am->Xam.IR.reg != hregX86_ESP()) { |
| 1935 | *p++ = mkModRegRM(2, iregNo(greg), iregNo(am->Xam.IR.reg)); |
| 1936 | p = emit32(p, am->Xam.IR.imm); |
| 1937 | return p; |
| 1938 | } |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 1939 | if (am->Xam.IR.reg == hregX86_ESP() |
| 1940 | && fits8bits(am->Xam.IR.imm)) { |
| 1941 | *p++ = mkModRegRM(1, iregNo(greg), 4); |
| 1942 | *p++ = 0x24; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1943 | *p++ = toUChar(am->Xam.IR.imm & 0xFF); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 1944 | return p; |
| 1945 | } |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1946 | ppX86AMode(am); |
| 1947 | vpanic("doAMode_M: can't emit amode IR"); |
| 1948 | /*NOTREACHED*/ |
| 1949 | } |
| 1950 | if (am->tag == Xam_IRRS) { |
| 1951 | if (fits8bits(am->Xam.IRRS.imm) |
| 1952 | && am->Xam.IRRS.index != hregX86_ESP()) { |
| 1953 | *p++ = mkModRegRM(1, iregNo(greg), 4); |
| 1954 | *p++ = mkSIB(am->Xam.IRRS.shift, am->Xam.IRRS.index, |
| 1955 | am->Xam.IRRS.base); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1956 | *p++ = toUChar(am->Xam.IRRS.imm & 0xFF); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1957 | return p; |
| 1958 | } |
| 1959 | if (am->Xam.IRRS.index != hregX86_ESP()) { |
| 1960 | *p++ = mkModRegRM(2, iregNo(greg), 4); |
| 1961 | *p++ = mkSIB(am->Xam.IRRS.shift, am->Xam.IRRS.index, |
| 1962 | am->Xam.IRRS.base); |
| 1963 | p = emit32(p, am->Xam.IRRS.imm); |
| 1964 | return p; |
| 1965 | } |
| 1966 | ppX86AMode(am); |
| 1967 | vpanic("doAMode_M: can't emit amode IRRS"); |
| 1968 | /*NOTREACHED*/ |
| 1969 | } |
| 1970 | vpanic("doAMode_M: unknown amode"); |
| 1971 | /*NOTREACHED*/ |
| 1972 | } |
| 1973 | |
| 1974 | |
| 1975 | /* Emit a mod-reg-rm byte when the rm bit denotes a reg. */ |
| 1976 | static UChar* doAMode_R ( UChar* p, HReg greg, HReg ereg ) |
| 1977 | { |
| 1978 | *p++ = mkModRegRM(3, iregNo(greg), iregNo(ereg)); |
| 1979 | return p; |
| 1980 | } |
| 1981 | |
| 1982 | |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1983 | /* Emit ffree %st(7) */ |
| 1984 | static UChar* do_ffree_st7 ( UChar* p ) |
| 1985 | { |
| 1986 | *p++ = 0xDD; |
| 1987 | *p++ = 0xC7; |
| 1988 | return p; |
| 1989 | } |
| 1990 | |
sewardj | eafde5a | 2004-10-09 01:36:57 +0000 | [diff] [blame] | 1991 | /* Emit fstp %st(i), 1 <= i <= 7 */ |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1992 | static UChar* do_fstp_st ( UChar* p, Int i ) |
| 1993 | { |
sewardj | eafde5a | 2004-10-09 01:36:57 +0000 | [diff] [blame] | 1994 | vassert(1 <= i && i <= 7); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1995 | *p++ = 0xDD; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1996 | *p++ = toUChar(0xD8+i); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1997 | return p; |
| 1998 | } |
| 1999 | |
sewardj | b3944c2 | 2004-10-15 22:22:09 +0000 | [diff] [blame] | 2000 | /* Emit fld %st(i), 0 <= i <= 6 */ |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2001 | static UChar* do_fld_st ( UChar* p, Int i ) |
| 2002 | { |
sewardj | b3944c2 | 2004-10-15 22:22:09 +0000 | [diff] [blame] | 2003 | vassert(0 <= i && i <= 6); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2004 | *p++ = 0xD9; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2005 | *p++ = toUChar(0xC0+i); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2006 | return p; |
| 2007 | } |
| 2008 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2009 | /* Emit f<op> %st(0) */ |
| 2010 | static UChar* do_fop1_st ( UChar* p, X86FpOp op ) |
| 2011 | { |
| 2012 | switch (op) { |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 2013 | case Xfp_NEG: *p++ = 0xD9; *p++ = 0xE0; break; |
| 2014 | case Xfp_ABS: *p++ = 0xD9; *p++ = 0xE1; break; |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 2015 | case Xfp_SQRT: *p++ = 0xD9; *p++ = 0xFA; break; |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 2016 | case Xfp_ROUND: *p++ = 0xD9; *p++ = 0xFC; break; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2017 | case Xfp_SIN: *p++ = 0xD9; *p++ = 0xFE; break; |
| 2018 | case Xfp_COS: *p++ = 0xD9; *p++ = 0xFF; break; |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2019 | case Xfp_2XM1: *p++ = 0xD9; *p++ = 0xF0; break; |
sewardj | bec1084 | 2004-10-12 13:44:45 +0000 | [diff] [blame] | 2020 | case Xfp_MOV: break; |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 2021 | case Xfp_TAN: p = do_ffree_st7(p); /* since fptan pushes 1.0 */ |
| 2022 | *p++ = 0xD9; *p++ = 0xF2; /* fptan */ |
| 2023 | *p++ = 0xD9; *p++ = 0xF7; /* fincstp */ |
| 2024 | break; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2025 | default: vpanic("do_fop1_st: unknown op"); |
| 2026 | } |
| 2027 | return p; |
| 2028 | } |
| 2029 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2030 | /* Emit f<op> %st(i), 1 <= i <= 5 */ |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2031 | static UChar* do_fop2_st ( UChar* p, X86FpOp op, Int i ) |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2032 | { |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 2033 | # define fake(_n) mkHReg((_n), HRcInt32, False) |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2034 | Int subopc; |
| 2035 | switch (op) { |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 2036 | case Xfp_ADD: subopc = 0; break; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 2037 | case Xfp_SUB: subopc = 4; break; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2038 | case Xfp_MUL: subopc = 1; break; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 2039 | case Xfp_DIV: subopc = 6; break; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2040 | default: vpanic("do_fop2_st: unknown op"); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2041 | } |
| 2042 | *p++ = 0xD8; |
| 2043 | p = doAMode_R(p, fake(subopc), fake(i)); |
| 2044 | return p; |
| 2045 | # undef fake |
| 2046 | } |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2047 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2048 | /* Push a 32-bit word on the stack. The word depends on tags[3:0]; |
| 2049 | each byte is either 0x00 or 0xFF depending on the corresponding bit in tags[]. |
| 2050 | */ |
| 2051 | static UChar* push_word_from_tags ( UChar* p, UShort tags ) |
| 2052 | { |
| 2053 | UInt w; |
| 2054 | vassert(0 == (tags & ~0xF)); |
| 2055 | if (tags == 0) { |
| 2056 | /* pushl $0x00000000 */ |
| 2057 | *p++ = 0x6A; |
| 2058 | *p++ = 0x00; |
| 2059 | } |
| 2060 | else |
| 2061 | /* pushl $0xFFFFFFFF */ |
| 2062 | if (tags == 0xF) { |
| 2063 | *p++ = 0x6A; |
| 2064 | *p++ = 0xFF; |
| 2065 | } else { |
| 2066 | vassert(0); /* awaiting test case */ |
| 2067 | w = 0; |
| 2068 | if (tags & 1) w |= 0x000000FF; |
| 2069 | if (tags & 2) w |= 0x0000FF00; |
| 2070 | if (tags & 4) w |= 0x00FF0000; |
| 2071 | if (tags & 8) w |= 0xFF000000; |
| 2072 | *p++ = 0x68; |
| 2073 | p = emit32(p, w); |
| 2074 | } |
| 2075 | return p; |
| 2076 | } |
| 2077 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 2078 | /* Emit an instruction into buf and return the number of bytes used. |
| 2079 | Note that buf is not the insn's final place, and therefore it is |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2080 | imperative to emit position-independent code. If the emitted |
| 2081 | instruction was a profiler inc, set *is_profInc to True, else |
| 2082 | leave it unchanged. */ |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 2083 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2084 | Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, |
| 2085 | UChar* buf, Int nbuf, X86Instr* i, |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 2086 | Bool mode64, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2087 | void* disp_cp_chain_me_to_slowEP, |
| 2088 | void* disp_cp_chain_me_to_fastEP, |
| 2089 | void* disp_cp_xindir, |
| 2090 | void* disp_cp_xassisted ) |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 2091 | { |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2092 | UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2093 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2094 | UInt xtra; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2095 | UChar* p = &buf[0]; |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2096 | UChar* ptmp; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2097 | vassert(nbuf >= 32); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 2098 | vassert(mode64 == False); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2099 | |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2100 | /* Wrap an integer as a int register, for use assembling |
| 2101 | GrpN insns, in which the greg field is used as a sub-opcode |
| 2102 | and does not really contain a register. */ |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 2103 | # define fake(_n) mkHReg((_n), HRcInt32, False) |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2104 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 2105 | /* vex_printf("asm ");ppX86Instr(i, mode64); vex_printf("\n"); */ |
sewardj | bec1084 | 2004-10-12 13:44:45 +0000 | [diff] [blame] | 2106 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 2107 | switch (i->tag) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2108 | |
| 2109 | case Xin_Alu32R: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2110 | /* Deal specially with MOV */ |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2111 | if (i->Xin.Alu32R.op == Xalu_MOV) { |
| 2112 | switch (i->Xin.Alu32R.src->tag) { |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2113 | case Xrmi_Imm: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2114 | *p++ = toUChar(0xB8 + iregNo(i->Xin.Alu32R.dst)); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2115 | p = emit32(p, i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
| 2116 | goto done; |
| 2117 | case Xrmi_Reg: |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2118 | *p++ = 0x89; |
| 2119 | p = doAMode_R(p, i->Xin.Alu32R.src->Xrmi.Reg.reg, |
| 2120 | i->Xin.Alu32R.dst); |
| 2121 | goto done; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2122 | case Xrmi_Mem: |
| 2123 | *p++ = 0x8B; |
| 2124 | p = doAMode_M(p, i->Xin.Alu32R.dst, |
| 2125 | i->Xin.Alu32R.src->Xrmi.Mem.am); |
| 2126 | goto done; |
| 2127 | default: |
| 2128 | goto bad; |
| 2129 | } |
| 2130 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2131 | /* MUL */ |
| 2132 | if (i->Xin.Alu32R.op == Xalu_MUL) { |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2133 | switch (i->Xin.Alu32R.src->tag) { |
| 2134 | case Xrmi_Reg: |
| 2135 | *p++ = 0x0F; |
| 2136 | *p++ = 0xAF; |
| 2137 | p = doAMode_R(p, i->Xin.Alu32R.dst, |
| 2138 | i->Xin.Alu32R.src->Xrmi.Reg.reg); |
| 2139 | goto done; |
sewardj | 140656d | 2004-08-22 02:37:25 +0000 | [diff] [blame] | 2140 | case Xrmi_Mem: |
| 2141 | *p++ = 0x0F; |
| 2142 | *p++ = 0xAF; |
| 2143 | p = doAMode_M(p, i->Xin.Alu32R.dst, |
| 2144 | i->Xin.Alu32R.src->Xrmi.Mem.am); |
| 2145 | goto done; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2146 | case Xrmi_Imm: |
| 2147 | if (fits8bits(i->Xin.Alu32R.src->Xrmi.Imm.imm32)) { |
| 2148 | *p++ = 0x6B; |
| 2149 | p = doAMode_R(p, i->Xin.Alu32R.dst, i->Xin.Alu32R.dst); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2150 | *p++ = toUChar(0xFF & i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2151 | } else { |
sewardj | 278c44c | 2004-08-20 00:28:13 +0000 | [diff] [blame] | 2152 | *p++ = 0x69; |
| 2153 | p = doAMode_R(p, i->Xin.Alu32R.dst, i->Xin.Alu32R.dst); |
| 2154 | p = emit32(p, i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2155 | } |
sewardj | 278c44c | 2004-08-20 00:28:13 +0000 | [diff] [blame] | 2156 | goto done; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2157 | default: |
| 2158 | goto bad; |
| 2159 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2160 | } |
| 2161 | /* ADD/SUB/ADC/SBB/AND/OR/XOR/CMP */ |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2162 | opc = opc_rr = subopc_imm = opc_imma = 0; |
| 2163 | switch (i->Xin.Alu32R.op) { |
sewardj | d3f9de7 | 2005-01-15 20:43:10 +0000 | [diff] [blame] | 2164 | case Xalu_ADC: opc = 0x13; opc_rr = 0x11; |
| 2165 | subopc_imm = 2; opc_imma = 0x15; break; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2166 | case Xalu_ADD: opc = 0x03; opc_rr = 0x01; |
| 2167 | subopc_imm = 0; opc_imma = 0x05; break; |
| 2168 | case Xalu_SUB: opc = 0x2B; opc_rr = 0x29; |
| 2169 | subopc_imm = 5; opc_imma = 0x2D; break; |
sewardj | 70f676d | 2004-12-10 14:59:57 +0000 | [diff] [blame] | 2170 | case Xalu_SBB: opc = 0x1B; opc_rr = 0x19; |
| 2171 | subopc_imm = 3; opc_imma = 0x1D; break; |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 2172 | case Xalu_AND: opc = 0x23; opc_rr = 0x21; |
| 2173 | subopc_imm = 4; opc_imma = 0x25; break; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2174 | case Xalu_XOR: opc = 0x33; opc_rr = 0x31; |
| 2175 | subopc_imm = 6; opc_imma = 0x35; break; |
| 2176 | case Xalu_OR: opc = 0x0B; opc_rr = 0x09; |
| 2177 | subopc_imm = 1; opc_imma = 0x0D; break; |
| 2178 | case Xalu_CMP: opc = 0x3B; opc_rr = 0x39; |
| 2179 | subopc_imm = 7; opc_imma = 0x3D; break; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2180 | default: goto bad; |
| 2181 | } |
| 2182 | switch (i->Xin.Alu32R.src->tag) { |
| 2183 | case Xrmi_Imm: |
| 2184 | if (i->Xin.Alu32R.dst == hregX86_EAX() |
| 2185 | && !fits8bits(i->Xin.Alu32R.src->Xrmi.Imm.imm32)) { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2186 | *p++ = toUChar(opc_imma); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2187 | p = emit32(p, i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
| 2188 | } else |
sewardj | d3f9de7 | 2005-01-15 20:43:10 +0000 | [diff] [blame] | 2189 | if (fits8bits(i->Xin.Alu32R.src->Xrmi.Imm.imm32)) { |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2190 | *p++ = 0x83; |
| 2191 | p = doAMode_R(p, fake(subopc_imm), i->Xin.Alu32R.dst); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2192 | *p++ = toUChar(0xFF & i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2193 | } else { |
| 2194 | *p++ = 0x81; |
| 2195 | p = doAMode_R(p, fake(subopc_imm), i->Xin.Alu32R.dst); |
| 2196 | p = emit32(p, i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
| 2197 | } |
| 2198 | goto done; |
| 2199 | case Xrmi_Reg: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2200 | *p++ = toUChar(opc_rr); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2201 | p = doAMode_R(p, i->Xin.Alu32R.src->Xrmi.Reg.reg, |
| 2202 | i->Xin.Alu32R.dst); |
| 2203 | goto done; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2204 | case Xrmi_Mem: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2205 | *p++ = toUChar(opc); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2206 | p = doAMode_M(p, i->Xin.Alu32R.dst, |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2207 | i->Xin.Alu32R.src->Xrmi.Mem.am); |
| 2208 | goto done; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2209 | default: |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2210 | goto bad; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2211 | } |
| 2212 | break; |
| 2213 | |
| 2214 | case Xin_Alu32M: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2215 | /* Deal specially with MOV */ |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2216 | if (i->Xin.Alu32M.op == Xalu_MOV) { |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2217 | switch (i->Xin.Alu32M.src->tag) { |
| 2218 | case Xri_Reg: |
| 2219 | *p++ = 0x89; |
| 2220 | p = doAMode_M(p, i->Xin.Alu32M.src->Xri.Reg.reg, |
| 2221 | i->Xin.Alu32M.dst); |
| 2222 | goto done; |
| 2223 | case Xri_Imm: |
| 2224 | *p++ = 0xC7; |
| 2225 | p = doAMode_M(p, fake(0), i->Xin.Alu32M.dst); |
| 2226 | p = emit32(p, i->Xin.Alu32M.src->Xri.Imm.imm32); |
| 2227 | goto done; |
| 2228 | default: |
| 2229 | goto bad; |
| 2230 | } |
| 2231 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2232 | /* ADD/SUB/ADC/SBB/AND/OR/XOR/CMP. MUL is not |
| 2233 | allowed here. */ |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2234 | opc = subopc_imm = opc_imma = 0; |
| 2235 | switch (i->Xin.Alu32M.op) { |
| 2236 | case Xalu_ADD: opc = 0x01; subopc_imm = 0; break; |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 2237 | case Xalu_SUB: opc = 0x29; subopc_imm = 5; break; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 2238 | case Xalu_CMP: opc = 0x39; subopc_imm = 7; break; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2239 | default: goto bad; |
| 2240 | } |
| 2241 | switch (i->Xin.Alu32M.src->tag) { |
| 2242 | case Xri_Reg: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2243 | *p++ = toUChar(opc); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2244 | p = doAMode_M(p, i->Xin.Alu32M.src->Xri.Reg.reg, |
| 2245 | i->Xin.Alu32M.dst); |
| 2246 | goto done; |
| 2247 | case Xri_Imm: |
| 2248 | if (fits8bits(i->Xin.Alu32M.src->Xri.Imm.imm32)) { |
| 2249 | *p++ = 0x83; |
| 2250 | p = doAMode_M(p, fake(subopc_imm), i->Xin.Alu32M.dst); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2251 | *p++ = toUChar(0xFF & i->Xin.Alu32M.src->Xri.Imm.imm32); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2252 | goto done; |
| 2253 | } else { |
| 2254 | *p++ = 0x81; |
| 2255 | p = doAMode_M(p, fake(subopc_imm), i->Xin.Alu32M.dst); |
| 2256 | p = emit32(p, i->Xin.Alu32M.src->Xri.Imm.imm32); |
| 2257 | goto done; |
| 2258 | } |
| 2259 | default: |
| 2260 | goto bad; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2261 | } |
| 2262 | break; |
| 2263 | |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2264 | case Xin_Sh32: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2265 | opc_cl = opc_imm = subopc = 0; |
| 2266 | switch (i->Xin.Sh32.op) { |
| 2267 | case Xsh_SHR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 5; break; |
sewardj | 07134a4 | 2004-07-26 02:04:54 +0000 | [diff] [blame] | 2268 | case Xsh_SAR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 7; break; |
| 2269 | case Xsh_SHL: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 4; break; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2270 | default: goto bad; |
| 2271 | } |
| 2272 | if (i->Xin.Sh32.src == 0) { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2273 | *p++ = toUChar(opc_cl); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2274 | p = doAMode_R(p, fake(subopc), i->Xin.Sh32.dst); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2275 | } else { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2276 | *p++ = toUChar(opc_imm); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2277 | p = doAMode_R(p, fake(subopc), i->Xin.Sh32.dst); |
| 2278 | *p++ = (UChar)(i->Xin.Sh32.src); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2279 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2280 | goto done; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2281 | |
| 2282 | case Xin_Test32: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 2283 | if (i->Xin.Test32.dst->tag == Xrm_Reg) { |
| 2284 | /* testl $imm32, %reg */ |
| 2285 | *p++ = 0xF7; |
| 2286 | p = doAMode_R(p, fake(0), i->Xin.Test32.dst->Xrm.Reg.reg); |
| 2287 | p = emit32(p, i->Xin.Test32.imm32); |
| 2288 | goto done; |
| 2289 | } else { |
| 2290 | /* testl $imm32, amode */ |
| 2291 | *p++ = 0xF7; |
| 2292 | p = doAMode_M(p, fake(0), i->Xin.Test32.dst->Xrm.Mem.am); |
| 2293 | p = emit32(p, i->Xin.Test32.imm32); |
| 2294 | goto done; |
| 2295 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2296 | |
| 2297 | case Xin_Unary32: |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 2298 | if (i->Xin.Unary32.op == Xun_NOT) { |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2299 | *p++ = 0xF7; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2300 | p = doAMode_R(p, fake(2), i->Xin.Unary32.dst); |
| 2301 | goto done; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2302 | } |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 2303 | if (i->Xin.Unary32.op == Xun_NEG) { |
| 2304 | *p++ = 0xF7; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2305 | p = doAMode_R(p, fake(3), i->Xin.Unary32.dst); |
| 2306 | goto done; |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 2307 | } |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2308 | break; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2309 | |
sewardj | 79e04f8 | 2007-03-31 14:30:12 +0000 | [diff] [blame] | 2310 | case Xin_Lea32: |
| 2311 | *p++ = 0x8D; |
| 2312 | p = doAMode_M(p, i->Xin.Lea32.dst, i->Xin.Lea32.am); |
| 2313 | goto done; |
| 2314 | |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 2315 | case Xin_MulL: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2316 | subopc = i->Xin.MulL.syned ? 5 : 4; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2317 | *p++ = 0xF7; |
| 2318 | switch (i->Xin.MulL.src->tag) { |
| 2319 | case Xrm_Mem: |
| 2320 | p = doAMode_M(p, fake(subopc), |
| 2321 | i->Xin.MulL.src->Xrm.Mem.am); |
| 2322 | goto done; |
| 2323 | case Xrm_Reg: |
| 2324 | p = doAMode_R(p, fake(subopc), |
| 2325 | i->Xin.MulL.src->Xrm.Reg.reg); |
| 2326 | goto done; |
| 2327 | default: |
| 2328 | goto bad; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2329 | } |
| 2330 | break; |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 2331 | |
| 2332 | case Xin_Div: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2333 | subopc = i->Xin.Div.syned ? 7 : 6; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2334 | *p++ = 0xF7; |
| 2335 | switch (i->Xin.Div.src->tag) { |
| 2336 | case Xrm_Mem: |
| 2337 | p = doAMode_M(p, fake(subopc), |
| 2338 | i->Xin.Div.src->Xrm.Mem.am); |
| 2339 | goto done; |
| 2340 | case Xrm_Reg: |
| 2341 | p = doAMode_R(p, fake(subopc), |
| 2342 | i->Xin.Div.src->Xrm.Reg.reg); |
| 2343 | goto done; |
| 2344 | default: |
| 2345 | goto bad; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2346 | } |
| 2347 | break; |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 2348 | |
| 2349 | case Xin_Sh3232: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2350 | vassert(i->Xin.Sh3232.op == Xsh_SHL || i->Xin.Sh3232.op == Xsh_SHR); |
| 2351 | if (i->Xin.Sh3232.amt == 0) { |
| 2352 | /* shldl/shrdl by %cl */ |
| 2353 | *p++ = 0x0F; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 2354 | if (i->Xin.Sh3232.op == Xsh_SHL) { |
| 2355 | *p++ = 0xA5; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 2356 | } else { |
| 2357 | *p++ = 0xAD; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 2358 | } |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 2359 | p = doAMode_R(p, i->Xin.Sh3232.src, i->Xin.Sh3232.dst); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2360 | goto done; |
| 2361 | } |
| 2362 | break; |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 2363 | |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2364 | case Xin_Push: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2365 | switch (i->Xin.Push.src->tag) { |
| 2366 | case Xrmi_Mem: |
| 2367 | *p++ = 0xFF; |
| 2368 | p = doAMode_M(p, fake(6), i->Xin.Push.src->Xrmi.Mem.am); |
| 2369 | goto done; |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 2370 | case Xrmi_Imm: |
| 2371 | *p++ = 0x68; |
| 2372 | p = emit32(p, i->Xin.Push.src->Xrmi.Imm.imm32); |
| 2373 | goto done; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2374 | case Xrmi_Reg: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2375 | *p++ = toUChar(0x50 + iregNo(i->Xin.Push.src->Xrmi.Reg.reg)); |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2376 | goto done; |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 2377 | default: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2378 | goto bad; |
| 2379 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2380 | |
| 2381 | case Xin_Call: |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame^] | 2382 | if (i->Xin.Call.cond != Xcc_ALWAYS && i->Xin.Call.rloc != RetLocNone) { |
| 2383 | /* The call might not happen (it isn't unconditional) and it |
| 2384 | returns a result. In this case we will need to generate a |
| 2385 | control flow diamond to put 0x555..555 in the return |
| 2386 | register(s) in the case where the call doesn't happen. If |
| 2387 | this ever becomes necessary, maybe copy code from the ARM |
| 2388 | equivalent. Until that day, just give up. */ |
| 2389 | goto bad; |
| 2390 | } |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2391 | /* See detailed comment for Xin_Call in getRegUsage_X86Instr above |
| 2392 | for explanation of this. */ |
| 2393 | switch (i->Xin.Call.regparms) { |
| 2394 | case 0: irno = iregNo(hregX86_EAX()); break; |
sewardj | 45c50eb | 2004-11-04 18:25:33 +0000 | [diff] [blame] | 2395 | case 1: irno = iregNo(hregX86_EDX()); break; |
| 2396 | case 2: irno = iregNo(hregX86_ECX()); break; |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2397 | case 3: irno = iregNo(hregX86_EDI()); break; |
| 2398 | default: vpanic(" emit_X86Instr:call:regparms"); |
| 2399 | } |
| 2400 | /* jump over the following two insns if the condition does not |
| 2401 | hold */ |
| 2402 | if (i->Xin.Call.cond != Xcc_ALWAYS) { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2403 | *p++ = toUChar(0x70 + (0xF & (i->Xin.Call.cond ^ 1))); |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2404 | *p++ = 0x07; /* 7 bytes in the next two insns */ |
| 2405 | } |
| 2406 | /* movl $target, %tmp */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2407 | *p++ = toUChar(0xB8 + irno); |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2408 | p = emit32(p, i->Xin.Call.target); |
| 2409 | /* call *%tmp */ |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2410 | *p++ = 0xFF; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2411 | *p++ = toUChar(0xD0 + irno); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2412 | goto done; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2413 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2414 | case Xin_XDirect: { |
| 2415 | /* NB: what goes on here has to be very closely coordinated with the |
| 2416 | chainXDirect_X86 and unchainXDirect_X86 below. */ |
| 2417 | /* We're generating chain-me requests here, so we need to be |
| 2418 | sure this is actually allowed -- no-redir translations can't |
| 2419 | use chain-me's. Hence: */ |
| 2420 | vassert(disp_cp_chain_me_to_slowEP != NULL); |
| 2421 | vassert(disp_cp_chain_me_to_fastEP != NULL); |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 2422 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2423 | /* Use ptmp for backpatching conditional jumps. */ |
| 2424 | ptmp = NULL; |
| 2425 | |
| 2426 | /* First off, if this is conditional, create a conditional |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2427 | jump over the rest of it. */ |
| 2428 | if (i->Xin.XDirect.cond != Xcc_ALWAYS) { |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2429 | /* jmp fwds if !condition */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2430 | *p++ = toUChar(0x70 + (0xF & (i->Xin.XDirect.cond ^ 1))); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2431 | ptmp = p; /* fill in this bit later */ |
| 2432 | *p++ = 0; /* # of bytes to jump over; don't know how many yet. */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2433 | } |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2434 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2435 | /* Update the guest EIP. */ |
| 2436 | /* movl $dstGA, amEIP */ |
| 2437 | *p++ = 0xC7; |
| 2438 | p = doAMode_M(p, fake(0), i->Xin.XDirect.amEIP); |
| 2439 | p = emit32(p, i->Xin.XDirect.dstGA); |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 2440 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2441 | /* --- FIRST PATCHABLE BYTE follows --- */ |
| 2442 | /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're calling |
| 2443 | to) backs up the return address, so as to find the address of |
| 2444 | the first patchable byte. So: don't change the length of the |
| 2445 | two instructions below. */ |
| 2446 | /* movl $disp_cp_chain_me_to_{slow,fast}EP,%edx; */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 2447 | *p++ = 0xBA; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2448 | void* disp_cp_chain_me |
| 2449 | = i->Xin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP |
| 2450 | : disp_cp_chain_me_to_slowEP; |
| 2451 | p = emit32(p, (UInt)Ptr_to_ULong(disp_cp_chain_me)); |
| 2452 | /* call *%edx */ |
| 2453 | *p++ = 0xFF; |
| 2454 | *p++ = 0xD2; |
| 2455 | /* --- END of PATCHABLE BYTES --- */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 2456 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2457 | /* Fix up the conditional jump, if there was one. */ |
| 2458 | if (i->Xin.XDirect.cond != Xcc_ALWAYS) { |
| 2459 | Int delta = p - ptmp; |
| 2460 | vassert(delta > 0 && delta < 40); |
| 2461 | *ptmp = toUChar(delta-1); |
| 2462 | } |
| 2463 | goto done; |
| 2464 | } |
| 2465 | |
| 2466 | case Xin_XIndir: { |
| 2467 | /* We're generating transfers that could lead indirectly to a |
| 2468 | chain-me, so we need to be sure this is actually allowed -- |
| 2469 | no-redir translations are not allowed to reach normal |
| 2470 | translations without going through the scheduler. That means |
| 2471 | no XDirects or XIndirs out from no-redir translations. |
| 2472 | Hence: */ |
| 2473 | vassert(disp_cp_xindir != NULL); |
| 2474 | |
| 2475 | /* Use ptmp for backpatching conditional jumps. */ |
| 2476 | ptmp = NULL; |
| 2477 | |
| 2478 | /* First off, if this is conditional, create a conditional |
| 2479 | jump over the rest of it. */ |
| 2480 | if (i->Xin.XIndir.cond != Xcc_ALWAYS) { |
| 2481 | /* jmp fwds if !condition */ |
| 2482 | *p++ = toUChar(0x70 + (0xF & (i->Xin.XIndir.cond ^ 1))); |
| 2483 | ptmp = p; /* fill in this bit later */ |
| 2484 | *p++ = 0; /* # of bytes to jump over; don't know how many yet. */ |
| 2485 | } |
| 2486 | |
| 2487 | /* movl dstGA(a reg), amEIP -- copied from Alu32M MOV case */ |
| 2488 | *p++ = 0x89; |
| 2489 | p = doAMode_M(p, i->Xin.XIndir.dstGA, i->Xin.XIndir.amEIP); |
| 2490 | |
| 2491 | /* movl $disp_indir, %edx */ |
| 2492 | *p++ = 0xBA; |
| 2493 | p = emit32(p, (UInt)Ptr_to_ULong(disp_cp_xindir)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 2494 | /* jmp *%edx */ |
| 2495 | *p++ = 0xFF; |
| 2496 | *p++ = 0xE2; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2497 | |
| 2498 | /* Fix up the conditional jump, if there was one. */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2499 | if (i->Xin.XIndir.cond != Xcc_ALWAYS) { |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2500 | Int delta = p - ptmp; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2501 | vassert(delta > 0 && delta < 40); |
| 2502 | *ptmp = toUChar(delta-1); |
| 2503 | } |
| 2504 | goto done; |
| 2505 | } |
| 2506 | |
| 2507 | case Xin_XAssisted: { |
| 2508 | /* Use ptmp for backpatching conditional jumps. */ |
| 2509 | ptmp = NULL; |
| 2510 | |
| 2511 | /* First off, if this is conditional, create a conditional |
| 2512 | jump over the rest of it. */ |
| 2513 | if (i->Xin.XAssisted.cond != Xcc_ALWAYS) { |
| 2514 | /* jmp fwds if !condition */ |
| 2515 | *p++ = toUChar(0x70 + (0xF & (i->Xin.XAssisted.cond ^ 1))); |
| 2516 | ptmp = p; /* fill in this bit later */ |
| 2517 | *p++ = 0; /* # of bytes to jump over; don't know how many yet. */ |
| 2518 | } |
| 2519 | |
| 2520 | /* movl dstGA(a reg), amEIP -- copied from Alu32M MOV case */ |
| 2521 | *p++ = 0x89; |
| 2522 | p = doAMode_M(p, i->Xin.XIndir.dstGA, i->Xin.XIndir.amEIP); |
| 2523 | /* movl $magic_number, %ebp. */ |
| 2524 | UInt trcval = 0; |
| 2525 | switch (i->Xin.XAssisted.jk) { |
sewardj | 39aacda | 2012-04-21 15:34:25 +0000 | [diff] [blame] | 2526 | case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break; |
| 2527 | case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break; |
| 2528 | case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break; |
| 2529 | case Ijk_Sys_int129: trcval = VEX_TRC_JMP_SYS_INT129; break; |
| 2530 | case Ijk_Sys_int130: trcval = VEX_TRC_JMP_SYS_INT130; break; |
| 2531 | case Ijk_Sys_sysenter: trcval = VEX_TRC_JMP_SYS_SYSENTER; break; |
| 2532 | case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break; |
| 2533 | case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; |
| 2534 | case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; |
| 2535 | case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; |
| 2536 | case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break; |
| 2537 | case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; |
| 2538 | case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; |
| 2539 | case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; |
| 2540 | case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2541 | /* We don't expect to see the following being assisted. */ |
| 2542 | case Ijk_Ret: |
| 2543 | case Ijk_Call: |
| 2544 | /* fallthrough */ |
| 2545 | default: |
| 2546 | ppIRJumpKind(i->Xin.XAssisted.jk); |
| 2547 | vpanic("emit_X86Instr.Xin_XAssisted: unexpected jump kind"); |
| 2548 | } |
| 2549 | vassert(trcval != 0); |
| 2550 | *p++ = 0xBD; |
| 2551 | p = emit32(p, trcval); |
| 2552 | |
| 2553 | /* movl $disp_indir, %edx */ |
| 2554 | *p++ = 0xBA; |
| 2555 | p = emit32(p, (UInt)Ptr_to_ULong(disp_cp_xassisted)); |
| 2556 | /* jmp *%edx */ |
| 2557 | *p++ = 0xFF; |
| 2558 | *p++ = 0xE2; |
| 2559 | |
| 2560 | /* Fix up the conditional jump, if there was one. */ |
| 2561 | if (i->Xin.XAssisted.cond != Xcc_ALWAYS) { |
| 2562 | Int delta = p - ptmp; |
| 2563 | vassert(delta > 0 && delta < 40); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2564 | *ptmp = toUChar(delta-1); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2565 | } |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2566 | goto done; |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 2567 | } |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 2568 | |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2569 | case Xin_CMov32: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2570 | vassert(i->Xin.CMov32.cond != Xcc_ALWAYS); |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2571 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2572 | /* This generates cmov, which is illegal on P54/P55. */ |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2573 | /* |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2574 | *p++ = 0x0F; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2575 | *p++ = toUChar(0x40 + (0xF & i->Xin.CMov32.cond)); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2576 | if (i->Xin.CMov32.src->tag == Xrm_Reg) { |
| 2577 | p = doAMode_R(p, i->Xin.CMov32.dst, i->Xin.CMov32.src->Xrm.Reg.reg); |
| 2578 | goto done; |
| 2579 | } |
| 2580 | if (i->Xin.CMov32.src->tag == Xrm_Mem) { |
| 2581 | p = doAMode_M(p, i->Xin.CMov32.dst, i->Xin.CMov32.src->Xrm.Mem.am); |
| 2582 | goto done; |
| 2583 | } |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2584 | */ |
| 2585 | |
| 2586 | /* Alternative version which works on any x86 variant. */ |
| 2587 | /* jmp fwds if !condition */ |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 2588 | *p++ = toUChar(0x70 + (i->Xin.CMov32.cond ^ 1)); |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2589 | *p++ = 0; /* # of bytes in the next bit, which we don't know yet */ |
| 2590 | ptmp = p; |
| 2591 | |
| 2592 | switch (i->Xin.CMov32.src->tag) { |
| 2593 | case Xrm_Reg: |
| 2594 | /* Big sigh. This is movl E -> G ... */ |
| 2595 | *p++ = 0x89; |
| 2596 | p = doAMode_R(p, i->Xin.CMov32.src->Xrm.Reg.reg, |
| 2597 | i->Xin.CMov32.dst); |
| 2598 | |
| 2599 | break; |
| 2600 | case Xrm_Mem: |
| 2601 | /* ... whereas this is movl G -> E. That's why the args |
| 2602 | to doAMode_R appear to be the wrong way round in the |
| 2603 | Xrm_Reg case. */ |
| 2604 | *p++ = 0x8B; |
| 2605 | p = doAMode_M(p, i->Xin.CMov32.dst, |
| 2606 | i->Xin.CMov32.src->Xrm.Mem.am); |
| 2607 | break; |
| 2608 | default: |
| 2609 | goto bad; |
| 2610 | } |
| 2611 | /* Fill in the jump offset. */ |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 2612 | *(ptmp-1) = toUChar(p - ptmp); |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2613 | goto done; |
| 2614 | |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2615 | break; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2616 | |
| 2617 | case Xin_LoadEX: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2618 | if (i->Xin.LoadEX.szSmall == 1 && !i->Xin.LoadEX.syned) { |
| 2619 | /* movzbl */ |
| 2620 | *p++ = 0x0F; |
| 2621 | *p++ = 0xB6; |
| 2622 | p = doAMode_M(p, i->Xin.LoadEX.dst, i->Xin.LoadEX.src); |
| 2623 | goto done; |
| 2624 | } |
| 2625 | if (i->Xin.LoadEX.szSmall == 2 && !i->Xin.LoadEX.syned) { |
| 2626 | /* movzwl */ |
| 2627 | *p++ = 0x0F; |
| 2628 | *p++ = 0xB7; |
| 2629 | p = doAMode_M(p, i->Xin.LoadEX.dst, i->Xin.LoadEX.src); |
| 2630 | goto done; |
| 2631 | } |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 2632 | if (i->Xin.LoadEX.szSmall == 1 && i->Xin.LoadEX.syned) { |
| 2633 | /* movsbl */ |
| 2634 | *p++ = 0x0F; |
| 2635 | *p++ = 0xBE; |
| 2636 | p = doAMode_M(p, i->Xin.LoadEX.dst, i->Xin.LoadEX.src); |
| 2637 | goto done; |
| 2638 | } |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2639 | break; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2640 | |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2641 | case Xin_Set32: |
| 2642 | /* Make the destination register be 1 or 0, depending on whether |
| 2643 | the relevant condition holds. We have to dodge and weave |
| 2644 | when the destination is %esi or %edi as we cannot directly |
| 2645 | emit the native 'setb %reg' for those. Further complication: |
| 2646 | the top 24 bits of the destination should be forced to zero, |
| 2647 | but doing 'xor %r,%r' kills the flag(s) we are about to read. |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2648 | Sigh. So start off my moving $0 into the dest. */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2649 | |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2650 | /* Do we need to swap in %eax? */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2651 | if (iregNo(i->Xin.Set32.dst) >= 4) { |
| 2652 | /* xchg %eax, %dst */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2653 | *p++ = toUChar(0x90 + iregNo(i->Xin.Set32.dst)); |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2654 | /* movl $0, %eax */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2655 | *p++ =toUChar(0xB8 + iregNo(hregX86_EAX())); |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2656 | p = emit32(p, 0); |
| 2657 | /* setb lo8(%eax) */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2658 | *p++ = 0x0F; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2659 | *p++ = toUChar(0x90 + (0xF & i->Xin.Set32.cond)); |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2660 | p = doAMode_R(p, fake(0), hregX86_EAX()); |
| 2661 | /* xchg %eax, %dst */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2662 | *p++ = toUChar(0x90 + iregNo(i->Xin.Set32.dst)); |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2663 | } else { |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2664 | /* movl $0, %dst */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2665 | *p++ = toUChar(0xB8 + iregNo(i->Xin.Set32.dst)); |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2666 | p = emit32(p, 0); |
| 2667 | /* setb lo8(%dst) */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2668 | *p++ = 0x0F; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2669 | *p++ = toUChar(0x90 + (0xF & i->Xin.Set32.cond)); |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2670 | p = doAMode_R(p, fake(0), i->Xin.Set32.dst); |
| 2671 | } |
| 2672 | goto done; |
| 2673 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 2674 | case Xin_Bsfr32: |
| 2675 | *p++ = 0x0F; |
| 2676 | if (i->Xin.Bsfr32.isFwds) { |
| 2677 | *p++ = 0xBC; |
| 2678 | } else { |
| 2679 | *p++ = 0xBD; |
| 2680 | } |
| 2681 | p = doAMode_R(p, i->Xin.Bsfr32.dst, i->Xin.Bsfr32.src); |
| 2682 | goto done; |
| 2683 | |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 2684 | case Xin_MFence: |
| 2685 | /* see comment in hdefs.h re this insn */ |
sewardj | bb3f52d | 2005-01-07 14:14:50 +0000 | [diff] [blame] | 2686 | if (0) vex_printf("EMIT FENCE\n"); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 2687 | if (i->Xin.MFence.hwcaps & (VEX_HWCAPS_X86_SSE3 |
| 2688 | |VEX_HWCAPS_X86_SSE2)) { |
| 2689 | /* mfence */ |
| 2690 | *p++ = 0x0F; *p++ = 0xAE; *p++ = 0xF0; |
| 2691 | goto done; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 2692 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 2693 | if (i->Xin.MFence.hwcaps & VEX_HWCAPS_X86_SSE1) { |
| 2694 | /* sfence */ |
| 2695 | *p++ = 0x0F; *p++ = 0xAE; *p++ = 0xF8; |
| 2696 | /* lock addl $0,0(%esp) */ |
| 2697 | *p++ = 0xF0; *p++ = 0x83; *p++ = 0x44; |
| 2698 | *p++ = 0x24; *p++ = 0x00; *p++ = 0x00; |
| 2699 | goto done; |
| 2700 | } |
| 2701 | if (i->Xin.MFence.hwcaps == 0/*baseline, no SSE*/) { |
| 2702 | /* lock addl $0,0(%esp) */ |
| 2703 | *p++ = 0xF0; *p++ = 0x83; *p++ = 0x44; |
| 2704 | *p++ = 0x24; *p++ = 0x00; *p++ = 0x00; |
| 2705 | goto done; |
| 2706 | } |
| 2707 | vpanic("emit_X86Instr:mfence:hwcaps"); |
| 2708 | /*NOTREACHED*/ |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 2709 | break; |
| 2710 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2711 | case Xin_ACAS: |
| 2712 | /* lock */ |
| 2713 | *p++ = 0xF0; |
| 2714 | /* cmpxchg{b,w,l} %ebx,mem. Expected-value in %eax, new value |
| 2715 | in %ebx. The new-value register is hardwired to be %ebx |
| 2716 | since letting it be any integer register gives the problem |
| 2717 | that %sil and %dil are unaddressible on x86 and hence we |
| 2718 | would have to resort to the same kind of trickery as with |
| 2719 | byte-sized Xin.Store, just below. Given that this isn't |
| 2720 | performance critical, it is simpler just to force the |
| 2721 | register operand to %ebx (could equally be %ecx or %edx). |
| 2722 | (Although %ebx is more consistent with cmpxchg8b.) */ |
| 2723 | if (i->Xin.ACAS.sz == 2) *p++ = 0x66; |
| 2724 | *p++ = 0x0F; |
| 2725 | if (i->Xin.ACAS.sz == 1) *p++ = 0xB0; else *p++ = 0xB1; |
| 2726 | p = doAMode_M(p, hregX86_EBX(), i->Xin.ACAS.addr); |
| 2727 | goto done; |
| 2728 | |
| 2729 | case Xin_DACAS: |
| 2730 | /* lock */ |
| 2731 | *p++ = 0xF0; |
| 2732 | /* cmpxchg8b m64. Expected-value in %edx:%eax, new value |
| 2733 | in %ecx:%ebx. All 4 regs are hardwired in the ISA, so |
| 2734 | aren't encoded in the insn. */ |
| 2735 | *p++ = 0x0F; |
| 2736 | *p++ = 0xC7; |
| 2737 | p = doAMode_M(p, fake(1), i->Xin.DACAS.addr); |
| 2738 | goto done; |
| 2739 | |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2740 | case Xin_Store: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2741 | if (i->Xin.Store.sz == 2) { |
| 2742 | /* This case, at least, is simple, given that we can |
| 2743 | reference the low 16 bits of any integer register. */ |
| 2744 | *p++ = 0x66; |
| 2745 | *p++ = 0x89; |
| 2746 | p = doAMode_M(p, i->Xin.Store.src, i->Xin.Store.dst); |
| 2747 | goto done; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2748 | } |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2749 | |
| 2750 | if (i->Xin.Store.sz == 1) { |
| 2751 | /* We have to do complex dodging and weaving if src is not |
| 2752 | the low 8 bits of %eax/%ebx/%ecx/%edx. */ |
| 2753 | if (iregNo(i->Xin.Store.src) < 4) { |
| 2754 | /* we're OK, can do it directly */ |
| 2755 | *p++ = 0x88; |
| 2756 | p = doAMode_M(p, i->Xin.Store.src, i->Xin.Store.dst); |
| 2757 | goto done; |
| 2758 | } else { |
| 2759 | /* Bleh. This means the source is %edi or %esi. Since |
| 2760 | the address mode can only mention three registers, at |
| 2761 | least one of %eax/%ebx/%ecx/%edx must be available to |
| 2762 | temporarily swap the source into, so the store can |
| 2763 | happen. So we have to look at the regs mentioned |
| 2764 | in the amode. */ |
sewardj | 2e56f9f | 2004-07-24 01:24:38 +0000 | [diff] [blame] | 2765 | HReg swap = INVALID_HREG; |
| 2766 | HReg eax = hregX86_EAX(), ebx = hregX86_EBX(), |
| 2767 | ecx = hregX86_ECX(), edx = hregX86_EDX(); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2768 | Bool a_ok = True, b_ok = True, c_ok = True, d_ok = True; |
| 2769 | HRegUsage u; |
| 2770 | Int j; |
| 2771 | initHRegUsage(&u); |
| 2772 | addRegUsage_X86AMode(&u, i->Xin.Store.dst); |
| 2773 | for (j = 0; j < u.n_used; j++) { |
| 2774 | HReg r = u.hreg[j]; |
| 2775 | if (r == eax) a_ok = False; |
| 2776 | if (r == ebx) b_ok = False; |
| 2777 | if (r == ecx) c_ok = False; |
| 2778 | if (r == edx) d_ok = False; |
| 2779 | } |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2780 | if (a_ok) swap = eax; |
| 2781 | if (b_ok) swap = ebx; |
| 2782 | if (c_ok) swap = ecx; |
| 2783 | if (d_ok) swap = edx; |
| 2784 | vassert(swap != INVALID_HREG); |
| 2785 | /* xchgl %source, %swap. Could do better if swap is %eax. */ |
| 2786 | *p++ = 0x87; |
| 2787 | p = doAMode_R(p, i->Xin.Store.src, swap); |
| 2788 | /* movb lo8{%swap}, (dst) */ |
| 2789 | *p++ = 0x88; |
| 2790 | p = doAMode_M(p, swap, i->Xin.Store.dst); |
| 2791 | /* xchgl %source, %swap. Could do better if swap is %eax. */ |
| 2792 | *p++ = 0x87; |
| 2793 | p = doAMode_R(p, i->Xin.Store.src, swap); |
| 2794 | goto done; |
| 2795 | } |
| 2796 | } /* if (i->Xin.Store.sz == 1) */ |
| 2797 | break; |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 2798 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2799 | case Xin_FpUnary: |
| 2800 | /* gop %src, %dst |
| 2801 | --> ffree %st7 ; fld %st(src) ; fop %st(0) ; fstp %st(1+dst) |
| 2802 | */ |
| 2803 | p = do_ffree_st7(p); |
| 2804 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpUnary.src)); |
| 2805 | p = do_fop1_st(p, i->Xin.FpUnary.op); |
| 2806 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpUnary.dst)); |
| 2807 | goto done; |
| 2808 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2809 | case Xin_FpBinary: |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2810 | if (i->Xin.FpBinary.op == Xfp_YL2X |
| 2811 | || i->Xin.FpBinary.op == Xfp_YL2XP1) { |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 2812 | /* Have to do this specially. */ |
| 2813 | /* ffree %st7 ; fld %st(srcL) ; |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2814 | ffree %st7 ; fld %st(srcR+1) ; fyl2x{p1} ; fstp(1+dst) */ |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 2815 | p = do_ffree_st7(p); |
| 2816 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL)); |
| 2817 | p = do_ffree_st7(p); |
| 2818 | p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcR)); |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2819 | *p++ = 0xD9; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2820 | *p++ = toUChar(i->Xin.FpBinary.op==Xfp_YL2X ? 0xF1 : 0xF9); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 2821 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst)); |
| 2822 | goto done; |
| 2823 | } |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 2824 | if (i->Xin.FpBinary.op == Xfp_ATAN) { |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2825 | /* Have to do this specially. */ |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2826 | /* ffree %st7 ; fld %st(srcL) ; |
| 2827 | ffree %st7 ; fld %st(srcR+1) ; fpatan ; fstp(1+dst) */ |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2828 | p = do_ffree_st7(p); |
| 2829 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL)); |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2830 | p = do_ffree_st7(p); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2831 | p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcR)); |
| 2832 | *p++ = 0xD9; *p++ = 0xF3; |
| 2833 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst)); |
| 2834 | goto done; |
| 2835 | } |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2836 | if (i->Xin.FpBinary.op == Xfp_PREM |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 2837 | || i->Xin.FpBinary.op == Xfp_PREM1 |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2838 | || i->Xin.FpBinary.op == Xfp_SCALE) { |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2839 | /* Have to do this specially. */ |
| 2840 | /* ffree %st7 ; fld %st(srcR) ; |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 2841 | ffree %st7 ; fld %st(srcL+1) ; fprem/fprem1/fscale ; fstp(2+dst) ; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2842 | fincstp ; ffree %st7 */ |
| 2843 | p = do_ffree_st7(p); |
| 2844 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcR)); |
| 2845 | p = do_ffree_st7(p); |
| 2846 | p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcL)); |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 2847 | *p++ = 0xD9; |
| 2848 | switch (i->Xin.FpBinary.op) { |
| 2849 | case Xfp_PREM: *p++ = 0xF8; break; |
| 2850 | case Xfp_PREM1: *p++ = 0xF5; break; |
| 2851 | case Xfp_SCALE: *p++ = 0xFD; break; |
| 2852 | default: vpanic("emitX86Instr(FpBinary,PREM/PREM1/SCALE)"); |
| 2853 | } |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2854 | p = do_fstp_st(p, 2+hregNumber(i->Xin.FpBinary.dst)); |
| 2855 | *p++ = 0xD9; *p++ = 0xF7; |
| 2856 | p = do_ffree_st7(p); |
| 2857 | goto done; |
| 2858 | } |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2859 | /* General case */ |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2860 | /* gop %srcL, %srcR, %dst |
| 2861 | --> ffree %st7 ; fld %st(srcL) ; fop %st(1+srcR) ; fstp %st(1+dst) |
| 2862 | */ |
| 2863 | p = do_ffree_st7(p); |
| 2864 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL)); |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 2865 | p = do_fop2_st(p, i->Xin.FpBinary.op, |
| 2866 | 1+hregNumber(i->Xin.FpBinary.srcR)); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2867 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst)); |
| 2868 | goto done; |
| 2869 | |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2870 | case Xin_FpLdSt: |
| 2871 | if (i->Xin.FpLdSt.isLoad) { |
| 2872 | /* Load from memory into %fakeN. |
sewardj | 7fb65eb | 2007-03-25 04:14:58 +0000 | [diff] [blame] | 2873 | --> ffree %st(7) ; fld{s/l/t} amode ; fstp st(N+1) |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2874 | */ |
| 2875 | p = do_ffree_st7(p); |
sewardj | 7fb65eb | 2007-03-25 04:14:58 +0000 | [diff] [blame] | 2876 | switch (i->Xin.FpLdSt.sz) { |
| 2877 | case 4: |
| 2878 | *p++ = 0xD9; |
| 2879 | p = doAMode_M(p, fake(0)/*subopcode*/, i->Xin.FpLdSt.addr); |
| 2880 | break; |
| 2881 | case 8: |
| 2882 | *p++ = 0xDD; |
| 2883 | p = doAMode_M(p, fake(0)/*subopcode*/, i->Xin.FpLdSt.addr); |
| 2884 | break; |
| 2885 | case 10: |
| 2886 | *p++ = 0xDB; |
| 2887 | p = doAMode_M(p, fake(5)/*subopcode*/, i->Xin.FpLdSt.addr); |
| 2888 | break; |
| 2889 | default: |
| 2890 | vpanic("emitX86Instr(FpLdSt,load)"); |
| 2891 | } |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2892 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpLdSt.reg)); |
| 2893 | goto done; |
| 2894 | } else { |
| 2895 | /* Store from %fakeN into memory. |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2896 | --> ffree %st(7) ; fld st(N) ; fstp{l|s} amode |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2897 | */ |
| 2898 | p = do_ffree_st7(p); |
| 2899 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpLdSt.reg)); |
sewardj | 7fb65eb | 2007-03-25 04:14:58 +0000 | [diff] [blame] | 2900 | switch (i->Xin.FpLdSt.sz) { |
| 2901 | case 4: |
| 2902 | *p++ = 0xD9; |
| 2903 | p = doAMode_M(p, fake(3)/*subopcode*/, i->Xin.FpLdSt.addr); |
| 2904 | break; |
| 2905 | case 8: |
| 2906 | *p++ = 0xDD; |
| 2907 | p = doAMode_M(p, fake(3)/*subopcode*/, i->Xin.FpLdSt.addr); |
| 2908 | break; |
| 2909 | case 10: |
| 2910 | *p++ = 0xDB; |
| 2911 | p = doAMode_M(p, fake(7)/*subopcode*/, i->Xin.FpLdSt.addr); |
| 2912 | break; |
| 2913 | default: |
| 2914 | vpanic("emitX86Instr(FpLdSt,store)"); |
| 2915 | } |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2916 | goto done; |
| 2917 | } |
| 2918 | break; |
| 2919 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2920 | case Xin_FpLdStI: |
| 2921 | if (i->Xin.FpLdStI.isLoad) { |
| 2922 | /* Load from memory into %fakeN, converting from an int. |
| 2923 | --> ffree %st(7) ; fild{w/l/ll} amode ; fstp st(N+1) |
| 2924 | */ |
| 2925 | switch (i->Xin.FpLdStI.sz) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 2926 | case 8: opc = 0xDF; subopc_imm = 5; break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2927 | case 4: opc = 0xDB; subopc_imm = 0; break; |
| 2928 | case 2: vassert(0); opc = 0xDF; subopc_imm = 0; break; |
| 2929 | default: vpanic("emitX86Instr(Xin_FpLdStI-load)"); |
| 2930 | } |
| 2931 | p = do_ffree_st7(p); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2932 | *p++ = toUChar(opc); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2933 | p = doAMode_M(p, fake(subopc_imm)/*subopcode*/, i->Xin.FpLdStI.addr); |
| 2934 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpLdStI.reg)); |
| 2935 | goto done; |
| 2936 | } else { |
| 2937 | /* Store from %fakeN into memory, converting to an int. |
| 2938 | --> ffree %st(7) ; fld st(N) ; fistp{w/l/ll} amode |
| 2939 | */ |
| 2940 | switch (i->Xin.FpLdStI.sz) { |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2941 | case 8: opc = 0xDF; subopc_imm = 7; break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2942 | case 4: opc = 0xDB; subopc_imm = 3; break; |
| 2943 | case 2: opc = 0xDF; subopc_imm = 3; break; |
| 2944 | default: vpanic("emitX86Instr(Xin_FpLdStI-store)"); |
| 2945 | } |
| 2946 | p = do_ffree_st7(p); |
| 2947 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpLdStI.reg)); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2948 | *p++ = toUChar(opc); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2949 | p = doAMode_M(p, fake(subopc_imm)/*subopcode*/, i->Xin.FpLdStI.addr); |
| 2950 | goto done; |
| 2951 | } |
| 2952 | break; |
| 2953 | |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 2954 | case Xin_Fp64to32: |
| 2955 | /* ffree %st7 ; fld %st(src) */ |
| 2956 | p = do_ffree_st7(p); |
| 2957 | p = do_fld_st(p, 0+fregNo(i->Xin.Fp64to32.src)); |
| 2958 | /* subl $4, %esp */ |
| 2959 | *p++ = 0x83; *p++ = 0xEC; *p++ = 0x04; |
| 2960 | /* fstps (%esp) */ |
| 2961 | *p++ = 0xD9; *p++ = 0x1C; *p++ = 0x24; |
| 2962 | /* flds (%esp) */ |
| 2963 | *p++ = 0xD9; *p++ = 0x04; *p++ = 0x24; |
| 2964 | /* addl $4, %esp */ |
| 2965 | *p++ = 0x83; *p++ = 0xC4; *p++ = 0x04; |
| 2966 | /* fstp %st(1+dst) */ |
| 2967 | p = do_fstp_st(p, 1+fregNo(i->Xin.Fp64to32.dst)); |
| 2968 | goto done; |
| 2969 | |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 2970 | case Xin_FpCMov: |
| 2971 | /* jmp fwds if !condition */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2972 | *p++ = toUChar(0x70 + (i->Xin.FpCMov.cond ^ 1)); |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 2973 | *p++ = 0; /* # of bytes in the next bit, which we don't know yet */ |
| 2974 | ptmp = p; |
| 2975 | |
| 2976 | /* ffree %st7 ; fld %st(src) ; fstp %st(1+dst) */ |
| 2977 | p = do_ffree_st7(p); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 2978 | p = do_fld_st(p, 0+fregNo(i->Xin.FpCMov.src)); |
| 2979 | p = do_fstp_st(p, 1+fregNo(i->Xin.FpCMov.dst)); |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 2980 | |
| 2981 | /* Fill in the jump offset. */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2982 | *(ptmp-1) = toUChar(p - ptmp); |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 2983 | goto done; |
| 2984 | |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2985 | case Xin_FpLdCW: |
| 2986 | *p++ = 0xD9; |
| 2987 | p = doAMode_M(p, fake(5)/*subopcode*/, i->Xin.FpLdCW.addr); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 2988 | goto done; |
| 2989 | |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2990 | case Xin_FpStSW_AX: |
| 2991 | /* note, this emits fnstsw %ax, not fstsw %ax */ |
| 2992 | *p++ = 0xDF; |
| 2993 | *p++ = 0xE0; |
| 2994 | goto done; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 2995 | |
| 2996 | case Xin_FpCmp: |
| 2997 | /* gcmp %fL, %fR, %dst |
| 2998 | -> ffree %st7; fpush %fL ; fucomp %(fR+1) ; |
| 2999 | fnstsw %ax ; movl %eax, %dst |
| 3000 | */ |
| 3001 | /* ffree %st7 */ |
| 3002 | p = do_ffree_st7(p); |
| 3003 | /* fpush %fL */ |
| 3004 | p = do_fld_st(p, 0+fregNo(i->Xin.FpCmp.srcL)); |
| 3005 | /* fucomp %(fR+1) */ |
| 3006 | *p++ = 0xDD; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3007 | *p++ = toUChar(0xE8 + (7 & (1+fregNo(i->Xin.FpCmp.srcR)))); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3008 | /* fnstsw %ax */ |
| 3009 | *p++ = 0xDF; |
| 3010 | *p++ = 0xE0; |
| 3011 | /* movl %eax, %dst */ |
| 3012 | *p++ = 0x89; |
| 3013 | p = doAMode_R(p, hregX86_EAX(), i->Xin.FpCmp.dst); |
| 3014 | goto done; |
| 3015 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3016 | case Xin_SseConst: { |
| 3017 | UShort con = i->Xin.SseConst.con; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3018 | p = push_word_from_tags(p, toUShort((con >> 12) & 0xF)); |
| 3019 | p = push_word_from_tags(p, toUShort((con >> 8) & 0xF)); |
| 3020 | p = push_word_from_tags(p, toUShort((con >> 4) & 0xF)); |
| 3021 | p = push_word_from_tags(p, toUShort(con & 0xF)); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3022 | /* movl (%esp), %xmm-dst */ |
| 3023 | *p++ = 0x0F; |
| 3024 | *p++ = 0x10; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3025 | *p++ = toUChar(0x04 + 8 * (7 & vregNo(i->Xin.SseConst.dst))); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3026 | *p++ = 0x24; |
| 3027 | /* addl $16, %esp */ |
| 3028 | *p++ = 0x83; |
| 3029 | *p++ = 0xC4; |
| 3030 | *p++ = 0x10; |
| 3031 | goto done; |
| 3032 | } |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 3033 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 3034 | case Xin_SseLdSt: |
| 3035 | *p++ = 0x0F; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3036 | *p++ = toUChar(i->Xin.SseLdSt.isLoad ? 0x10 : 0x11); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 3037 | p = doAMode_M(p, fake(vregNo(i->Xin.SseLdSt.reg)), i->Xin.SseLdSt.addr); |
| 3038 | goto done; |
| 3039 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 3040 | case Xin_SseLdzLO: |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 3041 | vassert(i->Xin.SseLdzLO.sz == 4 || i->Xin.SseLdzLO.sz == 8); |
| 3042 | /* movs[sd] amode, %xmm-dst */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3043 | *p++ = toUChar(i->Xin.SseLdzLO.sz==4 ? 0xF3 : 0xF2); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 3044 | *p++ = 0x0F; |
| 3045 | *p++ = 0x10; |
| 3046 | p = doAMode_M(p, fake(vregNo(i->Xin.SseLdzLO.reg)), |
| 3047 | i->Xin.SseLdzLO.addr); |
| 3048 | goto done; |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 3049 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3050 | case Xin_Sse32Fx4: |
| 3051 | xtra = 0; |
| 3052 | *p++ = 0x0F; |
| 3053 | switch (i->Xin.Sse32Fx4.op) { |
| 3054 | case Xsse_ADDF: *p++ = 0x58; break; |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 3055 | case Xsse_DIVF: *p++ = 0x5E; break; |
| 3056 | case Xsse_MAXF: *p++ = 0x5F; break; |
| 3057 | case Xsse_MINF: *p++ = 0x5D; break; |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 3058 | case Xsse_MULF: *p++ = 0x59; break; |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 3059 | case Xsse_RCPF: *p++ = 0x53; break; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 3060 | case Xsse_RSQRTF: *p++ = 0x52; break; |
| 3061 | case Xsse_SQRTF: *p++ = 0x51; break; |
| 3062 | case Xsse_SUBF: *p++ = 0x5C; break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3063 | case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; |
| 3064 | case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; |
| 3065 | case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; |
sewardj | a26f661 | 2005-11-05 01:54:07 +0000 | [diff] [blame] | 3066 | case Xsse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3067 | default: goto bad; |
| 3068 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 3069 | p = doAMode_R(p, fake(vregNo(i->Xin.Sse32Fx4.dst)), |
| 3070 | fake(vregNo(i->Xin.Sse32Fx4.src)) ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3071 | if (xtra & 0x100) |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3072 | *p++ = toUChar(xtra & 0xFF); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3073 | goto done; |
| 3074 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 3075 | case Xin_Sse64Fx2: |
| 3076 | xtra = 0; |
| 3077 | *p++ = 0x66; |
| 3078 | *p++ = 0x0F; |
| 3079 | switch (i->Xin.Sse64Fx2.op) { |
| 3080 | case Xsse_ADDF: *p++ = 0x58; break; |
| 3081 | case Xsse_DIVF: *p++ = 0x5E; break; |
| 3082 | case Xsse_MAXF: *p++ = 0x5F; break; |
| 3083 | case Xsse_MINF: *p++ = 0x5D; break; |
| 3084 | case Xsse_MULF: *p++ = 0x59; break; |
| 3085 | case Xsse_RCPF: *p++ = 0x53; break; |
| 3086 | case Xsse_RSQRTF: *p++ = 0x52; break; |
| 3087 | case Xsse_SQRTF: *p++ = 0x51; break; |
| 3088 | case Xsse_SUBF: *p++ = 0x5C; break; |
| 3089 | case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; |
| 3090 | case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; |
| 3091 | case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; |
sewardj | a26f661 | 2005-11-05 01:54:07 +0000 | [diff] [blame] | 3092 | case Xsse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 3093 | default: goto bad; |
| 3094 | } |
| 3095 | p = doAMode_R(p, fake(vregNo(i->Xin.Sse64Fx2.dst)), |
| 3096 | fake(vregNo(i->Xin.Sse64Fx2.src)) ); |
| 3097 | if (xtra & 0x100) |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3098 | *p++ = toUChar(xtra & 0xFF); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 3099 | goto done; |
| 3100 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3101 | case Xin_Sse32FLo: |
| 3102 | xtra = 0; |
| 3103 | *p++ = 0xF3; |
| 3104 | *p++ = 0x0F; |
| 3105 | switch (i->Xin.Sse32FLo.op) { |
| 3106 | case Xsse_ADDF: *p++ = 0x58; break; |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 3107 | case Xsse_DIVF: *p++ = 0x5E; break; |
| 3108 | case Xsse_MAXF: *p++ = 0x5F; break; |
| 3109 | case Xsse_MINF: *p++ = 0x5D; break; |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 3110 | case Xsse_MULF: *p++ = 0x59; break; |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 3111 | case Xsse_RCPF: *p++ = 0x53; break; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 3112 | case Xsse_RSQRTF: *p++ = 0x52; break; |
| 3113 | case Xsse_SQRTF: *p++ = 0x51; break; |
| 3114 | case Xsse_SUBF: *p++ = 0x5C; break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3115 | case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; |
| 3116 | case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; |
| 3117 | case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; |
sewardj | a26f661 | 2005-11-05 01:54:07 +0000 | [diff] [blame] | 3118 | case Xsse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 3119 | default: goto bad; |
| 3120 | } |
| 3121 | p = doAMode_R(p, fake(vregNo(i->Xin.Sse32FLo.dst)), |
| 3122 | fake(vregNo(i->Xin.Sse32FLo.src)) ); |
| 3123 | if (xtra & 0x100) |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3124 | *p++ = toUChar(xtra & 0xFF); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 3125 | goto done; |
| 3126 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 3127 | case Xin_Sse64FLo: |
| 3128 | xtra = 0; |
| 3129 | *p++ = 0xF2; |
| 3130 | *p++ = 0x0F; |
| 3131 | switch (i->Xin.Sse64FLo.op) { |
| 3132 | case Xsse_ADDF: *p++ = 0x58; break; |
| 3133 | case Xsse_DIVF: *p++ = 0x5E; break; |
| 3134 | case Xsse_MAXF: *p++ = 0x5F; break; |
| 3135 | case Xsse_MINF: *p++ = 0x5D; break; |
| 3136 | case Xsse_MULF: *p++ = 0x59; break; |
| 3137 | case Xsse_RCPF: *p++ = 0x53; break; |
| 3138 | case Xsse_RSQRTF: *p++ = 0x52; break; |
| 3139 | case Xsse_SQRTF: *p++ = 0x51; break; |
| 3140 | case Xsse_SUBF: *p++ = 0x5C; break; |
| 3141 | case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; |
| 3142 | case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; |
| 3143 | case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; |
sewardj | a26f661 | 2005-11-05 01:54:07 +0000 | [diff] [blame] | 3144 | case Xsse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 3145 | default: goto bad; |
| 3146 | } |
| 3147 | p = doAMode_R(p, fake(vregNo(i->Xin.Sse64FLo.dst)), |
| 3148 | fake(vregNo(i->Xin.Sse64FLo.src)) ); |
| 3149 | if (xtra & 0x100) |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3150 | *p++ = toUChar(xtra & 0xFF); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 3151 | goto done; |
| 3152 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 3153 | case Xin_SseReRg: |
| 3154 | # define XX(_n) *p++ = (_n) |
| 3155 | switch (i->Xin.SseReRg.op) { |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 3156 | case Xsse_MOV: /*movups*/ XX(0x0F); XX(0x10); break; |
| 3157 | case Xsse_OR: XX(0x0F); XX(0x56); break; |
| 3158 | case Xsse_XOR: XX(0x0F); XX(0x57); break; |
| 3159 | case Xsse_AND: XX(0x0F); XX(0x54); break; |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 3160 | case Xsse_PACKSSD: XX(0x66); XX(0x0F); XX(0x6B); break; |
| 3161 | case Xsse_PACKSSW: XX(0x66); XX(0x0F); XX(0x63); break; |
| 3162 | case Xsse_PACKUSW: XX(0x66); XX(0x0F); XX(0x67); break; |
| 3163 | case Xsse_ADD8: XX(0x66); XX(0x0F); XX(0xFC); break; |
| 3164 | case Xsse_ADD16: XX(0x66); XX(0x0F); XX(0xFD); break; |
| 3165 | case Xsse_ADD32: XX(0x66); XX(0x0F); XX(0xFE); break; |
| 3166 | case Xsse_ADD64: XX(0x66); XX(0x0F); XX(0xD4); break; |
| 3167 | case Xsse_QADD8S: XX(0x66); XX(0x0F); XX(0xEC); break; |
| 3168 | case Xsse_QADD16S: XX(0x66); XX(0x0F); XX(0xED); break; |
| 3169 | case Xsse_QADD8U: XX(0x66); XX(0x0F); XX(0xDC); break; |
| 3170 | case Xsse_QADD16U: XX(0x66); XX(0x0F); XX(0xDD); break; |
| 3171 | case Xsse_AVG8U: XX(0x66); XX(0x0F); XX(0xE0); break; |
| 3172 | case Xsse_AVG16U: XX(0x66); XX(0x0F); XX(0xE3); break; |
| 3173 | case Xsse_CMPEQ8: XX(0x66); XX(0x0F); XX(0x74); break; |
| 3174 | case Xsse_CMPEQ16: XX(0x66); XX(0x0F); XX(0x75); break; |
| 3175 | case Xsse_CMPEQ32: XX(0x66); XX(0x0F); XX(0x76); break; |
| 3176 | case Xsse_CMPGT8S: XX(0x66); XX(0x0F); XX(0x64); break; |
| 3177 | case Xsse_CMPGT16S: XX(0x66); XX(0x0F); XX(0x65); break; |
| 3178 | case Xsse_CMPGT32S: XX(0x66); XX(0x0F); XX(0x66); break; |
| 3179 | case Xsse_MAX16S: XX(0x66); XX(0x0F); XX(0xEE); break; |
| 3180 | case Xsse_MAX8U: XX(0x66); XX(0x0F); XX(0xDE); break; |
| 3181 | case Xsse_MIN16S: XX(0x66); XX(0x0F); XX(0xEA); break; |
| 3182 | case Xsse_MIN8U: XX(0x66); XX(0x0F); XX(0xDA); break; |
| 3183 | case Xsse_MULHI16U: XX(0x66); XX(0x0F); XX(0xE4); break; |
| 3184 | case Xsse_MULHI16S: XX(0x66); XX(0x0F); XX(0xE5); break; |
| 3185 | case Xsse_MUL16: XX(0x66); XX(0x0F); XX(0xD5); break; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 3186 | case Xsse_SHL16: XX(0x66); XX(0x0F); XX(0xF1); break; |
| 3187 | case Xsse_SHL32: XX(0x66); XX(0x0F); XX(0xF2); break; |
| 3188 | case Xsse_SHL64: XX(0x66); XX(0x0F); XX(0xF3); break; |
| 3189 | case Xsse_SAR16: XX(0x66); XX(0x0F); XX(0xE1); break; |
| 3190 | case Xsse_SAR32: XX(0x66); XX(0x0F); XX(0xE2); break; |
| 3191 | case Xsse_SHR16: XX(0x66); XX(0x0F); XX(0xD1); break; |
| 3192 | case Xsse_SHR32: XX(0x66); XX(0x0F); XX(0xD2); break; |
| 3193 | case Xsse_SHR64: XX(0x66); XX(0x0F); XX(0xD3); break; |
| 3194 | case Xsse_SUB8: XX(0x66); XX(0x0F); XX(0xF8); break; |
| 3195 | case Xsse_SUB16: XX(0x66); XX(0x0F); XX(0xF9); break; |
| 3196 | case Xsse_SUB32: XX(0x66); XX(0x0F); XX(0xFA); break; |
| 3197 | case Xsse_SUB64: XX(0x66); XX(0x0F); XX(0xFB); break; |
| 3198 | case Xsse_QSUB8S: XX(0x66); XX(0x0F); XX(0xE8); break; |
| 3199 | case Xsse_QSUB16S: XX(0x66); XX(0x0F); XX(0xE9); break; |
| 3200 | case Xsse_QSUB8U: XX(0x66); XX(0x0F); XX(0xD8); break; |
| 3201 | case Xsse_QSUB16U: XX(0x66); XX(0x0F); XX(0xD9); break; |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 3202 | case Xsse_UNPCKHB: XX(0x66); XX(0x0F); XX(0x68); break; |
| 3203 | case Xsse_UNPCKHW: XX(0x66); XX(0x0F); XX(0x69); break; |
| 3204 | case Xsse_UNPCKHD: XX(0x66); XX(0x0F); XX(0x6A); break; |
| 3205 | case Xsse_UNPCKHQ: XX(0x66); XX(0x0F); XX(0x6D); break; |
| 3206 | case Xsse_UNPCKLB: XX(0x66); XX(0x0F); XX(0x60); break; |
| 3207 | case Xsse_UNPCKLW: XX(0x66); XX(0x0F); XX(0x61); break; |
| 3208 | case Xsse_UNPCKLD: XX(0x66); XX(0x0F); XX(0x62); break; |
| 3209 | case Xsse_UNPCKLQ: XX(0x66); XX(0x0F); XX(0x6C); break; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 3210 | default: goto bad; |
| 3211 | } |
| 3212 | p = doAMode_R(p, fake(vregNo(i->Xin.SseReRg.dst)), |
| 3213 | fake(vregNo(i->Xin.SseReRg.src)) ); |
| 3214 | # undef XX |
| 3215 | goto done; |
| 3216 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 3217 | case Xin_SseCMov: |
| 3218 | /* jmp fwds if !condition */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3219 | *p++ = toUChar(0x70 + (i->Xin.SseCMov.cond ^ 1)); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 3220 | *p++ = 0; /* # of bytes in the next bit, which we don't know yet */ |
| 3221 | ptmp = p; |
| 3222 | |
| 3223 | /* movaps %src, %dst */ |
| 3224 | *p++ = 0x0F; |
| 3225 | *p++ = 0x28; |
| 3226 | p = doAMode_R(p, fake(vregNo(i->Xin.SseCMov.dst)), |
| 3227 | fake(vregNo(i->Xin.SseCMov.src)) ); |
| 3228 | |
| 3229 | /* Fill in the jump offset. */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 3230 | *(ptmp-1) = toUChar(p - ptmp); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 3231 | goto done; |
| 3232 | |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 3233 | case Xin_SseShuf: |
| 3234 | *p++ = 0x66; |
| 3235 | *p++ = 0x0F; |
| 3236 | *p++ = 0x70; |
| 3237 | p = doAMode_R(p, fake(vregNo(i->Xin.SseShuf.dst)), |
| 3238 | fake(vregNo(i->Xin.SseShuf.src)) ); |
| 3239 | *p++ = (UChar)(i->Xin.SseShuf.order); |
| 3240 | goto done; |
| 3241 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3242 | case Xin_EvCheck: { |
| 3243 | /* We generate: |
| 3244 | (3 bytes) decl 4(%ebp) 4 == offsetof(host_EvC_COUNTER) |
| 3245 | (2 bytes) jns nofail expected taken |
| 3246 | (3 bytes) jmp* 0(%ebp) 0 == offsetof(host_EvC_FAILADDR) |
| 3247 | nofail: |
| 3248 | */ |
| 3249 | /* This is heavily asserted re instruction lengths. It needs to |
| 3250 | be. If we get given unexpected forms of .amCounter or |
| 3251 | .amFailAddr -- basically, anything that's not of the form |
| 3252 | uimm7(%ebp) -- they are likely to fail. */ |
| 3253 | /* Note also that after the decl we must be very careful not to |
| 3254 | read the carry flag, else we get a partial flags stall. |
| 3255 | js/jns avoids that, though. */ |
| 3256 | UChar* p0 = p; |
| 3257 | /* --- decl 8(%ebp) --- */ |
| 3258 | /* "fake(1)" because + there's no register in this encoding; |
| 3259 | instead the register + field is used as a sub opcode. The |
| 3260 | encoding for "decl r/m32" + is FF /1, hence the fake(1). */ |
| 3261 | *p++ = 0xFF; |
| 3262 | p = doAMode_M(p, fake(1), i->Xin.EvCheck.amCounter); |
| 3263 | vassert(p - p0 == 3); |
| 3264 | /* --- jns nofail --- */ |
| 3265 | *p++ = 0x79; |
| 3266 | *p++ = 0x03; /* need to check this 0x03 after the next insn */ |
| 3267 | vassert(p - p0 == 5); |
| 3268 | /* --- jmp* 0(%ebp) --- */ |
| 3269 | /* The encoding is FF /4. */ |
| 3270 | *p++ = 0xFF; |
| 3271 | p = doAMode_M(p, fake(4), i->Xin.EvCheck.amFailAddr); |
| 3272 | vassert(p - p0 == 8); /* also ensures that 0x03 offset above is ok */ |
| 3273 | /* And crosscheck .. */ |
| 3274 | vassert(evCheckSzB_X86() == 8); |
| 3275 | goto done; |
| 3276 | } |
| 3277 | |
| 3278 | case Xin_ProfInc: { |
| 3279 | /* We generate addl $1,NotKnownYet |
| 3280 | adcl $0,NotKnownYet+4 |
| 3281 | in the expectation that a later call to LibVEX_patchProfCtr |
| 3282 | will be used to fill in the immediate fields once the right |
| 3283 | value is known. |
| 3284 | 83 05 00 00 00 00 01 |
| 3285 | 83 15 00 00 00 00 00 |
| 3286 | */ |
| 3287 | *p++ = 0x83; *p++ = 0x05; |
| 3288 | *p++ = 0x00; *p++ = 0x00; *p++ = 0x00; *p++ = 0x00; |
| 3289 | *p++ = 0x01; |
| 3290 | *p++ = 0x83; *p++ = 0x15; |
| 3291 | *p++ = 0x00; *p++ = 0x00; *p++ = 0x00; *p++ = 0x00; |
| 3292 | *p++ = 0x00; |
| 3293 | /* Tell the caller .. */ |
| 3294 | vassert(!(*is_profInc)); |
| 3295 | *is_profInc = True; |
| 3296 | goto done; |
| 3297 | } |
| 3298 | |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 3299 | default: |
| 3300 | goto bad; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 3301 | } |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 3302 | |
| 3303 | bad: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 3304 | ppX86Instr(i, mode64); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 3305 | vpanic("emit_X86Instr"); |
| 3306 | /*NOTREACHED*/ |
| 3307 | |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 3308 | done: |
| 3309 | vassert(p - &buf[0] <= 32); |
| 3310 | return p - &buf[0]; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 3311 | |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 3312 | # undef fake |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 3313 | } |
| 3314 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3315 | |
| 3316 | /* How big is an event check? See case for Xin_EvCheck in |
| 3317 | emit_X86Instr just above. That crosschecks what this returns, so |
| 3318 | we can tell if we're inconsistent. */ |
| 3319 | Int evCheckSzB_X86 ( void ) |
| 3320 | { |
| 3321 | return 8; |
| 3322 | } |
| 3323 | |
| 3324 | |
| 3325 | /* NB: what goes on here has to be very closely coordinated with the |
| 3326 | emitInstr case for XDirect, above. */ |
| 3327 | VexInvalRange chainXDirect_X86 ( void* place_to_chain, |
| 3328 | void* disp_cp_chain_me_EXPECTED, |
| 3329 | void* place_to_jump_to ) |
| 3330 | { |
| 3331 | /* What we're expecting to see is: |
| 3332 | movl $disp_cp_chain_me_EXPECTED, %edx |
| 3333 | call *%edx |
| 3334 | viz |
| 3335 | BA <4 bytes value == disp_cp_chain_me_EXPECTED> |
| 3336 | FF D2 |
| 3337 | */ |
| 3338 | UChar* p = (UChar*)place_to_chain; |
| 3339 | vassert(p[0] == 0xBA); |
| 3340 | vassert(*(UInt*)(&p[1]) == (UInt)Ptr_to_ULong(disp_cp_chain_me_EXPECTED)); |
| 3341 | vassert(p[5] == 0xFF); |
| 3342 | vassert(p[6] == 0xD2); |
| 3343 | /* And what we want to change it to is: |
| 3344 | jmp disp32 where disp32 is relative to the next insn |
| 3345 | ud2; |
| 3346 | viz |
| 3347 | E9 <4 bytes == disp32> |
| 3348 | 0F 0B |
| 3349 | The replacement has the same length as the original. |
| 3350 | */ |
| 3351 | /* This is the delta we need to put into a JMP d32 insn. It's |
| 3352 | relative to the start of the next insn, hence the -5. */ |
| 3353 | Long delta = (Long)((UChar*)place_to_jump_to - (UChar*)p) - (Long)5; |
| 3354 | |
| 3355 | /* And make the modifications. */ |
| 3356 | p[0] = 0xE9; |
| 3357 | p[1] = (delta >> 0) & 0xFF; |
| 3358 | p[2] = (delta >> 8) & 0xFF; |
| 3359 | p[3] = (delta >> 16) & 0xFF; |
| 3360 | p[4] = (delta >> 24) & 0xFF; |
| 3361 | p[5] = 0x0F; p[6] = 0x0B; |
| 3362 | /* sanity check on the delta -- top 32 are all 0 or all 1 */ |
| 3363 | delta >>= 32; |
| 3364 | vassert(delta == 0LL || delta == -1LL); |
florian | 5ea257b | 2012-09-29 17:05:46 +0000 | [diff] [blame] | 3365 | VexInvalRange vir = { (HWord)place_to_chain, 7 }; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3366 | return vir; |
| 3367 | } |
| 3368 | |
| 3369 | |
| 3370 | /* NB: what goes on here has to be very closely coordinated with the |
| 3371 | emitInstr case for XDirect, above. */ |
| 3372 | VexInvalRange unchainXDirect_X86 ( void* place_to_unchain, |
| 3373 | void* place_to_jump_to_EXPECTED, |
| 3374 | void* disp_cp_chain_me ) |
| 3375 | { |
| 3376 | /* What we're expecting to see is: |
| 3377 | jmp d32 |
| 3378 | ud2; |
| 3379 | viz |
| 3380 | E9 <4 bytes == disp32> |
| 3381 | 0F 0B |
| 3382 | */ |
| 3383 | UChar* p = (UChar*)place_to_unchain; |
| 3384 | Bool valid = False; |
| 3385 | if (p[0] == 0xE9 |
| 3386 | && p[5] == 0x0F && p[6] == 0x0B) { |
| 3387 | /* Check the offset is right. */ |
| 3388 | Int s32 = *(Int*)(&p[1]); |
| 3389 | if ((UChar*)p + 5 + s32 == (UChar*)place_to_jump_to_EXPECTED) { |
| 3390 | valid = True; |
| 3391 | if (0) |
| 3392 | vex_printf("QQQ unchainXDirect_X86: found valid\n"); |
| 3393 | } |
| 3394 | } |
| 3395 | vassert(valid); |
| 3396 | /* And what we want to change it to is: |
| 3397 | movl $disp_cp_chain_me, %edx |
| 3398 | call *%edx |
| 3399 | viz |
| 3400 | BA <4 bytes value == disp_cp_chain_me_EXPECTED> |
| 3401 | FF D2 |
| 3402 | So it's the same length (convenient, huh). |
| 3403 | */ |
| 3404 | p[0] = 0xBA; |
| 3405 | *(UInt*)(&p[1]) = (UInt)Ptr_to_ULong(disp_cp_chain_me); |
| 3406 | p[5] = 0xFF; |
| 3407 | p[6] = 0xD2; |
florian | 5ea257b | 2012-09-29 17:05:46 +0000 | [diff] [blame] | 3408 | VexInvalRange vir = { (HWord)place_to_unchain, 7 }; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3409 | return vir; |
| 3410 | } |
| 3411 | |
| 3412 | |
| 3413 | /* Patch the counter address into a profile inc point, as previously |
| 3414 | created by the Xin_ProfInc case for emit_X86Instr. */ |
| 3415 | VexInvalRange patchProfInc_X86 ( void* place_to_patch, |
| 3416 | ULong* location_of_counter ) |
| 3417 | { |
| 3418 | vassert(sizeof(ULong*) == 4); |
| 3419 | UChar* p = (UChar*)place_to_patch; |
| 3420 | vassert(p[0] == 0x83); |
| 3421 | vassert(p[1] == 0x05); |
| 3422 | vassert(p[2] == 0x00); |
| 3423 | vassert(p[3] == 0x00); |
| 3424 | vassert(p[4] == 0x00); |
| 3425 | vassert(p[5] == 0x00); |
| 3426 | vassert(p[6] == 0x01); |
| 3427 | vassert(p[7] == 0x83); |
| 3428 | vassert(p[8] == 0x15); |
| 3429 | vassert(p[9] == 0x00); |
| 3430 | vassert(p[10] == 0x00); |
| 3431 | vassert(p[11] == 0x00); |
| 3432 | vassert(p[12] == 0x00); |
| 3433 | vassert(p[13] == 0x00); |
| 3434 | UInt imm32 = (UInt)Ptr_to_ULong(location_of_counter); |
| 3435 | p[2] = imm32 & 0xFF; imm32 >>= 8; |
| 3436 | p[3] = imm32 & 0xFF; imm32 >>= 8; |
| 3437 | p[4] = imm32 & 0xFF; imm32 >>= 8; |
| 3438 | p[5] = imm32 & 0xFF; imm32 >>= 8; |
| 3439 | imm32 = 4 + (UInt)Ptr_to_ULong(location_of_counter); |
| 3440 | p[9] = imm32 & 0xFF; imm32 >>= 8; |
| 3441 | p[10] = imm32 & 0xFF; imm32 >>= 8; |
| 3442 | p[11] = imm32 & 0xFF; imm32 >>= 8; |
| 3443 | p[12] = imm32 & 0xFF; imm32 >>= 8; |
florian | 5ea257b | 2012-09-29 17:05:46 +0000 | [diff] [blame] | 3444 | VexInvalRange vir = { (HWord)place_to_patch, 14 }; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3445 | return vir; |
| 3446 | } |
| 3447 | |
| 3448 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 3449 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 3450 | /*--- end host_x86_defs.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 3451 | /*---------------------------------------------------------------*/ |