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gerrit-public.fairphone.software / platform / external / valgrind / ad00ea9f40f930d98bb2d278291a6c4c6636d6d6 / priv / ir_defs.c
  1. 0b70efa Constification part 1. by florian · 10 years ago
  2. e74ce2e Couple of fixes: by florian · 10 years ago
  3. e6b9bd9 Rename Iop_Extract{64,V128} to Iop_Slice{64,V128}, improve their by sewardj · 10 years ago
  4. 1ddee21 Rename IROps for reciprocal estimate, reciprocal step, reciprocal sqrt by sewardj · 10 years ago
  5. f7003bc arm64: implement: suqadd, usqadd (scalar) suqadd, usqadd (vector) by sewardj · 10 years ago
  6. a6b61f0 arm64: implement by sewardj · 10 years ago
  7. 1dd3ec1 Rename Iop_QSalN*, Iop_QShlN* and Iop_QShlN*S so as to more accurately by sewardj · 10 years ago
  8. ecedd98 arm64: implement: by sewardj · 10 years ago
  9. 1297218 arm64: add support for: sqshl, uqshl, sqrshl, uqrshl (reg) (vector and scalar) by sewardj · 10 years ago
  10. 51d012a arm64: implement: sqneg, {u,s}q{add,sub} (scalar), by sewardj · 10 years ago
  11. a5a6b75 arm64: implement: sadalp uadalp saddlp uaddlp saddlv uaddlv saddw{2} by sewardj · 10 years ago
  12. 715d162 arm64: implement: rbit 16b,8b, rev16 16b,8b by sewardj · 10 years ago
  13. 3368035 Rename the vector subparts-of-lanes-reversal IROps to names by sewardj · 10 years ago
  14. a8c7b0f The vector versions of the count leading zeros/sign bits primops by sewardj · 10 years ago
  15. 25523c4 arm64: implement: abs d_d, neg d_d, abs std7_std7, addhn, subhn, raddhn, rsubhn by sewardj · 10 years ago
  16. 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
  17. 6590299 ARM64: add support for cache management instructions (VEX side): by sewardj · 10 years ago
  18. 7d00913 First pass at implementation of load/store exclusive and by sewardj · 10 years ago
  19. 0e006f2 mips32: VEX Support for 64bit FPU on MIPS32 platforms. by dejanj · 10 years ago
  20. fab0914 Implement more aarch64 vector insns: by sewardj · 10 years ago
  21. ecde697 Implement a few more vector aarch64 insns: by sewardj · 10 years ago
  22. 606c4ba Improve front and back end support for SIMD instructions on Arm64. by sewardj · 10 years ago
  23. 9571dc0 Make the following primops take a third (initial) argument to by sewardj · 10 years ago
  24. 89ae847 Update copyright dates (20XY-2012 ==> 20XY-2013) by sewardj · 11 years ago
  25. 60c6bac This commit adds support for the following instructions: by carll · 11 years ago
  26. 7deaf95 Power 8 support, phase 5 by carll · 11 years ago
  27. 48ae46b Phase 3 support for IBM Power ISA 2.07 by carll · 11 years ago
  28. 9041956 Eliminate IRExprP__VECRET and IRExprP__BBPTR and introduce two new by florian · 11 years ago
  29. 0c74bb5 Initial ISA 2.07 support for POWER8-tuned libc by carll · 11 years ago
  30. 74142b8 Add infrastructural support (IR, VEX) to allow returns of 128- by sewardj · 11 years ago
  31. b22838d Add some more IRops to convert between binary floating point and by florian · 11 years ago
  32. 37c57f3 Add the following IROPs which are needed for s390 DFP support: by florian · 11 years ago
  33. cc3d219 AMD64: Add support for AVX2, BMI1, BMI2 and FMA instructions (VEX side). by sewardj · 11 years ago
  34. 99dd03e Infrastructure cleanup part 2. by florian · 11 years ago
  35. 009230b Infrastructure cleanup: change type of the condition field of by sewardj · 11 years ago
  36. cea07cc Fix implementation of the DFP integer operands. by carll · 12 years ago
  37. cfe046e Merge, from branches/COMEM, revisions 2568 to 2641. by sewardj · 12 years ago
  38. b17e16f Add 12 IROps for converting betwen DFP values and signed/unsigned integers. by florian · 12 years ago
  39. 4bbd3ec New IROps: Iop_ExtractSigD64 and Iop_ExtractSigD128. These are needed to by florian · 12 years ago
  40. 20c6bca s390x: Support "compare biased exponent" insns CEDTR, CEXTR. by florian · 12 years ago
  41. 6dd9f27 Fix typeOfPrimop for Iop_D32toD64 and Iop_D64toD32. by florian · 12 years ago
  42. 78a2059 Implement 128-bit PMOVMSKB using a single new primop (Iop_GetMSBs8x16) by sewardj · 12 years ago
  43. e13074c Improve accuracy of definedness tracking through the x86 PMOVMSKB and by sewardj · 12 years ago
  44. 1ff4756 Constify VEX's external interface. by florian · 12 years ago
  45. a6a1986 Add a proper support for several MIPS instructions that generate SigFPE. by petarj · 12 years ago
  46. 1c8f7ff s390: Add support for the "convert from/to logical" instruction family. by florian · 12 years ago
  47. 6d52228 Remove unused IRops Iop_SqrtF64r32 and Iop_CalcFPRF. by florian · 12 years ago
  48. 19aff3b Remove unused IR ops: Iop_I16StoF64, Iop_F32toI16S, and Iop_I16StoF32. by florian · 12 years ago
  49. a60e843 Fix a mixup. This never caused a problem because both fields have by florian · 12 years ago
  50. 25e5473 Update copyright dates to include 2012. by sewardj · 12 years ago
  51. 5df0b2f eqIRConst: handle Ico_V256. by sewardj · 12 years ago
  52. 44ce46d ARM: Implement QADD and QSUB. Fixes #286917. by sewardj · 12 years ago
  53. f5dfa3b Comment/formatting only change, to clarify semantics w.r.t. by sewardj · 12 years ago
  54. 44ab8f7 Make the IR sanity checker complain about dirty helpers that return by florian · 12 years ago
  55. 37a505b Add a new IRConst kind -- V256 -- containing an abbreviated vector by sewardj · 12 years ago
  56. 23db8a0 Add IR ops Iop_CmpNEZ32x8 and Iop_CmpNEZ64x4, needed for Memcheck by sewardj · 12 years ago
  57. 8209692 More AVX insns: by sewardj · 12 years ago
  58. 8eb7ae8 by sewardj · 12 years ago
  59. d8bca7e Implement by sewardj · 12 years ago
  60. 66becf3 More AVX insns: by sewardj · 12 years ago
  61. 2a2bda9 Fill in some missing AVX insns: by sewardj · 12 years ago
  62. 4b1cc83 Implement even more instructions generated by "gcc-4.7.0 -mavx -O3". by sewardj · 12 years ago
  63. 56c3031 Make a start at implementing 256-bit AVX instructions generated by by sewardj · 12 years ago
  64. 4c96e61 POWER Processor decimal FP support, part 5 (VEX side). Bug #299694. by sewardj · 12 years ago
  65. 420bfa9 Put the Triop member into a separate struct (IRTriop) and link to that by florian · 12 years ago
  66. 96d7cc3 Put the Qop member into a separate struct (IRQop) and link to that by florian · 12 years ago
  67. c9069f2 Enhance the guest state effects notation on IRDirty calls, so as to be by sewardj · 12 years ago
  68. d6f38b3 Reduce size of an IRStmt from 40 bytes to 32 bytes on LP64 by florian · 12 years ago
  69. c4530ae Add initial support for Intel AVX instructions (VEX side). by sewardj · 12 years ago
  70. 5eff1c5 Add support for POWER Power Decimal Floating Point (DFP) test class, by sewardj · 12 years ago
  71. cdc376d POWER Processor decimal floating point instruction support, part 3 by sewardj · 12 years ago
  72. db01409 Merge branches/TCHAIN from r2271 (its creation point) into trunk. by sewardj · 12 years ago
  73. 26217b0 by sewardj · 12 years ago
  74. c6f970f Add translation chaining support for amd64, x86 and ARM (VEX side). See #296422. by sewardj · 12 years ago
  75. c6bbd47 Initial support for POWER Processor decimal floating point instruction by sewardj · 12 years ago
  76. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  77. ad2c9ea VEX side fixes to match r12190, which is a fix for #279698 (incorrect by sewardj · 13 years ago
  78. d881562 Implement the SSE4.1 insn PCMPEQQ. n-i-bz. (VEX side changes) by sewardj · 13 years ago
  79. 6d615ba Support ARM and Thumb "CLREX" instructions since Dalvik generates by sewardj · 13 years ago
  80. e71e56a Add support for IBM Power ISA 2.06 -- stage 3. by sewardj · 13 years ago
  81. 4aa412a Add support for IBM Power ISA 2.06 -- stage 2. Bug 276784. by sewardj · 13 years ago
  82. ff7f5b7 Complete the implementation of ARM atomic ops: {LD,ST}REX{,B,H,D} in by sewardj · 13 years ago
  83. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  84. 718305c Unbreak Altivec support following r2159 (rename of saturating narrowing primops) by sewardj · 13 years ago
  85. 2260b99 Implement PACKUSDW (SSE4.1). Fixes #274776. by sewardj · 13 years ago
  86. c9bff7d Partially fix underspecification of saturating narrowing primops that by sewardj · 13 years ago
  87. 2f10aa6 Add a field 'UChar delta' to IRStmt_IMark, and use it to carry around by sewardj · 13 years ago
  88. 95d6f3a Fix up incorrect usage of Iop_I64UtoF32 in the PowerPC front and back by sewardj · 13 years ago
  89. 66d5ef2 Add support for IBM Power ISA 2.06 -- stage 1. Bug #267630 and by sewardj · 13 years ago
  90. 2019a97 Add a port to IBM z/Architecture (s390x) running Linux -- VEX by sewardj · 13 years ago
  91. 310d6b2 Add support for SMSAD{X}, SMLSD{X}, USAD{A}8. by sewardj · 14 years ago
  92. 7666c15 Handle Ity_I128 in sizeofIRType. (Florian Krohm, britzel@acm.org). by sewardj · 14 years ago
  93. e2ea176 by sewardj · 14 years ago
  94. 2fdd416 Merge from branches/THUMB: new IR primops and associated by sewardj · 14 years ago
  95. d15b597 Implement ROUNDSS (partial implementation, in the case where by sewardj · 14 years ago
  96. 69d98e3 Implement SSE4 instructions: PCMPGTQ PMAXUD PMINUD PMAXSB PMINSB PMULLD by sewardj · 14 years ago
  97. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  98. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  99. e768e92 by sewardj · 15 years ago
  100. 05a2c38 deepCopyIRCAS: handle NULL dataHi and expdHi without segfaulting. by sewardj · 15 years ago